[llvm-branch-commits] [llvm-branch] r164511 - in /llvm/branches/R600/lib/Target/Mips: MipsISelLowering.cpp MipsISelLowering.h
Tom Stellard
thomas.stellard at amd.com
Mon Sep 24 08:53:37 PDT 2012
Author: tstellar
Date: Mon Sep 24 10:51:59 2012
New Revision: 164511
URL: http://llvm.org/viewvc/llvm-project?rev=164511&view=rev
Log:
Add MIPS DSP register classes. Set actions of DSP vector operations and override
TargetLowering's callback functions.
Modified:
llvm/branches/R600/lib/Target/Mips/MipsISelLowering.cpp
llvm/branches/R600/lib/Target/Mips/MipsISelLowering.h
Modified: llvm/branches/R600/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/Mips/MipsISelLowering.cpp?rev=164511&r1=164510&r2=164511&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/branches/R600/lib/Target/Mips/MipsISelLowering.cpp Mon Sep 24 10:51:59 2012
@@ -129,6 +129,22 @@
addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
}
+ if (Subtarget->hasDSP()) {
+ MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
+
+ for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
+ addRegisterClass(VecTys[i], &Mips::DSPRegsRegClass);
+
+ // Expand all builtin opcodes.
+ for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
+ setOperationAction(Opc, VecTys[i], Expand);
+
+ setOperationAction(ISD::LOAD, VecTys[i], Legal);
+ setOperationAction(ISD::STORE, VecTys[i], Legal);
+ setOperationAction(ISD::BITCAST, VecTys[i], Legal);
+ }
+ }
+
if (!TM.Options.UseSoftFloat) {
addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
@@ -269,6 +285,9 @@
setOperationAction(ISD::VACOPY, MVT::Other, Expand);
setOperationAction(ISD::VAEND, MVT::Other, Expand);
+ setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
+ setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
+
// Use the default for now
setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
@@ -803,6 +822,26 @@
return SDValue();
}
+void
+MipsTargetLowering::LowerOperationWrapper(SDNode *N,
+ SmallVectorImpl<SDValue> &Results,
+ SelectionDAG &DAG) const {
+ SDValue Res = LowerOperation(SDValue(N, 0), DAG);
+
+ for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
+ Results.push_back(Res.getValue(I));
+}
+
+void
+MipsTargetLowering::ReplaceNodeResults(SDNode *N,
+ SmallVectorImpl<SDValue> &Results,
+ SelectionDAG &DAG) const {
+ SDValue Res = LowerOperation(SDValue(N, 0), DAG);
+
+ for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
+ Results.push_back(Res.getValue(I));
+}
+
SDValue MipsTargetLowering::
LowerOperation(SDValue Op, SelectionDAG &DAG) const
{
Modified: llvm/branches/R600/lib/Target/Mips/MipsISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/Mips/MipsISelLowering.h?rev=164511&r1=164510&r2=164511&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/Mips/MipsISelLowering.h (original)
+++ llvm/branches/R600/lib/Target/Mips/MipsISelLowering.h Mon Sep 24 10:51:59 2012
@@ -146,9 +146,19 @@
virtual bool allowsUnalignedMemoryAccesses (EVT VT) const;
+ virtual void LowerOperationWrapper(SDNode *N,
+ SmallVectorImpl<SDValue> &Results,
+ SelectionDAG &DAG) const;
+
/// LowerOperation - Provide custom lowering hooks for some operations.
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
+ /// ReplaceNodeResults - Replace the results of node with an illegal result
+ /// type with new values built out of custom code.
+ ///
+ virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
+ SelectionDAG &DAG) const;
+
/// getTargetNodeName - This method returns the name of a target specific
// DAG node.
virtual const char *getTargetNodeName(unsigned Opcode) const;
More information about the llvm-branch-commits
mailing list