[llvm-branch-commits] [llvm-branch] r164509 - in /llvm/branches/R600/lib/Target/Mips: MipsRegisterInfo.cpp MipsRegisterInfo.td

[Tom Stellard]

Author: tstellar
Date: Mon Sep 24 10:51:55 2012
New Revision: 164509

URL: http://llvm.org/viewvc/llvm-project?rev=164509&view=rev
Log:
Add MIPS accumulator and DSP control registers.

Modified:
    llvm/branches/R600/lib/Target/Mips/MipsRegisterInfo.cpp
    llvm/branches/R600/lib/Target/Mips/MipsRegisterInfo.td

Modified: llvm/branches/R600/lib/Target/Mips/MipsRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/Mips/MipsRegisterInfo.cpp?rev=164509&r1=164508&r2=164509&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/Mips/MipsRegisterInfo.cpp (original)
+++ llvm/branches/R600/lib/Target/Mips/MipsRegisterInfo.cpp Mon Sep 24 10:51:55 2012
@@ -123,6 +123,9 @@
   Reserved.set(Mips::HWR29);
   Reserved.set(Mips::HWR29_64);
 
+  // Reserve DSP control register.
+  Reserved.set(Mips::DSPCtrl);
+
   // Reserve RA if in mips16 mode.
   if (Subtarget.inMips16Mode()) {
     Reserved.set(Mips::RA);

Modified: llvm/branches/R600/lib/Target/Mips/MipsRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/Mips/MipsRegisterInfo.td?rev=164509&r1=164508&r2=164509&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/Mips/MipsRegisterInfo.td (original)
+++ llvm/branches/R600/lib/Target/Mips/MipsRegisterInfo.td Mon Sep 24 10:51:55 2012
@@ -245,13 +245,45 @@
   // Hardware register $29
   def HWR29 : Register<"29">;
   def HWR29_64 : Register<"29">;
+
+  // Accum registers
+  def LO0 : Register<"ac0"> {
+    let Aliases = [LO];
+  }
+  def HI0 : Register<"hi0"> {
+    let Aliases = [HI];
+  }
+  def LO1 : Register<"ac1">;
+  def HI1 : Register<"hi1">;
+  def LO2 : Register<"ac2">;
+  def HI2 : Register<"hi2">;
+  def LO3 : Register<"ac3">;
+  def HI3 : Register<"hi3">;
+
+  let SubRegIndices = [sub_32] in {
+    def LO0_64 : RegisterWithSubRegs<"ac0", [LO0]> {
+      let Aliases = [LO64];
+    }
+    def HI0_64 : RegisterWithSubRegs<"hi0", [HI0]> {
+      let Aliases = [HI64];
+    }
+    def LO1_64 : RegisterWithSubRegs<"ac1", [LO1]>;
+    def HI1_64 : RegisterWithSubRegs<"hi1", [HI1]>;
+    def LO2_64 : RegisterWithSubRegs<"ac2", [LO2]>;
+    def HI2_64 : RegisterWithSubRegs<"hi2", [HI2]>;
+    def LO3_64 : RegisterWithSubRegs<"ac3", [LO3]>;
+    def HI3_64 : RegisterWithSubRegs<"hi3", [HI3]>;
+  }
+
+  def DSPCtrl : Register<"dspctrl">;
 }
 
 //===----------------------------------------------------------------------===//
 // Register Classes
 //===----------------------------------------------------------------------===//
 
-def CPURegs : RegisterClass<"Mips", [i32], 32, (add
+class CPURegsClass<list<ValueType> regTypes> :
+  RegisterClass<"Mips", regTypes, 32, (add
   // Reserved
   ZERO, AT,
   // Return Values and Arguments
@@ -265,6 +297,9 @@
   // Reserved
   K0, K1, GP, SP, FP, RA)>;
 
+def CPURegs : CPURegsClass<[i32]>;
+def DSPRegs : CPURegsClass<[v4i8, v2i16]>;
+
 def CPU64Regs : RegisterClass<"Mips", [i64], 64, (add
 // Reserved
   ZERO_64, AT_64,
@@ -322,3 +357,9 @@
 def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>;
 def HWRegs64 : RegisterClass<"Mips", [i64], 32, (add HWR29_64)>;
 
+// Accum Registers
+def HIRegs : RegisterClass<"Mips", [i32], 32, (sequence "HI%u", 0, 3)>;
+def LORegs : RegisterClass<"Mips", [i32], 32, (sequence "LO%u", 0, 3)>;
+
+def HI64Regs : RegisterClass<"Mips", [i64], 64, (sequence "HI%u_64", 0, 3)>;
+def LO64Regs : RegisterClass<"Mips", [i64], 64, (sequence "LO%u_64", 0, 3)>;