[llvm-branch-commits] [llvm-branch] r163727 [2/2] - in /llvm/branches/AMDILBackend: include/llvm/CodeGen/ lib/Target/AMDIL/ lib/Target/AMDIL/TargetInfo/
Victor Oliveira
Victor.Oliveira at amd.com
Wed Sep 12 10:43:35 PDT 2012
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILMem32.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILMem32.td?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILMem32.td (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILMem32.td Wed Sep 12 12:43:34 2012
@@ -19,818 +19,572 @@
//===----------------------------------------------------------------------===//
// Store Memory Operations
//===----------------------------------------------------------------------===//
- defm GLOBALTRUNCSTORE : GTRUNCSTORE<"!global trunc store">;
- defm GLOBALSTORE : STORE<"!global store" , global_store>;
- defm LOCALTRUNCSTORE : LTRUNCSTORE<"!local trunc store">;
- defm LOCALSTORE : STORE<"!local store" , local_store>;
- defm PRIVATETRUNCSTORE : PTRUNCSTORE<"!private trunc store">;
- defm PRIVATESTORE : STORE<"!private store" , private_store>;
- defm REGIONTRUNCSTORE : RTRUNCSTORE<"!region trunc store">;
- defm REGIONSTORE : STORE<"!region hw store" , region_store>;
+ defm GLOBALTRUNCSTORE : GTRUNCSTORE<"!global trunc store", MEM3232, ADDR>;
+ let global = 1 in {
+ defm GLOBALSTORE : STORE<"!global store" , global_store, MEM3232, ADDR>;
+ }
+ defm LOCALTRUNCSTORE : LTRUNCSTORE<"!local trunc store", MEM3232, ADDR>;
+ let local = 1 in {
+ defm LOCALSTORE : STORE<"!local store" , local_store, MEM3232, ADDR>;
+ }
+ defm PRIVATETRUNCSTORE : PTRUNCSTORE<"!private trunc store", MEM3232, ADDR>;
+ let private = 1 in {
+ defm PRIVATESTORE : STORE<"!private store" , private_store, MEM3232, ADDR>;
+ }
+ defm REGIONTRUNCSTORE : RTRUNCSTORE<"!region trunc store", MEM3232, ADDR>;
+ let region = 1 in {
+ defm REGIONSTORE : STORE<"!region hw store" , region_store, MEM3232, ADDR>;
+ }
//===---------------------------------------------------------------------===//
// Load Memory Operations
//===---------------------------------------------------------------------===//
- defm GLOBALLOAD : LOAD<"!global load" , global_load>;
- defm GLOBALZEXTLOAD : LOAD<"!global zext load" , global_zext_load>;
- defm GLOBALSEXTLOAD : LOAD<"!global sext load" , global_sext_load>;
- defm GLOBALAEXTLOAD : LOAD<"!global aext load" , global_aext_load>;
- defm PRIVATELOAD : LOAD<"!private load" , private_load>;
- defm PRIVATEZEXTLOAD : LOAD<"!private zext load" , private_zext_load>;
- defm PRIVATESEXTLOAD : LOAD<"!private sext load" , private_sext_load>;
- defm PRIVATEAEXTLOAD : LOAD<"!private aext load" , private_aext_load>;
- defm CPOOLLOAD : LOAD<"!constant pool load" , cp_load>;
- defm CPOOLZEXTLOAD : LOAD<"!constant pool zext load", cp_zext_load>;
- defm CPOOLSEXTLOAD : LOAD<"!constant pool sext load", cp_sext_load>;
- defm CPOOLAEXTLOAD : LOAD<"!constant aext pool load", cp_aext_load>;
- defm CONSTANTLOAD : LOAD<"!constant load" , constant_load>;
- defm CONSTANTZEXTLOAD : LOAD<"!constant zext load" , constant_zext_load>;
- defm CONSTANTSEXTLOAD : LOAD<"!constant sext load" , constant_sext_load>;
- defm CONSTANTAEXTLOAD : LOAD<"!constant aext load" , constant_aext_load>;
- defm LOCALLOAD : LOAD<"!local load" , local_load>;
- defm LOCALZEXTLOAD : LOAD<"!local zext load" , local_zext_load>;
- defm LOCALSEXTLOAD : LOAD<"!local sext load" , local_sext_load>;
- defm LOCALAEXTLOAD : LOAD<"!local aext load" , local_aext_load>;
- defm REGIONLOAD : LOAD<"!region load" , region_load>;
- defm REGIONZEXTLOAD : LOAD<"!region zext load" , region_zext_load>;
- defm REGIONSEXTLOAD : LOAD<"!region sext load" , region_sext_load>;
- defm REGIONAEXTLOAD : LOAD<"!region aext load" , region_aext_load>;
+ let global = 1 in {
+ defm GLOBALLOAD : LOAD<"!global load" , global_load, MEM3232, ADDR>;
+ let extLoadType = 2 in {
+ defm GLOBALZEXTLOAD : LOAD<"!global zext load" , global_zext_load, MEM3232, ADDR>;
+ }
+ let extLoadType = 1 in {
+ defm GLOBALSEXTLOAD : LOAD<"!global sext load" , global_sext_load, MEM3232, ADDR>;
+ }
+ let extLoadType = 3 in {
+ defm GLOBALAEXTLOAD : LOAD<"!global aext load" , global_aext_load, MEM3232, ADDR>;
+ }
+ }
+ let private = 1 in {
+ defm PRIVATELOAD : LOAD<"!private load" , private_load, MEM3232, ADDR>;
+ let extLoadType = 2 in {
+ defm PRIVATEZEXTLOAD : LOAD<"!private zext load" , private_zext_load, MEM3232, ADDR>;
+ }
+ let extLoadType = 1 in {
+ defm PRIVATESEXTLOAD : LOAD<"!private sext load" , private_sext_load, MEM3232, ADDR>;
+ }
+ let extLoadType = 3 in {
+ defm PRIVATEAEXTLOAD : LOAD<"!private aext load" , private_aext_load, MEM3232, ADDR>;
+ }
+ }
+ let cpool = 1 in {
+ defm CPOOLLOAD : LOAD<"!constant pool load" , cp_load, MEM3232, ADDR>;
+ let extLoadType = 2 in {
+ defm CPOOLZEXTLOAD : LOAD<"!constant pool zext load", cp_zext_load, MEM3232, ADDR>;
+ }
+ let extLoadType = 1 in {
+ defm CPOOLSEXTLOAD : LOAD<"!constant pool sext load", cp_sext_load, MEM3232, ADDR>;
+ }
+ let extLoadType = 3 in {
+ defm CPOOLAEXTLOAD : LOAD<"!constant aext pool load", cp_aext_load, MEM3232, ADDR>;
+ }
+ }
+ let constant = 1 in {
+ defm CONSTANTLOAD : LOAD<"!constant load" , constant_load, MEM3232, ADDR>;
+ let extLoadType = 2 in {
+ defm CONSTANTZEXTLOAD : LOAD<"!constant zext load" , constant_zext_load, MEM3232, ADDR>;
+ }
+ let extLoadType = 1 in {
+ defm CONSTANTSEXTLOAD : LOAD<"!constant sext load" , constant_sext_load, MEM3232, ADDR>;
+ }
+ let extLoadType = 3 in {
+ defm CONSTANTAEXTLOAD : LOAD<"!constant aext load" , constant_aext_load, MEM3232, ADDR>;
+ }
+ }
+ let local = 1 in {
+ defm LOCALLOAD : LOAD<"!local load" , local_load, MEM3232, ADDR>;
+ let extLoadType = 2 in {
+ defm LOCALZEXTLOAD : LOAD<"!local zext load" , local_zext_load, MEM3232, ADDR>;
+ }
+ let extLoadType = 1 in {
+ defm LOCALSEXTLOAD : LOAD<"!local sext load" , local_sext_load, MEM3232, ADDR>;
+ }
+ let extLoadType = 3 in {
+ defm LOCALAEXTLOAD : LOAD<"!local aext load" , local_aext_load, MEM3232, ADDR>;
+ }
+ let region = 1 in {
+ defm REGIONLOAD : LOAD<"!region load" , region_load, MEM3232, ADDR>;
+ let extLoadType = 2 in {
+ defm REGIONZEXTLOAD : LOAD<"!region zext load" , region_zext_load, MEM3232, ADDR>;
+ }
+ let extLoadType = 1 in {
+ defm REGIONSEXTLOAD : LOAD<"!region sext load" , region_sext_load, MEM3232, ADDR>;
+ }
+ let extLoadType = 3 in {
+ defm REGIONAEXTLOAD : LOAD<"!region aext load" , region_aext_load, MEM3232, ADDR>;
+ }
+ }
+ }
}
//===---------------------------------------------------------------------===//
// IO Expansion Load/Store Instructions
//===---------------------------------------------------------------------===//
- // These opcode has custom swizzle patterns for some of the arguments.
- let mayLoad = 1 in {
- // Raw UAV Operations
- def UAVRAWLOAD_i32 : TwoInOneOut<IL_OP_RAW_UAV_LOAD, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i32imm:$id),
- !strconcat(IL_OP_RAW_UAV_LOAD.Text, "_id($id) $dst, $addy"), []>;
- def UAVRAWLOAD_v2i32 : TwoInOneOut<IL_OP_RAW_UAV_LOAD, (outs GPRV2I32:$dst),
- (ins GPRXI32:$addy, i32imm:$id),
- !strconcat(IL_OP_RAW_UAV_LOAD.Text, "_id($id) $dst, $addy"), []>;
- def UAVRAWLOAD_v4i32 : TwoInOneOut<IL_OP_RAW_UAV_LOAD, (outs GPRV4I32:$dst),
- (ins GPRXI32:$addy, i32imm:$id),
- !strconcat(IL_OP_RAW_UAV_LOAD.Text, "_id($id) $dst, $addy"), []>;
- def UAVRAWLOADCACHED_i32 : TwoInOneOut<IL_OP_RAW_UAV_LOAD, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i32imm:$id),
- !strconcat(IL_OP_RAW_UAV_LOAD.Text, "_id($id)_cached $dst, $addy"), []>;
- def UAVRAWLOADCACHED_v2i32 : TwoInOneOut<IL_OP_RAW_UAV_LOAD, (outs GPRV2I32:$dst),
- (ins GPRXI32:$addy, i32imm:$id),
- !strconcat(IL_OP_RAW_UAV_LOAD.Text, "_id($id)_cached $dst, $addy"), []>;
- def UAVRAWLOADCACHED_v4i32 : TwoInOneOut<IL_OP_RAW_UAV_LOAD, (outs GPRV4I32:$dst),
- (ins GPRXI32:$addy, i32imm:$id),
- !strconcat(IL_OP_RAW_UAV_LOAD.Text, "_id($id)_cached $dst, $addy"), []>;
- def UAVRAWLOADCACHEDALIGNED_v2i32 : TwoInOneOut<IL_OP_RAW_UAV_LOAD, (outs GPRV2I32:$dst),
- (ins GPRXI32:$addy, i32imm:$id),
- !strconcat(IL_OP_RAW_UAV_LOAD.Text, "_id($id)_cached_aligned $dst, $addy"), []>;
- def UAVRAWLOADCACHEDALIGNED_v4i32 : TwoInOneOut<IL_OP_RAW_UAV_LOAD, (outs GPRV4I32:$dst),
- (ins GPRXI32:$addy, i32imm:$id),
- !strconcat(IL_OP_RAW_UAV_LOAD.Text, "_id($id)_cached_aligned $dst, $addy"), []>;
- let Predicates = [HasByteShortUAV] in {
- def UAVRAWLOAD_i8 : TwoInOneOut<IL_OP_UAV_BYTE_LOAD, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i32imm:$id),
- !strconcat(IL_OP_UAV_BYTE_LOAD.Text, "_id($id) $dst, $addy"), []>;
- def UAVRAWLOAD_u8 : TwoInOneOut<IL_OP_UAV_UBYTE_LOAD, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i32imm:$id),
- !strconcat(IL_OP_UAV_UBYTE_LOAD.Text, "_id($id) $dst, $addy"), []>;
- def UAVRAWLOAD_i16 : TwoInOneOut<IL_OP_UAV_SHORT_LOAD, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i32imm:$id),
- !strconcat(IL_OP_UAV_SHORT_LOAD.Text, "_id($id) $dst, $addy"), []>;
- def UAVRAWLOAD_u16 : TwoInOneOut<IL_OP_UAV_USHORT_LOAD, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i32imm:$id),
- !strconcat(IL_OP_UAV_USHORT_LOAD.Text, "_id($id) $dst, $addy"), []>;
- def UAVRAWLOADCACHED_i8 : TwoInOneOut<IL_OP_UAV_BYTE_LOAD, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i32imm:$id),
- !strconcat(IL_OP_UAV_BYTE_LOAD.Text, "_id($id)_cached $dst, $addy"), []>;
- def UAVRAWLOADCACHED_u8 : TwoInOneOut<IL_OP_UAV_UBYTE_LOAD, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i32imm:$id),
- !strconcat(IL_OP_UAV_UBYTE_LOAD.Text, "_id($id)_cached $dst, $addy"), []>;
- def UAVRAWLOADCACHED_i16 : TwoInOneOut<IL_OP_UAV_SHORT_LOAD, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i32imm:$id),
- !strconcat(IL_OP_UAV_SHORT_LOAD.Text, "_id($id)_cached $dst, $addy"), []>;
- def UAVRAWLOADCACHED_u16 : TwoInOneOut<IL_OP_UAV_USHORT_LOAD, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i32imm:$id),
- !strconcat(IL_OP_UAV_USHORT_LOAD.Text, "_id($id)_cached $dst, $addy"), []>;
- }
- // Arena UAV Operations
- def UAVARENALOAD_i8 : TwoInOneOut<IL_OP_ARENA_UAV_LOAD, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i32imm:$id),
- !strconcat(IL_OP_ARENA_UAV_LOAD.Text, "_id($id)_size(byte) $dst, $addy"), []>;
- def UAVARENALOAD_i16 : TwoInOneOut<IL_OP_ARENA_UAV_LOAD, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i32imm:$id),
- !strconcat(IL_OP_ARENA_UAV_LOAD.Text, "_id($id)_size(short) $dst, $addy"), []>;
- def UAVARENALOAD_i32 : TwoInOneOut<IL_OP_ARENA_UAV_LOAD, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i32imm:$id),
- !strconcat(IL_OP_ARENA_UAV_LOAD.Text, "_id($id)_size(dword) $dst, $addy"), []>;
-
- // Scratch Buffer Operations
- def SCRATCHLOAD : TwoInOneOut<IL_OP_MOV, (outs GPRV4I32:$dst),
- (ins GPRXI32:$addy, i32imm:$id),
- !strconcat(IL_OP_MOV.Text, " $dst, x$id[$addy]"), []>;
-
+ let mayLoad = 1, load = 1, cbmem = 1 in {
// Constant Buffer Operations
- def CBLOAD : TwoInOneOut<IL_OP_MOV, (outs GPRV4I32:$dst),
+ def CB32LOAD : ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
(ins GPRXI32:$addy, i32imm:$id),
!strconcat(IL_OP_MOV.Text, " $dst, cb$id[$addy]"), []>;
-
- // GDS Operations
- def GDSLOAD : TwoInOneOut<IL_OP_GDS_LOAD, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i32imm:$id),
- !strconcat(IL_OP_GDS_LOAD.Text, "_id($id) $dst, $addy"), []>;
- def GDSLOAD_i8 : TwoInOneOut<IL_OP_GDS_LOAD_BYTE, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i32imm:$id),
- !strconcat(IL_OP_GDS_LOAD_BYTE.Text, "_id($id) $dst, $addy"), []>;
- def GDSLOAD_u8 : TwoInOneOut<IL_OP_GDS_LOAD_UBYTE, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i32imm:$id),
- !strconcat(IL_OP_GDS_LOAD_UBYTE.Text, "_id($id) $dst, $addy"), []>;
- def GDSLOAD_i16 : TwoInOneOut<IL_OP_GDS_LOAD_SHORT, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i32imm:$id),
- !strconcat(IL_OP_GDS_LOAD_SHORT.Text, "_id($id) $dst, $addy"), []>;
- def GDSLOAD_u16 : TwoInOneOut<IL_OP_GDS_LOAD_USHORT, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i32imm:$id),
- !strconcat(IL_OP_GDS_LOAD_USHORT.Text, "_id($id) $dst, $addy"), []>;
-
- // LDS Operations
- def LDSLOADVEC : TwoInOneOut<IL_OP_LDS_LOAD_VEC, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i32imm:$id),
- !strconcat(IL_OP_LDS_LOAD_VEC.Text, "_id($id) $dst, $addy, $addy"), []>;
- def LDSLOADVEC_v2i32 : TwoInOneOut<IL_OP_LDS_LOAD_VEC, (outs GPRV2I32:$dst),
- (ins GPRXI32:$addy, i32imm:$id),
- !strconcat(IL_OP_LDS_LOAD_VEC.Text, "_id($id) $dst, $addy, $addy"), []>;
- def LDSLOADVEC_v4i32 : TwoInOneOut<IL_OP_LDS_LOAD_VEC, (outs GPRV4I32:$dst),
- (ins GPRXI32:$addy, i32imm:$id),
- !strconcat(IL_OP_LDS_LOAD_VEC.Text, "_id($id) $dst, $addy, $addy"), []>;
- def LDSLOAD : TwoInOneOut<IL_OP_LDS_LOAD, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i32imm:$id),
- !strconcat(IL_OP_LDS_LOAD.Text, "_id($id) $dst, $addy"), []>;
- def LDSLOAD_i8 : TwoInOneOut<IL_OP_LDS_LOAD_BYTE, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i32imm:$id),
- !strconcat(IL_OP_LDS_LOAD_BYTE.Text, "_id($id) $dst, $addy"), []>;
- def LDSLOAD_u8 : TwoInOneOut<IL_OP_LDS_LOAD_UBYTE, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i32imm:$id),
- !strconcat(IL_OP_LDS_LOAD_UBYTE.Text, "_id($id) $dst, $addy"), []>;
- def LDSLOAD_i16 : TwoInOneOut<IL_OP_LDS_LOAD_SHORT, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i32imm:$id),
- !strconcat(IL_OP_LDS_LOAD_SHORT.Text, "_id($id) $dst, $addy"), []>;
- def LDSLOAD_u16 : TwoInOneOut<IL_OP_LDS_LOAD_USHORT, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i32imm:$id),
- !strconcat(IL_OP_LDS_LOAD_USHORT.Text, "_id($id) $dst, $addy"), []>;
-
}
- // Store Operations
- let mayStore = 1 in {
- // Raw UAV Operations
- def UAVRAWSTORE_i32 : TwoInOneOut<IL_OP_RAW_UAV_STORE, (outs GPRI32:$mem),
- (ins GPRXI32:$addy, GPRI32:$src, i32imm:$id),
- !strconcat(IL_OP_RAW_UAV_STORE.Text, "_id($id) $mem, $addy, $src"), []>;
- def UAVRAWSTORE_v2i32 : TwoInOneOut<IL_OP_RAW_UAV_STORE, (outs GPRV2I32:$mem),
- (ins GPRXI32:$addy, GPRV2I32:$src, i32imm:$id),
- !strconcat(IL_OP_RAW_UAV_STORE.Text, "_id($id) $mem, $addy, $src"), []>;
- def UAVRAWSTORE_v4i32 : TwoInOneOut<IL_OP_RAW_UAV_STORE, (outs GPRV4I32:$mem),
- (ins GPRXI32:$addy, GPRV4I32:$src, i32imm:$id),
- !strconcat(IL_OP_RAW_UAV_STORE.Text, "_id($id) $mem, $addy, $src"), []>;
- let Predicates = [HasByteShortUAV] in {
- def UAVRAWSTORE_i8 : TwoInOneOut<IL_OP_UAV_BYTE_STORE, (outs GPRI32:$mem),
- (ins GPRXI32:$addy, GPRI32:$src, i32imm:$id),
- !strconcat(IL_OP_UAV_BYTE_STORE.Text, "_id($id) $mem, $addy, $src"), []>;
- def UAVRAWSTORE_i16 : TwoInOneOut<IL_OP_UAV_SHORT_STORE, (outs GPRI32:$mem),
- (ins GPRXI32:$addy, GPRI32:$src, i32imm:$id),
- !strconcat(IL_OP_UAV_SHORT_STORE.Text, "_id($id) $mem, $addy, $src"), []>;
-
- }
- // Arena UAV Operations
- def UAVARENASTORE_i8 : TwoInOneOut<IL_OP_ARENA_UAV_STORE, (outs GPRXI32:$addy),
- (ins GPRI8:$src, i32imm:$id),
- !strconcat(IL_OP_ARENA_UAV_STORE.Text,
- "_id($id)_size(byte) $addy, $src"), []>;
- def UAVARENASTORE_i16 : TwoInOneOut<IL_OP_ARENA_UAV_STORE, (outs GPRXI32:$addy),
- (ins GPRI16:$src, i32imm:$id),
- !strconcat(IL_OP_ARENA_UAV_STORE.Text,
- "_id($id)_size(short) $addy, $src"), []>;
- def UAVARENASTORE_i32 : TwoInOneOut<IL_OP_ARENA_UAV_STORE, (outs GPRXI32:$addy),
- (ins GPRI32:$src, i32imm:$id),
- !strconcat(IL_OP_ARENA_UAV_STORE.Text,
- "_id($id)_size(dword) $addy, $src"), []>;
-
- // Scratch Buffer Operations
- def SCRATCHSTORE : TwoInOneOut<IL_OP_MOV, (outs GPRXI32:$addy),
- (ins GPRV4I32:$data, i32imm:$id),
- !strconcat(IL_OP_MOV.Text, " x$id[$addy, $data"), []>;
-
- // GDS Operations
- def GDSSTORE : TwoInOneOut<IL_OP_GDS_STORE, (outs GPRXI32:$addy),
- (ins GPRI32:$src, i32imm:$id),
- !strconcat(IL_OP_GDS_STORE.Text, "_id($id) $addy, $src"), []>;
-
- def GDSSTORE_i8 : TwoInOneOut<IL_OP_GDS_STORE_BYTE, (outs GPRXI32:$addy),
- (ins GPRI32:$src, i32imm:$id),
- !strconcat(IL_OP_GDS_STORE_BYTE.Text, "_id($id) $addy, $src"), []>;
-
- def GDSSTORE_i16 : TwoInOneOut<IL_OP_GDS_STORE_SHORT, (outs GPRXI32:$addy),
- (ins GPRI32:$src, i32imm:$id),
- !strconcat(IL_OP_GDS_STORE_SHORT.Text, "_id($id) $addy, $src"), []>;
-
- // LDS Operations
- def LDSSTOREVEC : ThreeInOneOut<IL_OP_LDS_STORE_VEC, (outs GPRI32:$mem),
- (ins GPRXI32:$addy, GPRI32:$src, i32imm:$id),
- !strconcat(IL_OP_LDS_STORE_VEC.Text, "_id($id) $mem, $addy, $src, $src"), []>;
- def LDSSTOREVEC_v2i32 : ThreeInOneOut<IL_OP_LDS_STORE_VEC, (outs GPRV2I32:$mem),
- (ins GPRXI32:$addy, GPRV2I32:$src, i32imm:$id),
- !strconcat(IL_OP_LDS_STORE_VEC.Text, "_id($id) $mem, $addy, $src, $src"), []>;
-
- def LDSSTOREVEC_v4i32 : ThreeInOneOut<IL_OP_LDS_STORE_VEC, (outs GPRV4I32:$mem),
- (ins GPRXI32:$addy, GPRV4I32:$src, i32imm:$id),
- !strconcat(IL_OP_LDS_STORE_VEC.Text, "_id($id) $mem, $addy, $src, $src"), []>;
-
- def LDSSTORE : TwoInOneOut<IL_OP_LDS_STORE, (outs GPRXI32:$addy),
- (ins GPRI32:$src, i32imm:$id),
- !strconcat(IL_OP_LDS_STORE.Text, "_id($id) $addy, $src"), []>;
-
- def LDSSTORE_i8 : TwoInOneOut<IL_OP_LDS_STORE_BYTE, (outs GPRXI32:$addy),
- (ins GPRI32:$src, i32imm:$id),
- !strconcat(IL_OP_LDS_STORE_BYTE.Text, "_id($id) $addy, $src"), []>;
-
- def LDSSTORE_i16 : TwoInOneOut<IL_OP_LDS_STORE_SHORT, (outs GPRXI32:$addy),
- (ins GPRI32:$src, i32imm:$id),
- !strconcat(IL_OP_LDS_STORE_SHORT.Text, "_id($id) $addy, $src"), []>;
+
+ defm UAVRAW32 : UAVRawLSInst<GPRXI32, "_id($id)">;
+ defm SCRATCH32 : ScratchLSInst<GPRXI32>;
+ defm UAVARENA32 : ArenaLSInst<GPRXI32>;
+ defm GDS32 : GDSLSInst<GPRXI32>;
+ defm LDS32 : LDSLSInst<GPRXI32>;
+
+ let image = 1, txld = 1, load = 1 in {
+ def TXLD321DB : ILFormat<IL_OP_LOAD, (outs GPRV4I32:$dst),
+ (ins MEM3232:$ptr, GPRI32:$addy),
+ !strconcat(IL_OP_LOAD.Text,
+ "_id($ptr) $dst, $addy"),
+ [(set GPRV4I32:$dst,
+ (int_AMDIL_image1d_buffer_load ADDR:$ptr, GPRI32:$addy))]>;
}
- // Image related operations.
- def IMAGE1D_READ : ILFormat<IL_OP_SAMPLE, (outs GPRV4I32:$dst),
- (ins MEM3232:$ptr, GPRI32:$sampler, GPRV4F32:$addy),
- !strconcat(IL_OP_SAMPLE.Text,
- "_id($ptr)_sampler($sampler)_coordtype(normalized) $dst, $addy"),
- [(set GPRV4I32:$dst,
- (int_AMDIL_image1d_read_norm ADDR:$ptr, GPRI32:$sampler, GPRV4F32:$addy))]>;
- def IMAGE1DA_READ : ILFormat<IL_OP_SAMPLE, (outs GPRV4I32:$dst),
- (ins MEM3232:$ptr, GPRI32:$sampler, GPRV4F32:$addy),
- !strconcat(IL_OP_SAMPLE.Text,
- "_id($ptr)_sampler($sampler)_coordtype(normalized) $dst, $addy"),
- [(set GPRV4I32:$dst,
- (int_AMDIL_image1d_array_read_norm ADDR:$ptr, GPRI32:$sampler, GPRV4F32:$addy))]>;
- def IMAGE1DB_READ : ILFormat<IL_OP_SAMPLE, (outs GPRV4I32:$dst),
- (ins MEM3232:$ptr, GPRI32:$sampler, GPRV4F32:$addy),
- !strconcat(IL_OP_SAMPLE.Text,
- "_id($ptr)_sampler($sampler)_coordtype(normalized) $dst, $addy"),
- [(set GPRV4I32:$dst,
- (int_AMDIL_image1d_buffer_read_norm ADDR:$ptr, GPRI32:$sampler, GPRV4F32:$addy))]>;
- def IMAGE1DB_TXLD : ILFormat<IL_OP_LOAD, (outs GPRV4I32:$dst),
- (ins MEM3232:$ptr, GPRI32:$addy),
- !strconcat(IL_OP_LOAD.Text,
- "_id($ptr) $dst, $addy"),
- [(set GPRV4I32:$dst,
- (int_AMDIL_image1d_buffer_load ADDR:$ptr, GPRI32:$addy))]>;
- def IMAGE2D_READ : ILFormat<IL_OP_SAMPLE, (outs GPRV4I32:$dst),
- (ins MEM3232:$ptr, GPRI32:$sampler, GPRV4F32:$addy),
- !strconcat(IL_OP_SAMPLE.Text,
- "_id($ptr)_sampler($sampler)_coordtype(normalized) $dst, $addy"),
- [(set GPRV4I32:$dst,
- (int_AMDIL_image2d_read_norm ADDR:$ptr, GPRI32:$sampler, GPRV4F32:$addy))]>;
- def IMAGE2DA_READ : ILFormat<IL_OP_SAMPLE, (outs GPRV4I32:$dst),
- (ins MEM3232:$ptr, GPRI32:$sampler, GPRV4F32:$addy),
- !strconcat(IL_OP_SAMPLE.Text,
- "_id($ptr)_sampler($sampler)_coordtype(normalized) $dst, $addy"),
- [(set GPRV4I32:$dst,
- (int_AMDIL_image2d_array_read_norm ADDR:$ptr, GPRI32:$sampler, GPRV4F32:$addy))]>;
- def IMAGE3D_READ : ILFormat<IL_OP_SAMPLE, (outs GPRV4I32:$dst),
- (ins MEM3232:$ptr, GPRI32:$sampler, GPRV4F32:$addy),
- !strconcat(IL_OP_SAMPLE.Text,
- "_id($ptr)_sampler($sampler)_coordtype(normalized) $dst, $addy"),
- [(set GPRV4I32:$dst,
- (int_AMDIL_image3d_read_norm ADDR:$ptr, GPRI32:$sampler, GPRV4F32:$addy))]>;
- def IMAGE1D_READ_UNNORM : ILFormat<IL_OP_SAMPLE, (outs GPRV4I32:$dst),
- (ins MEM3232:$ptr, GPRI32:$sampler, GPRV4F32:$addy),
- !strconcat(IL_OP_SAMPLE.Text,
- "_id($ptr)_sampler($sampler)_coordtype(unnormalized) $dst, $addy"),
- [(set GPRV4I32:$dst,
- (int_AMDIL_image1d_read_unnorm ADDR:$ptr, GPRI32:$sampler, GPRV4F32:$addy))]>;
- def IMAGE1DA_READ_UNNORM : ILFormat<IL_OP_SAMPLE, (outs GPRV4I32:$dst),
- (ins MEM3232:$ptr, GPRI32:$sampler, GPRV4F32:$addy),
- !strconcat(IL_OP_SAMPLE.Text,
- "_id($ptr)_sampler($sampler)_coordtype(unnormalized) $dst, $addy"),
- [(set GPRV4I32:$dst,
- (int_AMDIL_image1d_array_read_unnorm ADDR:$ptr, GPRI32:$sampler, GPRV4F32:$addy))]>;
- def IMAGE1DB_READ_UNNORM : ILFormat<IL_OP_SAMPLE, (outs GPRV4I32:$dst),
- (ins MEM3232:$ptr, GPRI32:$sampler, GPRV4F32:$addy),
- !strconcat(IL_OP_SAMPLE.Text,
- "_id($ptr)_sampler($sampler)_coordtype(unnormalized) $dst, $addy"),
- [(set GPRV4I32:$dst,
- (int_AMDIL_image1d_buffer_read_unnorm ADDR:$ptr, GPRI32:$sampler, GPRV4F32:$addy))]>;
- def IMAGE2D_READ_UNNORM : ILFormat<IL_OP_SAMPLE, (outs GPRV4I32:$dst),
- (ins MEM3232:$ptr, GPRI32:$sampler, GPRV4F32:$addy),
- !strconcat(IL_OP_SAMPLE.Text,
- "_id($ptr)_sampler($sampler)_coordtype(unnormalized) $dst, $addy"),
- [(set GPRV4I32:$dst,
- (int_AMDIL_image2d_read_unnorm ADDR:$ptr, GPRI32:$sampler, GPRV4F32:$addy))]>;
- def IMAGE2DA_READ_UNNORM : ILFormat<IL_OP_SAMPLE, (outs GPRV4I32:$dst),
- (ins MEM3232:$ptr, GPRI32:$sampler, GPRV4F32:$addy),
- !strconcat(IL_OP_SAMPLE.Text,
- "_id($ptr)_sampler($sampler)_coordtype(unnormalized) $dst, $addy"),
- [(set GPRV4I32:$dst,
- (int_AMDIL_image2d_array_read_unnorm ADDR:$ptr, GPRI32:$sampler, GPRV4F32:$addy))]>;
- def IMAGE3D_READ_UNNORM : ILFormat<IL_OP_SAMPLE, (outs GPRV4I32:$dst),
- (ins MEM3232:$ptr, GPRI32:$sampler, GPRV4F32:$addy),
- !strconcat(IL_OP_SAMPLE.Text,
- "_id($ptr)_sampler($sampler)_coordtype(unnormalized) $dst, $addy"),
- [(set GPRV4I32:$dst,
- (int_AMDIL_image3d_read_unnorm ADDR:$ptr, GPRI32:$sampler, GPRV4F32:$addy))]>;
- def IMAGE1D_INFO0 : ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
- (ins MEM3232:$ptr),
- !strconcat(IL_OP_MOV.Text, " $dst, $ptr"),
- [(set GPRV4I32:$dst, (int_AMDIL_image1d_info0 ADDR:$ptr))]>;
- def IMAGE1D_INFO1 : ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
- (ins MEM3232:$ptr),
- !strconcat(IL_OP_MOV.Text, " $dst, $ptr"),
- [(set GPRV4I32:$dst, (int_AMDIL_image1d_info1 ADDR:$ptr))]>;
- def IMAGE1DA_INFO0 : ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
- (ins MEM3232:$ptr),
- !strconcat(IL_OP_MOV.Text, " $dst, $ptr"),
- [(set GPRV4I32:$dst, (int_AMDIL_image1d_array_info0 ADDR:$ptr))]>;
- def IMAGE1DA_INFO1 : ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
- (ins MEM3232:$ptr),
- !strconcat(IL_OP_MOV.Text, " $dst, $ptr"),
- [(set GPRV4I32:$dst, (int_AMDIL_image1d_array_info1 ADDR:$ptr))]>;
- def IMAGE1DB_INFO0 : ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
- (ins MEM3232:$ptr),
- !strconcat(IL_OP_MOV.Text, " $dst, $ptr"),
- [(set GPRV4I32:$dst, (int_AMDIL_image1d_buffer_info0 ADDR:$ptr))]>;
- def IMAGE1DB_INFO1 : ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
- (ins MEM3232:$ptr),
- !strconcat(IL_OP_MOV.Text, " $dst, $ptr"),
- [(set GPRV4I32:$dst, (int_AMDIL_image1d_buffer_info1 ADDR:$ptr))]>;
- def IMAGE2D_INFO0 : ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
- (ins MEM3232:$ptr),
- !strconcat(IL_OP_MOV.Text, " $dst, $ptr"),
- [(set GPRV4I32:$dst, (int_AMDIL_image2d_info0 ADDR:$ptr))]>;
- def IMAGE2D_INFO1 : ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
- (ins MEM3232:$ptr),
- !strconcat(IL_OP_MOV.Text, " $dst, $ptr"),
- [(set GPRV4I32:$dst, (int_AMDIL_image2d_info1 ADDR:$ptr))]>;
- def IMAGE2DA_INFO0 : ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
- (ins MEM3232:$ptr),
- !strconcat(IL_OP_MOV.Text, " $dst, $ptr"),
- [(set GPRV4I32:$dst, (int_AMDIL_image2d_array_info0 ADDR:$ptr))]>;
- def IMAGE2DA_INFO1 : ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
- (ins MEM3232:$ptr),
- !strconcat(IL_OP_MOV.Text, " $dst, $ptr"),
- [(set GPRV4I32:$dst, (int_AMDIL_image2d_array_info1 ADDR:$ptr))]>;
- def IMAGE3D_INFO0 : ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
- (ins MEM3232:$ptr),
- !strconcat(IL_OP_MOV.Text, " $dst, $ptr"),
- [(set GPRV4I32:$dst, (int_AMDIL_image3d_info0 ADDR:$ptr))]>;
- def IMAGE3D_INFO1 : ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
- (ins MEM3232:$ptr),
- !strconcat(IL_OP_MOV.Text, " $dst, $ptr"),
- [(set GPRV4I32:$dst, (int_AMDIL_image3d_info1 ADDR:$ptr))]>;
- def IMAGE1D_WRITE : ILFormat<IL_OP_UAV_STORE, (outs),
- (ins MEM3232:$ptr, GPRV2I32:$addy, GPRV4I32:$data),
- !strconcat(IL_OP_UAV_STORE.Text,
- "_id($ptr) $addy, $data"),
- [(int_AMDIL_image1d_write ADDR:$ptr, GPRV2I32:$addy, GPRV4I32:$data)]>;
- def IMAGE1DA_WRITE : ILFormat<IL_OP_UAV_STORE, (outs),
- (ins MEM3232:$ptr, GPRV2I32:$addy, GPRV4I32:$data),
- !strconcat(IL_OP_UAV_STORE.Text,
- "_id($ptr) $addy, $data"),
- [(int_AMDIL_image1d_array_write ADDR:$ptr, GPRV2I32:$addy, GPRV4I32:$data)]>;
- def IMAGE1DB_WRITE : ILFormat<IL_OP_UAV_STORE, (outs),
- (ins MEM3232:$ptr, GPRV2I32:$addy, GPRV4I32:$data),
- !strconcat(IL_OP_UAV_STORE.Text,
- "_id($ptr) $addy, $data"),
- [(int_AMDIL_image1d_buffer_write ADDR:$ptr, GPRV2I32:$addy, GPRV4I32:$data)]>;
- def IMAGE2D_WRITE : ILFormat<IL_OP_UAV_STORE, (outs),
- (ins MEM3232:$ptr, GPRV2I32:$addy, GPRV4I32:$data),
- !strconcat(IL_OP_UAV_STORE.Text,
- "_id($ptr) $addy, $data"),
- [(int_AMDIL_image2d_write ADDR:$ptr, GPRV2I32:$addy, GPRV4I32:$data)]>;
- def IMAGE2DA_WRITE : ILFormat<IL_OP_UAV_STORE, (outs),
- (ins MEM3232:$ptr, GPRV4I32:$addy, GPRV4I32:$data),
- !strconcat(IL_OP_UAV_STORE.Text,
- "_id($ptr) $addy, $data"),
- [(int_AMDIL_image2d_array_write ADDR:$ptr, GPRV4I32:$addy, GPRV4I32:$data)]>;
- def IMAGE3D_WRITE : ILFormat<IL_OP_UAV_STORE, (outs),
- (ins MEM3232:$ptr, GPRV4I32:$addy, GPRV4I32:$data),
- !strconcat(IL_OP_UAV_STORE.Text,
- "_id($ptr) $addy, $data"),
- [(int_AMDIL_image3d_write ADDR:$ptr, GPRV4I32:$addy, GPRV4I32:$data)]>;
+ defm READ32 : IMAGEREAD<MEM3232, ADDR>;
+ defm INFO032 : IMAGEINFO0<MEM3232, ADDR>;
+ defm INFO132 : IMAGEINFO1<MEM3232, ADDR>;
+ defm WRITE32 : IMAGEWRITE<MEM3232, ADDR>;
// Printf related operations.
let isCall=1, isAsCheapAsAMove = 1 in {
- def GET_PRINTF_OFFSET_i32 : ILFormat<IL_OP_MOV, (outs GPRXI32:$dst),
+ def GET_PRINTF_OFFSETi32 : ILFormat<IL_OP_MOV, (outs GPRXI32:$dst),
(ins), !strconcat(IL_OP_MOV.Text, " $dst, cb0[8].y0"),
[(set GPRXI32:$dst, (int_AMDIL_get_printf_offset))]>;
- def GET_PRINTF_SIZE_i32 : ILFormat<IL_OP_MOV, (outs GPRXI32:$dst),
+ def GET_PRINTF_SIZEi32 : ILFormat<IL_OP_MOV, (outs GPRXI32:$dst),
(ins), !strconcat(IL_OP_MOV.Text, " $dst, cb0[8].z0"),
[(set GPRXI32:$dst, (int_AMDIL_get_printf_size))]>;
}
- // Atomic operations
- def ATOM_G_ADD_NORET : BinAtomNoRet<IL_OP_UAV_ADD,
- "_id($id)", atom_g_add_noret>;
- def ATOM_G_AND_NORET : BinAtomNoRet<IL_OP_UAV_AND,
- "_id($id)", atom_g_and_noret>;
- def ATOM_G_MAX_NORET : BinAtomNoRet<IL_OP_UAV_MAX,
- "_id($id)", atom_g_max_noret>;
- def ATOM_G_MIN_NORET : BinAtomNoRet<IL_OP_UAV_MIN,
- "_id($id)", atom_g_min_noret>;
- def ATOM_G_UMAX_NORET : BinAtomNoRet<IL_OP_UAV_UMAX,
- "_id($id)", atom_g_umax_noret>;
- def ATOM_G_UMIN_NORET : BinAtomNoRet<IL_OP_UAV_UMIN,
- "_id($id)", atom_g_umin_noret>;
- def ATOM_G_OR_NORET : BinAtomNoRet<IL_OP_UAV_OR,
- "_id($id)", atom_g_or_noret>;
- def ATOM_G_RSUB_NORET : BinAtomNoRet<IL_OP_UAV_RSUB,
- "_id($id)", atom_g_rsub_noret>;
- def ATOM_G_SUB_NORET : BinAtomNoRet<IL_OP_UAV_SUB,
- "_id($id)", atom_g_sub_noret>;
- def ATOM_G_XOR_NORET : BinAtomNoRet<IL_OP_UAV_XOR,
- "_id($id)", atom_g_xor_noret>;
- def ATOM_G_INC_NORET : BinAtomNoRet<IL_OP_UAV_INC,
- "_id($id)", atom_g_inc_noret>;
- def ATOM_G_DEC_NORET : BinAtomNoRet<IL_OP_UAV_DEC,
- "_id($id)", atom_g_dec_noret>;
- def ATOM_G_CMPXCHG_NORET : CmpXChgNoRet<IL_OP_UAV_CMP,
- "_id($id)", atom_g_cmpxchg_noret>;
- let Predicates = [ArenaSupport] in {
- def ATOM_A_ADD_NORET : BinAtomNoRet<IL_OP_UAV_ADD,
- "_id($id)_arena", atom_g_add_noret>;
- def ATOM_A_AND_NORET : BinAtomNoRet<IL_OP_UAV_AND,
- "_id($id)_arena", atom_g_and_noret>;
- def ATOM_A_MAX_NORET : BinAtomNoRet<IL_OP_UAV_MAX,
- "_id($id)_arena", atom_g_max_noret>;
- def ATOM_A_MIN_NORET : BinAtomNoRet<IL_OP_UAV_MIN,
- "_id($id)_arena", atom_g_min_noret>;
- def ATOM_A_UMAX_NORET : BinAtomNoRet<IL_OP_UAV_UMAX,
- "_id($id)_arena", atom_g_umax_noret>;
- def ATOM_A_UMIN_NORET : BinAtomNoRet<IL_OP_UAV_UMIN,
- "_id($id)_arena", atom_g_umin_noret>;
- def ATOM_A_OR_NORET : BinAtomNoRet<IL_OP_UAV_OR,
- "_id($id)_arena", atom_g_or_noret>;
- def ATOM_A_RSUB_NORET : BinAtomNoRet<IL_OP_UAV_RSUB,
- "_id($id)_arena", atom_g_rsub_noret>;
- def ATOM_A_SUB_NORET : BinAtomNoRet<IL_OP_UAV_SUB,
- "_id($id)_arena", atom_g_sub_noret>;
- def ATOM_A_XOR_NORET : BinAtomNoRet<IL_OP_UAV_XOR,
- "_id($id)_arena", atom_g_xor_noret>;
- def ATOM_A_INC_NORET : BinAtomNoRet<IL_OP_UAV_INC,
- "_id($id)_arena", atom_g_inc_noret>;
- def ATOM_A_DEC_NORET : BinAtomNoRet<IL_OP_UAV_DEC,
- "_id($id)_arena", atom_g_dec_noret>;
- def ATOM_A_CMPXCHG_NORET : CmpXChgNoRet<IL_OP_UAV_CMP,
- "_id($id)_arena", atom_g_cmpxchg_noret>;
+ let atomic = 1 in {
+ let global = 1 in {
+ // Atomic operations
+ def ATOM_G_ADD_NORET : BinAtomNoRet<IL_OP_UAV_ADD,
+ "_id($id)", atom_g_add_noret>;
+ def ATOM_G_AND_NORET : BinAtomNoRet<IL_OP_UAV_AND,
+ "_id($id)", atom_g_and_noret>;
+ def ATOM_G_MAX_NORET : BinAtomNoRet<IL_OP_UAV_MAX,
+ "_id($id)", atom_g_max_noret>;
+ def ATOM_G_MIN_NORET : BinAtomNoRet<IL_OP_UAV_MIN,
+ "_id($id)", atom_g_min_noret>;
+ def ATOM_G_UMAX_NORET : BinAtomNoRet<IL_OP_UAV_UMAX,
+ "_id($id)", atom_g_umax_noret>;
+ def ATOM_G_UMIN_NORET : BinAtomNoRet<IL_OP_UAV_UMIN,
+ "_id($id)", atom_g_umin_noret>;
+ def ATOM_G_OR_NORET : BinAtomNoRet<IL_OP_UAV_OR,
+ "_id($id)", atom_g_or_noret>;
+ def ATOM_G_RSUB_NORET : BinAtomNoRet<IL_OP_UAV_RSUB,
+ "_id($id)", atom_g_rsub_noret>;
+ def ATOM_G_SUB_NORET : BinAtomNoRet<IL_OP_UAV_SUB,
+ "_id($id)", atom_g_sub_noret>;
+ def ATOM_G_XOR_NORET : BinAtomNoRet<IL_OP_UAV_XOR,
+ "_id($id)", atom_g_xor_noret>;
+ def ATOM_G_INC_NORET : BinAtomNoRet<IL_OP_UAV_INC,
+ "_id($id)", atom_g_inc_noret>;
+ def ATOM_G_DEC_NORET : BinAtomNoRet<IL_OP_UAV_DEC,
+ "_id($id)", atom_g_dec_noret>;
+ def ATOM_G_CMPXCHG_NORET : CmpXChgNoRet<IL_OP_UAV_CMP,
+ "_id($id)", atom_g_cmpxchg_noret>;
+ // All of the atomic functions that return
+ def ATOM_G_ADD : BinAtom<IL_OP_UAV_READ_ADD,
+ "_id($id)", atom_g_add>;
+ def ATOM_G_AND : BinAtom<IL_OP_UAV_READ_AND,
+ "_id($id)", atom_g_and>;
+ def ATOM_G_MAX : BinAtom<IL_OP_UAV_READ_MAX,
+ "_id($id)", atom_g_max>;
+ def ATOM_G_MIN : BinAtom<IL_OP_UAV_READ_MIN,
+ "_id($id)", atom_g_min>;
+ def ATOM_G_UMAX : BinAtom<IL_OP_UAV_READ_UMAX,
+ "_id($id)", atom_g_umax>;
+ def ATOM_G_UMIN : BinAtom<IL_OP_UAV_READ_UMIN,
+ "_id($id)", atom_g_umin>;
+ def ATOM_G_OR : BinAtom<IL_OP_UAV_READ_OR,
+ "_id($id)", atom_g_or>;
+ def ATOM_G_RSUB : BinAtom<IL_OP_UAV_READ_RSUB,
+ "_id($id)", atom_g_rsub>;
+ def ATOM_G_SUB : BinAtom<IL_OP_UAV_READ_SUB,
+ "_id($id)", atom_g_sub>;
+ def ATOM_G_XOR : BinAtom<IL_OP_UAV_READ_XOR,
+ "_id($id)", atom_g_xor>;
+ def ATOM_G_INC : BinAtom<IL_OP_UAV_READ_INC,
+ "_id($id)", atom_g_inc>;
+ def ATOM_G_DEC : BinAtom<IL_OP_UAV_READ_DEC,
+ "_id($id)", atom_g_dec>;
+ def ATOM_G_XCHG : BinAtom<IL_OP_UAV_READ_XCHG,
+ "_id($id)", atom_g_xchg>;
+ def ATOM_G_CMPXCHG : CmpXChg<IL_OP_UAV_READ_CMPXCHG,
+ "_id($id)", atom_g_cmpxchg>;
+ def ATOM_G_ADD_NORET_B64 : BinAtomNoRetI64<IL_OP_UAV_ADD,
+ "_b64_id($id)", atom_g_add_noret>;
+ def ATOM_G_AND_NORET_B64 : BinAtomNoRetI64<IL_OP_UAV_AND,
+ "_b64_id($id)", atom_g_and_noret>;
+ def ATOM_G_MAX_NORET_B64 : BinAtomNoRetI64<IL_OP_UAV_MAX,
+ "_b64_id($id)", atom_g_max_noret>;
+ def ATOM_G_MIN_NORET_B64 : BinAtomNoRetI64<IL_OP_UAV_MIN,
+ "_b64_id($id)", atom_g_min_noret>;
+ def ATOM_G_UMAX_NORET_B64 : BinAtomNoRetI64<IL_OP_UAV_UMAX,
+ "_b64_id($id)", atom_g_umax_noret>;
+ def ATOM_G_UMIN_NORET_B64 : BinAtomNoRetI64<IL_OP_UAV_UMIN,
+ "_b64_id($id)", atom_g_umin_noret>;
+ def ATOM_G_OR_NORET_B64 : BinAtomNoRetI64<IL_OP_UAV_OR,
+ "_b64_id($id)", atom_g_or_noret>;
+ def ATOM_G_RSUB_NORET_B64 : BinAtomNoRetI64<IL_OP_UAV_RSUB,
+ "_b64_id($id)", atom_g_rsub_noret>;
+ def ATOM_G_SUB_NORET_B64 : BinAtomNoRetI64<IL_OP_UAV_SUB,
+ "_b64_id($id)", atom_g_sub_noret>;
+ def ATOM_G_XOR_NORET_B64 : BinAtomNoRetI64<IL_OP_UAV_XOR,
+ "_b64_id($id)", atom_g_xor_noret>;
+ def ATOM_G_INC_NORET_B64 : BinAtomNoRetI64<IL_OP_UAV_INC,
+ "_b64_id($id)", atom_g_inc_noret>;
+ def ATOM_G_DEC_NORET_B64 : BinAtomNoRetI64<IL_OP_UAV_DEC,
+ "_b64_id($id)", atom_g_dec_noret>;
+ def ATOM_G_CMPXCHG_NORET_B64 : CmpXChgNoRetI64<IL_OP_UAV_CMP,
+ "_b64_id($id)", atom_g_cmpxchg_noret>;
+ def ATOM_G_ADD_B64 : BinAtomI64<IL_OP_UAV_READ_ADD,
+ "_b64_id($id)", atom_g_add>;
+ def ATOM_G_AND_B64 : BinAtomI64<IL_OP_UAV_READ_AND,
+ "_b64_id($id)", atom_g_and>;
+ def ATOM_G_MAX_B64 : BinAtomI64<IL_OP_UAV_READ_MAX,
+ "_b64_id($id)", atom_g_max>;
+ def ATOM_G_MIN_B64 : BinAtomI64<IL_OP_UAV_READ_MIN,
+ "_b64_id($id)", atom_g_min>;
+ def ATOM_G_UMAX_B64 : BinAtomI64<IL_OP_UAV_READ_UMAX,
+ "_b64_id($id)", atom_g_umax>;
+ def ATOM_G_UMIN_B64 : BinAtomI64<IL_OP_UAV_READ_UMIN,
+ "_b64_id($id)", atom_g_umin>;
+ def ATOM_G_OR_B64 : BinAtomI64<IL_OP_UAV_READ_OR,
+ "_b64_id($id)", atom_g_or>;
+ def ATOM_G_RSUB_B64 : BinAtomI64<IL_OP_UAV_READ_RSUB,
+ "_b64_id($id)", atom_g_rsub>;
+ def ATOM_G_SUB_B64 : BinAtomI64<IL_OP_UAV_READ_SUB,
+ "_b64_id($id)", atom_g_sub>;
+ def ATOM_G_XOR_B64 : BinAtomI64<IL_OP_UAV_READ_XOR,
+ "_b64_id($id)", atom_g_xor>;
+ def ATOM_G_INC_B64 : BinAtomI64<IL_OP_UAV_READ_INC,
+ "_b64_id($id)", atom_g_inc>;
+ def ATOM_G_DEC_B64 : BinAtomI64<IL_OP_UAV_READ_DEC,
+ "_b64_id($id)", atom_g_dec>;
+ def ATOM_G_XCHG_B64 : BinAtomI64<IL_OP_UAV_READ_XCHG,
+ "_b64_id($id)", atom_g_xchg>;
+ def ATOM_G_CMPXCHG_B64 : CmpXChgI64<IL_OP_UAV_READ_CMPXCHG,
+ "_b64_id($id)", atom_g_cmpxchg>;
+ }
+ let Predicates = [ArenaSupport], arenauav = 1 in {
+ def ATOM_A_ADD_NORET : BinAtomNoRet<IL_OP_UAV_ADD,
+ "_id($id)_arena", atom_g_add_noret>;
+ def ATOM_A_AND_NORET : BinAtomNoRet<IL_OP_UAV_AND,
+ "_id($id)_arena", atom_g_and_noret>;
+ def ATOM_A_MAX_NORET : BinAtomNoRet<IL_OP_UAV_MAX,
+ "_id($id)_arena", atom_g_max_noret>;
+ def ATOM_A_MIN_NORET : BinAtomNoRet<IL_OP_UAV_MIN,
+ "_id($id)_arena", atom_g_min_noret>;
+ def ATOM_A_UMAX_NORET : BinAtomNoRet<IL_OP_UAV_UMAX,
+ "_id($id)_arena", atom_g_umax_noret>;
+ def ATOM_A_UMIN_NORET : BinAtomNoRet<IL_OP_UAV_UMIN,
+ "_id($id)_arena", atom_g_umin_noret>;
+ def ATOM_A_OR_NORET : BinAtomNoRet<IL_OP_UAV_OR,
+ "_id($id)_arena", atom_g_or_noret>;
+ def ATOM_A_RSUB_NORET : BinAtomNoRet<IL_OP_UAV_RSUB,
+ "_id($id)_arena", atom_g_rsub_noret>;
+ def ATOM_A_SUB_NORET : BinAtomNoRet<IL_OP_UAV_SUB,
+ "_id($id)_arena", atom_g_sub_noret>;
+ def ATOM_A_XOR_NORET : BinAtomNoRet<IL_OP_UAV_XOR,
+ "_id($id)_arena", atom_g_xor_noret>;
+ def ATOM_A_INC_NORET : BinAtomNoRet<IL_OP_UAV_INC,
+ "_id($id)_arena", atom_g_inc_noret>;
+ def ATOM_A_DEC_NORET : BinAtomNoRet<IL_OP_UAV_DEC,
+ "_id($id)_arena", atom_g_dec_noret>;
+ def ATOM_A_CMPXCHG_NORET : CmpXChgNoRet<IL_OP_UAV_CMP,
+ "_id($id)_arena", atom_g_cmpxchg_noret>;
+ def ATOM_A_ADD : BinAtom<IL_OP_UAV_READ_ADD,
+ "_id($id)_arena", atom_g_add>;
+ def ATOM_A_AND : BinAtom<IL_OP_UAV_READ_AND,
+ "_id($id)_arena", atom_g_and>;
+ def ATOM_A_MAX : BinAtom<IL_OP_UAV_READ_MAX,
+ "_id($id)_arena", atom_g_max>;
+ def ATOM_A_MIN : BinAtom<IL_OP_UAV_READ_MIN,
+ "_id($id)_arena", atom_g_min>;
+ def ATOM_A_UMAX : BinAtom<IL_OP_UAV_READ_UMAX,
+ "_id($id)_arena", atom_g_umax>;
+ def ATOM_A_UMIN : BinAtom<IL_OP_UAV_READ_UMIN,
+ "_id($id)_arena", atom_g_umin>;
+ def ATOM_A_OR : BinAtom<IL_OP_UAV_READ_OR,
+ "_id($id)_arena", atom_g_or>;
+ def ATOM_A_RSUB : BinAtom<IL_OP_UAV_READ_RSUB,
+ "_id($id)_arena", atom_g_rsub>;
+ def ATOM_A_SUB : BinAtom<IL_OP_UAV_READ_SUB,
+ "_id($id)_arena", atom_g_sub>;
+ def ATOM_A_XOR : BinAtom<IL_OP_UAV_READ_XOR,
+ "_id($id)_arena", atom_g_xor>;
+ def ATOM_A_INC : BinAtom<IL_OP_UAV_READ_INC,
+ "_id($id)_arena", atom_g_inc>;
+ def ATOM_A_DEC : BinAtom<IL_OP_UAV_READ_DEC,
+ "_id($id)_arena", atom_g_dec>;
+ def ATOM_A_XCHG : BinAtom<IL_OP_UAV_READ_XCHG,
+ "_id($id)_arena", atom_g_xchg>;
+ def ATOM_A_CMPXCHG : CmpXChg<IL_OP_UAV_READ_CMPXCHG,
+ "_id($id)_arena", atom_g_cmpxchg>;
+ }
+ let local = 1 in {
+ def ATOM_L_ADD_NORET : BinAtomNoRet<IL_OP_LDS_ADD,
+ "_id($id)", atom_l_add_noret>;
+ def ATOM_L_AND_NORET : BinAtomNoRet<IL_OP_LDS_AND,
+ "_id($id)", atom_l_and_noret>;
+ def ATOM_L_MAX_NORET : BinAtomNoRet<IL_OP_LDS_MAX,
+ "_id($id)", atom_l_max_noret>;
+ def ATOM_L_MIN_NORET : BinAtomNoRet<IL_OP_LDS_MIN,
+ "_id($id)", atom_l_min_noret>;
+ def ATOM_L_UMAX_NORET : BinAtomNoRet<IL_OP_LDS_UMAX,
+ "_id($id)", atom_l_umax_noret>;
+ def ATOM_L_UMIN_NORET : BinAtomNoRet<IL_OP_LDS_UMIN,
+ "_id($id)", atom_l_umin_noret>;
+ def ATOM_L_MSKOR_NORET : TriAtomNoRet<IL_OP_LDS_MSKOR,
+ "_id($id)", atom_l_mskor_noret>;
+ def ATOM_L_OR_NORET : BinAtomNoRet<IL_OP_LDS_OR,
+ "_id($id)", atom_l_or_noret>;
+ def ATOM_L_RSUB_NORET : BinAtomNoRet<IL_OP_LDS_RSUB,
+ "_id($id)", atom_l_rsub_noret>;
+ def ATOM_L_SUB_NORET : BinAtomNoRet<IL_OP_LDS_SUB,
+ "_id($id)", atom_l_sub_noret>;
+ def ATOM_L_XOR_NORET : BinAtomNoRet<IL_OP_LDS_XOR,
+ "_id($id)", atom_l_xor_noret>;
+ def ATOM_L_INC_NORET : BinAtomNoRet<IL_OP_LDS_INC,
+ "_id($id)", atom_l_inc_noret>;
+ def ATOM_L_DEC_NORET : BinAtomNoRet<IL_OP_LDS_DEC,
+ "_id($id)", atom_l_dec_noret>;
+ def ATOM_L_CMPXCHG_NORET : TriAtomNoRet<IL_OP_LDS_CMP,
+ "_id($id)", atom_l_cmpxchg_noret>;
+ def ATOM_L_ADD : BinAtom<IL_OP_LDS_READ_ADD,
+ "_id($id)", atom_l_add>;
+ def ATOM_L_AND : BinAtom<IL_OP_LDS_READ_AND,
+ "_id($id)", atom_l_and>;
+ def ATOM_L_MAX : BinAtom<IL_OP_LDS_READ_MAX,
+ "_id($id)", atom_l_max>;
+ def ATOM_L_MIN : BinAtom<IL_OP_LDS_READ_MIN,
+ "_id($id)", atom_l_min>;
+ def ATOM_L_UMAX : BinAtom<IL_OP_LDS_READ_UMAX,
+ "_id($id)", atom_l_umax>;
+ def ATOM_L_UMIN : BinAtom<IL_OP_LDS_READ_UMIN,
+ "_id($id)", atom_l_umin>;
+ def ATOM_L_OR : BinAtom<IL_OP_LDS_READ_OR,
+ "_id($id)", atom_l_or>;
+ def ATOM_L_MSKOR : TriAtom<IL_OP_LDS_READ_MSKOR,
+ "_id($id)", atom_l_mskor>;
+ def ATOM_L_RSUB : BinAtom<IL_OP_LDS_READ_RSUB,
+ "_id($id)", atom_l_rsub>;
+ def ATOM_L_SUB : BinAtom<IL_OP_LDS_READ_SUB,
+ "_id($id)", atom_l_sub>;
+ def ATOM_L_XOR : BinAtom<IL_OP_LDS_READ_XOR,
+ "_id($id)", atom_l_xor>;
+ def ATOM_L_INC : BinAtom<IL_OP_LDS_READ_INC,
+ "_id($id)", atom_l_inc>;
+ def ATOM_L_DEC : BinAtom<IL_OP_LDS_READ_DEC,
+ "_id($id)", atom_l_dec>;
+ def ATOM_L_XCHG : BinAtom<IL_OP_LDS_READ_XCHG,
+ "_id($id)", atom_l_xchg>;
+ def ATOM_L_CMPXCHG : TriAtom<IL_OP_LDS_READ_CMPXCHG,
+ "_id($id)", atom_l_cmpxchg>;
+ def ATOM_L_ADD_NORET_B64 : BinAtomNoRetI64<IL_OP_LDS_ADD,
+ "64_id($id)", atom_l_add_noret>;
+ def ATOM_L_AND_NORET_B64 : BinAtomNoRetI64<IL_OP_LDS_AND,
+ "64_id($id)", atom_l_and_noret>;
+ def ATOM_L_MAX_NORET_B64 : BinAtomNoRetI64<IL_OP_LDS_MAX,
+ "64_id($id)", atom_l_max_noret>;
+ def ATOM_L_MIN_NORET_B64 : BinAtomNoRetI64<IL_OP_LDS_MIN,
+ "64_id($id)", atom_l_min_noret>;
+ def ATOM_L_UMAX_NORET_B64 : BinAtomNoRetI64<IL_OP_LDS_UMAX,
+ "64_id($id)", atom_l_umax_noret>;
+ def ATOM_L_UMIN_NORET_B64 : BinAtomNoRetI64<IL_OP_LDS_UMIN,
+ "64_id($id)", atom_l_umin_noret>;
+ def ATOM_L_MSKOR_NORET_B64: TriAtomNoRetI64<IL_OP_LDS_MSKOR,
+ "64_id($id)", atom_l_mskor_noret>;
+ def ATOM_L_OR_NORET_B64 : BinAtomNoRetI64<IL_OP_LDS_OR,
+ "64_id($id)", atom_l_or_noret>;
+ def ATOM_L_RSUB_NORET_B64 : BinAtomNoRetI64<IL_OP_LDS_RSUB,
+ "64_id($id)", atom_l_rsub_noret>;
+ def ATOM_L_SUB_NORET_B64 : BinAtomNoRetI64<IL_OP_LDS_SUB,
+ "64_id($id)", atom_l_sub_noret>;
+ def ATOM_L_XOR_NORET_B64 : BinAtomNoRetI64<IL_OP_LDS_XOR,
+ "64_id($id)", atom_l_xor_noret>;
+ def ATOM_L_INC_NORET_B64 : BinAtomNoRetI64<IL_OP_LDS_INC,
+ "64_id($id)", atom_l_inc_noret>;
+ def ATOM_L_DEC_NORET_B64 : BinAtomNoRetI64<IL_OP_LDS_DEC,
+ "64_id($id)", atom_l_dec_noret>;
+ def ATOM_L_CMPXCHG_NORET_B64 : TriAtomNoRetI64<IL_OP_LDS_CMP,
+ "64_id($id)", atom_l_cmpxchg_noret>;
+ def ATOM_L_ADD_B64 : BinAtomI64<IL_OP_LDS_READ_ADD,
+ "64_id($id)", atom_l_add>;
+ def ATOM_L_AND_B64 : BinAtomI64<IL_OP_LDS_READ_AND,
+ "64_id($id)", atom_l_and>;
+ def ATOM_L_MAX_B64 : BinAtomI64<IL_OP_LDS_READ_MAX,
+ "64_id($id)", atom_l_max>;
+ def ATOM_L_MIN_B64 : BinAtomI64<IL_OP_LDS_READ_MIN,
+ "64_id($id)", atom_l_min>;
+ def ATOM_L_UMAX_B64 : BinAtomI64<IL_OP_LDS_READ_UMAX,
+ "64_id($id)", atom_l_umax>;
+ def ATOM_L_UMIN_B64 : BinAtomI64<IL_OP_LDS_READ_UMIN,
+ "64_id($id)", atom_l_umin>;
+ def ATOM_L_OR_B64 : BinAtomI64<IL_OP_LDS_READ_OR,
+ "64_id($id)", atom_l_or>;
+ def ATOM_L_MSKOR_B64 : TriAtomI64<IL_OP_LDS_READ_MSKOR,
+ "64_id($id)", atom_l_mskor>;
+ def ATOM_L_RSUB_B64 : BinAtomI64<IL_OP_LDS_READ_RSUB,
+ "64_id($id)", atom_l_rsub>;
+ def ATOM_L_SUB_B64 : BinAtomI64<IL_OP_LDS_READ_SUB,
+ "64_id($id)", atom_l_sub>;
+ def ATOM_L_XOR_B64 : BinAtomI64<IL_OP_LDS_READ_XOR,
+ "64_id($id)", atom_l_xor>;
+ def ATOM_L_INC_B64 : BinAtomI64<IL_OP_LDS_READ_INC,
+ "64_id($id)", atom_l_inc>;
+ def ATOM_L_DEC_B64 : BinAtomI64<IL_OP_LDS_READ_DEC,
+ "64_id($id)", atom_l_dec>;
+ def ATOM_L_XCHG_B64 : BinAtomI64<IL_OP_LDS_READ_XCHG,
+ "64_id($id)", atom_l_xchg>;
+ def ATOM_L_CMPXCHG_B64 : TriAtomI64<IL_OP_LDS_READ_CMPXCHG,
+ "64_id($id)", atom_l_cmpxchg>;
+ }
+ let region = 1 in {
+ def ATOM_R_ADD_NORET : BinAtomNoRet<IL_OP_GDS_ADD,
+ "_id($id)", atom_r_add_noret>;
+ def ATOM_R_AND_NORET : BinAtomNoRet<IL_OP_GDS_AND,
+ "_id($id)", atom_r_and_noret>;
+ def ATOM_R_MAX_NORET : BinAtomNoRet<IL_OP_GDS_MAX,
+ "_id($id)", atom_r_max_noret>;
+ def ATOM_R_MIN_NORET : BinAtomNoRet<IL_OP_GDS_MIN,
+ "_id($id)", atom_r_min_noret>;
+ def ATOM_R_UMAX_NORET : BinAtomNoRet<IL_OP_GDS_UMAX,
+ "_id($id)", atom_r_umax_noret>;
+ def ATOM_R_UMIN_NORET : BinAtomNoRet<IL_OP_GDS_UMIN,
+ "_id($id)", atom_r_umin_noret>;
+ def ATOM_R_MSKOR_NORET : TriAtomNoRet<IL_OP_GDS_MSKOR,
+ "_id($id)", atom_r_mskor_noret>;
+ def ATOM_R_OR_NORET : BinAtomNoRet<IL_OP_GDS_OR,
+ "_id($id)", atom_r_or_noret>;
+ def ATOM_R_RSUB_NORET : BinAtomNoRet<IL_OP_GDS_RSUB,
+ "_id($id)", atom_r_rsub_noret>;
+ def ATOM_R_SUB_NORET : BinAtomNoRet<IL_OP_GDS_SUB,
+ "_id($id)", atom_r_sub_noret>;
+ def ATOM_R_XOR_NORET : BinAtomNoRet<IL_OP_GDS_XOR,
+ "_id($id)", atom_r_xor_noret>;
+ def ATOM_R_INC_NORET : BinAtomNoRet<IL_OP_GDS_INC,
+ "_id($id)", atom_r_inc_noret>;
+ def ATOM_R_DEC_NORET : BinAtomNoRet<IL_OP_GDS_DEC,
+ "_id($id)", atom_r_dec_noret>;
+ def ATOM_R_CMPXCHG_NORET : TriAtomNoRet<IL_OP_GDS_CMP,
+ "_id($id)", atom_r_cmpxchg_noret>;
+ def ATOM_R_ADD : BinAtom<IL_OP_GDS_READ_ADD,
+ "_id($id)", atom_r_add>;
+ def ATOM_R_AND : BinAtom<IL_OP_GDS_READ_AND,
+ "_id($id)", atom_r_and>;
+ def ATOM_R_MAX : BinAtom<IL_OP_GDS_READ_MAX,
+ "_id($id)", atom_r_max>;
+ def ATOM_R_MIN : BinAtom<IL_OP_GDS_READ_MIN,
+ "_id($id)", atom_r_min>;
+ def ATOM_R_UMAX : BinAtom<IL_OP_GDS_READ_UMAX,
+ "_id($id)", atom_r_umax>;
+ def ATOM_R_UMIN : BinAtom<IL_OP_GDS_READ_UMIN,
+ "_id($id)", atom_r_umin>;
+ def ATOM_R_OR : BinAtom<IL_OP_GDS_READ_OR,
+ "_id($id)", atom_r_or>;
+ def ATOM_R_MSKOR : TriAtom<IL_OP_GDS_READ_MSKOR,
+ "_id($id)", atom_r_mskor>;
+ def ATOM_R_RSUB : BinAtom<IL_OP_GDS_READ_RSUB,
+ "_id($id)", atom_r_rsub>;
+ def ATOM_R_SUB : BinAtom<IL_OP_GDS_READ_SUB,
+ "_id($id)", atom_r_sub>;
+ def ATOM_R_XOR : BinAtom<IL_OP_GDS_READ_XOR,
+ "_id($id)", atom_r_xor>;
+ def ATOM_R_INC : BinAtom<IL_OP_GDS_READ_INC,
+ "_id($id)", atom_r_inc>;
+ def ATOM_R_DEC : BinAtom<IL_OP_GDS_READ_DEC,
+ "_id($id)", atom_r_dec>;
+ def ATOM_R_XCHG : BinAtom<IL_OP_GDS_READ_XCHG,
+ "_id($id)", atom_r_xchg>;
+ def ATOM_R_CMPXCHG : TriAtom<IL_OP_GDS_READ_CMPXCHG,
+ "_id($id)", atom_r_cmpxchg>;
+ def ATOM_R_ADD_NORET_B64 : BinAtomNoRetI64<IL_OP_GDS_ADD,
+ "64_id($id)", atom_r_add_noret>;
+ def ATOM_R_AND_NORET_B64 : BinAtomNoRetI64<IL_OP_GDS_AND,
+ "64_id($id)", atom_r_and_noret>;
+ def ATOM_R_MAX_NORET_B64 : BinAtomNoRetI64<IL_OP_GDS_MAX,
+ "64_id($id)", atom_r_max_noret>;
+ def ATOM_R_MIN_NORET_B64 : BinAtomNoRetI64<IL_OP_GDS_MIN,
+ "64_id($id)", atom_r_min_noret>;
+ def ATOM_R_UMAX_NORET_B64 : BinAtomNoRetI64<IL_OP_GDS_UMAX,
+ "64_id($id)", atom_r_umax_noret>;
+ def ATOM_R_UMIN_NORET_B64 : BinAtomNoRetI64<IL_OP_GDS_UMIN,
+ "64_id($id)", atom_r_umin_noret>;
+ def ATOM_R_MSKOR_NORET_B64: TriAtomNoRetI64<IL_OP_GDS_MSKOR,
+ "64_id($id)", atom_r_mskor_noret>;
+ def ATOM_R_OR_NORET_B64 : BinAtomNoRetI64<IL_OP_GDS_OR,
+ "64_id($id)", atom_r_or_noret>;
+ def ATOM_R_RSUB_NORET_B64 : BinAtomNoRetI64<IL_OP_GDS_RSUB,
+ "64_id($id)", atom_r_rsub_noret>;
+ def ATOM_R_SUB_NORET_B64 : BinAtomNoRetI64<IL_OP_GDS_SUB,
+ "64_id($id)", atom_r_sub_noret>;
+ def ATOM_R_XOR_NORET_B64 : BinAtomNoRetI64<IL_OP_GDS_XOR,
+ "64_id($id)", atom_r_xor_noret>;
+ def ATOM_R_INC_NORET_B64 : BinAtomNoRetI64<IL_OP_GDS_INC,
+ "64_id($id)", atom_r_inc_noret>;
+ def ATOM_R_DEC_NORET_B64 : BinAtomNoRetI64<IL_OP_GDS_DEC,
+ "64_id($id)", atom_r_dec_noret>;
+ def ATOM_R_CMPXCHG_NORET_B64 : TriAtomNoRetI64<IL_OP_GDS_CMP,
+ "64_id($id)", atom_r_cmpxchg_noret>;
+ def ATOM_R_ADD_B64 : BinAtomI64<IL_OP_GDS_READ_ADD,
+ "64_id($id)", atom_r_add>;
+ def ATOM_R_AND_B64 : BinAtomI64<IL_OP_GDS_READ_AND,
+ "64_id($id)", atom_r_and>;
+ def ATOM_R_MAX_B64 : BinAtomI64<IL_OP_GDS_READ_MAX,
+ "64_id($id)", atom_r_max>;
+ def ATOM_R_MIN_B64 : BinAtomI64<IL_OP_GDS_READ_MIN,
+ "64_id($id)", atom_r_min>;
+ def ATOM_R_UMAX_B64 : BinAtomI64<IL_OP_GDS_READ_UMAX,
+ "64_id($id)", atom_r_umax>;
+ def ATOM_R_UMIN_B64 : BinAtomI64<IL_OP_GDS_READ_UMIN,
+ "64_id($id)", atom_r_umin>;
+ def ATOM_R_OR_B64 : BinAtomI64<IL_OP_GDS_READ_OR,
+ "64_id($id)", atom_r_or>;
+ def ATOM_R_MSKOR_B64 : TriAtomI64<IL_OP_GDS_READ_MSKOR,
+ "64_id($id)", atom_r_mskor>;
+ def ATOM_R_RSUB_B64 : BinAtomI64<IL_OP_GDS_READ_RSUB,
+ "64_id($id)", atom_r_rsub>;
+ def ATOM_R_SUB_B64 : BinAtomI64<IL_OP_GDS_READ_SUB,
+ "64_id($id)", atom_r_sub>;
+ def ATOM_R_XOR_B64 : BinAtomI64<IL_OP_GDS_READ_XOR,
+ "64_id($id)", atom_r_xor>;
+ def ATOM_R_INC_B64 : BinAtomI64<IL_OP_GDS_READ_INC,
+ "64_id($id)", atom_r_inc>;
+ def ATOM_R_DEC_B64 : BinAtomI64<IL_OP_GDS_READ_DEC,
+ "64_id($id)", atom_r_dec>;
+ def ATOM_R_XCHG_B64 : BinAtomI64<IL_OP_GDS_READ_XCHG,
+ "64_id($id)", atom_r_xchg>;
+ def ATOM_R_CMPXCHG_B64 : TriAtomI64<IL_OP_GDS_READ_CMPXCHG,
+ "64_id($id)", atom_r_cmpxchg>;
+ }
+ }
+
+ let append = 1, swizzle = 3 in {
+ def APPEND_ALLOC : Append<IL_OP_APPEND_BUF_ALLOC,
+ "_id($id)", append_alloc>;
+ def APPEND_CONSUME : Append<IL_OP_APPEND_BUF_CONSUME,
+ "_id($id)", append_consume>;
+ }
+
+ let sema = 1 in {
+ let swizzle = 7 in {
+ def SEMAPHORE_WAIT : ILFormat<IL_OP_SEMAPHORE_WAIT, (outs),
+ (ins MEM3232:$ptr),
+ !strconcat(IL_OP_SEMAPHORE_WAIT.Text, "_id($ptr)"),
+ [(int_AMDIL_semaphore_wait ADDR:$ptr)]>;
+
+ def SEMAPHORE_SIGNAL : ILFormat<IL_OP_SEMAPHORE_SIGNAL, (outs),
+ (ins MEM3232:$ptr),
+ !strconcat(IL_OP_SEMAPHORE_SIGNAL.Text, "_id($ptr)"),
+ [(int_AMDIL_semaphore_signal ADDR:$ptr)]>;
+ }
+ }
+
+ let Predicates = [IsSIOrLaterDevice] in {
+ // atomic global load
+ defm ATOM_G_LOAD : AtomGLoadMC<MEM3232, ADDR>;
+ // atomic global store
+ defm ATOM_G_STORE : AtomGLoadMC<MEM3232, ADDR>;
}
- def ATOM_L_ADD_NORET : BinAtomNoRet<IL_OP_LDS_ADD,
- "_id($id)", atom_l_add_noret>;
- def ATOM_L_AND_NORET : BinAtomNoRet<IL_OP_LDS_AND,
- "_id($id)", atom_l_and_noret>;
- def ATOM_L_MAX_NORET : BinAtomNoRet<IL_OP_LDS_MAX,
- "_id($id)", atom_l_max_noret>;
- def ATOM_L_MIN_NORET : BinAtomNoRet<IL_OP_LDS_MIN,
- "_id($id)", atom_l_min_noret>;
- def ATOM_L_UMAX_NORET : BinAtomNoRet<IL_OP_LDS_UMAX,
- "_id($id)", atom_l_umax_noret>;
- def ATOM_L_UMIN_NORET : BinAtomNoRet<IL_OP_LDS_UMIN,
- "_id($id)", atom_l_umin_noret>;
- def ATOM_L_MSKOR_NORET : TriAtomNoRet<IL_OP_LDS_MSKOR,
- "_id($id)", atom_l_mskor_noret>;
- def ATOM_L_OR_NORET : BinAtomNoRet<IL_OP_LDS_OR,
- "_id($id)", atom_l_or_noret>;
- def ATOM_L_RSUB_NORET : BinAtomNoRet<IL_OP_LDS_RSUB,
- "_id($id)", atom_l_rsub_noret>;
- def ATOM_L_SUB_NORET : BinAtomNoRet<IL_OP_LDS_SUB,
- "_id($id)", atom_l_sub_noret>;
- def ATOM_L_XOR_NORET : BinAtomNoRet<IL_OP_LDS_XOR,
- "_id($id)", atom_l_xor_noret>;
- def ATOM_L_INC_NORET : BinAtomNoRet<IL_OP_LDS_INC,
- "_id($id)", atom_l_inc_noret>;
- def ATOM_L_DEC_NORET : BinAtomNoRet<IL_OP_LDS_DEC,
- "_id($id)", atom_l_dec_noret>;
- def ATOM_L_CMPXCHG_NORET : TriAtomNoRet<IL_OP_LDS_CMP,
- "_id($id)", atom_l_cmpxchg_noret>;
- def ATOM_R_ADD_NORET : BinAtomNoRet<IL_OP_GDS_ADD,
- "_id($id)", atom_r_add_noret>;
- def ATOM_R_AND_NORET : BinAtomNoRet<IL_OP_GDS_AND,
- "_id($id)", atom_r_and_noret>;
- def ATOM_R_MAX_NORET : BinAtomNoRet<IL_OP_GDS_MAX,
- "_id($id)", atom_r_max_noret>;
- def ATOM_R_MIN_NORET : BinAtomNoRet<IL_OP_GDS_MIN,
- "_id($id)", atom_r_min_noret>;
- def ATOM_R_UMAX_NORET : BinAtomNoRet<IL_OP_GDS_UMAX,
- "_id($id)", atom_r_umax_noret>;
- def ATOM_R_UMIN_NORET : BinAtomNoRet<IL_OP_GDS_UMIN,
- "_id($id)", atom_r_umin_noret>;
- def ATOM_R_MSKOR_NORET : TriAtomNoRet<IL_OP_GDS_MSKOR,
- "_id($id)", atom_r_mskor_noret>;
- def ATOM_R_OR_NORET : BinAtomNoRet<IL_OP_GDS_OR,
- "_id($id)", atom_r_or_noret>;
- def ATOM_R_RSUB_NORET : BinAtomNoRet<IL_OP_GDS_RSUB,
- "_id($id)", atom_r_rsub_noret>;
- def ATOM_R_SUB_NORET : BinAtomNoRet<IL_OP_GDS_SUB,
- "_id($id)", atom_r_sub_noret>;
- def ATOM_R_XOR_NORET : BinAtomNoRet<IL_OP_GDS_XOR,
- "_id($id)", atom_r_xor_noret>;
- def ATOM_R_INC_NORET : BinAtomNoRet<IL_OP_GDS_INC,
- "_id($id)", atom_r_inc_noret>;
- def ATOM_R_DEC_NORET : BinAtomNoRet<IL_OP_GDS_DEC,
- "_id($id)", atom_r_dec_noret>;
- def ATOM_R_CMPXCHG_NORET : CmpXChgNoRet<IL_OP_GDS_CMP,
- "_id($id)", atom_r_cmpxchg_noret>;
- // All of the atomic functions that return
- def ATOM_G_ADD : BinAtom<IL_OP_UAV_READ_ADD,
- "_id($id)", atom_g_add>;
- def ATOM_G_AND : BinAtom<IL_OP_UAV_READ_AND,
- "_id($id)", atom_g_and>;
- def ATOM_G_MAX : BinAtom<IL_OP_UAV_READ_MAX,
- "_id($id)", atom_g_max>;
- def ATOM_G_MIN : BinAtom<IL_OP_UAV_READ_MIN,
- "_id($id)", atom_g_min>;
- def ATOM_G_UMAX : BinAtom<IL_OP_UAV_READ_UMAX,
- "_id($id)", atom_g_umax>;
- def ATOM_G_UMIN : BinAtom<IL_OP_UAV_READ_UMIN,
- "_id($id)", atom_g_umin>;
- def ATOM_G_OR : BinAtom<IL_OP_UAV_READ_OR,
- "_id($id)", atom_g_or>;
- def ATOM_G_RSUB : BinAtom<IL_OP_UAV_READ_RSUB,
- "_id($id)", atom_g_rsub>;
- def ATOM_G_SUB : BinAtom<IL_OP_UAV_READ_SUB,
- "_id($id)", atom_g_sub>;
- def ATOM_G_XOR : BinAtom<IL_OP_UAV_READ_XOR,
- "_id($id)", atom_g_xor>;
- def ATOM_G_INC : BinAtom<IL_OP_UAV_READ_INC,
- "_id($id)", atom_g_inc>;
- def ATOM_G_DEC : BinAtom<IL_OP_UAV_READ_DEC,
- "_id($id)", atom_g_dec>;
- def ATOM_G_XCHG : BinAtom<IL_OP_UAV_READ_XCHG,
- "_id($id)", atom_g_xchg>;
- def ATOM_G_CMPXCHG : CmpXChg<IL_OP_UAV_READ_CMPXCHG,
- "_id($id)", atom_g_cmpxchg>;
- // Arena atomic accesses
- let Predicates = [ArenaSupport] in {
- def ATOM_A_ADD : BinAtom<IL_OP_UAV_READ_ADD,
- "_id($id)_arena", atom_g_add>;
- def ATOM_A_AND : BinAtom<IL_OP_UAV_READ_AND,
- "_id($id)_arena", atom_g_and>;
- def ATOM_A_MAX : BinAtom<IL_OP_UAV_READ_MAX,
- "_id($id)_arena", atom_g_max>;
- def ATOM_A_MIN : BinAtom<IL_OP_UAV_READ_MIN,
- "_id($id)_arena", atom_g_min>;
- def ATOM_A_UMAX : BinAtom<IL_OP_UAV_READ_UMAX,
- "_id($id)_arena", atom_g_umax>;
- def ATOM_A_UMIN : BinAtom<IL_OP_UAV_READ_UMIN,
- "_id($id)_arena", atom_g_umin>;
- def ATOM_A_OR : BinAtom<IL_OP_UAV_READ_OR,
- "_id($id)_arena", atom_g_or>;
- def ATOM_A_RSUB : BinAtom<IL_OP_UAV_READ_RSUB,
- "_id($id)_arena", atom_g_rsub>;
- def ATOM_A_SUB : BinAtom<IL_OP_UAV_READ_SUB,
- "_id($id)_arena", atom_g_sub>;
- def ATOM_A_XOR : BinAtom<IL_OP_UAV_READ_XOR,
- "_id($id)_arena", atom_g_xor>;
- def ATOM_A_INC : BinAtom<IL_OP_UAV_READ_INC,
- "_id($id)_arena", atom_g_inc>;
- def ATOM_A_DEC : BinAtom<IL_OP_UAV_READ_DEC,
- "_id($id)_arena", atom_g_dec>;
- def ATOM_A_XCHG : BinAtom<IL_OP_UAV_READ_XCHG,
- "_id($id)_arena", atom_g_xchg>;
- def ATOM_A_CMPXCHG : CmpXChg<IL_OP_UAV_READ_CMPXCHG,
- "_id($id)_arena", atom_g_cmpxchg>;
-}
- def ATOM_L_ADD : BinAtom<IL_OP_LDS_READ_ADD,
- "_id($id)", atom_l_add>;
- def ATOM_L_AND : BinAtom<IL_OP_LDS_READ_AND,
- "_id($id)", atom_l_and>;
- def ATOM_L_MAX : BinAtom<IL_OP_LDS_READ_MAX,
- "_id($id)", atom_l_max>;
- def ATOM_L_MIN : BinAtom<IL_OP_LDS_READ_MIN,
- "_id($id)", atom_l_min>;
- def ATOM_L_UMAX : BinAtom<IL_OP_LDS_READ_UMAX,
- "_id($id)", atom_l_umax>;
- def ATOM_L_UMIN : BinAtom<IL_OP_LDS_READ_UMIN,
- "_id($id)", atom_l_umin>;
- def ATOM_L_OR : BinAtom<IL_OP_LDS_READ_OR,
- "_id($id)", atom_l_or>;
- def ATOM_L_MSKOR : TriAtom<IL_OP_LDS_READ_MSKOR,
- "_id($id)", atom_l_mskor>;
- def ATOM_L_RSUB : BinAtom<IL_OP_LDS_READ_RSUB,
- "_id($id)", atom_l_rsub>;
- def ATOM_L_SUB : BinAtom<IL_OP_LDS_READ_SUB,
- "_id($id)", atom_l_sub>;
- def ATOM_L_XOR : BinAtom<IL_OP_LDS_READ_XOR,
- "_id($id)", atom_l_xor>;
- def ATOM_L_INC : BinAtom<IL_OP_LDS_READ_INC,
- "_id($id)", atom_l_inc>;
- def ATOM_L_DEC : BinAtom<IL_OP_LDS_READ_DEC,
- "_id($id)", atom_l_dec>;
- def ATOM_L_XCHG : BinAtom<IL_OP_LDS_READ_XCHG,
- "_id($id)", atom_l_xchg>;
- def ATOM_L_CMPXCHG : TriAtom<IL_OP_LDS_READ_CMPXCHG,
- "_id($id)", atom_l_cmpxchg>;
- def ATOM_R_ADD : BinAtom<IL_OP_GDS_READ_ADD,
- "_id($id)", atom_r_add>;
- def ATOM_R_AND : BinAtom<IL_OP_GDS_READ_AND,
- "_id($id)", atom_r_and>;
- def ATOM_R_MAX : BinAtom<IL_OP_GDS_READ_MAX,
- "_id($id)", atom_r_max>;
- def ATOM_R_MIN : BinAtom<IL_OP_GDS_READ_MIN,
- "_id($id)", atom_r_min>;
- def ATOM_R_UMAX : BinAtom<IL_OP_GDS_READ_UMAX,
- "_id($id)", atom_r_umax>;
- def ATOM_R_UMIN : BinAtom<IL_OP_GDS_READ_UMIN,
- "_id($id)", atom_r_umin>;
- def ATOM_R_OR : BinAtom<IL_OP_GDS_READ_OR,
- "_id($id)", atom_r_or>;
- def ATOM_R_MSKOR : TriAtom<IL_OP_GDS_READ_MSKOR,
- "_id($id)", atom_r_mskor>;
- def ATOM_R_RSUB : BinAtom<IL_OP_GDS_READ_RSUB,
- "_id($id)", atom_r_rsub>;
- def ATOM_R_SUB : BinAtom<IL_OP_GDS_READ_SUB,
- "_id($id)", atom_r_sub>;
- def ATOM_R_XOR : BinAtom<IL_OP_GDS_READ_XOR,
- "_id($id)", atom_r_xor>;
- def ATOM_R_INC : BinAtom<IL_OP_GDS_READ_INC,
- "_id($id)", atom_r_inc>;
- def ATOM_R_DEC : BinAtom<IL_OP_GDS_READ_DEC,
- "_id($id)", atom_r_dec>;
- def ATOM_R_XCHG : BinAtom<IL_OP_GDS_READ_XCHG,
- "_id($id)", atom_r_xchg>;
- def ATOM_R_CMPXCHG : CmpXChg<IL_OP_GDS_READ_CMPXCHG,
- "_id($id)", atom_r_cmpxchg>;
- // 64bit atomic operations.
- def ATOM_G_ADD_NORET_B64 : BinAtomNoRetI64<IL_OP_UAV_ADD,
- "_b64_id($id)", atom_g_add_noret>;
- def ATOM_G_AND_NORET_B64 : BinAtomNoRetI64<IL_OP_UAV_AND,
- "_b64_id($id)", atom_g_and_noret>;
- def ATOM_G_MAX_NORET_B64 : BinAtomNoRetI64<IL_OP_UAV_MAX,
- "_b64_id($id)", atom_g_max_noret>;
- def ATOM_G_MIN_NORET_B64 : BinAtomNoRetI64<IL_OP_UAV_MIN,
- "_b64_id($id)", atom_g_min_noret>;
- def ATOM_G_UMAX_NORET_B64 : BinAtomNoRetI64<IL_OP_UAV_UMAX,
- "_b64_id($id)", atom_g_umax_noret>;
- def ATOM_G_UMIN_NORET_B64 : BinAtomNoRetI64<IL_OP_UAV_UMIN,
- "_b64_id($id)", atom_g_umin_noret>;
- def ATOM_G_OR_NORET_B64 : BinAtomNoRetI64<IL_OP_UAV_OR,
- "_b64_id($id)", atom_g_or_noret>;
- def ATOM_G_RSUB_NORET_B64 : BinAtomNoRetI64<IL_OP_UAV_RSUB,
- "_b64_id($id)", atom_g_rsub_noret>;
- def ATOM_G_SUB_NORET_B64 : BinAtomNoRetI64<IL_OP_UAV_SUB,
- "_b64_id($id)", atom_g_sub_noret>;
- def ATOM_G_XOR_NORET_B64 : BinAtomNoRetI64<IL_OP_UAV_XOR,
- "_b64_id($id)", atom_g_xor_noret>;
- def ATOM_G_INC_NORET_B64 : BinAtomNoRetI64<IL_OP_UAV_INC,
- "_b64_id($id)", atom_g_inc_noret>;
- def ATOM_G_DEC_NORET_B64 : BinAtomNoRetI64<IL_OP_UAV_DEC,
- "_b64_id($id)", atom_g_dec_noret>;
- def ATOM_G_CMPXCHG_NORET_B64 : CmpXChgNoRetI64<IL_OP_UAV_CMP,
- "_b64_id($id)", atom_g_cmpxchg_noret>;
- def ATOM_L_ADD_NORET_B64 : BinAtomNoRetI64<IL_OP_LDS_ADD,
- "64_id($id)", atom_l_add_noret>;
- def ATOM_L_AND_NORET_B64 : BinAtomNoRetI64<IL_OP_LDS_AND,
- "64_id($id)", atom_l_and_noret>;
- def ATOM_L_MAX_NORET_B64 : BinAtomNoRetI64<IL_OP_LDS_MAX,
- "64_id($id)", atom_l_max_noret>;
- def ATOM_L_MIN_NORET_B64 : BinAtomNoRetI64<IL_OP_LDS_MIN,
- "64_id($id)", atom_l_min_noret>;
- def ATOM_L_UMAX_NORET_B64 : BinAtomNoRetI64<IL_OP_LDS_UMAX,
- "64_id($id)", atom_l_umax_noret>;
- def ATOM_L_UMIN_NORET_B64 : BinAtomNoRetI64<IL_OP_LDS_UMIN,
- "64_id($id)", atom_l_umin_noret>;
- def ATOM_L_MSKOR_NORET_B64: TriAtomNoRetI64<IL_OP_LDS_MSKOR,
- "64_id($id)", atom_l_mskor_noret>;
- def ATOM_L_OR_NORET_B64 : BinAtomNoRetI64<IL_OP_LDS_OR,
- "64_id($id)", atom_l_or_noret>;
- def ATOM_L_RSUB_NORET_B64 : BinAtomNoRetI64<IL_OP_LDS_RSUB,
- "64_id($id)", atom_l_rsub_noret>;
- def ATOM_L_SUB_NORET_B64 : BinAtomNoRetI64<IL_OP_LDS_SUB,
- "64_id($id)", atom_l_sub_noret>;
- def ATOM_L_XOR_NORET_B64 : BinAtomNoRetI64<IL_OP_LDS_XOR,
- "64_id($id)", atom_l_xor_noret>;
- def ATOM_L_INC_NORET_B64 : BinAtomNoRetI64<IL_OP_LDS_INC,
- "64_id($id)", atom_l_inc_noret>;
- def ATOM_L_DEC_NORET_B64 : BinAtomNoRetI64<IL_OP_LDS_DEC,
- "64_id($id)", atom_l_dec_noret>;
- def ATOM_L_CMPXCHG_NORET_B64 : TriAtomNoRetI64<IL_OP_LDS_CMP,
- "64_id($id)", atom_l_cmpxchg_noret>;
- def ATOM_R_ADD_NORET_B64 : BinAtomNoRetI64<IL_OP_GDS_ADD,
- "64_id($id)", atom_r_add_noret>;
- def ATOM_R_AND_NORET_B64 : BinAtomNoRetI64<IL_OP_GDS_AND,
- "64_id($id)", atom_r_and_noret>;
- def ATOM_R_MAX_NORET_B64 : BinAtomNoRetI64<IL_OP_GDS_MAX,
- "64_id($id)", atom_r_max_noret>;
- def ATOM_R_MIN_NORET_B64 : BinAtomNoRetI64<IL_OP_GDS_MIN,
- "64_id($id)", atom_r_min_noret>;
- def ATOM_R_UMAX_NORET_B64 : BinAtomNoRetI64<IL_OP_GDS_UMAX,
- "64_id($id)", atom_r_umax_noret>;
- def ATOM_R_UMIN_NORET_B64 : BinAtomNoRetI64<IL_OP_GDS_UMIN,
- "64_id($id)", atom_r_umin_noret>;
- def ATOM_R_MSKOR_NORET_B64: TriAtomNoRetI64<IL_OP_GDS_MSKOR,
- "64_id($id)", atom_r_mskor_noret>;
- def ATOM_R_OR_NORET_B64 : BinAtomNoRetI64<IL_OP_GDS_OR,
- "64_id($id)", atom_r_or_noret>;
- def ATOM_R_RSUB_NORET_B64 : BinAtomNoRetI64<IL_OP_GDS_RSUB,
- "64_id($id)", atom_r_rsub_noret>;
- def ATOM_R_SUB_NORET_B64 : BinAtomNoRetI64<IL_OP_GDS_SUB,
- "64_id($id)", atom_r_sub_noret>;
- def ATOM_R_XOR_NORET_B64 : BinAtomNoRetI64<IL_OP_GDS_XOR,
- "64_id($id)", atom_r_xor_noret>;
- def ATOM_R_INC_NORET_B64 : BinAtomNoRetI64<IL_OP_GDS_INC,
- "64_id($id)", atom_r_inc_noret>;
- def ATOM_R_DEC_NORET_B64 : BinAtomNoRetI64<IL_OP_GDS_DEC,
- "64_id($id)", atom_r_dec_noret>;
- def ATOM_R_CMPXCHG_NORET_B64 : CmpXChgNoRetI64<IL_OP_GDS_CMP,
- "64_id($id)", atom_r_cmpxchg_noret>;
- // All of the atomic functions that return
- def ATOM_G_ADD_B64 : BinAtomI64<IL_OP_UAV_READ_ADD,
- "_b64_id($id)", atom_g_add>;
- def ATOM_G_AND_B64 : BinAtomI64<IL_OP_UAV_READ_AND,
- "_b64_id($id)", atom_g_and>;
- def ATOM_G_MAX_B64 : BinAtomI64<IL_OP_UAV_READ_MAX,
- "_b64_id($id)", atom_g_max>;
- def ATOM_G_MIN_B64 : BinAtomI64<IL_OP_UAV_READ_MIN,
- "_b64_id($id)", atom_g_min>;
- def ATOM_G_UMAX_B64 : BinAtomI64<IL_OP_UAV_READ_UMAX,
- "_b64_id($id)", atom_g_umax>;
- def ATOM_G_UMIN_B64 : BinAtomI64<IL_OP_UAV_READ_UMIN,
- "_b64_id($id)", atom_g_umin>;
- def ATOM_G_OR_B64 : BinAtomI64<IL_OP_UAV_READ_OR,
- "_b64_id($id)", atom_g_or>;
- def ATOM_G_RSUB_B64 : BinAtomI64<IL_OP_UAV_READ_RSUB,
- "_b64_id($id)", atom_g_rsub>;
- def ATOM_G_SUB_B64 : BinAtomI64<IL_OP_UAV_READ_SUB,
- "_b64_id($id)", atom_g_sub>;
- def ATOM_G_XOR_B64 : BinAtomI64<IL_OP_UAV_READ_XOR,
- "_b64_id($id)", atom_g_xor>;
- def ATOM_G_INC_B64 : BinAtomI64<IL_OP_UAV_READ_INC,
- "_b64_id($id)", atom_g_inc>;
- def ATOM_G_DEC_B64 : BinAtomI64<IL_OP_UAV_READ_DEC,
- "_b64_id($id)", atom_g_dec>;
- def ATOM_G_XCHG_B64 : BinAtomI64<IL_OP_UAV_READ_XCHG,
- "_b64_id($id)", atom_g_xchg>;
- def ATOM_G_CMPXCHG_B64 : CmpXChgI64<IL_OP_UAV_READ_CMPXCHG,
- "_b64_id($id)", atom_g_cmpxchg>;
- def ATOM_L_ADD_B64 : BinAtomI64<IL_OP_LDS_READ_ADD,
- "64_id($id)", atom_l_add>;
- def ATOM_L_AND_B64 : BinAtomI64<IL_OP_LDS_READ_AND,
- "64_id($id)", atom_l_and>;
- def ATOM_L_MAX_B64 : BinAtomI64<IL_OP_LDS_READ_MAX,
- "64_id($id)", atom_l_max>;
- def ATOM_L_MIN_B64 : BinAtomI64<IL_OP_LDS_READ_MIN,
- "64_id($id)", atom_l_min>;
- def ATOM_L_UMAX_B64 : BinAtomI64<IL_OP_LDS_READ_UMAX,
- "64_id($id)", atom_l_umax>;
- def ATOM_L_UMIN_B64 : BinAtomI64<IL_OP_LDS_READ_UMIN,
- "64_id($id)", atom_l_umin>;
- def ATOM_L_OR_B64 : BinAtomI64<IL_OP_LDS_READ_OR,
- "64_id($id)", atom_l_or>;
- def ATOM_L_MSKOR_B64 : TriAtomI64<IL_OP_LDS_READ_MSKOR,
- "64_id($id)", atom_l_mskor>;
- def ATOM_L_RSUB_B64 : BinAtomI64<IL_OP_LDS_READ_RSUB,
- "64_id($id)", atom_l_rsub>;
- def ATOM_L_SUB_B64 : BinAtomI64<IL_OP_LDS_READ_SUB,
- "64_id($id)", atom_l_sub>;
- def ATOM_L_XOR_B64 : BinAtomI64<IL_OP_LDS_READ_XOR,
- "64_id($id)", atom_l_xor>;
- def ATOM_L_INC_B64 : BinAtomI64<IL_OP_LDS_READ_INC,
- "64_id($id)", atom_l_inc>;
- def ATOM_L_DEC_B64 : BinAtomI64<IL_OP_LDS_READ_DEC,
- "64_id($id)", atom_l_dec>;
- def ATOM_L_XCHG_B64 : BinAtomI64<IL_OP_LDS_READ_XCHG,
- "64_id($id)", atom_l_xchg>;
- def ATOM_L_CMPXCHG_B64 : TriAtomI64<IL_OP_LDS_READ_CMPXCHG,
- "64_id($id)", atom_l_cmpxchg>;
- def ATOM_R_ADD_B64 : BinAtomI64<IL_OP_GDS_READ_ADD,
- "64_id($id)", atom_r_add>;
- def ATOM_R_AND_B64 : BinAtomI64<IL_OP_GDS_READ_AND,
- "64_id($id)", atom_r_and>;
- def ATOM_R_MAX_B64 : BinAtomI64<IL_OP_GDS_READ_MAX,
- "64_id($id)", atom_r_max>;
- def ATOM_R_MIN_B64 : BinAtomI64<IL_OP_GDS_READ_MIN,
- "64_id($id)", atom_r_min>;
- def ATOM_R_UMAX_B64 : BinAtomI64<IL_OP_GDS_READ_UMAX,
- "64_id($id)", atom_r_umax>;
- def ATOM_R_UMIN_B64 : BinAtomI64<IL_OP_GDS_READ_UMIN,
- "64_id($id)", atom_r_umin>;
- def ATOM_R_OR_B64 : BinAtomI64<IL_OP_GDS_READ_OR,
- "64_id($id)", atom_r_or>;
- def ATOM_R_MSKOR_B64 : TriAtomI64<IL_OP_GDS_READ_MSKOR,
- "64_id($id)", atom_r_mskor>;
- def ATOM_R_RSUB_B64 : BinAtomI64<IL_OP_GDS_READ_RSUB,
- "64_id($id)", atom_r_rsub>;
- def ATOM_R_SUB_B64 : BinAtomI64<IL_OP_GDS_READ_SUB,
- "64_id($id)", atom_r_sub>;
- def ATOM_R_XOR_B64 : BinAtomI64<IL_OP_GDS_READ_XOR,
- "64_id($id)", atom_r_xor>;
- def ATOM_R_INC_B64 : BinAtomI64<IL_OP_GDS_READ_INC,
- "64_id($id)", atom_r_inc>;
- def ATOM_R_DEC_B64 : BinAtomI64<IL_OP_GDS_READ_DEC,
- "64_id($id)", atom_r_dec>;
- def ATOM_R_XCHG_B64 : BinAtomI64<IL_OP_GDS_READ_XCHG,
- "64_id($id)", atom_r_xchg>;
- def ATOM_R_CMPXCHG_B64 : CmpXChgI64<IL_OP_GDS_READ_CMPXCHG,
- "64_id($id)", atom_r_cmpxchg>;
-
- // atomic counter operations.
- def APPEND_ALLOC : Append<IL_OP_APPEND_BUF_ALLOC,
- "_id($id)", append_alloc>;
- def APPEND_CONSUME : Append<IL_OP_APPEND_BUF_CONSUME,
- "_id($id)", append_consume>;
}
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILMem64.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILMem64.td?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILMem64.td (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILMem64.td Wed Sep 12 12:43:34 2012
@@ -11,709 +11,521 @@
//
//===----------------------------------------------------------------------===//
-let Predicates = [Has64BitPtr] in {
+let Predicates = [Has64BitPtr], addr64 = 1 in {
let isCodeGenOnly=1 in {
//===----------------------------------------------------------------------===//
// Store Memory Operations
//===----------------------------------------------------------------------===//
- defm GLOBALTRUNCSTORE64 : GTRUNCSTORE64<"!global trunc store">;
- defm GLOBAL : STORE64<"!global store" , global_store>;
- defm LOCALTRUNCSTORE64 : LTRUNCSTORE64<"!local trunc store">;
- defm LOCAL : STORE64<"!local store" , local_store>;
- defm PRIVATETRUNCSTORE64 : PTRUNCSTORE64<"!private trunc store">;
- defm PRIVATE : STORE64<"!private store" , private_store>;
- defm REGIONTRUNCSTORE64 : RTRUNCSTORE64<"!region trunc store">;
- defm REGION : STORE64<"!region hw store" , region_store>;
-
-
- //===---------------------------------------------------------------------===//
- // Load Memory Operations
- //===---------------------------------------------------------------------===//
- defm GLOBAL : LOAD64<"!global load" , global_load>;
- defm GLOBALZEXT : LOAD64<"!global zext load" , global_zext_load>;
- defm GLOBALSEXT : LOAD64<"!global sext load" , global_sext_load>;
- defm GLOBALAEXT : LOAD64<"!global aext load" , global_aext_load>;
- defm PRIVATE : LOAD64<"!private load" , private_load>;
- defm PRIVATEZEXT : LOAD64<"!private zext load" , private_zext_load>;
- defm PRIVATESEXT : LOAD64<"!private sext load" , private_sext_load>;
- defm PRIVATEAEXT : LOAD64<"!private aext load" , private_aext_load>;
- defm CPOOL : LOAD64<"!constant pool load" , cp_load>;
- defm CPOOLZEXT : LOAD64<"!constant pool zext load", cp_zext_load>;
- defm CPOOLSEXT : LOAD64<"!constant pool sext load", cp_sext_load>;
- defm CPOOLAEXT : LOAD64<"!constant aext pool load", cp_aext_load>;
- defm CONSTANT : LOAD64<"!constant load" , constant_load>;
- defm CONSTANTZEXT : LOAD64<"!constant zext load" , constant_zext_load>;
- defm CONSTANTSEXT : LOAD64<"!constant sext load" , constant_sext_load>;
- defm CONSTANTAEXT : LOAD64<"!constant aext load" , constant_aext_load>;
- defm LOCAL : LOAD64<"!local load" , local_load>;
- defm LOCALZEXT : LOAD64<"!local zext load" , local_zext_load>;
- defm LOCALSEXT : LOAD64<"!local sext load" , local_sext_load>;
- defm LOCALAEXT : LOAD64<"!local aext load" , local_aext_load>;
- defm REGION : LOAD64<"!region load" , region_load>;
- defm REGIONZEXT : LOAD64<"!region zext load" , region_zext_load>;
- defm REGIONSEXT : LOAD64<"!region sext load" , region_sext_load>;
- defm REGIONAEXT : LOAD64<"!region aext load" , region_aext_load>;
+ defm GLOBALTRUNCSTORE64 : GTRUNCSTORE<"!global trunc store", MEM6464, ADDR64>;
+ let global = 1 in {
+ defm GLOBALSTORE64 : STORE<"!global store" , global_store, MEM6464, ADDR64>;
+ }
+ defm LOCALTRUNCSTORE64 : LTRUNCSTORE<"!local trunc store", MEM6464, ADDR64>;
+ let local = 1 in {
+ defm LOCALSTORE64 : STORE<"!local store" , local_store, MEM6464, ADDR64>;
+ }
+ defm PRIVATETRUNCSTORE64 : PTRUNCSTORE<"!private trunc store", MEM6464, ADDR64>;
+ let private = 1 in {
+ defm PRIVATESTORE64 : STORE<"!private store" , private_store, MEM6464, ADDR64>;
+ }
+ defm REGIONTRUNCSTORE64 : RTRUNCSTORE<"!region trunc store", MEM6464, ADDR64>;
+ let region = 1 in {
+ defm REGIONSTORE64 : STORE<"!region hw store" , region_store, MEM6464, ADDR64>;
+ }
+ }
+
+
+ //===---------------------------------------------------------------------===//
+ // Load Memory Operations
+ //===---------------------------------------------------------------------===//
+ let global = 1 in {
+ defm GLOBALLOAD64 : LOAD<"!global load" , global_load, MEM6464, ADDR64>;
+ let extLoadType = 2 in {
+ defm GLOBALZEXTLOAD64 : LOAD<"!global zext load" , global_zext_load, MEM6464, ADDR64>;
+ }
+ let extLoadType = 1 in {
+ defm GLOBALSEXTLOAD64 : LOAD<"!global sext load" , global_sext_load, MEM6464, ADDR64>;
+ }
+ let extLoadType = 3 in {
+ defm GLOBALAEXTLOAD64 : LOAD<"!global aext load" , global_aext_load, MEM6464, ADDR64>;
+ }
+ }
+ let private = 1 in {
+ defm PRIVATELOAD64 : LOAD<"!private load" , private_load, MEM6464, ADDR64>;
+ let extLoadType = 2 in {
+ defm PRIVATEZEXTLOAD64 : LOAD<"!private zext load" , private_zext_load, MEM6464, ADDR64>;
+ }
+ let extLoadType = 1 in {
+ defm PRIVATESEXTLOAD64 : LOAD<"!private sext load" , private_sext_load, MEM6464, ADDR64>;
+ }
+ let extLoadType = 3 in {
+ defm PRIVATEAEXTLOAD64 : LOAD<"!private aext load" , private_aext_load, MEM6464, ADDR64>;
+ }
+ }
+ let cpool = 1 in {
+ defm CPOOLLOAD64 : LOAD<"!constant pool load" , cp_load, MEM6464, ADDR64>;
+ let extLoadType = 2 in {
+ defm CPOOLZEXTLOAD64 : LOAD<"!constant pool zext load", cp_zext_load, MEM6464, ADDR64>;
+ }
+ let extLoadType = 1 in {
+ defm CPOOLSEXTLOAD64 : LOAD<"!constant pool sext load", cp_sext_load, MEM6464, ADDR64>;
+ }
+ let extLoadType = 3 in {
+ defm CPOOLAEXTLOAD64 : LOAD<"!constant aext pool load", cp_aext_load, MEM6464, ADDR64>;
+ }
+ }
+ let constant = 1 in {
+ defm CONSTANTLOAD64 : LOAD<"!constant load" , constant_load, MEM6464, ADDR64>;
+ let extLoadType = 2 in {
+ defm CONSTANTZEXTLOAD64 : LOAD<"!constant zext load" , constant_zext_load, MEM6464, ADDR64>;
+ }
+ let extLoadType = 1 in {
+ defm CONSTANTSEXTLOAD64 : LOAD<"!constant sext load" , constant_sext_load, MEM6464, ADDR64>;
+ }
+ let extLoadType = 3 in {
+ defm CONSTANTAEXTLOAD64 : LOAD<"!constant aext load" , constant_aext_load, MEM6464, ADDR64>;
+ }
+ }
+ let local = 1 in {
+ defm LOCALLOAD64 : LOAD<"!local load" , local_load, MEM6464, ADDR64>;
+ let extLoadType = 2 in {
+ defm LOCALZEXTLOAD64 : LOAD<"!local zext load" , local_zext_load, MEM6464, ADDR64>;
+ }
+ let extLoadType = 1 in {
+ defm LOCALSEXTLOAD64 : LOAD<"!local sext load" , local_sext_load, MEM6464, ADDR64>;
+ }
+ let extLoadType = 3 in {
+ defm LOCALAEXTLOAD64 : LOAD<"!local aext load" , local_aext_load, MEM6464, ADDR64>;
+ }
+ }
+ let region = 1 in {
+ defm REGIONLOAD64 : LOAD<"!region load" , region_load, MEM6464, ADDR64>;
+ let extLoadType = 2 in {
+ defm REGIONZEXTLOAD64 : LOAD<"!region zext load" , region_zext_load, MEM6464, ADDR64>;
+ }
+ let extLoadType = 1 in {
+ defm REGIONSEXTLOAD64 : LOAD<"!region sext load" , region_sext_load, MEM6464, ADDR64>;
+ }
+ let extLoadType = 3 in {
+ defm REGIONAEXTLOAD64 : LOAD<"!region aext load" , region_aext_load, MEM6464, ADDR64>;
+ }
}
//===---------------------------------------------------------------------===//
// IO Expansion Load/Store Instructions
//===---------------------------------------------------------------------===//
- // These opcode has custom swizzle patterns for some of the arguments.
- let mayLoad = 1 in {
- def UAVRAWLOAD64_i32 : TwoInOneOut<IL_OP_RAW_UAV_LOAD, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i64imm:$id),
- !strconcat(IL_OP_RAW_UAV_LOAD.Text, "_addr(64)_id($id) $dst, $addy"), []>;
- def UAVRAWLOAD64_v2i32 : TwoInOneOut<IL_OP_RAW_UAV_LOAD, (outs GPRV2I32:$dst),
- (ins GPRXI32:$addy, i64imm:$id),
- !strconcat(IL_OP_RAW_UAV_LOAD.Text, "_addr(64)_id($id) $dst, $addy"), []>;
- def UAVRAWLOAD64_v4i32 : TwoInOneOut<IL_OP_RAW_UAV_LOAD, (outs GPRV4I32:$dst),
- (ins GPRXI32:$addy, i64imm:$id),
- !strconcat(IL_OP_RAW_UAV_LOAD.Text, "_addr(64)_id($id) $dst, $addy"), []>;
- def UAVRAWLOADCACHED64_i32 : TwoInOneOut<IL_OP_RAW_UAV_LOAD, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i64imm:$id),
- !strconcat(IL_OP_RAW_UAV_LOAD.Text, "_addr(64)_id($id)_cached $dst, $addy"), []>;
- def UAVRAWLOADCACHED64_v2i32 : TwoInOneOut<IL_OP_RAW_UAV_LOAD, (outs GPRV2I32:$dst),
- (ins GPRXI32:$addy, i64imm:$id),
- !strconcat(IL_OP_RAW_UAV_LOAD.Text, "_addr(64)_id($id)_cached $dst, $addy"), []>;
- def UAVRAWLOADCACHED64_v4i32 : TwoInOneOut<IL_OP_RAW_UAV_LOAD, (outs GPRV4I32:$dst),
- (ins GPRXI32:$addy, i64imm:$id),
- !strconcat(IL_OP_RAW_UAV_LOAD.Text, "_addr(64)_id($id)_cached $dst, $addy"), []>;
- def UAVRAWLOADCACHEDALIGNED64_v2i32 : TwoInOneOut<IL_OP_RAW_UAV_LOAD, (outs GPRV2I32:$dst),
- (ins GPRXI32:$addy, i64imm:$id),
- !strconcat(IL_OP_RAW_UAV_LOAD.Text, "_addr(64)_id($id)_cached_aligned $dst, $addy"), []>;
- def UAVRAWLOADCACHEDALIGNED64_v4i32 : TwoInOneOut<IL_OP_RAW_UAV_LOAD, (outs GPRV4I32:$dst),
- (ins GPRXI32:$addy, i64imm:$id),
- !strconcat(IL_OP_RAW_UAV_LOAD.Text, "_addr(64)_id($id)_cached_aligned $dst, $addy"), []>;
- let Predicates = [HasByteShortUAV] in {
- def UAVRAWLOAD64_i8 : TwoInOneOut<IL_OP_UAV_BYTE_LOAD, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i64imm:$id),
- !strconcat(IL_OP_UAV_BYTE_LOAD.Text, "_addr(64)_id($id) $dst, $addy"), []>;
- def UAVRAWLOAD64_u8 : TwoInOneOut<IL_OP_UAV_UBYTE_LOAD, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i64imm:$id),
- !strconcat(IL_OP_UAV_UBYTE_LOAD.Text, "_addr(64)_id($id) $dst, $addy"), []>;
- def UAVRAWLOAD64_i16 : TwoInOneOut<IL_OP_UAV_SHORT_LOAD, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i64imm:$id),
- !strconcat(IL_OP_UAV_SHORT_LOAD.Text, "_addr(64)_id($id) $dst, $addy"), []>;
- def UAVRAWLOAD64_u16 : TwoInOneOut<IL_OP_UAV_USHORT_LOAD, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i64imm:$id),
- !strconcat(IL_OP_UAV_USHORT_LOAD.Text, "_addr(64)_id($id) $dst, $addy"), []>;
- def UAVRAWSTORE64_i8 : TwoInOneOut<IL_OP_UAV_BYTE_STORE, (outs GPRI32:$mem),
- (ins GPRXI32:$addy, GPRI32:$src, i64imm:$id),
- !strconcat(IL_OP_UAV_BYTE_STORE.Text, "_addr(64)_id($id) $mem, $addy, $src"), []>;
- def UAVRAWSTORE64_i16 : TwoInOneOut<IL_OP_UAV_SHORT_STORE, (outs GPRI32:$mem),
- (ins GPRXI32:$addy, GPRI32:$src, i64imm:$id),
- !strconcat(IL_OP_UAV_SHORT_STORE.Text, "_addr(64)_id($id) $mem, $addy, $src"), []>;
- def UAVRAWLOADCACHED64_i8 : TwoInOneOut<IL_OP_UAV_BYTE_LOAD, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i64imm:$id),
- !strconcat(IL_OP_UAV_BYTE_LOAD.Text, "_addr(64)_id($id)_cached $dst, $addy"), []>;
- def UAVRAWLOADCACHED64_u8 : TwoInOneOut<IL_OP_UAV_UBYTE_LOAD, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i64imm:$id),
- !strconcat(IL_OP_UAV_UBYTE_LOAD.Text, "_addr(64)_id($id)_cached $dst, $addy"), []>;
- def UAVRAWLOADCACHED64_i16 : TwoInOneOut<IL_OP_UAV_SHORT_LOAD, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i64imm:$id),
- !strconcat(IL_OP_UAV_SHORT_LOAD.Text, "_addr(64)_id($id)_cached $dst, $addy"), []>;
- def UAVRAWLOADCACHED64_u16 : TwoInOneOut<IL_OP_UAV_USHORT_LOAD, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i64imm:$id),
- !strconcat(IL_OP_UAV_USHORT_LOAD.Text, "_addr(64)_id($id)_cached $dst, $addy"), []>;
- }
- def SCRATCHLOAD64 : TwoInOneOut<IL_OP_MOV, (outs GPRV4I32:$dst),
- (ins GPRXI32:$addy, i64imm:$id),
- !strconcat(IL_OP_MOV.Text, " $dst, x$id[$addy]"), []>;
- def CBLOAD64 : TwoInOneOut<IL_OP_MOV, (outs GPRV4I32:$dst),
- (ins GPRXI32:$addy, i64imm:$id),
+ let mayLoad = 1, cbmem = 1 in {
+ def CB64LOAD : ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
+ (ins GPRXYI64:$addy, i32imm:$id),
!strconcat(IL_OP_MOV.Text, " $dst, cb$id[$addy]"), []>;
- def GDSLOAD64 : TwoInOneOut<IL_OP_GDS_LOAD, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i64imm:$id),
- !strconcat(IL_OP_GDS_LOAD.Text, "_id($id) $dst, $addy"), []>;
- def GDSLOAD64_i8 : TwoInOneOut<IL_OP_GDS_LOAD_BYTE, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i64imm:$id),
- !strconcat(IL_OP_GDS_LOAD_BYTE.Text, "_id($id) $dst, $addy"), []>;
- def GDSLOAD64_u8 : TwoInOneOut<IL_OP_GDS_LOAD_UBYTE, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i64imm:$id),
- !strconcat(IL_OP_GDS_LOAD_UBYTE.Text, "_id($id) $dst, $addy"), []>;
- def GDSLOAD64_i16 : TwoInOneOut<IL_OP_GDS_LOAD_SHORT, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i64imm:$id),
- !strconcat(IL_OP_GDS_LOAD_SHORT.Text, "_id($id) $dst, $addy"), []>;
- def GDSLOAD64_u16 : TwoInOneOut<IL_OP_GDS_LOAD_USHORT, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i64imm:$id),
- !strconcat(IL_OP_GDS_LOAD_USHORT.Text, "_id($id) $dst, $addy"), []>;
-
- def LDSLOADVEC64 : TwoInOneOut<IL_OP_LDS_LOAD_VEC, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i64imm:$id),
- !strconcat(IL_OP_LDS_LOAD_VEC.Text, "_id($id) $dst, $addy, $addy"), []>;
- def LDSLOADVEC64_v2i32 : TwoInOneOut<IL_OP_LDS_LOAD_VEC, (outs GPRV2I32:$dst),
- (ins GPRXI32:$addy, i64imm:$id),
- !strconcat(IL_OP_LDS_LOAD_VEC.Text, "_id($id) $dst, $addy, $addy"), []>;
- def LDSLOADVEC64_v4i32 : TwoInOneOut<IL_OP_LDS_LOAD_VEC, (outs GPRV4I32:$dst),
- (ins GPRXI32:$addy, i64imm:$id),
- !strconcat(IL_OP_LDS_LOAD_VEC.Text, "_id($id) $dst, $addy, $addy"), []>;
- def LDSLOAD64 : TwoInOneOut<IL_OP_LDS_LOAD, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i64imm:$id),
- !strconcat(IL_OP_LDS_LOAD.Text, "_id($id) $dst, $addy"), []>;
- def LDSLOAD64_i8 : TwoInOneOut<IL_OP_LDS_LOAD_BYTE, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i64imm:$id),
- !strconcat(IL_OP_LDS_LOAD_BYTE.Text, "_id($id) $dst, $addy"), []>;
- def LDSLOAD64_u8 : TwoInOneOut<IL_OP_LDS_LOAD_UBYTE, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i64imm:$id),
- !strconcat(IL_OP_LDS_LOAD_UBYTE.Text, "_id($id) $dst, $addy"), []>;
- def LDSLOAD64_i16 : TwoInOneOut<IL_OP_LDS_LOAD_SHORT, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i64imm:$id),
- !strconcat(IL_OP_LDS_LOAD_SHORT.Text, "_id($id) $dst, $addy"), []>;
- def LDSLOAD64_u16 : TwoInOneOut<IL_OP_LDS_LOAD_USHORT, (outs GPRI32:$dst),
- (ins GPRXI32:$addy, i64imm:$id),
- !strconcat(IL_OP_LDS_LOAD_USHORT.Text, "_id($id) $dst, $addy"), []>;
-
- }
- let mayStore = 1 in {
- def UAVRAWSTORE64_i32 : TwoInOneOut<IL_OP_RAW_UAV_STORE, (outs GPRI32:$mem),
- (ins GPRXI32:$addy, GPRI32:$src, i64imm:$id),
- !strconcat(IL_OP_RAW_UAV_STORE.Text, "_addr(64)_id($id) $mem, $addy, $src"), []>;
- def UAVRAWSTORE64_v2i32 : TwoInOneOut<IL_OP_RAW_UAV_STORE, (outs GPRV2I32:$mem),
- (ins GPRXI32:$addy, GPRV2I32:$src, i64imm:$id),
- !strconcat(IL_OP_RAW_UAV_STORE.Text, "_addr(64)_id($id) $mem, $addy, $src"), []>;
- def UAVRAWSTORE64_v4i32 : TwoInOneOut<IL_OP_RAW_UAV_STORE, (outs GPRV4I32:$mem),
- (ins GPRXI32:$addy, GPRV4I32:$src, i64imm:$id),
- !strconcat(IL_OP_RAW_UAV_STORE.Text, "_addr(64)_id($id) $mem, $addy, $src"), []>;
- def SCRATCHSTORE64 : TwoInOneOut<IL_OP_MOV, (outs GPRXI32:$addy),
- (ins GPRV4I32:$data, i64imm:$id),
- !strconcat(IL_OP_MOV.Text, " x$id[$addy, $data"), []>;
- def GDSSTORE64 : TwoInOneOut<IL_OP_GDS_STORE, (outs GPRXI32:$addy),
- (ins GPRI32:$src, i64imm:$id),
- !strconcat(IL_OP_GDS_STORE.Text, "_id($id) $addy, $src"), []>;
- def LDSSTOREVEC64 : ThreeInOneOut<IL_OP_LDS_STORE_VEC, (outs GPRI32:$mem),
- (ins GPRXI32:$addy, GPRI32:$src, i64imm:$id),
- !strconcat(IL_OP_LDS_STORE_VEC.Text, "_id($id) $mem, $addy, $src, $src"), []>;
- def LDSSTOREVEC64_v2i32 : ThreeInOneOut<IL_OP_LDS_STORE_VEC, (outs GPRV2I32:$mem),
- (ins GPRXI32:$addy, GPRV2I32:$src, i64imm:$id),
- !strconcat(IL_OP_LDS_STORE_VEC.Text, "_id($id) $mem, $addy, $src, $src"), []>;
- def LDSSTOREVEC64_v4i32 : ThreeInOneOut<IL_OP_LDS_STORE_VEC, (outs GPRV4I32:$mem),
- (ins GPRXI32:$addy, GPRV4I32:$src, i64imm:$id),
- !strconcat(IL_OP_LDS_STORE_VEC.Text, "_id($id) $mem, $addy, $src, $src"), []>;
- def LDSSTORE64 : TwoInOneOut<IL_OP_LDS_STORE, (outs GPRXI32:$addy),
- (ins GPRI32:$src, i64imm:$id),
- !strconcat(IL_OP_LDS_STORE.Text, "_id($id) $addy, $src"), []>;
- def LDSSTORE64_i8 : TwoInOneOut<IL_OP_LDS_STORE_BYTE, (outs GPRXI32:$addy),
- (ins GPRI32:$src, i64imm:$id),
- !strconcat(IL_OP_LDS_STORE_BYTE.Text, "_id($id) $addy, $src"), []>;
- def LDSSTORE64_i16 : TwoInOneOut<IL_OP_LDS_STORE_SHORT, (outs GPRXI32:$addy),
- (ins GPRI32:$src, i64imm:$id),
- !strconcat(IL_OP_LDS_STORE_SHORT.Text, "_id($id) $addy, $src"), []>;
- }
- // Image related operations.
- def IMAGE1D64_READ : ILFormat<IL_OP_SAMPLE, (outs GPRV4I32:$dst),
- (ins MEM6464:$ptr, GPRI32:$sampler, GPRV4F32:$addy),
- !strconcat(IL_OP_SAMPLE.Text,
- "_id($ptr)_sampler($sampler)_coordtype(normalized) $dst, $addy"),
- [(set GPRV4I32:$dst,
- (int_AMDIL_image1d_read_norm ADDR64:$ptr, GPRI32:$sampler, GPRV4F32:$addy))]>;
- def IMAGE1DA64_READ : ILFormat<IL_OP_SAMPLE, (outs GPRV4I32:$dst),
- (ins MEM6464:$ptr, GPRI32:$sampler, GPRV4F32:$addy),
- !strconcat(IL_OP_SAMPLE.Text,
- "_id($ptr)_sampler($sampler)_coordtype(normalized) $dst, $addy"),
- [(set GPRV4I32:$dst,
- (int_AMDIL_image1d_array_read_norm ADDR64:$ptr, GPRI32:$sampler, GPRV4F32:$addy))]>;
- def IMAGE1DB64_TXLD : ILFormat<IL_OP_LOAD, (outs GPRV4I32:$dst),
- (ins MEM6464:$ptr, GPRI32:$addy),
- !strconcat(IL_OP_LOAD.Text,
- "_id($ptr) $dst, $addy"),
- [(set GPRV4I32:$dst,
- (int_AMDIL_image1d_buffer_load ADDR64:$ptr, GPRI32:$addy))]>;
- def IMAGE1DB64_READ : ILFormat<IL_OP_SAMPLE, (outs GPRV4I32:$dst),
- (ins MEM6464:$ptr, GPRI32:$sampler, GPRV4F32:$addy),
- !strconcat(IL_OP_SAMPLE.Text,
- "_id($ptr)_sampler($sampler)_coordtype(normalized) $dst, $addy"),
- [(set GPRV4I32:$dst,
- (int_AMDIL_image1d_buffer_read_norm ADDR64:$ptr, GPRI32:$sampler, GPRV4F32:$addy))]>;
- def IMAGE2D64_READ : ILFormat<IL_OP_SAMPLE, (outs GPRV4I32:$dst),
- (ins MEM6464:$ptr, GPRI32:$sampler, GPRV4F32:$addy),
- !strconcat(IL_OP_SAMPLE.Text,
- "_id($ptr)_sampler($sampler)_coordtype(normalized) $dst, $addy"),
- [(set GPRV4I32:$dst,
- (int_AMDIL_image2d_read_norm ADDR64:$ptr, GPRI32:$sampler, GPRV4F32:$addy))]>;
- def IMAGE2DA64_READ : ILFormat<IL_OP_SAMPLE, (outs GPRV4I32:$dst),
- (ins MEM6464:$ptr, GPRI32:$sampler, GPRV4F32:$addy),
- !strconcat(IL_OP_SAMPLE.Text,
- "_id($ptr)_sampler($sampler)_coordtype(normalized) $dst, $addy"),
- [(set GPRV4I32:$dst,
- (int_AMDIL_image2d_array_read_norm ADDR64:$ptr, GPRI32:$sampler, GPRV4F32:$addy))]>;
- def IMAGE3D64_READ : ILFormat<IL_OP_SAMPLE, (outs GPRV4I32:$dst),
- (ins MEM6464:$ptr, GPRI32:$sampler, GPRV4F32:$addy),
- !strconcat(IL_OP_SAMPLE.Text,
- "_id($ptr)_sampler($sampler)_coordtype(normalized) $dst, $addy"),
- [(set GPRV4I32:$dst,
- (int_AMDIL_image3d_read_norm ADDR64:$ptr, GPRI32:$sampler, GPRV4F32:$addy))]>;
- def IMAGE1D64_READ_UNNORM : ILFormat<IL_OP_SAMPLE, (outs GPRV4I32:$dst),
- (ins MEM6464:$ptr, GPRI32:$sampler, GPRV4F32:$addy),
- !strconcat(IL_OP_SAMPLE.Text,
- "_id($ptr)_sampler($sampler)_coordtype(unnormalized) $dst, $addy"),
- [(set GPRV4I32:$dst,
- (int_AMDIL_image1d_read_unnorm ADDR64:$ptr, GPRI32:$sampler, GPRV4F32:$addy))]>;
- def IMAGE1DA64_READ_UNNORM : ILFormat<IL_OP_SAMPLE, (outs GPRV4I32:$dst),
- (ins MEM6464:$ptr, GPRI32:$sampler, GPRV4F32:$addy),
- !strconcat(IL_OP_SAMPLE.Text,
- "_id($ptr)_sampler($sampler)_coordtype(unnormalized) $dst, $addy"),
- [(set GPRV4I32:$dst,
- (int_AMDIL_image1d_array_read_unnorm ADDR64:$ptr, GPRI32:$sampler, GPRV4F32:$addy))]>;
- def IMAGE1DB64_READ_UNNORM : ILFormat<IL_OP_SAMPLE, (outs GPRV4I32:$dst),
- (ins MEM6464:$ptr, GPRI32:$sampler, GPRV4F32:$addy),
- !strconcat(IL_OP_SAMPLE.Text,
- "_id($ptr)_sampler($sampler)_coordtype(unnormalized) $dst, $addy"),
- [(set GPRV4I32:$dst,
- (int_AMDIL_image1d_buffer_read_unnorm ADDR64:$ptr, GPRI32:$sampler, GPRV4F32:$addy))]>;
- def IMAGE2D64_READ_UNNORM : ILFormat<IL_OP_SAMPLE, (outs GPRV4I32:$dst),
- (ins MEM6464:$ptr, GPRI32:$sampler, GPRV4F32:$addy),
- !strconcat(IL_OP_SAMPLE.Text,
- "_id($ptr)_sampler($sampler)_coordtype(unnormalized) $dst, $addy"),
- [(set GPRV4I32:$dst,
- (int_AMDIL_image2d_read_unnorm ADDR64:$ptr, GPRI32:$sampler, GPRV4F32:$addy))]>;
- def IMAGE2DA64_READ_UNNORM : ILFormat<IL_OP_SAMPLE, (outs GPRV4I32:$dst),
- (ins MEM6464:$ptr, GPRI32:$sampler, GPRV4F32:$addy),
- !strconcat(IL_OP_SAMPLE.Text,
- "_id($ptr)_sampler($sampler)_coordtype(unnormalized) $dst, $addy"),
- [(set GPRV4I32:$dst,
- (int_AMDIL_image2d_array_read_unnorm ADDR64:$ptr, GPRI32:$sampler, GPRV4F32:$addy))]>;
- def IMAGE3D64_READ_UNNORM : ILFormat<IL_OP_SAMPLE, (outs GPRV4I32:$dst),
- (ins MEM6464:$ptr, GPRI32:$sampler, GPRV4F32:$addy),
- !strconcat(IL_OP_SAMPLE.Text,
- "_id($ptr)_sampler($sampler)_coordtype(unnormalized) $dst, $addy"),
- [(set GPRV4I32:$dst,
- (int_AMDIL_image3d_read_unnorm ADDR64:$ptr, GPRI32:$sampler, GPRV4F32:$addy))]>;
- def IMAGE1D64_INFO0 : ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
- (ins MEM6464:$ptr),
- !strconcat(IL_OP_MOV.Text, " $dst, $ptr"),
- [(set GPRV4I32:$dst, (int_AMDIL_image1d_info0 ADDR64:$ptr))]>;
- def IMAGE1D64_INFO1 : ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
- (ins MEM6464:$ptr),
- !strconcat(IL_OP_MOV.Text, " $dst, $ptr"),
- [(set GPRV4I32:$dst, (int_AMDIL_image1d_info1 ADDR64:$ptr))]>;
- def IMAGE1DA64_INFO0 : ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
- (ins MEM6464:$ptr),
- !strconcat(IL_OP_MOV.Text, " $dst, $ptr"),
- [(set GPRV4I32:$dst, (int_AMDIL_image1d_array_info0 ADDR64:$ptr))]>;
- def IMAGE1DA64_INFO1 : ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
- (ins MEM6464:$ptr),
- !strconcat(IL_OP_MOV.Text, " $dst, $ptr"),
- [(set GPRV4I32:$dst, (int_AMDIL_image1d_array_info1 ADDR64:$ptr))]>;
- def IMAGE1DB64_INFO0 : ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
- (ins MEM6464:$ptr),
- !strconcat(IL_OP_MOV.Text, " $dst, $ptr"),
- [(set GPRV4I32:$dst, (int_AMDIL_image1d_buffer_info0 ADDR64:$ptr))]>;
- def IMAGE1DB64_INFO1 : ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
- (ins MEM6464:$ptr),
- !strconcat(IL_OP_MOV.Text, " $dst, $ptr"),
- [(set GPRV4I32:$dst, (int_AMDIL_image1d_buffer_info1 ADDR64:$ptr))]>;
- def IMAGE2DA64_INFO0 : ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
- (ins MEM6464:$ptr),
- !strconcat(IL_OP_MOV.Text, " $dst, $ptr"),
- [(set GPRV4I32:$dst, (int_AMDIL_image2d_array_info0 ADDR64:$ptr))]>;
- def IMAGE2DA64_INFO1 : ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
- (ins MEM6464:$ptr),
- !strconcat(IL_OP_MOV.Text, " $dst, $ptr"),
- [(set GPRV4I32:$dst, (int_AMDIL_image2d_array_info1 ADDR64:$ptr))]>;
- def IMAGE2D64_INFO0 : ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
- (ins MEM6464:$ptr),
- !strconcat(IL_OP_MOV.Text, " $dst, $ptr"),
- [(set GPRV4I32:$dst, (int_AMDIL_image2d_info0 ADDR64:$ptr))]>;
- def IMAGE2D64_INFO1 : ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
- (ins MEM6464:$ptr),
- !strconcat(IL_OP_MOV.Text, " $dst, $ptr"),
- [(set GPRV4I32:$dst, (int_AMDIL_image2d_info1 ADDR64:$ptr))]>;
- def IMAGE3D64_INFO0 : ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
- (ins MEM6464:$ptr),
- !strconcat(IL_OP_MOV.Text, " $dst, $ptr"),
- [(set GPRV4I32:$dst, (int_AMDIL_image3d_info0 ADDR64:$ptr))]>;
- def IMAGE3D64_INFO1 : ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
- (ins MEM6464:$ptr),
- !strconcat(IL_OP_MOV.Text, " $dst, $ptr"),
- [(set GPRV4I32:$dst, (int_AMDIL_image3d_info1 ADDR64:$ptr))]>;
- def IMAGE1D64_WRITE : ILFormat<IL_OP_UAV_STORE, (outs),
- (ins MEM6464:$ptr, GPRV2I32:$addy, GPRV4I32:$data),
- !strconcat(IL_OP_UAV_STORE.Text,
- "_id($ptr) $addy, $data"),
- [(int_AMDIL_image1d_write ADDR64:$ptr, GPRV2I32:$addy, GPRV4I32:$data)]>;
- def IMAGE1DA64_WRITE : ILFormat<IL_OP_UAV_STORE, (outs),
- (ins MEM6464:$ptr, GPRV2I32:$addy, GPRV4I32:$data),
- !strconcat(IL_OP_UAV_STORE.Text,
- "_id($ptr) $addy, $data"),
- [(int_AMDIL_image1d_array_write ADDR64:$ptr, GPRV2I32:$addy, GPRV4I32:$data)]>;
- def IMAGE1DB64_WRITE : ILFormat<IL_OP_UAV_STORE, (outs),
- (ins MEM6464:$ptr, GPRV2I32:$addy, GPRV4I32:$data),
- !strconcat(IL_OP_UAV_STORE.Text,
- "_id($ptr) $addy, $data"),
- [(int_AMDIL_image1d_buffer_write ADDR64:$ptr, GPRV2I32:$addy, GPRV4I32:$data)]>;
- def IMAGE2D64_WRITE : ILFormat<IL_OP_UAV_STORE, (outs),
- (ins MEM6464:$ptr, GPRV2I32:$addy, GPRV4I32:$data),
- !strconcat(IL_OP_UAV_STORE.Text,
- "_id($ptr) $addy, $data"),
- [(int_AMDIL_image2d_write ADDR64:$ptr, GPRV2I32:$addy, GPRV4I32:$data)]>;
- def IMAGE2DA64_WRITE : ILFormat<IL_OP_UAV_STORE, (outs),
- (ins MEM6464:$ptr, GPRV4I32:$addy, GPRV4I32:$data),
- !strconcat(IL_OP_UAV_STORE.Text,
- "_id($ptr) $addy, $data"),
- [(int_AMDIL_image2d_array_write ADDR64:$ptr, GPRV4I32:$addy, GPRV4I32:$data)]>;
- def IMAGE3D64_WRITE : ILFormat<IL_OP_UAV_STORE, (outs),
- (ins MEM6464:$ptr, GPRV4I32:$addy, GPRV4I32:$data),
- !strconcat(IL_OP_UAV_STORE.Text,
- "_id($ptr) $addy, $data"),
- [(int_AMDIL_image3d_write ADDR64:$ptr, GPRV4I32:$addy, GPRV4I32:$data)]>;
+ }
+ let addr64 = 1 in {
+ defm UAVRAW64 : UAVRawLSInst<GPRXYI64, "_addr(64)_id($id)">;
+ defm SCRATCH64 : ScratchLSInst<GPRXYI64>;
+ defm GDS64 : GDSLSInst<GPRI32>;
+ defm LDS64 : LDSLSInst<GPRI32>;
+
+ let image = 1, txld = 1, load = 1 in {
+ def TXLD641DB : ILFormat<IL_OP_LOAD, (outs GPRV4I32:$dst),
+ (ins MEM6464:$ptr, GPRI32:$addy),
+ !strconcat(IL_OP_LOAD.Text,
+ "_id($ptr) $dst, $addy"),
+ [(set GPRV4I32:$dst,
+ (int_AMDIL_image1d_buffer_load ADDR64:$ptr, GPRI32:$addy))]>;
+ }
+ defm READ64 : IMAGEREAD<MEM6464, ADDR64>;
+ defm INFO064 : IMAGEINFO0<MEM6464, ADDR64>;
+ defm INFO164 : IMAGEINFO1<MEM6464, ADDR64>;
+ defm WRITE64 : IMAGEWRITE<MEM6464, ADDR64>;
+ }
// Printf related operations.
let isCall=1, isAsCheapAsAMove = 1 in {
- def GET_PRINTF_OFFSET_i64: ILFormat<IL_OP_MOV, (outs GPRXYI64:$dst),
+ def GET_PRINTF_OFFSETi64: ILFormat<IL_OP_MOV, (outs GPRXYI64:$dst),
(ins), !strconcat(IL_OP_MOV.Text, " $dst, cb0[8].zw"),
[(set GPRXYI64:$dst, (int_AMDIL_get_printf_offset))]>;
- def GET_PRINTF_SIZE_i64 : ILFormat<IL_OP_MOV, (outs GPRXYI64:$dst),
+ def GET_PRINTF_SIZEi64 : ILFormat<IL_OP_MOV, (outs GPRXYI64:$dst),
(ins), !strconcat(IL_OP_MOV.Text, " $dst, cb0[9].x0"),
[(set GPRXYI64:$dst, (int_AMDIL_get_printf_size))]>;
}
- // Atomic operations
- def ATOM64_G_ADD_NORET : BinAtomNoRet64<IL_OP_UAV_ADD,
- "_addr(64)_id($id)", atom_g_add_noret>;
- def ATOM64_G_AND_NORET : BinAtomNoRet64<IL_OP_UAV_AND,
- "_addr(64)_id($id)", atom_g_and_noret>;
- def ATOM64_G_MAX_NORET : BinAtomNoRet64<IL_OP_UAV_MAX,
- "_addr(64)_id($id)", atom_g_max_noret>;
- def ATOM64_G_MIN_NORET : BinAtomNoRet64<IL_OP_UAV_MIN,
- "_addr(64)_id($id)", atom_g_min_noret>;
- def ATOM64_G_UMAX_NORET : BinAtomNoRet64<IL_OP_UAV_UMAX,
- "_addr(64)_id($id)", atom_g_umax_noret>;
- def ATOM64_G_UMIN_NORET : BinAtomNoRet64<IL_OP_UAV_UMIN,
- "_addr(64)_id($id)", atom_g_umin_noret>;
- def ATOM64_G_OR_NORET : BinAtomNoRet64<IL_OP_UAV_OR,
- "_addr(64)_id($id)", atom_g_or_noret>;
- def ATOM64_G_RSUB_NORET : BinAtomNoRet64<IL_OP_UAV_RSUB,
- "_addr(64)_id($id)", atom_g_rsub_noret>;
- def ATOM64_G_SUB_NORET : BinAtomNoRet64<IL_OP_UAV_SUB,
- "_addr(64)_id($id)", atom_g_sub_noret>;
- def ATOM64_G_XOR_NORET : BinAtomNoRet64<IL_OP_UAV_XOR,
- "_addr(64)_id($id)", atom_g_xor_noret>;
- def ATOM64_G_INC_NORET : BinAtomNoRet64<IL_OP_UAV_INC,
- "_addr(64)_id($id)", atom_g_inc_noret>;
- def ATOM64_G_DEC_NORET : BinAtomNoRet64<IL_OP_UAV_DEC,
- "_addr(64)_id($id)", atom_g_dec_noret>;
- def ATOM64_G_CMPXCHG_NORET : CmpXChgNoRet64<IL_OP_UAV_CMP,
- "_addr(64)_id($id)", atom_g_cmpxchg_noret>;
- def ATOM64_L_ADD_NORET : BinAtomNoRet64<IL_OP_LDS_ADD,
- "_id($id)", atom_l_add_noret>;
- def ATOM64_L_AND_NORET : BinAtomNoRet64<IL_OP_LDS_AND,
- "_id($id)", atom_l_and_noret>;
- def ATOM64_L_MAX_NORET : BinAtomNoRet64<IL_OP_LDS_MAX,
- "_id($id)", atom_l_max_noret>;
- def ATOM64_L_MIN_NORET : BinAtomNoRet64<IL_OP_LDS_MIN,
- "_id($id)", atom_l_min_noret>;
- def ATOM64_L_UMAX_NORET : BinAtomNoRet64<IL_OP_LDS_UMAX,
- "_id($id)", atom_l_umax_noret>;
- def ATOM64_L_UMIN_NORET : BinAtomNoRet64<IL_OP_LDS_UMIN,
- "_id($id)", atom_l_umin_noret>;
- def ATOM64_L_MSKOR_NORET : TriAtomNoRet64<IL_OP_LDS_MSKOR,
- "_id($id)", atom_l_mskor_noret>;
- def ATOM64_L_OR_NORET : BinAtomNoRet64<IL_OP_LDS_OR,
- "_id($id)", atom_l_or_noret>;
- def ATOM64_L_RSUB_NORET : BinAtomNoRet64<IL_OP_LDS_RSUB,
- "_id($id)", atom_l_rsub_noret>;
- def ATOM64_L_SUB_NORET : BinAtomNoRet64<IL_OP_LDS_SUB,
- "_id($id)", atom_l_sub_noret>;
- def ATOM64_L_XOR_NORET : BinAtomNoRet64<IL_OP_LDS_XOR,
- "_id($id)", atom_l_xor_noret>;
- def ATOM64_L_INC_NORET : BinAtomNoRet64<IL_OP_LDS_INC,
- "_id($id)", atom_l_inc_noret>;
- def ATOM64_L_DEC_NORET : BinAtomNoRet64<IL_OP_LDS_DEC,
- "_id($id)", atom_l_dec_noret>;
- def ATOM64_L_CMPXCHG_NORET : TriAtomNoRet64<IL_OP_LDS_CMP,
- "_id($id)", atom_l_cmpxchg_noret>;
- def ATOM64_R_ADD_NORET : BinAtomNoRet64<IL_OP_GDS_ADD,
- "_id($id)", atom_r_add_noret>;
- def ATOM64_R_AND_NORET : BinAtomNoRet64<IL_OP_GDS_AND,
- "_id($id)", atom_r_and_noret>;
- def ATOM64_R_MAX_NORET : BinAtomNoRet64<IL_OP_GDS_MAX,
- "_id($id)", atom_r_max_noret>;
- def ATOM64_R_MIN_NORET : BinAtomNoRet64<IL_OP_GDS_MIN,
- "_id($id)", atom_r_min_noret>;
- def ATOM64_R_UMAX_NORET : BinAtomNoRet64<IL_OP_GDS_UMAX,
- "_id($id)", atom_r_umax_noret>;
- def ATOM64_R_UMIN_NORET : BinAtomNoRet64<IL_OP_GDS_UMIN,
- "_id($id)", atom_r_umin_noret>;
- def ATOM64_R_MSKOR_NORET : TriAtomNoRet64<IL_OP_GDS_MSKOR,
- "_id($id)", atom_r_mskor_noret>;
- def ATOM64_R_OR_NORET : BinAtomNoRet64<IL_OP_GDS_OR,
- "_id($id)", atom_r_or_noret>;
- def ATOM64_R_RSUB_NORET : BinAtomNoRet64<IL_OP_GDS_RSUB,
- "_id($id)", atom_r_rsub_noret>;
- def ATOM64_R_SUB_NORET : BinAtomNoRet64<IL_OP_GDS_SUB,
- "_id($id)", atom_r_sub_noret>;
- def ATOM64_R_XOR_NORET : BinAtomNoRet64<IL_OP_GDS_XOR,
- "_id($id)", atom_r_xor_noret>;
- def ATOM64_R_INC_NORET : BinAtomNoRet64<IL_OP_GDS_INC,
- "_id($id)", atom_r_inc_noret>;
- def ATOM64_R_DEC_NORET : BinAtomNoRet64<IL_OP_GDS_DEC,
- "_id($id)", atom_r_dec_noret>;
- def ATOM64_R_CMPXCHG_NORET : CmpXChgNoRet64<IL_OP_GDS_CMP,
- "_id($id)", atom_r_cmpxchg_noret>;
- // All of the atomic functions that return
- def ATOM64_G_ADD : BinAtom64<IL_OP_UAV_READ_ADD,
- "_addr(64)_id($id)", atom_g_add>;
- def ATOM64_G_AND : BinAtom64<IL_OP_UAV_READ_AND,
- "_addr(64)_id($id)", atom_g_and>;
- def ATOM64_G_MAX : BinAtom64<IL_OP_UAV_READ_MAX,
- "_addr(64)_id($id)", atom_g_max>;
- def ATOM64_G_MIN : BinAtom64<IL_OP_UAV_READ_MIN,
- "_addr(64)_id($id)", atom_g_min>;
- def ATOM64_G_UMAX : BinAtom64<IL_OP_UAV_READ_UMAX,
- "_addr(64)_id($id)", atom_g_umax>;
- def ATOM64_G_UMIN : BinAtom64<IL_OP_UAV_READ_UMIN,
- "_addr(64)_id($id)", atom_g_umin>;
- def ATOM64_G_OR : BinAtom64<IL_OP_UAV_READ_OR,
- "_addr(64)_id($id)", atom_g_or>;
- def ATOM64_G_RSUB : BinAtom64<IL_OP_UAV_READ_RSUB,
- "_addr(64)_id($id)", atom_g_rsub>;
- def ATOM64_G_SUB : BinAtom64<IL_OP_UAV_READ_SUB,
- "_addr(64)_id($id)", atom_g_sub>;
- def ATOM64_G_XOR : BinAtom64<IL_OP_UAV_READ_XOR,
- "_addr(64)_id($id)", atom_g_xor>;
- def ATOM64_G_INC : BinAtom64<IL_OP_UAV_READ_INC,
- "_addr(64)_id($id)", atom_g_inc>;
- def ATOM64_G_DEC : BinAtom64<IL_OP_UAV_READ_DEC,
- "_addr(64)_id($id)", atom_g_dec>;
- def ATOM64_G_XCHG : BinAtom64<IL_OP_UAV_READ_XCHG,
- "_addr(64)_id($id)", atom_g_xchg>;
- def ATOM64_G_CMPXCHG : CmpXChg64<IL_OP_UAV_READ_CMPXCHG,
- "_addr(64)_id($id)", atom_g_cmpxchg>;
- def ATOM64_L_ADD : BinAtom64<IL_OP_LDS_READ_ADD,
- "_id($id)", atom_l_add>;
- def ATOM64_L_AND : BinAtom64<IL_OP_LDS_READ_AND,
- "_id($id)", atom_l_and>;
- def ATOM64_L_MAX : BinAtom64<IL_OP_LDS_READ_MAX,
- "_id($id)", atom_l_max>;
- def ATOM64_L_MIN : BinAtom64<IL_OP_LDS_READ_MIN,
- "_id($id)", atom_l_min>;
- def ATOM64_L_UMAX : BinAtom64<IL_OP_LDS_READ_UMAX,
- "_id($id)", atom_l_umax>;
- def ATOM64_L_UMIN : BinAtom64<IL_OP_LDS_READ_UMIN,
- "_id($id)", atom_l_umin>;
- def ATOM64_L_OR : BinAtom64<IL_OP_LDS_READ_OR,
- "_id($id)", atom_l_or>;
- def ATOM64_L_MSKOR : TriAtom64<IL_OP_LDS_READ_MSKOR,
- "_id($id)", atom_l_mskor>;
- def ATOM64_L_RSUB : BinAtom64<IL_OP_LDS_READ_RSUB,
- "_id($id)", atom_l_rsub>;
- def ATOM64_L_SUB : BinAtom64<IL_OP_LDS_READ_SUB,
- "_id($id)", atom_l_sub>;
- def ATOM64_L_XOR : BinAtom64<IL_OP_LDS_READ_XOR,
- "_id($id)", atom_l_xor>;
- def ATOM64_L_INC : BinAtom64<IL_OP_LDS_READ_INC,
- "_id($id)", atom_l_inc>;
- def ATOM64_L_DEC : BinAtom64<IL_OP_LDS_READ_DEC,
- "_id($id)", atom_l_dec>;
- def ATOM64_L_XCHG : BinAtom64<IL_OP_LDS_READ_XCHG,
- "_id($id)", atom_l_xchg>;
- def ATOM64_L_CMPXCHG : TriAtom64<IL_OP_LDS_READ_CMPXCHG,
- "_id($id)", atom_l_cmpxchg>;
- def ATOM64_R_ADD : BinAtom64<IL_OP_GDS_READ_ADD,
- "_id($id)", atom_r_add>;
- def ATOM64_R_AND : BinAtom64<IL_OP_GDS_READ_AND,
- "_id($id)", atom_r_and>;
- def ATOM64_R_MAX : BinAtom64<IL_OP_GDS_READ_MAX,
- "_id($id)", atom_r_max>;
- def ATOM64_R_MIN : BinAtom64<IL_OP_GDS_READ_MIN,
- "_id($id)", atom_r_min>;
- def ATOM64_R_UMAX : BinAtom64<IL_OP_GDS_READ_UMAX,
- "_id($id)", atom_r_umax>;
- def ATOM64_R_UMIN : BinAtom64<IL_OP_GDS_READ_UMIN,
- "_id($id)", atom_r_umin>;
- def ATOM64_R_OR : BinAtom64<IL_OP_GDS_READ_OR,
- "_id($id)", atom_r_or>;
- def ATOM64_R_MSKOR : TriAtom64<IL_OP_GDS_READ_MSKOR,
- "_id($id)", atom_r_mskor>;
- def ATOM64_R_RSUB : BinAtom64<IL_OP_GDS_READ_RSUB,
- "_id($id)", atom_r_rsub>;
- def ATOM64_R_SUB : BinAtom64<IL_OP_GDS_READ_SUB,
- "_id($id)", atom_r_sub>;
- def ATOM64_R_XOR : BinAtom64<IL_OP_GDS_READ_XOR,
- "_id($id)", atom_r_xor>;
- def ATOM64_R_INC : BinAtom64<IL_OP_GDS_READ_INC,
- "_id($id)", atom_r_inc>;
- def ATOM64_R_DEC : BinAtom64<IL_OP_GDS_READ_DEC,
- "_id($id)", atom_r_dec>;
- def ATOM64_R_XCHG : BinAtom64<IL_OP_GDS_READ_XCHG,
- "_id($id)", atom_r_xchg>;
- def ATOM64_R_CMPXCHG : CmpXChg64<IL_OP_GDS_READ_CMPXCHG,
- "_id($id)", atom_r_cmpxchg>;
- // 64bit atomic operations.
- def ATOM64_G_ADD_NORET_B64 : BinAtomNoRet64I64<IL_OP_UAV_ADD,
- "_b64_addr(64)_id($id)", atom_g_add_noret>;
- def ATOM64_G_AND_NORET_B64 : BinAtomNoRet64I64<IL_OP_UAV_AND,
- "_b64_addr(64)_id($id)", atom_g_and_noret>;
- def ATOM64_G_MAX_NORET_B64 : BinAtomNoRet64I64<IL_OP_UAV_MAX,
- "_b64_addr(64)_id($id)", atom_g_max_noret>;
- def ATOM64_G_MIN_NORET_B64 : BinAtomNoRet64I64<IL_OP_UAV_MIN,
- "_b64_addr(64)_id($id)", atom_g_min_noret>;
- def ATOM64_G_UMAX_NORET_B64 : BinAtomNoRet64I64<IL_OP_UAV_UMAX,
- "_b64_addr(64)_id($id)", atom_g_umax_noret>;
- def ATOM64_G_UMIN_NORET_B64 : BinAtomNoRet64I64<IL_OP_UAV_UMIN,
- "_b64_addr(64)_id($id)", atom_g_umin_noret>;
- def ATOM64_G_OR_NORET_B64 : BinAtomNoRet64I64<IL_OP_UAV_OR,
- "_b64_addr(64)_id($id)", atom_g_or_noret>;
- def ATOM64_G_RSUB_NORET_B64 : BinAtomNoRet64I64<IL_OP_UAV_RSUB,
- "_b64_addr(64)_id($id)", atom_g_rsub_noret>;
- def ATOM64_G_SUB_NORET_B64 : BinAtomNoRet64I64<IL_OP_UAV_SUB,
- "_b64_addr(64)_id($id)", atom_g_sub_noret>;
- def ATOM64_G_XOR_NORET_B64 : BinAtomNoRet64I64<IL_OP_UAV_XOR,
- "_b64_addr(64)_id($id)", atom_g_xor_noret>;
- def ATOM64_G_INC_NORET_B64 : BinAtomNoRet64I64<IL_OP_UAV_INC,
- "_b64_addr(64)_id($id)", atom_g_inc_noret>;
- def ATOM64_G_DEC_NORET_B64 : BinAtomNoRet64I64<IL_OP_UAV_DEC,
- "_b64_addr(64)_id($id)", atom_g_dec_noret>;
- def ATOM64_G_CMPXCHG_NORET_B64 : CmpXChgNoRet64I64<IL_OP_UAV_CMP,
- "_b64_addr(64)_id($id)", atom_g_cmpxchg_noret>;
- def ATOM64_G_ADD_B64 : BinAtom64I64<IL_OP_UAV_READ_ADD,
- "_b64_addr(64)_id($id)", atom_g_add>;
- def ATOM64_G_AND_B64 : BinAtom64I64<IL_OP_UAV_READ_AND,
- "_b64_addr(64)_id($id)", atom_g_and>;
- def ATOM64_G_MAX_B64 : BinAtom64I64<IL_OP_UAV_READ_MAX,
- "_b64_addr(64)_id($id)", atom_g_max>;
- def ATOM64_G_MIN_B64 : BinAtom64I64<IL_OP_UAV_READ_MIN,
- "_b64_addr(64)_id($id)", atom_g_min>;
- def ATOM64_G_UMAX_B64 : BinAtom64I64<IL_OP_UAV_READ_UMAX,
- "_b64_addr(64)_id($id)", atom_g_umax>;
- def ATOM64_G_UMIN_B64 : BinAtom64I64<IL_OP_UAV_READ_UMIN,
- "_b64_addr(64)_id($id)", atom_g_umin>;
- def ATOM64_G_OR_B64 : BinAtom64I64<IL_OP_UAV_READ_OR,
- "_b64_addr(64)_id($id)", atom_g_or>;
- def ATOM64_G_RSUB_B64 : BinAtom64I64<IL_OP_UAV_READ_RSUB,
- "_b64_addr(64)_id($id)", atom_g_rsub>;
- def ATOM64_G_SUB_B64 : BinAtom64I64<IL_OP_UAV_READ_SUB,
- "_b64_addr(64)_id($id)", atom_g_sub>;
- def ATOM64_G_XOR_B64 : BinAtom64I64<IL_OP_UAV_READ_XOR,
- "_b64_addr(64)_id($id)", atom_g_xor>;
- def ATOM64_G_INC_B64 : BinAtom64I64<IL_OP_UAV_READ_INC,
- "_b64_addr(64)_id($id)", atom_g_inc>;
- def ATOM64_G_DEC_B64 : BinAtom64I64<IL_OP_UAV_READ_DEC,
- "_b64_addr(64)_id($id)", atom_g_dec>;
- def ATOM64_G_XCHG_B64 : BinAtom64I64<IL_OP_UAV_READ_XCHG,
- "_b64_addr(64)_id($id)", atom_g_xchg>;
- def ATOM64_G_CMPXCHG_B64 : CmpXChg64I64<IL_OP_UAV_READ_CMPXCHG,
- "_b64_addr(64)_id($id)", atom_g_cmpxchg>;
- def ATOM64_L_ADD_NORET_B64 : BinAtomNoRet64I64<IL_OP_LDS_ADD,
- "64_id($id)", atom_l_add_noret>;
- def ATOM64_L_AND_NORET_B64 : BinAtomNoRet64I64<IL_OP_LDS_AND,
- "64_id($id)", atom_l_and_noret>;
- def ATOM64_L_MAX_NORET_B64 : BinAtomNoRet64I64<IL_OP_LDS_MAX,
- "64_id($id)", atom_l_max_noret>;
- def ATOM64_L_MIN_NORET_B64 : BinAtomNoRet64I64<IL_OP_LDS_MIN,
- "64_id($id)", atom_l_min_noret>;
- def ATOM64_L_UMAX_NORET_B64 : BinAtomNoRet64I64<IL_OP_LDS_UMAX,
- "64_id($id)", atom_l_umax_noret>;
- def ATOM64_L_UMIN_NORET_B64 : BinAtomNoRet64I64<IL_OP_LDS_UMIN,
- "64_id($id)", atom_l_umin_noret>;
- def ATOM64_L_MSKOR_NORET_B64: TriAtomNoRet64I64<IL_OP_LDS_MSKOR,
- "64_id($id)", atom_l_mskor_noret>;
- def ATOM64_L_OR_NORET_B64 : BinAtomNoRet64I64<IL_OP_LDS_OR,
- "64_id($id)", atom_l_or_noret>;
- def ATOM64_L_RSUB_NORET_B64 : BinAtomNoRet64I64<IL_OP_LDS_RSUB,
- "64_id($id)", atom_l_rsub_noret>;
- def ATOM64_L_SUB_NORET_B64 : BinAtomNoRet64I64<IL_OP_LDS_SUB,
- "64_id($id)", atom_l_sub_noret>;
- def ATOM64_L_XOR_NORET_B64 : BinAtomNoRet64I64<IL_OP_LDS_XOR,
- "64_id($id)", atom_l_xor_noret>;
- def ATOM64_L_INC_NORET_B64 : BinAtomNoRet64I64<IL_OP_LDS_INC,
- "64_id($id)", atom_l_inc_noret>;
- def ATOM64_L_DEC_NORET_B64 : BinAtomNoRet64I64<IL_OP_LDS_DEC,
- "64_id($id)", atom_l_dec_noret>;
- def ATOM64_L_CMPXCHG_NORET_B64 : TriAtomNoRet64I64<IL_OP_LDS_CMP,
- "64_id($id)", atom_l_cmpxchg_noret>;
- def ATOM64_R_ADD_NORET_B64 : BinAtomNoRet64I64<IL_OP_GDS_ADD,
- "64_id($id)", atom_r_add_noret>;
- def ATOM64_R_AND_NORET_B64 : BinAtomNoRet64I64<IL_OP_GDS_AND,
- "64_id($id)", atom_r_and_noret>;
- def ATOM64_R_MAX_NORET_B64 : BinAtomNoRet64I64<IL_OP_GDS_MAX,
- "64_id($id)", atom_r_max_noret>;
- def ATOM64_R_MIN_NORET_B64 : BinAtomNoRet64I64<IL_OP_GDS_MIN,
- "64_id($id)", atom_r_min_noret>;
- def ATOM64_R_UMAX_NORET_B64 : BinAtomNoRet64I64<IL_OP_GDS_UMAX,
- "64_id($id)", atom_r_umax_noret>;
- def ATOM64_R_UMIN_NORET_B64 : BinAtomNoRet64I64<IL_OP_GDS_UMIN,
- "64_id($id)", atom_r_umin_noret>;
- def ATOM64_R_MSKOR_NORET_B64: TriAtomNoRet64I64<IL_OP_GDS_MSKOR,
- "64_id($id)", atom_r_mskor_noret>;
- def ATOM64_R_OR_NORET_B64 : BinAtomNoRet64I64<IL_OP_GDS_OR,
- "64_id($id)", atom_r_or_noret>;
- def ATOM64_R_RSUB_NORET_B64 : BinAtomNoRet64I64<IL_OP_GDS_RSUB,
- "64_id($id)", atom_r_rsub_noret>;
- def ATOM64_R_SUB_NORET_B64 : BinAtomNoRet64I64<IL_OP_GDS_SUB,
- "64_id($id)", atom_r_sub_noret>;
- def ATOM64_R_XOR_NORET_B64 : BinAtomNoRet64I64<IL_OP_GDS_XOR,
- "64_id($id)", atom_r_xor_noret>;
- def ATOM64_R_INC_NORET_B64 : BinAtomNoRet64I64<IL_OP_GDS_INC,
- "64_id($id)", atom_r_inc_noret>;
- def ATOM64_R_DEC_NORET_B64 : BinAtomNoRet64I64<IL_OP_GDS_DEC,
- "64_id($id)", atom_r_dec_noret>;
- def ATOM64_R_CMPXCHG_NORET_B64 : CmpXChgNoRet64I64<IL_OP_GDS_CMP,
- "64_id($id)", atom_r_cmpxchg_noret>;
- // All of the atomic functions that return
- def ATOM64_L_ADD_B64 : BinAtom64I64<IL_OP_LDS_READ_ADD,
- "64_id($id)", atom_l_add>;
- def ATOM64_L_AND_B64 : BinAtom64I64<IL_OP_LDS_READ_AND,
- "64_id($id)", atom_l_and>;
- def ATOM64_L_MAX_B64 : BinAtom64I64<IL_OP_LDS_READ_MAX,
- "64_id($id)", atom_l_max>;
- def ATOM64_L_MIN_B64 : BinAtom64I64<IL_OP_LDS_READ_MIN,
- "64_id($id)", atom_l_min>;
- def ATOM64_L_UMAX_B64 : BinAtom64I64<IL_OP_LDS_READ_UMAX,
- "64_id($id)", atom_l_umax>;
- def ATOM64_L_UMIN_B64 : BinAtom64I64<IL_OP_LDS_READ_UMIN,
- "64_id($id)", atom_l_umin>;
- def ATOM64_L_OR_B64 : BinAtom64I64<IL_OP_LDS_READ_OR,
- "64_id($id)", atom_l_or>;
- def ATOM64_L_MSKOR_B64 : TriAtom64I64<IL_OP_LDS_READ_MSKOR,
- "64_id($id)", atom_l_mskor>;
- def ATOM64_L_RSUB_B64 : BinAtom64I64<IL_OP_LDS_READ_RSUB,
- "64_id($id)", atom_l_rsub>;
- def ATOM64_L_SUB_B64 : BinAtom64I64<IL_OP_LDS_READ_SUB,
- "64_id($id)", atom_l_sub>;
- def ATOM64_L_XOR_B64 : BinAtom64I64<IL_OP_LDS_READ_XOR,
- "64_id($id)", atom_l_xor>;
- def ATOM64_L_INC_B64 : BinAtom64I64<IL_OP_LDS_READ_INC,
- "64_id($id)", atom_l_inc>;
- def ATOM64_L_DEC_B64 : BinAtom64I64<IL_OP_LDS_READ_DEC,
- "64_id($id)", atom_l_dec>;
- def ATOM64_L_XCHG_B64 : BinAtom64I64<IL_OP_LDS_READ_XCHG,
- "64_id($id)", atom_l_xchg>;
- def ATOM64_L_CMPXCHG_B64 : TriAtom64I64<IL_OP_LDS_READ_CMPXCHG,
- "64_id($id)", atom_l_cmpxchg>;
- def ATOM64_R_ADD_B64 : BinAtom64I64<IL_OP_GDS_READ_ADD,
- "64_id($id)", atom_r_add>;
- def ATOM64_R_AND_B64 : BinAtom64I64<IL_OP_GDS_READ_AND,
- "64_id($id)", atom_r_and>;
- def ATOM64_R_MAX_B64 : BinAtom64I64<IL_OP_GDS_READ_MAX,
- "64_id($id)", atom_r_max>;
- def ATOM64_R_MIN_B64 : BinAtom64I64<IL_OP_GDS_READ_MIN,
- "64_id($id)", atom_r_min>;
- def ATOM64_R_UMAX_B64 : BinAtom64I64<IL_OP_GDS_READ_UMAX,
- "64_id($id)", atom_r_umax>;
- def ATOM64_R_UMIN_B64 : BinAtom64I64<IL_OP_GDS_READ_UMIN,
- "64_id($id)", atom_r_umin>;
- def ATOM64_R_OR_B64 : BinAtom64I64<IL_OP_GDS_READ_OR,
- "64_id($id)", atom_r_or>;
- def ATOM64_R_MSKOR_B64 : TriAtom64I64<IL_OP_GDS_READ_MSKOR,
- "64_id($id)", atom_r_mskor>;
- def ATOM64_R_RSUB_B64 : BinAtom64I64<IL_OP_GDS_READ_RSUB,
- "64_id($id)", atom_r_rsub>;
- def ATOM64_R_SUB_B64 : BinAtom64I64<IL_OP_GDS_READ_SUB,
- "64_id($id)", atom_r_sub>;
- def ATOM64_R_XOR_B64 : BinAtom64I64<IL_OP_GDS_READ_XOR,
- "64_id($id)", atom_r_xor>;
- def ATOM64_R_INC_B64 : BinAtom64I64<IL_OP_GDS_READ_INC,
- "64_id($id)", atom_r_inc>;
- def ATOM64_R_DEC_B64 : BinAtom64I64<IL_OP_GDS_READ_DEC,
- "64_id($id)", atom_r_dec>;
- def ATOM64_R_XCHG_B64 : BinAtom64I64<IL_OP_GDS_READ_XCHG,
- "64_id($id)", atom_r_xchg>;
- def ATOM64_R_CMPXCHG_B64 : CmpXChg64I64<IL_OP_GDS_READ_CMPXCHG,
- "64_id($id)", atom_r_cmpxchg>;
-
- // atomic counter operations.
- def APPEND64_ALLOC : Append64<IL_OP_APPEND_BUF_ALLOC,
- "_id($id)", append_alloc>;
- def APPEND64_CONSUME : Append64<IL_OP_APPEND_BUF_CONSUME,
- "_id($id)", append_consume>;
+ let atomic = 1 in {
+ let global = 1 in {
+ def ATOM64_G_ADD_NORET : BinAtomNoRet64<IL_OP_UAV_ADD,
+ "_addr(64)_id($id)", atom_g_add_noret>;
+ def ATOM64_G_AND_NORET : BinAtomNoRet64<IL_OP_UAV_AND,
+ "_addr(64)_id($id)", atom_g_and_noret>;
+ def ATOM64_G_MAX_NORET : BinAtomNoRet64<IL_OP_UAV_MAX,
+ "_addr(64)_id($id)", atom_g_max_noret>;
+ def ATOM64_G_MIN_NORET : BinAtomNoRet64<IL_OP_UAV_MIN,
+ "_addr(64)_id($id)", atom_g_min_noret>;
+ def ATOM64_G_UMAX_NORET : BinAtomNoRet64<IL_OP_UAV_UMAX,
+ "_addr(64)_id($id)", atom_g_umax_noret>;
+ def ATOM64_G_UMIN_NORET : BinAtomNoRet64<IL_OP_UAV_UMIN,
+ "_addr(64)_id($id)", atom_g_umin_noret>;
+ def ATOM64_G_OR_NORET : BinAtomNoRet64<IL_OP_UAV_OR,
+ "_addr(64)_id($id)", atom_g_or_noret>;
+ def ATOM64_G_RSUB_NORET : BinAtomNoRet64<IL_OP_UAV_RSUB,
+ "_addr(64)_id($id)", atom_g_rsub_noret>;
+ def ATOM64_G_SUB_NORET : BinAtomNoRet64<IL_OP_UAV_SUB,
+ "_addr(64)_id($id)", atom_g_sub_noret>;
+ def ATOM64_G_XOR_NORET : BinAtomNoRet64<IL_OP_UAV_XOR,
+ "_addr(64)_id($id)", atom_g_xor_noret>;
+ def ATOM64_G_INC_NORET : BinAtomNoRet64<IL_OP_UAV_INC,
+ "_addr(64)_id($id)", atom_g_inc_noret>;
+ def ATOM64_G_DEC_NORET : BinAtomNoRet64<IL_OP_UAV_DEC,
+ "_addr(64)_id($id)", atom_g_dec_noret>;
+ def ATOM64_G_CMPXCHG_NORET : CmpXChgNoRet64<IL_OP_UAV_CMP,
+ "_addr(64)_id($id)", atom_g_cmpxchg_noret>;
+
+ // All of the atomic functions that return
+ def ATOM64_G_ADD : BinAtom64<IL_OP_UAV_READ_ADD,
+ "_addr(64)_id($id)", atom_g_add>;
+ def ATOM64_G_AND : BinAtom64<IL_OP_UAV_READ_AND,
+ "_addr(64)_id($id)", atom_g_and>;
+ def ATOM64_G_MAX : BinAtom64<IL_OP_UAV_READ_MAX,
+ "_addr(64)_id($id)", atom_g_max>;
+ def ATOM64_G_MIN : BinAtom64<IL_OP_UAV_READ_MIN,
+ "_addr(64)_id($id)", atom_g_min>;
+ def ATOM64_G_UMAX : BinAtom64<IL_OP_UAV_READ_UMAX,
+ "_addr(64)_id($id)", atom_g_umax>;
+ def ATOM64_G_UMIN : BinAtom64<IL_OP_UAV_READ_UMIN,
+ "_addr(64)_id($id)", atom_g_umin>;
+ def ATOM64_G_OR : BinAtom64<IL_OP_UAV_READ_OR,
+ "_addr(64)_id($id)", atom_g_or>;
+ def ATOM64_G_RSUB : BinAtom64<IL_OP_UAV_READ_RSUB,
+ "_addr(64)_id($id)", atom_g_rsub>;
+ def ATOM64_G_SUB : BinAtom64<IL_OP_UAV_READ_SUB,
+ "_addr(64)_id($id)", atom_g_sub>;
+ def ATOM64_G_XOR : BinAtom64<IL_OP_UAV_READ_XOR,
+ "_addr(64)_id($id)", atom_g_xor>;
+ def ATOM64_G_INC : BinAtom64<IL_OP_UAV_READ_INC,
+ "_addr(64)_id($id)", atom_g_inc>;
+ def ATOM64_G_DEC : BinAtom64<IL_OP_UAV_READ_DEC,
+ "_addr(64)_id($id)", atom_g_dec>;
+ def ATOM64_G_XCHG : BinAtom64<IL_OP_UAV_READ_XCHG,
+ "_addr(64)_id($id)", atom_g_xchg>;
+ def ATOM64_G_CMPXCHG : CmpXChg64<IL_OP_UAV_READ_CMPXCHG,
+ "_addr(64)_id($id)", atom_g_cmpxchg>;
+ def ATOM64_G_ADD_NORET_B64 : BinAtomNoRet64<IL_OP_UAV_ADD,
+ "_b64_addr(64)_id($id)", atom_g_add_noret>;
+ def ATOM64_G_AND_NORET_B64 : BinAtomNoRet64<IL_OP_UAV_AND,
+ "_b64_addr(64)_id($id)", atom_g_and_noret>;
+ def ATOM64_G_MAX_NORET_B64 : BinAtomNoRet64<IL_OP_UAV_MAX,
+ "_b64_addr(64)_id($id)", atom_g_max_noret>;
+ def ATOM64_G_MIN_NORET_B64 : BinAtomNoRet64<IL_OP_UAV_MIN,
+ "_b64_addr(64)_id($id)", atom_g_min_noret>;
+ def ATOM64_G_UMAX_NORET_B64 : BinAtomNoRet64<IL_OP_UAV_UMAX,
+ "_b64_addr(64)_id($id)", atom_g_umax_noret>;
+ def ATOM64_G_UMIN_NORET_B64 : BinAtomNoRet64<IL_OP_UAV_UMIN,
+ "_b64_addr(64)_id($id)", atom_g_umin_noret>;
+ def ATOM64_G_OR_NORET_B64 : BinAtomNoRet64<IL_OP_UAV_OR,
+ "_b64_addr(64)_id($id)", atom_g_or_noret>;
+ def ATOM64_G_RSUB_NORET_B64 : BinAtomNoRet64<IL_OP_UAV_RSUB,
+ "_b64_addr(64)_id($id)", atom_g_rsub_noret>;
+ def ATOM64_G_SUB_NORET_B64 : BinAtomNoRet64<IL_OP_UAV_SUB,
+ "_b64_addr(64)_id($id)", atom_g_sub_noret>;
+ def ATOM64_G_XOR_NORET_B64 : BinAtomNoRet64<IL_OP_UAV_XOR,
+ "_b64_addr(64)_id($id)", atom_g_xor_noret>;
+ def ATOM64_G_INC_NORET_B64 : BinAtomNoRet64<IL_OP_UAV_INC,
+ "_b64_addr(64)_id($id)", atom_g_inc_noret>;
+ def ATOM64_G_DEC_NORET_B64 : BinAtomNoRet64<IL_OP_UAV_DEC,
+ "_b64_addr(64)_id($id)", atom_g_dec_noret>;
+ def ATOM64_G_CMPXCHG_NORET_B64 : CmpXChgNoRet64<IL_OP_UAV_CMP,
+ "_b64_addr(64)_id($id)", atom_g_cmpxchg_noret>;
+ def ATOM64_G_ADD_B64 : BinAtom64I64<IL_OP_UAV_READ_ADD,
+ "_b64_addr(64)_id($id)", atom_g_add>;
+ def ATOM64_G_AND_B64 : BinAtom64I64<IL_OP_UAV_READ_AND,
+ "_b64_addr(64)_id($id)", atom_g_and>;
+ def ATOM64_G_MAX_B64 : BinAtom64I64<IL_OP_UAV_READ_MAX,
+ "_b64_addr(64)_id($id)", atom_g_max>;
+ def ATOM64_G_MIN_B64 : BinAtom64I64<IL_OP_UAV_READ_MIN,
+ "_b64_addr(64)_id($id)", atom_g_min>;
+ def ATOM64_G_UMAX_B64 : BinAtom64I64<IL_OP_UAV_READ_UMAX,
+ "_b64_addr(64)_id($id)", atom_g_umax>;
+ def ATOM64_G_UMIN_B64 : BinAtom64I64<IL_OP_UAV_READ_UMIN,
+ "_b64_addr(64)_id($id)", atom_g_umin>;
+ def ATOM64_G_OR_B64 : BinAtom64I64<IL_OP_UAV_READ_OR,
+ "_b64_addr(64)_id($id)", atom_g_or>;
+ def ATOM64_G_RSUB_B64 : BinAtom64I64<IL_OP_UAV_READ_RSUB,
+ "_b64_addr(64)_id($id)", atom_g_rsub>;
+ def ATOM64_G_SUB_B64 : BinAtom64I64<IL_OP_UAV_READ_SUB,
+ "_b64_addr(64)_id($id)", atom_g_sub>;
+ def ATOM64_G_XOR_B64 : BinAtom64I64<IL_OP_UAV_READ_XOR,
+ "_b64_addr(64)_id($id)", atom_g_xor>;
+ def ATOM64_G_INC_B64 : BinAtom64I64<IL_OP_UAV_READ_INC,
+ "_b64_addr(64)_id($id)", atom_g_inc>;
+ def ATOM64_G_DEC_B64 : BinAtom64I64<IL_OP_UAV_READ_DEC,
+ "_b64_addr(64)_id($id)", atom_g_dec>;
+ def ATOM64_G_XCHG_B64 : BinAtom64I64<IL_OP_UAV_READ_XCHG,
+ "_b64_addr(64)_id($id)", atom_g_xchg>;
+ def ATOM64_G_CMPXCHG_B64 : CmpXChg64I64<IL_OP_UAV_READ_CMPXCHG,
+ "_b64_addr(64)_id($id)", atom_g_cmpxchg>;
+ }
+ let local = 1 in {
+ def ATOM64_L_ADD_NORET : BinAtomNoRet64<IL_OP_LDS_ADD,
+ "_id($id)", atom_l_add_noret>;
+ def ATOM64_L_AND_NORET : BinAtomNoRet64<IL_OP_LDS_AND,
+ "_id($id)", atom_l_and_noret>;
+ def ATOM64_L_MAX_NORET : BinAtomNoRet64<IL_OP_LDS_MAX,
+ "_id($id)", atom_l_max_noret>;
+ def ATOM64_L_MIN_NORET : BinAtomNoRet64<IL_OP_LDS_MIN,
+ "_id($id)", atom_l_min_noret>;
+ def ATOM64_L_UMAX_NORET : BinAtomNoRet64<IL_OP_LDS_UMAX,
+ "_id($id)", atom_l_umax_noret>;
+ def ATOM64_L_UMIN_NORET : BinAtomNoRet64<IL_OP_LDS_UMIN,
+ "_id($id)", atom_l_umin_noret>;
+ def ATOM64_L_MSKOR_NORET : TriAtomNoRet64<IL_OP_LDS_MSKOR,
+ "_id($id)", atom_l_mskor_noret>;
+ def ATOM64_L_OR_NORET : BinAtomNoRet64<IL_OP_LDS_OR,
+ "_id($id)", atom_l_or_noret>;
+ def ATOM64_L_RSUB_NORET : BinAtomNoRet64<IL_OP_LDS_RSUB,
+ "_id($id)", atom_l_rsub_noret>;
+ def ATOM64_L_SUB_NORET : BinAtomNoRet64<IL_OP_LDS_SUB,
+ "_id($id)", atom_l_sub_noret>;
+ def ATOM64_L_XOR_NORET : BinAtomNoRet64<IL_OP_LDS_XOR,
+ "_id($id)", atom_l_xor_noret>;
+ def ATOM64_L_INC_NORET : BinAtomNoRet64<IL_OP_LDS_INC,
+ "_id($id)", atom_l_inc_noret>;
+ def ATOM64_L_DEC_NORET : BinAtomNoRet64<IL_OP_LDS_DEC,
+ "_id($id)", atom_l_dec_noret>;
+ def ATOM64_L_CMPXCHG_NORET : TriAtomNoRet64<IL_OP_LDS_CMP,
+ "_id($id)", atom_l_cmpxchg_noret>;
+ def ATOM64_L_ADD : BinAtom64<IL_OP_LDS_READ_ADD,
+ "_id($id)", atom_l_add>;
+ def ATOM64_L_AND : BinAtom64<IL_OP_LDS_READ_AND,
+ "_id($id)", atom_l_and>;
+ def ATOM64_L_MAX : BinAtom64<IL_OP_LDS_READ_MAX,
+ "_id($id)", atom_l_max>;
+ def ATOM64_L_MIN : BinAtom64<IL_OP_LDS_READ_MIN,
+ "_id($id)", atom_l_min>;
+ def ATOM64_L_UMAX : BinAtom64<IL_OP_LDS_READ_UMAX,
+ "_id($id)", atom_l_umax>;
+ def ATOM64_L_UMIN : BinAtom64<IL_OP_LDS_READ_UMIN,
+ "_id($id)", atom_l_umin>;
+ def ATOM64_L_OR : BinAtom64<IL_OP_LDS_READ_OR,
+ "_id($id)", atom_l_or>;
+ def ATOM64_L_MSKOR : TriAtom64<IL_OP_LDS_READ_MSKOR,
+ "_id($id)", atom_l_mskor>;
+ def ATOM64_L_RSUB : BinAtom64<IL_OP_LDS_READ_RSUB,
+ "_id($id)", atom_l_rsub>;
+ def ATOM64_L_SUB : BinAtom64<IL_OP_LDS_READ_SUB,
+ "_id($id)", atom_l_sub>;
+ def ATOM64_L_XOR : BinAtom64<IL_OP_LDS_READ_XOR,
+ "_id($id)", atom_l_xor>;
+ def ATOM64_L_INC : BinAtom64<IL_OP_LDS_READ_INC,
+ "_id($id)", atom_l_inc>;
+ def ATOM64_L_DEC : BinAtom64<IL_OP_LDS_READ_DEC,
+ "_id($id)", atom_l_dec>;
+ def ATOM64_L_XCHG : BinAtom64<IL_OP_LDS_READ_XCHG,
+ "_id($id)", atom_l_xchg>;
+ def ATOM64_L_CMPXCHG : TriAtom64<IL_OP_LDS_READ_CMPXCHG,
+ "_id($id)", atom_l_cmpxchg>;
+ def ATOM64_L_ADD_NORET_B64 : BinAtomNoRet64<IL_OP_LDS_ADD,
+ "64_id($id)", atom_l_add_noret>;
+ def ATOM64_L_AND_NORET_B64 : BinAtomNoRet64<IL_OP_LDS_AND,
+ "64_id($id)", atom_l_and_noret>;
+ def ATOM64_L_MAX_NORET_B64 : BinAtomNoRet64<IL_OP_LDS_MAX,
+ "64_id($id)", atom_l_max_noret>;
+ def ATOM64_L_MIN_NORET_B64 : BinAtomNoRet64<IL_OP_LDS_MIN,
+ "64_id($id)", atom_l_min_noret>;
+ def ATOM64_L_UMAX_NORET_B64 : BinAtomNoRet64<IL_OP_LDS_UMAX,
+ "64_id($id)", atom_l_umax_noret>;
+ def ATOM64_L_UMIN_NORET_B64 : BinAtomNoRet64<IL_OP_LDS_UMIN,
+ "64_id($id)", atom_l_umin_noret>;
+ def ATOM64_L_MSKOR_NORET_B64: TriAtomNoRet64<IL_OP_LDS_MSKOR,
+ "64_id($id)", atom_l_mskor_noret>;
+ def ATOM64_L_OR_NORET_B64 : BinAtomNoRet64<IL_OP_LDS_OR,
+ "64_id($id)", atom_l_or_noret>;
+ def ATOM64_L_RSUB_NORET_B64 : BinAtomNoRet64<IL_OP_LDS_RSUB,
+ "64_id($id)", atom_l_rsub_noret>;
+ def ATOM64_L_SUB_NORET_B64 : BinAtomNoRet64<IL_OP_LDS_SUB,
+ "64_id($id)", atom_l_sub_noret>;
+ def ATOM64_L_XOR_NORET_B64 : BinAtomNoRet64<IL_OP_LDS_XOR,
+ "64_id($id)", atom_l_xor_noret>;
+ def ATOM64_L_INC_NORET_B64 : BinAtomNoRet64<IL_OP_LDS_INC,
+ "64_id($id)", atom_l_inc_noret>;
+ def ATOM64_L_DEC_NORET_B64 : BinAtomNoRet64<IL_OP_LDS_DEC,
+ "64_id($id)", atom_l_dec_noret>;
+ def ATOM64_L_CMPXCHG_NORET_B64 : TriAtomNoRet64<IL_OP_LDS_CMP,
+ "64_id($id)", atom_l_cmpxchg_noret>;
+ def ATOM64_L_ADD_B64 : BinAtom64I64<IL_OP_LDS_READ_ADD,
+ "64_id($id)", atom_l_add>;
+ def ATOM64_L_AND_B64 : BinAtom64I64<IL_OP_LDS_READ_AND,
+ "64_id($id)", atom_l_and>;
+ def ATOM64_L_MAX_B64 : BinAtom64I64<IL_OP_LDS_READ_MAX,
+ "64_id($id)", atom_l_max>;
+ def ATOM64_L_MIN_B64 : BinAtom64I64<IL_OP_LDS_READ_MIN,
+ "64_id($id)", atom_l_min>;
+ def ATOM64_L_UMAX_B64 : BinAtom64I64<IL_OP_LDS_READ_UMAX,
+ "64_id($id)", atom_l_umax>;
+ def ATOM64_L_UMIN_B64 : BinAtom64I64<IL_OP_LDS_READ_UMIN,
+ "64_id($id)", atom_l_umin>;
+ def ATOM64_L_OR_B64 : BinAtom64I64<IL_OP_LDS_READ_OR,
+ "64_id($id)", atom_l_or>;
+ def ATOM64_L_MSKOR_B64 : TriAtom64I64<IL_OP_LDS_READ_MSKOR,
+ "64_id($id)", atom_l_mskor>;
+ def ATOM64_L_RSUB_B64 : BinAtom64I64<IL_OP_LDS_READ_RSUB,
+ "64_id($id)", atom_l_rsub>;
+ def ATOM64_L_SUB_B64 : BinAtom64I64<IL_OP_LDS_READ_SUB,
+ "64_id($id)", atom_l_sub>;
+ def ATOM64_L_XOR_B64 : BinAtom64I64<IL_OP_LDS_READ_XOR,
+ "64_id($id)", atom_l_xor>;
+ def ATOM64_L_INC_B64 : BinAtom64I64<IL_OP_LDS_READ_INC,
+ "64_id($id)", atom_l_inc>;
+ def ATOM64_L_DEC_B64 : BinAtom64I64<IL_OP_LDS_READ_DEC,
+ "64_id($id)", atom_l_dec>;
+ def ATOM64_L_XCHG_B64 : BinAtom64I64<IL_OP_LDS_READ_XCHG,
+ "64_id($id)", atom_l_xchg>;
+ def ATOM64_L_CMPXCHG_B64 : TriAtom64I64<IL_OP_LDS_READ_CMPXCHG,
+ "64_id($id)", atom_l_cmpxchg>;
+ }
+ let region = 1 in {
+ def ATOM64_R_ADD_NORET : BinAtomNoRet64<IL_OP_GDS_ADD,
+ "_id($id)", atom_r_add_noret>;
+ def ATOM64_R_AND_NORET : BinAtomNoRet64<IL_OP_GDS_AND,
+ "_id($id)", atom_r_and_noret>;
+ def ATOM64_R_MAX_NORET : BinAtomNoRet64<IL_OP_GDS_MAX,
+ "_id($id)", atom_r_max_noret>;
+ def ATOM64_R_MIN_NORET : BinAtomNoRet64<IL_OP_GDS_MIN,
+ "_id($id)", atom_r_min_noret>;
+ def ATOM64_R_UMAX_NORET : BinAtomNoRet64<IL_OP_GDS_UMAX,
+ "_id($id)", atom_r_umax_noret>;
+ def ATOM64_R_UMIN_NORET : BinAtomNoRet64<IL_OP_GDS_UMIN,
+ "_id($id)", atom_r_umin_noret>;
+ def ATOM64_R_MSKOR_NORET : TriAtomNoRet64<IL_OP_GDS_MSKOR,
+ "_id($id)", atom_r_mskor_noret>;
+ def ATOM64_R_OR_NORET : BinAtomNoRet64<IL_OP_GDS_OR,
+ "_id($id)", atom_r_or_noret>;
+ def ATOM64_R_RSUB_NORET : BinAtomNoRet64<IL_OP_GDS_RSUB,
+ "_id($id)", atom_r_rsub_noret>;
+ def ATOM64_R_SUB_NORET : BinAtomNoRet64<IL_OP_GDS_SUB,
+ "_id($id)", atom_r_sub_noret>;
+ def ATOM64_R_XOR_NORET : BinAtomNoRet64<IL_OP_GDS_XOR,
+ "_id($id)", atom_r_xor_noret>;
+ def ATOM64_R_INC_NORET : BinAtomNoRet64<IL_OP_GDS_INC,
+ "_id($id)", atom_r_inc_noret>;
+ def ATOM64_R_DEC_NORET : BinAtomNoRet64<IL_OP_GDS_DEC,
+ "_id($id)", atom_r_dec_noret>;
+ def ATOM64_R_CMPXCHG_NORET : TriAtomNoRet64<IL_OP_GDS_CMP,
+ "_id($id)", atom_r_cmpxchg_noret>;
+ def ATOM64_R_ADD : BinAtom64<IL_OP_GDS_READ_ADD,
+ "_id($id)", atom_r_add>;
+ def ATOM64_R_AND : BinAtom64<IL_OP_GDS_READ_AND,
+ "_id($id)", atom_r_and>;
+ def ATOM64_R_MAX : BinAtom64<IL_OP_GDS_READ_MAX,
+ "_id($id)", atom_r_max>;
+ def ATOM64_R_MIN : BinAtom64<IL_OP_GDS_READ_MIN,
+ "_id($id)", atom_r_min>;
+ def ATOM64_R_UMAX : BinAtom64<IL_OP_GDS_READ_UMAX,
+ "_id($id)", atom_r_umax>;
+ def ATOM64_R_UMIN : BinAtom64<IL_OP_GDS_READ_UMIN,
+ "_id($id)", atom_r_umin>;
+ def ATOM64_R_OR : BinAtom64<IL_OP_GDS_READ_OR,
+ "_id($id)", atom_r_or>;
+ def ATOM64_R_MSKOR : TriAtom64<IL_OP_GDS_READ_MSKOR,
+ "_id($id)", atom_r_mskor>;
+ def ATOM64_R_RSUB : BinAtom64<IL_OP_GDS_READ_RSUB,
+ "_id($id)", atom_r_rsub>;
+ def ATOM64_R_SUB : BinAtom64<IL_OP_GDS_READ_SUB,
+ "_id($id)", atom_r_sub>;
+ def ATOM64_R_XOR : BinAtom64<IL_OP_GDS_READ_XOR,
+ "_id($id)", atom_r_xor>;
+ def ATOM64_R_INC : BinAtom64<IL_OP_GDS_READ_INC,
+ "_id($id)", atom_r_inc>;
+ def ATOM64_R_DEC : BinAtom64<IL_OP_GDS_READ_DEC,
+ "_id($id)", atom_r_dec>;
+ def ATOM64_R_XCHG : BinAtom64<IL_OP_GDS_READ_XCHG,
+ "_id($id)", atom_r_xchg>;
+ def ATOM64_R_CMPXCHG : TriAtom64<IL_OP_GDS_READ_CMPXCHG,
+ "_id($id)", atom_r_cmpxchg>;
+ def ATOM64_R_ADD_NORET_B64 : BinAtomNoRet64<IL_OP_GDS_ADD,
+ "64_id($id)", atom_r_add_noret>;
+ def ATOM64_R_AND_NORET_B64 : BinAtomNoRet64<IL_OP_GDS_AND,
+ "64_id($id)", atom_r_and_noret>;
+ def ATOM64_R_MAX_NORET_B64 : BinAtomNoRet64<IL_OP_GDS_MAX,
+ "64_id($id)", atom_r_max_noret>;
+ def ATOM64_R_MIN_NORET_B64 : BinAtomNoRet64<IL_OP_GDS_MIN,
+ "64_id($id)", atom_r_min_noret>;
+ def ATOM64_R_UMAX_NORET_B64 : BinAtomNoRet64<IL_OP_GDS_UMAX,
+ "64_id($id)", atom_r_umax_noret>;
+ def ATOM64_R_UMIN_NORET_B64 : BinAtomNoRet64<IL_OP_GDS_UMIN,
+ "64_id($id)", atom_r_umin_noret>;
+ def ATOM64_R_MSKOR_NORET_B64: TriAtomNoRet64<IL_OP_GDS_MSKOR,
+ "64_id($id)", atom_r_mskor_noret>;
+ def ATOM64_R_OR_NORET_B64 : BinAtomNoRet64<IL_OP_GDS_OR,
+ "64_id($id)", atom_r_or_noret>;
+ def ATOM64_R_RSUB_NORET_B64 : BinAtomNoRet64<IL_OP_GDS_RSUB,
+ "64_id($id)", atom_r_rsub_noret>;
+ def ATOM64_R_SUB_NORET_B64 : BinAtomNoRet64<IL_OP_GDS_SUB,
+ "64_id($id)", atom_r_sub_noret>;
+ def ATOM64_R_XOR_NORET_B64 : BinAtomNoRet64<IL_OP_GDS_XOR,
+ "64_id($id)", atom_r_xor_noret>;
+ def ATOM64_R_INC_NORET_B64 : BinAtomNoRet64<IL_OP_GDS_INC,
+ "64_id($id)", atom_r_inc_noret>;
+ def ATOM64_R_DEC_NORET_B64 : BinAtomNoRet64<IL_OP_GDS_DEC,
+ "64_id($id)", atom_r_dec_noret>;
+ def ATOM64_R_CMPXCHG_NORET_B64 : TriAtomNoRet64<IL_OP_GDS_CMP,
+ "64_id($id)", atom_r_cmpxchg_noret>;
+ def ATOM64_R_ADD_B64 : BinAtom64I64<IL_OP_GDS_READ_ADD,
+ "64_id($id)", atom_r_add>;
+ def ATOM64_R_AND_B64 : BinAtom64I64<IL_OP_GDS_READ_AND,
+ "64_id($id)", atom_r_and>;
+ def ATOM64_R_MAX_B64 : BinAtom64I64<IL_OP_GDS_READ_MAX,
+ "64_id($id)", atom_r_max>;
+ def ATOM64_R_MIN_B64 : BinAtom64I64<IL_OP_GDS_READ_MIN,
+ "64_id($id)", atom_r_min>;
+ def ATOM64_R_UMAX_B64 : BinAtom64I64<IL_OP_GDS_READ_UMAX,
+ "64_id($id)", atom_r_umax>;
+ def ATOM64_R_UMIN_B64 : BinAtom64I64<IL_OP_GDS_READ_UMIN,
+ "64_id($id)", atom_r_umin>;
+ def ATOM64_R_OR_B64 : BinAtom64I64<IL_OP_GDS_READ_OR,
+ "64_id($id)", atom_r_or>;
+ def ATOM64_R_MSKOR_B64 : TriAtom64I64<IL_OP_GDS_READ_MSKOR,
+ "64_id($id)", atom_r_mskor>;
+ def ATOM64_R_RSUB_B64 : BinAtom64I64<IL_OP_GDS_READ_RSUB,
+ "64_id($id)", atom_r_rsub>;
+ def ATOM64_R_SUB_B64 : BinAtom64I64<IL_OP_GDS_READ_SUB,
+ "64_id($id)", atom_r_sub>;
+ def ATOM64_R_XOR_B64 : BinAtom64I64<IL_OP_GDS_READ_XOR,
+ "64_id($id)", atom_r_xor>;
+ def ATOM64_R_INC_B64 : BinAtom64I64<IL_OP_GDS_READ_INC,
+ "64_id($id)", atom_r_inc>;
+ def ATOM64_R_DEC_B64 : BinAtom64I64<IL_OP_GDS_READ_DEC,
+ "64_id($id)", atom_r_dec>;
+ def ATOM64_R_XCHG_B64 : BinAtom64I64<IL_OP_GDS_READ_XCHG,
+ "64_id($id)", atom_r_xchg>;
+ def ATOM64_R_CMPXCHG_B64 : TriAtom64I64<IL_OP_GDS_READ_CMPXCHG,
+ "64_id($id)", atom_r_cmpxchg>;
+ }
+ }
+
+ let append = 1, swizzle = 1 in {
+ def APPEND64_ALLOC : Append64<IL_OP_APPEND_BUF_ALLOC,
+ "_id($id)", append_alloc>;
+ def APPEND64_CONSUME : Append64<IL_OP_APPEND_BUF_CONSUME,
+ "_id($id)", append_consume>;
+ }
+ let sema = 1 in {
+ let swizzle = 7 in {
+ def SEMAPHORE64_WAIT : ILFormat<IL_OP_SEMAPHORE_WAIT, (outs),
+ (ins MEM3232:$ptr),
+ !strconcat(IL_OP_SEMAPHORE_WAIT.Text, "_id($ptr)"),
+ [(int_AMDIL_semaphore_wait ADDR:$ptr)]>;
+
+ def SEMAPHORE64_SIGNAL : ILFormat<IL_OP_SEMAPHORE_SIGNAL, (outs),
+ (ins MEM3232:$ptr),
+ !strconcat(IL_OP_SEMAPHORE_SIGNAL.Text, "_id($ptr)"),
+ [(int_AMDIL_semaphore_signal ADDR:$ptr)]>;
+ }
+ }
+
+ let Predicates = [IsSIOrLaterDevice] in {
+ let addr64 = 1 in {
+ // atomic global load
+ defm ATOM64_G_LOAD : AtomGLoadMC<MEM6464, ADDR64>;
+ // atomic global store
+ defm ATOM64_G_STORE : AtomGStoreMC<MEM6464, ADDR64>;
+ }
+ }
+
}
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILModuleInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILModuleInfo.cpp?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILModuleInfo.cpp (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILModuleInfo.cpp Wed Sep 12 12:43:34 2012
@@ -27,16 +27,12 @@
using namespace llvm;
-static inline uint32_t AlignDown_32(uint32_t Value, uint32_t Alignment)
-{
+static inline uint32_t AlignDown_32(uint32_t Value, uint32_t Alignment) {
return Value & ~(Alignment - 1);
}
-
-static inline uint32_t AlignUp_32(uint32_t Value, uint32_t Alignment)
-{
+static inline uint32_t AlignUp_32(uint32_t Value, uint32_t Alignment) {
return AlignDown_32(Value + Alignment - 1, Alignment);
}
-
AMDILModuleInfo::AMDILModuleInfo(const MachineModuleInfo &MMI)
: mMMI(&MMI),
symTab(NULL),
@@ -46,24 +42,26 @@
mReservedBuffs(0),
mCurrentCPOffset(0),
mPrintfOffset(0),
- mProcessed(false) { }
+ mNumLocalBuffers(1),
+ mProcessed(false) {
+}
-AMDILModuleInfo::~AMDILModuleInfo()
-{
- for (StringMap<AMDILKernel*>::iterator kb = mKernels.begin(), ke = mKernels.end();
+AMDILModuleInfo::~AMDILModuleInfo() {
+ for (StringMap<AMDILKernel*>::iterator kb = mKernels.begin(),
+ ke = mKernels.end();
kb != ke; ++kb) {
StringMapEntry<AMDILKernel*> cur = *kb;
AMDILKernel *ptr = cur.getValue();
delete ptr;
}
}
-
-static const AMDILConstPtr *getConstPtr(const AMDILKernel *krnl, const std::string &arg)
-{
+static const AMDILConstPtr *getConstPtr(const AMDILKernel *krnl,
+ const std::string &arg) {
if (!krnl) {
return NULL;
}
- llvm::SmallVector<AMDILConstPtr, DEFAULT_VEC_SLOTS>::const_iterator begin, end;
+ llvm::SmallVector<AMDILConstPtr,
+ DEFAULT_VEC_SLOTS>::const_iterator begin, end;
for (begin = krnl->constPtr.begin(), end = krnl->constPtr.end();
begin != end; ++begin) {
if (!strcmp(begin->name.data(),arg.c_str())) {
@@ -72,10 +70,8 @@
}
return NULL;
}
-
void AMDILModuleInfo::processModule(const Module *M,
- const AMDILTargetMachine *mTM)
-{
+ const AMDILTargetMachine *mTM) {
Module::const_global_iterator GI;
Module::const_global_iterator GE;
mSTM = mTM->getSubtargetImpl();
@@ -94,7 +90,8 @@
} else if (!strncmp(name, "fgv", 3)) {
// we can ignore this since we don't care about the filename
// string
- } else if ((name[0] == 'l' || name[0] == 'r') && !strncmp(name + 1, "vgv", 3)) {
+ } else if ((name[0] == 'l' ||
+ name[0] == 'r') && !strncmp(name + 1, "vgv", 3)) {
// "lvgv" or "rvgv"
mLocalArgs[GVName] = parseXVGV(GV);
} else if (!strncmp(name, "llvm.image.annotations", 22)) {
@@ -137,9 +134,7 @@
// is called everytime a MachineFunctionInfo object is instantiated.
mProcessed = true;
}
-
-void AMDILModuleInfo::allocateGlobalCB(void)
-{
+void AMDILModuleInfo::allocateGlobalCB(void) {
uint32_t maxCBSize = mSTM->device()->getMaxCBSize();
uint32_t offset = 0;
uint32_t curCB = 0;
@@ -176,9 +171,7 @@
mReservedBuffs = curCB + 1;
}
}
-
-bool AMDILModuleInfo::checkConstPtrsUseHW(llvm::Module::const_iterator *FCI)
-{
+bool AMDILModuleInfo::checkConstPtrsUseHW(llvm::Module::const_iterator *FCI) {
Function::const_arg_iterator AI, AE;
const Function *func = *FCI;
std::string name = func->getName();
@@ -268,9 +261,7 @@
}
return false;
}
-
-int32_t AMDILModuleInfo::getArrayOffset(const llvm::StringRef &a) const
-{
+int32_t AMDILModuleInfo::getArrayOffset(const llvm::StringRef &a) const {
StringMap<AMDILArrayMem>::const_iterator iter = mArrayMems.find(a);
if (iter != mArrayMems.end()) {
return iter->second.offset;
@@ -278,9 +269,7 @@
return -1;
}
}
-
-int32_t AMDILModuleInfo::getConstOffset(const llvm::StringRef &a) const
-{
+int32_t AMDILModuleInfo::getConstOffset(const llvm::StringRef &a) const {
StringMap<AMDILConstPtr>::const_iterator iter = mConstMems.find(a);
if (iter != mConstMems.end()) {
return iter->second.offset;
@@ -288,9 +277,7 @@
return -1;
}
}
-
-bool AMDILModuleInfo::getConstHWBit(const llvm::StringRef &name) const
-{
+bool AMDILModuleInfo::getConstHWBit(const llvm::StringRef &name) const {
StringMap<AMDILConstPtr>::const_iterator iter = mConstMems.find(name);
if (iter != mConstMems.end()) {
return iter->second.usesHardware;
@@ -298,11 +285,9 @@
return false;
}
}
-
// As of right now we only care about the required group size
// so we can skip the variable encoding
-AMDILKernelAttr AMDILModuleInfo::parseSGV(const GlobalValue *G)
-{
+AMDILKernelAttr AMDILModuleInfo::parseSGV(const GlobalValue *G) {
AMDILKernelAttr nArg;
const GlobalVariable *GV = dyn_cast<GlobalVariable>(G);
memset(&nArg, 0, sizeof(nArg));
@@ -324,7 +309,7 @@
pos += 3;
std::string LWS = init.substr(pos, init.length() - pos);
const char *lws = LWS.c_str();
- sscanf(lws, "%u,%u,%u", &(nArg.reqGroupSize[0]),
+ sscanf(lws, "%d,%d,%d", &(nArg.reqGroupSize[0]),
&(nArg.reqGroupSize[1]),
&(nArg.reqGroupSize[2]));
nArg.mHasRWG = true;
@@ -334,16 +319,14 @@
pos += 3;
std::string LWS = init.substr(pos, init.length() - pos);
const char *lws = LWS.c_str();
- sscanf(lws, "%u,%u,%u", &(nArg.reqRegionSize[0]),
+ sscanf(lws, "%d,%d,%d", &(nArg.reqRegionSize[0]),
&(nArg.reqRegionSize[1]),
&(nArg.reqRegionSize[2]));
nArg.mHasRWR = true;
}
return nArg;
}
-
-AMDILLocalArg AMDILModuleInfo::parseXVGV(const GlobalValue *G)
-{
+AMDILLocalArg AMDILModuleInfo::parseXVGV(const GlobalValue *G) {
AMDILLocalArg nArg;
const GlobalVariable *GV = dyn_cast<GlobalVariable>(G);
nArg.name = "";
@@ -368,7 +351,6 @@
}
return nArg;
}
-
void AMDILModuleInfo::parseSamplerAnnotate(const GlobalValue *G)
{
const GlobalVariable *GV = dyn_cast_or_null<GlobalVariable>(G);
@@ -395,10 +377,8 @@
// and don't generate code/metadata for strings that are never used.
mConstMems.erase(mConstMems.find(nameGV->getName()));
}
-
}
}
-
void AMDILModuleInfo::parseIgnoredGlobal(const GlobalValue *G)
{
const GlobalVariable *GV = dyn_cast_or_null<GlobalVariable>(G);
@@ -423,15 +403,13 @@
}
}
}
-
std::set<std::string> *
AMDILModuleInfo::getSamplerForKernel(llvm::StringRef &ref)
{
- return (mSamplerSet.find(ref) != mSamplerSet.end()) ? &mSamplerSet[ref] : NULL;
+ return (mSamplerSet.find(ref) !=
+ mSamplerSet.end()) ? &mSamplerSet[ref] : NULL;
}
-
-void AMDILModuleInfo::parseConstantPtrAnnotate(const GlobalValue *G)
-{
+void AMDILModuleInfo::parseConstantPtrAnnotate(const GlobalValue *G) {
const GlobalVariable *GV = dyn_cast_or_null<GlobalVariable>(G);
const ConstantArray *CA =
dyn_cast_or_null<ConstantArray>(GV->getInitializer());
@@ -491,9 +469,7 @@
mKernels[AMDILKernelName] = k;
}
}
-
-void AMDILModuleInfo::parseImageAnnotate(const GlobalValue *G)
-{
+void AMDILModuleInfo::parseImageAnnotate(const GlobalValue *G) {
const GlobalVariable *GV = dyn_cast<GlobalVariable>(G);
const ConstantArray *CA = dyn_cast<ConstantArray>(GV->getInitializer());
if (!CA) {
@@ -544,11 +520,10 @@
}
mKernels[name] = k;
}
-
-void AMDILModuleInfo::parseAutoArray(const GlobalValue *GV, bool isRegion)
-{
+void AMDILModuleInfo::parseAutoArray(const GlobalValue *GV, bool isRegion) {
const GlobalVariable *G = dyn_cast<GlobalVariable>(GV);
AMDILArrayMem tmp;
+ tmp.base = GV;
tmp.isHW = true;
tmp.offset = 0;
tmp.align = std::max(G->getAlignment(), 16U);
@@ -564,11 +539,10 @@
tmp.vecSize = TM->getTargetData()->getTypeAllocSize(ty);
}
tmp.isRegion = isRegion;
+ tmp.resourceID = 0;
mArrayMems[GV->getName()] = tmp;
}
-
-void AMDILModuleInfo::parseConstantPtr(const GlobalValue *GV)
-{
+void AMDILModuleInfo::parseConstantPtr(const GlobalValue *GV) {
const GlobalVariable *G = dyn_cast<GlobalVariable>(GV);
AMDILConstPtr constAttr;
constAttr.name = G->getName();
@@ -592,9 +566,7 @@
constAttr.usesHardware = false;
mConstMems[GV->getName()] = constAttr;
}
-
-void AMDILModuleInfo::parseGlobalAnnotate(const GlobalValue *G)
-{
+void AMDILModuleInfo::parseGlobalAnnotate(const GlobalValue *G) {
const GlobalVariable *GV = dyn_cast<GlobalVariable>(G);
if (!GV->hasInitializer()) {
return;
@@ -613,9 +585,8 @@
parseKernelInformation(CA->getOperand(i));
}
}
-
-AMDILLocalArg* AMDILModuleInfo::parseKernelLRInfo(AMDILKernel *kernel, const Constant *CV)
-{
+AMDILLocalArg* AMDILModuleInfo::parseKernelLRInfo(AMDILKernel *kernel,
+ const Constant *CV) {
llvm::StringRef xvgvName = ""; // lvgv or rvgv
assert(CV);
@@ -639,6 +610,8 @@
curSize = (a->isHW) ? &kernel->curHWRSize : &kernel->curRSize;
} else {
curSize = (a->isHW) ? &kernel->curHWSize : &kernel->curSize;
+ // by default all local arrays are allocated in the default local buffer
+ a->resourceID = mSTM->device()->getResourceID(AMDILDevice::LDS_ID);
}
a->offset = AlignUp_32(*curSize, a->align);
*curSize = a->offset + a->vecSize;
@@ -647,9 +620,7 @@
return ptr;
}
-
-void AMDILModuleInfo::parseKernelInformation(const Value *V)
-{
+void AMDILModuleInfo::parseKernelInformation(const Value *V) {
if (isa<GlobalValue>(V)) {
return;
}
@@ -692,7 +663,6 @@
kernel->sgv = &mKernelArgs[sgvName];
}
-
// The third operand is FGV, which is skipped
// The fourth operand is LVGV
@@ -700,17 +670,16 @@
// The possibly missing (e.g. on Apple) fifth operand is RVGV
if (N >= 5) {
- kernel->rvgv = parseKernelLRInfo(kernel, dyn_cast<Constant>(CS->getOperand(4)));
+ kernel->rvgv =
+ parseKernelLRInfo(kernel, dyn_cast<Constant>(CS->getOperand(4)));
}
// The last (fifth or sixth) operand is NULL
mKernels[AMDILKernelName] = kernel;
}
-
AMDILKernel *
-AMDILModuleInfo::getKernel(const llvm::StringRef &name)
-{
+AMDILModuleInfo::getKernel(const llvm::StringRef &name) {
StringMap<AMDILKernel*>::iterator iter = mKernels.find(name);
if (iter == mKernels.end()) {
return NULL;
@@ -718,34 +687,26 @@
return iter->second;
}
}
-
-bool AMDILModuleInfo::isKernel(const llvm::StringRef &name) const
-{
+bool AMDILModuleInfo::isKernel(const llvm::StringRef &name) const {
return (mKernels.find(name) != mKernels.end());
}
-
bool AMDILModuleInfo::isWriteOnlyImage(const llvm::StringRef &name,
- uint32_t iID) const
-{
+ uint32_t iID) const {
const StringMap<AMDILKernel*>::const_iterator kiter = mKernels.find(name);
if (kiter == mKernels.end()) {
return false;
}
return kiter->second->writeOnly.count(iID);
}
-
bool AMDILModuleInfo::isReadOnlyImage(const llvm::StringRef &name,
- uint32_t iID) const
-{
+ uint32_t iID) const {
const StringMap<AMDILKernel*>::const_iterator kiter = mKernels.find(name);
if (kiter == mKernels.end()) {
return false;
}
return kiter->second->readOnly.count(iID);
}
-
-int32_t AMDILModuleInfo::getArgID(const Argument *arg)
-{
+int32_t AMDILModuleInfo::getArgID(const Argument *arg) {
DenseMap<const Argument *, int32_t>::iterator argiter = mArgIDMap.find(arg);
if (argiter != mArgIDMap.end()) {
return argiter->second;
@@ -753,16 +714,13 @@
return -1;
}
}
-
uint32_t
-AMDILModuleInfo::getRegion(const llvm::StringRef &name, uint32_t dim) const
-{
+AMDILModuleInfo::getRegion(const llvm::StringRef &name, uint32_t dim) const {
StringMap<AMDILKernel*>::const_iterator iter = mKernels.find(name);
if (iter != mKernels.end() && iter->second->sgv) {
AMDILKernelAttr *sgv = iter->second->sgv;
switch (dim) {
- default:
- break;
+ default: break;
case 0:
case 1:
case 2:
@@ -789,40 +747,28 @@
};
return 1;
}
-
-StringMap<AMDILConstPtr>::iterator AMDILModuleInfo::consts_begin()
-{
+StringMap<AMDILConstPtr>::iterator AMDILModuleInfo::consts_begin() {
return mConstMems.begin();
}
-
-
-StringMap<AMDILConstPtr>::iterator AMDILModuleInfo::consts_end()
-{
+StringMap<AMDILConstPtr>::iterator AMDILModuleInfo::consts_end() {
return mConstMems.end();
}
-
-bool AMDILModuleInfo::consts_empty()
-{
+bool AMDILModuleInfo::consts_empty() {
return mConstMems.empty();
}
-
-bool AMDILModuleInfo::byteStoreExists(StringRef S) const
-{
+bool AMDILModuleInfo::byteStoreExists(StringRef S) const {
return mByteStore.find(S) != mByteStore.end();
}
-
bool AMDILModuleInfo::usesHWConstant(const AMDILKernel *krnl,
- const llvm::StringRef &arg)
-{
+ const llvm::StringRef &arg) {
const AMDILConstPtr *curConst = getConstPtr(krnl, arg);
if (!curConst) {
return false;
}
return curConst->usesHardware;
}
-
uint32_t AMDILModuleInfo::getConstPtrSize(const AMDILKernel *krnl,
- const llvm::StringRef &arg)
+ const llvm::StringRef &arg)
{
const AMDILConstPtr *curConst = getConstPtr(krnl, arg);
if (!curConst) {
@@ -830,9 +776,8 @@
}
return curConst->size;
}
-
uint32_t AMDILModuleInfo::getConstPtrOff(const AMDILKernel *krnl,
- const llvm::StringRef &arg)
+ const llvm::StringRef &arg)
{
const AMDILConstPtr *curConst = getConstPtr(krnl, arg);
if (!curConst) {
@@ -840,20 +785,16 @@
}
return curConst->offset;
}
-
uint32_t AMDILModuleInfo::getConstPtrCB(const AMDILKernel *krnl,
- const llvm::StringRef &arg)
-{
+ const llvm::StringRef &arg) {
const AMDILConstPtr *curConst = getConstPtr(krnl, arg);
if (!curConst) {
return 0;
}
return curConst->cbNum;
}
-
void AMDILModuleInfo::calculateCPOffsets(const MachineFunction *MF,
- AMDILKernel *krnl)
-{
+ AMDILKernel *krnl) {
const MachineConstantPool *MCP = MF->getConstantPool();
if (!MCP) {
return;
@@ -882,10 +823,8 @@
mCurrentCPOffset += curSize;
}
}
-
bool AMDILModuleInfo::isConstPtrArray(const AMDILKernel *krnl,
- const llvm::StringRef &arg)
-{
+ const llvm::StringRef &arg) {
const AMDILConstPtr *curConst = getConstPtr(krnl, arg);
if (curConst) {
return curConst->isArray;
@@ -893,10 +832,8 @@
return false;
}
}
-
bool AMDILModuleInfo::isConstPtrArgument(const AMDILKernel *krnl,
- const llvm::StringRef &arg)
-{
+ const llvm::StringRef &arg) {
const AMDILConstPtr *curConst = getConstPtr(krnl, arg);
if (curConst) {
return curConst->isArgument;
@@ -904,10 +841,8 @@
return false;
}
}
-
const Value *AMDILModuleInfo::getConstPtrValue(const AMDILKernel *krnl,
- const llvm::StringRef &arg)
-{
+ const llvm::StringRef &arg) {
const AMDILConstPtr *curConst = getConstPtr(krnl, arg);
if (curConst) {
return curConst->base;
@@ -915,7 +850,6 @@
return NULL;
}
}
-
static void
dumpZeroElements(StructType * const T, OSTREAM_TYPE &O, bool asBytes);
static void
@@ -927,8 +861,7 @@
static void
dumpZeroElements(Type * const T, OSTREAM_TYPE &O, bool asBytes);
-void dumpZeroElements(Type * const T, OSTREAM_TYPE &O, bool asBytes)
-{
+void dumpZeroElements(Type * const T, OSTREAM_TYPE &O, bool asBytes) {
if (!T) {
return;
}
@@ -954,14 +887,16 @@
} else {
O << ":0";
}
+ break;
case Type::IntegerTyID:
dumpZeroElements(dyn_cast<IntegerType>(T), O, asBytes);
break;
- case Type::StructTyID: {
+ case Type::StructTyID:
+ {
const StructType *ST = cast<StructType>(T);
if (!ST->isOpaque()) {
dumpZeroElements(dyn_cast<StructType>(T), O, asBytes);
- } else { // A pre-LLVM 3.0 opaque type
+ } else { // A pre-LLVM 3.0 opaque type
if (asBytes) {
O << ":0:0:0:0";
} else {
@@ -978,10 +913,8 @@
break;
};
}
-
void
-dumpZeroElements(StructType * const ST, OSTREAM_TYPE &O, bool asBytes)
-{
+dumpZeroElements(StructType * const ST, OSTREAM_TYPE &O, bool asBytes) {
if (!ST) {
return;
}
@@ -993,10 +926,8 @@
dumpZeroElements(curType, O, asBytes);
}
}
-
void
-dumpZeroElements(IntegerType * const IT, OSTREAM_TYPE &O, bool asBytes)
-{
+dumpZeroElements(IntegerType * const IT, OSTREAM_TYPE &O, bool asBytes) {
if (asBytes) {
unsigned byteWidth = (IT->getBitWidth() >> 3);
for (unsigned x = 0; x < byteWidth; ++x) {
@@ -1004,28 +935,22 @@
}
}
}
-
void
-dumpZeroElements(ArrayType * const AT, OSTREAM_TYPE &O, bool asBytes)
-{
+dumpZeroElements(ArrayType * const AT, OSTREAM_TYPE &O, bool asBytes) {
size_t size = AT->getNumElements();
for (size_t x = 0; x < size; ++x) {
dumpZeroElements(AT->getElementType(), O, asBytes);
}
}
-
void
-dumpZeroElements(VectorType * const VT, OSTREAM_TYPE &O, bool asBytes)
-{
+dumpZeroElements(VectorType * const VT, OSTREAM_TYPE &O, bool asBytes) {
size_t size = VT->getNumElements();
for (size_t x = 0; x < size; ++x) {
dumpZeroElements(VT->getElementType(), O, asBytes);
}
}
-
void AMDILModuleInfo::printConstantValue(const Constant *CAval,
- OSTREAM_TYPE &O, bool asBytes)
-{
+ OSTREAM_TYPE &O, bool asBytes) {
if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CAval)) {
bool isDouble = &CFP->getValueAPF().getSemantics()==&APFloat::IEEEdouble;
if (isDouble) {
@@ -1070,7 +995,8 @@
O.write_hex(zVal);
} else {
switch (CI->getBitWidth()) {
- default: {
+ default:
+ {
union ltob_union {
uint64_t l;
char c[8];
@@ -1086,7 +1012,8 @@
O << ":";
O.write_hex(zVal & 0xFF);
break;
- case 16: {
+ case 16:
+ {
union stob_union {
uint16_t s;
char c[2];
@@ -1098,7 +1025,8 @@
O.write_hex((unsigned)conv.c[1] & 0xFF);
}
break;
- case 32: {
+ case 32:
+ {
union itob_union {
uint32_t i;
char c[4];
@@ -1126,7 +1054,7 @@
printConstantValue(CS->getOperand(x), O, asBytes);
}
} else if (const ConstantAggregateZero *CAZ
- = dyn_cast<ConstantAggregateZero>(CAval)) {
+ = dyn_cast<ConstantAggregateZero>(CAval)) {
int y = CAZ->getNumOperands();
if (y > 0) {
int x = 0;
@@ -1151,7 +1079,8 @@
for (; x < y; ++x) {
printConstantValue(CA->getOperand(x), O, asBytes);
}
- } else if (const ConstantDataSequential *CDS = dyn_cast<ConstantDataSequential>(CAval)) {
+ } else if (const ConstantDataSequential *CDS =
+ dyn_cast<ConstantDataSequential>(CAval)) {
int y = CDS->getNumElements();
int x = 0;
for (; x < y; ++x) {
@@ -1167,7 +1096,6 @@
assert(0 && "Hit condition which was not expected");
}
}
-
static bool isStruct(Type * const T)
{
if (!T) {
@@ -1184,12 +1112,10 @@
case Type::VectorTyID:
return isStruct(dyn_cast<SequentialType>(T)->getElementType());
};
-
}
-
-void AMDILModuleInfo::dumpDataToCB(OSTREAM_TYPE &O, AMDILMachineFunctionInfo *mfi,
- uint32_t id)
-{
+void AMDILModuleInfo::dumpDataToCB(OSTREAM_TYPE &O,
+ AMDILMachineFunctionInfo *mfi,
+ uint32_t id) {
uint32_t size = 0;
for (StringMap<AMDILConstPtr>::iterator cmb = consts_begin(),
cme = consts_end(); cmb != cme; ++cmb) {
@@ -1224,7 +1150,7 @@
size_t size = (isStruct(Ty) ? TD->getTypeAllocSize(Ty)
: getNumElements(Ty));
O << ";#" << getTypeName(Ty, symTab, mfi, true) << ":";
- O << offset << ":" << size ;
+ O << offset << ":" << size;
printConstantValue(C, O, isStruct(Ty));
O << "\n";
}
@@ -1234,7 +1160,8 @@
O << ";#DATASTART:" << id << ":" << size << "\n";
}
- for (StringMap<AMDILConstPtr>::iterator cmb = consts_begin(), cme = consts_end();
+ for (StringMap<AMDILConstPtr>::iterator cmb = consts_begin(),
+ cme = consts_end();
cmb != cme; ++cmb) {
if (cmb->second.cbNum != id) {
continue;
@@ -1266,15 +1193,15 @@
O << ";#DATAEND:" << id << "\n";
}
}
-
void
-AMDILModuleInfo::dumpDataSection(OSTREAM_TYPE &O, AMDILMachineFunctionInfo *mfi)
-{
+AMDILModuleInfo::dumpDataSection(OSTREAM_TYPE &O,
+ AMDILMachineFunctionInfo *mfi) {
if (consts_empty() && !mCurrentCPOffset) {
return;
} else {
llvm::DenseSet<uint32_t> const_set;
- for (StringMap<AMDILConstPtr>::iterator cmb = consts_begin(), cme = consts_end();
+ for (StringMap<AMDILConstPtr>::iterator cmb = consts_begin(),
+ cme = consts_end();
cmb != cme; ++cmb) {
const_set.insert(cmb->second.cbNum);
}
@@ -1287,11 +1214,9 @@
}
}
}
-
/// Create a function ID if it is not known or return the known
/// function ID.
-uint32_t AMDILModuleInfo::getOrCreateFunctionID(const GlobalValue* func)
-{
+uint32_t AMDILModuleInfo::getOrCreateFunctionID(const GlobalValue* func) {
if (func->getName().size()) {
return getOrCreateFunctionID(func->getName());
}
@@ -1304,9 +1229,7 @@
}
return id;
}
-
-uint32_t AMDILModuleInfo::getOrCreateFunctionID(const std::string &func)
-{
+uint32_t AMDILModuleInfo::getOrCreateFunctionID(const std::string &func) {
uint32_t id;
if (mFuncNames.find(func) == mFuncNames.end()) {
id = mFuncNames.size() + RESERVED_FUNCS + mFuncPtrNames.size();
@@ -1316,4 +1239,32 @@
}
return id;
}
-
+// populate the next local buffer with a set of local pointers
+// return the resource ID of the local buffer populated
+uint32_t AMDILModuleInfo::populateNextLocalBuffer(
+ const SmallSet<const Value*, 1>& locals, bool isDefaultBuf)
+{
+ uint32_t defLocalId = mSTM->device()->getResourceID(AMDILDevice::LDS_ID);
+ uint32_t resId = isDefaultBuf ? defLocalId : defLocalId + mNumLocalBuffers;
+ if (!isDefaultBuf) ++mNumLocalBuffers;
+ unsigned offset = 0;
+ for (SmallSet<const Value*, 1>::iterator sBegin = locals.begin(),
+ sEnd = locals.end();
+ sBegin != sEnd; ++sBegin) {
+ const Value* V = *sBegin;
+ // skip kernal arguments
+ if (!isa<GlobalValue>(V)) continue;
+ const Value* GV = *sBegin;
+ const PointerType *PT = dyn_cast<PointerType>(GV->getType());
+ assert(PT && PT->getAddressSpace() == AMDILAS::LOCAL_ADDRESS && "sanity");
+ llvm::StringRef GVName = GV->getName();
+ StringMap<AMDILArrayMem>::iterator iter = mArrayMems.find(GVName);
+ assert(iter != mArrayMems.end() && "undefined local buffer?");
+ AMDILArrayMem& local = iter->second;
+ assert(local.isHW && !local.isRegion && "sanity");
+ local.resourceID = resId;
+ local.offset = AlignUp_32(offset, local.align);
+ offset = local.offset + local.vecSize;
+ }
+ return resId;
+}
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILModuleInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILModuleInfo.h?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILModuleInfo.h (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILModuleInfo.h Wed Sep 12 12:43:34 2012
@@ -27,8 +27,7 @@
#include <set>
#define CB_BASE_OFFSET 2
-namespace llvm
-{
+namespace llvm {
class AMDILKernel;
class Argument;
class TypeSymbolTable;
@@ -37,8 +36,7 @@
class GlobalValue;
class AMDILMachineFunctionInfo;
-class AMDILModuleInfo : public MachineModuleInfoImpl
-{
+class AMDILModuleInfo : public MachineModuleInfoImpl {
protected:
const MachineModuleInfo *mMMI;
public:
@@ -103,7 +101,8 @@
uint32_t getConstPtrCB(const AMDILKernel *krnl, const llvm::StringRef &arg);
/// Query the Value* that the constant pointer originates from.
- const Value *getConstPtrValue(const AMDILKernel *krnl, const llvm::StringRef &arg);
+ const Value *getConstPtrValue(const AMDILKernel *krnl,
+ const llvm::StringRef &arg);
/// Get the ID of the argument.
int32_t getArgID(const Argument *arg);
@@ -123,8 +122,12 @@
uint32_t get_printf_offset() {
return mPrintfOffset;
}
-
+ uint32_t populateNextLocalBuffer(
+ const SmallSet<const Value*, 1>& locals, bool isDefaultBuf);
std::set<std::string>* getSamplerForKernel(llvm::StringRef &kernelName);
+ uint32_t numLocalBuffers() const {
+ return mNumLocalBuffers;
+ }
private:
/// Various functions that parse global value information and store them in
@@ -144,7 +147,6 @@
OSTREAM_TYPE& O,
bool asByte);
-
// parse the local and region operands for parseKernelInformation
AMDILLocalArg* parseKernelLRInfo(AMDILKernel *kernel, const Constant *CV);
void parseKernelInformation(const Value *V);
@@ -173,11 +175,9 @@
uint32_t mReservedBuffs;
uint32_t mCurrentCPOffset;
uint32_t mPrintfOffset;
+ uint32_t mNumLocalBuffers;
bool mProcessed;
};
-
-
-
} // end namespace llvm
#endif // _AMDIL_COFF_MACHINE_MODULE_INFO_H_
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILMultiClass.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILMultiClass.td?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILMultiClass.td (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILMultiClass.td Wed Sep 12 12:43:34 2012
@@ -11,1692 +11,3144 @@
//
//===----------------------------------------------------------------------===//
-multiclass BranchConditional<SDNode Op> {
- def _i8 : ILFormat<IL_OP_IFC, (outs),
- (ins brtarget:$target, GPRI8:$src0),
- "; i8 Pseudo branch instruction",
- [(Op bb:$target, GPRI8:$src0)]>;
- def _i16 : ILFormat<IL_OP_IFC, (outs),
- (ins brtarget:$target, GPRI16:$src0),
- "; i16 Pseudo branch instruction",
- [(Op bb:$target, GPRI16:$src0)]>;
- def _i32 : ILFormat<IL_OP_IFC, (outs),
- (ins brtarget:$target, GPRI32:$src0),
- "; i32 Pseudo branch instruction",
- [(Op bb:$target, GPRI32:$src0)]>;
- def _f32 : ILFormat<IL_OP_IFC, (outs),
- (ins brtarget:$target, GPRF32:$src0),
- "; f32 Pseudo branch instruction",
- [(Op bb:$target, GPRF32:$src0)]>;
- def _i64 : ILFormat<IL_OP_IFC, (outs),
- (ins brtarget:$target, GPRI64:$src0),
- "; i64 Pseudo branch instruction",
- [(Op bb:$target, (i64 GPRI64:$src0))]>;
- def _f64 : ILFormat<IL_OP_IFC, (outs),
- (ins brtarget:$target, GPRF64:$src0),
- "; f64 Pseudo branch instruction",
- [(Op bb:$target, (f64 GPRF64:$src0))]>;
-}
-// Multiclass that handles compare instructions
-// When a definition is added here, a corrosponding defition
-// needs to be added at:
-// AMDILISelLowering.cpp at EmitInstrWithCustomInserter
-multiclass Compare<string asm> {
- def _i8 : ILFormat<IL_OP_CMP, (outs GPRI8:$dst),
- (ins i32imm:$cc, GPRI8:$src0, GPRI8:$src1),
- !strconcat("; i8 ", asm),
- [(set GPRI8:$dst, (IL_cmp imm:$cc, GPRI8:$src0, GPRI8:$src1))]>;
- def _i16 : ILFormat<IL_OP_CMP, (outs GPRI16:$dst),
- (ins i32imm:$cc, GPRI16:$src0, GPRI16:$src1),
- !strconcat("; i16 ", asm),
- [(set GPRI16:$dst, (IL_cmp imm:$cc, GPRI16:$src0, GPRI16:$src1))]>;
- def _i32 : ILFormat<IL_OP_CMP, (outs GPRI32:$dst),
- (ins i32imm:$cc, GPRI32:$src0, GPRI32:$src1),
- !strconcat("; i32 ", asm),
- [(set GPRI32:$dst, (IL_cmp imm:$cc, GPRI32:$src0, GPRI32:$src1))]>;
- def _i64 : ILFormat<IL_OP_CMP, (outs GPRI64:$dst),
- (ins i32imm:$cc, GPRI64:$src0, GPRI64:$src1),
- !strconcat("; i64 ", asm),
- [(set GPRI64:$dst, (IL_cmp imm:$cc, GPRI64:$src0, GPRI64:$src1))]>;
- def _f32 : ILFormat<IL_OP_CMP, (outs GPRF32:$dst),
- (ins i32imm:$cc, GPRF32:$src0, GPRF32:$src1),
- !strconcat("; f32 ", asm),
- [(set GPRF32:$dst, (IL_cmp imm:$cc, GPRF32:$src0, GPRF32:$src1))]>;
- def _f64 : ILFormat<IL_OP_CMP, (outs GPRF64:$dst),
- (ins i32imm:$cc, GPRF64:$src0, GPRF64:$src1),
- !strconcat("; f64 ", asm),
- [(set GPRF64:$dst, (IL_cmp imm:$cc, GPRF64:$src0, GPRF64:$src1))]>;
- def _v2i8 : ILFormat<IL_OP_CMP, (outs GPRV2I8:$dst),
- (ins i32imm:$cc, GPRV2I8:$src0, GPRV2I8:$src1),
- !strconcat("; i8 ", asm),
- [(set GPRV2I8:$dst, (IL_cmp imm:$cc, GPRV2I8:$src0, GPRV2I8:$src1))]>;
- def _v2i16 : ILFormat<IL_OP_CMP, (outs GPRV2I16:$dst),
- (ins i32imm:$cc, GPRV2I16:$src0, GPRV2I16:$src1),
- !strconcat("; i16 ", asm),
- [(set GPRV2I16:$dst, (IL_cmp imm:$cc, GPRV2I16:$src0, GPRV2I16:$src1))]>;
- def _v2i32 : ILFormat<IL_OP_CMP, (outs GPRV2I32:$dst),
- (ins i32imm:$cc, GPRV2I32:$src0, GPRV2I32:$src1),
- !strconcat("; i32 ", asm),
- [(set GPRV2I32:$dst, (IL_cmp imm:$cc, GPRV2I32:$src0, GPRV2I32:$src1))]>;
- def _v2i64 : ILFormat<IL_OP_CMP, (outs GPRV2I64:$dst),
- (ins i32imm:$cc, GPRV2I64:$src0, GPRV2I64:$src1),
- !strconcat("; i64 ", asm),
- [(set GPRV2I64:$dst, (IL_cmp imm:$cc, GPRV2I64:$src0, GPRV2I64:$src1))]>;
- def _v2f32 : ILFormat<IL_OP_CMP, (outs GPRV2F32:$dst),
- (ins i32imm:$cc, GPRV2F32:$src0, GPRV2F32:$src1),
- !strconcat("; f32 ", asm),
- [(set GPRV2F32:$dst, (IL_cmp imm:$cc, GPRV2F32:$src0, GPRV2F32:$src1))]>;
- def _v2f64 : ILFormat<IL_OP_CMP, (outs GPRV2F64:$dst),
- (ins i32imm:$cc, GPRV2F64:$src0, GPRV2F64:$src1),
- !strconcat("; f64 ", asm),
- [(set GPRV2F64:$dst, (IL_cmp imm:$cc, GPRV2F64:$src0, GPRV2F64:$src1))]>;
- def _v4i8 : ILFormat<IL_OP_CMP, (outs GPRV4I8:$dst),
- (ins i32imm:$cc, GPRV4I8:$src0, GPRV4I8:$src1),
- !strconcat("; i8 ", asm),
- [(set GPRV4I8:$dst, (IL_cmp imm:$cc, GPRV4I8:$src0, GPRV4I8:$src1))]>;
- def _v4i16 : ILFormat<IL_OP_CMP, (outs GPRV4I16:$dst),
- (ins i32imm:$cc, GPRV4I16:$src0, GPRV4I16:$src1),
- !strconcat("; i16 ", asm),
- [(set GPRV4I16:$dst, (IL_cmp imm:$cc, GPRV4I16:$src0, GPRV4I16:$src1))]>;
- def _v4i32 : ILFormat<IL_OP_CMP, (outs GPRV4I32:$dst),
- (ins i32imm:$cc, GPRV4I32:$src0, GPRV4I32:$src1),
- !strconcat("; i32 ", asm),
- [(set GPRV4I32:$dst, (IL_cmp imm:$cc, GPRV4I32:$src0, GPRV4I32:$src1))]>;
- def _v4f32 : ILFormat<IL_OP_CMP, (outs GPRV4F32:$dst),
- (ins i32imm:$cc, GPRV4F32:$src0, GPRV4F32:$src1),
- !strconcat("; f32 ", asm),
- [(set GPRV4F32:$dst, (IL_cmp imm:$cc, GPRV4F32:$src0, GPRV4F32:$src1))]>;
+multiclass Branch<SDNode Op, RegisterClass reg, Operand oper, ValueType type, SDNode imm0> {
+ def br: ILFormat<IL_OP_IFC, (outs), (ins brtarget:$target, reg:$src0),
+ "; Pseudo branch instrucion",
+ [(Op bb:$target, (type reg:$src0))]>;
+ def bi: ILFormat<IL_OP_IFC, (outs), (ins brtarget:$target, oper:$src0),
+ "; Pseudo branch instrucion",
+ [(Op bb:$target, (type imm0:$src0))]>;
+}
+multiclass BranchMC<SDNode Op> {
+ def b : ILFormat<IL_PSEUDO_INST, (outs), (ins brtarget:$target),
+ "; Pseudo unconditional branch instrution",
+ [(br bb:$target)]>;
+ defm i8 : Branch<Op, GPRI8, i8imm, i8, imm>;
+ defm i16 : Branch<Op, GPRI16, i16imm, i16, imm>;
+ defm i32 : Branch<Op, GPRI32, i32imm, i32, imm>;
+ defm i64 : Branch<Op, GPRI64, i64imm, i64, imm>;
+ defm f32 : Branch<Op, GPRF32, f32imm, f32, fpimm>;
+ defm f64 : Branch<Op, GPRF64, f64imm, f64, fpimm>;
+}
+
+multiclass ILFrameIndex<string asm> {
+ def i32 : ILFormat<IL_OP_MOV, (outs GPRI32:$dst),
+ (ins i32imm:$val),
+ asm, [(set GPRI32:$dst, frameindex:$val)]>;
}
// Multiclass that handles constant values
multiclass ILConstant<string asm> {
- def _i8 : ILFormat<IL_OP_MOV, (outs GPRI8:$dst),
+ def i8 : ILFormat<IL_OP_MOV, (outs GPRI8:$dst),
(ins i8imm:$val),
asm, [(set GPRI8:$dst, imm:$val)]>;
- // def _v2i8 : ILFormat<IL_OP_MOV, (outs GPRV2I8:$dst),
- // (ins i8imm:$val),
- // asm, [(set GPRV2I8:$dst, GPRV2I8:$val)]>;
-
- //def _v4i8 : ILFormat<IL_OP_MOV, (outs GPRV4I8:$dst),
- //(ins i8imm:$val),
- //asm, [(set GPRV4I8:$dst, GPRV4I8:$val)]>;
+ def v2i8 : ILFormat<IL_OP_MOV, (outs GPRV2I8:$dst),
+ (ins v2i8imm:$val),
+ asm, [(set GPRV2I8:$dst, imm:$val)]>;
+
+ def v4i8 : ILFormat<IL_OP_MOV, (outs GPRV4I8:$dst),
+ (ins v4i8imm:$val),
+ asm, [(set GPRV4I8:$dst, imm:$val)]>;
- def _i16 : ILFormat<IL_OP_MOV, (outs GPRI16:$dst),
+ def i16 : ILFormat<IL_OP_MOV, (outs GPRI16:$dst),
(ins i16imm:$val),
asm, [(set GPRI16:$dst, imm:$val)]>;
- // def _v2i16 : ILFormat<IL_OP_MOV, (outs GPRV2I16:$dst),
- // (ins i16imm:$val),
- // asm, [(set GPRV2I16:$dst, GPRV2I16:$val)]>;
-
- // def _v4i16 : ILFormat<IL_OP_MOV, (outs GPRV4I16:$dst),
- // (ins i16imm:$val),
- // asm, [(set GPRV4I16:$dst, GPRV4I16:$val)]>;
+ def v2i16 : ILFormat<IL_OP_MOV, (outs GPRV2I16:$dst),
+ (ins v2i16imm:$val),
+ asm, [(set GPRV2I16:$dst, imm:$val)]>;
+
+ def v4i16 : ILFormat<IL_OP_MOV, (outs GPRV4I16:$dst),
+ (ins v4i16imm:$val),
+ asm, [(set GPRV4I16:$dst, imm:$val)]>;
- def _i32 : ILFormat<IL_OP_MOV, (outs GPRI32:$dst),
+ def i32 : ILFormat<IL_OP_MOV, (outs GPRI32:$dst),
(ins i32imm:$val),
asm, [(set GPRI32:$dst, imm:$val)]>;
- // def _v2i32 : ILFormat<IL_OP_MOV, (outs GPRV2I32:$dst),
- // (ins i32imm:$val),
- // asm, [(set GPRV2I32:$dst, GPRV2I32:$val)]>;
-
- // def _v4i32 : ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
- // (ins GPRV4I32:$val),
- // asm, [(set GPRV4I32:$dst, GPRV4I32:$val)]>;
+ def v2i32 : ILFormat<IL_OP_MOV, (outs GPRV2I32:$dst),
+ (ins v2i32imm:$val),
+ asm, [(set GPRV2I32:$dst, imm:$val)]>;
+
+ def v4i32 : ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
+ (ins v4i32imm:$val),
+ asm, [(set GPRV4I32:$dst, imm:$val)]>;
- def _i64 : ILFormat<IL_OP_MOV, (outs GPRI64:$dst),
+ def i64 : ILFormat<IL_OP_MOV, (outs GPRI64:$dst),
(ins i64imm:$val),
asm, [(set GPRI64:$dst, imm:$val)]>;
- // def _v2i64 : ILFormat<IL_OP_MOV, (outs GPRV2I64:$dst),
- // (ins i64imm:$val),
- // asm, [(set GPRV2I64:$dst, GPRV2I64:$val)]>;
+ def v2i64 : ILFormat<IL_OP_MOV, (outs GPRV2I64:$dst),
+ (ins v2i64imm:$val),
+ asm, [(set GPRV2I64:$dst, imm:$val)]>;
- def _f32 : ILFormat<IL_OP_MOV, (outs GPRF32:$dst),
+ def f32 : ILFormat<IL_OP_MOV, (outs GPRF32:$dst),
(ins f32imm:$val),
asm, [(set GPRF32:$dst, fpimm:$val)]>;
- // def _v2f32 : ILFormat<IL_OP_MOV, (outs GPRV2F32:$dst),
- // (ins f32imm:$val),
- // asm, [(set GPRV2F32:$dst, GPRV2F32:$val)]>;
-
- // def _v4f32 : ILFormat<IL_OP_MOV, (outs GPRV4F32:$dst),
- // (ins f32imm:$val),
- // asm, [(set GPRV4F32:$dst, GPRV4F32:$val)]>;
+ def v2f32 : ILFormat<IL_OP_MOV, (outs GPRV2F32:$dst),
+ (ins v2f32imm:$val),
+ asm, [(set GPRV2F32:$dst, fpimm:$val)]>;
+
+ def v4f32 : ILFormat<IL_OP_MOV, (outs GPRV4F32:$dst),
+ (ins v4f32imm:$val),
+ asm, [(set GPRV4F32:$dst, fpimm:$val)]>;
- def _f64 : ILFormat<IL_OP_MOV, (outs GPRF64:$dst),
+ def f64 : ILFormat<IL_OP_MOV, (outs GPRF64:$dst),
(ins f64imm:$val),
asm, [(set GPRF64:$dst, fpimm:$val)]>;
- // def _v2f64 : ILFormat<IL_OP_MOV, (outs GPRV2F64:$dst),
- // (ins f64imm:$val),
- // asm, [(set GPRV2F64:$dst, GPRV2F64:$val)]>;
-
-}
-
-// Multiclass that handles memory store operations
-multiclass GTRUNCSTORE<string asm> {
- def _i16i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI16:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(global_i8trunc_store GPRI16:$val, ADDR:$ptr)]>;
- def _i32i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI32:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(global_i8trunc_store GPRI32:$val, ADDR:$ptr)]>;
- def _i64i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI64:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(global_i8trunc_store GPRI64:$val, ADDR:$ptr)]>;
- def _i32i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI32:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(global_i16trunc_store GPRI32:$val, ADDR:$ptr)]>;
- def _i64i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI64:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(global_i16trunc_store GPRI64:$val, ADDR:$ptr)]>;
- def _i64i32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI64:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(global_i32trunc_store GPRI64:$val, ADDR:$ptr)]>;
- def _f64f32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRF64:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(global_f32trunc_store GPRF64:$val, ADDR:$ptr)]>;
- def _v2i32i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I32:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(global_v2i8trunc_store GPRV2I32:$val, ADDR:$ptr)]>;
- def _v4i32i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4I32:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(global_v4i8trunc_store GPRV4I32:$val, ADDR:$ptr)]>;
- def _v2i16i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I16:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(global_v2i8trunc_store GPRV2I16:$val, ADDR:$ptr)]>;
- def _v4i16i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4I16:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(global_v4i8trunc_store GPRV4I16:$val, ADDR:$ptr)]>;
- def _v2i32i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I32:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(global_v2i16trunc_store GPRV2I32:$val, ADDR:$ptr)]>;
- def _v4i32i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4I32:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(global_v4i16trunc_store GPRV4I32:$val, ADDR:$ptr)]>;
- def _v2f64f32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2F64:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(global_v2f32trunc_store GPRV2F64:$val, ADDR:$ptr)]>;
- def _v2i64i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I64:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(global_v2i8trunc_store GPRV2I64:$val, ADDR:$ptr)]>;
- def _v2i64i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I64:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(global_v2i16trunc_store GPRV2I64:$val, ADDR:$ptr)]>;
- def _v2i64i32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I64:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(global_v2i32trunc_store GPRV2I64:$val, ADDR:$ptr)]>;
-}
-
-// Multiclass that handles memory store operations
-multiclass LTRUNCSTORE<string asm> {
- def _i16i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI16:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(local_i8trunc_store GPRI16:$val, ADDR:$ptr)]>;
- def _i32i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI32:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(local_i8trunc_store GPRI32:$val, ADDR:$ptr)]>;
- def _i64i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI64:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(local_i8trunc_store GPRI64:$val, ADDR:$ptr)]>;
- def _i32i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI32:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(local_i16trunc_store GPRI32:$val, ADDR:$ptr)]>;
- def _i64i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI64:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(local_i16trunc_store GPRI64:$val, ADDR:$ptr)]>;
- def _i64i32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI64:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(local_i32trunc_store GPRI64:$val, ADDR:$ptr)]>;
- def _f64f32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRF64:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(local_f32trunc_store GPRF64:$val, ADDR:$ptr)]>;
- def _v2i32i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I32:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(local_v2i8trunc_store GPRV2I32:$val, ADDR:$ptr)]>;
- def _v4i32i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4I32:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(local_v4i8trunc_store GPRV4I32:$val, ADDR:$ptr)]>;
- def _v2i16i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I16:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(local_v2i8trunc_store GPRV2I16:$val, ADDR:$ptr)]>;
- def _v4i16i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4I16:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(local_v4i8trunc_store GPRV4I16:$val, ADDR:$ptr)]>;
- def _v2i32i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I32:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(local_v2i16trunc_store GPRV2I32:$val, ADDR:$ptr)]>;
- def _v4i32i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4I32:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(local_v4i16trunc_store GPRV4I32:$val, ADDR:$ptr)]>;
- def _v2f64f32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2F64:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(local_v2f32trunc_store GPRV2F64:$val, ADDR:$ptr)]>;
- def _v2i64i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I64:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(local_v2i8trunc_store GPRV2I64:$val, ADDR:$ptr)]>;
- def _v2i64i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I64:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(local_v2i16trunc_store GPRV2I64:$val, ADDR:$ptr)]>;
- def _v2i64i32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I64:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(local_v2i32trunc_store GPRV2I64:$val, ADDR:$ptr)]>;
-}
-
-// Multiclass that handles memory store operations
-multiclass PTRUNCSTORE<string asm> {
- def _i16i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI16:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(private_i8trunc_store GPRI16:$val, ADDR:$ptr)]>;
- def _i32i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI32:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(private_i8trunc_store GPRI32:$val, ADDR:$ptr)]>;
- def _i64i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI64:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(private_i8trunc_store GPRI64:$val, ADDR:$ptr)]>;
- def _i32i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI32:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(private_i16trunc_store GPRI32:$val, ADDR:$ptr)]>;
- def _i64i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI64:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(private_i16trunc_store GPRI64:$val, ADDR:$ptr)]>;
- def _i64i32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI64:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(private_i32trunc_store GPRI64:$val, ADDR:$ptr)]>;
- def _f64f32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRF64:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(private_f32trunc_store GPRF64:$val, ADDR:$ptr)]>;
- def _v2i32i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I32:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(private_v2i8trunc_store GPRV2I32:$val, ADDR:$ptr)]>;
- def _v4i32i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4I32:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(private_v4i8trunc_store GPRV4I32:$val, ADDR:$ptr)]>;
- def _v2i16i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I16:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(private_v2i8trunc_store GPRV2I16:$val, ADDR:$ptr)]>;
- def _v4i16i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4I16:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(private_v4i8trunc_store GPRV4I16:$val, ADDR:$ptr)]>;
- def _v2i32i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I32:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(private_v2i16trunc_store GPRV2I32:$val, ADDR:$ptr)]>;
- def _v4i32i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4I32:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(private_v4i16trunc_store GPRV4I32:$val, ADDR:$ptr)]>;
- def _v2f64f32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2F64:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(private_v2f32trunc_store GPRV2F64:$val, ADDR:$ptr)]>;
- def _v2i64i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I64:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(private_v2i8trunc_store GPRV2I64:$val, ADDR:$ptr)]>;
- def _v2i64i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I64:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(private_v2i16trunc_store GPRV2I64:$val, ADDR:$ptr)]>;
- def _v2i64i32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I64:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(private_v2i32trunc_store GPRV2I64:$val, ADDR:$ptr)]>;
-}
-
-// Multiclass that handles memory store operations
-multiclass RTRUNCSTORE<string asm> {
- def _i16i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI16:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(region_i8trunc_store GPRI16:$val, ADDR:$ptr)]>;
- def _i32i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI32:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(region_i8trunc_store GPRI32:$val, ADDR:$ptr)]>;
- def _i64i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI64:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(region_i8trunc_store GPRI64:$val, ADDR:$ptr)]>;
- def _i32i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI32:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(region_i16trunc_store GPRI32:$val, ADDR:$ptr)]>;
- def _i64i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI64:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(region_i16trunc_store GPRI64:$val, ADDR:$ptr)]>;
- def _i64i32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI64:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(region_i32trunc_store GPRI64:$val, ADDR:$ptr)]>;
- def _f64f32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRF64:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(region_f32trunc_store GPRF64:$val, ADDR:$ptr)]>;
- def _v2i32i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I32:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(region_v2i8trunc_store GPRV2I32:$val, ADDR:$ptr)]>;
- def _v4i32i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4I32:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(region_v4i8trunc_store GPRV4I32:$val, ADDR:$ptr)]>;
- def _v2i16i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I16:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(region_v2i8trunc_store GPRV2I16:$val, ADDR:$ptr)]>;
- def _v4i16i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4I16:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(region_v4i8trunc_store GPRV4I16:$val, ADDR:$ptr)]>;
- def _v2i32i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I32:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(region_v2i16trunc_store GPRV2I32:$val, ADDR:$ptr)]>;
- def _v4i32i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4I32:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(region_v4i16trunc_store GPRV4I32:$val, ADDR:$ptr)]>;
- def _v2f64f32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2F64:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(region_v2f32trunc_store GPRV2F64:$val, ADDR:$ptr)]>;
- def _v2i64i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I64:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(region_v2i8trunc_store GPRV2I64:$val, ADDR:$ptr)]>;
- def _v2i64i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I64:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(region_v2i16trunc_store GPRV2I64:$val, ADDR:$ptr)]>;
- def _v2i64i32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I64:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(region_v2i32trunc_store GPRV2I64:$val, ADDR:$ptr)]>;
-}
-
-
-// Multiclass that handles memory store operations
-multiclass STORE<string asm, PatFrag OpNode> {
- def _i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI8:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRI8:$val, ADDR:$ptr)]>;
- def _i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI16:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRI16:$val, ADDR:$ptr)]>;
- def _i32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI32:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRI32:$val, ADDR:$ptr)]>;
- def _f32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRF32:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRF32:$val, ADDR:$ptr)]>;
- def _i64 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI64:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRI64:$val, ADDR:$ptr)]>;
- def _f64 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRF64:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRF64:$val, ADDR:$ptr)]>;
- def _v4f32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4F32:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV4F32:$val, ADDR:$ptr)]>;
- def _v2f32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2F32:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV2F32:$val, ADDR:$ptr)]>;
- def _v4i32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4I32:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV4I32:$val, ADDR:$ptr)]>;
- def _v2i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I8:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV2I8:$val, ADDR:$ptr)]>;
- def _v2i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I16:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV2I16:$val, ADDR:$ptr)]>;
- def _v4i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4I8:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV4I8:$val, ADDR:$ptr)]>;
- def _v4i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4I16:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV4I16:$val, ADDR:$ptr)]>;
- def _v2i32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I32:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV2I32:$val, ADDR:$ptr)]>;
- def _v2f64 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2F64:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV2F64:$val, ADDR:$ptr)]>;
- def _v2i64 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I64:$val, MEM3232:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV2I64:$val, ADDR:$ptr)]>;
-}
-
-// Multiclass that handles load operations
-multiclass LOAD<string asm, PatFrag OpNode> {
- def _i8 : OneInOneOut<IL_OP_MOV, (outs GPRI8:$dst), (ins MEM3232:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRI8:$dst, (OpNode ADDR:$ptr))]>;
- def _i16 : OneInOneOut<IL_OP_MOV, (outs GPRI16:$dst), (ins MEM3232:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRI16:$dst, (OpNode ADDR:$ptr))]>;
- def _i32 : OneInOneOut<IL_OP_MOV, (outs GPRI32:$dst), (ins MEM3232:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRI32:$dst, (OpNode ADDR:$ptr))]>;
- def _f32 : OneInOneOut<IL_OP_MOV, (outs GPRF32:$dst), (ins MEM3232:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRF32:$dst, (OpNode ADDR:$ptr))]>;
- def _i64 : OneInOneOut<IL_OP_MOV, (outs GPRI64:$dst), (ins MEM3232:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRI64:$dst, (OpNode ADDR:$ptr))]>;
- def _f64 : OneInOneOut<IL_OP_MOV, (outs GPRF64:$dst), (ins MEM3232:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRF64:$dst, (OpNode ADDR:$ptr))]>;
- def _v4f32 : OneInOneOut<IL_OP_MOV, (outs GPRV4F32:$dst), (ins MEM3232:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV4F32:$dst, (OpNode ADDR:$ptr))]>;
- def _v2f32 : OneInOneOut<IL_OP_MOV, (outs GPRV2F32:$dst), (ins MEM3232:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV2F32:$dst, (OpNode ADDR:$ptr))]>;
- def _v2f64 : OneInOneOut<IL_OP_MOV, (outs GPRV2F64:$dst), (ins MEM3232:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV2F64:$dst, (OpNode ADDR:$ptr))]>;
- def _v4i32 : OneInOneOut<IL_OP_MOV, (outs GPRV4I32:$dst), (ins MEM3232:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV4I32:$dst, (OpNode ADDR:$ptr))]>;
- def _v2i8 : OneInOneOut<IL_OP_MOV, (outs GPRV2I8:$dst), (ins MEM3232:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV2I8:$dst, (OpNode ADDR:$ptr))]>;
- def _v2i16 : OneInOneOut<IL_OP_MOV, (outs GPRV2I16:$dst), (ins MEM3232:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV2I16:$dst, (OpNode ADDR:$ptr))]>;
- def _v4i8 : OneInOneOut<IL_OP_MOV, (outs GPRV4I8:$dst), (ins MEM3232:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV4I8:$dst, (OpNode ADDR:$ptr))]>;
- def _v4i16 : OneInOneOut<IL_OP_MOV, (outs GPRV4I16:$dst), (ins MEM3232:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV4I16:$dst, (OpNode ADDR:$ptr))]>;
- def _v2i32 : OneInOneOut<IL_OP_MOV, (outs GPRV2I32:$dst), (ins MEM3232:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV2I32:$dst, (OpNode ADDR:$ptr))]>;
- def _v2i64 : OneInOneOut<IL_OP_MOV, (outs GPRV2I64:$dst), (ins MEM3232:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV2I64:$dst, (OpNode ADDR:$ptr))]>;
-}
-
-// Multiclass that handles memory store operations
-multiclass GTRUNCSTORE64<string asm> {
- def _i16i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI16:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(global_i8trunc_store GPRI16:$val, ADDR64:$ptr)]>;
- def _i32i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI32:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(global_i8trunc_store GPRI32:$val, ADDR64:$ptr)]>;
- def _i64i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI64:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(global_i8trunc_store GPRI64:$val, ADDR64:$ptr)]>;
- def _i32i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI32:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(global_i16trunc_store GPRI32:$val, ADDR64:$ptr)]>;
- def _i64i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI64:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(global_i16trunc_store GPRI64:$val, ADDR64:$ptr)]>;
- def _i64i32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI64:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(global_i32trunc_store GPRI64:$val, ADDR64:$ptr)]>;
- def _f64f32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRF64:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(global_f32trunc_store GPRF64:$val, ADDR64:$ptr)]>;
- def _v2i32i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I32:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(global_v2i8trunc_store GPRV2I32:$val, ADDR64:$ptr)]>;
- def _v4i32i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4I32:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(global_v4i8trunc_store GPRV4I32:$val, ADDR64:$ptr)]>;
- def _v2i16i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I16:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(global_v2i8trunc_store GPRV2I16:$val, ADDR64:$ptr)]>;
- def _v4i16i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4I16:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(global_v4i8trunc_store GPRV4I16:$val, ADDR64:$ptr)]>;
- def _v2i32i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I32:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(global_v2i16trunc_store GPRV2I32:$val, ADDR64:$ptr)]>;
- def _v4i32i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4I32:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(global_v4i16trunc_store GPRV4I32:$val, ADDR64:$ptr)]>;
- def _v2f64f32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2F64:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(global_v2f32trunc_store GPRV2F64:$val, ADDR64:$ptr)]>;
- def _v2i64i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I64:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(global_v2i8trunc_store GPRV2I64:$val, ADDR64:$ptr)]>;
- def _v2i64i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I64:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(global_v2i16trunc_store GPRV2I64:$val, ADDR64:$ptr)]>;
- def _v2i64i32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I64:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(global_v2i32trunc_store GPRV2I64:$val, ADDR64:$ptr)]>;
-}
-
-// Multiclass that handles memory store operations
-multiclass LTRUNCSTORE64<string asm> {
- def _i16i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI16:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(local_i8trunc_store GPRI16:$val, ADDR64:$ptr)]>;
- def _i32i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI32:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(local_i8trunc_store GPRI32:$val, ADDR64:$ptr)]>;
- def _i64i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI64:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(local_i8trunc_store GPRI64:$val, ADDR64:$ptr)]>;
- def _i32i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI32:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(local_i16trunc_store GPRI32:$val, ADDR64:$ptr)]>;
- def _i64i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI64:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(local_i16trunc_store GPRI64:$val, ADDR64:$ptr)]>;
- def _i64i32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI64:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(local_i32trunc_store GPRI64:$val, ADDR64:$ptr)]>;
- def _f64f32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRF64:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(local_f32trunc_store GPRF64:$val, ADDR64:$ptr)]>;
- def _v2i32i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I32:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(local_v2i8trunc_store GPRV2I32:$val, ADDR64:$ptr)]>;
- def _v4i32i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4I32:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(local_v4i8trunc_store GPRV4I32:$val, ADDR64:$ptr)]>;
- def _v2i16i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I16:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(local_v2i8trunc_store GPRV2I16:$val, ADDR64:$ptr)]>;
- def _v4i16i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4I16:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(local_v4i8trunc_store GPRV4I16:$val, ADDR64:$ptr)]>;
- def _v2i32i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I32:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(local_v2i16trunc_store GPRV2I32:$val, ADDR64:$ptr)]>;
- def _v4i32i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4I32:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(local_v4i16trunc_store GPRV4I32:$val, ADDR64:$ptr)]>;
- def _v2f64f32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2F64:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(local_v2f32trunc_store GPRV2F64:$val, ADDR64:$ptr)]>;
- def _v2i64i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I64:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(local_v2i8trunc_store GPRV2I64:$val, ADDR64:$ptr)]>;
- def _v2i64i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I64:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(local_v2i16trunc_store GPRV2I64:$val, ADDR64:$ptr)]>;
- def _v2i64i32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I64:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(local_v2i32trunc_store GPRV2I64:$val, ADDR64:$ptr)]>;
-}
-
-// Multiclass that handles memory store operations
-multiclass PTRUNCSTORE64<string asm> {
- def _i16i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI16:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(private_i8trunc_store GPRI16:$val, ADDR64:$ptr)]>;
- def _i32i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI32:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(private_i8trunc_store GPRI32:$val, ADDR64:$ptr)]>;
- def _i64i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI64:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(private_i8trunc_store GPRI64:$val, ADDR64:$ptr)]>;
- def _i32i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI32:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(private_i16trunc_store GPRI32:$val, ADDR64:$ptr)]>;
- def _i64i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI64:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(private_i16trunc_store GPRI64:$val, ADDR64:$ptr)]>;
- def _i64i32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI64:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(private_i32trunc_store GPRI64:$val, ADDR64:$ptr)]>;
- def _f64f32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRF64:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(private_f32trunc_store GPRF64:$val, ADDR64:$ptr)]>;
- def _v2i32i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I32:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(private_v2i8trunc_store GPRV2I32:$val, ADDR64:$ptr)]>;
- def _v4i32i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4I32:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(private_v4i8trunc_store GPRV4I32:$val, ADDR64:$ptr)]>;
- def _v2i16i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I16:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(private_v2i8trunc_store GPRV2I16:$val, ADDR64:$ptr)]>;
- def _v4i16i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4I16:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(private_v4i8trunc_store GPRV4I16:$val, ADDR64:$ptr)]>;
- def _v2i32i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I32:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(private_v2i16trunc_store GPRV2I32:$val, ADDR64:$ptr)]>;
- def _v4i32i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4I32:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(private_v4i16trunc_store GPRV4I32:$val, ADDR64:$ptr)]>;
- def _v2f64f32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2F64:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(private_v2f32trunc_store GPRV2F64:$val, ADDR64:$ptr)]>;
- def _v2i64i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I64:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(private_v2i8trunc_store GPRV2I64:$val, ADDR64:$ptr)]>;
- def _v2i64i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I64:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(private_v2i16trunc_store GPRV2I64:$val, ADDR64:$ptr)]>;
- def _v2i64i32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I64:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(private_v2i32trunc_store GPRV2I64:$val, ADDR64:$ptr)]>;
-}
-
-// Multiclass that handles memory store operations
-multiclass RTRUNCSTORE64<string asm> {
- def _i16i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI16:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(region_i8trunc_store GPRI16:$val, ADDR64:$ptr)]>;
- def _i32i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI32:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(region_i8trunc_store GPRI32:$val, ADDR64:$ptr)]>;
- def _i64i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI64:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(region_i8trunc_store GPRI64:$val, ADDR64:$ptr)]>;
- def _i32i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI32:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(region_i16trunc_store GPRI32:$val, ADDR64:$ptr)]>;
- def _i64i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI64:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(region_i16trunc_store GPRI64:$val, ADDR64:$ptr)]>;
- def _i64i32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI64:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(region_i32trunc_store GPRI64:$val, ADDR64:$ptr)]>;
- def _f64f32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRF64:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(region_f32trunc_store GPRF64:$val, ADDR64:$ptr)]>;
- def _v2i32i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I32:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(region_v2i8trunc_store GPRV2I32:$val, ADDR64:$ptr)]>;
- def _v4i32i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4I32:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(region_v4i8trunc_store GPRV4I32:$val, ADDR64:$ptr)]>;
- def _v2i16i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I16:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(region_v2i8trunc_store GPRV2I16:$val, ADDR64:$ptr)]>;
- def _v4i16i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4I16:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(region_v4i8trunc_store GPRV4I16:$val, ADDR64:$ptr)]>;
- def _v2i32i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I32:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(region_v2i16trunc_store GPRV2I32:$val, ADDR64:$ptr)]>;
- def _v4i32i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4I32:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(region_v4i16trunc_store GPRV4I32:$val, ADDR64:$ptr)]>;
- def _v2f64f32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2F64:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(region_v2f32trunc_store GPRV2F64:$val, ADDR64:$ptr)]>;
- def _v2i64i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I64:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(region_v2i8trunc_store GPRV2I64:$val, ADDR64:$ptr)]>;
- def _v2i64i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I64:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(region_v2i16trunc_store GPRV2I64:$val, ADDR64:$ptr)]>;
- def _v2i64i32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I64:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(region_v2i32trunc_store GPRV2I64:$val, ADDR64:$ptr)]>;
-}
-
-
-// Multiclass that handles memory store operations
-multiclass STORE64<string asm, PatFrag OpNode> {
- def STORE64_i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI8:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRI8:$val, ADDR64:$ptr)]>;
- def STORE64_i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI16:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRI16:$val, ADDR64:$ptr)]>;
- def STORE64_i32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI32:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRI32:$val, ADDR64:$ptr)]>;
- def STORE64_f32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRF32:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRF32:$val, ADDR64:$ptr)]>;
- def STORE64_i64 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI64:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRI64:$val, ADDR64:$ptr)]>;
- def STORE64_f64 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRF64:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRF64:$val, ADDR64:$ptr)]>;
- def STORE64_v4f32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4F32:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV4F32:$val, ADDR64:$ptr)]>;
- def STORE64_v2f32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2F32:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV2F32:$val, ADDR64:$ptr)]>;
- def STORE64_v4i32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4I32:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV4I32:$val, ADDR64:$ptr)]>;
- def STORE64_v2i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I8:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV2I8:$val, ADDR64:$ptr)]>;
- def STORE64_v2i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I16:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV2I16:$val, ADDR64:$ptr)]>;
- def STORE64_v4i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4I8:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV4I8:$val, ADDR64:$ptr)]>;
- def STORE64_v4i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4I16:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV4I16:$val, ADDR64:$ptr)]>;
- def STORE64_v2i32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I32:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV2I32:$val, ADDR64:$ptr)]>;
- def STORE64_v2f64 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2F64:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV2F64:$val, ADDR64:$ptr)]>;
- def STORE64_v2i64 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I64:$val, MEM6464:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV2I64:$val, ADDR64:$ptr)]>;
- /*
- def STORE6432_i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI8:$val, MEM6432:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRI8:$val, ADDR64:$ptr)]>;
- def STORE6432_i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI16:$val, MEM6432:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRI16:$val, ADDR64:$ptr)]>;
- def STORE6432_i32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI32:$val, MEM6432:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRI32:$val, ADDR64:$ptr)]>;
- def STORE6432_f32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRF32:$val, MEM6432:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRF32:$val, ADDR64:$ptr)]>;
- def STORE6432_i64 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI64:$val, MEM6432:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRI64:$val, ADDR64:$ptr)]>;
- def STORE6432_f64 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRF64:$val, MEM6432:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRF64:$val, ADDR64:$ptr)]>;
- def STORE6432_v4f32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4F32:$val, MEM6432:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV4F32:$val, ADDR64:$ptr)]>;
- def STORE6432_v2f32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2F32:$val, MEM6432:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV2F32:$val, ADDR64:$ptr)]>;
- def STORE6432_v4i32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4I32:$val, MEM6432:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV4I32:$val, ADDR64:$ptr)]>;
- def STORE6432_v2i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I8:$val, MEM6432:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV2I8:$val, ADDR64:$ptr)]>;
- def STORE6432_v2i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I16:$val, MEM6432:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV2I16:$val, ADDR64:$ptr)]>;
- def STORE6432_v4i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4I8:$val, MEM6432:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV4I8:$val, ADDR64:$ptr)]>;
- def STORE6432_v4i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4I16:$val, MEM6432:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV4I16:$val, ADDR64:$ptr)]>;
- def STORE6432_v2i32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I32:$val, MEM6432:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV2I32:$val, ADDR64:$ptr)]>;
- def STORE6432_v2f64 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2F64:$val, MEM6432:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV2F64:$val, ADDR64:$ptr)]>;
- def STORE6432_v2i64 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I64:$val, MEM6432:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV2I64:$val, ADDR64:$ptr)]>;
- def STORE3264_i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI8:$val, MEM3264:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRI8:$val, ADDR64:$ptr)]>;
- def STORE3264_i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI16:$val, MEM3264:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRI16:$val, ADDR64:$ptr)]>;
- def STORE3264_i32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI32:$val, MEM3264:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRI32:$val, ADDR64:$ptr)]>;
- def STORE3264_f32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRF32:$val, MEM3264:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRF32:$val, ADDR64:$ptr)]>;
- def STORE3264_i64 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRI64:$val, MEM3264:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRI64:$val, ADDR64:$ptr)]>;
- def STORE3264_f64 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRF64:$val, MEM3264:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRF64:$val, ADDR64:$ptr)]>;
- def STORE3264_v4f32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4F32:$val, MEM3264:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV4F32:$val, ADDR64:$ptr)]>;
- def STORE3264_v2f32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2F32:$val, MEM3264:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV2F32:$val, ADDR64:$ptr)]>;
- def STORE3264_v4i32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4I32:$val, MEM3264:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV4I32:$val, ADDR64:$ptr)]>;
- def STORE3264_v2i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I8:$val, MEM3264:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV2I8:$val, ADDR64:$ptr)]>;
- def STORE3264_v2i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I16:$val, MEM3264:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV2I16:$val, ADDR64:$ptr)]>;
- def STORE3264_v4i8 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4I8:$val, MEM3264:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV4I8:$val, ADDR64:$ptr)]>;
- def STORE3264_v4i16 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV4I16:$val, MEM3264:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV4I16:$val, ADDR64:$ptr)]>;
- def STORE3264_v2i32 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I32:$val, MEM3264:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV2I32:$val, ADDR64:$ptr)]>;
- def STORE3264_v2f64 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2F64:$val, MEM3264:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV2F64:$val, ADDR64:$ptr)]>;
- def STORE3264_v2i64 : OneInOneOut<IL_OP_MOV, (outs), (ins GPRV2I64:$val, MEM3264:$ptr),
- !strconcat(asm, " $val $ptr"),
- [(OpNode GPRV2I64:$val, ADDR64:$ptr)]>;
- */
+ def v2f64 : ILFormat<IL_OP_MOV, (outs GPRV2F64:$dst),
+ (ins v2f64imm:$val),
+ asm, [(set GPRV2F64:$dst, fpimm:$val)]>;
+}
+
+multiclass StoreMC<string asm, PatFrag opn,
+ RegisterClass reg, Operand oper, ValueType type, SDNode imm0,
+ Operand mem, ComplexPattern addr>
+{
+ def r : ILFormat<IL_OP_MOV, (outs), (ins reg:$val, mem:$ptr),
+ !strconcat(asm, " $val $ptr"), [(opn (type reg:$val), addr:$ptr)]>;
+ //def i : ILFormat<IL_OP_MOV, (outs), (ins oper:$val, mem:$ptr),
+ //!strconcat(asm, " $val $ptr"), [(opn (type imm0:$val), addr:$ptr)]>;
+}
+
+multiclass LoadMC<string asm, PatFrag opn,
+ RegisterClass reg, Operand oper, ValueType type, SDNode imm0,
+ Operand mem, ComplexPattern addr>
+{
+ def r : ILFormat<IL_OP_MOV, (outs reg:$dst), (ins mem:$ptr),
+ !strconcat(asm, " $dst $ptr"),
+ [(set (type reg:$dst), (opn addr:$ptr))]>;
+}
+
+multiclass GTRUNCSTORE<string asm, Operand mem, ComplexPattern addr> {
+ let store = 1, truncate = 1, global = 1 in {
+ let sub32bit = 1 in {
+ defm i16i8 : StoreMC<asm, global_i8trunc_store, GPRI16, i16imm, i16, imm, mem, addr>;
+ defm i32i8 : StoreMC<asm, global_i8trunc_store, GPRI32, i32imm, i32, imm, mem, addr>;
+ defm i64i8 : StoreMC<asm, global_i8trunc_store, GPRI64, i64imm, i64, imm, mem, addr>;
+ defm i32i16 : StoreMC<asm, global_i16trunc_store, GPRI32, i32imm, i32, imm, mem, addr>;
+ defm i64i16 : StoreMC<asm, global_i16trunc_store, GPRI64, i64imm, i64, imm, mem, addr>;
+ }
+ defm i64i32 : StoreMC<asm, global_i32trunc_store, GPRI64, i64imm, i64, imm, mem, addr>;
+ defm f64f32 : StoreMC<asm, global_f32trunc_store, GPRF64, f64imm, f64, fpimm, mem, addr>;
+ let packed = 1 in {
+ let sub32bit = 1 in {
+ let packType = 0 in {
+ defm v2i16i8 : StoreMC<asm, global_v2i8trunc_store, GPRV2I16, v2i16imm, v2i16, imm, mem, addr>;
+ defm v2i32i8 : StoreMC<asm, global_v2i8trunc_store, GPRV2I32, v2i32imm, v2i32, imm, mem, addr>;
+ defm v2i64i8 : StoreMC<asm, global_v2i8trunc_store, GPRV2I64, v2i64imm, v2i64, imm, mem, addr>;
+ }
+ }
+ let packType = 2 in {
+ defm v4i16i8 : StoreMC<asm, global_v4i8trunc_store, GPRV4I16, v4i16imm, v4i16, imm, mem, addr>;
+ defm v4i32i8 : StoreMC<asm, global_v4i8trunc_store, GPRV4I32, v4i32imm, v4i32, imm, mem, addr>;
+ }
+ let packType = 1 in {
+ defm v2i32i16 : StoreMC<asm, global_v2i16trunc_store, GPRV2I32, v2i32imm, v2i32, imm, mem, addr>;
+ defm v2i64i16 : StoreMC<asm, global_v2i16trunc_store, GPRV2I64, v2i64imm, v2i64, imm, mem, addr>;
+ }
+ let packType = 3 in {
+ defm v4i32i16 : StoreMC<asm, global_v4i16trunc_store, GPRV4I32, v4i32imm, v4i32, imm, mem, addr>;
+ }
+ }
+ defm v2f64f32 : StoreMC<asm, global_v2f32trunc_store, GPRV2F64, v2f64imm, v2f64, fpimm, mem, addr>;
+ defm v2i64i32 : StoreMC<asm, global_v2i32trunc_store, GPRV2I64, v2i64imm, v2i64, imm, mem, addr>;
+ }
+}
+
+multiclass PTRUNCSTORE<string asm, Operand mem, ComplexPattern addr> {
+ let store = 1, truncate = 1, private = 1 in {
+ let sub32bit = 1 in {
+ defm i16i8 : StoreMC<asm, private_i8trunc_store, GPRI16, i16imm, i16, imm, mem, addr>;
+ defm i32i8 : StoreMC<asm, private_i8trunc_store, GPRI32, i32imm, i32, imm, mem, addr>;
+ defm i64i8 : StoreMC<asm, private_i8trunc_store, GPRI64, i64imm, i64, imm, mem, addr>;
+ defm i32i16 : StoreMC<asm, private_i16trunc_store, GPRI32, i32imm, i32, imm, mem, addr>;
+ defm i64i16 : StoreMC<asm, private_i16trunc_store, GPRI64, i64imm, i64, imm, mem, addr>;
+ }
+ defm i64i32 : StoreMC<asm, private_i32trunc_store, GPRI64, i64imm, i64, imm, mem, addr>;
+ defm f64f32 : StoreMC<asm, private_f32trunc_store, GPRF64, f64imm, f64, fpimm, mem, addr>;
+ let packed = 1 in {
+ let sub32bit = 1 in {
+ let packType = 0 in {
+ defm v2i16i8 : StoreMC<asm, private_v2i8trunc_store, GPRV2I16, v2i16imm, v2i16, imm, mem, addr>;
+ defm v2i32i8 : StoreMC<asm, private_v2i8trunc_store, GPRV2I32, v2i32imm, v2i32, imm, mem, addr>;
+ defm v2i64i8 : StoreMC<asm, private_v2i8trunc_store, GPRV2I64, v2i64imm, v2i64, imm, mem, addr>;
+ }
+ }
+ let packType = 2 in {
+ defm v4i16i8 : StoreMC<asm, private_v4i8trunc_store, GPRV4I16, v4i16imm, v4i16, imm, mem, addr>;
+ defm v4i32i8 : StoreMC<asm, private_v4i8trunc_store, GPRV4I32, v4i32imm, v4i32, imm, mem, addr>;
+ }
+ let packType = 1 in {
+ defm v2i32i16 : StoreMC<asm, private_v2i16trunc_store, GPRV2I32, v2i32imm, v2i32, imm, mem, addr>;
+ defm v2i64i16 : StoreMC<asm, private_v2i16trunc_store, GPRV2I64, v2i64imm, v2i64, imm, mem, addr>;
+ }
+ let packType = 3 in {
+ defm v4i32i16 : StoreMC<asm, private_v4i16trunc_store, GPRV4I32, v4i32imm, v4i32, imm, mem, addr>;
+ }
+ }
+ defm v2f64f32 : StoreMC<asm, private_v2f32trunc_store, GPRV2F64, v2f64imm, v2f64, fpimm, mem, addr>;
+ defm v2i64i32 : StoreMC<asm, private_v2i32trunc_store, GPRV2I64, v2i64imm, v2i64, imm, mem, addr>;
+ }
+}
+
+multiclass LTRUNCSTORE<string asm, Operand mem, ComplexPattern addr> {
+ let store = 1, truncate = 1, local = 1 in {
+ let sub32bit = 1 in {
+ defm i16i8 : StoreMC<asm, local_i8trunc_store, GPRI16, i16imm, i16, imm, mem, addr>;
+ defm i32i8 : StoreMC<asm, local_i8trunc_store, GPRI32, i32imm, i32, imm, mem, addr>;
+ defm i64i8 : StoreMC<asm, local_i8trunc_store, GPRI64, i64imm, i64, imm, mem, addr>;
+ defm i32i16 : StoreMC<asm, local_i16trunc_store, GPRI32, i32imm, i32, imm, mem, addr>;
+ defm i64i16 : StoreMC<asm, local_i16trunc_store, GPRI64, i64imm, i64, imm, mem, addr>;
+ }
+ defm i64i32 : StoreMC<asm, local_i32trunc_store, GPRI64, i64imm, i64, imm, mem, addr>;
+ defm f64f32 : StoreMC<asm, local_f32trunc_store, GPRF64, f64imm, f64, fpimm, mem, addr>;
+ let packed = 1 in {
+ let sub32bit = 1 in {
+ let packType = 0 in {
+ defm v2i16i8 : StoreMC<asm, local_v2i8trunc_store, GPRV2I16, v2i16imm, v2i16, imm, mem, addr>;
+ defm v2i32i8 : StoreMC<asm, local_v2i8trunc_store, GPRV2I32, v2i32imm, v2i32, imm, mem, addr>;
+ defm v2i64i8 : StoreMC<asm, local_v2i8trunc_store, GPRV2I64, v2i64imm, v2i64, imm, mem, addr>;
+ }
+ }
+ let packType = 2 in {
+ defm v4i16i8 : StoreMC<asm, local_v4i8trunc_store, GPRV4I16, v4i16imm, v4i16, imm, mem, addr>;
+ defm v4i32i8 : StoreMC<asm, local_v4i8trunc_store, GPRV4I32, v4i32imm, v4i32, imm, mem, addr>;
+ }
+ let packType = 1 in {
+ defm v2i32i16 : StoreMC<asm, local_v2i16trunc_store, GPRV2I32, v2i32imm, v2i32, imm, mem, addr>;
+ defm v2i64i16 : StoreMC<asm, local_v2i16trunc_store, GPRV2I64, v2i64imm, v2i64, imm, mem, addr>;
+ }
+ let packType = 3 in {
+ defm v4i32i16 : StoreMC<asm, local_v4i16trunc_store, GPRV4I32, v4i32imm, v4i32, imm, mem, addr>;
+ }
+ }
+ defm v2f64f32 : StoreMC<asm, local_v2f32trunc_store, GPRV2F64, v2f64imm, v2f64, fpimm, mem, addr>;
+ defm v2i64i32 : StoreMC<asm, local_v2i32trunc_store, GPRV2I64, v2i64imm, v2i64, imm, mem, addr>;
+ }
+}
+
+multiclass RTRUNCSTORE<string asm, Operand mem, ComplexPattern addr> {
+ let store = 1, truncate = 1, region = 1 in {
+ let sub32bit = 1 in {
+ defm i16i8 : StoreMC<asm, region_i8trunc_store, GPRI16, i16imm, i16, imm, mem, addr>;
+ defm i32i8 : StoreMC<asm, region_i8trunc_store, GPRI32, i32imm, i32, imm, mem, addr>;
+ defm i64i8 : StoreMC<asm, region_i8trunc_store, GPRI64, i64imm, i64, imm, mem, addr>;
+ defm i32i16 : StoreMC<asm, region_i16trunc_store, GPRI32, i32imm, i32, imm, mem, addr>;
+ defm i64i16 : StoreMC<asm, region_i16trunc_store, GPRI64, i64imm, i64, imm, mem, addr>;
+ }
+ defm i64i32 : StoreMC<asm, region_i32trunc_store, GPRI64, i64imm, i64, imm, mem, addr>;
+ defm f64f32 : StoreMC<asm, region_f32trunc_store, GPRF64, f64imm, f64, fpimm, mem, addr>;
+ let packed = 1 in {
+ let sub32bit = 1 in {
+ let packType = 0 in {
+ defm v2i16i8 : StoreMC<asm, region_v2i8trunc_store, GPRV2I16, v2i16imm, v2i16, imm, mem, addr>;
+ defm v2i32i8 : StoreMC<asm, region_v2i8trunc_store, GPRV2I32, v2i32imm, v2i32, imm, mem, addr>;
+ defm v2i64i8 : StoreMC<asm, region_v2i8trunc_store, GPRV2I64, v2i64imm, v2i64, imm, mem, addr>;
+ }
+ }
+ let packType = 2 in {
+ defm v4i16i8 : StoreMC<asm, region_v4i8trunc_store, GPRV4I16, v4i16imm, v4i16, imm, mem, addr>;
+ defm v4i32i8 : StoreMC<asm, region_v4i8trunc_store, GPRV4I32, v4i32imm, v4i32, imm, mem, addr>;
+ }
+ let packType = 1 in {
+ defm v2i32i16 : StoreMC<asm, region_v2i16trunc_store, GPRV2I32, v2i32imm, v2i32, imm, mem, addr>;
+ defm v2i64i16 : StoreMC<asm, region_v2i16trunc_store, GPRV2I64, v2i64imm, v2i64, imm, mem, addr>;
+ }
+ let packType = 3 in {
+ defm v4i32i16 : StoreMC<asm, region_v4i16trunc_store, GPRV4I32, v4i32imm, v4i32, imm, mem, addr>;
+ }
+ }
+ defm v2f64f32 : StoreMC<asm, region_v2f32trunc_store, GPRV2F64, v2f64imm, v2f64, fpimm, mem, addr>;
+ defm v2i64i32 : StoreMC<asm, region_v2i32trunc_store, GPRV2I64, v2i64imm, v2i64, imm, mem, addr>;
+ }
+}
+
+multiclass STORE<string asm, PatFrag opn, Operand mem, ComplexPattern addr> {
+ let store = 1 in {
+ let sub32bit = 1 in {
+ defm i8 : StoreMC<asm, opn, GPRI8, i8imm, i8, imm, mem, addr>;
+ defm i16 : StoreMC<asm, opn, GPRI16, i16imm, i16, imm, mem, addr>;
+ }
+ defm i32 : StoreMC<asm, opn, GPRI32, i32imm, i32, imm, mem, addr>;
+ defm v2i32 : StoreMC<asm, opn, GPRV2I32, v2i32imm, v2i32, imm, mem, addr>;
+ defm v4i32 : StoreMC<asm, opn, GPRV4I32, v4i32imm, v4i32, imm, mem, addr>;
+ defm i64 : StoreMC<asm, opn, GPRI64, i64imm, i64, imm, mem, addr>;
+ defm v2i64 : StoreMC<asm, opn, GPRV2I64, v2i64imm, v2i64, imm, mem, addr>;
+ defm f32 : StoreMC<asm, opn, GPRF32, f32imm, f32, fpimm, mem, addr>;
+ defm v2f32 : StoreMC<asm, opn, GPRV2F32, v2f32imm, v2f32, fpimm, mem, addr>;
+ defm v4f32 : StoreMC<asm, opn, GPRV4F32, v4f32imm, v4f32, fpimm, mem, addr>;
+ defm f64 : StoreMC<asm, opn, GPRF64, f64imm, f64, fpimm, mem, addr>;
+ defm v2f64 : StoreMC<asm, opn, GPRV2F64, v2f64imm, v2f64, fpimm, mem, addr>;
+ let packed = 1 in {
+ let sub32bit = 1, packType = 1 in {
+ defm v2i16 : StoreMC<asm, opn, GPRV2I16, v2i16imm, v2i16, imm, mem, addr>;
+ }
+ let packType = 3 in {
+ defm v4i16 : StoreMC<asm, opn, GPRV4I16, v4i16imm, v4i16, imm, mem, addr>;
+ }
+ let packType = 0 in {
+ defm v2i8 : StoreMC<asm, opn, GPRV2I8, v2i8imm, v2i8, imm, mem, addr>;
+ }
+ let packType = 2 in {
+ defm v4i8 : StoreMC<asm, opn, GPRV4I8, v4i8imm, v4i8, imm, mem, addr>;
+ }
+ }
+ }
}
// Multiclass that handles load operations
-multiclass LOAD64<string asm, PatFrag OpNode> {
- def LOAD64_i8 : OneInOneOut<IL_OP_MOV, (outs GPRI8:$dst), (ins MEM6464:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRI8:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD64_i16 : OneInOneOut<IL_OP_MOV, (outs GPRI16:$dst), (ins MEM6464:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRI16:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD64_i32 : OneInOneOut<IL_OP_MOV, (outs GPRI32:$dst), (ins MEM6464:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRI32:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD64_f32 : OneInOneOut<IL_OP_MOV, (outs GPRF32:$dst), (ins MEM6464:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRF32:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD64_i64 : OneInOneOut<IL_OP_MOV, (outs GPRI64:$dst), (ins MEM6464:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRI64:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD64_f64 : OneInOneOut<IL_OP_MOV, (outs GPRF64:$dst), (ins MEM6464:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRF64:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD64_v4f32 : OneInOneOut<IL_OP_MOV, (outs GPRV4F32:$dst), (ins MEM6464:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV4F32:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD64_v2f32 : OneInOneOut<IL_OP_MOV, (outs GPRV2F32:$dst), (ins MEM6464:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV2F32:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD64_v2f64 : OneInOneOut<IL_OP_MOV, (outs GPRV2F64:$dst), (ins MEM6464:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV2F64:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD64_v4i32 : OneInOneOut<IL_OP_MOV, (outs GPRV4I32:$dst), (ins MEM6464:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV4I32:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD64_v2i8 : OneInOneOut<IL_OP_MOV, (outs GPRV2I8:$dst), (ins MEM6464:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV2I8:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD64_v2i16 : OneInOneOut<IL_OP_MOV, (outs GPRV2I16:$dst), (ins MEM6464:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV2I16:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD64_v4i8 : OneInOneOut<IL_OP_MOV, (outs GPRV4I8:$dst), (ins MEM6464:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV4I8:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD64_v4i16 : OneInOneOut<IL_OP_MOV, (outs GPRV4I16:$dst), (ins MEM6464:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV4I16:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD64_v2i32 : OneInOneOut<IL_OP_MOV, (outs GPRV2I32:$dst), (ins MEM6464:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV2I32:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD64_v2i64 : OneInOneOut<IL_OP_MOV, (outs GPRV2I64:$dst), (ins MEM6464:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV2I64:$dst, (OpNode ADDR64:$ptr))]>;
-/*
- def LOAD6432_i8 : OneInOneOut<IL_OP_MOV, (outs GPRI8:$dst), (ins MEM6432:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRI8:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD6432_i16 : OneInOneOut<IL_OP_MOV, (outs GPRI16:$dst), (ins MEM6432:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRI16:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD6432_i32 : OneInOneOut<IL_OP_MOV, (outs GPRI32:$dst), (ins MEM6432:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRI32:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD6432_f32 : OneInOneOut<IL_OP_MOV, (outs GPRF32:$dst), (ins MEM6432:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRF32:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD6432_i64 : OneInOneOut<IL_OP_MOV, (outs GPRI64:$dst), (ins MEM6432:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRI64:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD6432_f64 : OneInOneOut<IL_OP_MOV, (outs GPRF64:$dst), (ins MEM6432:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRF64:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD6432_v4f32 : OneInOneOut<IL_OP_MOV, (outs GPRV4F32:$dst), (ins MEM6432:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV4F32:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD6432_v2f32 : OneInOneOut<IL_OP_MOV, (outs GPRV2F32:$dst), (ins MEM6432:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV2F32:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD6432_v2f64 : OneInOneOut<IL_OP_MOV, (outs GPRV2F64:$dst), (ins MEM6432:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV2F64:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD6432_v4i32 : OneInOneOut<IL_OP_MOV, (outs GPRV4I32:$dst), (ins MEM6432:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV4I32:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD6432_v2i8 : OneInOneOut<IL_OP_MOV, (outs GPRV2I8:$dst), (ins MEM6432:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV2I8:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD6432_v2i16 : OneInOneOut<IL_OP_MOV, (outs GPRV2I16:$dst), (ins MEM6432:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV2I16:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD6432_v4i8 : OneInOneOut<IL_OP_MOV, (outs GPRV4I8:$dst), (ins MEM6432:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV4I8:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD6432_v4i16 : OneInOneOut<IL_OP_MOV, (outs GPRV4I16:$dst), (ins MEM6432:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV4I16:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD6432_v2i32 : OneInOneOut<IL_OP_MOV, (outs GPRV2I32:$dst), (ins MEM6432:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV2I32:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD6432_v2i64 : OneInOneOut<IL_OP_MOV, (outs GPRV2I64:$dst), (ins MEM6432:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV2I64:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD3264_i8 : OneInOneOut<IL_OP_MOV, (outs GPRI8:$dst), (ins MEM3264:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRI8:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD3264_i16 : OneInOneOut<IL_OP_MOV, (outs GPRI16:$dst), (ins MEM3264:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRI16:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD3264_i32 : OneInOneOut<IL_OP_MOV, (outs GPRI32:$dst), (ins MEM3264:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRI32:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD3264_f32 : OneInOneOut<IL_OP_MOV, (outs GPRF32:$dst), (ins MEM3264:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRF32:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD3264_i64 : OneInOneOut<IL_OP_MOV, (outs GPRI64:$dst), (ins MEM3264:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRI64:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD3264_f64 : OneInOneOut<IL_OP_MOV, (outs GPRF64:$dst), (ins MEM3264:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRF64:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD3264_v4f32 : OneInOneOut<IL_OP_MOV, (outs GPRV4F32:$dst), (ins MEM3264:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV4F32:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD3264_v2f32 : OneInOneOut<IL_OP_MOV, (outs GPRV2F32:$dst), (ins MEM3264:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV2F32:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD3264_v2f64 : OneInOneOut<IL_OP_MOV, (outs GPRV2F64:$dst), (ins MEM3264:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV2F64:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD3264_v4i32 : OneInOneOut<IL_OP_MOV, (outs GPRV4I32:$dst), (ins MEM3264:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV4I32:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD3264_v2i8 : OneInOneOut<IL_OP_MOV, (outs GPRV2I8:$dst), (ins MEM3264:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV2I8:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD3264_v2i16 : OneInOneOut<IL_OP_MOV, (outs GPRV2I16:$dst), (ins MEM3264:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV2I16:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD3264_v4i8 : OneInOneOut<IL_OP_MOV, (outs GPRV4I8:$dst), (ins MEM3264:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV4I8:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD3264_v4i16 : OneInOneOut<IL_OP_MOV, (outs GPRV4I16:$dst), (ins MEM3264:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV4I16:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD3264_v2i32 : OneInOneOut<IL_OP_MOV, (outs GPRV2I32:$dst), (ins MEM3264:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV2I32:$dst, (OpNode ADDR64:$ptr))]>;
- def LOAD3264_v2i64 : OneInOneOut<IL_OP_MOV, (outs GPRV2I64:$dst), (ins MEM3264:$ptr),
- !strconcat(asm, " $dst $ptr"),
- [(set GPRV2I64:$dst, (OpNode ADDR64:$ptr))]>;
- */
+multiclass LOAD<string asm, PatFrag opn, Operand mem, ComplexPattern addr> {
+ let load = 1 in {
+ let swsextload = 1 in {
+ defm i8 : LoadMC<asm, opn, GPRI8, i8imm, i8, imm, mem, addr>;
+ defm i16 : LoadMC<asm, opn, GPRI16, i16imm, i16, imm, mem, addr>;
+ let packed = 1 in {
+ let packType = 0 in {
+ defm v2i8 : LoadMC<asm, opn, GPRV2I8, v2i8imm, v2i8, imm, mem, addr>;
+ }
+ let packType = 2 in {
+ defm v4i8 : LoadMC<asm, opn, GPRV4I8, v4i8imm, v4i8, imm, mem, addr>;
+ }
+ let packType = 1 in {
+ defm v2i16 : LoadMC<asm, opn, GPRV2I16, v2i16imm, v2i16, imm, mem, addr>;
+ }
+ let packType = 3 in {
+ defm v4i16 : LoadMC<asm, opn, GPRV4I16, v4i16imm, v4i16, imm, mem, addr>;
+ }
+ }
+ }
+ defm f32 : LoadMC<asm, opn, GPRF32, f32imm, f32, imm, mem, addr>;
+ defm i32 : LoadMC<asm, opn, GPRI32, i32imm, i32, imm, mem, addr>;
+ defm i64 : LoadMC<asm, opn, GPRI64, i64imm, i64, imm, mem, addr>;
+ defm f64 : LoadMC<asm, opn, GPRF64, f64imm, f64, imm, mem, addr>;
+ defm v2f32 : LoadMC<asm, opn, GPRV2F32, v2f32imm, v2f32, imm, mem, addr>;
+ defm v2i32 : LoadMC<asm, opn, GPRV2I32, v2i32imm, v2i32, imm, mem, addr>;
+ defm v2i64 : LoadMC<asm, opn, GPRV2I64, v2i64imm, v2i64, imm, mem, addr>;
+ defm v2f64 : LoadMC<asm, opn, GPRV2F64, v2f64imm, v2f64, imm, mem, addr>;
+ defm v4f32 : LoadMC<asm, opn, GPRV4F32, v4f32imm, v4f32, imm, mem, addr>;
+ defm v4i32 : LoadMC<asm, opn, GPRV4I32, v4i32imm, v4i32, imm, mem, addr>;
+ }
+}
+
+multiclass UAVRawLSInst<RegisterClass reg, string str> {
+ let rawuav = 1 in {
+ let mayLoad = 1, load = 1 in {
+ def LOADi32 : ILFormat<IL_OP_RAW_UAV_LOAD, (outs GPRI32:$dst),
+ (ins reg:$addy, i32imm:$id),
+ !strconcat(IL_OP_RAW_UAV_LOAD.Text, !strconcat(str, " $dst, $addy")), []>;
+ def LOADv2i32 : ILFormat<IL_OP_RAW_UAV_LOAD, (outs GPRV2I32:$dst),
+ (ins reg:$addy, i32imm:$id),
+ !strconcat(IL_OP_RAW_UAV_LOAD.Text, !strconcat(str, " $dst, $addy")), []>;
+ def LOADv4i32 : ILFormat<IL_OP_RAW_UAV_LOAD, (outs GPRV4I32:$dst),
+ (ins reg:$addy, i32imm:$id),
+ !strconcat(IL_OP_RAW_UAV_LOAD.Text, !strconcat(str, " $dst, $addy")), []>;
+ def LOADCACHEDi32 : ILFormat<IL_OP_RAW_UAV_LOAD, (outs GPRI32:$dst),
+ (ins reg:$addy, i32imm:$id),
+ !strconcat(IL_OP_RAW_UAV_LOAD.Text, !strconcat(str, "_cached $dst, $addy")), []>;
+ def LOADCACHEDv2i32 : ILFormat<IL_OP_RAW_UAV_LOAD, (outs GPRV2I32:$dst),
+ (ins reg:$addy, i32imm:$id),
+ !strconcat(IL_OP_RAW_UAV_LOAD.Text, !strconcat(str, "_cached $dst, $addy")), []>;
+ def LOADCACHEDv4i32 : ILFormat<IL_OP_RAW_UAV_LOAD, (outs GPRV4I32:$dst),
+ (ins reg:$addy, i32imm:$id),
+ !strconcat(IL_OP_RAW_UAV_LOAD.Text, !strconcat(str, "_cached $dst, $addy")), []>;
+ def LOADCACHEDALIGNEDv2i32 : ILFormat<IL_OP_RAW_UAV_LOAD, (outs GPRV2I32:$dst),
+ (ins reg:$addy, i32imm:$id),
+ !strconcat(IL_OP_RAW_UAV_LOAD.Text, !strconcat(str, "_cached_aligned $dst, $addy")), []>;
+ def LOADCACHEDALIGNEDv4i32 : ILFormat<IL_OP_RAW_UAV_LOAD, (outs GPRV4I32:$dst),
+ (ins reg:$addy, i32imm:$id),
+ !strconcat(IL_OP_RAW_UAV_LOAD.Text, !strconcat(str, "_cached_aligned $dst, $addy")), []>;
+ let Predicates = [IsSIOrLaterDevice] in {
+ def LOADi8 : ILFormat<IL_OP_UAV_BYTE_LOAD, (outs GPRI32:$dst),
+ (ins reg:$addy, i32imm:$id),
+ !strconcat(IL_OP_UAV_BYTE_LOAD.Text, !strconcat(str, " $dst, $addy")), []>;
+ def LOADu8 : ILFormat<IL_OP_UAV_UBYTE_LOAD, (outs GPRI32:$dst),
+ (ins reg:$addy, i32imm:$id),
+ !strconcat(IL_OP_UAV_UBYTE_LOAD.Text, !strconcat(str, " $dst, $addy")), []>;
+ def LOADi16 : ILFormat<IL_OP_UAV_SHORT_LOAD, (outs GPRI32:$dst),
+ (ins reg:$addy, i32imm:$id),
+ !strconcat(IL_OP_UAV_SHORT_LOAD.Text, !strconcat(str, " $dst, $addy")), []>;
+ def LOADu16 : ILFormat<IL_OP_UAV_USHORT_LOAD, (outs GPRI32:$dst),
+ (ins reg:$addy, i32imm:$id),
+ !strconcat(IL_OP_UAV_USHORT_LOAD.Text, !strconcat(str, " $dst, $addy")), []>;
+ def LOADCACHEDi8 : ILFormat<IL_OP_UAV_BYTE_LOAD, (outs GPRI32:$dst),
+ (ins reg:$addy, i32imm:$id),
+ !strconcat(IL_OP_UAV_BYTE_LOAD.Text, !strconcat(str, "_cached $dst, $addy")), []>;
+ def LOADCACHEDu8 : ILFormat<IL_OP_UAV_UBYTE_LOAD, (outs GPRI32:$dst),
+ (ins reg:$addy, i32imm:$id),
+ !strconcat(IL_OP_UAV_UBYTE_LOAD.Text, !strconcat(str, "_cached $dst, $addy")), []>;
+ def LOADCACHEDi16 : ILFormat<IL_OP_UAV_SHORT_LOAD, (outs GPRI32:$dst),
+ (ins reg:$addy, i32imm:$id),
+ !strconcat(IL_OP_UAV_SHORT_LOAD.Text, !strconcat(str, "_cached $dst, $addy")), []>;
+ def LOADCACHEDu16 : ILFormat<IL_OP_UAV_USHORT_LOAD, (outs GPRI32:$dst),
+ (ins reg:$addy, i32imm:$id),
+ !strconcat(IL_OP_UAV_USHORT_LOAD.Text, !strconcat(str, "_cached $dst, $addy")), []>;
+ }
+
+ }
+ let mayStore = 1, store = 1 in {
+ def STOREi32 : ILFormat<IL_OP_RAW_UAV_STORE, (outs GPRI32:$mem),
+ (ins reg:$addy, GPRI32:$src, i32imm:$id),
+ !strconcat(IL_OP_RAW_UAV_STORE.Text, !strconcat(str, " $mem, $addy, $src")), []>;
+ def STOREv2i32 : ILFormat<IL_OP_RAW_UAV_STORE, (outs GPRV2I32:$mem),
+ (ins reg:$addy, GPRV2I32:$src, i32imm:$id),
+ !strconcat(IL_OP_RAW_UAV_STORE.Text, !strconcat(str, " $mem, $addy, $src")), []>;
+ def STOREv4i32 : ILFormat<IL_OP_RAW_UAV_STORE, (outs GPRV4I32:$mem),
+ (ins reg:$addy, GPRV4I32:$src, i32imm:$id),
+ !strconcat(IL_OP_RAW_UAV_STORE.Text, !strconcat(str, " $mem, $addy, $src")), []>;
+ let Predicates = [IsSIOrLaterDevice] in {
+ def STOREi8 : ILFormat<IL_OP_UAV_BYTE_STORE, (outs GPRI32:$mem),
+ (ins reg:$addy, GPRI32:$src, i32imm:$id),
+ !strconcat(IL_OP_UAV_BYTE_STORE.Text, !strconcat(str, " $mem, $addy, $src")), []>;
+ def STOREi16 : ILFormat<IL_OP_UAV_SHORT_STORE, (outs GPRI32:$mem),
+ (ins reg:$addy, GPRI32:$src, i32imm:$id),
+ !strconcat(IL_OP_UAV_SHORT_STORE.Text, !strconcat(str, " $mem, $addy, $src")), []>;
+
+ }
+ }
+ }
+}
+
+
+multiclass ScratchLSInst<RegisterClass reg> {
+ let scratch = 1 in {
+ let mayLoad = 1, load = 1 in {
+ def LOAD : ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
+ (ins reg:$addy, i32imm:$id),
+ !strconcat(IL_OP_MOV.Text, " $dst, x$id[$addy]"), []>;
+ }
+ let mayStore = 1, store = 1 in {
+ def STORE : ILFormat<IL_OP_MOV, (outs),
+ (ins reg:$addy, GPRV4I32:$data, i32imm:$id),
+ !strconcat(IL_OP_MOV.Text, " x$id[$addy, $data"), []>;
+ }
+ }
+}
+
+multiclass ArenaLSInst<RegisterClass reg> {
+ let arenauav = 1 in {
+ let mayStore = 1, store = 1 in {
+ def STOREi8 : ILFormat<IL_OP_ARENA_UAV_STORE, (outs reg:$addy),
+ (ins GPRI8:$src, i32imm:$id),
+ !strconcat(IL_OP_ARENA_UAV_STORE.Text,
+ "_id($id)_size(byte) $addy, $src"), []>;
+ def STOREi16 : ILFormat<IL_OP_ARENA_UAV_STORE, (outs reg:$addy),
+ (ins GPRI16:$src, i32imm:$id),
+ !strconcat(IL_OP_ARENA_UAV_STORE.Text,
+ "_id($id)_size(short) $addy, $src"), []>;
+ def STOREi32 : ILFormat<IL_OP_ARENA_UAV_STORE, (outs reg:$addy),
+ (ins GPRI32:$src, i32imm:$id),
+ !strconcat(IL_OP_ARENA_UAV_STORE.Text,
+ "_id($id)_size(dword) $addy, $src"), []>;
+ }
+ let mayLoad = 1, load = 1 in {
+ def LOADi8 : ILFormat<IL_OP_ARENA_UAV_LOAD, (outs GPRI8:$dst),
+ (ins reg:$addy, i32imm:$id),
+ !strconcat(IL_OP_ARENA_UAV_LOAD.Text, "_id($id)_size(byte) $dst, $addy"), []>;
+ def LOADi16 : ILFormat<IL_OP_ARENA_UAV_LOAD, (outs GPRI16:$dst),
+ (ins reg:$addy, i32imm:$id),
+ !strconcat(IL_OP_ARENA_UAV_LOAD.Text, "_id($id)_size(short) $dst, $addy"), []>;
+ def LOADi32 : ILFormat<IL_OP_ARENA_UAV_LOAD, (outs GPRI32:$dst),
+ (ins reg:$addy, i32imm:$id),
+ !strconcat(IL_OP_ARENA_UAV_LOAD.Text, "_id($id)_size(dword) $dst, $addy"), []>;
+ }
+ }
+}
+
+multiclass LDSLSInst<RegisterClass reg> {
+ let lds = 1 in {
+ let mayStore = 1, store = 1 in {
+ def STOREi8r : ILFormat<IL_OP_LDS_STORE_BYTE, (outs),
+ (ins reg:$addy, GPRI8:$src, i32imm:$id),
+ !strconcat(IL_OP_LDS_STORE_BYTE.Text, "_id($id) $addy, $src"), []>;
+ def STOREi16r : ILFormat<IL_OP_LDS_STORE_SHORT, (outs),
+ (ins reg:$addy, GPRI16:$src, i32imm:$id),
+ !strconcat(IL_OP_LDS_STORE_SHORT.Text, "_id($id) $addy, $src"), []>;
+ def STOREi32r : ILFormat<IL_OP_LDS_STORE, (outs),
+ (ins reg:$addy, GPRI32:$src, i32imm:$id),
+ !strconcat(IL_OP_LDS_STORE.Text, "_id($id) $addy, $src"), []>;
+ def STOREv2i32r : ILFormat<IL_OP_LDS_STORE_VEC, (outs GPRI32:$mem),
+ (ins reg:$addy, GPRV4I32:$src, i32imm:$id),
+ !strconcat(IL_OP_LDS_STORE_VEC.Text, "_id($id) $mem, $addy, $src, $src"), []>;
+ def STOREv4i32r : ILFormat<IL_OP_LDS_STORE_VEC, (outs GPRI32:$mem),
+ (ins reg:$addy, GPRV4I32:$src, i32imm:$id),
+ !strconcat(IL_OP_LDS_STORE_VEC.Text, "_id($id) $mem, $addy, $src, $src"), []>;
+ }
+ let mayLoad = 1, load = 1 in {
+ def LOADu8r : ILFormat<IL_OP_LDS_LOAD_UBYTE, (outs GPRI8:$dst),
+ (ins reg:$addy, i32imm:$id),
+ !strconcat(IL_OP_LDS_LOAD_UBYTE.Text, "_id($id) $dst, $addy"), []>;
+ def LOADi8r : ILFormat<IL_OP_LDS_LOAD_BYTE, (outs GPRI8:$dst),
+ (ins reg:$addy, i32imm:$id),
+ !strconcat(IL_OP_LDS_LOAD_BYTE.Text, "_id($id) $dst, $addy"), []>;
+ def LOADu16r : ILFormat<IL_OP_LDS_LOAD_USHORT, (outs GPRI16:$dst),
+ (ins reg:$addy, i32imm:$id),
+ !strconcat(IL_OP_LDS_LOAD_USHORT.Text, "_id($id) $dst, $addy"), []>;
+ def LOADi16r : ILFormat<IL_OP_LDS_LOAD_SHORT, (outs GPRI16:$dst),
+ (ins reg:$addy, i32imm:$id),
+ !strconcat(IL_OP_LDS_LOAD_SHORT.Text, "_id($id) $dst, $addy"), []>;
+ def LOADi32r : ILFormat<IL_OP_LDS_LOAD, (outs GPRI32:$dst),
+ (ins reg:$addy, i32imm:$id),
+ !strconcat(IL_OP_LDS_LOAD.Text, "_id($id) $dst, $addy"), []>;
+ def LOADv2i32r: ILFormat<IL_OP_LDS_LOAD_VEC, (outs GPRV2I32:$dst),
+ (ins reg:$addy, i32imm:$id),
+ !strconcat(IL_OP_LDS_LOAD_VEC.Text, "_id($id) $dst, $addy, $addy"), []>;
+ def LOADv4i32r: ILFormat<IL_OP_LDS_LOAD_VEC, (outs GPRV4I32:$dst),
+ (ins reg:$addy, i32imm:$id),
+ !strconcat(IL_OP_LDS_LOAD_VEC.Text, "_id($id) $dst, $addy, $addy"), []>;
+ }
+ }
+}
+
+multiclass GDSLSInst<RegisterClass reg> {
+ let gds = 1 in {
+ let mayStore = 1, store = 1 in {
+ def STOREi8r : ILFormat<IL_OP_GDS_STORE_BYTE, (outs),
+ (ins reg:$addy, GPRI8:$src, i32imm:$id),
+ !strconcat(IL_OP_GDS_STORE_BYTE.Text, "_id($id) $addy, $src"), []>;
+ def STOREi16r : ILFormat<IL_OP_GDS_STORE_SHORT, (outs),
+ (ins reg:$addy, GPRI16:$src, i32imm:$id),
+ !strconcat(IL_OP_GDS_STORE_SHORT.Text, "_id($id) $addy, $src"), []>;
+ def STOREi32r : ILFormat<IL_OP_GDS_STORE, (outs),
+ (ins reg:$addy, GPRI32:$src, i32imm:$id),
+ !strconcat(IL_OP_GDS_STORE.Text, "_id($id) $addy, $src"), []>;
+ }
+ let mayLoad = 1, load = 1 in {
+ def LOADu8r : ILFormat<IL_OP_GDS_LOAD_UBYTE, (outs GPRI8:$dst),
+ (ins reg:$addy, i32imm:$id),
+ !strconcat(IL_OP_GDS_LOAD_UBYTE.Text, "_id($id) $dst, $addy"), []>;
+ def LOADi8r : ILFormat<IL_OP_GDS_LOAD_BYTE, (outs GPRI16:$dst),
+ (ins reg:$addy, i32imm:$id),
+ !strconcat(IL_OP_GDS_LOAD_BYTE.Text, "_id($id) $dst, $addy"), []>;
+ def LOADu16r : ILFormat<IL_OP_GDS_LOAD_USHORT, (outs GPRI32:$dst),
+ (ins reg:$addy, i32imm:$id),
+ !strconcat(IL_OP_GDS_LOAD_USHORT.Text, "_id($id) $dst, $addy"), []>;
+ def LOADi16r : ILFormat<IL_OP_GDS_LOAD_SHORT, (outs GPRI32:$dst),
+ (ins reg:$addy, i32imm:$id),
+ !strconcat(IL_OP_GDS_LOAD_SHORT.Text, "_id($id) $dst, $addy"), []>;
+ def LOADi32r : ILFormat<IL_OP_GDS_LOAD, (outs GPRI32:$dst),
+ (ins reg:$addy, i32imm:$id),
+ !strconcat(IL_OP_GDS_LOAD.Text, "_id($id) $dst, $addy"), []>;
+ }
+ }
+}
+multiclass IMAGEINFO0<Operand mem, ComplexPattern addr> {
+ let image = 1, info = 1 in {
+ def I1D: ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
+ (ins mem:$ptr),
+ !strconcat(IL_OP_MOV.Text, " $dst, $ptr"),
+ [(set GPRV4I32:$dst, (int_AMDIL_image1d_info0 addr:$ptr))]>;
+ def I1DA: ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
+ (ins mem:$ptr),
+ !strconcat(IL_OP_MOV.Text, " $dst, $ptr"),
+ [(set GPRV4I32:$dst, (int_AMDIL_image1d_array_info0 addr:$ptr))]>;
+ def I1DB: ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
+ (ins mem:$ptr),
+ !strconcat(IL_OP_MOV.Text, " $dst, $ptr"),
+ [(set GPRV4I32:$dst, (int_AMDIL_image1d_buffer_info0 addr:$ptr))]>;
+ def I2D: ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
+ (ins mem:$ptr),
+ !strconcat(IL_OP_MOV.Text, " $dst, $ptr"),
+ [(set GPRV4I32:$dst, (int_AMDIL_image2d_info0 addr:$ptr))]>;
+ def I2DA: ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
+ (ins mem:$ptr),
+ !strconcat(IL_OP_MOV.Text, " $dst, $ptr"),
+ [(set GPRV4I32:$dst, (int_AMDIL_image2d_array_info0 addr:$ptr))]>;
+ def I3D: ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
+ (ins mem:$ptr),
+ !strconcat(IL_OP_MOV.Text, " $dst, $ptr"),
+ [(set GPRV4I32:$dst, (int_AMDIL_image3d_info0 addr:$ptr))]>;
+ }
+}
+multiclass IMAGEINFO1<Operand mem, ComplexPattern addr> {
+ let image = 1, info = 2 in {
+ def I1D: ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
+ (ins mem:$ptr),
+ !strconcat(IL_OP_MOV.Text, " $dst, $ptr"),
+ [(set GPRV4I32:$dst, (int_AMDIL_image1d_info1 addr:$ptr))]>;
+ def I1DA: ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
+ (ins mem:$ptr),
+ !strconcat(IL_OP_MOV.Text, " $dst, $ptr"),
+ [(set GPRV4I32:$dst, (int_AMDIL_image1d_array_info1 addr:$ptr))]>;
+ def I1DB: ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
+ (ins mem:$ptr),
+ !strconcat(IL_OP_MOV.Text, " $dst, $ptr"),
+ [(set GPRV4I32:$dst, (int_AMDIL_image1d_buffer_info1 addr:$ptr))]>;
+ def I2D: ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
+ (ins mem:$ptr),
+ !strconcat(IL_OP_MOV.Text, " $dst, $ptr"),
+ [(set GPRV4I32:$dst, (int_AMDIL_image2d_info1 addr:$ptr))]>;
+ def I2DA: ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
+ (ins mem:$ptr),
+ !strconcat(IL_OP_MOV.Text, " $dst, $ptr"),
+ [(set GPRV4I32:$dst, (int_AMDIL_image2d_array_info1 addr:$ptr))]>;
+ def I3D: ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
+ (ins mem:$ptr),
+ !strconcat(IL_OP_MOV.Text, " $dst, $ptr"),
+ [(set GPRV4I32:$dst, (int_AMDIL_image3d_info1 addr:$ptr))]>;
+ }
+}
+multiclass IMAGEREAD<Operand mem, ComplexPattern addr> {
+ let image = 1, load = 1 in {
+ def I1D : ILFormat<IL_OP_SAMPLE, (outs GPRV4I32:$dst),
+ (ins mem:$ptr, GPRI32:$sampler, GPRV4F32:$addy),
+ !strconcat(IL_OP_SAMPLE.Text,
+ "_id($ptr)_sampler($sampler)_coordtype(normalized) $dst, $addy"),
+ [(set GPRV4I32:$dst,
+ (int_AMDIL_image1d_read_norm addr:$ptr, GPRI32:$sampler, GPRV4F32:$addy))]>;
+ def I1DA : ILFormat<IL_OP_SAMPLE, (outs GPRV4I32:$dst),
+ (ins mem:$ptr, GPRI32:$sampler, GPRV4F32:$addy),
+ !strconcat(IL_OP_SAMPLE.Text,
+ "_id($ptr)_sampler($sampler)_coordtype(normalized) $dst, $addy"),
+ [(set GPRV4I32:$dst,
+ (int_AMDIL_image1d_array_read_norm addr:$ptr, GPRI32:$sampler, GPRV4F32:$addy))]>;
+ def I1DB : ILFormat<IL_OP_SAMPLE, (outs GPRV4I32:$dst),
+ (ins mem:$ptr, GPRI32:$sampler, GPRV4F32:$addy),
+ !strconcat(IL_OP_SAMPLE.Text,
+ "_id($ptr)_sampler($sampler)_coordtype(normalized) $dst, $addy"),
+ [(set GPRV4I32:$dst,
+ (int_AMDIL_image1d_buffer_read_norm addr:$ptr, GPRI32:$sampler, GPRV4F32:$addy))]>;
+ def I2D : ILFormat<IL_OP_SAMPLE, (outs GPRV4I32:$dst),
+ (ins mem:$ptr, GPRI32:$sampler, GPRV4F32:$addy),
+ !strconcat(IL_OP_SAMPLE.Text,
+ "_id($ptr)_sampler($sampler)_coordtype(normalized) $dst, $addy"),
+ [(set GPRV4I32:$dst,
+ (int_AMDIL_image2d_read_norm addr:$ptr, GPRI32:$sampler, GPRV4F32:$addy))]>;
+ def I2DA : ILFormat<IL_OP_SAMPLE, (outs GPRV4I32:$dst),
+ (ins mem:$ptr, GPRI32:$sampler, GPRV4F32:$addy),
+ !strconcat(IL_OP_SAMPLE.Text,
+ "_id($ptr)_sampler($sampler)_coordtype(normalized) $dst, $addy"),
+ [(set GPRV4I32:$dst,
+ (int_AMDIL_image2d_array_read_norm addr:$ptr, GPRI32:$sampler, GPRV4F32:$addy))]>;
+ def I3D : ILFormat<IL_OP_SAMPLE, (outs GPRV4I32:$dst),
+ (ins mem:$ptr, GPRI32:$sampler, GPRV4F32:$addy),
+ !strconcat(IL_OP_SAMPLE.Text,
+ "_id($ptr)_sampler($sampler)_coordtype(normalized) $dst, $addy"),
+ [(set GPRV4I32:$dst,
+ (int_AMDIL_image3d_read_norm addr:$ptr, GPRI32:$sampler, GPRV4F32:$addy))]>;
+ def I1D_UNNORM : ILFormat<IL_OP_SAMPLE, (outs GPRV4I32:$dst),
+ (ins mem:$ptr, GPRI32:$sampler, GPRV4F32:$addy),
+ !strconcat(IL_OP_SAMPLE.Text,
+ "_id($ptr)_sampler($sampler)_coordtype(unnormalized) $dst, $addy"),
+ [(set GPRV4I32:$dst,
+ (int_AMDIL_image1d_read_unnorm addr:$ptr, GPRI32:$sampler, GPRV4F32:$addy))]>;
+ def I1DA_UNNORM : ILFormat<IL_OP_SAMPLE, (outs GPRV4I32:$dst),
+ (ins mem:$ptr, GPRI32:$sampler, GPRV4F32:$addy),
+ !strconcat(IL_OP_SAMPLE.Text,
+ "_id($ptr)_sampler($sampler)_coordtype(unnormalized) $dst, $addy"),
+ [(set GPRV4I32:$dst,
+ (int_AMDIL_image1d_array_read_unnorm addr:$ptr, GPRI32:$sampler, GPRV4F32:$addy))]>;
+ def I1DB_UNNORM : ILFormat<IL_OP_SAMPLE, (outs GPRV4I32:$dst),
+ (ins mem:$ptr, GPRI32:$sampler, GPRV4F32:$addy),
+ !strconcat(IL_OP_SAMPLE.Text,
+ "_id($ptr)_sampler($sampler)_coordtype(unnormalized) $dst, $addy"),
+ [(set GPRV4I32:$dst,
+ (int_AMDIL_image1d_buffer_read_unnorm addr:$ptr, GPRI32:$sampler, GPRV4F32:$addy))]>;
+ def I2D_UNNORM : ILFormat<IL_OP_SAMPLE, (outs GPRV4I32:$dst),
+ (ins mem:$ptr, GPRI32:$sampler, GPRV4F32:$addy),
+ !strconcat(IL_OP_SAMPLE.Text,
+ "_id($ptr)_sampler($sampler)_coordtype(unnormalized) $dst, $addy"),
+ [(set GPRV4I32:$dst,
+ (int_AMDIL_image2d_read_unnorm addr:$ptr, GPRI32:$sampler, GPRV4F32:$addy))]>;
+ def I2DA_UNNORM : ILFormat<IL_OP_SAMPLE, (outs GPRV4I32:$dst),
+ (ins mem:$ptr, GPRI32:$sampler, GPRV4F32:$addy),
+ !strconcat(IL_OP_SAMPLE.Text,
+ "_id($ptr)_sampler($sampler)_coordtype(unnormalized) $dst, $addy"),
+ [(set GPRV4I32:$dst,
+ (int_AMDIL_image2d_array_read_unnorm addr:$ptr, GPRI32:$sampler, GPRV4F32:$addy))]>;
+ def I3D_UNNORM : ILFormat<IL_OP_SAMPLE, (outs GPRV4I32:$dst),
+ (ins mem:$ptr, GPRI32:$sampler, GPRV4F32:$addy),
+ !strconcat(IL_OP_SAMPLE.Text,
+ "_id($ptr)_sampler($sampler)_coordtype(unnormalized) $dst, $addy"),
+ [(set GPRV4I32:$dst,
+ (int_AMDIL_image3d_read_unnorm addr:$ptr, GPRI32:$sampler, GPRV4F32:$addy))]>;
+ }
+}
+multiclass IMAGEWRITE<Operand mem, ComplexPattern addr> {
+ let image = 1, store = 1 in {
+ def I1D: ILFormat<IL_OP_UAV_STORE, (outs),
+ (ins mem:$ptr, GPRV2I32:$addy, GPRV4I32:$data),
+ !strconcat(IL_OP_UAV_STORE.Text,
+ "_id($ptr) $addy, $data"),
+ [(int_AMDIL_image1d_write addr:$ptr, GPRV2I32:$addy, GPRV4I32:$data)]>;
+ def I1DA: ILFormat<IL_OP_UAV_STORE, (outs),
+ (ins mem:$ptr, GPRV2I32:$addy, GPRV4I32:$data),
+ !strconcat(IL_OP_UAV_STORE.Text,
+ "_id($ptr) $addy, $data"),
+ [(int_AMDIL_image1d_array_write addr:$ptr, GPRV2I32:$addy, GPRV4I32:$data)]>;
+ def I1DB: ILFormat<IL_OP_UAV_STORE, (outs),
+ (ins mem:$ptr, GPRV2I32:$addy, GPRV4I32:$data),
+ !strconcat(IL_OP_UAV_STORE.Text,
+ "_id($ptr) $addy, $data"),
+ [(int_AMDIL_image1d_buffer_write addr:$ptr, GPRV2I32:$addy, GPRV4I32:$data)]>;
+ def I2D: ILFormat<IL_OP_UAV_STORE, (outs),
+ (ins mem:$ptr, GPRV2I32:$addy, GPRV4I32:$data),
+ !strconcat(IL_OP_UAV_STORE.Text,
+ "_id($ptr) $addy, $data"),
+ [(int_AMDIL_image2d_write addr:$ptr, GPRV2I32:$addy, GPRV4I32:$data)]>;
+ def I2DA: ILFormat<IL_OP_UAV_STORE, (outs),
+ (ins mem:$ptr, GPRV4I32:$addy, GPRV4I32:$data),
+ !strconcat(IL_OP_UAV_STORE.Text,
+ "_id($ptr) $addy, $data"),
+ [(int_AMDIL_image2d_array_write addr:$ptr, GPRV4I32:$addy, GPRV4I32:$data)]>;
+ def I3D: ILFormat<IL_OP_UAV_STORE, (outs),
+ (ins mem:$ptr, GPRV4I32:$addy, GPRV4I32:$data),
+ !strconcat(IL_OP_UAV_STORE.Text,
+ "_id($ptr) $addy, $data"),
+ [(int_AMDIL_image3d_write addr:$ptr, GPRV4I32:$addy, GPRV4I32:$data)]>;
+ }
}
// Only scalar types should generate flow control
multiclass BranchInstr<ILOpCode opc> {
- def _i8 : UnaryOpNoRet<opc, (outs), (ins GPRI8:$src),
- !strconcat(opc.Text, " $src"), []>;
- def _i16 : UnaryOpNoRet<opc, (outs), (ins GPRI16:$src),
- !strconcat(opc.Text, " $src"), []>;
- def _i32 : UnaryOpNoRet<opc, (outs), (ins GPRI32:$src),
- !strconcat(opc.Text, " $src"), []>;
- def _i64 : UnaryOpNoRet<opc, (outs), (ins GPRI64:$src),
- !strconcat(opc.Text, " $src"), []>;
- def _f32 : UnaryOpNoRet<opc, (outs), (ins GPRF32:$src),
- !strconcat(opc.Text, " $src"), []>;
- def _f64 : UnaryOpNoRet<opc, (outs), (ins GPRF64:$src),
- !strconcat(opc.Text, " $src"), []>;
+ def i8r : ILFormat<opc, (outs), (ins GPRI8:$src0),
+ !strconcat(opc.Text, " $src0"), []>;
+ def i16r : ILFormat<opc, (outs), (ins GPRI16:$src0),
+ !strconcat(opc.Text, " $src0"), []>;
+ def i32r : ILFormat<opc, (outs), (ins GPRI32:$src0),
+ !strconcat(opc.Text, " $src0"), []>;
+ def f32r : ILFormat<opc, (outs), (ins GPRF32:$src0),
+ !strconcat(opc.Text, " $src0"), []>;
+ let swizzle = 2 in {
+ def i64r : ILFormat<opc, (outs), (ins GPRI64:$src0),
+ !strconcat(opc.Text, " $src0"), []>;
+ def f64r : ILFormat<opc, (outs), (ins GPRF64:$src0),
+ !strconcat(opc.Text, " $src0"), []>;
+ }
}
// Only scalar types should generate flow control
multiclass BranchInstr2<ILOpCode opc> {
- def _i8 : BinaryOpNoRet<opc, (outs), (ins GPRI8:$src0, GPRI8:$src1),
+ def i8rr : ILFormat<opc, (outs), (ins GPRI8:$src0, GPRI8:$src1),
!strconcat(opc.Text, " $src0, $src1"), []>;
- def _i16 : BinaryOpNoRet<opc, (outs), (ins GPRI16:$src0, GPRI16:$src1),
+ def i16rr : ILFormat<opc, (outs), (ins GPRI16:$src0, GPRI16:$src1),
!strconcat(opc.Text, " $src0, $src1"), []>;
- def _i32 : BinaryOpNoRet<opc, (outs), (ins GPRI32:$src0, GPRI32:$src1),
+ def i32rr : ILFormat<opc, (outs), (ins GPRI32:$src0, GPRI32:$src1),
!strconcat(opc.Text, " $src0, $src1"), []>;
- def _i64 : BinaryOpNoRet<opc, (outs), (ins GPRI64:$src0, GPRI64:$src1),
+ def f32rr : ILFormat<opc, (outs), (ins GPRF32:$src0, GPRF32:$src1),
!strconcat(opc.Text, " $src0, $src1"), []>;
- def _f32 : BinaryOpNoRet<opc, (outs), (ins GPRF32:$src0, GPRF32:$src1),
+ def i64rr : ILFormat<opc, (outs), (ins GPRI64:$src0, GPRI64:$src1),
!strconcat(opc.Text, " $src0, $src1"), []>;
- def _f64 : BinaryOpNoRet<opc, (outs), (ins GPRF64:$src0, GPRF64:$src1),
+ def f64rr : ILFormat<opc, (outs), (ins GPRF64:$src0, GPRF64:$src1),
!strconcat(opc.Text, " $src0, $src1"), []>;
}
+//===--------------------------------------------------------------------===//
+// The base class for vector extract instructions. The vector extract
+// instructions take as an input value a source register and a 32bit integer
+// with the same encoding as specified in InsertVectorClass and produces
+// a result with only the swizzled component in the destination register.
+//===--------------------------------------------------------------------===//
+
+multiclass ExtractVectorClass<SDNode opn, RegisterClass dreg, ValueType dtype,
+ RegisterClass reg, Operand oper, ValueType type, SDNode imm0>
+{
+ let vector = 1 in {
+ def r : ILFormat<IL_OP_MOV, (outs dreg:$dst),
+ (ins reg:$src, i32imm:$src1),
+ !strconcat(IL_OP_MOV.Text, " $dst, $src"),
+ [(set (dtype dreg:$dst), (opn (type reg:$src), timm:$src1))]>;
+ def i : ILFormat<IL_OP_MOV, (outs dreg:$dst),
+ (ins oper:$src, i32imm:$src1),
+ !strconcat(IL_OP_MOV.Text, " $dst, $src"),
+ [(set (dtype dreg:$dst), (opn (type imm0:$src), timm:$src1))]>;
+ }
+}
// Class that handles the various vector extract patterns
-multiclass VectorExtract<SDNode OpNode> {
- def _v2f64 : ExtractVectorClass<GPRF64, GPRV2F64, OpNode>;
- def _v4f32: ExtractVectorClass<GPRF32, GPRV4F32, OpNode>;
- def _v2f32 : ExtractVectorClass<GPRF32, GPRV2F32, OpNode>;
- def _v2i64 : ExtractVectorClass<GPRI64, GPRV2I64, OpNode>;
- def _v4i8 : ExtractVectorClass<GPRI8, GPRV4I8, OpNode>;
- def _v4i16 : ExtractVectorClass<GPRI16, GPRV4I16, OpNode>;
- def _v4i32 : ExtractVectorClass<GPRI32, GPRV4I32, OpNode>;
- def _v2i8 : ExtractVectorClass<GPRI8, GPRV2I8, OpNode>;
- def _v2i16 : ExtractVectorClass<GPRI16, GPRV2I16, OpNode>;
- def _v2i32 : ExtractVectorClass<GPRI32, GPRV2I32, OpNode>;
-}
-
-multiclass VectorConcat<SDNode OpNode> {
- def _v2f64 : VectorConcatClass<GPRV2F64, GPRF64, OpNode>;
- def _v2i64 : VectorConcatClass<GPRV2F64, GPRI64, OpNode>;
- def _v4f32 : VectorConcatClass<GPRV4F32, GPRV2F32, OpNode>;
- def _v4i32 : VectorConcatClass<GPRV4I32, GPRV2I32, OpNode>;
- def _v4i16 : VectorConcatClass<GPRV4I16, GPRV2I16, OpNode>;
- def _v4i8 : VectorConcatClass<GPRV4I8, GPRV2I8, OpNode>;
- def _v2f32 : VectorConcatClass<GPRV2F32, GPRF32, OpNode>;
- def _v2i32 : VectorConcatClass<GPRV2I32, GPRI32, OpNode>;
- def _v2i16 : VectorConcatClass<GPRV2I16, GPRI16, OpNode>;
- def _v2i8 : VectorConcatClass<GPRV2I8, GPRI8, OpNode>;
+multiclass VectorExtract<SDNode opn> {
+ defm v2f64 : ExtractVectorClass<opn, GPRF64, f64, GPRV2F64, v2f64imm, v2f64, fpimm>;
+ defm v4f32 : ExtractVectorClass<opn, GPRF32, f32, GPRV4F32, v4f32imm, v4f32, fpimm>;
+ defm v2f32 : ExtractVectorClass<opn, GPRF32, f32, GPRV2F32, v2f32imm, v2f32, fpimm>;
+ defm v2i64 : ExtractVectorClass<opn, GPRI64, i64, GPRV2I64, v2i64imm, v2i64, imm>;
+ defm v4i8 : ExtractVectorClass<opn, GPRI8, i8, GPRV4I8, v4i8imm, v4i8, imm>;
+ defm v4i16 : ExtractVectorClass<opn, GPRI16, i16, GPRV4I16, v4i16imm, v4i16, imm>;
+ defm v4i32 : ExtractVectorClass<opn, GPRI32, i32, GPRV4I32, v4i32imm, v4i32, imm>;
+ defm v2i8 : ExtractVectorClass<opn, GPRI8, i8, GPRV2I8, v2i8imm, v2i8, imm>;
+ defm v2i16 : ExtractVectorClass<opn, GPRI16, i16, GPRV2I16, v2i16imm, v2i16, imm>;
+ defm v2i32 : ExtractVectorClass<opn, GPRI32, i32, GPRV2I32, v2i32imm, v2i32, imm>;
+}
+//===--------------------------------------------------------------------===//
+// The base class for vector concatenation. This class creates either a vec2
+// or a vec4 of 32bit data types or a vec2 of 64bit data types. This is done
+// by swizzling either the 'x' or 'xy' components of the source operands
+// into the destination register.
+//===--------------------------------------------------------------------===//
+
+multiclass VectorConcatClass<SDNode opn, RegisterClass dreg, ValueType dtype,
+ RegisterClass sreg, Operand soper, ValueType stype, SDNode simm>
+{
+ let vector = 1 in {
+ def rr : ILFormat<IL_OP_I_ADD, (outs dreg:$dst), (ins sreg:$src0, sreg:$src1),
+ !strconcat(IL_OP_I_ADD.Text, " $dst, $src0, $src1"),
+ [(set (dtype dreg:$dst), (opn (stype sreg:$src0), (stype sreg:$src1)))]>;
+ def ir : ILFormat<IL_OP_I_ADD, (outs dreg:$dst), (ins soper:$src0, sreg:$src1),
+ !strconcat(IL_OP_I_ADD.Text, " $dst, $src0, $src1"),
+ [(set (dtype dreg:$dst), (opn (stype simm:$src0), (stype sreg:$src1)))]>;
+ def ri : ILFormat<IL_OP_I_ADD, (outs dreg:$dst), (ins sreg:$src0, soper:$src1),
+ !strconcat(IL_OP_I_ADD.Text, " $dst, $src0, $src1"),
+ [(set (dtype dreg:$dst), (opn (stype sreg:$src0), (stype simm:$src1)))]>;
+ def ii : ILFormat<IL_OP_I_ADD, (outs dreg:$dst), (ins soper:$src0, soper:$src1),
+ !strconcat(IL_OP_I_ADD.Text, " $dst, $src0, $src1"),
+ [(set (dtype dreg:$dst), (opn (stype simm:$src0), (stype simm:$src1)))]>;
+ }
+}
+
+multiclass VectorConcat<SDNode opn> {
+ defm v2f64 : VectorConcatClass<opn, GPRV2F64, v2f64, GPRF64, f64imm, f64, fpimm>;
+ defm v2i64 : VectorConcatClass<opn, GPRV2I64, v2i64, GPRI64, i64imm, i64, imm>;
+ defm v4f32 : VectorConcatClass<opn, GPRV4F32, v4f32, GPRV2F32, v2f32imm, v2f32, fpimm>;
+ defm v4i32 : VectorConcatClass<opn, GPRV4I32, v4i32, GPRV2I32, v2i32imm, v2i32, imm>;
+ defm v4i16 : VectorConcatClass<opn, GPRV4I16, v4i16, GPRV2I16, v2i16imm, v2i16, imm>;
+ defm v4i8 : VectorConcatClass<opn, GPRV4I8, v4i8, GPRV2I8, v2i8imm, v2i8, imm>;
+ defm v2f32 : VectorConcatClass<opn, GPRV2F32, v2f32, GPRF32, f32imm, f32, fpimm>;
+ defm v2i32 : VectorConcatClass<opn, GPRV2I32, v2i32, GPRI32, i32imm, i32, imm>;
+ defm v2i16 : VectorConcatClass<opn, GPRV2I16, v2i16, GPRI16, i16imm, i16, imm>;
+ defm v2i8 : VectorConcatClass<opn, GPRV2I8, v2i8, GPRI8, i8imm, i8, imm>;
+}
+//===--------------------------------------------------------------------===//
+// The base class for vector insert instructions. It is a single dest, quad
+// source instruction where the last two source operands must be 32bit
+// immediate values that are encoding the swizzle of the source register
+// The src2 and src3 instructions must also be inversion of each other such
+// that if src2 is 0x1000300(x0z0), src3 must be 0x20004(0y0w). The values
+// are encoded as 32bit integer with each 8 char representing a swizzle value.
+// The encoding is as follows for 32bit register types:
+// 0x00 -> '_'
+// 0x01 -> 'x'
+// 0x02 -> 'y'
+// 0x03 -> 'z'
+// 0x04 -> 'w'
+// 0x05 -> 'x'
+// 0x06 -> 'y'
+// 0x07 -> 'z'
+// 0x08 -> 'w'
+// 0x09 -> '0'
+// The encoding is as follows for 64bit register types:
+// 0x00 -> "__"
+// 0x01 -> "xy"
+// 0x02 -> "zw"
+// 0x03 -> "xy"
+// 0x04 -> "zw"
+// 0x05 -> "00"
+//===--------------------------------------------------------------------===//
+
+multiclass InsertVectorClass<SDNode opn,
+ RegisterClass sreg, Operand soper, ValueType stype, SDNode simm,
+ RegisterClass sreg1, Operand soper1, ValueType stype1, SDNode simm1>
+{
+ let vector = 1 in {
+ def rr : ILFormat<IL_OP_I_ADD, (outs sreg:$dst), (ins sreg:$src0, sreg1:$src1, i32imm:$src2, i32imm:$src3),
+ !strconcat(IL_OP_I_ADD.Text, " $dst, $src0, $src1"),
+ [(set (stype sreg:$dst), (opn (stype sreg:$src0), (stype1 sreg1:$src1), timm:$src2, timm:$src3))]>;
+ def ir : ILFormat<IL_OP_I_ADD, (outs sreg:$dst), (ins soper:$src0, sreg1:$src1, i32imm:$src2, i32imm:$src3),
+ !strconcat(IL_OP_I_ADD.Text, " $dst, $src0, $src1"),
+ [(set (stype sreg:$dst), (opn (stype simm:$src0), (stype1 sreg1:$src1), timm:$src2, timm:$src3))]>;
+ def ri : ILFormat<IL_OP_I_ADD, (outs sreg:$dst), (ins sreg:$src0, soper1:$src1, i32imm:$src2, i32imm:$src3),
+ !strconcat(IL_OP_I_ADD.Text, " $dst, $src0, $src1"),
+ [(set (stype sreg:$dst), (opn (stype sreg:$src0), (stype1 simm1:$src1), timm:$src2, timm:$src3))]>;
+ def ii : ILFormat<IL_OP_I_ADD, (outs sreg:$dst), (ins soper:$src0, soper1:$src1, i32imm:$src2, i32imm:$src3),
+ !strconcat(IL_OP_I_ADD.Text, " $dst, $src0, $src1"),
+ [(set (stype sreg:$dst), (opn (stype simm:$src0), (stype1 simm1:$src1), timm:$src2, timm:$src3))]>;
+ }
}
// Class that handles the various vector insert patterns
-multiclass VectorInsert<SDNode OpNode> {
- def _v2f64 : InsertVectorClass<IL_OP_I_ADD, GPRV2F64,
- GPRF64, OpNode, "iadd">;
- def _v4f32: InsertVectorClass<IL_OP_I_ADD, GPRV4F32,
- GPRF32, OpNode, "iadd">;
- def _v2f32 : InsertVectorClass<IL_OP_I_ADD, GPRV2F32,
- GPRF32, OpNode, "iadd">;
- def _v2i64 : InsertVectorClass<IL_OP_I_ADD, GPRV2I64,
- GPRI64, OpNode, "iadd">;
- def _v4i8 : InsertVectorClass<IL_OP_I_ADD, GPRV4I8,
- GPRI8, OpNode, "iadd">;
- def _v4i16 : InsertVectorClass<IL_OP_I_ADD, GPRV4I16,
- GPRI16, OpNode, "iadd">;
- def _v4i32 : InsertVectorClass<IL_OP_I_ADD, GPRV4I32,
- GPRI32, OpNode, "iadd">;
- def _v2i8 : InsertVectorClass<IL_OP_I_ADD, GPRV2I8,
- GPRI8, OpNode, "iadd">;
- def _v2i16 : InsertVectorClass<IL_OP_I_ADD, GPRV2I16,
- GPRI16, OpNode, "iadd">;
- def _v2i32 : InsertVectorClass<IL_OP_I_ADD, GPRV2I32,
- GPRI32, OpNode, "iadd">;
-}
-
-// generic class that handles math instruction for OneInOneOut instruction
-// patterns
-multiclass UnaryOpMC<ILOpCode OpCode, SDNode OpNode> {
- def _i8 : UnaryOp<OpCode, OpNode, GPRI8, GPRI8>;
- def _i16 : UnaryOp<OpCode, OpNode, GPRI16, GPRI16>;
- def _i32 : UnaryOp<OpCode, OpNode, GPRI32, GPRI32>;
- def _f32 : UnaryOp<OpCode, OpNode, GPRF32, GPRF32>;
- def _f64 : UnaryOp<OpCode, OpNode, GPRF64, GPRF64>;
- def _i64 : UnaryOp<OpCode, OpNode, GPRI64, GPRI64>;
- def _v4f32: UnaryOp<OpCode, OpNode, GPRV4F32, GPRV4F32>;
- def _v4i16 : UnaryOp<OpCode, OpNode, GPRV4I16, GPRV4I16>;
- def _v4i8 : UnaryOp<OpCode, OpNode, GPRV4I8, GPRV4I8>;
- def _v4i32 : UnaryOp<OpCode, OpNode, GPRV4I32, GPRV4I32>;
- def _v2f32 : UnaryOp<OpCode, OpNode, GPRV2F32, GPRV2F32>;
- def _v2i16 : UnaryOp<OpCode, OpNode, GPRV2I16, GPRV2I16>;
- def _v2i8 : UnaryOp<OpCode, OpNode, GPRV2I8, GPRV2I8>;
- def _v2i32 : UnaryOp<OpCode, OpNode, GPRV2I32, GPRV2I32>;
- def _v2f64 : UnaryOp<OpCode, OpNode, GPRV2F64, GPRV2F64>;
- def _v2i64 : UnaryOp<OpCode, OpNode, GPRV2I64, GPRV2I64>;
-}
-multiclass UnaryOpMCVec<ILOpCode OpCode, SDNode OpNode> {
- def _v4f32: UnaryOp<OpCode, OpNode, GPRV4F32, GPRF32>;
- def _v4i16 : UnaryOp<OpCode, OpNode, GPRV4I16, GPRI16>;
- def _v4i8 : UnaryOp<OpCode, OpNode, GPRV4I8, GPRI8>;
- def _v4i32 : UnaryOp<OpCode, OpNode, GPRV4I32, GPRI32>;
- def _v2f32 : UnaryOp<OpCode, OpNode, GPRV2F32, GPRF32>;
- def _v2i16 : UnaryOp<OpCode, OpNode, GPRV2I16, GPRI16>;
- def _v2i8 : UnaryOp<OpCode, OpNode, GPRV2I8, GPRI8>;
- def _v2i32 : UnaryOp<OpCode, OpNode, GPRV2I32, GPRI32>;
- def _v2f64 : UnaryOp<OpCode, OpNode, GPRV2F64, GPRF64>;
- def _v2i64 : UnaryOp<OpCode, OpNode, GPRV2I64, GPRI64>;
-}
-
-multiclass UnaryOpMCf32< ILOpCode f32OpCode, SDNode OpNode> {
- def _f32 : UnaryOp<f32OpCode, OpNode, GPRF32, GPRF32>;
- def _v4f32: UnaryOp<f32OpCode, OpNode, GPRV4F32, GPRV4F32>;
- def _v2f32 : UnaryOp<f32OpCode, OpNode, GPRV2F32, GPRV2F32>;
-}
-
-
-multiclass UnaryOpMCf64<ILOpCode f64OpCode, SDNode OpNode> {
- def _f64 : UnaryOp<f64OpCode, OpNode, GPRF64, GPRF64>;
-}
-
-multiclass UnaryOpMCi32< ILOpCode i32OpCode, SDNode OpNode> {
- def _i8 : UnaryOp<i32OpCode, OpNode, GPRI8, GPRI8>;
- def _i16 : UnaryOp<i32OpCode, OpNode, GPRI16, GPRI16>;
- def _i32 : UnaryOp<i32OpCode, OpNode, GPRI32, GPRI32>;
- def _v4i16 : UnaryOp<i32OpCode, OpNode, GPRV4I16, GPRV4I16>;
- def _v4i8 : UnaryOp<i32OpCode, OpNode, GPRV4I8, GPRV4I8>;
- def _v4i32 : UnaryOp<i32OpCode, OpNode, GPRV4I32, GPRV4I32>;
- def _v2i16 : UnaryOp<i32OpCode, OpNode, GPRV2I16, GPRV2I16>;
- def _v2i8 : UnaryOp<i32OpCode, OpNode, GPRV2I8, GPRV2I8>;
- def _v2i32 : UnaryOp<i32OpCode, OpNode, GPRV2I32, GPRV2I32>;
-}
-
-
-multiclass BinaryOpMC<ILOpCode OpCode, SDNode OpNode> {
- def _i8 : BinaryOp<OpCode, OpNode, GPRI8, GPRI8, GPRI8>;
-
- def _i16 : BinaryOp<OpCode, OpNode, GPRI16, GPRI16, GPRI16>;
- def _i32 : BinaryOp<OpCode, OpNode, GPRI32, GPRI32, GPRI32>;
- def _f32 : BinaryOp<OpCode, OpNode, GPRF32, GPRF32, GPRF32>;
- def _f64 : BinaryOp<OpCode, OpNode, GPRF64, GPRF64, GPRF64>;
- def _i64 : BinaryOp<OpCode, OpNode, GPRI64, GPRI64, GPRI64>;
- def _v4f32: BinaryOp<OpCode, OpNode, GPRV4F32, GPRV4F32, GPRV4F32>;
- def _v4i16 : BinaryOp<OpCode, OpNode, GPRV4I16, GPRV4I16, GPRV4I16>;
- def _v4i8 : BinaryOp<OpCode, OpNode, GPRV4I8, GPRV4I8, GPRV4I8>;
- def _v4i32 : BinaryOp<OpCode, OpNode, GPRV4I32, GPRV4I32, GPRV4I32>;
- def _v2f32 : BinaryOp<OpCode, OpNode, GPRV2F32, GPRV2F32, GPRV2F32>;
- def _v2i16 : BinaryOp<OpCode, OpNode, GPRV2I16, GPRV2I16, GPRV2I16>;
- def _v2i8 : BinaryOp<OpCode, OpNode, GPRV2I8, GPRV2I8, GPRV2I8>;
- def _v2i32 : BinaryOp<OpCode, OpNode, GPRV2I32, GPRV2I32, GPRV2I32>;
- def _v2f64 : BinaryOp<OpCode, OpNode, GPRV2F64, GPRV2F64, GPRV2F64>;
- def _v2i64 : BinaryOp<OpCode, OpNode, GPRV2I64, GPRV2I64, GPRV2I64>;
-}
-
-multiclass BinaryOpMCInt<ILOpCode OpCode, SDNode OpNode> {
- def _i8 : BinaryOp<OpCode, OpNode, GPRI8, GPRI8, GPRI8>;
-
- def _i16 : BinaryOp<OpCode, OpNode, GPRI16, GPRI16, GPRI16>;
- def _i32 : BinaryOp<OpCode, OpNode, GPRI32, GPRI32, GPRI32>;
- def _i64 : BinaryOp<OpCode, OpNode, GPRI64, GPRI64, GPRI64>;
- def _v4i16 : BinaryOp<OpCode, OpNode, GPRV4I16, GPRV4I16, GPRV4I16>;
- def _v4i8 : BinaryOp<OpCode, OpNode, GPRV4I8, GPRV4I8, GPRV4I8>;
- def _v4i32 : BinaryOp<OpCode, OpNode, GPRV4I32, GPRV4I32, GPRV4I32>;
- def _v2i16 : BinaryOp<OpCode, OpNode, GPRV2I16, GPRV2I16, GPRV2I16>;
- def _v2i8 : BinaryOp<OpCode, OpNode, GPRV2I8, GPRV2I8, GPRV2I8>;
- def _v2i32 : BinaryOp<OpCode, OpNode, GPRV2I32, GPRV2I32, GPRV2I32>;
- def _v2i64 : BinaryOp<OpCode, OpNode, GPRV2I64, GPRV2I64, GPRV2I64>;
-}
-
-// generic class that handles math instruction for ThreeInOneOut
-// instruction patterns
-multiclass TernaryOpMC<ILOpCode OpCode, SDNode OpNode> {
- def _i8 : TernaryOp<OpCode, OpNode, GPRI8, GPRI8, GPRI8, GPRI8>;
- def _i16 : TernaryOp<OpCode, OpNode, GPRI16, GPRI16, GPRI16, GPRI16>;
- def _i32 : TernaryOp<OpCode, OpNode, GPRI32, GPRI32, GPRI32, GPRI32>;
- def _f32 : TernaryOp<OpCode, OpNode, GPRF32, GPRF32, GPRF32, GPRF32>;
- def _f64 : TernaryOp<OpCode, OpNode, GPRF64, GPRF64, GPRF64, GPRF64>;
- def _i64 : TernaryOp<OpCode, OpNode, GPRI64, GPRI64, GPRI64, GPRI64>;
- def _v4f32: TernaryOp<OpCode, OpNode, GPRV4F32, GPRV4F32,
- GPRV4F32, GPRV4F32>;
- def _v4i8 : TernaryOp<OpCode, OpNode, GPRV4I8, GPRV4I8,
- GPRV4I8, GPRV4I8>;
- def _v4i16 : TernaryOp<OpCode, OpNode, GPRV4I16, GPRV4I16,
- GPRV4I16, GPRV4I16>;
- def _v4i32 : TernaryOp<OpCode, OpNode, GPRV4I32, GPRV4I32,
- GPRV4I32, GPRV4I32>;
- def _v2f32 : TernaryOp<OpCode, OpNode, GPRV2F32, GPRV2F32,
- GPRV2F32, GPRV2F32>;
- def _v2i8 : TernaryOp<OpCode, OpNode, GPRV2I8, GPRV2I8,
- GPRV2I8, GPRV2I8>;
- def _v2i16 : TernaryOp<OpCode, OpNode, GPRV2I16, GPRV2I16,
- GPRV2I16, GPRV2I16>;
- def _v2i32 : TernaryOp<OpCode, OpNode, GPRV2I32, GPRV2I32,
- GPRV2I32, GPRV2I32>;
- def _v2f64 : TernaryOp<OpCode, OpNode, GPRV2F64, GPRV2F64,
- GPRV2F64, GPRV2F64>;
- def _v2i64 : TernaryOp<OpCode, OpNode, GPRV2I64, GPRV2I64,
- GPRV2I64, GPRV2I64>;
-}
-multiclass BinaryOpMCi32<ILOpCode i32OpCode, SDNode OpNode> {
- def _i8 : BinaryOp<i32OpCode, OpNode, GPRI8, GPRI8, GPRI8>;
- def _i16 : BinaryOp<i32OpCode, OpNode, GPRI16, GPRI16, GPRI16>;
- def _i32 : BinaryOp<i32OpCode, OpNode, GPRI32, GPRI32, GPRI32>;
- def _v4i16 : BinaryOp<i32OpCode, OpNode, GPRV4I16,
- GPRV4I16, GPRV4I16>;
- def _v4i8 : BinaryOp<i32OpCode, OpNode, GPRV4I8,
- GPRV4I8, GPRV4I8>;
- def _v4i32 : BinaryOp<i32OpCode, OpNode, GPRV4I32,
- GPRV4I32, GPRV4I32>;
- def _v2i16 : BinaryOp<i32OpCode, OpNode, GPRV2I16,
- GPRV2I16, GPRV2I16>;
- def _v2i8 : BinaryOp<i32OpCode, OpNode, GPRV2I8,
- GPRV2I8, GPRV2I8>;
- def _v2i32 : BinaryOp<i32OpCode, OpNode, GPRV2I32,
- GPRV2I32, GPRV2I32>;
-}
-multiclass BinaryOpMCi64<ILOpCode i64OpCode, SDNode OpNode> {
- def _i64 : BinaryOp<i64OpCode, OpNode, GPRI64, GPRI64, GPRI64>;
- def _v2i64 : BinaryOp<i64OpCode, OpNode, GPRV2I64,
- GPRV2I64, GPRV2I64>;
-}
-
-multiclass BinaryOpMCf64<ILOpCode f64OpCode, SDNode OpNode> {
- def _f64 : BinaryOp<f64OpCode, OpNode, GPRF64, GPRF64, GPRF64>;
-}
-multiclass BinaryOpMCi32Const<ILOpCode i32OpCode, SDNode OpNode> {
- def _i8 : BinaryOp<i32OpCode, OpNode, GPRI8, GPRI8, GPRI32>;
- def _i16 : BinaryOp<i32OpCode, OpNode, GPRI16, GPRI16, GPRI32>;
- def _i32 : BinaryOp<i32OpCode, OpNode, GPRI32, GPRI32, GPRI32>;
- def _v4i16 : BinaryOp<i32OpCode, OpNode, GPRV4I32,
- GPRV4I32, GPRI32>;
- def _v4i8 : BinaryOp<i32OpCode, OpNode, GPRV4I32,
- GPRV4I32, GPRI32>;
- def _v4i32 : BinaryOp<i32OpCode, OpNode, GPRV4I32,
- GPRV4I32, GPRI32>;
- def _v2i16 : BinaryOp<i32OpCode, OpNode, GPRV2I32,
- GPRV2I32, GPRI32>;
- def _v2i8 : BinaryOp<i32OpCode, OpNode, GPRV2I32,
- GPRV2I32, GPRI32>;
- def _v2i32 : BinaryOp<i32OpCode, OpNode, GPRV2I32,
- GPRV2I32, GPRI32>;
-}
-multiclass BinaryOpMCi64Const<ILOpCode i32OpCode, SDNode OpNode> {
- def _i8i64 : BinaryOp<i32OpCode, OpNode, GPRI8, GPRI8, GPRI64>;
- def _i16i64 : BinaryOp<i32OpCode, OpNode, GPRI16, GPRI16, GPRI64>;
- def _i32i64 : BinaryOp<i32OpCode, OpNode, GPRI32, GPRI32, GPRI64>;
- def _v4i16i64 : BinaryOp<i32OpCode, OpNode, GPRV4I32,
- GPRV4I32, GPRI64>;
- def _v4i8i64 : BinaryOp<i32OpCode, OpNode, GPRV4I32,
- GPRV4I32, GPRI64>;
- def _v4i32i64 : BinaryOp<i32OpCode, OpNode, GPRV4I32,
- GPRV4I32, GPRI64>;
- def _v2i16i64 : BinaryOp<i32OpCode, OpNode, GPRV2I32,
- GPRV2I32, GPRI64>;
- def _v2i8i64 : BinaryOp<i32OpCode, OpNode, GPRV2I32,
- GPRV2I32, GPRI64>;
- def _v2i32i64 : BinaryOp<i32OpCode, OpNode, GPRV2I32,
- GPRV2I32, GPRI64>;
-}
-multiclass BinaryOpMCf32<ILOpCode f32OpCode, SDNode OpNode> {
- def _f32 : BinaryOp<f32OpCode, OpNode, GPRF32,
- GPRF32, GPRF32>;
- def _v4f32: BinaryOp<f32OpCode, OpNode, GPRV4F32,
- GPRV4F32, GPRV4F32>;
- def _v2f32 : BinaryOp<f32OpCode, OpNode, GPRV2F32,
- GPRV2F32, GPRV2F32>;
-}
-
-multiclass TernaryOpMCf64<ILOpCode f64OpCode, SDNode OpNode> {
- def _f64 : TernaryOp<f64OpCode, OpNode, GPRF64,
- GPRF64, GPRF64, GPRF64>;
-}
-
-multiclass TernaryOpMCf32<ILOpCode f32OpCode, SDNode OpNode> {
- def _f32 : TernaryOp<f32OpCode, OpNode, GPRF32,
- GPRF32, GPRF32, GPRF32>;
- def _v4f32: TernaryOp<f32OpCode, OpNode, GPRV4F32,
- GPRV4F32, GPRV4F32, GPRV4F32>;
- def _v2f32 : TernaryOp<f32OpCode, OpNode, GPRV2F32,
- GPRV2F32, GPRV2F32, GPRV2F32>;
-}
-multiclass BinaryOpMCFloat<ILOpCode f32OpCode, ILOpCode f64OpCode,
- SDNode OpNode> {
- def _f64 : BinaryOp<f64OpCode, OpNode, GPRF64,
- GPRF64, GPRF64>;
- def _v2f64 : BinaryOp<f64OpCode, OpNode, GPRV2F64,
- GPRV2F64, GPRV2F64>;
- def _f32 : BinaryOp<f32OpCode, OpNode, GPRF32,
- GPRF32, GPRF32>;
- def _v2f32 : BinaryOp<f32OpCode, OpNode, GPRV2F32,
- GPRV2F32, GPRV2F32>;
- def _v4f32: BinaryOp<f32OpCode, OpNode, GPRV4F32,
- GPRV4F32, GPRV4F32>;
- }
-
-multiclass TernaryOpMCScalar<ILOpCode opcode, SDNode node>
-{
- def _i8: TernaryOp<opcode, node, GPRI8, GPRI8, GPRI8, GPRI8>;
- def _i16: TernaryOp<opcode, node, GPRI16, GPRI8, GPRI16, GPRI16>;
- def _i32: TernaryOp<opcode, node, GPRI32, GPRI8, GPRI32, GPRI32>;
- def _i64: TernaryOp<opcode, node, GPRI64, GPRI8, GPRI64, GPRI64>;
- def _f32: TernaryOp<opcode, node, GPRF32, GPRI8, GPRF32, GPRF32>;
- def _f64: TernaryOp<opcode, node, GPRF64, GPRI8, GPRF64, GPRF64>;
-}
-
-
-multiclass BitConversion<ILOpCode opcode, RegisterClass Regs, SDNode OpNode>
-{
- def _i8 : UnaryOp<opcode, OpNode, Regs, GPRI8>;
- def _i16 : UnaryOp<opcode, OpNode, Regs, GPRI16>;
- def _i32 : UnaryOp<opcode, OpNode, Regs, GPRI32>;
- def _f32 : UnaryOp<opcode, OpNode, Regs, GPRF32>;
- def _i64 : UnaryOp<opcode, OpNode, Regs, GPRI64>;
- def _f64 : UnaryOp<opcode, OpNode, Regs, GPRF64>;
- def _v2i8 : UnaryOp<opcode, OpNode, Regs, GPRV2I8>;
- def _v2i16 : UnaryOp<opcode, OpNode, Regs, GPRV2I16>;
- def _v2i32 : UnaryOp<opcode, OpNode, Regs, GPRV2I32>;
- def _v2f32 : UnaryOp<opcode, OpNode, Regs, GPRV2F32>;
- def _v2i64 : UnaryOp<opcode, OpNode, Regs, GPRV2I64>;
- def _v2f64 : UnaryOp<opcode, OpNode, Regs, GPRV2F64>;
- def _v4i8 : UnaryOp<opcode, OpNode, Regs, GPRV4I8>;
- def _v4i16 : UnaryOp<opcode, OpNode, Regs, GPRV4I16>;
- def _v4i32 : UnaryOp<opcode, OpNode, Regs, GPRV4I32>;
- def _v4f32 : UnaryOp<opcode, OpNode, Regs, GPRV4F32>;
-}
-
-
-multiclass UnaryIntrinsicInt<ILOpCode opcode, Intrinsic intr>
-{
- def _i32 : OneInOneOut<opcode, (outs GPRI32:$dst),
- (ins GPRI32:$src),
- !strconcat(opcode.Text, " $dst, $src"),
- [(set GPRI32:$dst, (intr GPRI32:$src))]>;
- def _v2i32 : OneInOneOut<opcode, (outs GPRV2I32:$dst),
- (ins GPRV2I32:$src),
- !strconcat(opcode.Text, " $dst, $src"),
- [(set GPRV2I32:$dst, (intr GPRV2I32:$src))]>;
- def _v4i32 : OneInOneOut<opcode, (outs GPRV4I32:$dst),
- (ins GPRV4I32:$src),
- !strconcat(opcode.Text, " $dst, $src"),
- [(set GPRV4I32:$dst, (intr GPRV4I32:$src))]>;
+multiclass VectorInsert<SDNode opn> {
+ defm v2f64 : InsertVectorClass<opn, GPRV2F64, v2f64imm, v2f64, fpimm,
+ GPRF64, f64imm, f64, fpimm>;
+ defm v4f32 : InsertVectorClass<opn, GPRV4F32, v4f32imm, v4f32, fpimm,
+ GPRF32, f32imm, f32, fpimm>;
+ defm v2f32 : InsertVectorClass<opn, GPRV2F32, v2f32imm, v2f32, fpimm,
+ GPRF32, f32imm, f32, fpimm>;
+ defm v2i64 : InsertVectorClass<opn, GPRV2I64, v2i64imm, v2i64, imm,
+ GPRI64, i64imm, i64, imm>;
+ defm v4i8 : InsertVectorClass<opn, GPRV4I8, v4i8imm, v4i8, imm,
+ GPRI8, i8imm, i8, imm>;
+ defm v4i16 : InsertVectorClass<opn, GPRV4I16, v4i16imm, v4i16, imm,
+ GPRI16, i16imm, i16, imm>;
+ defm v4i32 : InsertVectorClass<opn, GPRV4I32, v4i32imm, v4i32, imm,
+ GPRI32, i32imm, i32, imm>;
+ defm v2i8 : InsertVectorClass<opn, GPRV2I8, v2i8imm, v2i8, imm,
+ GPRI8, i8imm, i8, imm>;
+ defm v2i16 : InsertVectorClass<opn, GPRV2I16, v2i16imm, v2i16, imm,
+ GPRI16, i16imm, i16, imm>;
+ defm v2i32 : InsertVectorClass<opn, GPRV2I32, v2i32imm, v2i32, imm,
+ GPRI32, i32imm, i32, imm>;
+}
+multiclass ConvertOpMC<ILOpCode opcode, SDNode intr,
+ ValueType dtype, RegisterClass dreg,
+ ValueType stype, RegisterClass sreg, Operand soper, SDNode imm0>
+{
+ def r : ILFormat<opcode, (outs dreg:$dst), (ins sreg:$src0),
+ !strconcat(opcode.Text, " $dst, $src0"),
+ [(set (dtype dreg:$dst), (intr (stype sreg:$src0)))]>;
+ def i : ILFormat<opcode, (outs dreg:$dst), (ins soper:$src0),
+ !strconcat(opcode.Text, " $dst, $src0"),
+ [(set (dtype dreg:$dst), (intr (stype imm0:$src0)))]>;
+}
+
+multiclass VectorCreate<ILOpCode opc, SDNode opn>
+{
+ defm v4f32 : ConvertOpMC<opc, opn, v4f32, GPRV4F32, f32, GPRF32, f32imm, fpimm>;
+ defm v4i16 : ConvertOpMC<opc, opn, v4i16, GPRV4I16, i16, GPRI16, i16imm, imm>;
+ defm v4i8 : ConvertOpMC<opc, opn, v4i8, GPRV4I8, i8, GPRI8, i8imm, imm>;
+ defm v4i32 : ConvertOpMC<opc, opn, v4i32, GPRV4I32, i32, GPRI32, i32imm, imm>;
+ defm v2f32 : ConvertOpMC<opc, opn, v2f32, GPRV2F32, f32, GPRF32, f32imm, fpimm>;
+ defm v2i16 : ConvertOpMC<opc, opn, v2i16, GPRV2I16, i16, GPRI16, i16imm, imm>;
+ defm v2i8 : ConvertOpMC<opc, opn, v2i8, GPRV2I8, i8, GPRI8, i8imm, imm>;
+ defm v2i32 : ConvertOpMC<opc, opn, v2i32, GPRV2I32, i32, GPRI32, i32imm, imm>;
+ defm v2f64 : ConvertOpMC<opc, opn, v2f64, GPRV2F64, f64, GPRF64, f64imm, fpimm>;
+ defm v2i64 : ConvertOpMC<opc, opn, v2i64, GPRV2I64, i64, GPRI64, i64imm, imm>;
+}
+
+multiclass IntToAnyMC<ILOpCode opc, SDNode opn>
+{
+ defm i32 : ConvertOpMC<opc, opn, i32, GPRI32, i32, GPRI32, i32imm, imm>;
+ defm i8 : ConvertOpMC<opc, opn, i8, GPRI8, i32, GPRI32, i32imm, imm>;
+ defm i16 : ConvertOpMC<opc, opn, i16, GPRI16, i32, GPRI32, i32imm, imm>;
+ defm f32 : ConvertOpMC<opc, opn, f32, GPRF32, i32, GPRI32, i32imm, imm>;
+}
+
+multiclass BitConversion<ILOpCode opc, SDNode opn, ValueType t, RegisterClass r>
+{
+ defm i32 : ConvertOpMC<opc, opn, t, r, i32, GPRI32, i32imm, imm>;
+ defm i8 : ConvertOpMC<opc, opn, t, r, i8, GPRI8, i8imm, imm>;
+ defm i16 : ConvertOpMC<opc, opn, t, r, i16, GPRI16, i16imm, imm>;
+ defm f32 : ConvertOpMC<opc, opn, t, r, f32, GPRF32, f32imm, fpimm>;
+ defm i64 : ConvertOpMC<opc, opn, t, r, i64, GPRI64, i64imm, imm>;
+ defm f64 : ConvertOpMC<opc, opn, t, r, f64, GPRF64, f64imm, fpimm>;
+ defm v2i8 : ConvertOpMC<opc, opn, t, r, v2i8, GPRV2I8, v2i8imm, imm>;
+ defm v2i16 : ConvertOpMC<opc, opn, t, r, v2i16, GPRV2I16, v2i16imm, imm>;
+ defm v2i32 : ConvertOpMC<opc, opn, t, r, v2i32, GPRV2I32, v2i32imm, imm>;
+ defm v2i64 : ConvertOpMC<opc, opn, t, r, v2i64, GPRV2I64, v2i64imm, imm>;
+ defm v2f32 : ConvertOpMC<opc, opn, t, r, v2f32, GPRV2F32, v2f32imm, fpimm>;
+ defm v2f64 : ConvertOpMC<opc, opn, t, r, v2f64, GPRV2F64, v2f64imm, fpimm>;
+ defm v4i8 : ConvertOpMC<opc, opn, t, r, v4i8, GPRV4I8, v4i8imm, imm>;
+ defm v4i16 : ConvertOpMC<opc, opn, t, r, v4i16, GPRV4I16, v4i16imm, imm>;
+ defm v4i32 : ConvertOpMC<opc, opn, t, r, v4i32, GPRV4I32, v4i32imm, imm>;
+ defm v4f32 : ConvertOpMC<opc, opn, t, r, v4f32, GPRV4F32, v4f32imm, fpimm>;
+}
+
+
+multiclass ConvertIntMC<ILOpCode opcode, Intrinsic intr,
+ ValueType dtype, RegisterClass dreg,
+ ValueType stype, RegisterClass sreg, Operand oper,
+ SDNode imm0>
+{
+ def r : ILFormat<opcode, (outs dreg:$dst), (ins sreg:$src0),
+ !strconcat(opcode.Text, " $dst, $src0"),
+ [(set (dtype dreg:$dst), (intr (stype sreg:$src0)))]>;
+ def i : ILFormat<opcode, (outs dreg:$dst), (ins oper:$src0),
+ !strconcat(opcode.Text, " $dst, $src0"),
+ [(set (dtype dreg:$dst), (intr (stype imm0:$src0)))]>;
}
multiclass IntrConvertF32TOF16<ILOpCode opcode, Intrinsic intr>
{
- def _i16 : OneInOneOut<opcode, (outs GPRI16:$dst),
- (ins GPRF32:$src),
- !strconcat(opcode.Text, " $dst, $src"),
- [(set GPRI16:$dst, (intr GPRF32:$src))]>;
- def _v2i16 : OneInOneOut<opcode, (outs GPRV2I16:$dst),
- (ins GPRV2F32:$src),
- !strconcat(opcode.Text, " $dst, $src"),
- [(set GPRV2I16:$dst, (intr GPRV2F32:$src))]>;
- def _v4i16 : OneInOneOut<opcode, (outs GPRV4I16:$dst),
- (ins GPRV4F32:$src),
- !strconcat(opcode.Text, " $dst, $src"),
- [(set GPRV4I16:$dst, (intr GPRV4F32:$src))]>;
+ defm i16 : ConvertIntMC<opcode, intr, i16, GPRI16, f32, GPRF32, f32imm, fpimm>;
+ defm v2i16 : ConvertIntMC<opcode, intr, v2i16, GPRV2I16, v2f32, GPRV2F32, v2f32imm, fpimm>;
+ defm v4i16 : ConvertIntMC<opcode, intr, v4i16, GPRV4I16, v4f32, GPRV4F32, v4f32imm, fpimm>;
}
-
multiclass IntrConvertF32TOI32<ILOpCode opcode, Intrinsic intr>
{
- def _i32 : OneInOneOut<opcode, (outs GPRI32:$dst),
- (ins GPRF32:$src),
- !strconcat(opcode.Text, " $dst, $src"),
- [(set GPRI32:$dst, (intr GPRF32:$src))]>;
- def _v2i32 : OneInOneOut<opcode, (outs GPRV2I32:$dst),
- (ins GPRV2F32:$src),
- !strconcat(opcode.Text, " $dst, $src"),
- [(set GPRV2I32:$dst, (intr GPRV2F32:$src))]>;
- def _v4i32 : OneInOneOut<opcode, (outs GPRV4I32:$dst),
- (ins GPRV4F32:$src),
- !strconcat(opcode.Text, " $dst, $src"),
- [(set GPRV4I32:$dst, (intr GPRV4F32:$src))]>;
+ defm i32 : ConvertIntMC<opcode, intr, i32, GPRI32, f32, GPRF32, f32imm, fpimm>;
+ defm v2i32 : ConvertIntMC<opcode, intr, v2i32, GPRV2I32, v2f32, GPRV2F32, v2f32imm, fpimm>;
+ defm v4i32 : ConvertIntMC<opcode, intr, v4i32, GPRV4I32, v4f32, GPRV4F32, v4f32imm, fpimm>;
}
multiclass IntrConvertF64TOI32<ILOpCode opcode, Intrinsic intr>
{
- def _i32 : OneInOneOut<opcode, (outs GPRI32:$dst),
- (ins GPRF64:$src),
- !strconcat(opcode.Text, " $dst, $src"),
- [(set GPRI32:$dst, (intr GPRF64:$src))]>;
- def _v2i32 : OneInOneOut<opcode, (outs GPRV2I32:$dst),
- (ins GPRV2F64:$src),
- !strconcat(opcode.Text, " $dst, $src"),
- [(set GPRV2I32:$dst, (intr GPRV2F64:$src))]>;
+ defm i32 : ConvertIntMC<opcode, intr, i32, GPRI32, f64, GPRF64, f64imm, fpimm>;
+ defm v2i32 : ConvertIntMC<opcode, intr, v2i32, GPRV2I32, v2f64, GPRV2F64, v2f64imm, fpimm>;
}
multiclass IntrConvertF16TOF32<ILOpCode opcode, Intrinsic intr>
{
- def _f32 : OneInOneOut<opcode, (outs GPRF32:$dst),
- (ins GPRI16:$src),
- !strconcat(opcode.Text, " $dst, $src"),
- [(set GPRF32:$dst, (intr GPRI16:$src))]>;
- def _v2f32 : OneInOneOut<opcode, (outs GPRV2F32:$dst),
- (ins GPRV2I16:$src),
- !strconcat(opcode.Text, " $dst, $src"),
- [(set GPRV2F32:$dst, (intr GPRV2I16:$src))]>;
- def _v4f32 : OneInOneOut<opcode, (outs GPRV4F32:$dst),
- (ins GPRV4I16:$src),
- !strconcat(opcode.Text, " $dst, $src"),
- [(set GPRV4F32:$dst, (intr GPRV4I16:$src))]>;
+ defm f32 : ConvertIntMC<opcode, intr, f32, GPRF32, i16, GPRI16, i16imm, imm>;
+ defm v2f32 : ConvertIntMC<opcode, intr, v2f32, GPRV2F32, v2i16, GPRV2I16, v2i16imm, imm>;
+ defm v4f32 : ConvertIntMC<opcode, intr, v4f32, GPRV4F32, v4i16, GPRV4I16, v4i16imm, imm>;
}
multiclass IntrConvertI32TOF32<ILOpCode opcode, Intrinsic intr>
{
- def _f32 : OneInOneOut<opcode, (outs GPRF32:$dst),
+ defm f32 : ConvertIntMC<opcode, intr, f32, GPRF32, i32, GPRI32, i32imm, imm>;
+ defm v2f32 : ConvertIntMC<opcode, intr, v2f32, GPRV2F32, v2i32, GPRV2I32, v2i32imm, imm>;
+ defm v4f32 : ConvertIntMC<opcode, intr, v4f32, GPRV4F32, v4i32, GPRV4I32, v4i32imm, imm>;
+}
+
+multiclass ClassExpandMC<ILOpCode opcode, Intrinsic intr,
+ ValueType stype, RegisterClass sreg, Operand soper, SDNode simm,
+ ValueType dtype, RegisterClass dreg, Operand doper, SDNode dimm>
+{
+ def rr : ILFormat<opcode, (outs dreg:$dst), (ins sreg:$src0, dreg:$src1),
+ !strconcat(opcode.Text, " $dst, $src0, $src1"),
+ [(set (dtype dreg:$dst), (intr (stype sreg:$src0), (dtype dreg:$src1)))]>;
+ def ir : ILFormat<opcode, (outs dreg:$dst), (ins soper:$src0, dreg:$src1),
+ !strconcat(opcode.Text, " $dst, $src0, $src1"),
+ [(set (dtype dreg:$dst), (intr (stype simm:$src0), (dtype dreg:$src1)))]>;
+ def ri : ILFormat<opcode, (outs dreg:$dst), (ins sreg:$src0, doper:$src1),
+ !strconcat(opcode.Text, " $dst, $src0, $src1"),
+ [(set (dtype dreg:$dst), (intr (stype sreg:$src0), (dtype dimm:$src1)))]>;
+ def ii : ILFormat<opcode, (outs dreg:$dst), (ins soper:$src0, doper:$src1),
+ !strconcat(opcode.Text, " $dst, $src0, $src1"),
+ [(set (dtype dreg:$dst), (intr (stype simm:$src0), (dtype dimm:$src1)))]>;
+}
+
+
+multiclass ClassMC<Intrinsic intr>
+{
+ defm f64 : ClassExpandMC<IL_OP_D_CLASS, intr, f64, GPRF64, f64imm, fpimm,
+ i32, GPRI32, i32imm, imm>;
+ defm v2f64 : ClassExpandMC<IL_OP_D_CLASS, intr, v2f64, GPRV2F64, v2f64imm, fpimm,
+ v2i32, GPRV2I32, v2i32imm, imm>;
+ defm f32 : ClassExpandMC<IL_OP_CLASS, intr, f32, GPRF32, f32imm, fpimm,
+ i32, GPRI32, i32imm, imm>;
+ defm v2f32 : ClassExpandMC<IL_OP_CLASS, intr, v2f32, GPRV2F32, v2f32imm, fpimm,
+ v2i32, GPRV2I32, v2i32imm, imm>;
+ defm v4f32 : ClassExpandMC<IL_OP_CLASS, intr, v4f32, GPRV4F32, v4f32imm, fpimm,
+ v4i32, GPRV4I32, v4i32imm, imm>;
+}
+
+
+//----------------------------------------------------------------------------//
+// Multiclasses that deal with one operand instructions.
+//----------------------------------------------------------------------------//
+multiclass UnaryNegReg<ILOpCode opc, SDNode opn,
+ RegisterClass reg, Operand oper, ValueType type, SDNode imm0,
+ string str>
+{
+ def r : ILFormat<opc,
+ (outs reg:$dst),
+ (ins reg:$src0),
+ !strconcat(!strconcat(opc.Text, " $dst, "), str),
+ [(set (type reg:$dst),
+ (opn (type reg:$src0)))]>;
+ def i : ILFormat<opc,
+ (outs reg:$dst),
+ (ins oper:$src0),
+ !strconcat(!strconcat(opc.Text, " $dst, "), str),
+ [(set (type reg:$dst),
+ (opn (type imm0:$src0)))]>;
+}
+
+multiclass UnaryNegExpand<ILOpCode opc, SDNode opn,
+ RegisterClass reg, Operand oper, ValueType type,
+ string str>
+ : UnaryNegReg<opc, opn, reg, oper, type, imm, str>;
+
+ multiclass UnaryNegExpandFP<ILOpCode opc, SDNode opn,
+ RegisterClass reg, Operand oper, ValueType type,
+ string str>
+ : UnaryNegReg<opc, opn, reg, oper, type, fpimm, str>;
+
+ multiclass UnaryNegMCf32<ILOpCode opc, SDNode opn>
+{
+ defm f32 : UnaryNegExpandFP<opc, opn, GPRF32, f32imm,
+ f32, "${src0}_neg(xyzw)">;
+ defm v2f32 : UnaryNegExpandFP<opc, opn, GPRV2F32, v2f32imm,
+ v2f32, "${src0}_neg(xyzw)">;
+ defm v4f32 : UnaryNegExpandFP<opc, opn, GPRV4F32, v4f32imm,
+ v4f32, "${src0}_neg(xyzw)">;
+}
+
+multiclass UnaryNegMCf64<ILOpCode opc, SDNode opn>
+{
+ defm f64 : UnaryNegExpandFP<opc, opn, GPRF64, f64imm,
+ f64, "${src0}_neg(yw)">;
+ defm v2f64 : UnaryNegExpandFP<opc, opn, GPRV2F64, v2f64imm,
+ v2f64, "${src0}_neg(yw)">;
+}
+multiclass UnaryOpMCFull<ILOpCode opc, SDNode opn,
+ ValueType dtype, RegisterClass dreg,
+ ValueType stype0, RegisterClass sreg0, Operand oper0, SDNode imm0>
+{
+ def r : ILFormat<opc, (outs dreg:$dst),
+ (ins sreg0:$src0),
+ !strconcat(opc.Text, " $dst, $src0"),
+ [(set (dtype dreg:$dst),
+ (opn (stype0 sreg0:$src0)))]>;
+ def i : ILFormat<opc, (outs dreg:$dst),
+ (ins oper0:$src0),
+ !strconcat(opc.Text, " $dst, $src0"),
+ [(set (dtype dreg:$dst),
+ (opn (stype0 imm0:$src0)))]>;
+}
+
+
+
+
+multiclass UnaryOpReg<ILOpCode opc, SDNode opn,
+ RegisterClass reg, Operand oper, ValueType type, SDNode imm0>
+ : UnaryOpMCFull<opc, opn, type, reg, type, reg, oper, imm0>;
+
+multiclass UnaryOpExpand<ILOpCode opc, SDNode opn,
+ RegisterClass reg, Operand oper, ValueType type>
+ : UnaryOpReg<opc, opn, reg, oper, type, imm>;
+
+ multiclass UnaryOpExpandFP<ILOpCode opc, SDNode opn,
+ RegisterClass reg, Operand oper, ValueType type>
+ : UnaryOpReg<opc, opn, reg, oper, type, fpimm>;
+
+
+ multiclass UnaryOpMCi8Scalar<ILOpCode opc, SDNode opn>
+{
+ defm i8 : UnaryOpExpand<opc, opn, GPRI8, i8imm, i8>;
+}
+
+multiclass UnaryOpMCi8Vector<ILOpCode opc, SDNode opn>
+{
+ defm v2i8 : UnaryOpExpand<opc, opn, GPRV2I8, v2i8imm, v2i8>;
+ defm v4i8 : UnaryOpExpand<opc, opn, GPRV4I8, v4i8imm, v4i8>;
+}
+
+multiclass UnaryOpMCi16Scalar<ILOpCode opc, SDNode opn>
+{
+ defm i16 : UnaryOpExpand<opc, opn, GPRI16, i16imm, i16>;
+}
+
+multiclass UnaryOpMCi16Vector<ILOpCode opc, SDNode opn>
+{
+ defm v2i16 : UnaryOpExpand<opc, opn, GPRV2I16, v2i16imm, v2i16>;
+ defm v4i16 : UnaryOpExpand<opc, opn, GPRV4I16, v4i16imm, v4i16>;
+}
+
+multiclass UnaryOpMCi32Scalar<ILOpCode opc, SDNode opn>
+{
+ defm i32 : UnaryOpExpand<opc, opn, GPRI32, i32imm, i32>;
+}
+
+multiclass UnaryOpMCi32Vector<ILOpCode opc, SDNode opn>
+{
+ defm v2i32 : UnaryOpExpand<opc, opn, GPRV2I32, v2i32imm, v2i32>;
+ defm v4i32 : UnaryOpExpand<opc, opn, GPRV4I32, v4i32imm, v4i32>;
+}
+
+multiclass UnaryOpMCi64Scalar<ILOpCode opc, SDNode opn>
+{
+ defm i64 : UnaryOpExpand<opc, opn, GPRI64, i64imm, i64>;
+}
+
+multiclass UnaryOpMCi64Vector<ILOpCode opc, SDNode opn>
+{
+ defm v2i64 : UnaryOpExpand<opc, opn, GPRV2I64, v2i64imm, v2i64>;
+}
+
+multiclass UnaryOpMCf32Scalar<ILOpCode opc, SDNode opn>
+{
+ defm f32 : UnaryOpExpandFP<opc, opn, GPRF32, f32imm, f32>;
+}
+
+multiclass UnaryOpMCf32Vector<ILOpCode opc, SDNode opn>
+{
+ defm v2f32 : UnaryOpExpandFP<opc, opn, GPRV2F32, v2f32imm, v2f32>;
+ defm v4f32 : UnaryOpExpandFP<opc, opn, GPRV4F32, v4f32imm, v4f32>;
+}
+
+
+multiclass UnaryOpMCf64Scalar<ILOpCode opc, SDNode opn>
+{
+ defm f64 : UnaryOpExpandFP<opc, opn, GPRF64, f64imm, f64>;
+}
+
+multiclass UnaryOpMCf64Vector<ILOpCode opc, SDNode opn>
+{
+ defm v2f64 : UnaryOpExpandFP<opc, opn, GPRV2F64, v2f64imm, v2f64>;
+}
+
+multiclass UnaryOpMCi32<ILOpCode opc, SDNode opn>
+: UnaryOpMCi32Scalar<opc, opn>, UnaryOpMCi32Vector<opc, opn>,
+ UnaryOpMCi16Scalar<opc, opn>, UnaryOpMCi16Vector<opc, opn>,
+ UnaryOpMCi8Scalar< opc, opn>, UnaryOpMCi8Vector< opc, opn>;
+
+multiclass UnaryOpMCi64<ILOpCode opc, SDNode opn>
+: UnaryOpMCi64Scalar<opc, opn>, UnaryOpMCi64Vector<opc, opn>;
+
+multiclass UnaryOpMCf32<ILOpCode opc, SDNode opn>
+: UnaryOpMCf32Scalar<opc, opn>, UnaryOpMCf32Vector<opc, opn>;
+
+multiclass UnaryOpMCf64<ILOpCode opc, SDNode opn>
+: UnaryOpMCf64Scalar<opc, opn>, UnaryOpMCf64Vector<opc, opn>;
+
+multiclass UnaryOpMCInt<ILOpCode opc, SDNode opn>
+: UnaryOpMCi32<opc, opn> , UnaryOpMCi64<opc, opn>;
+
+multiclass UnaryOpMCFP<ILOpCode opc, SDNode opn>
+: UnaryOpMCf32<opc, opn>, UnaryOpMCf64<opc, opn>;
+
+multiclass UnaryOpMC<ILOpCode opc, SDNode opn>
+: UnaryOpMCInt<opc, opn>, UnaryOpMCFP<opc, opn>;
+
+//----------------------------------------------------------------------------//
+// Multiclasses that deal with one operand intrinsics.
+//----------------------------------------------------------------------------//
+multiclass UnaryIntMCVoid<ILOpCode opc, Intrinsic opn,
+ ValueType stype0, RegisterClass sreg0, Operand oper0, SDNode imm0,
+ string str>
+{
+ def r : ILFormat<opc, (outs), (ins sreg0:$src0),
+ !strconcat(opc.Text, str), [(opn (stype0 sreg0:$src0))]>;
+ def i : ILFormat<opc, (outs), (ins oper0:$src0),
+ !strconcat(opc.Text, str), [(opn (stype0 imm0:$src0))]>;
+}
+multiclass Fence<ILOpCode opc, Intrinsic opn>
+: UnaryIntMCVoid<opc, opn, i32, GPRI32, i32imm, imm, "">;
+multiclass UnaryIntMCFull<ILOpCode opc, Intrinsic opn,
+ ValueType dtype, RegisterClass dreg,
+ ValueType stype0, RegisterClass sreg0, Operand oper0, SDNode imm0>
+{
+ def r : ILFormat<opc, (outs dreg:$dst),
+ (ins sreg0:$src0),
+ !strconcat(opc.Text, " $dst, $src0"),
+ [(set (dtype dreg:$dst),
+ (opn (stype0 sreg0:$src0)))]>;
+ def i : ILFormat<opc, (outs dreg:$dst),
+ (ins oper0:$src0),
+ !strconcat(opc.Text, " $dst, $src0"),
+ [(set (dtype dreg:$dst),
+ (opn (stype0 imm0:$src0)))]>;
+}
+
+multiclass FTZMCReg<ILOpCode opc, Intrinsic opn,
+ RegisterClass reg, Operand oper, ValueType type, SDNode imm0>
+{
+ def r : ILFormat<opc,
+ (outs reg:$dst),
+ (ins reg:$src0),
+ !strconcat(opc.Text, " $dst, $src0, r0.1"),
+ [(set (type reg:$dst),
+ (opn (type reg:$src0)))]>;
+ def i : ILFormat<opc,
+ (outs reg:$dst),
+ (ins oper:$src0),
+ !strconcat(opc.Text, " $dst, $src0, r0.1"),
+ [(set (type reg:$dst),
+ (opn (type imm0:$src0)))]>;
+}
+
+multiclass FTZMC<ILOpCode opc, Intrinsic opn>
+{
+ defm f32 : FTZMCReg<opc, opn, GPRF32, f32imm, f32, fpimm>;
+ defm v2f32 : FTZMCReg<opc, opn, GPRV2F32, v2f32imm, v2f32, fpimm>;
+ defm v4f32 : FTZMCReg<opc, opn, GPRV4F32, v4f32imm, v4f32, fpimm>;
+}
+
+multiclass UnaryIntReg<ILOpCode opc, Intrinsic opn,
+ RegisterClass reg, Operand oper, ValueType type, SDNode imm0>
+{
+ def r : ILFormat<opc,
+ (outs reg:$dst),
+ (ins reg:$src0),
+ !strconcat(opc.Text, " $dst, $src0"),
+ [(set (type reg:$dst),
+ (opn (type reg:$src0)))]>;
+ def i : ILFormat<opc,
+ (outs reg:$dst),
+ (ins oper:$src0),
+ !strconcat(opc.Text, " $dst, $src0"),
+ [(set (type reg:$dst),
+ (opn (type imm0:$src0)))]>;
+}
+
+multiclass UnaryIntExpand<ILOpCode opc, Intrinsic opn,
+ RegisterClass reg, Operand oper, ValueType type>
+ : UnaryIntReg<opc, opn, reg, oper, type, imm>;
+
+ multiclass UnaryIntExpandFP<ILOpCode opc, Intrinsic opn,
+ RegisterClass reg, Operand oper, ValueType type>
+ : UnaryIntReg<opc, opn, reg, oper, type, fpimm>;
+
+
+ multiclass UnaryIntMCi8Scalar<ILOpCode opc, Intrinsic opn>
+{
+ defm i8 : UnaryIntExpand<opc, opn, GPRI8, i8imm, i8>;
+}
+
+multiclass UnaryIntMCi8Vector<ILOpCode opc, Intrinsic opn>
+{
+ defm v2i8 : UnaryIntExpand<opc, opn, GPRV2I8, v2i8imm, v2i8>;
+ defm v4i8 : UnaryIntExpand<opc, opn, GPRV4I8, v4i8imm, v4i8>;
+}
+
+multiclass UnaryIntMCi16Scalar<ILOpCode opc, Intrinsic opn>
+{
+ defm i16 : UnaryIntExpand<opc, opn, GPRI16, i16imm, i16>;
+}
+
+multiclass UnaryIntMCi16Vector<ILOpCode opc, Intrinsic opn>
+{
+ defm v2i16 : UnaryIntExpand<opc, opn, GPRV2I16, v2i16imm, v2i16>;
+ defm v4i16 : UnaryIntExpand<opc, opn, GPRV4I16, v4i16imm, v4i16>;
+}
+
+multiclass UnaryIntMCi32Scalar<ILOpCode opc, Intrinsic opn>
+{
+ defm i32 : UnaryIntExpand<opc, opn, GPRI32, i32imm, i32>;
+}
+
+multiclass UnaryIntMCi32Vector<ILOpCode opc, Intrinsic opn>
+{
+ defm v2i32 : UnaryIntExpand<opc, opn, GPRV2I32, v2i32imm, v2i32>;
+ defm v4i32 : UnaryIntExpand<opc, opn, GPRV4I32, v4i32imm, v4i32>;
+}
+
+multiclass UnaryIntMCi64Scalar<ILOpCode opc, Intrinsic opn>
+{
+ defm i64 : UnaryIntExpand<opc, opn, GPRI64, i64imm, i64>;
+}
+
+multiclass UnaryIntMCi64Vector<ILOpCode opc, Intrinsic opn>
+{
+ defm v2i64 : UnaryIntExpand<opc, opn, GPRV2I64, v2i64imm, v2i64>;
+}
+
+multiclass UnaryIntMCf32Scalar<ILOpCode opc, Intrinsic opn>
+{
+ defm f32 : UnaryIntExpandFP<opc, opn, GPRF32, f32imm, f32>;
+}
+
+multiclass UnaryIntMCf32Vector<ILOpCode opc, Intrinsic opn>
+{
+ defm v2f32 : UnaryIntExpandFP<opc, opn, GPRV2F32, v2f32imm, v2f32>;
+ defm v4f32 : UnaryIntExpandFP<opc, opn, GPRV4F32, v4f32imm, v4f32>;
+}
+
+
+multiclass UnaryIntMCf64Scalar<ILOpCode opc, Intrinsic opn>
+{
+ defm f64 : UnaryIntExpandFP<opc, opn, GPRF64, f64imm, f64>;
+}
+
+multiclass UnaryIntMCf64Vector<ILOpCode opc, Intrinsic opn>
+{
+ defm v2f64 : UnaryIntExpandFP<opc, opn, GPRV2F64, v2f64imm, v2f64>;
+}
+
+multiclass UnaryIntMCi32<ILOpCode opc, Intrinsic opn>
+: UnaryIntMCi32Scalar<opc, opn>, UnaryIntMCi32Vector<opc, opn>,
+ UnaryIntMCi16Scalar<opc, opn>, UnaryIntMCi16Vector<opc, opn>,
+ UnaryIntMCi8Scalar< opc, opn>, UnaryIntMCi8Vector< opc, opn>;
+
+multiclass UnaryIntMCi64<ILOpCode opc, Intrinsic opn>
+: UnaryIntMCi64Scalar<opc, opn>, UnaryIntMCi64Vector<opc, opn>;
+
+multiclass UnaryIntMCf32<ILOpCode opc, Intrinsic opn>
+: UnaryIntMCf32Scalar<opc, opn>, UnaryIntMCf32Vector<opc, opn>;
+
+multiclass UnaryIntMCf64<ILOpCode opc, Intrinsic opn>
+: UnaryIntMCf64Scalar<opc, opn>, UnaryIntMCf64Vector<opc, opn>;
+
+multiclass UnaryIntMCInt<ILOpCode opc, Intrinsic opn>
+: UnaryIntMCi32<opc, opn> , UnaryIntMCi64<opc, opn>;
+
+multiclass UnaryIntMCFP<ILOpCode opc, Intrinsic opn>
+: UnaryIntMCf32<opc, opn>, UnaryIntMCf64<opc, opn>;
+
+multiclass UnaryIntMC<ILOpCode opc, Intrinsic opn>
+: UnaryIntMCInt<opc, opn>, UnaryIntMCFP<opc, opn>;
+
+//----------------------------------------------------------------------------//
+// Multiclasses that deal with one operand pattern fragments.
+//----------------------------------------------------------------------------//
+multiclass UnaryPatReg<ILOpCode opc, PatFrag opn,
+ RegisterClass reg, Operand oper, ValueType type, SDNode imm0>
+{
+ def r : ILFormat<opc,
+ (outs reg:$dst),
+ (ins reg:$src0),
+ !strconcat(opc.Text, " $dst, $src0"),
+ [(set (type reg:$dst),
+ (opn (type reg:$src0)))]>;
+}
+multiclass UnaryNCPatReg<ILOpCode opc, PatFrag opn,
+ RegisterClass reg, Operand oper, ValueType type, SDNode imm0>
+ : UnaryPatReg<opc, opn, reg, oper, type, imm0>
+{
+ def i : ILFormat<opc,
+ (outs reg:$dst),
+ (ins oper:$src0),
+ !strconcat(opc.Text, " $dst, $src0"),
+ [(set (type reg:$dst),
+ (opn (type imm0:$src0)))]>;
+}
+
+multiclass UnaryPatExpand<ILOpCode opc, PatFrag opn,
+ RegisterClass reg, Operand oper, ValueType type>
+ : UnaryNCPatReg<opc, opn, reg, oper, type, imm>;
+
+ multiclass UnaryPatExpandFP<ILOpCode opc, PatFrag opn,
+ RegisterClass reg, Operand oper, ValueType type>
+ : UnaryNCPatReg<opc, opn, reg, oper, type, fpimm>;
+
+
+ multiclass UnaryPatMCi8Scalar<ILOpCode opc, PatFrag opn>
+{
+ defm i8 : UnaryPatExpand<opc, opn, GPRI8, i8imm, i8>;
+}
+
+multiclass NotMCReg<ILOpCode opc, PatFrag opn, PatFrag vopn>
+{
+ defm i8 : UnaryPatReg<opc, vopn, GPRI8, i8imm, i8, imm>;
+ defm v2i8 : UnaryPatReg<opc, vopn, GPRV2I8, v2i8imm, v2i8, imm>;
+ defm v4i8 : UnaryPatReg<opc, vopn, GPRV4I8, v4i8imm, v4i8, imm>;
+ defm i16 : UnaryPatReg<opc, vopn, GPRI16, i16imm, i16, imm>;
+ defm v2i16 : UnaryPatReg<opc, vopn, GPRV2I16, v2i16imm, v2i16, imm>;
+ defm v4i16 : UnaryPatReg<opc, vopn, GPRV4I16, v4i16imm, v4i16, imm>;
+ defm i32 : UnaryPatReg<opc, vopn, GPRI32, i32imm, i32, imm>;
+ defm v2i32 : UnaryPatReg<opc, vopn, GPRV2I32, v2i32imm, v2i32, imm>;
+ defm v4i32 : UnaryPatReg<opc, vopn, GPRV4I32, v4i32imm, v4i32, imm>;
+ defm i64 : UnaryPatReg<opc, vopn, GPRI64, i64imm, i64, imm>;
+ defm v2i64 : UnaryPatReg<opc, vopn, GPRV2I64, v2i64imm, v2i64, imm>;
+}
+
+
+multiclass UnaryPatMCi8Vector<ILOpCode opc, PatFrag opn>
+{
+ defm v2i8 : UnaryPatExpand<opc, opn, GPRV2I8, v2i8imm, v2i8>;
+ defm v4i8 : UnaryPatExpand<opc, opn, GPRV4I8, v4i8imm, v4i8>;
+}
+
+multiclass UnaryPatMCi16Scalar<ILOpCode opc, PatFrag opn>
+{
+ defm i16 : UnaryPatExpand<opc, opn, GPRI16, i16imm, i16>;
+}
+
+multiclass UnaryPatMCi16Vector<ILOpCode opc, PatFrag opn>
+{
+ defm v2i16 : UnaryPatExpand<opc, opn, GPRV2I16, v2i16imm, v2i16>;
+ defm v4i16 : UnaryPatExpand<opc, opn, GPRV4I16, v4i16imm, v4i16>;
+}
+
+multiclass UnaryPatMCi32Scalar<ILOpCode opc, PatFrag opn>
+{
+ defm i32 : UnaryPatExpand<opc, opn, GPRI32, i32imm, i32>;
+}
+
+multiclass UnaryPatMCi32Vector<ILOpCode opc, PatFrag opn>
+{
+ defm v2i32 : UnaryPatExpand<opc, opn, GPRV2I32, v2i32imm, v2i32>;
+ defm v4i32 : UnaryPatExpand<opc, opn, GPRV4I32, v4i32imm, v4i32>;
+}
+
+multiclass UnaryPatMCi64Scalar<ILOpCode opc, PatFrag opn>
+{
+ defm i64 : UnaryPatExpand<opc, opn, GPRI64, i64imm, i64>;
+}
+
+multiclass UnaryPatMCi64Vector<ILOpCode opc, PatFrag opn>
+{
+ defm v2i64 : UnaryPatExpand<opc, opn, GPRV2I64, v2i64imm, v2i64>;
+}
+
+multiclass UnaryPatMCf32Scalar<ILOpCode opc, PatFrag opn>
+{
+ defm f32 : UnaryPatExpandFP<opc, opn, GPRF32, f32imm, f32>;
+}
+
+multiclass UnaryPatMCf32Vector<ILOpCode opc, PatFrag opn>
+{
+ defm v2f32 : UnaryPatExpandFP<opc, opn, GPRV2F32, v2f32imm, v2f32>;
+ defm v4f32 : UnaryPatExpandFP<opc, opn, GPRV4F32, v4f32imm, v4f32>;
+}
+
+
+multiclass UnaryPatMCf64Scalar<ILOpCode opc, PatFrag opn>
+{
+ defm f64 : UnaryPatExpandFP<opc, opn, GPRF64, f64imm, f64>;
+}
+
+multiclass UnaryPatMCf64Vector<ILOpCode opc, PatFrag opn>
+{
+ defm v2f64 : UnaryPatExpandFP<opc, opn, GPRV2F64, v2f64imm, v2f64>;
+}
+
+multiclass UnaryPatMCi32<ILOpCode opc, PatFrag opn>
+: UnaryPatMCi32Scalar<opc, opn>, UnaryPatMCi32Vector<opc, opn>,
+ UnaryPatMCi16Scalar<opc, opn>, UnaryPatMCi16Vector<opc, opn>,
+ UnaryPatMCi8Scalar< opc, opn>, UnaryPatMCi8Vector< opc, opn>;
+
+multiclass UnaryPatMCi64<ILOpCode opc, PatFrag opn>
+: UnaryPatMCi64Scalar<opc, opn>, UnaryPatMCi64Vector<opc, opn>;
+
+multiclass UnaryPatMCf32<ILOpCode opc, PatFrag opn>
+: UnaryPatMCf32Scalar<opc, opn>, UnaryPatMCf32Vector<opc, opn>;
+
+multiclass UnaryPatMCf64<ILOpCode opc, PatFrag opn>
+: UnaryPatMCf64Scalar<opc, opn>, UnaryPatMCf64Vector<opc, opn>;
+
+multiclass UnaryPatMCInt<ILOpCode opc, PatFrag opn>
+: UnaryPatMCi32<opc, opn> , UnaryPatMCi64<opc, opn>;
+
+multiclass UnaryPatMCFP<ILOpCode opc, PatFrag opn>
+: UnaryPatMCf32<opc, opn>, UnaryPatMCf64<opc, opn>;
+
+multiclass UnaryPatMC<ILOpCode opc, PatFrag opn>
+: UnaryPatMCInt<opc, opn>, UnaryPatMCFP<opc, opn>;
+
+multiclass UnpackPatFrag<ILOpCode opc, PatFrag node> {
+ def f32r : ILFormat<opc, (outs GPRF32:$dst),
(ins GPRI32:$src),
- !strconcat(opcode.Text, " $dst, $src"),
- [(set GPRF32:$dst, (intr GPRI32:$src))]>;
- def _v2f32 : OneInOneOut<opcode, (outs GPRV2F32:$dst),
- (ins GPRV2I32:$src),
- !strconcat(opcode.Text, " $dst, $src"),
- [(set GPRV2F32:$dst, (intr GPRV2I32:$src))]>;
- def _v4f32 : OneInOneOut<opcode, (outs GPRV4F32:$dst),
- (ins GPRV4I32:$src),
- !strconcat(opcode.Text, " $dst, $src"),
- [(set GPRV4F32:$dst, (intr GPRV4I32:$src))]>;
-}
-
-multiclass BinaryIntrinsicLong<ILOpCode opcode, Intrinsic intr>
-{
- def _i64 : TwoInOneOut<opcode, (outs GPRI64:$dst),
- (ins GPRI64:$src, GPRI64:$src2),
- !strconcat(opcode.Text, " $dst, $src, $src2"),
- [(set GPRI64:$dst,
- (intr GPRI64:$src, GPRI64:$src2))]>;
-}
-
-
-multiclass BinaryIntrinsicInt<ILOpCode opcode, Intrinsic intr>
-{
- def _i32 : TwoInOneOut<opcode, (outs GPRI32:$dst),
- (ins GPRI32:$src, GPRI32:$src2),
- !strconcat(opcode.Text, " $dst, $src, $src2"),
- [(set GPRI32:$dst,
- (intr GPRI32:$src, GPRI32:$src2))]>;
- def _v2i32 : TwoInOneOut<opcode, (outs GPRV2I32:$dst),
- (ins GPRV2I32:$src, GPRV2I32:$src2),
- !strconcat(opcode.Text, " $dst, $src, $src2"),
- [(set GPRV2I32:$dst,
- (intr GPRV2I32:$src, GPRV2I32:$src2))]>;
- def _v4i32 : TwoInOneOut<opcode, (outs GPRV4I32:$dst),
- (ins GPRV4I32:$src, GPRV4I32:$src2),
- !strconcat(opcode.Text, " $dst, $src, $src2"),
- [(set GPRV4I32:$dst,
- (intr GPRV4I32:$src, GPRV4I32:$src2))]>;
-}
-
-multiclass TernaryIntrinsicInt<ILOpCode opcode, Intrinsic intr>
-{
- def _i32 : ThreeInOneOut<opcode, (outs GPRI32:$dst),
- (ins GPRI32:$src, GPRI32:$src2, GPRI32:$src3),
- !strconcat(opcode.Text, " $dst, $src, $src2, $src3"),
- [(set GPRI32:$dst,
- (intr GPRI32:$src, GPRI32:$src2, GPRI32:$src3))]>;
- def _v2i32 : ThreeInOneOut<opcode, (outs GPRV2I32:$dst),
- (ins GPRV2I32:$src, GPRV2I32:$src2, GPRV2I32:$src3),
- !strconcat(opcode.Text, " $dst, $src, $src2, $src3"),
- [(set GPRV2I32:$dst,
- (intr GPRV2I32:$src, GPRV2I32:$src2, GPRV2I32:$src3))]>;
- def _v4i32 : ThreeInOneOut<opcode, (outs GPRV4I32:$dst),
- (ins GPRV4I32:$src, GPRV4I32:$src2, GPRV4I32:$src3),
- !strconcat(opcode.Text, " $dst, $src, $src2, $src3"),
- [(set GPRV4I32:$dst,
- (intr GPRV4I32:$src, GPRV4I32:$src2, GPRV4I32:$src3))]>;
-}
-
-multiclass TernaryIntrinsicFloat<ILOpCode opcode, Intrinsic intr>
-{
- def _f32 : ThreeInOneOut<opcode, (outs GPRF32:$dst),
- (ins GPRF32:$src, GPRF32:$src2, GPRF32:$src3),
- !strconcat(opcode.Text, " $dst, $src, $src2, $src3"),
- [(set GPRF32:$dst,
- (intr GPRF32:$src, GPRF32:$src2, GPRF32:$src3))]>;
- def _v2f32 : ThreeInOneOut<opcode, (outs GPRV2F32:$dst),
- (ins GPRV2F32:$src, GPRV2F32:$src2, GPRV2F32:$src3),
- !strconcat(opcode.Text, " $dst, $src, $src2, $src3"),
- [(set GPRV2F32:$dst,
- (intr GPRV2F32:$src, GPRV2F32:$src2, GPRV2F32:$src3))]>;
- def _v4f32 : ThreeInOneOut<opcode, (outs GPRV4F32:$dst),
- (ins GPRV4F32:$src, GPRV4F32:$src2, GPRV4F32:$src3),
- !strconcat(opcode.Text, " $dst, $src, $src2, $src3"),
- [(set GPRV4F32:$dst,
- (intr GPRV4F32:$src, GPRV4F32:$src2, GPRV4F32:$src3))]>;
-}
-
-multiclass BinaryIntrinsicDoubleScalar<ILOpCode opcode, Intrinsic intr>
-{
- def _f64 : ThreeInOneOut<opcode, (outs GPRF64:$dst),
- (ins GPRF64:$src, GPRF64:$src2),
- !strconcat(opcode.Text, " $dst, $src, $src2"),
- [(set GPRF64:$dst,
- (intr GPRF64:$src, GPRF64:$src2))]>;
-}
-
-multiclass TernaryIntrinsicDoubleScalar<ILOpCode opcode, Intrinsic intr>
-{
- def _f64 : ThreeInOneOut<opcode, (outs GPRF64:$dst),
- (ins GPRF64:$src, GPRF64:$src2, GPRF64:$src3),
- !strconcat(opcode.Text, " $dst, $src, $src2, $src3"),
- [(set GPRF64:$dst,
- (intr GPRF64:$src, GPRF64:$src2, GPRF64:$src3))]>;
-}
-
-
-multiclass TernaryIntrinsicLongScalar<ILOpCode opcode, Intrinsic intr>
-{
- def _i64 : ThreeInOneOut<opcode, (outs GPRI64:$dst),
- (ins GPRI64:$src, GPRI64:$src2, GPRI64:$src3),
- !strconcat(opcode.Text, " $dst, $src, $src2, $src3"),
- [(set GPRI64:$dst,
- (intr GPRI64:$src, GPRI64:$src2, GPRI64:$src3))]>;
-}
-
-multiclass QuaternaryIntrinsicInt<ILOpCode opcode, Intrinsic intr>
-{
- def _i32 : FourInOneOut<opcode, (outs GPRI32:$dst),
- (ins GPRI32:$src, GPRI32:$src2, GPRI32:$src3, GPRI32:$src4),
- !strconcat(opcode.Text, " $dst, $src, $src2, $src3, $src4"),
- [(set GPRI32:$dst,
- (intr GPRI32:$src, GPRI32:$src2, GPRI32:$src3, GPRI32:$src4))]>;
- def _v2i32 : FourInOneOut<opcode, (outs GPRV2I32:$dst),
- (ins GPRV2I32:$src, GPRV2I32:$src2, GPRV2I32:$src3, GPRV2I32:$src4),
- !strconcat(opcode.Text, " $dst, $src, $src2, $src3, $src4"),
- [(set GPRV2I32:$dst,
- (intr GPRV2I32:$src, GPRV2I32:$src2, GPRV2I32:$src3, GPRV2I32:$src4))]>;
- def _v4i32 : FourInOneOut<opcode, (outs GPRV4I32:$dst),
- (ins GPRV4I32:$src, GPRV4I32:$src2, GPRV4I32:$src3, GPRV4I32:$src4),
- !strconcat(opcode.Text, " $dst, $src, $src2, $src3, $src4"),
- [(set GPRV4I32:$dst,
- (intr GPRV4I32:$src, GPRV4I32:$src2, GPRV4I32:$src3, GPRV4I32:$src4))]>;
-}
-
-multiclass UnaryIntrinsicFloatScalar<ILOpCode opcode, Intrinsic intr>
-{
- def _f32 : OneInOneOut<opcode, (outs GPRF32:$dst),
- (ins GPRF32:$src),
- !strconcat(opcode.Text, " $dst, $src"),
- [(set GPRF32:$dst, (intr GPRF32:$src))]>;
-}
-
-multiclass UnaryIntrinsicFloat<ILOpCode opcode, Intrinsic intr>
-{
- def _f32 : OneInOneOut<opcode, (outs GPRF32:$dst),
- (ins GPRF32:$src),
- !strconcat(opcode.Text, " $dst, $src"),
- [(set GPRF32:$dst, (intr GPRF32:$src))]>;
- def _v2f32 : OneInOneOut<opcode, (outs GPRV2F32:$dst),
- (ins GPRV2F32:$src),
- !strconcat(opcode.Text, " $dst, $src"),
- [(set GPRV2F32:$dst, (intr GPRV2F32:$src))]>;
- def _v4f32 : OneInOneOut<opcode, (outs GPRV4F32:$dst),
- (ins GPRV4F32:$src),
- !strconcat(opcode.Text, " $dst, $src"),
- [(set GPRV4F32:$dst, (intr GPRV4F32:$src))]>;
-}
-
-multiclass BinaryIntrinsicFloatScalar<ILOpCode opcode, Intrinsic intr>
-{
- def _f32 : TwoInOneOut<opcode, (outs GPRF32:$dst),
- (ins GPRF32:$src, GPRF32:$src2),
- !strconcat(opcode.Text, " $dst, $src, $src2"),
- [(set GPRF32:$dst,
- (intr GPRF32:$src, GPRF32:$src2))]>;
-}
-multiclass BinaryIntrinsicFloat<ILOpCode opcode, Intrinsic intr>
-{
- def _f32 : TwoInOneOut<opcode, (outs GPRF32:$dst),
- (ins GPRF32:$src, GPRF32:$src2),
- !strconcat(opcode.Text, " $dst, $src, $src2"),
- [(set GPRF32:$dst,
- (intr GPRF32:$src, GPRF32:$src2))]>;
- def _v2f32 : TwoInOneOut<opcode, (outs GPRV2F32:$dst),
- (ins GPRV2F32:$src, GPRV2F32:$src2),
- !strconcat(opcode.Text, " $dst, $src, $src2"),
- [(set GPRV2F32:$dst,
- (intr GPRV2F32:$src, GPRV2F32:$src2))]>;
- def _v4f32 : TwoInOneOut<opcode, (outs GPRV4F32:$dst),
- (ins GPRV4F32:$src, GPRV4F32:$src2),
- !strconcat(opcode.Text, " $dst, $src, $src2"),
- [(set GPRV4F32:$dst,
- (intr GPRV4F32:$src, GPRV4F32:$src2))]>;
-}
-
-multiclass UnaryIntrinsicDoubleScalar<ILOpCode opcode, Intrinsic intr>
-{
- def _f64 : OneInOneOut<opcode, (outs GPRF64:$dst),
- (ins GPRF64:$src),
- !strconcat(opcode.Text, " $dst, $src"),
- [(set GPRF64:$dst, (intr GPRF64:$src))]>;
-}
-
-multiclass UnaryIntrinsicDouble<ILOpCode opcode, Intrinsic intr>
-{
- def _f64 : OneInOneOut<opcode, (outs GPRF64:$dst),
- (ins GPRF64:$src),
- !strconcat(opcode.Text, " $dst, $src"),
- [(set GPRF64:$dst, (intr GPRF64:$src))]>;
- def _v2f64 : OneInOneOut<opcode, (outs GPRV2F64:$dst),
- (ins GPRV2F64:$src),
- !strconcat(opcode.Text, " $dst, $src"),
- [(set GPRV2F64:$dst, (intr GPRV2F64:$src))]>;
-}
-
-multiclass BinaryIntrinsicDouble<ILOpCode opcode, Intrinsic intr>
-{
- def _f64 : TwoInOneOut<opcode, (outs GPRF64:$dst),
- (ins GPRF64:$src, GPRF64:$src2),
- !strconcat(opcode.Text, " $dst, $src, $src2"),
- [(set GPRF64:$dst,
- (intr GPRF64:$src, GPRF64:$src2))]>;
- def _v2f64 : TwoInOneOut<opcode, (outs GPRV2F64:$dst),
- (ins GPRV2F64:$src, GPRV2F64:$src2),
- !strconcat(opcode.Text, " $dst, $src, $src2"),
- [(set GPRV2F64:$dst,
- (intr GPRV2F64:$src, GPRV2F64:$src2))]>;
-}
-
-multiclass TernaryIntrinsicDouble<ILOpCode opcode, Intrinsic intr>
-{
- def _f64 : TwoInOneOut<opcode, (outs GPRF64:$dst),
- (ins GPRF64:$src, GPRF64:$src2, GPRF64:$src3),
- !strconcat(opcode.Text, " $dst, $src, $src2, $src3"),
- [(set GPRF64:$dst,
- (intr GPRF64:$src, GPRF64:$src2, GPRF64:$src3))]>;
- def _v2f64 : TwoInOneOut<opcode, (outs GPRV2F64:$dst),
- (ins GPRV2F64:$src, GPRV2F64:$src2, GPRV2F64:$src3),
- !strconcat(opcode.Text, " $dst, $src, $src2, $src3"),
- [(set GPRV2F64:$dst,
- (intr GPRV2F64:$src, GPRV2F64:$src2, GPRV2F64:$src3))]>;
-}
-/// Binary pattern instructions multiclass
-multiclass BinaryPatFragI32<ILOpCode opcode, PatFrag node> {
- def _i32 : TwoInOneOut<opcode, (outs GPRI32:$dst),
- (ins GPRI32:$lhs, GPRI32:$rhs),
- !strconcat(opcode.Text, " $dst, $lhs, $rhs"),
- [(set GPRI32:$dst, (node GPRI32:$lhs, GPRI32:$rhs))]>;
-/*
- // FIXME: Need to rewrite the patterns to get the vector versions t work.
- def _v2i32 : TwoInOneOut<opcode, (outs GPRV2I32:$dst),
- (ins GPRV2I32:$lhs, GPRV2I32:$rhs),
- !strconcat(opcode.Text, " $dst, $lhs, $rhs"),
- [(set GPRV2I32:$dst, (node GPRV2I32:$lhs, GPRV2I32:$rhs))]>;
-
- def _v4i32 : TwoInOneOut<opcode, (outs GPRV4I32:$dst),
- (ins GPRV4I32:$lhs, GPRV4I32:$rhs),
- !strconcat(opcode.Text, " $dst, $lhs, $rhs"),
- [(set GPRV4I32:$dst, (node GPRV4I32:$lhs, GPRV4I32:$rhs))]>;
- */
-}
-
-/// Ternary pattern instructions multiclass
-multiclass TernaryPatFragI32<ILOpCode opcode, PatFrag node> {
- def _i32 : ThreeInOneOut<opcode, (outs GPRI32:$dst),
- (ins GPRI32:$lhs, GPRI32:$rhs, GPRI32:$bitpat),
- !strconcat(opcode.Text, " $dst, $bitpat, $lhs, $rhs"),
- [(set GPRI32:$dst, (node GPRI32:$lhs, GPRI32:$rhs, GPRI32:$bitpat))]>;
-
- def _v2i32 : ThreeInOneOut<opcode, (outs GPRV2I32:$dst),
- (ins GPRV2I32:$lhs, GPRV2I32:$rhs, GPRV2I32:$bitpat),
- !strconcat(opcode.Text, " $dst, $bitpat, $lhs, $rhs"),
- [(set GPRV2I32:$dst,
- (node GPRV2I32:$lhs, GPRV2I32:$rhs, GPRV2I32:$bitpat))]>;
-
- def _v4i32 : ThreeInOneOut<opcode, (outs GPRV4I32:$dst),
- (ins GPRV4I32:$lhs, GPRV4I32:$rhs, GPRV4I32:$bitpat),
- !strconcat(opcode.Text, " $dst, $bitpat, $lhs, $rhs"),
- [(set GPRV4I32:$dst,
- (node GPRV4I32:$lhs, GPRV4I32:$rhs, GPRV4I32:$bitpat))]>;
+ !strconcat(opc.Text, " $dst, $src"),
+ [(set GPRF32:$dst, (node GPRI32:$src))]>;
+ def f32i : ILFormat<opc, (outs GPRF32:$dst),
+ (ins i32imm:$src),
+ !strconcat(opc.Text, " $dst, $src"),
+ [(set GPRF32:$dst, (node (i32 imm:$src)))]>;
+}
+
+
+//----------------------------------------------------------------------------//
+// Multiclasses that deal with two operand instructions that are commutable.
+//----------------------------------------------------------------------------//
+multiclass BinaryNegReg<ILOpCode opc, SDNode opn,
+ RegisterClass reg, Operand oper, ValueType type, SDNode imm0,
+ string str>
+{
+ def rr : ILFormat<opc,
+ (outs reg:$dst),
+ (ins reg:$src0, reg:$src1),
+ !strconcat(!strconcat(opc.Text, " $dst, $src0, "), str),
+ [(set (type reg:$dst),
+ (opn (type reg:$src0), (type reg:$src1)))]>;
+ def ir : ILFormat<opc,
+ (outs reg:$dst),
+ (ins oper:$src0, reg:$src1),
+ !strconcat(!strconcat(opc.Text, " $dst, $src0, "), str),
+ [(set (type reg:$dst),
+ (opn (type imm0:$src0), (type reg:$src1)))]>;
+ def ri : ILFormat<opc,
+ (outs reg:$dst),
+ (ins reg:$src0, oper:$src1),
+ !strconcat(!strconcat(opc.Text, " $dst, $src0, "), str),
+ [(set (type reg:$dst),
+ (opn (type reg:$src0), (type imm0:$src1)))]>;
+ def ii : ILFormat<opc,
+ (outs reg:$dst),
+ (ins oper:$src0, oper:$src1),
+ !strconcat(!strconcat(opc.Text, " $dst, $src0, "), str),
+ [(set (type reg:$dst),
+ (opn (type imm0:$src0), (type imm0:$src1)))]>;
+}
+
+multiclass BinaryNegExpand<ILOpCode opc, SDNode opn,
+ RegisterClass reg, Operand oper, ValueType type,
+ string str>
+ : BinaryNegReg<opc, opn, reg, oper, type, imm, str>;
+
+ multiclass BinaryNegExpandFP<ILOpCode opc, SDNode opn,
+ RegisterClass reg, Operand oper, ValueType type,
+ string str>
+ : BinaryNegReg<opc, opn, reg, oper, type, fpimm, str>;
+
+ multiclass BinaryNegMCf32<ILOpCode opc, SDNode opn>
+{
+ defm f32 : BinaryNegExpandFP<opc, opn, GPRF32, f32imm,
+ f32, "${src1}_neg(xyzw)">;
+ defm v2f32 : BinaryNegExpandFP<opc, opn, GPRV2F32, v2f32imm,
+ v2f32, "${src1}_neg(xyzw)">;
+ defm v4f32 : BinaryNegExpandFP<opc, opn, GPRV4F32, v4f32imm,
+ v4f32, "${src1}_neg(xyzw)">;
+}
+multiclass BinaryNegMCf64<ILOpCode opc, SDNode opn>
+{
+ defm f64 : BinaryNegExpandFP<opc, opn, GPRF64, f64imm,
+ f64, "${src1}_neg(yw)">;
+ defm v2f64 : BinaryNegExpandFP<opc, opn, GPRV2F64, v2f64imm,
+ v2f64, "${src1}_neg(yw)">;
+}
+
+multiclass BinaryOpMCFull<ILOpCode opc, SDNode opn,
+ ValueType dtype, RegisterClass dreg,
+ ValueType stype0, RegisterClass sreg0, Operand oper0, SDNode imm0,
+ ValueType stype1, RegisterClass sreg1, Operand oper1, SDNode imm1>
+{
+ def rr : ILFormat<opc, (outs dreg:$dst), (ins sreg0:$src0, sreg1:$src1),
+ !strconcat(opc.Text, " $dst, $src0, $src1"),
+ [(set (dtype dreg:$dst),
+ (opn (stype0 sreg0:$src0), (stype1 sreg1:$src1)))]>;
+ def ri : ILFormat<opc, (outs dreg:$dst), (ins sreg0:$src0, oper1:$src1),
+ !strconcat(opc.Text, " $dst, $src0, $src1"),
+ [(set (dtype dreg:$dst),
+ (opn (stype0 sreg0:$src0), (stype1 imm1:$src1)))]>;
+ def ii : ILFormat<opc, (outs dreg:$dst), (ins oper0:$src0, oper1:$src1),
+ !strconcat(opc.Text, " $dst, $src0, $src1"),
+ [(set (dtype dreg:$dst),
+ (opn (stype0 imm0:$src0), (stype1 imm1:$src1)))]>;
+}
+
+multiclass BinaryOpReg<ILOpCode opc, SDNode opn,
+ RegisterClass reg, Operand oper, ValueType type, SDNode imm0>
+ : BinaryOpMCFull<opc, opn, type, reg,
+ type, reg, oper, imm0, type, reg, oper, imm0>;
+
+multiclass BinaryOpExpand<ILOpCode opc, SDNode opn,
+ RegisterClass reg, Operand oper, ValueType type, SDNode imm0>
+ : BinaryOpReg<opc, opn, reg, oper, type, imm0>;
+
+ multiclass BinaryOpMCi32Scalar<ILOpCode opc, SDNode opn>
+{
+ defm i8 : BinaryOpExpand<opc, opn, GPRI8, i8imm, i8, imm>;
+ defm i16 : BinaryOpExpand<opc, opn, GPRI16, i16imm, i16, imm>;
+ defm i32 : BinaryOpExpand<opc, opn, GPRI32, i32imm, i32, imm>;
+}
+
+multiclass BinaryOpMCi32Vector<ILOpCode opc, SDNode opn>
+{
+ defm v2i8 : BinaryOpExpand<opc, opn, GPRV2I8, v2i8imm, v2i8, imm>;
+ defm v2i16 : BinaryOpExpand<opc, opn, GPRV2I16, v2i16imm, v2i16, imm>;
+ defm v2i32 : BinaryOpExpand<opc, opn, GPRV2I32, v2i32imm, v2i32, imm>;
+ defm v4i8 : BinaryOpExpand<opc, opn, GPRV4I8, v4i8imm, v4i8, imm>;
+ defm v4i16 : BinaryOpExpand<opc, opn, GPRV4I16, v4i16imm, v4i16, imm>;
+ defm v4i32 : BinaryOpExpand<opc, opn, GPRV4I32, v4i32imm, v4i32, imm>;
+}
+
+multiclass BinaryOpMCi64Scalar<ILOpCode opc, SDNode opn>
+{
+ defm i64 : BinaryOpExpand<opc, opn, GPRI64, i64imm, i64, imm>;
+}
+
+multiclass BinaryOpMCi64Vector<ILOpCode opc, SDNode opn>
+{
+ defm v2i64 : BinaryOpExpand<opc, opn, GPRV2I64, v2i64imm, v2i64, imm>;
+}
+
+multiclass BinaryOpMCf32Scalar<ILOpCode opc, SDNode opn>
+{
+ defm f32 : BinaryOpExpand<opc, opn, GPRF32, f32imm, f32, fpimm>;
+}
+
+multiclass BinaryOpMCf32Vector<ILOpCode opc, SDNode opn>
+{
+ defm v2f32 : BinaryOpExpand<opc, opn, GPRV2F32, v2f32imm, v2f32, fpimm>;
+ defm v4f32 : BinaryOpExpand<opc, opn, GPRV4F32, v4f32imm, v4f32, fpimm>;
+}
+
+
+multiclass BinaryOpMCf64Scalar<ILOpCode opc, SDNode opn>
+{
+ defm f64 : BinaryOpExpand<opc, opn, GPRF64, f64imm, f64, fpimm>;
+}
+
+multiclass BinaryOpMCf64Vector<ILOpCode opc, SDNode opn>
+{
+ defm v2f64 : BinaryOpExpand<opc, opn, GPRV2F64, v2f64imm, v2f64, fpimm>;
}
+
+multiclass BinaryOpMCi32<ILOpCode opc, SDNode opn>
+: BinaryOpMCi32Scalar<opc, opn>, BinaryOpMCi32Vector<opc, opn>;
+
+multiclass BinaryOpMCi64<ILOpCode opc, SDNode opn>
+: BinaryOpMCi64Scalar<opc, opn>, BinaryOpMCi64Vector<opc, opn>;
+
+multiclass BinaryOpMCf32<ILOpCode opc, SDNode opn>
+: BinaryOpMCf32Scalar<opc, opn>, BinaryOpMCf32Vector<opc, opn>;
+
+multiclass BinaryOpMCf64<ILOpCode opc, SDNode opn>
+: BinaryOpMCf64Scalar<opc, opn>, BinaryOpMCf64Vector<opc, opn>;
+
+multiclass BinaryOpMCInt<ILOpCode opc, SDNode opn>
+: BinaryOpMCi32<opc, opn> , BinaryOpMCi64<opc, opn>;
+
+multiclass BinaryOpMCFP<ILOpCode opc, SDNode opn>
+: BinaryOpMCf32<opc, opn>, BinaryOpMCf64<opc, opn>;
+
+multiclass BinaryOpMC<ILOpCode opc, SDNode opn>
+: BinaryOpMCInt<opc, opn>, BinaryOpMCFP<opc, opn>;
+
+//----------------------------------------------------------------------------//
+// Multiclasses that deal with two operand instructions that are not commutable.
+//----------------------------------------------------------------------------//
+multiclass BinaryNCOpExpand<ILOpCode opc, SDNode opn,
+ RegisterClass reg, Operand oper, ValueType type, SDNode imm0>
+ : BinaryOpExpand<opc, opn, reg, oper, type, imm0>
+ {
+ def ir : ILFormat<opc, (outs reg:$dst), (ins oper:$src0, reg:$src1),
+ !strconcat(opc.Text, " $dst, $src0, $src1"),
+ [(set (type reg:$dst),
+ (opn (type imm0:$src0), (type reg:$src1)))]>;
+ }
+
+
+ multiclass BinaryNCOpMCi32Scalar<ILOpCode opc, SDNode opn>
+{
+ defm i8 : BinaryNCOpExpand<opc, opn, GPRI8, i8imm, i8, imm>;
+ defm i16 : BinaryNCOpExpand<opc, opn, GPRI16, i16imm, i16, imm>;
+ defm i32 : BinaryNCOpExpand<opc, opn, GPRI32, i32imm, i32, imm>;
+}
+
+multiclass BinaryNCOpMCi32Vector<ILOpCode opc, SDNode opn>
+{
+ defm v2i8 : BinaryNCOpExpand<opc, opn, GPRV2I8, v2i8imm, v2i8, imm>;
+ defm v2i16 : BinaryNCOpExpand<opc, opn, GPRV2I16, v2i16imm, v2i16, imm>;
+ defm v2i32 : BinaryNCOpExpand<opc, opn, GPRV2I32, v2i32imm, v2i32, imm>;
+ defm v4i8 : BinaryNCOpExpand<opc, opn, GPRV4I8, v4i8imm, v4i8, imm>;
+ defm v4i16 : BinaryNCOpExpand<opc, opn, GPRV4I16, v4i16imm, v4i16, imm>;
+ defm v4i32 : BinaryNCOpExpand<opc, opn, GPRV4I32, v4i32imm, v4i32, imm>;
+}
+
+multiclass BinaryNCOpMCi64Scalar<ILOpCode opc, SDNode opn>
+{
+ defm i64 : BinaryNCOpExpand<opc, opn, GPRI64, i64imm, i64, imm>;
+}
+
+multiclass BinaryNCOpMCi64Vector<ILOpCode opc, SDNode opn>
+{
+ defm v2i64 : BinaryNCOpExpand<opc, opn, GPRV2I64, v2i64imm, v2i64, imm>;
+}
+
+multiclass BinaryNCOpMCf32Scalar<ILOpCode opc, SDNode opn>
+{
+ defm f32 : BinaryNCOpExpand<opc, opn, GPRF32, f32imm, f32, fpimm>;
+}
+
+multiclass BinaryNCOpMCf32Vector<ILOpCode opc, SDNode opn>
+{
+ defm v2f32 : BinaryNCOpExpand<opc, opn, GPRV2F32, v2f32imm, v2f32, fpimm>;
+ defm v4f32 : BinaryNCOpExpand<opc, opn, GPRV4F32, v4f32imm, v4f32, fpimm>;
+}
+
+
+multiclass BinaryNCOpMCf64Scalar<ILOpCode opc, SDNode opn>
+{
+ defm f64 : BinaryNCOpExpand<opc, opn, GPRF64, f64imm, f64, fpimm>;
+}
+
+multiclass BinaryNCOpMCf64Vector<ILOpCode opc, SDNode opn>
+{
+ defm v2f64 : BinaryNCOpExpand<opc, opn, GPRV2F64, v2f64imm, v2f64, fpimm>;
+}
+
+
+
+multiclass BinaryNCOpMCi32<ILOpCode opc, SDNode opn>
+: BinaryNCOpMCi32Scalar<opc, opn>, BinaryNCOpMCi32Vector<opc, opn>;
+
+multiclass BinaryNCOpMCi64<ILOpCode opc, SDNode opn>
+: BinaryNCOpMCi64Scalar<opc, opn>, BinaryNCOpMCi64Vector<opc, opn>;
+
+multiclass BinaryNCOpShift<ILOpCode opc, SDNode opn,
+ RegisterClass dreg, RegisterClass sreg,
+ Operand oper, ValueType type, ValueType stype>
+{
+ def rr : ILFormat<opc,
+ (outs dreg:$dst),
+ (ins dreg:$src0, sreg:$src1),
+ !strconcat(opc.Text, " $dst, $src0, $src1"),
+ [(set (type dreg:$dst),
+ (opn (type dreg:$src0), (stype sreg:$src1)))]>;
+ def ri : ILFormat<opc,
+ (outs dreg:$dst),
+ (ins dreg:$src0, oper:$src1),
+ !strconcat(opc.Text, " $dst, $src0, $src1"),
+ [(set (type dreg:$dst),
+ (opn (type dreg:$src0), (stype imm:$src1)))]>;
+}
+
+
+
+multiclass BinaryNCOpMCi32Shift<ILOpCode opc, SDNode opn>
+{
+ defm i8i8 : BinaryNCOpShift<opc, opn, GPRI8, GPRI8, i8imm, i8, i8>;
+ defm v2i8i8 : BinaryNCOpShift<opc, opn, GPRV2I8, GPRV2I8, v2i8imm, v2i8, v2i8>;
+ defm v4i8i8 : BinaryNCOpShift<opc, opn, GPRV4I8, GPRV4I8, v4i8imm, v4i8, v4i8>;
+ defm i16i16 : BinaryNCOpShift<opc, opn, GPRI16, GPRI16, i16imm, i16, i16>;
+ defm v2i16i16 : BinaryNCOpShift<opc, opn, GPRV2I16, GPRV2I16, v2i16imm, v2i16, v2i16>;
+ defm v4i16i16 : BinaryNCOpShift<opc, opn, GPRV4I16, GPRV4I16, v4i16imm, v4i16, v4i16>;
+ defm i8i32 : BinaryNCOpShift<opc, opn, GPRI8, GPRI32, i32imm, i8, i32>;
+ defm v2i8i32 : BinaryNCOpShift<opc, opn, GPRV2I8, GPRV2I32, v2i32imm, v2i8, v2i32>;
+ defm v4i8i32 : BinaryNCOpShift<opc, opn, GPRV4I8, GPRV4I32, v4i32imm, v4i8, v4i32>;
+ defm i16i32 : BinaryNCOpShift<opc, opn, GPRI16, GPRI32, i32imm, i16, i32>;
+ defm v2i16i32 : BinaryNCOpShift<opc, opn, GPRV2I16, GPRV2I32, v2i32imm, v2i16, v2i32>;
+ defm v4i16i32 : BinaryNCOpShift<opc, opn, GPRV4I16, GPRV4I32, v4i32imm, v4i16, v4i32>;
+ defm i32i32 : BinaryNCOpShift<opc, opn, GPRI32, GPRI32, i32imm, i32, i32>;
+ defm v2i32i32 : BinaryNCOpShift<opc, opn, GPRV2I32, GPRV2I32, v2i32imm, v2i32, v2i32>;
+ defm v4i32i32 : BinaryNCOpShift<opc, opn, GPRV4I32, GPRV4I32, v4i32imm, v4i32, v4i32>;
+ defm i8i64 : BinaryNCOpShift<opc, opn, GPRI8, GPRI64, i64imm, i8, i64>;
+ defm v2i8i64 : BinaryNCOpShift<opc, opn, GPRV2I8, GPRV2I64, v2i64imm, v2i8, v2i64>;
+ defm i16i64 : BinaryNCOpShift<opc, opn, GPRI16, GPRI64, i64imm, i16, i64>;
+ defm v2i16i64 : BinaryNCOpShift<opc, opn, GPRV2I16, GPRV2I64, v2i64imm, v2i16, v2i64>;
+ defm i32i64 : BinaryNCOpShift<opc, opn, GPRI32, GPRI64, i64imm, i32, i64>;
+ defm v2i32i64 : BinaryNCOpShift<opc, opn, GPRV2I32, GPRV2I64, v2i64imm, v2i32, v2i64>;
+}
+
+multiclass BinaryNCOpMCi64Shift<ILOpCode opc, SDNode opn>
+{
+ defm i64i64 : BinaryNCOpShift<opc, opn, GPRI64, GPRI64, i64imm, i64, i64>;
+ defm v2i64i64 : BinaryNCOpShift<opc, opn, GPRV2I64, GPRV2I64, v2i64imm, v2i64, v2i64>;
+ defm i64i32 : BinaryNCOpShift<opc, opn, GPRI64, GPRI32, i32imm, i64, i32>;
+ defm v2i64i32 : BinaryNCOpShift<opc, opn, GPRV2I64, GPRV2I32, v2i32imm, v2i64, v2i32>;
+}
+
+multiclass BinaryNCOpMCf32<ILOpCode opc, SDNode opn>
+: BinaryNCOpMCf32Scalar<opc, opn>, BinaryNCOpMCf32Vector<opc, opn>;
+
+multiclass BinaryNCOpMCf64<ILOpCode opc, SDNode opn>
+: BinaryNCOpMCf64Scalar<opc, opn>, BinaryNCOpMCf64Vector<opc, opn>;
+
+multiclass BinaryNCOpMCInt<ILOpCode opc, SDNode opn>
+: BinaryNCOpMCi32<opc, opn> , BinaryNCOpMCi64<opc, opn>;
+
+multiclass BinaryNCOpMCFP<ILOpCode opc, SDNode opn>
+: BinaryNCOpMCf32<opc, opn>, BinaryNCOpMCf64<opc, opn>;
+
+multiclass BinaryNCOpMC<ILOpCode opc, SDNode opn>
+: BinaryNCOpMCInt<opc, opn>, BinaryNCOpMCFP<opc, opn>;
+
+//----------------------------------------------------------------------------//
+// Multiclasses that deal with two operand intrinsics.
+//----------------------------------------------------------------------------//
+
+multiclass BinaryIntMCFull<ILOpCode opc, Intrinsic opn,
+ ValueType dtype, RegisterClass dreg,
+ ValueType stype0, RegisterClass sreg0, Operand oper0, SDNode imm0,
+ ValueType stype1, RegisterClass sreg1, Operand oper1, SDNode imm1>
+{
+ def rr : ILFormat<opc, (outs dreg:$dst),
+ (ins sreg0:$src0, sreg1:$src1),
+ !strconcat(opc.Text, " $dst, $src0, $src1"),
+ [(set (dtype dreg:$dst),
+ (opn (stype0 sreg0:$src0), (stype1 sreg1:$src1)))]>;
+ def ri : ILFormat<opc, (outs dreg:$dst),
+ (ins sreg0:$src0, oper1:$src1),
+ !strconcat(opc.Text, " $dst, $src0, $src1"),
+ [(set (dtype dreg:$dst),
+ (opn (stype0 sreg0:$src0), (stype1 imm1:$src1)))]>;
+ def ir : ILFormat<opc, (outs dreg:$dst),
+ (ins oper0:$src0, sreg1:$src1),
+ !strconcat(opc.Text, " $dst, $src0, $src1"),
+ [(set (dtype dreg:$dst),
+ (opn (stype0 imm0:$src0), (stype1 sreg1:$src1)))]>;
+ def ii : ILFormat<opc, (outs dreg:$dst),
+ (ins oper0:$src0, oper1:$src1),
+ !strconcat(opc.Text, " $dst, $src0, $src1"),
+ [(set (dtype dreg:$dst),
+ (opn (stype0 imm0:$src0), (stype1 imm1:$src1)))]>;
+}
+
+multiclass BinaryIntMCFFI<ILOpCode opc, Intrinsic opn>
+{
+ defm f32 : BinaryIntMCFull<opc, opn, f32, GPRF32,
+ f32, GPRF32, f32imm, fpimm, i32, GPRI32, i32imm, imm>;
+ defm v2f32 : BinaryIntMCFull<opc, opn, v2f32, GPRV2F32,
+ v2f32, GPRV2F32, v2f32imm, fpimm, v2i32, GPRV2I32, v2i32imm, imm>;
+ defm v4f32 : BinaryIntMCFull<opc, opn, v4f32, GPRV4F32,
+ v4f32, GPRV4F32, v4f32imm, fpimm, v4i32, GPRV4I32, v4i32imm, imm>;
+}
+
+
+multiclass BinaryIntMCDDI<ILOpCode opc, Intrinsic opn>
+{
+ defm f64 : BinaryIntMCFull<opc, opn, f64, GPRF64,
+ f64, GPRF64, f64imm, fpimm, i32, GPRI32, i32imm, imm>;
+ defm v2f64 : BinaryIntMCFull<opc, opn, v2f64, GPRV2F64,
+ v2f64, GPRV2F64, v2f64imm, fpimm, v2i32, GPRV2I32, v2i32imm, imm>;
+}
+
+
+multiclass BinaryIntReg<ILOpCode opc, Intrinsic opn,
+ RegisterClass reg, Operand oper, ValueType type,
+ SDNode imm0>
+{
+ def rr : ILFormat<opc, (outs reg:$dst), (ins reg:$src0, reg:$src1),
+ !strconcat(opc.Text, " $dst, $src0, $src1"),
+ [(set (type reg:$dst),
+ (opn (type reg:$src0), (type reg:$src1)))]>;
+ def ri : ILFormat<opc, (outs reg:$dst), (ins reg:$src0, oper:$src1),
+ !strconcat(opc.Text, " $dst, $src0, $src1"),
+ [(set (type reg:$dst),
+ (opn (type reg:$src0), (type imm0:$src1)))]>;
+ def ii : ILFormat<opc, (outs reg:$dst), (ins oper:$src0, oper:$src1),
+ !strconcat(opc.Text, " $dst, $src0, $src1"),
+ [(set (type reg:$dst),
+ (opn (type imm0:$src0), (type imm0:$src1)))]>;
+ }
+multiclass BinaryIntExpand<ILOpCode opc, Intrinsic opn,
+ RegisterClass reg, Operand oper, ValueType type>
+ : BinaryIntReg<opc, opn, reg, oper, type, imm>;
+
+ multiclass BinaryIntExpandFP<ILOpCode opc, Intrinsic opn,
+ RegisterClass reg, Operand oper, ValueType type>
+ : BinaryIntReg<opc, opn, reg, oper, type, fpimm>;
+
+ multiclass BinaryIntMCi8Scalar<ILOpCode opc, Intrinsic opn>
+{
+ defm i8 : BinaryIntExpand<opc, opn, GPRI8, i8imm, i8>;
+}
+
+multiclass BinaryIntMCi8Vector<ILOpCode opc, Intrinsic opn>
+{
+ defm v2i8 : BinaryIntExpand<opc, opn, GPRV2I8, v2i8imm, v2i8>;
+ defm v4i8 : BinaryIntExpand<opc, opn, GPRV4I8, v4i8imm, v4i8>;
+}
+
+multiclass BinaryIntMCi16Scalar<ILOpCode opc, Intrinsic opn>
+{
+ defm i16 : BinaryIntExpand<opc, opn, GPRI16, i16imm, i16>;
+}
+
+multiclass BinaryIntMCi16Vector<ILOpCode opc, Intrinsic opn>
+{
+ defm v2i16 : BinaryIntExpand<opc, opn, GPRV2I16, v2i16imm, v2i16>;
+ defm v4i16 : BinaryIntExpand<opc, opn, GPRV4I16, v4i16imm, v4i16>;
+}
+
+multiclass BinaryIntMCi32Scalar<ILOpCode opc, Intrinsic opn>
+{
+ defm i32 : BinaryIntExpand<opc, opn, GPRI32, i32imm, i32>;
+}
+
+multiclass BinaryIntMCi32Vector<ILOpCode opc, Intrinsic opn>
+{
+ defm v2i32 : BinaryIntExpand<opc, opn, GPRV2I32, v2i32imm, v2i32>;
+ defm v4i32 : BinaryIntExpand<opc, opn, GPRV4I32, v4i32imm, v4i32>;
+}
+
+multiclass BinaryIntMCi64Scalar<ILOpCode opc, Intrinsic opn>
+{
+ defm i64 : BinaryIntExpand<opc, opn, GPRI64, i64imm, i64>;
+}
+
+multiclass BinaryIntMCi64Vector<ILOpCode opc, Intrinsic opn>
+{
+ defm v2i64 : BinaryIntExpand<opc, opn, GPRV2I64, v2i64imm, v2i64>;
+}
+
+multiclass BinaryIntMCf32Scalar<ILOpCode opc, Intrinsic opn>
+{
+ defm f32 : BinaryIntExpandFP<opc, opn, GPRF32, f32imm, f32>;
+}
+
+multiclass BinaryIntMCf32Vector<ILOpCode opc, Intrinsic opn>
+{
+ defm v2f32 : BinaryIntExpandFP<opc, opn, GPRV2F32, v2f32imm, v2f32>;
+ defm v4f32 : BinaryIntExpandFP<opc, opn, GPRV4F32, v4f32imm, v4f32>;
+}
+
+
+multiclass BinaryIntMCf64Scalar<ILOpCode opc, Intrinsic opn>
+{
+ defm f64 : BinaryIntExpandFP<opc, opn, GPRF64, f64imm, f64>;
+}
+
+multiclass BinaryIntMCf64Vector<ILOpCode opc, Intrinsic opn>
+{
+ defm v2f64 : BinaryIntExpandFP<opc, opn, GPRV2F64, v2f64imm, v2f64>;
+}
+
+
+multiclass BinaryIntMCi32Only<ILOpCode opc, Intrinsic opn>
+: BinaryIntMCi32Scalar<opc, opn>, BinaryIntMCi32Vector<opc, opn>;
+
+multiclass BinaryIntMCi32<ILOpCode opc, Intrinsic opn>
+: BinaryIntMCi32Scalar<opc, opn>, BinaryIntMCi32Vector<opc, opn>,
+ BinaryIntMCi16Scalar<opc, opn>, BinaryIntMCi16Vector<opc, opn>,
+ BinaryIntMCi8Scalar< opc, opn>, BinaryIntMCi8Vector< opc, opn>;
+
+multiclass BinaryIntMCi64<ILOpCode opc, Intrinsic opn>
+: BinaryIntMCi64Scalar<opc, opn>, BinaryIntMCi64Vector<opc, opn>;
+
+multiclass BinaryIntMCf32<ILOpCode opc, Intrinsic opn>
+: BinaryIntMCf32Scalar<opc, opn>, BinaryIntMCf32Vector<opc, opn>;
+
+multiclass BinaryIntMCf64<ILOpCode opc, Intrinsic opn>
+: BinaryIntMCf64Scalar<opc, opn>, BinaryIntMCf64Vector<opc, opn>;
+
+multiclass BinaryIntMCInt<ILOpCode opc, Intrinsic opn>
+: BinaryIntMCi32<opc, opn> , BinaryIntMCi64<opc, opn>;
+
+multiclass BinaryIntMCFP<ILOpCode opc, Intrinsic opn>
+: BinaryIntMCf32<opc, opn>, BinaryIntMCf64<opc, opn>;
+
+multiclass BinaryIntMC<ILOpCode opc, Intrinsic opn>
+: BinaryIntMCInt<opc, opn>, BinaryIntMCFP<opc, opn>;
+
+//----------------------------------------------------------------------------//
+// Multiclasses that deal with two operand Pattern Fragments.
+//----------------------------------------------------------------------------//
+multiclass BinaryPatReg<ILOpCode opc, PatFrag opn,
+ RegisterClass reg, Operand oper, ValueType type,
+ SDNode imm0>
+{
+ def rr : ILFormat<opc,
+ (outs reg:$dst),
+ (ins reg:$src0, reg:$src1),
+ !strconcat(opc.Text, " $dst, $src0, $src1"),
+ [(set (type reg:$dst),
+ (opn (type reg:$src0), (type reg:$src1)))]>;
+ def ri : ILFormat<opc,
+ (outs reg:$dst),
+ (ins reg:$src0, oper:$src1),
+ !strconcat(opc.Text, " $dst, $src0, $src1"),
+ [(set (type reg:$dst),
+ (opn (type reg:$src0), (type imm0:$src1)))]>;
+ def ii : ILFormat<opc,
+ (outs reg:$dst),
+ (ins oper:$src0, oper:$src1),
+ !strconcat(opc.Text, " $dst, $src0, $src1"),
+ [(set (type reg:$dst),
+ (opn (type imm0:$src0), (type imm0:$src1)))]>;
+ }
+multiclass BinaryPatExpand<ILOpCode opc, PatFrag opn,
+ RegisterClass reg, Operand oper, ValueType type>
+ : BinaryPatReg<opc, opn, reg, oper, type, imm>;
+
+ multiclass BinaryPatExpandFP<ILOpCode opc, PatFrag opn,
+ RegisterClass reg, Operand oper, ValueType type>
+ : BinaryPatReg<opc, opn, reg, oper, type, fpimm>;
+
+ multiclass BinaryPatMCi8Scalar<ILOpCode opc, PatFrag opn>
+{
+ defm i8 : BinaryPatExpand<opc, opn, GPRI8, i8imm, i8>;
+}
+
+multiclass BinaryPatMCi8Vector<ILOpCode opc, PatFrag opn>
+{
+ defm v2i8 : BinaryPatExpand<opc, opn, GPRV2I8, v2i8imm, v2i8>;
+ defm v4i8 : BinaryPatExpand<opc, opn, GPRV4I8, v4i8imm, v4i8>;
+}
+
+multiclass BinaryPatMCi16Scalar<ILOpCode opc, PatFrag opn>
+{
+ defm i16 : BinaryPatExpand<opc, opn, GPRI16, i16imm, i16>;
+}
+
+multiclass BinaryPatMCi16Vector<ILOpCode opc, PatFrag opn>
+{
+ defm v2i16 : BinaryPatExpand<opc, opn, GPRV2I16, v2i16imm, v2i16>;
+ defm v4i16 : BinaryPatExpand<opc, opn, GPRV4I16, v4i16imm, v4i16>;
+}
+
+multiclass BinaryPatMCi32Scalar<ILOpCode opc, PatFrag opn>
+{
+ defm i32 : BinaryPatExpand<opc, opn, GPRI32, i32imm, i32>;
+}
+
+multiclass BinaryPatMCi32Vector<ILOpCode opc, PatFrag opn>
+{
+ defm v2i32 : BinaryPatExpand<opc, opn, GPRV2I32, v2i32imm, v2i32>;
+ defm v4i32 : BinaryPatExpand<opc, opn, GPRV4I32, v4i32imm, v4i32>;
+}
+
+multiclass BinaryPatMCi64Scalar<ILOpCode opc, PatFrag opn>
+{
+ defm i64 : BinaryPatExpand<opc, opn, GPRI64, i64imm, i64>;
+}
+
+multiclass BinaryPatMCi64Vector<ILOpCode opc, PatFrag opn>
+{
+ defm v2i64 : BinaryPatExpand<opc, opn, GPRV2I64, v2i64imm, v2i64>;
+}
+
+multiclass BinaryPatMCf32Scalar<ILOpCode opc, PatFrag opn>
+{
+ defm f32 : BinaryPatExpandFP<opc, opn, GPRF32, f32imm, f32>;
+}
+
+multiclass BinaryPatMCf32Vector<ILOpCode opc, PatFrag opn>
+{
+ defm v2f32 : BinaryPatExpandFP<opc, opn, GPRV2F32, v2f32imm, v2f32>;
+ defm v4f32 : BinaryPatExpandFP<opc, opn, GPRV4F32, v4f32imm, v4f32>;
+}
+
+
+multiclass BinaryPatMCf64Scalar<ILOpCode opc, PatFrag opn>
+{
+ defm f64 : BinaryPatExpandFP<opc, opn, GPRF64, f64imm, f64>;
+}
+
+multiclass BinaryPatMCf64Vector<ILOpCode opc, PatFrag opn>
+{
+ defm v2f64 : BinaryPatExpandFP<opc, opn, GPRV2F64, v2f64imm, v2f64>;
+}
+
+
+multiclass BinaryPatMCi32Only<ILOpCode opc, PatFrag opn>
+: BinaryPatMCi32Scalar<opc, opn>, BinaryPatMCi32Vector<opc, opn>;
+
+multiclass BinaryPatMCi32<ILOpCode opc, PatFrag opn>
+: BinaryPatMCi32Scalar<opc, opn>, BinaryPatMCi32Vector<opc, opn>,
+ BinaryPatMCi16Scalar<opc, opn>, BinaryPatMCi16Vector<opc, opn>,
+ BinaryPatMCi8Scalar< opc, opn>, BinaryPatMCi8Vector< opc, opn>;
+
+multiclass BinaryPatMCi64<ILOpCode opc, PatFrag opn>
+: BinaryPatMCi64Scalar<opc, opn>, BinaryPatMCi64Vector<opc, opn>;
+
+multiclass BinaryPatMCf32<ILOpCode opc, PatFrag opn>
+: BinaryPatMCf32Scalar<opc, opn>, BinaryPatMCf32Vector<opc, opn>;
+
+multiclass BinaryPatMCf64<ILOpCode opc, PatFrag opn>
+: BinaryPatMCf64Scalar<opc, opn>, BinaryPatMCf64Vector<opc, opn>;
+
+multiclass BinaryPatMCInt<ILOpCode opc, PatFrag opn>
+: BinaryPatMCi32<opc, opn> , BinaryPatMCi64<opc, opn>;
+
+multiclass BinaryPatMCFP<ILOpCode opc, PatFrag opn>
+: BinaryPatMCf32<opc, opn>, BinaryPatMCf64<opc, opn>;
+
+multiclass BinaryPatMC<ILOpCode opc, PatFrag opn>
+: BinaryPatMCInt<opc, opn>, BinaryPatMCFP<opc, opn>;
+
+//----------------------------------------------------------------------------//
+// Multiclasses that deal with three operand instructions.
+//----------------------------------------------------------------------------//
+multiclass TernaryOpReg<ILOpCode opc, SDNode opn,
+ RegisterClass reg, Operand oper, ValueType type, SDNode imm0>
+{
+ def rrr : ILFormat<opc,
+ (outs reg:$dst),
+ (ins reg:$src0, reg:$src1, reg:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (type reg:$dst),
+ (opn (type reg:$src0), (type reg:$src1), (type reg:$src2)))]>;
+ def iii : ILFormat<opc,
+ (outs reg:$dst),
+ (ins oper:$src0, oper:$src1, oper:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (type reg:$dst),
+ (opn (type imm0:$src0), (type imm0:$src1), (type imm0:$src2)))]>;
+ def irr : ILFormat<opc,
+ (outs reg:$dst),
+ (ins oper:$src0, reg:$src1, reg:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (type reg:$dst),
+ (opn (type imm0:$src0), (type reg:$src1), (type reg:$src2)))]>;
+ def rir : ILFormat<opc,
+ (outs reg:$dst),
+ (ins reg:$src0, oper:$src1, reg:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (type reg:$dst),
+ (opn (type reg:$src0), (type imm0:$src1), (type reg:$src2)))]>;
+ def rri : ILFormat<opc,
+ (outs reg:$dst),
+ (ins reg:$src0, reg:$src1, oper:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (type reg:$dst),
+ (opn (type reg:$src0), (type reg:$src1), (type imm0:$src2)))]>;
+ def iir : ILFormat<opc,
+ (outs reg:$dst),
+ (ins oper:$src0, oper:$src1, reg:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (type reg:$dst),
+ (opn (type imm0:$src0), (type imm0:$src1), (type reg:$src2)))]>;
+ def iri : ILFormat<opc,
+ (outs reg:$dst),
+ (ins oper:$src0, reg:$src1, oper:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (type reg:$dst),
+ (opn (type imm0:$src0), (type reg:$src1), (type imm0:$src2)))]>;
+ def rii : ILFormat<opc,
+ (outs reg:$dst),
+ (ins reg:$src0, oper:$src1, oper:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (type reg:$dst),
+ (opn (type reg:$src0), (type imm0:$src1), (type imm0:$src2)))]>;
+}
+
+multiclass TernaryOpExpand<ILOpCode opc, SDNode opn,
+ RegisterClass reg, Operand oper, ValueType type>
+ : TernaryOpReg<opc, opn, reg, oper, type, imm>;
+
+ multiclass TernaryOpExpandFP<ILOpCode opc, SDNode opn,
+ RegisterClass reg, Operand oper, ValueType type>
+ : TernaryOpReg<opc, opn, reg, oper, type, fpimm>;
+
+
+ multiclass TernaryOpMCi8Scalar<ILOpCode opc, SDNode opn>
+{
+ defm i8 : TernaryOpExpand<opc, opn, GPRI8, i8imm, i8>;
+}
+
+multiclass TernaryOpMCi8Vector<ILOpCode opc, SDNode opn>
+{
+ defm v2i8 : TernaryOpExpand<opc, opn, GPRV2I8, v2i8imm, v2i8>;
+ defm v4i8 : TernaryOpExpand<opc, opn, GPRV4I8, v4i8imm, v4i8>;
+}
+
+multiclass TernaryOpMCi16Scalar<ILOpCode opc, SDNode opn>
+{
+ defm i16 : TernaryOpExpand<opc, opn, GPRI16, i16imm, i16>;
+}
+
+multiclass TernaryOpMCi16Vector<ILOpCode opc, SDNode opn>
+{
+ defm v2i16 : TernaryOpExpand<opc, opn, GPRV2I16, v2i16imm, v2i16>;
+ defm v4i16 : TernaryOpExpand<opc, opn, GPRV4I16, v4i16imm, v4i16>;
+}
+
+multiclass TernaryOpMCi32Scalar<ILOpCode opc, SDNode opn>
+{
+ defm i32 : TernaryOpExpand<opc, opn, GPRI32, i32imm, i32>;
+}
+
+multiclass TernaryOpMCi32Vector<ILOpCode opc, SDNode opn>
+{
+ defm v2i32 : TernaryOpExpand<opc, opn, GPRV2I32, v2i32imm, v2i32>;
+ defm v4i32 : TernaryOpExpand<opc, opn, GPRV4I32, v4i32imm, v4i32>;
+}
+
+multiclass TernaryOpMCi64Scalar<ILOpCode opc, SDNode opn>
+{
+ defm i64 : TernaryOpExpand<opc, opn, GPRI64, i64imm, i64>;
+}
+
+multiclass TernaryOpMCi64Vector<ILOpCode opc, SDNode opn>
+{
+ defm v2i64 : TernaryOpExpand<opc, opn, GPRV2I64, v2i64imm, v2i64>;
+}
+
+multiclass TernaryOpMCf32Scalar<ILOpCode opc, SDNode opn>
+{
+ defm f32 : TernaryOpExpandFP<opc, opn, GPRF32, f32imm, f32>;
+}
+
+multiclass TernaryOpMCf32Vector<ILOpCode opc, SDNode opn>
+{
+ defm v2f32 : TernaryOpExpandFP<opc, opn, GPRV2F32, v2f32imm, v2f32>;
+ defm v4f32 : TernaryOpExpandFP<opc, opn, GPRV4F32, v4f32imm, v4f32>;
+}
+
+
+multiclass TernaryOpMCf64Scalar<ILOpCode opc, SDNode opn>
+{
+ defm f64 : TernaryOpExpandFP<opc, opn, GPRF64, f64imm, f64>;
+}
+
+multiclass TernaryOpMCf64Vector<ILOpCode opc, SDNode opn>
+{
+ defm v2f64 : TernaryOpExpandFP<opc, opn, GPRV2F64, v2f64imm, v2f64>;
+}
+
+multiclass TernaryOpMCi32<ILOpCode opc, SDNode opn>
+: TernaryOpMCi32Scalar<opc, opn>, TernaryOpMCi32Vector<opc, opn>,
+ TernaryOpMCi16Scalar<opc, opn>, TernaryOpMCi16Vector<opc, opn>,
+ TernaryOpMCi8Scalar< opc, opn>, TernaryOpMCi8Vector< opc, opn>;
+
+multiclass TernaryOpMCi64<ILOpCode opc, SDNode opn>
+: TernaryOpMCi64Scalar<opc, opn>, TernaryOpMCi64Vector<opc, opn>;
+
+multiclass TernaryOpMCf32<ILOpCode opc, SDNode opn>
+: TernaryOpMCf32Scalar<opc, opn>, TernaryOpMCf32Vector<opc, opn>;
+
+multiclass TernaryOpMCf64<ILOpCode opc, SDNode opn>
+: TernaryOpMCf64Scalar<opc, opn>, TernaryOpMCf64Vector<opc, opn>;
+
+multiclass TernaryOpMCInt<ILOpCode opc, SDNode opn>
+: TernaryOpMCi32<opc, opn> , TernaryOpMCi64<opc, opn>;
+
+multiclass TernaryOpMCFP<ILOpCode opc, SDNode opn>
+: TernaryOpMCf32<opc, opn>, TernaryOpMCf64<opc, opn>;
+
+multiclass TernaryOpMC<ILOpCode opc, SDNode opn>
+: TernaryOpMCInt<opc, opn>, TernaryOpMCFP<opc, opn>;
+//----------------------------------------------------------------------------//
+// Multiclasses that deal with the select instruction.
+//----------------------------------------------------------------------------//
+multiclass SelectReg<ILOpCode opc, SDNode opn,
+ RegisterClass creg, Operand coper, ValueType ctype,
+ RegisterClass reg, Operand oper, ValueType type,
+ SDNode imm0>
+{
+ def rrr : ILFormat<opc,
+ (outs reg:$dst),
+ (ins creg:$src0, reg:$src1, reg:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (type reg:$dst),
+ (opn (ctype creg:$src0), (type reg:$src1), (type reg:$src2)))]>;
+ def iii : ILFormat<opc,
+ (outs reg:$dst),
+ (ins coper:$src0, oper:$src1, oper:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (type reg:$dst),
+ (opn (ctype imm:$src0), (type imm0:$src1), (type imm0:$src2)))]>;
+ def irr : ILFormat<opc,
+ (outs reg:$dst),
+ (ins coper:$src0, reg:$src1, reg:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (type reg:$dst),
+ (opn (ctype imm:$src0), (type reg:$src1), (type reg:$src2)))]>;
+ def rir : ILFormat<opc,
+ (outs reg:$dst),
+ (ins creg:$src0, oper:$src1, reg:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (type reg:$dst),
+ (opn (ctype creg:$src0), (type imm0:$src1), (type reg:$src2)))]>;
+ def rri : ILFormat<opc,
+ (outs reg:$dst),
+ (ins creg:$src0, reg:$src1, oper:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (type reg:$dst),
+ (opn (ctype creg:$src0), (type reg:$src1), (type imm0:$src2)))]>;
+ def iir : ILFormat<opc,
+ (outs reg:$dst),
+ (ins coper:$src0, oper:$src1, reg:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (type reg:$dst),
+ (opn (ctype imm:$src0), (type imm0:$src1), (type reg:$src2)))]>;
+ def iri : ILFormat<opc,
+ (outs reg:$dst),
+ (ins coper:$src0, reg:$src1, oper:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (type reg:$dst),
+ (opn (ctype imm:$src0), (type reg:$src1), (type imm0:$src2)))]>;
+ def rii : ILFormat<opc,
+ (outs reg:$dst),
+ (ins creg:$src0, oper:$src1, oper:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (type reg:$dst),
+ (opn (ctype creg:$src0), (type imm0:$src1), (type imm0:$src2)))]>;
+
+}
+
+multiclass SelectMC<ILOpCode opc>
+{
+ defm i8 : SelectReg<opc, select, GPRI32, i32imm, i32,
+ GPRI8, i8imm, i8, imm>;
+ defm i16 : SelectReg<opc, select, GPRI32, i32imm, i32,
+ GPRI16, i16imm, i16, imm>;
+ defm i32 : SelectReg<opc, select, GPRI32, i32imm, i32,
+ GPRI32, i32imm, i32, imm>;
+ defm f32 : SelectReg<opc, select, GPRI32, i32imm, i32,
+ GPRF32, f32imm, f32, fpimm>;
+let swizzle = 2 in {
+ defm i64 : SelectReg<opc, select, GPRI64, i64imm, i64,
+ GPRI64, i64imm, i64, imm>;
+ defm f64 : SelectReg<opc, select, GPRI64, i64imm, i64,
+ GPRF64, f64imm, f64, fpimm>;
+}
+ defm v2i8 : SelectReg<opc, vselect, GPRV2I32, v2i32imm, v2i32,
+ GPRV2I8, v2i8imm, v2i8, imm>;
+ defm v2i16 : SelectReg<opc, vselect, GPRV2I32, v2i32imm, v2i32,
+ GPRV2I16, v2i16imm, v2i16, imm>;
+ defm v2i32 : SelectReg<opc, vselect, GPRV2I32, v2i32imm, v2i32,
+ GPRV2I32, v2i32imm, v2i32, imm>;
+ defm v2f32 : SelectReg<opc, vselect, GPRV2I32, v2i32imm, v2i32,
+ GPRV2F32, v2f32imm, v2f32, fpimm>;
+let swizzle = 2 in {
+ defm v2i64 : SelectReg<opc, vselect, GPRV2I64, v2i64imm, v2i64,
+ GPRV2I64, v2i64imm, v2i64, imm>;
+ defm v2f64 : SelectReg<opc, vselect, GPRV2I64, v2i64imm, v2i64,
+ GPRV2F64, v2f64imm, v2f64, fpimm>;
+}
+ defm v4i8 : SelectReg<opc, vselect, GPRV4I32, v4i32imm, v4i32,
+ GPRV4I8, v4i8imm, v4i8, imm>;
+ defm v4i16 : SelectReg<opc, vselect, GPRV4I32, v4i32imm, v4i32,
+ GPRV4I16, v4i16imm, v4i16, imm>;
+ defm v4i32 : SelectReg<opc, vselect, GPRV4I32, v4i32imm, v4i32,
+ GPRV4I32, v4i32imm, v4i32, imm>;
+ defm v4f32 : SelectReg<opc, vselect, GPRV4I32, v4i32imm, v4i32,
+ GPRV4F32, v4f32imm, v4f32, fpimm>;
+}
+//----------------------------------------------------------------------------//
+// Multiclasses that deal with two operand Pattern Fragments.
+//----------------------------------------------------------------------------//
+multiclass BinaryBaseCmp<ILOpCode opc, PatFrag opn,
+ RegisterClass dreg, ValueType dtype,
+ RegisterClass reg, Operand oper, ValueType type,
+ SDNode imm0, string ops>
+{
+ def rr : ILFormat<opc, (outs dreg:$dst),
+ (ins reg:$src0, reg:$src1),
+ !strconcat(opc.Text, ops),
+ [(set (dtype dreg:$dst),
+ (opn (type reg:$src0), (type reg:$src1)))]>;
+ def ri : ILFormat<opc, (outs dreg:$dst),
+ (ins reg:$src0, oper:$src1),
+ !strconcat(opc.Text, ops),
+ [(set (dtype dreg:$dst),
+ (opn (type reg:$src0), (type imm0:$src1)))]>;
+ def ir : ILFormat<opc, (outs dreg:$dst),
+ (ins oper:$src0, reg:$src1),
+ !strconcat(opc.Text, ops),
+ [(set (dtype dreg:$dst),
+ (opn (type imm0:$src0), (type reg:$src1)))]>;
+ def ii : ILFormat<opc, (outs dreg:$dst),
+ (ins oper:$src0, oper:$src1),
+ !strconcat(opc.Text, ops),
+ [(set (dtype dreg:$dst),
+ (opn (type imm0:$src0), (type imm0:$src1)))]>;
+}
+
+multiclass BinaryCmpReg<ILOpCode opc, PatFrag opn,
+ RegisterClass dreg, ValueType dtype,
+ RegisterClass reg, Operand oper, ValueType type>
+ : BinaryBaseCmp<opc, opn, dreg, dtype,
+ reg, oper, type, imm, " $dst, $src0, $src1">;
+
+multiclass BinaryCmpRegFP<ILOpCode opc, PatFrag opn,
+ RegisterClass dreg, ValueType dtype,
+ RegisterClass reg, Operand oper, ValueType type>
+ : BinaryBaseCmp<opc, opn, dreg, dtype,
+ reg, oper, type, fpimm, " $dst, $src0, $src1">;
+
+multiclass BinaryCmpMCi32<ILOpCode opc, PatFrag opn>
+{
+ defm i8 : BinaryCmpReg<opc, opn, GPRI32, i32, GPRI8, i8imm, i8>;
+ defm v2i8 : BinaryCmpReg<opc, opn, GPRV2I32, v2i32, GPRV2I8, v2i8imm, v2i8>;
+ defm v4i8 : BinaryCmpReg<opc, opn, GPRV4I32, v4i32, GPRV4I8, v4i8imm, v4i8>;
+ defm i16 : BinaryCmpReg<opc, opn, GPRI32, i32, GPRI16, i16imm, i16>;
+ defm v2i16 : BinaryCmpReg<opc, opn, GPRV2I32, v2i32, GPRV2I16, v2i16imm, v2i16>;
+ defm v4i16 : BinaryCmpReg<opc, opn, GPRV4I32, v4i32, GPRV4I16, v4i16imm, v4i16>;
+ defm i32 : BinaryCmpReg<opc, opn, GPRI32, i32, GPRI32, i32imm, i32>;
+ defm v2i32 : BinaryCmpReg<opc, opn, GPRV2I32, v2i32, GPRV2I32, v2i32imm, v2i32>;
+ defm v4i32 : BinaryCmpReg<opc, opn, GPRV4I32, v4i32, GPRV4I32, v4i32imm, v4i32>;
+}
+
+
+multiclass BinaryCmpMCi64<ILOpCode opc, PatFrag opn>
+{
+ defm i64 : BinaryCmpReg<opc, opn, GPRI64, i64, GPRI64, i64imm, i64>;
+ defm v2i64 : BinaryCmpReg<opc, opn, GPRV2I64, v2i64, GPRV2I64, v2i64imm, v2i64>;
+}
+
+multiclass BinaryCmpMCf32<ILOpCode opc, PatFrag opn>
+{
+ defm f32 : BinaryCmpRegFP<opc, opn, GPRI32, i32, GPRF32, f32imm, f32>;
+ defm v2f32 : BinaryCmpRegFP<opc, opn, GPRV2I32, v2i32, GPRV2F32, v2f32imm, v2f32>;
+ defm v4f32 : BinaryCmpRegFP<opc, opn, GPRV4I32, v4i32, GPRV4F32, v4f32imm, v4f32>;
+}
+
+
+multiclass BinaryCmpMCf64<ILOpCode opc, PatFrag opn>
+{
+ defm f64 : BinaryCmpRegFP<opc, opn, GPRI64, i64, GPRF64, f64imm, f64>;
+ defm v2f64 : BinaryCmpRegFP<opc, opn, GPRV2I64, v2i64, GPRV2F64, v2f64imm, v2f64>;
+}
+/**/
+ //Uncomment these if LLVM doesn't support expansion of LE/GT.
+multiclass BinaryInvCmpReg<ILOpCode opc, PatFrag opn,
+ RegisterClass dreg, ValueType dtype,
+ RegisterClass reg, Operand oper, ValueType type>
+ : BinaryBaseCmp<opc, opn, dreg, dtype,
+ reg, oper, type, imm, " $dst, $src1, $src0">;
+
+multiclass BinaryInvCmpRegFP<ILOpCode opc, PatFrag opn,
+ RegisterClass dreg, ValueType dtype,
+ RegisterClass reg, Operand oper, ValueType type>
+ : BinaryBaseCmp<opc, opn, dreg, dtype,
+ reg, oper, type, fpimm, " $dst, $src1, $src0">;
+
+multiclass BinaryInvCmpMCi32<ILOpCode opc, PatFrag opn>
+{
+ defm i8 : BinaryInvCmpReg<opc, opn, GPRI32, i32, GPRI8, i8imm, i8>;
+ defm v2i8 : BinaryInvCmpReg<opc, opn, GPRV2I32, v2i32, GPRV2I8, v2i8imm, v2i8>;
+ defm v4i8 : BinaryInvCmpReg<opc, opn, GPRV4I32, v4i32, GPRV4I8, v4i8imm, v4i8>;
+ defm i16 : BinaryInvCmpReg<opc, opn, GPRI32, i32, GPRI16, i16imm, i16>;
+ defm v2i16 : BinaryInvCmpReg<opc, opn, GPRV2I32, v2i32, GPRV2I16, v2i16imm, v2i16>;
+ defm v4i16 : BinaryInvCmpReg<opc, opn, GPRV4I32, v4i32, GPRV4I16, v4i16imm, v4i16>;
+ defm i32 : BinaryInvCmpReg<opc, opn, GPRI32, i32, GPRI32, i32imm, i32>;
+ defm v2i32 : BinaryInvCmpReg<opc, opn, GPRV2I32, v2i32, GPRV2I32, v2i32imm, v2i32>;
+ defm v4i32 : BinaryInvCmpReg<opc, opn, GPRV4I32, v4i32, GPRV4I32, v4i32imm, v4i32>;
+}
+multiclass BinaryInvCmpMCi64<ILOpCode opc, PatFrag opn>
+{
+ defm i64 : BinaryInvCmpReg<opc, opn, GPRI64, i64, GPRI64, i64imm, i64>;
+ defm v2i64 : BinaryInvCmpReg<opc, opn, GPRV2I64, v2i64, GPRV2I64, v2i64imm, v2i64>;
+}
+
+multiclass BinaryInvCmpMCf32<ILOpCode opc, PatFrag opn>
+{
+ defm f32 : BinaryInvCmpRegFP<opc, opn, GPRI32, i32, GPRF32, f32imm, f32>;
+ defm v2f32 : BinaryInvCmpRegFP<opc, opn, GPRV2I32, v2i32, GPRV2F32, v2f32imm, v2f32>;
+ defm v4f32 : BinaryInvCmpRegFP<opc, opn, GPRV4I32, v4i32, GPRV4F32, v4f32imm, v4f32>;
+}
+
+
+multiclass BinaryInvCmpMCf64<ILOpCode opc, PatFrag opn>
+{
+ defm f64 : BinaryInvCmpRegFP<opc, opn, GPRI64, i64, GPRF64, f64imm, f64>;
+ defm v2f64 : BinaryInvCmpRegFP<opc, opn, GPRV2I64, v2i64, GPRV2F64, v2f64imm, v2f64>;
+}
+/**/
+//----------------------------------------------------------------------------//
+// Multiclasses that deal with three operand intrinsics.
+//----------------------------------------------------------------------------//
+
+multiclass TernaryIntMCFull<ILOpCode opc, Intrinsic opn,
+ ValueType dtype, RegisterClass dreg,
+ ValueType stype0, RegisterClass sreg0, Operand oper0, SDNode imm0,
+ ValueType stype1, RegisterClass sreg1, Operand oper1, SDNode imm1,
+ ValueType stype2, RegisterClass sreg2, Operand oper2, SDNode imm2>
+{
+ def rrr : ILFormat<opc, (outs dreg:$dst),
+ (ins sreg0:$src0, sreg1:$src1, sreg2:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (dtype dreg:$dst),
+ (opn (stype0 sreg0:$src0), (stype1 sreg1:$src1),
+ (stype2 sreg2:$src2)))]>;
+ def iii : ILFormat<opc, (outs dreg:$dst),
+ (ins oper0:$src0, oper1:$src1, oper2:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (dtype dreg:$dst),
+ (opn (stype0 imm0:$src0), (stype1 imm1:$src1),
+ (stype2 imm2:$src2)))]>;
+ def irr : ILFormat<opc, (outs dreg:$dst),
+ (ins oper0:$src0, sreg1:$src1, sreg2:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (dtype dreg:$dst),
+ (opn (stype0 imm0:$src0), (stype1 sreg1:$src1),
+ (stype2 sreg2:$src2)))]>;
+ def rir : ILFormat<opc, (outs dreg:$dst),
+ (ins sreg0:$src0, oper1:$src1, sreg2:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (dtype dreg:$dst),
+ (opn (stype0 sreg0:$src0), (stype1 imm1:$src1),
+ (stype2 sreg2:$src2)))]>;
+ def rri : ILFormat<opc, (outs dreg:$dst),
+ (ins sreg0:$src0, sreg1:$src1, oper2:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (dtype dreg:$dst),
+ (opn (stype0 sreg0:$src0), (stype1 sreg1:$src1),
+ (stype2 imm2:$src2)))]>;
+ def iir : ILFormat<opc, (outs dreg:$dst),
+ (ins oper0:$src0, oper1:$src1, sreg2:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (dtype dreg:$dst),
+ (opn (stype0 imm0:$src0), (stype1 imm1:$src1),
+ (stype2 sreg2:$src2)))]>;
+ def iri : ILFormat<opc, (outs dreg:$dst),
+ (ins oper0:$src0, sreg1:$src1, oper2:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (dtype dreg:$dst),
+ (opn (stype0 imm0:$src0), (stype1 sreg1:$src1),
+ (stype2 imm2:$src2)))]>;
+ def rii : ILFormat<opc, (outs dreg:$dst),
+ (ins sreg0:$src0, oper1:$src1, oper2:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (dtype dreg:$dst),
+ (opn (stype0 sreg0:$src0), (stype1 imm1:$src1),
+ (stype2 imm2:$src2)))]>;
+}
+
+multiclass TernaryIntLLIL64Scalar<ILOpCode opc, Intrinsic opn>
+{
+ defm i64 : TernaryIntMCFull<opc, opn, i64, GPRI64, i64, GPRI64, i64imm, imm,
+ i32, GPRI32, i32imm, imm, i64, GPRI64, i64imm, imm>;
+}
+
+
+multiclass TernaryIntReg<ILOpCode opc, Intrinsic opn,
+ RegisterClass reg, Operand oper, ValueType type, SDNode imm0>
+{
+ def rrr : ILFormat<opc,
+ (outs reg:$dst),
+ (ins reg:$src0, reg:$src1, reg:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (type reg:$dst),
+ (opn (type reg:$src0), (type reg:$src1), (type reg:$src2)))]>;
+ def iii : ILFormat<opc,
+ (outs reg:$dst),
+ (ins oper:$src0, oper:$src1, oper:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (type reg:$dst),
+ (opn (type imm0:$src0), (type imm0:$src1), (type imm0:$src2)))]>;
+ def irr : ILFormat<opc,
+ (outs reg:$dst),
+ (ins oper:$src0, reg:$src1, reg:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (type reg:$dst),
+ (opn (type imm0:$src0), (type reg:$src1), (type reg:$src2)))]>;
+ def rir : ILFormat<opc,
+ (outs reg:$dst),
+ (ins reg:$src0, oper:$src1, reg:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (type reg:$dst),
+ (opn (type reg:$src0), (type imm0:$src1), (type reg:$src2)))]>;
+ def rri : ILFormat<opc,
+ (outs reg:$dst),
+ (ins reg:$src0, reg:$src1, oper:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (type reg:$dst),
+ (opn (type reg:$src0), (type reg:$src1), (type imm0:$src2)))]>;
+ def iir : ILFormat<opc,
+ (outs reg:$dst),
+ (ins oper:$src0, oper:$src1, reg:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (type reg:$dst),
+ (opn (type imm0:$src0), (type imm0:$src1), (type reg:$src2)))]>;
+ def iri : ILFormat<opc,
+ (outs reg:$dst),
+ (ins oper:$src0, reg:$src1, oper:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (type reg:$dst),
+ (opn (type imm0:$src0), (type reg:$src1), (type imm0:$src2)))]>;
+ def rii : ILFormat<opc,
+ (outs reg:$dst),
+ (ins reg:$src0, oper:$src1, oper:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (type reg:$dst),
+ (opn (type reg:$src0), (type imm0:$src1), (type imm0:$src2)))]>;
+}
+
+multiclass TernaryIntExpand<ILOpCode opc, Intrinsic opn,
+ RegisterClass reg, Operand oper, ValueType type>
+ : TernaryIntReg<opc, opn, reg, oper, type, imm>;
+
+ multiclass TernaryIntExpandFP<ILOpCode opc, Intrinsic opn,
+ RegisterClass reg, Operand oper, ValueType type>
+ : TernaryIntReg<opc, opn, reg, oper, type, fpimm>;
+
+
+ multiclass TernaryIntMCi8Scalar<ILOpCode opc, Intrinsic opn>
+{
+ defm i8 : TernaryIntExpand<opc, opn, GPRI8, i8imm, i8>;
+}
+
+multiclass TernaryIntMCi8Vector<ILOpCode opc, Intrinsic opn>
+{
+ defm v2i8 : TernaryIntExpand<opc, opn, GPRV2I8, v2i8imm, v2i8>;
+ defm v4i8 : TernaryIntExpand<opc, opn, GPRV4I8, v4i8imm, v4i8>;
+}
+
+multiclass TernaryIntMCi16Scalar<ILOpCode opc, Intrinsic opn>
+{
+ defm i16 : TernaryIntExpand<opc, opn, GPRI16, i16imm, i16>;
+}
+
+multiclass TernaryIntMCi16Vector<ILOpCode opc, Intrinsic opn>
+{
+ defm v2i16 : TernaryIntExpand<opc, opn, GPRV2I16, v2i16imm, v2i16>;
+ defm v4i16 : TernaryIntExpand<opc, opn, GPRV4I16, v4i16imm, v4i16>;
+}
+
+multiclass TernaryIntMCi32Scalar<ILOpCode opc, Intrinsic opn>
+{
+ defm i32 : TernaryIntExpand<opc, opn, GPRI32, i32imm, i32>;
+}
+
+multiclass TernaryIntMCi32Vector<ILOpCode opc, Intrinsic opn>
+{
+ defm v2i32 : TernaryIntExpand<opc, opn, GPRV2I32, v2i32imm, v2i32>;
+ defm v4i32 : TernaryIntExpand<opc, opn, GPRV4I32, v4i32imm, v4i32>;
+}
+
+multiclass TernaryIntMCi64Scalar<ILOpCode opc, Intrinsic opn>
+{
+ defm i64 : TernaryIntExpand<opc, opn, GPRI64, i64imm, i64>;
+}
+
+multiclass TernaryIntMCi64Vector<ILOpCode opc, Intrinsic opn>
+{
+ defm v2i64 : TernaryIntExpand<opc, opn, GPRV2I64, v2i64imm, v2i64>;
+}
+
+multiclass TernaryIntMCf32Scalar<ILOpCode opc, Intrinsic opn>
+{
+ defm f32 : TernaryIntExpandFP<opc, opn, GPRF32, f32imm, f32>;
+}
+
+multiclass TernaryIntMCf32Vector<ILOpCode opc, Intrinsic opn>
+{
+ defm v2f32 : TernaryIntExpandFP<opc, opn, GPRV2F32, v2f32imm, v2f32>;
+ defm v4f32 : TernaryIntExpandFP<opc, opn, GPRV4F32, v4f32imm, v4f32>;
+}
+
+
+multiclass TernaryIntMCf64Scalar<ILOpCode opc, Intrinsic opn>
+{
+ defm f64 : TernaryIntExpandFP<opc, opn, GPRF64, f64imm, f64>;
+}
+
+multiclass TernaryIntMCf64Vector<ILOpCode opc, Intrinsic opn>
+{
+ defm v2f64 : TernaryIntExpandFP<opc, opn, GPRV2F64, v2f64imm, v2f64>;
+}
+
+multiclass TernaryIntMCi32<ILOpCode opc, Intrinsic opn>
+: TernaryIntMCi32Scalar<opc, opn>, TernaryIntMCi32Vector<opc, opn>,
+ TernaryIntMCi16Scalar<opc, opn>, TernaryIntMCi16Vector<opc, opn>,
+ TernaryIntMCi8Scalar< opc, opn>, TernaryIntMCi8Vector< opc, opn>;
+
+multiclass TernaryIntMCi64<ILOpCode opc, Intrinsic opn>
+: TernaryIntMCi64Scalar<opc, opn>, TernaryIntMCi64Vector<opc, opn>;
+
+multiclass TernaryIntMCf32<ILOpCode opc, Intrinsic opn>
+: TernaryIntMCf32Scalar<opc, opn>, TernaryIntMCf32Vector<opc, opn>;
+
+multiclass TernaryIntMCf64<ILOpCode opc, Intrinsic opn>
+: TernaryIntMCf64Scalar<opc, opn>, TernaryIntMCf64Vector<opc, opn>;
+
+multiclass TernaryIntMCInt<ILOpCode opc, Intrinsic opn>
+: TernaryIntMCi32<opc, opn> , TernaryIntMCi64<opc, opn>;
+
+multiclass TernaryIntMCFP<ILOpCode opc, Intrinsic opn>
+: TernaryIntMCf32<opc, opn>, TernaryIntMCf64<opc, opn>;
+
+multiclass TernaryIntMC<ILOpCode opc, Intrinsic opn>
+: TernaryIntMCInt<opc, opn>, TernaryIntMCFP<opc, opn>;
+
+//----------------------------------------------------------------------------//
+// Multiclasses that deal with three operand pattern fragments.
+//----------------------------------------------------------------------------//
+multiclass TernaryPatReg<ILOpCode opc, PatFrag opn,
+ RegisterClass reg, ValueType type>
+{
+ def rrr : ILFormat<opc,
+ (outs reg:$dst),
+ (ins reg:$src0, reg:$src1, reg:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (type reg:$dst),
+ (opn (type reg:$src0), (type reg:$src1), (type reg:$src2)))]>;
+}
+multiclass TernaryNCPatReg<ILOpCode opc, PatFrag opn,
+ RegisterClass reg, Operand oper, ValueType type, SDNode imm0>
+ : TernaryPatReg<opc, opn, reg, type>
+{
+ def irr : ILFormat<opc,
+ (outs reg:$dst),
+ (ins oper:$src0, reg:$src1, reg:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (type reg:$dst),
+ (opn (type imm0:$src0), (type reg:$src1), (type reg:$src2)))]>;
+ def rri : ILFormat<opc,
+ (outs reg:$dst),
+ (ins reg:$src0, reg:$src1, oper:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (type reg:$dst),
+ (opn (type reg:$src0), (type reg:$src1), (type imm0:$src2)))]>;
+ def iir : ILFormat<opc,
+ (outs reg:$dst),
+ (ins oper:$src0, oper:$src1, reg:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (type reg:$dst),
+ (opn (type imm0:$src0), (type imm0:$src1), (type reg:$src2)))]>;
+ def iii : ILFormat<opc,
+ (outs reg:$dst),
+ (ins oper:$src0, oper:$src1, oper:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (type reg:$dst),
+ (opn (type imm0:$src0), (type imm0:$src1), (type imm0:$src2)))]>;
+ def rir : ILFormat<opc,
+ (outs reg:$dst),
+ (ins reg:$src0, oper:$src1, reg:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (type reg:$dst),
+ (opn (type reg:$src0), (type imm0:$src1), (type reg:$src2)))]>;
+ def iri : ILFormat<opc,
+ (outs reg:$dst),
+ (ins oper:$src0, reg:$src1, oper:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (type reg:$dst),
+ (opn (type imm0:$src0), (type reg:$src1), (type imm0:$src2)))]>;
+ def rii : ILFormat<opc,
+ (outs reg:$dst),
+ (ins reg:$src0, oper:$src1, oper:$src2),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set (type reg:$dst),
+ (opn (type reg:$src0), (type imm0:$src1), (type imm0:$src2)))]>;
+}
+
+multiclass TernaryPatExpand<ILOpCode opc, PatFrag opn,
+ RegisterClass reg, Operand oper, ValueType type>
+ : TernaryNCPatReg<opc, opn, reg, oper, type, imm>;
+
+ multiclass TernaryPatExpandFP<ILOpCode opc, PatFrag opn,
+ RegisterClass reg, Operand oper, ValueType type>
+ : TernaryNCPatReg<opc, opn, reg, oper, type, fpimm>;
+
+
+ multiclass TernaryPatMCi8Scalar<ILOpCode opc, PatFrag opn>
+{
+ defm i8 : TernaryPatExpand<opc, opn, GPRI8, i8imm, i8>;
+}
+
+multiclass TernaryPatMCi8Vector<ILOpCode opc, PatFrag opn>
+{
+ defm v2i8 : TernaryPatExpand<opc, opn, GPRV2I8, v2i8imm, v2i8>;
+ defm v4i8 : TernaryPatExpand<opc, opn, GPRV4I8, v4i8imm, v4i8>;
+}
+
+multiclass TernaryPatMCi16Scalar<ILOpCode opc, PatFrag opn>
+{
+ defm i16 : TernaryPatExpand<opc, opn, GPRI16, i16imm, i16>;
+}
+
+multiclass TernaryPatMCi16Vector<ILOpCode opc, PatFrag opn>
+{
+ defm v2i16 : TernaryPatExpand<opc, opn, GPRV2I16, v2i16imm, v2i16>;
+ defm v4i16 : TernaryPatExpand<opc, opn, GPRV4I16, v4i16imm, v4i16>;
+}
+
+multiclass TernaryPatMCi32Scalar<ILOpCode opc, PatFrag opn>
+{
+ defm i32 : TernaryPatExpand<opc, opn, GPRI32, i32imm, i32>;
+}
+
+multiclass TernaryPatMCi32Vector<ILOpCode opc, PatFrag opn>
+{
+ defm v2i32 : TernaryPatExpand<opc, opn, GPRV2I32, v2i32imm, v2i32>;
+ defm v4i32 : TernaryPatExpand<opc, opn, GPRV4I32, v4i32imm, v4i32>;
+}
+
+multiclass TernaryPatMCi64Scalar<ILOpCode opc, PatFrag opn>
+{
+ defm i64 : TernaryPatExpand<opc, opn, GPRI64, i64imm, i64>;
+}
+
+multiclass TernaryPatMCi64Vector<ILOpCode opc, PatFrag opn>
+{
+ defm v2i64 : TernaryPatExpand<opc, opn, GPRV2I64, v2i64imm, v2i64>;
+}
+
+multiclass TernaryPatMCf32Scalar<ILOpCode opc, PatFrag opn>
+{
+ defm f32 : TernaryPatExpandFP<opc, opn, GPRF32, f32imm, f32>;
+}
+
+multiclass TernaryPatMCf32Vector<ILOpCode opc, PatFrag opn>
+{
+ defm v2f32 : TernaryPatExpandFP<opc, opn, GPRV2F32, v2f32imm, v2f32>;
+ defm v4f32 : TernaryPatExpandFP<opc, opn, GPRV4F32, v4f32imm, v4f32>;
+}
+
+
+multiclass TernaryPatMCf64Scalar<ILOpCode opc, PatFrag opn>
+{
+ defm f64 : TernaryPatExpandFP<opc, opn, GPRF64, f64imm, f64>;
+}
+
+multiclass TernaryPatMCf64Vector<ILOpCode opc, PatFrag opn>
+{
+ defm v2f64 : TernaryPatExpandFP<opc, opn, GPRV2F64, v2f64imm, v2f64>;
+}
+
+multiclass TernaryPatMCi32<ILOpCode opc, PatFrag opn>
+: TernaryPatMCi32Scalar<opc, opn>, TernaryPatMCi32Vector<opc, opn>,
+ TernaryPatMCi16Scalar<opc, opn>, TernaryPatMCi16Vector<opc, opn>,
+ TernaryPatMCi8Scalar< opc, opn>, TernaryPatMCi8Vector< opc, opn>;
+
+multiclass TernaryPatMCi64<ILOpCode opc, PatFrag opn>
+: TernaryPatMCi64Scalar<opc, opn>, TernaryPatMCi64Vector<opc, opn>;
+
+multiclass TernaryPatMCf32<ILOpCode opc, PatFrag opn>
+: TernaryPatMCf32Scalar<opc, opn>, TernaryPatMCf32Vector<opc, opn>;
+
+multiclass TernaryPatMCf64<ILOpCode opc, PatFrag opn>
+: TernaryPatMCf64Scalar<opc, opn>, TernaryPatMCf64Vector<opc, opn>;
+
+multiclass TernaryPatMCInt<ILOpCode opc, PatFrag opn>
+: TernaryPatMCi32<opc, opn> , TernaryPatMCi64<opc, opn>;
+
+multiclass TernaryPatMCFP<ILOpCode opc, PatFrag opn>
+: TernaryPatMCf32<opc, opn>, TernaryPatMCf64<opc, opn>;
+
+multiclass TernaryPatMC<ILOpCode opc, PatFrag opn>
+: TernaryPatMCInt<opc, opn>, TernaryPatMCFP<opc, opn>;
+//----------------------------------------------------------------------------//
+// Multiclasses that deal with four operand intrinsics.
+//----------------------------------------------------------------------------//
+multiclass QuaternaryIntReg<ILOpCode opc, Intrinsic opn,
+ RegisterClass reg, Operand oper, ValueType type, SDNode imm0>
+{
+ def rrrr : ILFormat<opc,
+ (outs reg:$dst),
+ (ins reg:$src0, reg:$src1, reg:$src2, reg:$src3),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2, $src3"),
+ [(set (type reg:$dst),
+ (opn (type reg:$src0), (type reg:$src1),
+ (type reg:$src2), (type reg:$src3)))]>;
+ def iiii : ILFormat<opc,
+ (outs reg:$dst),
+ (ins oper:$src0, oper:$src1, oper:$src2, oper:$src3),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2, $src3"),
+ [(set (type reg:$dst),
+ (opn (type imm0:$src0), (type imm0:$src1),
+ (type imm0:$src2), (type imm0:$src3)))]>;
+ def irrr : ILFormat<opc,
+ (outs reg:$dst),
+ (ins oper:$src0, reg:$src1, reg:$src2, reg:$src3),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2, $src3"),
+ [(set (type reg:$dst),
+ (opn (type imm0:$src0), (type reg:$src1),
+ (type reg:$src2), (type reg:$src3)))]>;
+ def rirr : ILFormat<opc,
+ (outs reg:$dst),
+ (ins reg:$src0, oper:$src1, reg:$src2, reg:$src3),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2, $src3"),
+ [(set (type reg:$dst),
+ (opn (type reg:$src0), (type imm0:$src1),
+ (type reg:$src2), (type reg:$src3)))]>;
+ def rrir : ILFormat<opc,
+ (outs reg:$dst),
+ (ins reg:$src0, reg:$src1, oper:$src2, reg:$src3),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2, $src3"),
+ [(set (type reg:$dst),
+ (opn (type reg:$src0), (type reg:$src1),
+ (type imm0:$src2), (type reg:$src3)))]>;
+ def rrri : ILFormat<opc,
+ (outs reg:$dst),
+ (ins reg:$src0, reg:$src1, reg:$src2, oper:$src3),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2, $src3"),
+ [(set (type reg:$dst),
+ (opn (type reg:$src0), (type reg:$src1),
+ (type reg:$src2), (type imm0:$src3)))]>;
+ def iirr : ILFormat<opc,
+ (outs reg:$dst),
+ (ins oper:$src0, oper:$src1, reg:$src2, reg:$src3),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2, $src3"),
+ [(set (type reg:$dst),
+ (opn (type imm0:$src0), (type imm0:$src1),
+ (type reg:$src2), (type reg:$src3)))]>;
+ def rrii : ILFormat<opc,
+ (outs reg:$dst),
+ (ins reg:$src0, reg:$src1, oper:$src2, oper:$src3),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2, $src3"),
+ [(set (type reg:$dst),
+ (opn (type reg:$src0), (type reg:$src1),
+ (type imm0:$src2), (type imm0:$src3)))]>;
+ def irir : ILFormat<opc,
+ (outs reg:$dst),
+ (ins oper:$src0, reg:$src1, oper:$src2, reg:$src3),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2, $src3"),
+ [(set (type reg:$dst),
+ (opn (type imm0:$src0), (type reg:$src1),
+ (type imm0:$src2), (type reg:$src3)))]>;
+ def irri : ILFormat<opc,
+ (outs reg:$dst),
+ (ins oper:$src0, reg:$src1, reg:$src2, oper:$src3),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2, $src3"),
+ [(set (type reg:$dst),
+ (opn (type imm0:$src0), (type reg:$src1),
+ (type reg:$src2), (type imm0:$src3)))]>;
+ def riir : ILFormat<opc,
+ (outs reg:$dst),
+ (ins reg:$src0, oper:$src1, oper:$src2, reg:$src3),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2, $src3"),
+ [(set (type reg:$dst),
+ (opn (type reg:$src0), (type imm0:$src1),
+ (type imm0:$src2), (type reg:$src3)))]>;
+ def riri : ILFormat<opc,
+ (outs reg:$dst),
+ (ins reg:$src0, oper:$src1, reg:$src2, oper:$src3),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2, $src3"),
+ [(set (type reg:$dst),
+ (opn (type reg:$src0), (type imm0:$src1),
+ (type reg:$src2), (type imm0:$src3)))]>;
+ def iiir : ILFormat<opc,
+ (outs reg:$dst),
+ (ins oper:$src0, oper:$src1, oper:$src2, reg:$src3),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2, $src3"),
+ [(set (type reg:$dst),
+ (opn (type imm0:$src0), (type imm0:$src1),
+ (type imm0:$src2), (type reg:$src3)))]>;
+ def iiri : ILFormat<opc,
+ (outs reg:$dst),
+ (ins oper:$src0, oper:$src1, reg:$src2, oper:$src3),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2, $src3"),
+ [(set (type reg:$dst),
+ (opn (type imm0:$src0), (type imm0:$src1),
+ (type reg:$src2), (type imm0:$src3)))]>;
+ def irii : ILFormat<opc,
+ (outs reg:$dst),
+ (ins oper:$src0, reg:$src1, oper:$src2, oper:$src3),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2, $src3"),
+ [(set (type reg:$dst),
+ (opn (type imm0:$src0), (type reg:$src1),
+ (type imm0:$src2), (type imm0:$src3)))]>;
+ def riii : ILFormat<opc,
+ (outs reg:$dst),
+ (ins reg:$src0, oper:$src1, oper:$src2, oper:$src3),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2, $src3"),
+ [(set (type reg:$dst),
+ (opn (type reg:$src0), (type imm0:$src1),
+ (type imm0:$src2), (type imm0:$src3)))]>;
+}
+
+multiclass QuaternaryIntExpand<ILOpCode opc, Intrinsic opn,
+ RegisterClass reg, Operand oper, ValueType type>
+ : QuaternaryIntReg<opc, opn, reg, oper, type, imm>;
+
+ multiclass QuaternaryIntExpandFP<ILOpCode opc, Intrinsic opn,
+ RegisterClass reg, Operand oper, ValueType type>
+ : QuaternaryIntReg<opc, opn, reg, oper, type, fpimm>;
+
+
+ multiclass QuaternaryIntMCi8Scalar<ILOpCode opc, Intrinsic opn>
+{
+ defm i8 : QuaternaryIntExpand<opc, opn, GPRI8, i8imm, i8>;
+}
+
+multiclass QuaternaryIntMCi8Vector<ILOpCode opc, Intrinsic opn>
+{
+ defm v2i8 : QuaternaryIntExpand<opc, opn, GPRV2I8, v2i8imm, v2i8>;
+ defm v4i8 : QuaternaryIntExpand<opc, opn, GPRV4I8, v4i8imm, v4i8>;
+}
+
+multiclass QuaternaryIntMCi16Scalar<ILOpCode opc, Intrinsic opn>
+{
+ defm i16 : QuaternaryIntExpand<opc, opn, GPRI16, i16imm, i16>;
+}
+
+multiclass QuaternaryIntMCi16Vector<ILOpCode opc, Intrinsic opn>
+{
+ defm v2i16 : QuaternaryIntExpand<opc, opn, GPRV2I16, v2i16imm, v2i16>;
+ defm v4i16 : QuaternaryIntExpand<opc, opn, GPRV4I16, v4i16imm, v4i16>;
+}
+
+multiclass QuaternaryIntMCi32Scalar<ILOpCode opc, Intrinsic opn>
+{
+ defm i32 : QuaternaryIntExpand<opc, opn, GPRI32, i32imm, i32>;
+}
+
+multiclass QuaternaryIntMCi32Vector<ILOpCode opc, Intrinsic opn>
+{
+ defm v2i32 : QuaternaryIntExpand<opc, opn, GPRV2I32, v2i32imm, v2i32>;
+ defm v4i32 : QuaternaryIntExpand<opc, opn, GPRV4I32, v4i32imm, v4i32>;
+}
+
+multiclass QuaternaryIntMCi64Scalar<ILOpCode opc, Intrinsic opn>
+{
+ defm i64 : QuaternaryIntExpand<opc, opn, GPRI64, i64imm, i64>;
+}
+
+multiclass QuaternaryIntMCi64Vector<ILOpCode opc, Intrinsic opn>
+{
+ defm v2i64 : QuaternaryIntExpand<opc, opn, GPRV2I64, v2i64imm, v2i64>;
+}
+
+multiclass QuaternaryIntMCf32Scalar<ILOpCode opc, Intrinsic opn>
+{
+ defm f32 : QuaternaryIntExpandFP<opc, opn, GPRF32, f32imm, f32>;
+}
+
+multiclass QuaternaryIntMCf32Vector<ILOpCode opc, Intrinsic opn>
+{
+ defm v2f32 : QuaternaryIntExpandFP<opc, opn, GPRV2F32, v2f32imm, v2f32>;
+ defm v4f32 : QuaternaryIntExpandFP<opc, opn, GPRV4F32, v4f32imm, v4f32>;
+}
+
+
+multiclass QuaternaryIntMCf64Scalar<ILOpCode opc, Intrinsic opn>
+{
+ defm f64 : QuaternaryIntExpandFP<opc, opn, GPRF64, f64imm, f64>;
+}
+
+multiclass QuaternaryIntMCf64Vector<ILOpCode opc, Intrinsic opn>
+{
+ defm v2f64 : QuaternaryIntExpandFP<opc, opn, GPRV2F64, v2f64imm, v2f64>;
+}
+
+multiclass QuaternaryIntMCi32<ILOpCode opc, Intrinsic opn>
+: QuaternaryIntMCi32Scalar<opc, opn>, QuaternaryIntMCi32Vector<opc, opn>,
+ QuaternaryIntMCi16Scalar<opc, opn>, QuaternaryIntMCi16Vector<opc, opn>,
+ QuaternaryIntMCi8Scalar< opc, opn>, QuaternaryIntMCi8Vector< opc, opn>;
+
+multiclass QuaternaryIntMCi64<ILOpCode opc, Intrinsic opn>
+: QuaternaryIntMCi64Scalar<opc, opn>, QuaternaryIntMCi64Vector<opc, opn>;
+
+multiclass QuaternaryIntMCf32<ILOpCode opc, Intrinsic opn>
+: QuaternaryIntMCf32Scalar<opc, opn>, QuaternaryIntMCf32Vector<opc, opn>;
+
+multiclass QuaternaryIntMCf64<ILOpCode opc, Intrinsic opn>
+: QuaternaryIntMCf64Scalar<opc, opn>, QuaternaryIntMCf64Vector<opc, opn>;
+
+multiclass QuaternaryIntMCInt<ILOpCode opc, Intrinsic opn>
+: QuaternaryIntMCi32<opc, opn> , QuaternaryIntMCi64<opc, opn>;
+
+multiclass QuaternaryIntMCFP<ILOpCode opc, Intrinsic opn>
+: QuaternaryIntMCf32<opc, opn>, QuaternaryIntMCf64<opc, opn>;
+
+multiclass QuaternaryIntMC<ILOpCode opc, Intrinsic opn>
+: QuaternaryIntMCInt<opc, opn>, QuaternaryIntMCFP<opc, opn>;
+
+multiclass BitAlignPatFragCI32<ILOpCode opc, PatFrag node> {
+ def i32rrrr : ILFormat<opc, (outs GPRI32:$dst),
+ (ins GPRI32:$src0, GPRI32:$src1, GPRI32:$src2, GPRI32:$src3),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set GPRI32:$dst, (node GPRI32:$src0, GPRI32:$src1, GPRI32:$src2, GPRI32:$src3))]>;
+ def i32irrr : ILFormat<opc, (outs GPRI32:$dst),
+ (ins i32imm:$src0, GPRI32:$src1, GPRI32:$src2, GPRI32:$src3),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set GPRI32:$dst, (node(i32 imm:$src0), GPRI32:$src1, GPRI32:$src2, GPRI32:$src3))]>;
+ def i32rirr : ILFormat<opc, (outs GPRI32:$dst),
+ (ins GPRI32:$src0, i32imm:$src1, GPRI32:$src2, GPRI32:$src3),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set GPRI32:$dst, (node GPRI32:$src0,(i32 imm:$src1), GPRI32:$src2, GPRI32:$src3))]>;
+ def i32rrir : ILFormat<opc, (outs GPRI32:$dst),
+ (ins GPRI32:$src0, GPRI32:$src1, i32imm:$src2, GPRI32:$src3),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set GPRI32:$dst, (node GPRI32:$src0, GPRI32:$src1,(i32 imm:$src2), GPRI32:$src3))]>;
+ def i32rrri : ILFormat<opc, (outs GPRI32:$dst),
+ (ins GPRI32:$src0, GPRI32:$src1, GPRI32:$src2, i32imm:$src3),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set GPRI32:$dst, (node GPRI32:$src0, GPRI32:$src1, GPRI32:$src2,(i32 imm:$src3)))]>;
+ def i32iirr : ILFormat<opc, (outs GPRI32:$dst),
+ (ins i32imm:$src0, i32imm:$src1, GPRI32:$src2, GPRI32:$src3),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set GPRI32:$dst, (node(i32 imm:$src0),(i32 imm:$src1), GPRI32:$src2, GPRI32:$src3))]>;
+ def i32irir : ILFormat<opc, (outs GPRI32:$dst),
+ (ins i32imm:$src0, GPRI32:$src1, i32imm:$src2, GPRI32:$src3),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set GPRI32:$dst, (node(i32 imm:$src0), GPRI32:$src1,(i32 imm:$src2), GPRI32:$src3))]>;
+ def i32irri : ILFormat<opc, (outs GPRI32:$dst),
+ (ins i32imm:$src0, GPRI32:$src1, GPRI32:$src2, i32imm:$src3),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set GPRI32:$dst, (node(i32 imm:$src0), GPRI32:$src1, GPRI32:$src2,(i32 imm:$src3)))]>;
+ def i32riir : ILFormat<opc, (outs GPRI32:$dst),
+ (ins GPRI32:$src0, i32imm:$src1, i32imm:$src2, GPRI32:$src3),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set GPRI32:$dst, (node GPRI32:$src0,(i32 imm:$src1),(i32 imm:$src2), GPRI32:$src3))]>;
+ def i32riri : ILFormat<opc, (outs GPRI32:$dst),
+ (ins GPRI32:$src0, i32imm:$src1, GPRI32:$src2, i32imm:$src3),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set GPRI32:$dst, (node GPRI32:$src0,(i32 imm:$src1), GPRI32:$src2,(i32 imm:$src3)))]>;
+ def i32rrii : ILFormat<opc, (outs GPRI32:$dst),
+ (ins GPRI32:$src0, GPRI32:$src1, i32imm:$src2, i32imm:$src3),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set GPRI32:$dst, (node GPRI32:$src0, GPRI32:$src1,(i32 imm:$src2),(i32 imm:$src3)))]>;
+ def i32iiir : ILFormat<opc, (outs GPRI32:$dst),
+ (ins i32imm:$src0, i32imm:$src1, i32imm:$src2, GPRI32:$src3),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set GPRI32:$dst, (node(i32 imm:$src0),(i32 imm:$src1),(i32 imm:$src2), GPRI32:$src3))]>;
+ def i32iiri : ILFormat<opc, (outs GPRI32:$dst),
+ (ins i32imm:$src0, i32imm:$src1, GPRI32:$src2, i32imm:$src3),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set GPRI32:$dst, (node(i32 imm:$src0),(i32 imm:$src1), GPRI32:$src2,(i32 imm:$src3)))]>;
+ def i32riii : ILFormat<opc, (outs GPRI32:$dst),
+ (ins GPRI32:$src0, i32imm:$src1, i32imm:$src2, i32imm:$src3),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set GPRI32:$dst, (node GPRI32:$src0,(i32 imm:$src1),(i32 imm:$src2),(i32 imm:$src3)))]>;
+ def i32irii : ILFormat<opc, (outs GPRI32:$dst),
+ (ins i32imm:$src0, GPRI32:$src1, i32imm:$src2, i32imm:$src3),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set GPRI32:$dst, (node(i32 imm:$src0), GPRI32:$src1,(i32 imm:$src2),(i32 imm:$src3)))]>;
+ def i32iiii : ILFormat<opc, (outs GPRI32:$dst),
+ (ins i32imm:$src0, i32imm:$src1, i32imm:$src2, i32imm:$src3),
+ !strconcat(opc.Text, " $dst, $src0, $src1, $src2"),
+ [(set GPRI32:$dst, (node(i32 imm:$src0),(i32 imm:$src1),(i32 imm:$src2),(i32 imm:$src3)))]>;
+}
+
+// atomic global load
+multiclass AtomGLoadMC<Operand memOpType, ComplexPattern addrType> {
+ let load = 1, global = 1, atomic = 1, rawuav = 1 in {
+ def i8 : AtomGLoadClass<IL_OP_UAV_BYTE_LOAD, memOpType,
+ GPRI8, addrType>;
+ def i16 : AtomGLoadClass<IL_OP_UAV_SHORT_LOAD, memOpType,
+ GPRI16, addrType>;
+ def i32 : AtomGLoadClass<IL_OP_RAW_UAV_LOAD, memOpType,
+ GPRI32, addrType>;
+ def v2i32 : AtomGLoadClass<IL_OP_RAW_UAV_LOAD, memOpType,
+ GPRV2I32, addrType>;
+ def v4i32 : AtomGLoadClass<IL_OP_RAW_UAV_LOAD, memOpType,
+ GPRV4I32, addrType>;
+ }
+}
+
+// atomic global store
+multiclass AtomGStoreMC<Operand memOpType, ComplexPattern addrType> {
+ let store = 1, global = 1, atomic = 1, rawuav = 1 in {
+ def i8 : AtomGStoreClass<IL_OP_UAV_BYTE_STORE, memOpType,
+ GPRI8, addrType>;
+ def i16 : AtomGStoreClass<IL_OP_UAV_SHORT_STORE, memOpType,
+ GPRI16, addrType>;
+ def i32 : AtomGStoreClass<IL_OP_RAW_UAV_STORE, memOpType,
+ GPRI32, addrType>;
+ def v2i32 : AtomGStoreClass<IL_OP_RAW_UAV_STORE, memOpType,
+ GPRV2I32, addrType>;
+ def v4i32 : AtomGStoreClass<IL_OP_RAW_UAV_STORE, memOpType,
+ GPRV4I32, addrType>;
+ }
+}
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILNIDevice.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILNIDevice.cpp?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILNIDevice.cpp (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILNIDevice.cpp Wed Sep 12 12:43:34 2012
@@ -33,7 +33,6 @@
AMDILNIDevice::~AMDILNIDevice()
{
}
-
size_t
AMDILNIDevice::getMaxLDSSize() const
{
@@ -43,24 +42,19 @@
return 0;
}
}
-
uint32_t
AMDILNIDevice::getGeneration() const
{
return AMDILDeviceInfo::HD6XXX;
}
-
-
AMDILCaymanDevice::AMDILCaymanDevice(AMDILSubtarget *ST)
: AMDILNIDevice(ST)
{
setCaps();
}
-
AMDILCaymanDevice::~AMDILCaymanDevice()
{
}
-
void
AMDILCaymanDevice::setCaps()
{
@@ -72,4 +66,3 @@
mSWBits.reset(AMDILDeviceInfo::Signed24BitOps);
mSWBits.set(AMDILDeviceInfo::ArenaSegment);
}
-
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILNIDevice.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILNIDevice.h?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILNIDevice.h (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILNIDevice.h Wed Sep 12 12:43:34 2012
@@ -15,8 +15,7 @@
#define _AMDILNIDEVICE_H_
#include "AMDILEvergreenDevice.h"
#include "AMDILSubtarget.h"
-namespace llvm
-{
+namespace llvm {
class AMDILSubtarget;
//===---------------------------------------------------------------------===//
// NI generation of devices and their respective sub classes
@@ -28,15 +27,14 @@
// NI devices are all 64 wide wavefronts and also add support for signed 24 bit
// integer operations
-class AMDILNIDevice : public AMDILEvergreenDevice
-{
+class AMDILNIDevice : public AMDILEvergreenDevice {
public:
AMDILNIDevice(AMDILSubtarget*);
virtual ~AMDILNIDevice();
virtual size_t getMaxLDSSize() const;
virtual uint32_t getGeneration() const;
protected:
-}; // AMDILNIDevice
+}; // AMDILNIDevice
// Just as the AMDILCypressDevice is the double capable version of the
// AMDILEvergreenDevice, the AMDILCaymanDevice is the double capable version of
@@ -44,14 +42,13 @@
// standpoint is that the Cayman Device has 4 wide ALU's, whereas the rest of the
// NI family is a 5 wide.
-class AMDILCaymanDevice: public AMDILNIDevice
-{
+class AMDILCaymanDevice : public AMDILNIDevice {
public:
AMDILCaymanDevice(AMDILSubtarget*);
virtual ~AMDILCaymanDevice();
private:
virtual void setCaps();
-}; // AMDILCaymanDevice
+}; // AMDILCaymanDevice
static const unsigned int MAX_LDS_SIZE_900 = AMDILDevice::MAX_LDS_SIZE_800;
} // namespace llvm
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILNodes.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILNodes.td?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILNodes.td (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILNodes.td Wed Sep 12 12:43:34 2012
@@ -13,7 +13,6 @@
def IL_d2f : SDNode<"AMDILISD::DP_TO_FP" , SDTIL_DPToFPOp>;
-def IL_inttoany: SDNode<"AMDILISD::INTTOANY", SDTIL_IntToAny>;
//===----------------------------------------------------------------------===//
// Flow Control DAG Nodes
//===----------------------------------------------------------------------===//
@@ -50,32 +49,15 @@
// Instructions
//===--------------------------------------------------------------------===//
// Floating point math functions
-def IL_cmov_logical : SDNode<"AMDILISD::CMOVLOG", SDTIL_GenTernaryOp>;
def IL_add : SDNode<"AMDILISD::ADD" , SDTIL_GenBinaryOp,
[SDNPCommutative, SDNPAssociative]>;
-def IL_cmov : SDNode<"AMDILISD::CMOV" , SDTIL_GenBinaryOp>;
-def IL_or : SDNode<"AMDILISD::OR" ,SDTIL_GenBinaryOp,
- [SDNPCommutative, SDNPAssociative]>;
-def IL_and : SDNode<"AMDILISD::AND" ,SDTIL_GenBinaryOp,
- [SDNPCommutative, SDNPAssociative]>;
-def IL_xor : SDNode<"AMDILISD::XOR", SDTIL_GenBinaryOp,
- [SDNPCommutative, SDNPAssociative]>;
-def IL_not : SDNode<"AMDILISD::NOT", SDTIL_GenUnaryOp>;
-def IL_div_inf : SDNode<"AMDILISD::DIV_INF", SDTIL_GenBinaryOp>;
-def IL_mad : SDNode<"AMDILISD::MAD", SDTIL_GenTernaryOp>;
//===----------------------------------------------------------------------===//
// Integer functions
//===----------------------------------------------------------------------===//
-def IL_inegate : SDNode<"AMDILISD::INEGATE" , SDTIntUnaryOp>;
def IL_umul : SDNode<"AMDILISD::UMUL" , SDTIntBinOp,
[SDNPCommutative, SDNPAssociative]>;
-def IL_mov : SDNode<"AMDILISD::MOVE", SDTIL_GenUnaryOp>;
-def IL_phimov : SDNode<"AMDILISD::PHIMOVE", SDTIL_GenUnaryOp>;
def IL_bitconv : SDNode<"AMDILISD::BITCONV", SDTIL_GenBitConv>;
-def IL_ffb_hi : SDNode<"AMDILISD::IFFB_HI", SDTIL_GenUnaryOp>;
-def IL_ffb_lo : SDNode<"AMDILISD::IFFB_LO", SDTIL_GenUnaryOp>;
-def IL_smax : SDNode<"AMDILISD::SMAX", SDTIL_GenBinaryOp>;
//===----------------------------------------------------------------------===//
// Double functions
@@ -141,6 +123,10 @@
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
def atom_g_xor : SDNode<"AMDILISD::ATOM_G_XOR", SDTIL_BinAtom,
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
+def atom_g_store : SDNode<"AMDILISD::ATOM_G_STORE", SDTIL_AtomStore,
+ [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
+def atom_g_load : SDNode<"AMDILISD::ATOM_G_LOAD",SDTIL_AtomLoad,
+ [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
//===------------- 32 bit global atomics without return values ------------===//
def atom_g_add_noret : SDNode<"AMDILISD::ATOM_G_ADD_NORET", SDTIL_BinAtomNoRet,
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILOperands.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILOperands.td?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILOperands.td (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILOperands.td Wed Sep 12 12:43:34 2012
@@ -13,36 +13,38 @@
def MEM3232 : Operand<i32> {
let PrintMethod = "printMemOperand";
- let MIOperandInfo = (ops GPRI32, GPRI32);
+ let MIOperandInfo = (ops ptr_rc, GPRI32);
}
def MEM6464 : Operand<i64> {
let PrintMethod = "printMemOperand";
- let MIOperandInfo = (ops GPRI64, GPRI64);
+ let MIOperandInfo = (ops ptr_rc, GPRI64);
}
def MEM3264 : Operand<i64> {
let PrintMethod = "printMemOperand";
- let MIOperandInfo = (ops GPRI32, GPRI64);
+ let MIOperandInfo = (ops ptr_rc, GPRI64);
}
def MEM6432 : Operand<i64> {
let PrintMethod = "printMemOperand";
- let MIOperandInfo = (ops GPRI64, GPRI32);
+ let MIOperandInfo = (ops ptr_rc, GPRI32);
}
// Call target types
def calltarget : Operand<i32>;
def brtarget : Operand<OtherVT>;
-// def v2i8imm : Operand<v2i8>;
-// def v4i8imm : Operand<v4i8>;
-// def v2i16imm : Operand<v2i16>;
-// def v4i16imm : Operand<v4i16>;
-// def v2i32imm : Operand<v2i32>;
-// def v4i32imm : Operand<v4i32>;
-// def v2i64imm : Operand<v2i64>;
-// def v2f32imm : Operand<v2f32>;
-// def v4f32imm : Operand<v4f32>;
-// def v2f64imm : Operand<v2f64>;
+let OperandType = "OPERAND_IMMEDIATE" in {
+def v2i8imm : Operand<v2i8>;
+def v4i8imm : Operand<v4i8>;
+def v2i16imm : Operand<v2i16>;
+def v4i16imm : Operand<v4i16>;
+def v2i32imm : Operand<v2i32>;
+def v4i32imm : Operand<v4i32>;
+def v2i64imm : Operand<v2i64>;
+def v2f32imm : Operand<v2f32>;
+def v4f32imm : Operand<v4f32>;
+def v2f64imm : Operand<v2f64>;
+}
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILPatterns.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILPatterns.td?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILPatterns.td (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILPatterns.td Wed Sep 12 12:43:34 2012
@@ -428,78 +428,6 @@
//===----------------------------------------------------------------------===//
// Complex addressing mode patterns
//===----------------------------------------------------------------------===//
-def ADDR : ComplexPattern<i32, 2, "SelectADDR", [], []>;
-def ADDRF : ComplexPattern<i32, 2, "SelectADDR", [frameindex], []>;
-def ADDR64 : ComplexPattern<i64, 2, "SelectADDR64", [], []>;
-def ADDR64F : ComplexPattern<i64, 2, "SelectADDR64", [frameindex], []>;
+def ADDR : ComplexPattern<i32, 2, "SelectADDR", [frameindex], []>;
+def ADDR64 : ComplexPattern<i64, 2, "SelectADDR64", [frameindex], []>;
-
-//===----------------------------------------------------------------------===//
-// Conditional Instruction Pattern Leafs
-//===----------------------------------------------------------------------===//
-class IL_CC_Op<int N> : PatLeaf<(i32 N)>;
-def IL_CC_D_EQ : IL_CC_Op<0>;
-def IL_CC_D_GE : IL_CC_Op<1>;
-def IL_CC_D_LT : IL_CC_Op<2>;
-def IL_CC_D_NE : IL_CC_Op<3>;
-def IL_CC_F_EQ : IL_CC_Op<4>;
-def IL_CC_F_GE : IL_CC_Op<5>;
-def IL_CC_F_LT : IL_CC_Op<6>;
-def IL_CC_F_NE : IL_CC_Op<7>;
-def IL_CC_I_EQ : IL_CC_Op<8>;
-def IL_CC_I_GE : IL_CC_Op<9>;
-def IL_CC_I_LT : IL_CC_Op<10>;
-def IL_CC_I_NE : IL_CC_Op<11>;
-def IL_CC_U_GE : IL_CC_Op<12>;
-def IL_CC_U_LT : IL_CC_Op<13>;
-// Pseudo IL comparison instructions that aren't natively supported
-def IL_CC_F_GT : IL_CC_Op<14>;
-def IL_CC_U_GT : IL_CC_Op<15>;
-def IL_CC_I_GT : IL_CC_Op<16>;
-def IL_CC_D_GT : IL_CC_Op<17>;
-def IL_CC_F_LE : IL_CC_Op<18>;
-def IL_CC_U_LE : IL_CC_Op<19>;
-def IL_CC_I_LE : IL_CC_Op<20>;
-def IL_CC_D_LE : IL_CC_Op<21>;
-def IL_CC_F_UNE : IL_CC_Op<22>;
-def IL_CC_F_UEQ : IL_CC_Op<23>;
-def IL_CC_F_ULT : IL_CC_Op<24>;
-def IL_CC_F_UGT : IL_CC_Op<25>;
-def IL_CC_F_ULE : IL_CC_Op<26>;
-def IL_CC_F_UGE : IL_CC_Op<27>;
-def IL_CC_F_ONE : IL_CC_Op<28>;
-def IL_CC_F_OEQ : IL_CC_Op<29>;
-def IL_CC_F_OLT : IL_CC_Op<30>;
-def IL_CC_F_OGT : IL_CC_Op<31>;
-def IL_CC_F_OLE : IL_CC_Op<32>;
-def IL_CC_F_OGE : IL_CC_Op<33>;
-def IL_CC_D_UNE : IL_CC_Op<34>;
-def IL_CC_D_UEQ : IL_CC_Op<35>;
-def IL_CC_D_ULT : IL_CC_Op<36>;
-def IL_CC_D_UGT : IL_CC_Op<37>;
-def IL_CC_D_ULE : IL_CC_Op<38>;
-def IL_CC_D_UGE : IL_CC_Op<39>;
-def IL_CC_D_ONE : IL_CC_Op<30>;
-def IL_CC_D_OEQ : IL_CC_Op<41>;
-def IL_CC_D_OLT : IL_CC_Op<42>;
-def IL_CC_D_OGT : IL_CC_Op<43>;
-def IL_CC_D_OLE : IL_CC_Op<44>;
-def IL_CC_D_OGE : IL_CC_Op<45>;
-def IL_CC_U_EQ : IL_CC_Op<46>;
-def IL_CC_U_NE : IL_CC_Op<47>;
-def IL_CC_F_O : IL_CC_Op<48>;
-def IL_CC_D_O : IL_CC_Op<49>;
-def IL_CC_F_UO : IL_CC_Op<50>;
-def IL_CC_D_UO : IL_CC_Op<51>;
-def IL_CC_L_LE : IL_CC_Op<52>;
-def IL_CC_L_GE : IL_CC_Op<53>;
-def IL_CC_L_EQ : IL_CC_Op<54>;
-def IL_CC_L_NE : IL_CC_Op<55>;
-def IL_CC_L_LT : IL_CC_Op<56>;
-def IL_CC_L_GT : IL_CC_Op<57>;
-def IL_CC_UL_LE : IL_CC_Op<58>;
-def IL_CC_UL_GE : IL_CC_Op<59>;
-def IL_CC_UL_EQ : IL_CC_Op<60>;
-def IL_CC_UL_NE : IL_CC_Op<61>;
-def IL_CC_UL_LT : IL_CC_Op<62>;
-def IL_CC_UL_GT : IL_CC_Op<63>;
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILPeepholeOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILPeepholeOptimizer.cpp?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILPeepholeOptimizer.cpp (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILPeepholeOptimizer.cpp Wed Sep 12 12:43:34 2012
@@ -11,8 +11,8 @@
//
//===----------------------------------------------------------------------===//
-#define DEBUG_TYPE "PeepholeOpt"
-#ifdef DEBUG
+#define DEBUG_TYPE "peepholeopt"
+#if !defined(NDEBUG)
#define DEBUGME (DebugFlag && isCurrentDebugType(DEBUG_TYPE))
#else
#define DEBUGME 0
@@ -38,15 +38,16 @@
#include "llvm/Support/InstIterator.h"
#include "llvm/Transforms/Utils/Local.h"
#include <sstream>
+STATISTIC(PointerAssignments, "Number of dynamic pointer "
+ "assigments discovered");
+STATISTIC(PointerSubtract, "Number of pointer subtractions discovered");
STATISTIC(LocalFuncs, "Number of get_local_size(N) functions removed");
using namespace llvm;
// The Peephole optimization pass is used to do simple last minute optimizations
// that are required for correct code or to remove redundant functions
-namespace
-{
-class LLVM_LIBRARY_VISIBILITY AMDILPeepholeOpt : public FunctionPass
-{
+namespace {
+class LLVM_LIBRARY_VISIBILITY AMDILPeepholeOpt : public FunctionPass {
public:
TargetMachine &TM;
static char ID;
@@ -95,18 +96,13 @@
bool setupBitInsert(Instruction *base,
Instruction *&src,
Constant *&mask,
- Constant *&shift);
+ Constant *&shift,
+ bool &inv_mode);
// A peephole optimization to optimize [d]class calls that or the results.
bool optimizeClassInst(Instruction *inst);
// Generate F2U4 intrinisic
bool genIntrF2U4(Instruction *inst);
- // Expand the bit field insert instruction on versions of OpenCL that
- // don't support it.
- bool expandBFI(CallInst *CI);
- // Expand the bit field mask instruction on version of OpenCL that
- // don't support it.
- bool expandBFM(CallInst *CI);
// On 7XX and 8XX operations, we do not have 24 bit signed operations. So in
// this case we need to expand them. These functions check for 24bit functions
// and then expand.
@@ -150,7 +146,9 @@
For exaample: given that val = 0xFF00; start_bit = 8 and bitwidth = 8.
*/
bool
-getMaskBitfield(unsigned int val, unsigned int &start_bit, unsigned int &bitwidth)
+getMaskBitfield(unsigned int val,
+ unsigned int &start_bit,
+ unsigned int &bitwidth)
{
if (val == 0) {
// zero, no bitfield
@@ -176,7 +174,6 @@
}
return true;
}
-
bool getVectorComponent(Instruction *inst, int tid, unsigned int numElem,
Value*& vecval, unsigned& whichelem)
{
@@ -187,7 +184,8 @@
vecval = einst->getVectorOperand();
VectorType *vt = dyn_cast<VectorType>(vecval->getType());
- assert (vt && "ExtractElementInst must have a vector type as its first argument");
+ assert (
+ vt && "ExtractElementInst must have a vector type as its first argument");
Type *et = vt->getElementType();
if ( (vt->getNumElements() != numElem) ||
(et->getTypeID() != tid) ) {
@@ -201,7 +199,6 @@
whichelem = (unsigned)cv->getZExtValue();
return true;
}
-
bool getIntValue(Instruction *Inst, Value *& Src, unsigned int &src_start,
unsigned int &dst_start, unsigned int &dst_width)
{
@@ -290,11 +287,9 @@
dst_width = nbits;
return true;
}
-
} // anonymous namespace
-namespace llvm
-{
+namespace llvm {
FunctionPass *
createAMDILPeepholeOpt(TargetMachine &tm, CodeGenOpt::Level OL)
{
@@ -308,17 +303,14 @@
mDebug = DEBUGME;
optLevel = OL;
}
-
AMDILPeepholeOpt::~AMDILPeepholeOpt()
{
}
-
const char *
AMDILPeepholeOpt::getPassName() const
{
return "AMDIL PeepHole Optimization Pass";
}
-
bool
containsPointerType(Type *Ty)
{
@@ -347,7 +339,6 @@
};
return false;
}
-
bool
AMDILPeepholeOpt::dumpAllIntoArena(Function &F)
{
@@ -361,7 +352,7 @@
}
Type *DereferencedType = PT->getElementType();
if (!dyn_cast<StructType>(DereferencedType)
- ) {
+ ) {
continue;
}
if (!containsPointerType(DereferencedType)) {
@@ -404,7 +395,6 @@
atomicFuncs[x].first->setOperand(
atomicFuncs[x].first->getNumOperands()-1,
atomicFuncs[x].second);
-
}
mChanged = true;
if (mConvertAtomics) {
@@ -428,7 +418,6 @@
}
}
}
-
bool
AMDILPeepholeOpt::runOnFunction(Function &MF)
{
@@ -477,7 +466,6 @@
}
return mChanged;
}
-
bool
AMDILPeepholeOpt::optimizeCallInst(Instruction *inst)
{
@@ -497,10 +485,6 @@
if (propagateSamplerInst(CI)) {
return true;
}
- if (expandBFI(CI) || expandBFM(CI)) {
- CI->eraseFromParent();
- return true;
- }
if (convertAccurateDivide(CI)) {
expandAccurateDivide(CI);
CI->eraseFromParent();
@@ -547,6 +531,8 @@
return false;
}
if (F->getName().startswith("__atom") && !CI->getNumUses()
+ && !F->getName().startswith("__atomic_load")
+ && !F->getName().startswith("__atomic_store")
&& F->getName().find("_xchg") == StringRef::npos
&& F->getName().find("_noret") == StringRef::npos) {
std::string buffer(F->getName().str() + "_noret");
@@ -554,14 +540,14 @@
FunctionType *ptr = F->getFunctionType();
callTypes.insert(callTypes.begin(), ptr->param_begin(), ptr->param_end());
FunctionType *newFunc = FunctionType::get(Type::getVoidTy(F->getContext()),
- callTypes, false);
+ callTypes, false);
std::vector<Value*> args;
for (unsigned x = 0, y = CI->getNumArgOperands(); x < y; ++x) {
args.push_back(CI->getArgOperand(x));
}
Function *newF = dyn_cast<Function>(
- F->getParent()->getOrInsertFunction(buffer, newFunc));
+ F->getParent()->getOrInsertFunction(buffer, newFunc));
CallInst *newCI = CallInst::Create(newF, args);
newCI->insertAfter(CI);
CI->eraseFromParent();
@@ -588,7 +574,7 @@
std::string val;
ss >> val;
F = dyn_cast<Function>(
- F->getParent() ->getOrInsertFunction(val, F->getFunctionType()));
+ F->getParent()->getOrInsertFunction(val, F->getFunctionType()));
atomicFuncs.push_back(std::make_pair(CI, F));
} else {
mConvertAtomics = false;
@@ -599,12 +585,12 @@
}
return false;
}
-
bool
AMDILPeepholeOpt::setupBitInsert(Instruction *base,
Instruction *&src,
Constant *&mask,
- Constant *&shift)
+ Constant *&shift,
+ bool &inv_type)
{
if (!base) {
if (mDebug) {
@@ -612,12 +598,12 @@
}
return false;
}
- bool andOp = false;
if (base->getOpcode() == Instruction::Shl) {
shift = dyn_cast<Constant>(base->getOperand(1));
+ inv_type = true;
} else if (base->getOpcode() == Instruction::And) {
mask = dyn_cast<Constant>(base->getOperand(1));
- andOp = true;
+ inv_type = false;
} else {
if (mDebug) {
dbgs() << "Failed setup with no Shl or And instruction on base opcode!\n";
@@ -632,18 +618,13 @@
}
return false;
}
- // If we find an 'and' operation, then we don't need to
- // find the next operation as we already know the
- // bits that are valid at this point.
- if (andOp) {
- return true;
- }
if (src->getOpcode() == Instruction::Shl && !shift) {
shift = dyn_cast<Constant>(src->getOperand(1));
src = dyn_cast<Instruction>(src->getOperand(0));
} else if (src->getOpcode() == Instruction::And && !mask) {
mask = dyn_cast<Constant>(src->getOperand(1));
}
+
if (!mask && !shift) {
if (mDebug) {
dbgs() << "Failed setup since both mask and shift are NULL!\n";
@@ -716,7 +697,6 @@
}
return true;
}
-
bool
AMDILPeepholeOpt::optimizeBitInsert(Instruction *inst)
{
@@ -768,98 +748,51 @@
Constant *LHSShift = NULL, *RHSShift = NULL;
Instruction *LHS = dyn_cast<Instruction>(inst->getOperand(0));
Instruction *RHS = dyn_cast<Instruction>(inst->getOperand(1));
- if (!setupBitInsert(LHS, LHSSrc, LHSMask, LHSShift)) {
+ bool lhs_inv_type = false, rhs_inv_type = false;
+ if (!setupBitInsert(LHS, LHSSrc, LHSMask, LHSShift, lhs_inv_type)) {
if (mDebug) {
dbgs() << "Found an OR Operation that failed setup!\n";
inst->dump();
- if (LHS) {
- LHS->dump();
- }
- if (LHSSrc) {
- LHSSrc->dump();
- }
- if (LHSMask) {
- LHSMask->dump();
- }
- if (LHSShift) {
- LHSShift->dump();
- }
+ if (LHS) { LHS->dump(); }
+ if (LHSSrc) { LHSSrc->dump(); }
+ if (LHSMask) { LHSMask->dump(); }
+ if (LHSShift) { LHSShift->dump(); }
}
// There was an issue with the setup for BitInsert.
return false;
}
- if (!setupBitInsert(RHS, RHSSrc, RHSMask, RHSShift)) {
+ if (!setupBitInsert(RHS, RHSSrc, RHSMask, RHSShift, rhs_inv_type)) {
if (mDebug) {
dbgs() << "Found an OR Operation that failed setup!\n";
inst->dump();
- if (RHS) {
- RHS->dump();
- }
- if (RHSSrc) {
- RHSSrc->dump();
- }
- if (RHSMask) {
- RHSMask->dump();
- }
- if (RHSShift) {
- RHSShift->dump();
- }
+ if (RHS) { RHS->dump(); }
+ if (RHSSrc) { RHSSrc->dump(); }
+ if (RHSMask) { RHSMask->dump(); }
+ if (RHSShift) { RHSShift->dump(); }
}
// There was an issue with the setup for BitInsert.
return false;
}
if (mDebug) {
- dbgs() << "Found an OR operation that can possible be optimized to ubit insert!\n";
- dbgs() << "Op: ";
- inst->dump();
+ dbgs() <<
+ "Found an OR operation that can possible be optimized to ubit insert!\n";
+ dbgs() << "Op: "; inst->dump();
dbgs() << "LHS: ";
- if (LHS) {
- LHS->dump();
- } else {
- dbgs() << "(None)\n";
- }
+ if (LHS) { LHS->dump(); } else { dbgs() << "(None)\n"; }
dbgs() << "LHS Src: ";
- if (LHSSrc) {
- LHSSrc->dump();
- } else {
- dbgs() << "(None)\n";
- }
+ if (LHSSrc) { LHSSrc->dump(); } else { dbgs() << "(None)\n"; }
dbgs() << "LHS Mask: ";
- if (LHSMask) {
- LHSMask->dump();
- } else {
- dbgs() << "(None)\n";
- }
+ if (LHSMask) { LHSMask->dump(); } else { dbgs() << "(None)\n"; }
dbgs() << "LHS Shift: ";
- if (LHSShift) {
- LHSShift->dump();
- } else {
- dbgs() << "(None)\n";
- }
+ if (LHSShift) { LHSShift->dump(); } else { dbgs() << "(None)\n"; }
dbgs() << "RHS: ";
- if (RHS) {
- RHS->dump();
- } else {
- dbgs() << "(None)\n";
- }
+ if (RHS) { RHS->dump(); } else { dbgs() << "(None)\n"; }
dbgs() << "RHS Src: ";
- if (RHSSrc) {
- RHSSrc->dump();
- } else {
- dbgs() << "(None)\n";
- }
+ if (RHSSrc) { RHSSrc->dump(); } else { dbgs() << "(None)\n"; }
dbgs() << "RHS Mask: ";
- if (RHSMask) {
- RHSMask->dump();
- } else {
- dbgs() << "(None)\n";
- }
+ if (RHSMask) { RHSMask->dump(); } else { dbgs() << "(None)\n"; }
dbgs() << "RHS Shift: ";
- if (RHSShift) {
- RHSShift->dump();
- } else {
- dbgs() << "(None)\n";
- }
+ if (RHSShift) { RHSShift->dump(); } else { dbgs() << "(None)\n"; }
}
Constant *offset = NULL;
Constant *width = NULL;
@@ -875,16 +808,28 @@
? dyn_cast<ConstantInt>(LHSShift)->getZExtValue() : 0);
rhsShiftVal = (int32_t)(RHSShift
? dyn_cast<ConstantInt>(RHSShift)->getZExtValue() : 0);
- lhsMaskWidth = lhsMaskVal ? CountPopulation_32(lhsMaskVal) : 32 - lhsShiftVal;
- rhsMaskWidth = rhsMaskVal ? CountPopulation_32(rhsMaskVal) : 32 - rhsShiftVal;
- lhsMaskOffset = lhsMaskVal ? CountTrailingZeros_32(lhsMaskVal) : lhsShiftVal;
- rhsMaskOffset = rhsMaskVal ? CountTrailingZeros_32(rhsMaskVal) : rhsShiftVal;
+ lhsMaskWidth = CountPopulation_32(lhsMaskVal);
+ rhsMaskWidth = CountPopulation_32(rhsMaskVal);
+ lhsMaskOffset = CountTrailingZeros_32(lhsMaskVal);
+ rhsMaskOffset = CountTrailingZeros_32(rhsMaskVal);
// TODO: Handle the case of A & B | D & ~B(i.e. inverted masks).
if (mDebug) {
- dbgs() << "Found pattern: \'((A" << (LHSMask ? " & B)" : ")");
- dbgs() << (LHSShift ? " << C)" : ")") << " | ((D" ;
- dbgs() << (RHSMask ? " & E)" : ")");
- dbgs() << (RHSShift ? " << F)\'\n" : ")\'\n");
+ dbgs() << "Found pattern: \'";
+ if (lhs_inv_type) {
+ dbgs() << "((A" << (LHSShift ? " << C)" : ")");
+ dbgs() << (LHSMask ? " & B)" : ")");
+ } else {
+ dbgs() << "((A" << (LHSMask ? " & B)" : ")");
+ dbgs() << (LHSShift ? " << C)" : ")");
+ }
+ dbgs() << " | ";
+ if (rhs_inv_type) {
+ dbgs() << "((D" << (RHSMask ? " & E)" : ")");
+ dbgs() << (RHSShift ? " << F)\'\n" : ")\'\n");
+ } else {
+ dbgs() << "((D" << (RHSShift ? " << F)" : ")");
+ dbgs() << (RHSMask ? " & E)\'\n" : ")\'\n");
+ }
dbgs() << "A = LHSSrc\t\tD = RHSSrc \n";
dbgs() << "B = " << lhsMaskVal << "\t\tE = " << rhsMaskVal << "\n";
dbgs() << "C = " << lhsShiftVal << "\t\tF = " << rhsShiftVal << "\n";
@@ -893,108 +838,208 @@
dbgs() << "offset(B) = " << lhsMaskOffset;
dbgs() << "\toffset(E) = " << rhsMaskOffset << "\n";
dbgs() << "Constraints: \n";
- dbgs() << "\t(1) B ^ E == 0\n";
- dbgs() << "\t(2-LHS) B is a mask\n";
- dbgs() << "\t(2-LHS) E is a mask\n";
- dbgs() << "\t(3-LHS) (offset(B)) >= (width(E) + offset(E))\n";
- dbgs() << "\t(3-RHS) (offset(E)) >= (width(B) + offset(B))\n";
- }
- if ((lhsMaskVal || rhsMaskVal) && !(lhsMaskVal ^ rhsMaskVal)) {
- if (mDebug) {
- dbgs() << lhsMaskVal << " ^ " << rhsMaskVal;
- dbgs() << " = " << (lhsMaskVal ^ rhsMaskVal) << "\n";
- dbgs() << "Failed constraint 1!\n";
+ dbgs() << "\t(1) (B";
+ if (lhs_inv_type) {
+ dbgs() << " << C";
+ }
+ dbgs() << ") ^ (E";
+ if (rhs_inv_type) {
+ dbgs() << " << F";
+ }
+ dbgs() << ") == 0\n";
+ if (lhsMaskVal) {
+ dbgs() << "\t(2-LHS) B is a mask\n";
+ } else {
+ dbgs() << "\t(2-LHS) C > 0\n";
+ }
+ if (rhsMaskVal) {
+ dbgs() << "\t(2-RHS) E is a mask\n";
+ } else {
+ dbgs() << "\t(2-RHS) F > 0\n";
+ }
+ dbgs() << "\t(3-LHS) (B << C) is a mask\n";
+ dbgs() << "\t(3-RHS) (E << F) is a mask\n";
+ if (lhsMaskWidth) {
+ if (lhs_inv_type) {
+ dbgs() << "\t(4-LHS) (offset(B) + C) < 32)\n";
+ } else {
+ dbgs() << "\t(4-LHS) (offset(B) + width(B)) <= 32\n";
+ }
+ } else {
+ dbgs() << "\t(4-LHS) (offset(B) - C > 0\n";
+ }
+ if (rhsMaskWidth) {
+ if (rhs_inv_type) {
+ dbgs() << "\t(4-RHS) (offset(E) + F) < 32)\n";
+ } else {
+ dbgs() << "\t(4-RHS) (offset(E) + width(E)) <= 32\n";
+ }
+ } else {
+ dbgs() << "\t(4-RHS) (offset(E) - F > 0\n";
+ }
+ if (rhsMaskWidth) {
+ if (lhsMaskWidth) {
+ if (lhs_inv_type) {
+ dbgs() << "\t(5-LHS) (offset(B) + C) >= (width(E) + offset(E) + F)\n";
+ } else {
+ dbgs() << "\t(5-LHS) offset(B) >= (width(E) + offset(E) + F)\n";
+ }
+ } else {
+ dbgs() << "\t(5-LHS) C >= (width(E) + offset(E) + F)\n";
+ }
+ } else {
+ if (lhsMaskWidth) {
+ dbgs() << "\t(5-LHS) (offset(B) + C) >= F\n";
+ } else {
+ dbgs() << "\t(5-LHS) C >= F\n";
+ }
+ }
+ if (lhsMaskWidth) {
+ if (rhsMaskWidth) {
+ if (rhs_inv_type) {
+ dbgs() << "\t(5-RHS) (offset(E) + F) >= (width(B) + offset(B) + C)\n";
+ } else {
+ dbgs() << "\t(5-RHS) offset(E) >= (width(B) + offset(B) + C)\n";
+ }
+ } else {
+ dbgs() << "\t(5-RHS) F >= (width(B) + offset(B) + C)\n";
+ }
+ } else {
+ if (rhsMaskWidth) {
+ dbgs() << "\t(5-RHS) (offset(E) + F) >= C\n";
+ } else {
+ dbgs() << "\t(5-RHS) F >= C\n";
+ }
}
+ }
+ if ((lhsMaskVal ||
+ rhsMaskVal) &&
+ !((lhsMaskVal <<
+ (lhs_inv_type ? lhsShiftVal : 0)) ^
+ (rhsMaskVal << (rhs_inv_type ? rhsShiftVal : 0)))) {
+ DEBUG(dbgs() << "Failed constraint 1!\n");
return false;
}
- if (mDebug) {
- dbgs() << "LHS = " << lhsMaskOffset << "";
- dbgs() << " >= (" << rhsMaskWidth << " + " << rhsMaskOffset << ") = ";
- dbgs() << (lhsMaskOffset >= (rhsMaskWidth + rhsMaskOffset));
- dbgs() << "\nRHS = " << rhsMaskOffset << "";
- dbgs() << " >= (" << lhsMaskWidth << " + " << lhsMaskOffset << ") = ";
- dbgs() << (rhsMaskOffset >= (lhsMaskWidth + lhsMaskOffset));
- dbgs() << "\n";
- }
- if (lhsMaskOffset >= (rhsMaskWidth + rhsMaskOffset)) {
- offset = ConstantInt::get(aType, lhsMaskOffset, false);
- width = ConstantInt::get(aType, lhsMaskWidth, false);
+ if (
+ (rhsMaskWidth && lhsMaskWidth && lhs_inv_type &&
+ (lhsMaskOffset + lhsShiftVal) >=
+ (rhsMaskWidth + rhsMaskOffset + rhsShiftVal)) ||
+ (rhsMaskWidth && lhsMaskWidth && !lhs_inv_type && lhsMaskOffset >=
+ (rhsMaskWidth + rhsMaskOffset + rhsShiftVal)) ||
+ (rhsMaskWidth && !lhsMaskWidth && lhsShiftVal >=
+ (rhsMaskWidth + rhsMaskOffset + rhsShiftVal)) ||
+ (!rhsMaskWidth && lhsMaskWidth &&
+ ((lhsMaskOffset + lhsShiftVal) >= rhsShiftVal)) ||
+ (!rhsMaskWidth && !lhsMaskWidth && (lhsShiftVal >= rhsShiftVal))
+ ) {
+ if (lhsMaskVal) {
+ offset =
+ ConstantInt::get(aType,
+ lhsMaskOffset +
+ (lhs_inv_type ? lhsShiftVal : (lhsMaskOffset ? -
+ lhsShiftVal : 0)),
+ false);
+ width = ConstantInt::get(aType, lhsMaskWidth, false);
+ } else {
+ offset = ConstantInt::get(aType, lhsShiftVal, false);
+ width = ConstantInt::get(aType, lhsMaskOffset - lhsShiftVal, false);
+ }
RHSSrc = RHS;
- if (!isMask_32(lhsMaskVal) && !isShiftedMask_32(lhsMaskVal)) {
- if (mDebug) {
- dbgs() << "Value is not a Mask: " << lhsMaskVal << "\n";
- dbgs() << "Failed constraint 2!\n";
- }
+ if ((lhsMaskVal && !isMask_32(lhsMaskVal) && !isShiftedMask_32(lhsMaskVal))
+ || (!lhsMaskVal && !lhsShiftVal)) {
+ DEBUG(dbgs() << "Failed constraint 2-LHS!\n");
return false;
}
- if (!LHSShift) {
- LHSSrc = BinaryOperator::Create(Instruction::LShr, LHSSrc, offset,
- "MaskShr", LHS);
- } else if (lhsShiftVal != lhsMaskOffset) {
- LHSSrc = BinaryOperator::Create(Instruction::LShr, LHSSrc, offset,
- "MaskShr", LHS);
+ if (lhsShiftVal && !isShiftedMask_32(lhsMaskVal << lhsShiftVal)) {
+ DEBUG(dbgs() << "Failed constraint 3-LHS!\n");
+ return false;
}
- if (mDebug) {
- dbgs() << "Optimizing LHS!\n";
+ if ((lhsMaskVal && (lhsMaskOffset + lhsShiftVal) >= 32)
+ || (lhsMaskOffset - lhsShiftVal) > 32) {
+ DEBUG(dbgs() << "Failed constraint 4-LHS!\n");
+ return false;
+ }
+ // If we have a mask offset, but we don't have a shift,
+ // we need to make sure that the mask offset is returned back to 0.
+ if (!LHSShift && lhsMaskOffset) {
+ LHSSrc = BinaryOperator::Create(Instruction::LShr, LHSSrc, offset,
+ "MaskShr1", LHS);
+ } else if (!lhs_inv_type && lhsShiftVal && lhsMaskOffset) {
+ LHSSrc = BinaryOperator::Create(Instruction::LShr, LHSSrc,
+ offset, "MaskShr2", LHS);
+ offset = ConstantInt::get(aType, lhsMaskOffset, false);
+ } else if (lhs_inv_type && lhsShiftVal && lhsMaskOffset && lhsMaskWidth) {
+ LHSSrc = BinaryOperator::Create(Instruction::LShr, LHS,
+ offset, "MaskShr3", inst);
+ }
+ DEBUG(dbgs() << "Optimizing LHS!\n");
+ } else if ((lhsMaskWidth && rhsMaskWidth && rhs_inv_type &&
+ (rhsMaskOffset + rhsShiftVal) >=
+ (lhsMaskWidth + lhsMaskOffset + lhsShiftVal)) ||
+ (lhsMaskWidth && rhsMaskWidth && !rhs_inv_type && rhsMaskOffset >=
+ (lhsMaskWidth + lhsMaskOffset + lhsShiftVal)) ||
+ (lhsMaskWidth && !rhsMaskWidth && rhsShiftVal >=
+ (lhsMaskWidth + lhsMaskOffset + lhsShiftVal)) ||
+ (!lhsMaskWidth && rhsMaskWidth &&
+ ((rhsMaskOffset + rhsShiftVal) >= lhsShiftVal)) ||
+ (!lhsMaskWidth && !rhsMaskWidth && (rhsShiftVal >= lhsShiftVal))
+ ) {
+ if (rhsMaskVal) {
+ offset =
+ ConstantInt::get(aType,
+ rhsMaskOffset +
+ (rhs_inv_type ? rhsShiftVal : (rhsMaskOffset ? -
+ rhsShiftVal : 0)),
+ false);
+ width = ConstantInt::get(aType, rhsMaskWidth, false);
+ } else {
+ offset = ConstantInt::get(aType, rhsShiftVal, false);
+ width = ConstantInt::get(aType, rhsMaskOffset - rhsShiftVal, false);
}
- } else if (rhsMaskOffset >= (lhsMaskWidth + lhsMaskOffset)) {
- offset = ConstantInt::get(aType, rhsMaskOffset, false);
- width = ConstantInt::get(aType, rhsMaskWidth, false);
LHSSrc = RHSSrc;
RHSSrc = LHS;
- if (!isMask_32(rhsMaskVal) && !isShiftedMask_32(rhsMaskVal)) {
- if (mDebug) {
- dbgs() << "Non-Mask: " << rhsMaskVal << "\n";
- dbgs() << "Failed constraint 2!\n";
- }
+ if ((rhsMaskVal && !isMask_32(rhsMaskVal) && !isShiftedMask_32(rhsMaskVal))
+ || (!rhsMaskVal && !rhsShiftVal)) {
+ DEBUG(dbgs() << "Failed constraint 2-RHS!\n");
return false;
}
- if (!RHSShift) {
- LHSSrc = BinaryOperator::Create(Instruction::LShr, LHSSrc, offset,
- "MaskShr", RHS);
- } else if (rhsShiftVal != rhsMaskOffset) {
- LHSSrc = BinaryOperator::Create(Instruction::LShr, LHSSrc, offset,
- "MaskShr", RHS);
+ if (rhsShiftVal && !isShiftedMask_32(rhsMaskVal << rhsShiftVal)) {
+ DEBUG(dbgs() << "Failed constraint 3-RHS!\n");
+ return false;
}
- if (mDebug) {
- dbgs() << "Optimizing RHS!\n";
+ if ((rhsMaskVal && (rhsMaskOffset + rhsShiftVal) >= 32)
+ || (rhsMaskOffset - rhsShiftVal > 32)) {
+ DEBUG(dbgs() << "Failed constraint 4-RHS!\n");
+ return false;
}
- } else {
- if (mDebug) {
- dbgs() << "Failed constraint 3!\n";
+ if (!RHSShift && rhsMaskOffset) {
+ LHSSrc = BinaryOperator::Create(Instruction::LShr, LHSSrc, offset,
+ "MaskShr1", RHS);
+ } else if (!rhs_inv_type && rhsShiftVal && rhsMaskOffset) {
+ LHSSrc = BinaryOperator::Create(Instruction::LShr, LHSSrc,
+ offset, "MaskShr2", RHS);
+ offset = ConstantInt::get(aType, rhsMaskOffset, false);
+ } else if (rhs_inv_type && rhsShiftVal && rhsMaskWidth && rhsMaskOffset) {
+ LHSSrc = BinaryOperator::Create(Instruction::LShr, RHS,
+ offset, "MaskShr3", inst);
}
+ DEBUG(dbgs() << "Optimizing RHS!\n");
+ } else {
+ DEBUG(dbgs() << "Failed constraint 5!\n");
return false;
}
- if (mDebug) {
+ DEBUG(
dbgs() << "Width: ";
- if (width) {
- width->dump();
- } else {
- dbgs() << "(0)\n";
- }
+ if (width) { width->dump(); } else { dbgs() << "(0)\n"; }
dbgs() << "Offset: ";
- if (offset) {
- offset->dump();
- } else {
- dbgs() << "(0)\n";
- }
+ if (offset) { offset->dump(); } else { dbgs() << "(0)\n"; }
dbgs() << "LHSSrc: ";
- if (LHSSrc) {
- LHSSrc->dump();
- } else {
- dbgs() << "(0)\n";
- }
+ if (LHSSrc) { LHSSrc->dump(); } else { dbgs() << "(0)\n"; }
dbgs() << "RHSSrc: ";
- if (RHSSrc) {
- RHSSrc->dump();
- } else {
- dbgs() << "(0)\n";
- }
- }
+ if (RHSSrc) { RHSSrc->dump(); } else { dbgs() << "(0)\n"; }
+ );
if (!offset || !width) {
- if (mDebug) {
- dbgs() << "Either width or offset are NULL, failed detection!\n";
- }
+ DEBUG(dbgs() << "Either width or offset are NULL, failed detection!\n");
return false;
}
// Lets create the function signature.
@@ -1005,11 +1050,8 @@
callTypes.push_back(aType);
FunctionType *funcType = FunctionType::get(aType, callTypes, false);
std::string name = "__amdil_ubit_insert";
- if (isVector) {
- name += "_v" + itostr(numEle) + "u32";
- } else {
- name += "_u32";
- }
+ if (isVector) { name += "_v" + itostr(numEle) + "u32"; } else { name +=
+ "_u32"; }
Function *Func =
dyn_cast<Function>(inst->getParent()->getParent()->getParent()->
getOrInsertFunction(llvm::StringRef(name), funcType));
@@ -1032,15 +1074,13 @@
inst->eraseFromParent();
return true;
}
-
bool
AMDILPeepholeOpt::optimizeBFI(Instruction *inst)
{
assert (inst && (inst->getOpcode() == Instruction::Xor) &&
"optimizeBitExtract() expects Xor instruction");
if (mDebug) {
- dbgs() << "\nInst: ";
- inst->dump();
+ dbgs() << "\nInst: "; inst->dump();
}
if (optLevel == CodeGenOpt::None) {
return false;
@@ -1077,17 +1117,14 @@
// Inverted operands, swap them.
Apneg1 = dyn_cast<Constant>(inst->getOperand(0));
Ap = dyn_cast<Instruction>(inst->getOperand(1));
-
}
if (Apneg1 == NULL || Ap == NULL ||
Ap->getOpcode() != Instruction::And) {
return false;
}
if (mDebug) {
- dbgs() << "Ap: ";
- Ap->dump();
- dbgs() << "Ap-1: ";
- Apneg1->dump();
+ dbgs() << "Ap: "; Ap->dump();
+ dbgs() << "Ap-1: "; Apneg1->dump();
}
Instruction *Cp = dyn_cast<Instruction>(Ap->getOperand(0));
Instruction *A = dyn_cast<Instruction>(Ap->getOperand(1));
@@ -1095,10 +1132,8 @@
return false;
}
if (mDebug) {
- dbgs() << "A: ";
- A->dump();
- dbgs() << "Cp: ";
- Cp->dump();
+ dbgs() << "A: "; A->dump();
+ dbgs() << "Cp: "; Cp->dump();
}
if (Cp->getOpcode() != Instruction::Or
&& A->getOpcode() == Instruction::Or) {
@@ -1121,10 +1156,8 @@
return false;
}
if (mDebug) {
- dbgs() << "C: ";
- C->dump();
- dbgs() << "Bp: ";
- Bp->dump();
+ dbgs() << "C: "; C->dump();
+ dbgs() << "Bp: "; Bp->dump();
}
Constant *Bpneg1 = dyn_cast<Constant>(Bp->getOperand(1));
Instruction *B = dyn_cast<Instruction>(Bp->getOperand(0));
@@ -1136,10 +1169,8 @@
return false;
}
if (mDebug) {
- dbgs() << "B: ";
- B->dump();
- dbgs() << "Bp-1: ";
- Bpneg1->dump();
+ dbgs() << "B: "; B->dump();
+ dbgs() << "Bp-1: "; Bpneg1->dump();
}
if (aType->isVectorTy()) {
ConstantDataVector *Bpneg1v = dyn_cast<ConstantDataVector>(Bpneg1);
@@ -1227,7 +1258,6 @@
inst->eraseFromParent();
return true;
}
-
bool
AMDILPeepholeOpt::optimizeBitExtract(Instruction *inst)
{
@@ -1298,8 +1328,10 @@
"combination where the number of elements to a "
"shift and an and are different!");
for (size_t x = 0, y = AndMaskVec->getNumElements(); x < y; ++x) {
- ConstantInt *AndCI = dyn_cast<ConstantInt>(AndMaskVec->getElementAsConstant(x));
- ConstantInt *ShiftIC = dyn_cast<ConstantInt>(ShrValVec->getElementAsConstant(x));
+ ConstantInt *AndCI = dyn_cast<ConstantInt>(
+ AndMaskVec->getElementAsConstant(x));
+ ConstantInt *ShiftIC = dyn_cast<ConstantInt>(
+ ShrValVec->getElementAsConstant(x));
if (!AndCI || !ShiftIC) {
return false;
}
@@ -1375,7 +1407,6 @@
inst->eraseFromParent();
return true;
}
-
bool
getVectorComponent(Instruction *inst, int tid, unsigned int numElem,
Value*& vecval, unsigned& whichelem)
@@ -1387,7 +1418,8 @@
vecval = einst->getVectorOperand();
VectorType *vt = dyn_cast<VectorType>(vecval->getType());
- assert (!vt && "ExtractElementInst must have a vector type as its first argument");
+ assert (
+ !vt && "ExtractElementInst must have a vector type as its first argument");
Type *et = vt->getElementType();
if ( (vt->getNumElements() != numElem) ||
(et->getTypeID() != tid) ) {
@@ -1401,7 +1433,6 @@
whichelem = (unsigned)cv->getZExtValue();
return true;
}
-
bool getIntValue(Instruction *Inst, Value *& Val,
unsigned int &start_pos, unsigned int &nbits)
{
@@ -1475,7 +1506,6 @@
Val = intval;
return true;
}
-
/*
format: f_2_u4 dst, src
semantics: dist.xyzw =
@@ -1520,7 +1550,8 @@
or1 = dyn_cast<Instruction>(or1->getOperand(1));
if (!or1 || !or2) {
return false;
- } else {
+ }
+ else {
bool b1 = (or1->getOpcode() == Instruction::Or);
bool b2 = (or2->getOpcode() == Instruction::Or);
if ((b1 && b2) || (!b1 && !b2)) {
@@ -1612,7 +1643,7 @@
argtypes.push_back(v4f32val->getType());
FunctionType *functype = FunctionType::get(rtype, argtypes, false);
Function *proto_f2u4 = dyn_cast<Function>(
- mF->getParent()->getOrInsertFunction("__amdil_f_2_u4", functype));
+ mF->getParent()->getOrInsertFunction("__amdil_f_2_u4", functype));
CallInst *call_f2u4 = CallInst::Create(proto_f2u4, v4f32val, "F_2_U4", inst);
inst->replaceAllUsesWith(call_f2u4);
@@ -1620,97 +1651,14 @@
return true;
}
-
-bool
-AMDILPeepholeOpt::expandBFI(CallInst *CI)
-{
- if (!CI || mSTM->calVersion() > CAL_VERSION_SC_150) {
- return false;
- }
- Value *LHS = CI->getOperand(CI->getNumOperands() - 1);
- if (!LHS->getName().startswith("__amdil_bfi")) {
- return false;
- }
- Type* type = CI->getOperand(0)->getType();
- Constant *negOneConst = NULL;
- if (type->isVectorTy()) {
- std::vector<Constant *> negOneVals;
- negOneConst = ConstantInt::get(CI->getContext(),
- APInt(32, StringRef("-1"), 10));
- for (size_t x = 0,
- y = dyn_cast<VectorType>(type)->getNumElements(); x < y; ++x) {
- negOneVals.push_back(negOneConst);
- }
- negOneConst = ConstantVector::get(negOneVals);
- } else {
- negOneConst = ConstantInt::get(CI->getContext(),
- APInt(32, StringRef("-1"), 10));
- }
- // __amdil_bfi => (A & B) | (~A & C)
- BinaryOperator *lhs =
- BinaryOperator::Create(Instruction::And, CI->getOperand(0),
- CI->getOperand(1), "bfi_and", CI);
- BinaryOperator *rhs =
- BinaryOperator::Create(Instruction::Xor, CI->getOperand(0), negOneConst,
- "bfi_not", CI);
- rhs = BinaryOperator::Create(Instruction::And, rhs, CI->getOperand(2),
- "bfi_and", CI);
- lhs = BinaryOperator::Create(Instruction::Or, lhs, rhs, "bfi_or", CI);
- CI->replaceAllUsesWith(lhs);
- return true;
-}
-
-bool
-AMDILPeepholeOpt::expandBFM(CallInst *CI)
-{
- if (!CI || mSTM->calVersion() > CAL_VERSION_SC_150) {
- return false;
- }
- Value *LHS = CI->getOperand(CI->getNumOperands() - 1);
- if (!LHS->getName().startswith("__amdil_bfm")) {
- return false;
- }
- // __amdil_bfm => ((1 << (src0 & 0x1F)) - 1) << (src1 & 0x1f)
- Constant *newMaskConst = NULL;
- Constant *newShiftConst = NULL;
- Type* type = CI->getOperand(0)->getType();
- if (type->isVectorTy()) {
- std::vector<Constant*> newMaskVals, newShiftVals;
- newMaskConst = ConstantInt::get(Type::getInt32Ty(*mCTX), 0x1F);
- newShiftConst = ConstantInt::get(Type::getInt32Ty(*mCTX), 1);
- for (size_t x = 0,
- y = dyn_cast<VectorType>(type)->getNumElements(); x < y; ++x) {
- newMaskVals.push_back(newMaskConst);
- newShiftVals.push_back(newShiftConst);
- }
- newMaskConst = ConstantVector::get(newMaskVals);
- newShiftConst = ConstantVector::get(newShiftVals);
- } else {
- newMaskConst = ConstantInt::get(Type::getInt32Ty(*mCTX), 0x1F);
- newShiftConst = ConstantInt::get(Type::getInt32Ty(*mCTX), 1);
- }
- BinaryOperator *lhs =
- BinaryOperator::Create(Instruction::And, CI->getOperand(0),
- newMaskConst, "bfm_mask", CI);
- lhs = BinaryOperator::Create(Instruction::Shl, newShiftConst,
- lhs, "bfm_shl", CI);
- lhs = BinaryOperator::Create(Instruction::Sub, lhs,
- newShiftConst, "bfm_sub", CI);
- BinaryOperator *rhs =
- BinaryOperator::Create(Instruction::And, CI->getOperand(1),
- newMaskConst, "bfm_mask", CI);
- lhs = BinaryOperator::Create(Instruction::Shl, lhs, rhs, "bfm_shl", CI);
- CI->replaceAllUsesWith(lhs);
- return true;
-}
-
bool
AMDILPeepholeOpt::instLevelOptimizations(Instruction* inst)
{
assert (inst && "inst should not be NULL");
bool isDebug = (optLevel == CodeGenOpt::None);
- bool isEGOrLater = (mSTM->device()->getGeneration() >= AMDILDeviceInfo::HD5XXX);
+ bool isEGOrLater =
+ (mSTM->device()->getGeneration() >= AMDILDeviceInfo::HD5XXX);
// Remove dead inst (probably should do it in caller)
if (!isDebug && isInstructionTriviallyDead(inst)) {
@@ -1761,7 +1709,6 @@
}
return false;
}
-
bool
AMDILPeepholeOpt::correctMisalignedMemOp(Instruction *inst)
{
@@ -1813,7 +1760,6 @@
}
return true;
}
-
void
AMDILPeepholeOpt::expandSigned24BitOps(CallInst *CI)
{
@@ -1842,8 +1788,8 @@
name += "_i32";
}
Function *Func = dyn_cast<Function>(
- CI->getParent()->getParent()->getParent()->
- getOrInsertFunction(llvm::StringRef(name), funcType));
+ CI->getParent()->getParent()->getParent()->
+ getOrInsertFunction(llvm::StringRef(name), funcType));
Value *Operands[3] = {
CI->getOperand(0),
CI->getOperand(1),
@@ -1874,8 +1820,8 @@
name += "_i32";
}
Function *Func = dyn_cast<Function>(
- CI->getParent()->getParent()->getParent()->
- getOrInsertFunction(llvm::StringRef(name), funcType));
+ CI->getParent()->getParent()->getParent()->
+ getOrInsertFunction(llvm::StringRef(name), funcType));
Value *Operands[2] = {
CI->getOperand(0),
CI->getOperand(1)
@@ -1885,7 +1831,6 @@
CI->replaceAllUsesWith(nCI);
}
}
-
bool
AMDILPeepholeOpt::isRWGLocalOpt(CallInst *CI)
{
@@ -1900,7 +1845,6 @@
// information.
&& mAMI->getKernel(mF->getName()));
}
-
void
AMDILPeepholeOpt::expandRWGLocalOpt(CallInst *CI)
{
@@ -1920,7 +1864,6 @@
++LocalFuncs;
return;
}
-
bool
AMDILPeepholeOpt::convertAccurateDivide(CallInst *CI)
{
@@ -1936,7 +1879,6 @@
return CI->getOperand(CI->getNumOperands() - 1)->getName().substr(0, 20)
== "__amdil_improved_div";
}
-
void
AMDILPeepholeOpt::expandAccurateDivide(CallInst *CI)
{
@@ -1947,7 +1889,6 @@
CI->getOperand(1), "fdiv32", CI);
CI->replaceAllUsesWith(divOp);
}
-
bool
AMDILPeepholeOpt::propagateSamplerInst(CallInst *CI)
{
@@ -2011,19 +1952,16 @@
lInst->replaceAllUsesWith(samplerVal);
return true;
}
-
bool
AMDILPeepholeOpt::doInitialization(Module &M)
{
return false;
}
-
bool
AMDILPeepholeOpt::doFinalization(Module &M)
{
return false;
}
-
void
AMDILPeepholeOpt::getAnalysisUsage(AnalysisUsage &AU) const
{
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILPointerManager.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILPointerManager.cpp?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILPointerManager.cpp (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILPointerManager.cpp Wed Sep 12 12:43:34 2012
@@ -46,9 +46,7 @@
#define SAMPLER_INDEX 3
#define SAMPLER_ARG_COUNT 5
using namespace llvm;
-char AMDILPointerManager::ID = 0;
-namespace llvm
-{
+namespace llvm {
FunctionPass*
createAMDILPointerManager(TargetMachine &tm, CodeGenOpt::Level OL)
{
@@ -57,25 +55,25 @@
}
}
-AMDILPointerManager::AMDILPointerManager(
- TargetMachine &tm,
- CodeGenOpt::Level OL) :
- MachineFunctionPass(ID),
- TM(tm)
+namespace llvm
{
- initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
+extern void initializeAMDILPointerManagerPass(llvm::PassRegistry&);
}
-AMDILPointerManager::~AMDILPointerManager()
+char AMDILPointerManager::ID = 0;
+INITIALIZE_PASS(AMDILPointerManager, "pointer-manager",
+ "AMDIL Pointer Manager", false, false);
+
+AMDILPointerManager::AMDILPointerManager()
+ : MachineFunctionPass(ID)
{
+ initializeAMDILPointerManagerPass(*PassRegistry::getPassRegistry());
}
-
const char*
AMDILPointerManager::getPassName() const
{
return "AMD IL Default Pointer Manager Pass";
}
-
void
AMDILPointerManager::getAnalysisUsage(AnalysisUsage &AU) const
{
@@ -83,13 +81,15 @@
AU.addRequiredID(MachineDominatorsID);
MachineFunctionPass::getAnalysisUsage(AU);
}
-
// The default pointer manager just assigns the default ID's to
// each load/store instruction and does nothing else. This is
// the pointer manager for the 7XX series of cards.
bool
AMDILPointerManager::runOnMachineFunction(MachineFunction &MF)
{
+ const TargetMachine& TM = MF.getTarget();
+ const AMDILTargetMachine *ATM
+ = reinterpret_cast<const AMDILTargetMachine*>(&TM);
if (DEBUGME) {
dbgs() << getPassName() << "\n";
dbgs() << MF.getFunction()->getName() << "\n";
@@ -98,44 +98,30 @@
// On the 7XX we don't have to do any special processing, so we
// can just allocate the default ID and be done with it.
AMDILPointerManagerImpl impl(MF, TM);
- impl.allocateDefaultIDs(TM);
- clearTempMIFlags(MF);
- return false;
+ bool changed = impl.perform();
+ return changed;
}
-
-void
-AMDILPointerManager::clearTempMIFlags(MachineFunction &MF)
+namespace llvm
{
- for (MachineFunction::iterator mfBegin = MF.begin(),
- mfEnd = MF.end(); mfBegin != mfEnd; ++mfBegin) {
- MachineBasicBlock *MB = mfBegin;
- for (MachineBasicBlock::instr_iterator mbb = MB->instr_begin(), mbe = MB->instr_end();
- mbb != mbe; ++mbb) {
- MachineInstr *MI = mbb;
- AMDILAS::InstrResEnc curRes;
- getAsmPrinterFlags(MI, curRes);
- // Clear temporary flas
- curRes.bits.isImage = 0;
- curRes.bits.ConflictPtr = 0;
- curRes.bits.ByteStore = 0;
- curRes.bits.PointerPath = 0;
- setAsmPrinterFlags(MI, curRes);
- }
- }
+extern void initializeAMDILEGPointerManagerPass(llvm::PassRegistry&);
}
+char AMDILEGPointerManager::ID = 0;
+INITIALIZE_PASS(AMDILEGPointerManager, "eg-pointer-manager",
+ "AMDIL EG Pointer Manager", false, false);
-AMDILEGPointerManager::AMDILEGPointerManager(
- TargetMachine &tm,
- CodeGenOpt::Level OL) :
- AMDILPointerManager(tm, OL)
+AMDILEGPointerManager::AMDILEGPointerManager()
+ : MachineFunctionPass(ID)
{
+ initializeAMDILEGPointerManagerPass(*PassRegistry::getPassRegistry());
}
-
-AMDILEGPointerManager::~AMDILEGPointerManager()
+void
+AMDILEGPointerManager::getAnalysisUsage(AnalysisUsage &AU) const
{
+ AU.setPreservesAll();
+ AU.addRequiredID(MachineDominatorsID);
+ MachineFunctionPass::getAnalysisUsage(AU);
}
-
bool
AMDILEGPointerManager::runOnMachineFunction(MachineFunction &MF)
{
@@ -145,41 +131,65 @@
MF.dump();
}
- AMDILPointerManagerImpl impl(MF, TM);
+ const TargetMachine& TM = MF.getTarget();
+ AMDILEGPointerManagerImpl impl(MF, TM);
bool changed = impl.perform();
- clearTempMIFlags(MF);
return changed;
}
-
const char*
AMDILEGPointerManager::getPassName() const
{
return "AMD IL EG Pointer Manager Pass";
}
-
AMDILPointerManagerImpl::AMDILPointerManagerImpl(MachineFunction& mf,
- TargetMachine& tm)
+ const TargetMachine& tm)
: MF(mf), TM(tm)
{
+ mMFI = MF.getInfo<AMDILMachineFunctionInfo>();
ATM = reinterpret_cast<const AMDILTargetMachine*>(&TM);
STM = ATM->getSubtargetImpl();
KM = STM->getKernelManager();
mAMI = &(MF.getMMI().getObjFileInfo<AMDILModuleInfo>());
- mMFI = MF.getInfo<AMDILMachineFunctionInfo>();
+}
+bool AMDILPointerManagerImpl::perform()
+{
+ allocateDefaultIDs();
+ clearTempMIFlags(MF);
+ return false;
+}
+void
+AMDILPointerManagerImpl::clearTempMIFlags(MachineFunction &MF)
+{
+ for (MachineFunction::iterator mfBegin = MF.begin(),
+ mfEnd = MF.end(); mfBegin != mfEnd; ++mfBegin) {
+ MachineBasicBlock *MB = mfBegin;
+ for (MachineBasicBlock::instr_iterator mbb = MB->instr_begin(),
+ mbe = MB->instr_end();
+ mbb != mbe; ++mbb) {
+ MachineInstr *MI = mbb;
+ AMDILAS::InstrResEnc curRes;
+ getAsmPrinterFlags(MI, curRes);
+ // Clear temporary flas
+ curRes.bits.isImage = 0;
+ curRes.bits.ConflictPtr = 0;
+ curRes.bits.ByteStore = 0;
+ curRes.bits.PointerPath = 0;
+ setAsmPrinterFlags(MI, curRes);
+ }
+ }
+}
+AMDILEGPointerManagerImpl::AMDILEGPointerManagerImpl(MachineFunction& mf,
+ const TargetMachine& tm)
+ : AMDILPointerManagerImpl(mf, tm)
+{
numWriteImages = 0;
+ doPerPointerLDS = false;
}
-
std::string
-AMDILPointerManagerImpl::findSamplerName(TargetMachine &TM, MachineInstr* MI, unsigned &val)
+AMDILEGPointerManagerImpl::findSamplerNameFromReg(unsigned reg, unsigned &val)
{
std::string sampler = "unknown";
- assert(MI->getNumOperands() == SAMPLER_ARG_COUNT && "Only an "
- "image read instruction with SAMPLER_ARG_COUNT arguments can "
- "have a sampler.");
- assert(MI->getOperand(SAMPLER_INDEX).isReg() &&
- "Argument SAMPLER_INDEX must be a register to call this function");
val = ~0U;
- unsigned reg = MI->getOperand(SAMPLER_INDEX).getReg();
// If this register points to an argument, then
// we can return the argument name.
if (dyn_cast_or_null<Argument>(lookupTable[reg].second.second)) {
@@ -195,19 +205,21 @@
// In the optimized case, the instruction that defined
// register from operand #3 is a private load.
MachineRegisterInfo ®Info = MF.getRegInfo();
- assert(!regInfo.def_empty(reg)
- && "We don't have any defs of this register, but we aren't an argument!");
+ assert(!regInfo.def_empty(
+ reg)
+ &&
+ "We don't have any defs of this register, but we aren't an argument!");
MachineOperand& defOp = regInfo.reg_begin(reg).getOperand();
-
MachineInstr *defMI = defOp.getParent();
- if (isPrivateInst(TM, defMI) && isLoadInst(TM, defMI)) {
+
+ if (isPrivateInst(defMI) && isPtrLoadInst(defMI)) {
if (defMI->getOperand(1).isFI()) {
RegValPair &fiRVP = FIToPtrMap[defMI->getOperand(1).getIndex()];
if (fiRVP.second.second && dyn_cast<Argument>(fiRVP.second.second)) {
return fiRVP.second.second->getName();
} else if (!fiRVP.second.second && fiRVP.first) {
- defOp = regInfo.reg_begin(fiRVP.first).getOperand();
+ defOp = regInfo.reg_begin(fiRVP.first).getOperand();
defMI = defOp.getParent();
if (defMI->getOperand(1).isImm()) {
val = defMI->getOperand(1).getImm();
@@ -222,15 +234,60 @@
}
} else {
// FIXME: Fix the case where the value stored is not a kernel argument and not a situation which is modified by AMDdbgmove pass.
- assert(!"Found a private load of a sampler where the value isn't an argument!");
+ assert(
+ !
+ "Found a private load of a sampler where the value isn't an argument!");
}
} else {
// FIXME: Fix the case where someone dynamically loads a sampler value
// from private memory. This is problematic because we need to know the
// sampler value at compile time and if it is dynamically loaded, we won't
// know what sampler value to use.
- assert(!"Found a private load of a sampler that isn't from a frame index!");
+ assert(
+ !"Found a private load of a sampler that isn't from a frame index!");
}
+ } else if (isConstantInst(defMI) && isPtrLoadInst(defMI)) {
+ if (defMI->hasOneMemOperand()) {
+ const Value *memRef = (*defMI->memoperands_begin())->getValue();
+ if (dyn_cast<Argument>(memRef)) {
+ return memRef->getName();
+ } else if (dyn_cast<GlobalVariable>(memRef)) {
+ const GlobalVariable *gvRef = dyn_cast<GlobalVariable>(memRef);
+ if (gvRef->hasInitializer()) {
+ if (dyn_cast<ConstantInt>(gvRef->getInitializer())) {
+ char buffer[1024];
+ sprintf(buffer, "_%u", (uint32_t)dyn_cast<ConstantInt>(
+ gvRef->getInitializer())->getZExtValue());
+ return sampler + std::string(buffer);
+ } else {
+ // FIXME: Found a case where a non-integer initializer
+ // was found!
+ assert(!"Found a case we don't handle!");
+ }
+ } else {
+ // FIXME: Found a global sampler from the constant address space
+ // that does not have an initializer, this isn't legal in OpenCL.
+ assert(!"Found a constant global sampler without an initializer!");
+ }
+ } else {
+ // FIXME: We are loading from a constant pointer that is not
+ // a global variable or an argument, how is that possible?
+ assert(!"Found a constant load for a value type that isn't understood.");
+ }
+ } else {
+ // FIXME: What do we do if we have a load from a constant that
+ // does not memory operand associated with it!
+ assert(!"Found a constant load but no memory operand!");
+ }
+ } else if (defMI->getOpcode() == TargetOpcode::COPY) {
+ // Somehow are a copy instruction, we need to further parse up and
+ // see if we can determine the sampler name.
+ return findSamplerNameFromReg(defMI->getOperand(1).getReg(), val);
+ } else if (defMI->getOpcode() == AMDIL::LOADCONSTi32) {
+ char buffer[256];
+ memset(buffer, 0, sizeof(buffer));
+ ::sprintf(buffer,"_%d", (int32_t)defMI->getOperand(1).getImm());
+ sampler += buffer;
} else {
// FIXME: Handle the case where the def is neither a private instruction
// and not a load instruction. This shouldn't occur, but putting an assertion
@@ -239,58 +296,89 @@
}
return sampler;
}
+std::string
+AMDILEGPointerManagerImpl::findSamplerName(MachineInstr* MI, unsigned &val)
+{
+ assert(MI->getNumOperands() == SAMPLER_ARG_COUNT && "Only an "
+ "image read instruction with SAMPLER_ARG_COUNT arguments can "
+ "have a sampler.");
+ assert(MI->getOperand(SAMPLER_INDEX).isReg() &&
+ "Argument SAMPLER_INDEX must be a register to call this function");
+ unsigned reg = MI->getOperand(SAMPLER_INDEX).getReg();
+ return findSamplerNameFromReg(reg, val);
+}
+// initialize localPtrSets and localPtr2SetIdMap
+// initialize localPtrSets so that each global local pointer is in its own set,
+// and all argument local pointers are in the default local buffer set
+// then map the local pointers to the id of the set that it belongs
+void AMDILEGPointerManagerImpl::initializeLocalPtrSets()
+{
+ const AMDILKernel *krnl = mAMI->getKernel(MF.getFunction()->getName());
+ const AMDILLocalArg* lvgv = krnl->lvgv;
+ if (lvgv == NULL) return;
+ localPtrSets.reserve(lvgv->local.size() + 1);
+
+ // first put local pointer arguments to the default buffer set
+ localPtrSets.push_back(SmallValSet());
+ for (ValueSet::iterator siBegin = localPtrs.begin(), siEnd = localPtrs.end();
+ siBegin != siEnd; ++siBegin) {
+ const Value* val = *siBegin;
+ if (isa<GlobalValue>(val)) continue;
+
+ localPtrSets.back().insert(val);
+ localPtr2SetIdMap[val] = 0;
+ }
+ // next put each non-argument local pointer in its own set
+ for (ValueSet::iterator siBegin = localPtrs.begin(), siEnd = localPtrs.end();
+ siBegin != siEnd; ++siBegin) {
+ const Value* val = *siBegin;
+ if (!isa<GlobalValue>(val)) continue;
+ localPtrSets.push_back(SmallValSet());
+ localPtrSets.back().insert(val);
+ localPtr2SetIdMap[val] = localPtrSets.size() - 1;
+ }
+}
// Helper function to determine if the current pointer is from the
// local, region or private address spaces.
static bool
-isLRPInst(TargetMachine &TM,
- MachineInstr *MI,
- const AMDILTargetMachine *ATM)
-{
- const AMDILSubtarget *STM
- = ATM->getSubtargetImpl();
- if (!MI) {
- return false;
- }
- if ((isRegionInst(TM, MI)
+isLRPInst(MachineInstr *MI, const AMDILSubtarget *STM)
+{
+ if ((isRegionInst(MI)
&& STM->device()->usesHardware(AMDILDeviceInfo::RegionMem))
- || (isLocalInst(TM, MI)
+ || (isLocalInst(MI)
&& STM->device()->usesHardware(AMDILDeviceInfo::LocalMem))
- || (isPrivateInst(TM, MI)
+ || (isPrivateInst(MI)
&& STM->device()->usesHardware(AMDILDeviceInfo::PrivateMem))
// FIXME: This is a hack since the frontend doesn't recognize semaphores yet.
- || isSemaphoreInst(TM, MI)) {
+ || isSemaphoreInst(MI)) {
return true;
}
return false;
}
-
/// Helper function to determine if the I/O instruction uses
/// global device memory or not.
static bool
usesGlobal(
- TargetMachine &TM,
+ const TargetMachine &TM,
const AMDILTargetMachine *ATM,
- MachineInstr *MI)
-{
+ MachineInstr *MI) {
const AMDILSubtarget *STM = ATM->getSubtargetImpl();
- return (isGlobalInst(TM, MI)
- || (isRegionInst(TM, MI)
+ return (isGlobalInst(MI)
+ || (isRegionInst(MI)
&& !STM->device()->usesHardware(AMDILDeviceInfo::RegionMem))
- || (isLocalInst(TM, MI)
+ || (isLocalInst(MI)
&& !STM->device()->usesHardware(AMDILDeviceInfo::LocalMem))
- || (isConstantInst(TM, MI)
+ || (isConstantInst(MI)
&& !STM->device()->usesHardware(AMDILDeviceInfo::ConstantMem))
- || (isPrivateInst(TM, MI)
+ || (isPrivateInst(MI)
&& !STM->device()->usesHardware(AMDILDeviceInfo::PrivateMem)));
}
-
// Helper function that allocates the default resource ID for the
// respective I/O types.
void
AMDILPointerManagerImpl::allocateDefaultID(
- TargetMachine &TM,
AMDILAS::InstrResEnc &curRes,
MachineInstr *MI,
bool addID)
@@ -302,11 +390,11 @@
// If we use global memory, lets set the Operand to
// the ARENA_UAV_ID.
if (usesGlobal(TM, ATM, MI)
- || isGlobalAtomic(TM, MI) || is64BitGlobalAtomic(TM, MI)
- || isArenaAtomic(TM, MI)) {
+ || isGlobalAtomic(MI) || is64BitGlobalAtomic(MI)
+ || isArenaAtomic(MI)) {
curRes.bits.ResourceID =
STM->device()->getResourceID(AMDILDevice::GLOBAL_ID);
- if (isAtomicInst(TM, MI)) {
+ if (isAtomicInst(MI)) {
MI->getOperand(MI->getNumOperands()-1)
.setImm(curRes.bits.ResourceID);
}
@@ -318,35 +406,35 @@
if (addID) {
mMFI->uav_insert(curRes.bits.ResourceID);
}
- } else if (isPrivateInst(TM, MI)) {
+ } else if (isPrivateInst(MI)) {
curRes.bits.ResourceID =
STM->device()->getResourceID(AMDILDevice::SCRATCH_ID);
mMFI->setUsesScratch();
- } else if (isLocalInst(TM, MI)
- || isLocalAtomic(TM, MI) || is64BitLocalAtomic(TM, MI)) {
+ } else if (isLocalInst(MI)
+ || isLocalAtomic(MI) || is64BitLocalAtomic(MI)) {
curRes.bits.ResourceID =
STM->device()->getResourceID(AMDILDevice::LDS_ID);
mMFI->setUsesLDS();
- if (isAtomicInst(TM, MI)) {
+ if (isAtomicInst(MI)) {
assert(curRes.bits.ResourceID && "Atomic resource ID "
"cannot be zero!");
MI->getOperand(MI->getNumOperands()-1)
.setImm(curRes.bits.ResourceID);
}
mMFI->setUsesLDS();
- } else if (isRegionInst(TM, MI)
- || isRegionAtomic(TM, MI) || is64BitRegionAtomic(TM, MI)) {
+ } else if (isRegionInst(MI)
+ || isRegionAtomic(MI) || is64BitRegionAtomic(MI)) {
curRes.bits.ResourceID =
STM->device()->getResourceID(AMDILDevice::GDS_ID);
mMFI->setUsesGDS();
- if (isAtomicInst(TM, MI)) {
+ if (isAtomicInst(MI)) {
assert(curRes.bits.ResourceID && "Atomic resource ID "
"cannot be zero!");
(MI)->getOperand((MI)->getNumOperands()-1)
.setImm(curRes.bits.ResourceID);
}
mMFI->setUsesGDS();
- } else if (isConstantInst(TM, MI)) {
+ } else if (isConstantInst(MI)) {
// If we are unknown constant instruction and the base pointer is known.
// Set the resource ID accordingly, otherwise use the default constant ID.
// FIXME: this should not require the base pointer to know what constant
@@ -366,29 +454,31 @@
curRes.bits.ResourceID = 2;
curRes.bits.HardwareInst = 1;
} else {
- if (isStoreInst(TM, MI)) {
+ if (isPtrStoreInst(MI)) {
if (DEBUGME) {
dbgs() << __LINE__ << ": Setting byte store bit on instruction: ";
MI->dump();
}
curRes.bits.ByteStore = 1;
}
- curRes.bits.ResourceID = STM->device()->getResourceID(AMDILDevice::CONSTANT_ID);
+ curRes.bits.ResourceID = STM->device()->getResourceID(
+ AMDILDevice::CONSTANT_ID);
}
mMFI->setUsesConstant();
} else {
- if (isStoreInst(TM, MI)) {
+ if (isPtrStoreInst(MI)) {
if (DEBUGME) {
dbgs() << __LINE__ << ": Setting byte store bit on instruction: ";
MI->dump();
}
curRes.bits.ByteStore = 1;
}
- curRes.bits.ResourceID = STM->device()->getResourceID(AMDILDevice::GLOBAL_ID);
+ curRes.bits.ResourceID = STM->device()->getResourceID(
+ AMDILDevice::GLOBAL_ID);
KM->setUAVID(NULL, curRes.bits.ResourceID);
mMFI->uav_insert(curRes.bits.ResourceID);
}
- } else if (isAppendInst(TM, MI)) {
+ } else if (isAppendInst(MI)) {
unsigned opcode = MI->getOpcode();
if (opcode == AMDIL::APPEND_ALLOC || opcode == AMDIL::APPEND64_ALLOC) {
curRes.bits.ResourceID = 1;
@@ -398,7 +488,24 @@
}
setAsmPrinterFlags(MI, curRes);
}
-
+// add local arrays that belong to the given function into "localPtrs" set
+void
+AMDILEGPointerManagerImpl::parseLocalArrays()
+{
+ const Function* func = MF.getFunction();
+ const AMDILKernel *krnl = mAMI->getKernel(func->getName());
+ const AMDILLocalArg* lvgv = krnl->lvgv;
+ if (lvgv == NULL) return;
+
+ llvm::SmallVector<AMDILArrayMem *, DEFAULT_VEC_SLOTS>::const_iterator it
+ = lvgv->local.begin();
+ llvm::SmallVector<AMDILArrayMem *, DEFAULT_VEC_SLOTS>::const_iterator end
+ = lvgv->local.end();
+ for (; it != end; ++it) {
+ const AMDILArrayMem* local = *it;
+ localPtrs.insert(local->base);
+ }
+}
// Function that parses the arguments and updates the lookupTable with the
// pointer -> register mapping. This function also checks for cacheable
// pointers and updates the CacheableSet with the arguments that
@@ -406,7 +513,7 @@
// purpose of this function is to update the images and counters
// with all pointers that are either images or atomic counters.
uint32_t
-AMDILPointerManagerImpl::parseArguments()
+AMDILEGPointerManagerImpl::parseArguments()
{
uint32_t writeOnlyImages = 0;
uint32_t readOnlyImages = 0;
@@ -489,17 +596,19 @@
// correctly encode the 'info' intrinsics.
lookupTable[mMFI->getArgReg(regNum)] =
std::make_pair
- ((cbNum << 16 | readOnlyImages++), createStrValPair(curArg));
- } else if (mAMI->isWriteOnlyImage(MF.getFunction()->getName(), imageNum)) {
+ ((cbNum << 16 | readOnlyImages++), createStrValPair(curArg));
+ } else if (mAMI->isWriteOnlyImage(MF.getFunction()->getName(),
+ imageNum)) {
if (DEBUGME) {
dbgs() << "Pointer: '" << curArg->getName()
- << "' is a write only image # " << writeOnlyImages << "!\n";
+ << "' is a write only image # " << writeOnlyImages <<
+ "!\n";
}
// We store the cbNum along with the image number so that we can
// correctly encode the 'info' intrinsics.
lookupTable[mMFI->getArgReg(regNum)] =
std::make_pair
- ((cbNum << 16 | writeOnlyImages++), createStrValPair(curArg));
+ ((cbNum << 16 | writeOnlyImages++), createStrValPair(curArg));
} else {
assert(!"Read/Write images are not supported!");
}
@@ -525,11 +634,11 @@
if (STM->device()->isSupported(AMDILDeviceInfo::CachedMem)
&& GV && GV->hasInitializer()) {
const ConstantArray *nameArray
- = dyn_cast_or_null<ConstantArray>(GV->getInitializer());
+ = dyn_cast_or_null<ConstantArray>(GV->getInitializer());
if (nameArray) {
for (unsigned x = 0, y = nameArray->getNumOperands(); x < y; ++x) {
const GlobalVariable *gV= dyn_cast_or_null<GlobalVariable>(
- nameArray->getOperand(x)->getOperand(0));
+ nameArray->getOperand(x)->getOperand(0));
const ConstantDataArray *argName =
dyn_cast_or_null<ConstantDataArray>(gV->getInitializer());
if (!argName) {
@@ -553,19 +662,19 @@
dbgs() << "Pointer: " << curArg->getName() << " is assigned ";
if (as == AMDILAS::GLOBAL_ADDRESS) {
dbgs() << "uav " << STM->device()
- ->getResourceID(AMDILDevice::GLOBAL_ID);
+ ->getResourceID(AMDILDevice::GLOBAL_ID);
} else if (as == AMDILAS::PRIVATE_ADDRESS) {
dbgs() << "scratch " << STM->device()
- ->getResourceID(AMDILDevice::SCRATCH_ID);
+ ->getResourceID(AMDILDevice::SCRATCH_ID);
} else if (as == AMDILAS::LOCAL_ADDRESS) {
dbgs() << "lds " << STM->device()
- ->getResourceID(AMDILDevice::LDS_ID);
+ ->getResourceID(AMDILDevice::LDS_ID);
} else if (as == AMDILAS::CONSTANT_ADDRESS) {
dbgs() << "cb " << STM->device()
- ->getResourceID(AMDILDevice::CONSTANT_ID);
+ ->getResourceID(AMDILDevice::CONSTANT_ID);
} else if (as == AMDILAS::REGION_ADDRESS) {
dbgs() << "gds " << STM->device()
- ->getResourceID(AMDILDevice::GDS_ID);
+ ->getResourceID(AMDILDevice::GDS_ID);
} else {
assert(!"Found an address space that we don't support!");
}
@@ -575,26 +684,38 @@
switch (as) {
default:
lookupTable[mMFI->getArgReg(regNum)] = std::make_pair
- (STM->device()->getResourceID(AMDILDevice::GLOBAL_ID), createStrValPair(curArg));
+ (STM->device()->getResourceID(
+ AMDILDevice::GLOBAL_ID),
+ createStrValPair(curArg));
break;
case AMDILAS::LOCAL_ADDRESS:
lookupTable[mMFI->getArgReg(regNum)] = std::make_pair
- (STM->device()->getResourceID(AMDILDevice::LDS_ID), createStrValPair(curArg));
+ (STM->device()->getResourceID(
+ AMDILDevice::LDS_ID),
+ createStrValPair(curArg));
mMFI->setHasLDSArg();
+ localPtrs.insert(curArg);
+ localPtrMap[mMFI->getArgReg(regNum)].insert(curArg);
break;
case AMDILAS::REGION_ADDRESS:
lookupTable[mMFI->getArgReg(regNum)] = std::make_pair
- (STM->device()->getResourceID(AMDILDevice::GDS_ID), createStrValPair(curArg));
+ (STM->device()->getResourceID(
+ AMDILDevice::GDS_ID),
+ createStrValPair(curArg));
mMFI->setHasGDSArg();
break;
case AMDILAS::CONSTANT_ADDRESS:
lookupTable[mMFI->getArgReg(regNum)] = std::make_pair
- (STM->device()->getResourceID(AMDILDevice::CONSTANT_ID), createStrValPair(curArg));
+ (STM->device()->getResourceID(
+ AMDILDevice::CONSTANT_ID),
+ createStrValPair(curArg));
mMFI->setHasConstantArg();
break;
case AMDILAS::PRIVATE_ADDRESS:
lookupTable[mMFI->getArgReg(regNum)] = std::make_pair
- (STM->device()->getResourceID(AMDILDevice::SCRATCH_ID), createStrValPair(curArg));
+ (STM->device()->getResourceID(
+ AMDILDevice::SCRATCH_ID),
+ createStrValPair(curArg));
mMFI->setHasScratchArg();
break;
}
@@ -605,20 +726,89 @@
// Is anything missing that is legal in CL?
assert(0 && "Current type is not supported!");
lookupTable[mMFI->getArgReg(regNum)] = std::make_pair
- (STM->device()->getResourceID(AMDILDevice::GLOBAL_ID), createStrValPair(curArg));
+ (STM->device()->getResourceID(
+ AMDILDevice::GLOBAL_ID),
+ createStrValPair(curArg));
++regNum;
++cbNum;
}
}
return writeOnlyImages;
}
+// Given a load, store or atomic instruction, if it's a local instruction,
+// and if its pointer oper derives from multiple local pointers, then
+// merge the sets that the conflicting local pointers belong to,
+// so that in the end local pointers that conflict with each other
+// are in the same set.
+void
+AMDILEGPointerManagerImpl::detectConflictLocalPtrs(MachineInstr *MI,
+ unsigned reg,
+ const AMDILSubtarget *STM)
+{
+ assert((isLoadInst(MI) || isStoreInst(MI) || isAtomicInst(MI))
+ && "unexpected instruction type");
+ assert(isLocalInst(MI)
+ && STM->device()->usesHardware(AMDILDeviceInfo::LocalMem)
+ && "not local");
+ Reg2ValSet::iterator it = localPtrMap.find(reg);
+ if (it != localPtrMap.end()) {
+ SmallValSet& locals = it->second;
+ assert(!locals.empty() && "sanity");
+
+ // see if one of the local pointers is a kernel argument
+ bool hasKernelArg = false;
+ for (SmallValSet::iterator it = locals.begin(), end = locals.end();
+ it != end; ++it) {
+ if (!isa<GlobalValue>(*it)) {
+ hasKernelArg = true;
+ break;
+ }
+ }
+ // if one of the local pointers is an argument, merge to the default
+ // local buffer set, otherwise merge to the set that the first local
+ // belongs to
+ unsigned dstSetId;
+ if (hasKernelArg) {
+ dstSetId = 0;
+ }
+ else {
+ dstSetId = localPtr2SetIdMap[*locals.begin()];
+ }
+ for (SmallValSet::iterator it = locals.begin(), end = locals.end();
+ it != end; ++it) {
+ const Value* local = *it;
+ unsigned curSetId = localPtr2SetIdMap[local];
+ if (curSetId == dstSetId) continue;
+
+ // point the local pointers in current set to dst set
+ for (SmallValSet::iterator it2 = localPtrSets[curSetId].begin(),
+ end2 = localPtrSets[curSetId].end();
+ it2 != end2; ++it2) {
+ localPtr2SetIdMap[*it2] = dstSetId;
+ }
+
+ // merge the set current local belongs to the set dst local belongs
+ localPtrSets[dstSetId].insert(localPtrSets[curSetId].begin(),
+ localPtrSets[curSetId].end());
+ localPtrSets[curSetId].clear();
+
+ // merge instructions current set accesses to dst set
+ localSetId2InstMap[dstSetId].insert(
+ localSetId2InstMap[dstSetId].end(),
+ localSetId2InstMap[curSetId].begin(),
+ localSetId2InstMap[curSetId].end());
+ }
+ // add MI to list of instructions dst set accesses
+ localSetId2InstMap[dstSetId].push_back(MI);
+ }
+}
// The call stack is interesting in that even in SSA form, it assigns
// registers to the same value's over and over again. So we need to
// ignore the values that are assigned and just deal with the input
// and return registers.
void
-AMDILPointerManagerImpl::parseCall(
+AMDILEGPointerManagerImpl::parseCall(
MachineBasicBlock::iterator &mBegin,
MachineBasicBlock::iterator mEnd)
{
@@ -630,35 +820,49 @@
MachineBasicBlock::iterator callInst = mBegin;
MachineInstr *CallMI = callInst;
getAsmPrinterFlags(CallMI, curRes);
- MachineInstr *MI = --mBegin;
+ MachineInstr *MI = NULL;
unsigned reg = AMDIL::R1;
- // First we need to check the input registers.
- do {
- // We stop if we hit the beginning of the call stack
- // adjustment.
- if (MI->getOpcode() == AMDIL::ADJCALLSTACKDOWN
- || MI->getOpcode() == AMDIL::ADJCALLSTACKUP
- || MI->getNumOperands() != 2
- || !MI->getOperand(0).isReg()) {
- break;
- }
- reg = MI->getOperand(0).getReg();
- if (MI->getOperand(1).isReg()) {
- unsigned reg1 = MI->getOperand(1).getReg();
- inputRegs.push_back(reg1);
- if (lookupTable[reg1].second.second) {
- curRes.bits.PointerPath = 1;
- }
- }
- lookupTable.erase(reg);
- if ((signed)reg < 0
- || mBegin == CallMI->getParent()->begin()) {
- break;
- }
+ if (CallMI->getParent()->begin() != mBegin) {
MI = --mBegin;
- } while (1);
+ // First we need to check the input registers.
+ do {
+ // We stop if we hit the beginning of the call stack
+ // adjustment.
+ if (MI->getOpcode() == AMDIL::ADJCALLSTACKDOWN
+ || MI->getOpcode() == AMDIL::ADJCALLSTACKUP
+ || MI->getNumOperands() != 2
+ || !MI->getOperand(0).isReg()) {
+ break;
+ }
+ reg = MI->getOperand(0).getReg();
+ if (MI->getOperand(1).isReg()) {
+ unsigned reg1 = MI->getOperand(1).getReg();
+ inputRegs.push_back(reg1);
+ if (lookupTable[reg1].second.second) {
+ curRes.bits.PointerPath = 1;
+ }
+ }
+ lookupTable.erase(reg);
+ if ((signed)reg < 0
+ || mBegin == CallMI->getParent()->begin()) {
+ break;
+ }
+ MI = --mBegin;
+ } while (1);
+ }
mBegin = callInst;
MI = ++mBegin;
+ // If we hit the end, then lets move back one and return.
+ // This occurs when a function call with no return is the
+ // last instruction in a basic block.
+ if (mBegin == mEnd) {
+ setAsmPrinterFlags(CallMI, curRes);
+ --mBegin;
+ if (DEBUGME) {
+ dbgs() << "Parsing Call Stack End.\n";
+ }
+ return;
+ }
// If the next registers operand 1 is not a register or that register
// is not R1, then we don't have any return values.
if (MI->getNumOperands() == 2
@@ -693,7 +897,7 @@
// Detect if the current instruction conflicts with another instruction
// and add the instruction to the correct location accordingly.
void
-AMDILPointerManagerImpl::detectConflictInst(
+AMDILEGPointerManagerImpl::detectConflictInst(
MachineInstr *MI,
AMDILAS::InstrResEnc &curRes,
bool isLoadStore,
@@ -718,23 +922,13 @@
assert(dyn_cast<PointerType>(lookupTable[reg].second.second->getType())
&& "Must be a pointer type for an instruction!");
switch (dyn_cast<PointerType>(
- lookupTable[reg].second.second->getType())->getAddressSpace()) {
- case AMDILAS::GLOBAL_ADDRESS:
- dbgs() << " UAV: ";
- break;
- case AMDILAS::LOCAL_ADDRESS:
- dbgs() << " LDS: ";
- break;
- case AMDILAS::REGION_ADDRESS:
- dbgs() << " GDS: ";
- break;
- case AMDILAS::PRIVATE_ADDRESS:
- dbgs() << " SCRATCH: ";
- break;
- case AMDILAS::CONSTANT_ADDRESS:
- dbgs() << " CB: ";
- break;
-
+ lookupTable[reg].second.second->getType())->getAddressSpace())
+ {
+ case AMDILAS::GLOBAL_ADDRESS: dbgs() << " UAV: "; break;
+ case AMDILAS::LOCAL_ADDRESS: dbgs() << " LDS: "; break;
+ case AMDILAS::REGION_ADDRESS: dbgs() << " GDS: "; break;
+ case AMDILAS::PRIVATE_ADDRESS: dbgs() << " SCRATCH: "; break;
+ case AMDILAS::CONSTANT_ADDRESS: dbgs() << " CB: "; break;
}
dbgs() << lookupTable[reg].first << " Reg: " << reg
<< " assigned to reg " << dstReg << ". Inst: ";
@@ -757,23 +951,13 @@
assert(dyn_cast<PointerType>(lookupTable[reg].second.second->getType())
&& "Must be a pointer type for a conflict instruction!");
switch (dyn_cast<PointerType>(
- lookupTable[reg].second.second->getType())->getAddressSpace()) {
- case AMDILAS::GLOBAL_ADDRESS:
- dbgs() << " UAV: ";
- break;
- case AMDILAS::LOCAL_ADDRESS:
- dbgs() << " LDS: ";
- break;
- case AMDILAS::REGION_ADDRESS:
- dbgs() << " GDS: ";
- break;
- case AMDILAS::PRIVATE_ADDRESS:
- dbgs() << " SCRATCH: ";
- break;
- case AMDILAS::CONSTANT_ADDRESS:
- dbgs() << " CB: ";
- break;
-
+ lookupTable[reg].second.second->getType())->getAddressSpace())
+ {
+ case AMDILAS::GLOBAL_ADDRESS: dbgs() << " UAV: "; break;
+ case AMDILAS::LOCAL_ADDRESS: dbgs() << " LDS: "; break;
+ case AMDILAS::REGION_ADDRESS: dbgs() << " GDS: "; break;
+ case AMDILAS::PRIVATE_ADDRESS: dbgs() << " SCRATCH: "; break;
+ case AMDILAS::CONSTANT_ADDRESS: dbgs() << " CB: "; break;
}
dbgs() << lookupTable[reg].first << " Reg: " << reg;
if (InstToPtrMap[MI].size() > 1) {
@@ -802,12 +986,11 @@
}
setAsmPrinterFlags(MI, curRes);
}
-
// In this case we want to handle a load instruction.
void
-AMDILPointerManagerImpl::parseLoadInst(TargetMachine &TM, MachineInstr *MI)
+AMDILEGPointerManagerImpl::parseLoadInst(MachineInstr *MI)
{
- assert(isLoadInst(TM, MI) && "Only a load instruction can be parsed by "
+ assert(isPtrLoadInst(MI) && "Only a load instruction can be parsed by "
"the parseLoadInst function.");
AMDILAS::InstrResEnc curRes;
getAsmPrinterFlags(MI, curRes);
@@ -836,12 +1019,20 @@
}
cpool.insert(MI);
}
- // If we are a hardware local, then we don't need to track as there
- // is only one resource ID that we need to know about, so we
+
+ // if this is a local inst, detect if we find conflicting local ptrs
+ if (isLocalInst(MI)
+ && STM->device()->usesHardware(AMDILDeviceInfo::LocalMem)
+ && MI->getOperand(1).isReg()) {
+ detectConflictLocalPtrs(MI, idx, STM);
+ return;
+ }
+
+ // If we are a hardware region or private, then we don't need to track
+ // as there is only one resource ID that we need to know about, so we
// map it using allocateDefaultID, which maps it to the default.
- // This is also the case for REGION_ADDRESS and PRIVATE_ADDRESS.
- if (isLRPInst(TM, MI, ATM) || !basePtr) {
- allocateDefaultID(TM, curRes, MI, true);
+ if (isLRPInst(MI, STM) || !basePtr) {
+ allocateDefaultID(curRes, MI, true);
return;
}
// We have a load instruction so we map this instruction
@@ -850,40 +1041,41 @@
InstToPtrMap[MI].insert(createStrValPair(basePtr));
PtrToInstMap[basePtr].push_back(MI);
- if (isGlobalInst(TM, MI)) {
+ if (isGlobalInst(MI)) {
// Add to the cacheable set for the block. If there was a store earlier
// in the block, this call won't actually add it to the cacheable set.
bbCacheable[MI->getParent()].addPossiblyCacheableInst(MI);
}
if (DEBUGME) {
- dbgs() << "Assigning instruction to pointer ";
+ dbgs() << "Assigning instruction to load pointer ";
dbgs() << basePtr->getName() << ". Inst: ";
MI->dump();
}
detectConflictInst(MI, curRes, true, idx, dstReg);
}
-
// In this case we want to handle a store instruction.
void
-AMDILPointerManagerImpl::parseStoreInst(TargetMachine &TM, MachineInstr *MI)
+AMDILEGPointerManagerImpl::parseStoreInst(MachineInstr *MI)
{
- assert(isStoreInst(TM, MI) && "Only a store instruction can be parsed by "
+ assert(isPtrStoreInst(MI) && "Only a store instruction can be parsed by "
"the parseStoreInst function.");
AMDILAS::InstrResEnc curRes;
getAsmPrinterFlags(MI, curRes);
- unsigned dstReg;
+ unsigned dstReg = ~0U;
if (MI->getOperand(0).isFI()) {
dstReg = MI->getOperand(0).getIndex();
- } else {
+ } else if (MI->getOperand(0).isReg()) {
dstReg = MI->getOperand(0).getReg();
+ } else {
}
// If the data part of the store instruction is known to
// be a pointer, then we need to mark this pointer as being
// a byte pointer. This is the conservative case that needs
// to be handled correctly.
- if (lookupTable[dstReg].second.second && lookupTable[dstReg].first != ~0U) {
+ if (dstReg != ~0U && lookupTable[dstReg].second.second &&
+ lookupTable[dstReg].first != ~0U) {
curRes.bits.ConflictPtr = 1;
if (DEBUGME) {
dbgs() << "Found a case where the pointer is being stored!\n";
@@ -899,7 +1091,7 @@
// Before we go through the special cases, for the cacheable information
// all we care is if the store if global or not.
- if (!isLRPInst(TM, MI, ATM)) {
+ if (!isLRPInst(MI, STM)) {
bbCacheable[MI->getParent()].setReachesExit();
}
@@ -943,23 +1135,33 @@
FIToPtrMap[MI->getOperand(1).getIndex()] = tmp;
}
- allocateDefaultID(TM, curRes, MI, true);
+ allocateDefaultID(curRes, MI, true);
return;
}
+
unsigned reg = MI->getOperand(1).getReg();
+
+ // if this is a local inst, detect if we find conflicting local ptrs
+ if (isLocalInst(MI)
+ && STM->device()->usesHardware(AMDILDeviceInfo::LocalMem)) {
+ detectConflictLocalPtrs(MI, reg, STM);
+ return;
+ }
+
// If we don't know what value the register
// is assigned to, then we need to special case
// this instruction.
if (!lookupTable[reg].second.second) {
- allocateDefaultID(TM, curRes, MI, true);
+ allocateDefaultID(curRes, MI, true);
return;
}
- // If we are a hardware local, then we don't need to track as there
- // is only one resource ID that we need to know about, so we
+
+ // If we are a hardware region or private, then we don't need to track
+ // as there is only one resource ID that we need to know about, so we
// map it using allocateDefaultID, which maps it to the default.
// This is also the case for REGION_ADDRESS and PRIVATE_ADDRESS.
- if (isLRPInst(TM, MI, ATM)) {
- allocateDefaultID(TM, curRes, MI, true);
+ if (isLRPInst(MI, STM)) {
+ allocateDefaultID(curRes, MI, true);
return;
}
@@ -983,7 +1185,7 @@
curRes.bits.ByteStore = 1;
setAsmPrinterFlags(MI, curRes);
const PointerType *PT = dyn_cast<PointerType>(
- lookupTable[reg].second.second->getType());
+ lookupTable[reg].second.second->getType());
if (PT) {
bytePtrs.insert(lookupTable[reg].second);
}
@@ -994,61 +1196,57 @@
// size of the pointer that we are truncating to, and if we
// are less than 32 bits, we need to mark the pointer as a
// byte store pointer.
- switch (MI->getOpcode()) {
- case AMDIL::GLOBALTRUNCSTORE_i16i8:
- case AMDIL::GLOBALTRUNCSTORE_v2i16i8:
- case AMDIL::GLOBALTRUNCSTORE_i32i8:
- case AMDIL::GLOBALTRUNCSTORE_v2i32i8:
- case AMDIL::GLOBALTRUNCSTORE_i64i8:
- case AMDIL::GLOBALTRUNCSTORE_v2i64i8:
- case AMDIL::GLOBALTRUNCSTORE_i32i16:
- case AMDIL::GLOBALTRUNCSTORE_i64i16:
- case AMDIL::GLOBALSTORE_i8:
- case AMDIL::GLOBALSTORE_i16:
+ if (isGlobalInst(MI) && isStoreInst(MI) && isSub32BitIOInst(MI)) {
curRes.bits.ByteStore = 1;
setAsmPrinterFlags(MI, curRes);
bytePtrs.insert(lookupTable[reg].second);
- break;
- default:
- break;
}
if (DEBUGME) {
- dbgs() << "Assigning instruction to pointer ";
+ dbgs() << "Assigning instruction to store pointer ";
dbgs() << lookupTable[reg].second.second->getName() << ". Inst: ";
MI->dump();
}
- detectConflictInst(MI, curRes, true, reg, dstReg);
+ if (dstReg != ~0U) {
+ detectConflictInst(MI, curRes, true, reg, dstReg);
+ }
}
-
// In this case we want to handle an atomic instruction.
void
-AMDILPointerManagerImpl::parseAtomicInst(TargetMachine &TM, MachineInstr *MI)
+AMDILEGPointerManagerImpl::parseAtomicInst(MachineInstr *MI)
{
- assert(isAtomicInst(TM, MI) && "Only an atomic instruction can be parsed by "
+ assert(isAtomicInst(MI) && "Only an atomic instruction can be parsed by "
"the parseAtomicInst function.");
AMDILAS::InstrResEnc curRes;
unsigned dstReg = MI->getOperand(0).getReg();
unsigned reg = 0;
getAsmPrinterFlags(MI, curRes);
- unsigned numOps = MI->getNumOperands();
+ int numOps = MI->getNumOperands() - 1;
bool found = false;
- while (--numOps) {
+ while (--numOps >= 0) {
MachineOperand &Op = MI->getOperand(numOps);
if (!Op.isReg()) {
continue;
}
reg = Op.getReg();
+
+ if (isLocalInst(MI)
+ && STM->device()->usesHardware(AMDILDeviceInfo::LocalMem)) {
+ detectConflictLocalPtrs(MI, reg, STM);
+ continue;
+ }
+
// If the register is not known to be owned by a pointer
// then we can ignore it
if (!lookupTable[reg].second.second) {
continue;
}
- // if the pointer is known to be local, region or private, then we
+
+ // if the pointer is known to be region or private, then we
// can ignore it. Although there are no private atomics, we still
// do this check so we don't have to write a new function to check
- // for only local and region.
- if (isLRPInst(TM, MI, ATM)) {
+ // for only region.
+ if (isLRPInst(MI, STM)) {
continue;
}
found = true;
@@ -1059,35 +1257,32 @@
// This is a store so must update the cacheable information.
bbCacheable[MI->getParent()].setReachesExit();
- // Only do if have SC with arena atomic bug fix (EPR 326883).
- if (STM->calVersion() >= CAL_VERSION_SC_150) {
- // Force pointers that are used by atomics to be in the arena.
- // If they were allowed to be accessed as RAW they would cause
- // all access to use the slow complete path.
- if (DEBUGME) {
- dbgs() << __LINE__ << ": Setting byte store bit on atomic instruction: ";
- MI->dump();
- }
- curRes.bits.ByteStore = 1;
- bytePtrs.insert(lookupTable[reg].second);
+ // Force pointers that are used by atomics to be in the arena.
+ // If they were allowed to be accessed as RAW they would cause
+ // all access to use the slow complete path.
+ if (DEBUGME) {
+ dbgs() << __LINE__ << ": Setting byte store bit on atomic instruction: ";
+ MI->dump();
}
+ curRes.bits.ByteStore = 1;
+ bytePtrs.insert(lookupTable[reg].second);
if (DEBUGME) {
- dbgs() << "Assigning instruction to pointer ";
+ dbgs() << "Assigning instruction to atomic ";
dbgs() << lookupTable[reg].second.second->getName()<< ". Inst: ";
MI->dump();
}
detectConflictInst(MI, curRes, true, reg, dstReg);
}
if (!found) {
- allocateDefaultID(TM, curRes, MI, true);
+ allocateDefaultID(curRes, MI, true);
}
}
// In this case we want to handle a counter instruction.
void
-AMDILPointerManagerImpl::parseAppendInst(TargetMachine &TM, MachineInstr *MI)
+AMDILEGPointerManagerImpl::parseAppendInst(MachineInstr *MI)
{
- assert(isAppendInst(TM, MI) && "Only an atomic counter instruction can be "
+ assert(isAppendInst(MI) && "Only an atomic counter instruction can be "
"parsed by the parseAppendInst function.");
AMDILAS::InstrResEnc curRes;
unsigned dstReg = MI->getOperand(0).getReg();
@@ -1096,13 +1291,13 @@
// If the register is not known to be owned by a pointer
// then we set it to the default
if (!lookupTable[reg].second.second) {
- allocateDefaultID(TM, curRes, MI, true);
+ allocateDefaultID(curRes, MI, true);
return;
}
InstToPtrMap[MI].insert(lookupTable[reg].second);
PtrToInstMap[lookupTable[reg].second.second].push_back(MI);
if (DEBUGME) {
- dbgs() << "Assigning instruction to pointer ";
+ dbgs() << "Assigning instruction to append ";
dbgs() << lookupTable[reg].second.second->getName() << ". Inst: ";
MI->dump();
}
@@ -1110,9 +1305,9 @@
}
/// In this case we want to handle a counter instruction.
void
-AMDILPointerManagerImpl::parseSemaInst(TargetMachine &TM, MachineInstr *MI)
+AMDILEGPointerManagerImpl::parseSemaInst(MachineInstr *MI)
{
- assert(isSemaphoreInst(TM, MI) && "Only an semaphore instruction can be "
+ assert(isSemaphoreInst(MI) && "Only an semaphore instruction can be "
"parsed by the parseSemaInst function.");
AMDILAS::InstrResEnc curRes;
unsigned dstReg = MI->getOperand(0).getReg();
@@ -1120,20 +1315,20 @@
InstToPtrMap[MI].insert(lookupTable[dstReg].second);
PtrToInstMap[lookupTable[dstReg].second.second].push_back(MI);
if (DEBUGME) {
- dbgs() << "Assigning instruction to pointer ";
+ dbgs() << "Assigning instruction to semaphore ";
dbgs() << lookupTable[dstReg].second.second->getName() << ". Inst: ";
MI->dump();
}
}
// In this case we want to handle an Image instruction.
void
-AMDILPointerManagerImpl::parseImageInst(TargetMachine &TM, MachineInstr *MI)
+AMDILEGPointerManagerImpl::parseImageInst(MachineInstr *MI)
{
- assert(isImageInst(TM, MI) && "Only an image instruction can be "
+ assert(isImageInst(MI) && "Only an image instruction can be "
"parsed by the parseImageInst function.");
AMDILAS::InstrResEnc curRes;
getAsmPrinterFlags(MI, curRes);
- if (isWriteImageInst(TM, MI)) {
+ if (isWriteImageInst(MI)) {
unsigned dstReg = MI->getOperand(0).getReg();
curRes.bits.ResourceID = lookupTable[dstReg].first & 0xFFFF;
curRes.bits.isImage = 1;
@@ -1151,7 +1346,7 @@
// then we set it to the default
if (!lookupTable[reg].second.second) {
assert(!"This should not happen for images!");
- allocateDefaultID(TM, curRes, MI, true);
+ allocateDefaultID(curRes, MI, true);
return;
}
InstToPtrMap[MI].insert(lookupTable[reg].second);
@@ -1161,9 +1356,9 @@
dbgs() << lookupTable[reg].second.second->getName() << ". Inst: ";
MI->dump();
}
- if (isImageTXLDInst(TM, MI)) {
+ if (isImageTXLDInst(MI)) {
curRes.bits.ResourceID = lookupTable[reg].first & 0xFFFF;
- } else if (isReadImageInst(TM, MI)) {
+ } else if (isReadImageInst(MI)) {
curRes.bits.ResourceID = lookupTable[reg].first & 0xFFFF;
if (MI->getOperand(SAMPLER_INDEX).isReg()) {
// Our sampler is not a literal value.
@@ -1176,7 +1371,7 @@
}
uint32_t val = ~0U;
if (sampler_name.empty()) {
- sampler_name = findSamplerName(TM, MI, val);
+ sampler_name = findSamplerName(MI, val);
}
val = mMFI->addSampler(sampler_name, val);
if (DEBUGME) {
@@ -1192,7 +1387,8 @@
memset(buffer, 0, sizeof(buffer));
::sprintf(buffer,"_%d", (int32_t)MI->getOperand(SAMPLER_INDEX).getImm());
std::string sampler_name = std::string("unknown") + std::string(buffer);
- uint32_t val = mMFI->addSampler(sampler_name, MI->getOperand(SAMPLER_INDEX).getImm());
+ uint32_t val =
+ mMFI->addSampler(sampler_name, MI->getOperand(SAMPLER_INDEX).getImm());
if (DEBUGME) {
dbgs() << "Mapping internal sampler " << sampler_name
<< " to sampler number " << val << " for Inst:\n";
@@ -1200,22 +1396,40 @@
}
MI->getOperand(SAMPLER_INDEX).setImm(val);
}
- } else if (isImageInfo0Inst(TM, MI)) {
+ } else if (isImageInfo0Inst(MI)) {
curRes.bits.ResourceID = lookupTable[reg].first >> 16;
- } else if (isImageInfo1Inst(TM, MI)) {
+ } else if (isImageInfo1Inst(MI)) {
curRes.bits.ResourceID = (lookupTable[reg].first >> 16) + 1;
}
curRes.bits.isImage = 1;
}
setAsmPrinterFlags(MI, curRes);
}
-
+// if addri's address is a local array, map addri's dest reg to the local arra y
+void
+AMDILEGPointerManagerImpl::parseAddriInst(MachineInstr *MI)
+{
+ assert(isAddriInst(MI) && "Only a Addri instruction can be parsed by "
+ "the parseAddriInst function.");
+ unsigned dstReg = MI->getOperand(0).getReg();
+ MachineOperand &MemOp = MI->getOperand(1);
+ if (!MemOp.isGlobal()) return;
+ const GlobalValue* GV = MemOp.getGlobal();
+ if (!localPtrs.count(GV)) return;
+ if (DEBUGME) {
+ dbgs() << "Pointer: " << GV->getName();
+ dbgs() << "Reg: " << dstReg << " map to " << GV->getName() << "\n";
+ }
+ localPtrMap[dstReg].insert(GV);
+ localNAddriVec.push_back(GVInstPair(GV, MI));
+ mMFI->setUsesLDS();
+}
// This case handles the rest of the instructions
void
-AMDILPointerManagerImpl::parseInstruction(TargetMachine &TM, MachineInstr *MI)
+AMDILEGPointerManagerImpl::parseInstruction(MachineInstr *MI)
{
- assert(!isAtomicInst(TM, MI) && !isStoreInst(TM, MI) && !isLoadInst(TM, MI) &&
- !isAppendInst(TM, MI) && !isImageInst(TM, MI) &&
+ assert(!isAtomicInst(MI) && !isPtrStoreInst(MI) && !isPtrLoadInst(MI) &&
+ !isAppendInst(MI) && !isImageInst(MI) &&
"Atomic/Load/Store/Append/Image insts should not be handled here!");
unsigned numOps = MI->getNumOperands();
// If we don't have any operands, we can skip this instruction
@@ -1228,19 +1442,19 @@
if (!MI->getOperand(0).isReg()) {
return;
}
- // If we are a LOADCONST_i32, we might be a sampler, so we need
+ // If we are a LOADCONSTi32, we might be a sampler, so we need
// to propogate the LOADCONST to IMAGE[1|2|3]D[A|B][64]_READ instructions.
- if (MI->getOpcode() == AMDIL::LOADCONST_i32) {
+ if (MI->getOpcode() == AMDIL::LOADCONSTi32) {
uint32_t val = MI->getOperand(1).getImm();
for(MachineRegisterInfo::reg_iterator
RI = MF.getRegInfo().reg_begin(MI->getOperand(0).getReg()),
RE = MF.getRegInfo().reg_end();
RI != RE; ++RI) {
- if (isReadImageInst(TM, RI.getOperand().getParent())) {
+ if (isReadImageInst(RI.getOperand().getParent())) {
if (DEBUGME) {
dbgs() << "Found a constant sampler for image read inst: ";
- RI.getOperand().print(dbgs());
+ RI.getOperand().getParent()->print(dbgs());
}
RI.getOperand().ChangeToImmediate(val);
}
@@ -1261,48 +1475,53 @@
continue;
}
reg = Op.getReg();
+ // propagate local ptr set from oper to dst
+ Reg2ValSet::iterator it = localPtrMap.find(reg);
+ if (it != localPtrMap.end()) {
+ SmallValSet& locals = it->second;
+ localPtrMap[dstReg].insert(locals.begin(), locals.end());
+ }
// If the register is not known to be owned by a pointer
// then we can ignore it
if (!lookupTable[reg].second.second) {
continue;
}
detectConflictInst(MI, curRes, false, reg, dstReg);
-
}
}
-
// This function parses the basic block and based on the instruction type,
// calls the function to finish parsing the instruction.
void
-AMDILPointerManagerImpl::parseBasicBlock(TargetMachine &TM, MachineBasicBlock *MB)
+AMDILEGPointerManagerImpl::parseBasicBlock(MachineBasicBlock *MB)
{
for (MachineBasicBlock::iterator mbb = MB->begin(), mbe = MB->end();
mbb != mbe; ++mbb) {
MachineInstr *MI = mbb;
if (MI->getOpcode() == AMDIL::CALL) {
parseCall(mbb, mbe);
- } else if (isLoadInst(TM, MI)) {
- parseLoadInst(TM, MI);
- } else if (isStoreInst(TM, MI)) {
- parseStoreInst(TM, MI);
- } else if (isAtomicInst(TM, MI)) {
- parseAtomicInst(TM, MI);
- } else if (isAppendInst(TM, MI)) {
- parseAppendInst(TM, MI);
- } else if (isSemaphoreInst(TM, MI)) {
- parseSemaInst(TM, MI);
- } else if (isImageInst(TM, MI)) {
- parseImageInst(TM, MI);
+ } else if (isPtrLoadInst(MI)) {
+ parseLoadInst(MI);
+ } else if (isPtrStoreInst(MI)) {
+ parseStoreInst(MI);
+ } else if (isAtomicInst(MI)) {
+ parseAtomicInst(MI);
+ } else if (isAppendInst(MI)) {
+ parseAppendInst(MI);
+ } else if (isSemaphoreInst(MI)) {
+ parseSemaInst(MI);
+ } else if (isImageInst(MI)) {
+ parseImageInst(MI);
+ } else if (isAddriInst(MI)) {
+ parseAddriInst(MI);
} else {
- parseInstruction(TM, MI);
+ parseInstruction(MI);
}
}
}
-
// Follows the Reverse Post Order Traversal of the basic blocks to
// determine which order to parse basic blocks in.
void
-AMDILPointerManagerImpl::parseFunction(TargetMachine &TM)
+AMDILEGPointerManagerImpl::parseFunction()
{
std::list<MachineBasicBlock*> prop_worklist;
@@ -1328,7 +1547,7 @@
dbgs() << "[BlockOrdering] Parsing CurrentBlock: "
<< MB->getNumber() << "\n";
}
- parseBasicBlock(TM, MB);
+ parseBasicBlock(MB);
if (bci.storeReachesExit())
prop_worklist.push_back(MB);
@@ -1339,7 +1558,8 @@
for (CacheableInstrSet::const_iterator cibit = bci.cacheableBegin(),
cibitend = bci.cacheableEnd();
cibit != cibitend;
- cibit++) {
+ cibit++)
+ {
(*cibit)->dump();
}
}
@@ -1355,7 +1575,8 @@
for (MachineBasicBlock::succ_iterator mbbit = wlb->succ_begin(),
mbbitend = wlb->succ_end();
mbbit != mbbitend;
- mbbit++) {
+ mbbit++)
+ {
BlockCacheableInfo &blockCache = bbCacheable[*mbbit];
if (!blockCache.storeReachesTop()) {
blockCache.setReachesTop();
@@ -1370,11 +1591,10 @@
}
}
}
-
// Helper function that dumps to dbgs() information about
// a pointer set.
void
-AMDILPointerManagerImpl::dumpPointers(AppendSet &Ptrs, const char *str)
+AMDILEGPointerManagerImpl::dumpPointers(AppendSet &Ptrs, const char *str)
{
if (Ptrs.empty()) {
return;
@@ -1389,7 +1609,7 @@
// Helper function that dumps to dbgs() information about
// a pointer set.
void
-AMDILPointerManagerImpl::dumpPointers(PtrSet &Ptrs, const char *str)
+AMDILEGPointerManagerImpl::dumpPointers(PtrSet &Ptrs, const char *str)
{
if (Ptrs.empty()) {
return;
@@ -1405,7 +1625,7 @@
// the pointers that are detected to the conflict set, otherwise
// they are added to the raw or byte set based on their usage.
void
-AMDILPointerManagerImpl::detectConflictingPointers(TargetMachine &TM)
+AMDILEGPointerManagerImpl::detectConflictingPointers()
{
if (InstToPtrMap.empty()) {
return;
@@ -1423,9 +1643,8 @@
// already detected as byte-inst
continue;
}
- if (isLRPInst(TM, MI, ATM)) {
- // We don't need to deal with pointers to local/region/private
- // memory regions
+ if (isLRPInst(MI, STM)) {
+ // We don't need to deal with pointers to local/region/private memory regions
continue;
}
AMDILAS::InstrResEnc curRes;
@@ -1501,7 +1720,7 @@
cfIter->second->dump();
}
// bool aliased = false;
- if (isLRPInst(TM, mapIter->first, ATM)) {
+ if (isLRPInst(mapIter->first, STM)) {
// We don't need to deal with pointers to local/region/private
// memory regions
continue;
@@ -1558,7 +1777,7 @@
}
// Function that detects aliased constant pool operations.
void
-AMDILPointerManagerImpl::detectAliasedCPoolOps()
+AMDILEGPointerManagerImpl::detectAliasedCPoolOps()
{
if (DEBUGME && !cpool.empty()) {
dbgs() << "Instructions w/ CPool Ops: \n";
@@ -1583,7 +1802,7 @@
if (visited.count(cur)) {
continue;
}
- if (isLoadInst(TM, cur) && isPrivateInst(TM, cur)) {
+ if (isPtrLoadInst(cur) && isPrivateInst(cur)) {
// If we are a private load and the register is
// used in the address register, we need to
// switch from private to constant pool load.
@@ -1595,18 +1814,20 @@
}
AMDILAS::InstrResEnc curRes;
getAsmPrinterFlags(cur, curRes);
- curRes.bits.ResourceID = STM->device()->getResourceID(AMDILDevice::GLOBAL_ID);
+ curRes.bits.ResourceID = STM->device()->getResourceID(
+ AMDILDevice::GLOBAL_ID);
curRes.bits.ConflictPtr = 1;
setAsmPrinterFlags(cur, curRes);
cur->setDesc(TM.getInstrInfo()->get(
- (cur->getOpcode() - AMDIL::PRIVATEAEXTLOAD_f32)
- + AMDIL::CPOOLAEXTLOAD_f32));
+ (cur->getOpcode() - AMDIL::PRIVATEAEXTLOAD64f32r)
+ + AMDIL::CPOOLAEXTLOAD64f32r));
} else {
if (cur->getOperand(0).isReg()) {
for(MachineRegisterInfo::reg_iterator
RI = MF.getRegInfo().reg_begin(cur->getOperand(0).getReg()),
RE = MF.getRegInfo().reg_end();
- RI != RE && RI.getOperand().isDef() && RI.getOperand().isReg(); ++RI) {
+ RI != RE && RI.getOperand().isDef() && RI.getOperand().isReg();
+ ++RI) {
queue.push(RI.getOperand().getParent());
}
}
@@ -1618,7 +1839,7 @@
// Function that detects fully cacheable pointers. Fully cacheable pointers
// are pointers that have no writes to them and no-alias is specified.
void
-AMDILPointerManagerImpl::detectFullyCacheablePointers(TargetMachine &TM)
+AMDILEGPointerManagerImpl::detectFullyCacheablePointers()
{
if (PtrToInstMap.empty()) {
return;
@@ -1645,11 +1866,11 @@
for (std::vector<MachineInstr*>::iterator
miBegin = mapIter->second.begin(),
miEnd = mapIter->second.end(); miBegin != miEnd; ++miBegin) {
- if (isStoreInst(TM, *miBegin) ||
- isImageInst(TM, *miBegin) ||
- isAtomicInst(TM, *miBegin) ||
- isAppendInst(TM, *miBegin) ||
- isSemaphoreInst(TM, *miBegin)) {
+ if (isPtrStoreInst(*miBegin) ||
+ isImageInst(*miBegin) ||
+ isAtomicInst(*miBegin) ||
+ isAppendInst(*miBegin) ||
+ isSemaphoreInst(*miBegin)) {
cacheable = false;
break;
}
@@ -1678,10 +1899,9 @@
}
}
}
-
// Are any of the pointers in PtrSet also in the BytePtrs or the CachePtrs?
bool
-AMDILPointerManagerImpl::ptrSetIntersectsByteOrCache(PtrSet &cacheSet)
+AMDILEGPointerManagerImpl::ptrSetIntersectsByteOrCache(PtrSet &cacheSet)
{
for (PtrSet::const_iterator psit = cacheSet.begin(),
psitend = cacheSet.end();
@@ -1694,14 +1914,13 @@
}
return false;
}
-
// Function that detects which instructions are cacheable even if
// all instructions of the pointer are not cacheable. The resulting
// set of instructions will not contain Ptrs that are in the cacheable
// ptr set (under the assumption they will get marked cacheable already)
// or pointers in the byte set, since they are not cacheable.
void
-AMDILPointerManagerImpl::detectCacheableInstrs()
+AMDILEGPointerManagerImpl::detectCacheableInstrs()
{
for (MBBCacheableMap::const_iterator mbbcit = bbCacheable.begin(),
@@ -1709,9 +1928,9 @@
mbbcit != mbbcitend;
mbbcit++) {
for (CacheableInstrSet::const_iterator bciit
- = mbbcit->second.cacheableBegin(),
+ = mbbcit->second.cacheableBegin(),
bciitend
- = mbbcit->second.cacheableEnd();
+ = mbbcit->second.cacheableEnd();
bciit != bciitend;
bciit++) {
if (!ptrSetIntersectsByteOrCache(InstToPtrMap[*bciit])) {
@@ -1729,7 +1948,7 @@
// condition means that UAV 11 is available for cacheable
// reads.
void
-AMDILPointerManagerImpl::annotateCacheablePtrs()
+AMDILEGPointerManagerImpl::annotateCacheablePtrs()
{
PtrSet::iterator siBegin, siEnd;
std::vector<MachineInstr*>::iterator miBegin, miEnd;
@@ -1766,11 +1985,10 @@
static unsigned switchAtomicToArena(unsigned op)
{
#define ATOM_CASE(OP) \
- case AMDIL::ATOM_G_##OP: return AMDIL::ATOM_A_##OP; \
- case AMDIL::ATOM_G_##OP##_NORET: return AMDIL::ATOM_A_##OP##_NORET;
+case AMDIL::ATOM_G_ ## OP: return AMDIL::ATOM_A_ ## OP; \
+case AMDIL::ATOM_G_ ## OP ## _NORET: return AMDIL::ATOM_A_ ## OP ## _NORET;
switch (op) {
- default:
- break;
+ default: break;
ATOM_CASE(ADD);
ATOM_CASE(AND);
ATOM_CASE(CMPXCHG);
@@ -1784,8 +2002,7 @@
ATOM_CASE(UMAX);
ATOM_CASE(UMIN);
ATOM_CASE(XOR);
- case AMDIL::ATOM_G_XCHG:
- return AMDIL::ATOM_A_XCHG;
+ case AMDIL::ATOM_G_XCHG: return AMDIL::ATOM_A_XCHG;
}
assert(!"Unknown atomic opcode found!");
return 0;
@@ -1793,7 +2010,7 @@
// A byte pointer is a pointer that along the pointer path has a
// byte store assigned to it.
void
-AMDILPointerManagerImpl::annotateBytePtrs()
+AMDILEGPointerManagerImpl::annotateBytePtrs()
{
PtrSet::iterator siBegin, siEnd;
std::vector<MachineInstr*>::iterator miBegin, miEnd;
@@ -1836,7 +2053,7 @@
if (mAMI->isKernel(funcName)) {
const AMDILKernel *krnl = mAMI->getKernel(funcName);
curRes.bits.ResourceID = mAMI->getConstPtrCB(krnl,
- siBegin->second->getName());
+ siBegin->second->getName());
curRes.bits.HardwareInst = 1;
} else {
curRes.bits.ResourceID = STM->device()
@@ -1849,7 +2066,7 @@
// the device to use as the ResourceID
curRes.bits.ResourceID = STM->device()
->getResourceID(AMDILDevice::LDS_ID);
- if (isAtomicInst(TM, *miBegin)) {
+ if (isAtomicInst(*miBegin)) {
assert(curRes.bits.ResourceID && "Atomic resource ID "
"cannot be non-zero!");
(*miBegin)->getOperand((*miBegin)->getNumOperands()-1)
@@ -1862,7 +2079,7 @@
// the device to use as the ResourceID
curRes.bits.ResourceID = STM->device()
->getResourceID(AMDILDevice::GDS_ID);
- if (isAtomicInst(TM, *miBegin)) {
+ if (isAtomicInst(*miBegin)) {
assert(curRes.bits.ResourceID && "Atomic resource ID "
"cannot be non-zero!");
(*miBegin)->getOperand((*miBegin)->getNumOperands()-1)
@@ -1881,13 +2098,15 @@
}
curRes.bits.ByteStore = 1;
curRes.bits.ResourceID = (curArg
- && (STM->device()->isSupported(AMDILDeviceInfo::NoAlias)
+ && (STM->device()->isSupported(
+ AMDILDeviceInfo::NoAlias)
|| curArg->hasNoAliasAttr())) ?
- arenaID : STM->device()->getResourceID(AMDILDevice::ARENA_UAV_ID);
+ arenaID : STM->device()->getResourceID(
+ AMDILDevice::ARENA_UAV_ID);
if (STM->device()->isSupported(AMDILDeviceInfo::ArenaSegment)) {
arenaInc = true;
}
- if (isAtomicInst(TM, *miBegin) &&
+ if (isAtomicInst(*miBegin) &&
STM->device()->isSupported(AMDILDeviceInfo::ArenaUAV)) {
(*miBegin)->getOperand((*miBegin)->getNumOperands()-1)
.setImm(curRes.bits.ResourceID);
@@ -1914,11 +2133,12 @@
// A semaphore pointer is a opaque object that has semaphore instructions
// in its path.
void
-AMDILPointerManagerImpl::annotateSemaPtrs()
+AMDILEGPointerManagerImpl::annotateSemaPtrs()
{
unsigned currentSemaphore = 1;
for (SemaSet::iterator asBegin = semaphores.begin(),
- asEnd = semaphores.end(); asBegin != asEnd; ++asBegin) {
+ asEnd = semaphores.end(); asBegin != asEnd; ++asBegin)
+ {
const Value* curVal = asBegin->second;
if (DEBUGME) {
dbgs() << "Semaphore: " << curVal->getName()
@@ -1936,20 +2156,6 @@
MI->dump();
}
break;
- case AMDIL::SEMAPHORE_INIT: {
- MachineRegisterInfo ®Info = MI->getParent()->getParent()->getRegInfo();
- MachineOperand &init_value = MI->getOperand(2);
- MachineOperand& defOp = regInfo.reg_begin(init_value.getReg()).getOperand();
- MachineInstr *defMI = defOp.getParent();
- if (!defOp.isReg()
- || defMI->getOpcode() != AMDIL::LOADCONST_i32
- || MI->getNumOperands() != 3) {
- mMFI->addErrorMsg(
- amd::CompilerErrorMessage[INVALID_INIT_VALUE]);
- } else {
- MI->getOperand(2).ChangeToImmediate(defMI->getOperand(1).getImm());
- }
- }
case AMDIL::SEMAPHORE_WAIT:
case AMDIL::SEMAPHORE_SIGNAL:
MI->getOperand(0).ChangeToImmediate(currentSemaphore);
@@ -1971,11 +2177,12 @@
/// An append pointer is a opaque object that has append instructions
// in its path.
void
-AMDILPointerManagerImpl::annotateAppendPtrs()
+AMDILEGPointerManagerImpl::annotateAppendPtrs()
{
unsigned currentCounter = 0;
for (AppendSet::iterator asBegin = counters.begin(),
- asEnd = counters.end(); asBegin != asEnd; ++asBegin) {
+ asEnd = counters.end(); asBegin != asEnd; ++asBegin)
+ {
bool usesWrite = false;
bool usesRead = false;
const Value* curVal = asBegin->second;
@@ -2023,7 +2230,7 @@
}
// A raw pointer is any pointer that does not have byte store in its path.
void
-AMDILPointerManagerImpl::annotateRawPtrs()
+AMDILEGPointerManagerImpl::annotateRawPtrs()
{
PtrSet::iterator siBegin, siEnd;
std::vector<MachineInstr*>::iterator miBegin, miEnd;
@@ -2069,7 +2276,7 @@
if (mAMI->isKernel(funcName)) {
const AMDILKernel *krnl = mAMI->getKernel(funcName);
curRes.bits.ResourceID = mAMI->getConstPtrCB(krnl,
- siBegin->second->getName());
+ siBegin->second->getName());
curRes.bits.HardwareInst = 1;
} else {
curRes.bits.ResourceID = STM->device()
@@ -2082,7 +2289,7 @@
// the device to use as the ResourceID
curRes.bits.ResourceID = STM->device()
->getResourceID(AMDILDevice::LDS_ID);
- if (isAtomicInst(TM, *miBegin)) {
+ if (isAtomicInst(*miBegin)) {
assert(curRes.bits.ResourceID && "Atomic resource ID "
"cannot be non-zero!");
(*miBegin)->getOperand((*miBegin)->getNumOperands()-1)
@@ -2095,7 +2302,7 @@
// the device to use as the ResourceID
curRes.bits.ResourceID = STM->device()
->getResourceID(AMDILDevice::GDS_ID);
- if (isAtomicInst(TM, *miBegin)) {
+ if (isAtomicInst(*miBegin)) {
assert(curRes.bits.ResourceID && "Atomic resource ID "
"cannot be non-zero!");
(*miBegin)->getOperand((*miBegin)->getNumOperands()-1)
@@ -2132,7 +2339,7 @@
curRes.bits.ResourceID = STM->device()
->getResourceID(AMDILDevice::ARENA_UAV_ID);
}
- if (isAtomicInst(TM, *miBegin)) {
+ if (isAtomicInst(*miBegin)) {
(*miBegin)->getOperand((*miBegin)->getNumOperands()-1)
.setImm(curRes.bits.ResourceID);
if (curRes.bits.ResourceID
@@ -2152,11 +2359,9 @@
setAsmPrinterFlags(*miBegin, curRes);
}
}
-
}
-
void
-AMDILPointerManagerImpl::annotateCacheableInstrs()
+AMDILEGPointerManagerImpl::annotateCacheableInstrs()
{
CacheableInstrSet::iterator miBegin, miEnd;
@@ -2177,28 +2382,134 @@
}
}
}
+// A local pointer is a pointer that point to the local address space
+// For local pointers that don't conflict with other local pointers,
+// allocate a new local buffer for each such pointer. For all local
+// pointers that conflict with another local pointer, allocate all local
+// pointers that conflict with each other into their own local buffer.
+void
+AMDILEGPointerManagerImpl::annotateLocalPtrs()
+{
+ assert(STM->device()->usesHardware(AMDILDeviceInfo::LocalMem)
+ && "not checked before calling this");
+ std::vector<MachineInstr*>::iterator miBegin, miEnd;
+ unsigned setId = 0;
+ for (SmallValSets::iterator siBegin = localPtrSets.begin(),
+ siEnd = localPtrSets.end();
+ siBegin != siEnd; ++siBegin, ++setId) {
+ const SmallValSet& set = *siBegin;
+ if (set.empty()) continue;
+
+ // populate the next local buffer with the current set of local pointers
+ bool isDefaultBuf = setId == 0;
+ uint32_t resourceID = mAMI->populateNextLocalBuffer(set, isDefaultBuf);
+
+ // mark resource id of all instructions that accesses local pointers
+ // in the set to the local buffer id
+ for (miBegin = localSetId2InstMap[setId].begin(),
+ miEnd = localSetId2InstMap[setId].end();
+ miBegin != miEnd; ++miBegin) {
+ if (DEBUGME) {
+ dbgs() << "Annotating local pointer as " << resourceID << ". Inst: ";
+ (*miBegin)->dump();
+ }
+ AMDILAS::InstrResEnc curRes;
+ getAsmPrinterFlags(*miBegin, curRes);
-// Annotate the instructions along various pointer paths. The paths that
-// are handled are the raw, byte and cacheable pointer paths.
+ if (curRes.bits.ResourceID != resourceID) {
+ curRes.bits.ResourceID = resourceID;
+ setAsmPrinterFlags((*miBegin), curRes);
+ if (isAtomicInst(*miBegin)) {
+ (*miBegin)->getOperand((*miBegin)->getNumOperands()-1)
+ .setImm(resourceID);
+ }
+ }
+ }
+ }
+}
+// Now replace the Addri instruction that corresponds to each local array
+// with a loadconst instruction
void
-AMDILPointerManagerImpl::annotatePtrPath()
+AMDILEGPointerManagerImpl::replaceAddri()
{
- if (PtrToInstMap.empty()) {
- return;
+ MachineRegisterInfo ®Info = MF.getRegInfo();
+ for (GVInstPairVec::iterator it = localNAddriVec.begin(),
+ end = localNAddriVec.end(); it != end; ++it) {
+ const GlobalValue* localPtr = (*it).first;
+ MachineInstr* addri = (*it).second;
+ unsigned baseOffsetReg = addri->getOperand(2).getReg();
+ MachineInstr* baseOffsetInst = regInfo.getVRegDef(baseOffsetReg);
+ assert(baseOffsetInst->getOpcode() == AMDIL::LOADCONSTi32 && "sanity");
+ int32_t baseOffset = baseOffsetInst->getOperand(1).getImm();
+ int32_t dummyimm = addri->getOperand(3).getImm();
+ assert(dummyimm == 0 && "sanity");
+ int32_t arrayOffset = mAMI->getArrayOffset(localPtr->getName().str());
+ unsigned dstReg = addri->getOperand(0).getReg();
+ // if baseOffst + arrayOffset is 0, and addri's use is a add,
+ // it's adding 0, so the add can be optimized away
+ if (baseOffset + arrayOffset == 0) {
+ SmallVector<MachineInstr*, 1> deadInsts;
+ for (MachineRegisterInfo::use_iterator it = regInfo.use_begin(dstReg),
+ end = regInfo.use_end(); it != end; ++it) {
+ MachineInstr& useInst = *it;
+ if (isAddInst(&useInst) || isCustomAddInst(&useInst)) {
+ assert(useInst.getNumOperands() == 3
+ && useInst.getOperand(0).isDef()
+ && "unexpected add inst format");
+ unsigned useDstReg = useInst.getOperand(0).getReg();
+ unsigned useOp1Reg = useInst.getOperand(1).getReg();
+ unsigned useOp2Reg = useInst.getOperand(2).getReg();
+ assert((useOp1Reg == dstReg || useOp2Reg == dstReg) && "invalid use");
+ unsigned opReg = (useOp1Reg == dstReg) ? useOp2Reg : useOp1Reg;
+ regInfo.replaceRegWith(useDstReg, opReg);
+ deadInsts.push_back(&useInst);
+ }
+ }
+ // erase the add instructions
+ for (SmallVector<MachineInstr*, 1>::iterator it = deadInsts.begin(),
+ end = deadInsts.end(); it != end; ++it) {
+ (*it)->eraseFromParent();
+ }
+ }
+ if (!regInfo.use_empty(dstReg)) {
+ short ptrRegClassID = addri->getDesc().OpInfo[0].RegClass;
+ assert((ptrRegClassID == AMDIL::GPRI32RegClassID
+ || ptrRegClassID == AMDIL::GPRI64RegClassID)
+ && "unexpected reg class for pointer type");
+ unsigned loadconstOp = (ptrRegClassID == AMDIL::GPRI32RegClassID)
+ ? AMDIL::LOADCONSTi32 : AMDIL::LOADCONSTi64;
+ MachineBasicBlock* mb = addri->getParent();
+ BuildMI(*mb, addri, addri->getDebugLoc(),
+ TM.getInstrInfo()->get(loadconstOp), dstReg)
+ .addImm(arrayOffset + baseOffset);
+ }
+ addri->eraseFromParent();
}
- // First we can check the cacheable pointers
- annotateCacheablePtrs();
+}
+// Annotate the instructions along various pointer paths. The paths that
+// are handled are the raw, byte, cacheable and local pointer paths.
+void
+AMDILEGPointerManagerImpl::annotatePtrPath()
+{
+ if (!PtrToInstMap.empty()) {
+ // First we can check the cacheable pointers
+ annotateCacheablePtrs();
- // Next we annotate the byte pointers
- annotateBytePtrs();
+ // Next we annotate the byte pointers
+ annotateBytePtrs();
- // Next we annotate the raw pointers
- annotateRawPtrs();
-}
+ // Next we annotate the raw pointers
+ annotateRawPtrs();
+ }
+ // Next we annotate the local pointers
+ if(STM->device()->usesHardware(AMDILDeviceInfo::LocalMem)) {
+ if (doPerPointerLDS) annotateLocalPtrs();
+ }
+}
// Allocate MultiUAV pointer ID's for the raw/conflict pointers.
void
-AMDILPointerManagerImpl::allocateMultiUAVPointers(TargetMachine &TM)
+AMDILEGPointerManagerImpl::allocateMultiUAVPointers()
{
if (PtrToInstMap.empty()) {
return;
@@ -2216,8 +2527,9 @@
// First lets handle the raw pointers.
for (siBegin = rawPtrs.begin(), siEnd = rawPtrs.end();
siBegin != siEnd; ++siBegin) {
- assert(siBegin->second->getType()->isPointerTy() && "We must be a pointer type "
- "to be processed at this point!");
+ assert(
+ siBegin->second->getType()->isPointerTy() && "We must be a pointer type "
+ "to be processed at this point!");
const PointerType *PT = dyn_cast<PointerType>(siBegin->second->getType());
if (conflictPtrs.count(*siBegin) || !PT) {
continue;
@@ -2243,7 +2555,8 @@
}
if (PT->getAddressSpace() == AMDILAS::PRIVATE_ADDRESS) {
if (STM->device()->usesSoftware(AMDILDeviceInfo::PrivateMem)) {
- const PointerType *PT = dyn_cast<PointerType>(siBegin->second->getType());
+ const PointerType *PT = dyn_cast<PointerType>(
+ siBegin->second->getType());
if (PT) {
conflictPtrs.insert(*siBegin);
}
@@ -2251,7 +2564,7 @@
if (DEBUGME) {
dbgs() << "Scratch Pointer '" << siBegin->second->getName()
<< "' being assigned uav "<<
- STM->device()->getResourceID(AMDILDevice::SCRATCH_ID) << "\n";
+ STM->device()->getResourceID(AMDILDevice::SCRATCH_ID) << "\n";
}
for (miBegin = PtrToInstMap[siBegin->second].begin(),
miEnd = PtrToInstMap[siBegin->second].end();
@@ -2301,7 +2614,7 @@
AMDILAS::InstrResEnc curRes;
getAsmPrinterFlags(*miBegin, curRes);
curRes.bits.ResourceID = curUAV;
- if (isAtomicInst(TM, *miBegin)) {
+ if (isAtomicInst(*miBegin)) {
(*miBegin)->getOperand((*miBegin)->getNumOperands()-1)
.setImm(curRes.bits.ResourceID);
if (curRes.bits.ResourceID
@@ -2345,8 +2658,9 @@
// Now lets handle the conflict pointers
for (siBegin = conflictPtrs.begin(), siEnd = conflictPtrs.end();
siBegin != siEnd; ++siBegin) {
- assert(siBegin->second->getType()->isPointerTy() && "We must be a pointer type "
- "to be processed at this point!");
+ assert(
+ siBegin->second->getType()->isPointerTy() && "We must be a pointer type "
+ "to be processed at this point!");
const PointerType *PT = dyn_cast<PointerType>(siBegin->second->getType());
// We only want to process global address space pointers
if (!PT || PT->getAddressSpace() != AMDILAS::GLOBAL_ADDRESS) {
@@ -2366,7 +2680,7 @@
AMDILAS::InstrResEnc curRes;
getAsmPrinterFlags(*miBegin, curRes);
curRes.bits.ResourceID = curUAV;
- if (isAtomicInst(TM, *miBegin)) {
+ if (isAtomicInst(*miBegin)) {
(*miBegin)->getOperand((*miBegin)->getNumOperands()-1)
.setImm(curRes.bits.ResourceID);
if (curRes.bits.ResourceID
@@ -2401,8 +2715,9 @@
// is just an optimization to more efficiently allocate
// resource ID's.
void
-AMDILPointerManagerImpl::allocateDefaultIDs(TargetMachine &TM)
+AMDILPointerManagerImpl::allocateDefaultIDs()
{
+ MachineModuleInfo &mmi = MF.getMMI();
std::string longName = std::string("llvm.sampler.annotations.") +
std::string(MF.getFunction()->getName());
llvm::StringRef funcName = longName;
@@ -2419,23 +2734,22 @@
for (MachineBasicBlock::iterator mbb = MB->begin(), mbe = MB->end();
mbb != mbe; ++mbb) {
MachineInstr *MI = mbb;
- if (isLoadInst(TM, MI)
- || isStoreInst(TM, MI)
- || isAtomicInst(TM, MI)) {
+ if (isPtrLoadInst(MI)
+ || isPtrStoreInst(MI)
+ || isAtomicInst(MI)) {
AMDILAS::InstrResEnc curRes;
getAsmPrinterFlags(MI, curRes);
- allocateDefaultID(TM, curRes, MI, false);
+ allocateDefaultID(curRes, MI, false);
}
}
}
}
-
bool
-AMDILPointerManagerImpl::perform()
+AMDILEGPointerManagerImpl::perform()
{
// Start out by allocating the default ID's to all instructions in the
// function.
- allocateDefaultIDs(TM);
+ allocateDefaultIDs();
if (!mMFI->isKernel()) {
// We don't need to parse non-kernel functions as
@@ -2449,6 +2763,32 @@
// live in registers to the lookup table and the pointer mapping.
numWriteImages = parseArguments();
+ doPerPointerLDS = false;
+
+ // If hardware supports local memory, remember local arrays that belongs
+ // to this function into "localPtrs"
+ if (STM->device()->usesHardware(AMDILDeviceInfo::LocalMem)) {
+#ifndef PER_POINTER_LDS_WITH_KERNEL_ARG
+ // As of now, the meta data we pass to the runtime only has the total
+ // amount of lds buffer allocated by the kernel. If both lds pointer type
+ // kernel arguments and lds arrays exist, the runtime needs to also know
+ // the amount allocated by the kernel in the lds buffer where kernel
+ // arguments will be allocated. But we don't want to change the ABI to
+ // break ABI compatibility.
+ // So for now, disable per-pointer lds buffer allocation if lds pointer
+ // kernel arguments exist, until we move away from meta data.
+ if (!localPtrs.empty()) {
+ doPerPointerLDS = false;
+ localPtrs.clear();
+ }
+#endif
+ if (doPerPointerLDS) {
+ parseLocalArrays();
+ // initialize localPtrSets
+ initializeLocalPtrSets();
+ }
+ }
+
// Lets do some error checking on the results of the parsing.
if (counters.size() > OPENCL_MAX_NUM_ATOMIC_COUNTERS) {
mMFI->addErrorMsg(
@@ -2466,24 +2806,23 @@
// Now lets parse all of the instructions and update our
// lookup tables.
- parseFunction(TM);
+ parseFunction();
// We need to go over our pointer map and find all the conflicting
// pointers that have byte stores and put them in the bytePtr map.
// All conflicting pointers that don't have byte stores go into
// the rawPtr map.
- detectConflictingPointers(TM);
+ detectConflictingPointers();
// The next step is to detect whether the pointer should be added to
// the fully cacheable set or not. A pointer is marked as cacheable if
// no store instruction exists.
- detectFullyCacheablePointers(TM);
+ detectFullyCacheablePointers();
// Disable partially cacheable for now when multiUAV is on.
// SC versions before SC139 have a bug that generates incorrect
// addressing for some cached accesses.
- if (!STM->device()->isSupported(AMDILDeviceInfo::MultiUAV) &&
- STM->calVersion() >= CAL_VERSION_SC_139) {
+ if (!STM->device()->isSupported(AMDILDeviceInfo::MultiUAV)) {
// Now we take the set of loads that have no reachable stores and
// create a list of additional instructions (those that aren't already
// in a cacheablePtr set) that are safe to mark as cacheable.
@@ -2506,13 +2845,21 @@
// Annotate the semaphore path if any exists.
annotateSemaPtrs();
+ // Now replace the Addri instruction that corresponds to each local array
+ // with a loadconst instruction.
+ // Note that this should be called after annotateLocalPtrs()
+ if(STM->device()->usesHardware(AMDILDeviceInfo::LocalMem)
+ && doPerPointerLDS) {
+ replaceAddri();
+ }
+
// If we support MultiUAV, then we need to determine how
// many write images exist so that way we know how many UAV are
// left to allocate to buffers.
if (STM->device()->isSupported(AMDILDeviceInfo::MultiUAV)) {
// We now have (OPENCL_MAX_WRITE_IMAGES - numPtrs) buffers open for
// multi-uav allocation.
- allocateMultiUAVPointers(TM);
+ allocateMultiUAVPointers();
}
// The last step is to detect if we have any alias constant pool operations.
@@ -2528,6 +2875,10 @@
csEnd = cacheablePtrs.end(); csBegin != csEnd; ++csBegin) {
mMFI->add_read_ptr((*csBegin).second);
}
+
+ // clear temporary machine instruction flags
+ clearTempMIFlags(MF);
+
if (DEBUGME) {
dumpPointers(bytePtrs, "Byte Store Ptrs");
dumpPointers(rawPtrs, "Raw Ptrs");
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILPointerManager.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILPointerManager.h?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILPointerManager.h (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILPointerManager.h Wed Sep 12 12:43:34 2012
@@ -32,8 +32,7 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/Target/TargetMachine.h"
-namespace llvm
-{
+namespace llvm {
class MachineFunction;
class AnalysisUsage;
// The default pointer manager. This handles pointer
@@ -42,10 +41,9 @@
class AMDILPointerManager : public MachineFunctionPass
{
public:
- AMDILPointerManager(
- TargetMachine &tm,
- CodeGenOpt::Level OL);
- virtual ~AMDILPointerManager();
+ AMDILPointerManager();
+ virtual ~AMDILPointerManager() {
+ };
virtual const char*
getPassName() const;
virtual bool
@@ -53,27 +51,26 @@
virtual void
getAnalysisUsage(AnalysisUsage &AU) const;
static char ID;
-protected:
- TargetMachine& TM;
- virtual void clearTempMIFlags(MachineFunction &F);
private:
-}; // class AMDILPointerManager
+}; // class AMDILPointerManager
// The pointer manager for Evergreen and Northern Island
// devices. This pointer manager allocates and trackes
// cached memory, arena resources, raw resources and
// whether multi-uav is utilized or not.
-class AMDILEGPointerManager : public AMDILPointerManager
+class AMDILEGPointerManager : public MachineFunctionPass
{
public:
- AMDILEGPointerManager(
- TargetMachine &tm,
- CodeGenOpt::Level OL);
- virtual ~AMDILEGPointerManager();
+ AMDILEGPointerManager();
+ virtual ~AMDILEGPointerManager() {
+ };
virtual const char*
getPassName() const;
virtual bool
runOnMachineFunction(MachineFunction &F);
-}; // class AMDILEGPointerManager
+ virtual void
+ getAnalysisUsage(AnalysisUsage &AU) const;
+ static char ID;
+}; // class AMDILEGPointerManager
} // end llvm namespace
#endif // _AMDIL_POINTER_MANAGER_H_
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILPointerManagerImpl.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILPointerManagerImpl.h?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILPointerManagerImpl.h (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILPointerManagerImpl.h Wed Sep 12 12:43:34 2012
@@ -22,6 +22,7 @@
#include "AMDIL.h"
#include "AMDILUtilityFunctions.h"
+#include "llvm/ADT/SmallSet.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/MachineFunctionAnalysis.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
@@ -35,18 +36,54 @@
#include <list>
#include <queue>
-namespace llvm
-{
+namespace llvm {
class Value;
class MachineBasicBlock;
class AMDILModuleInfo;
// The default pointer manager implementation.
+// This pointer manager implementation just assigns the default ID's to
+// each load/store instruction and does nothing else. This is
+// the pointer manager for the 7XX series of cards.
+class AMDILPointerManagerImpl {
+protected:
+ // Helper function that allocates the default resource ID for the
+ // respective I/O types.
+ void allocateDefaultID(AMDILAS::InstrResEnc &curRes,
+ MachineInstr *MI,
+ bool addID);
+ void clearTempMIFlags(MachineFunction &MF);
+
+ // The first thing we should do is to allocate the default
+ // ID for each load/store/atomic instruction so that
+ // it is correctly allocated. Everything else after this
+ // is just an optimization to more efficiently allocate
+ // resource ID's.
+ void allocateDefaultIDs();
+
+public:
+ AMDILPointerManagerImpl(MachineFunction& mf, const TargetMachine& tm);
+ ~AMDILPointerManagerImpl() {
+ }
+
+ // the main driver function
+ virtual bool perform();
+
+protected:
+ MachineFunction& MF;
+ const TargetMachine &TM;
+ AMDILMachineFunctionInfo *mMFI;
+ const AMDILTargetMachine *ATM;
+ const AMDILSubtarget *STM;
+ AMDILKernelManager *KM;
+ AMDILModuleInfo* mAMI;
+};
+
+// The EG pointer manager implementation.
// This pointer manager implementation allocates and trackes
// cached memory, arena resources, raw resources and
// whether multi-uav is utilized or not.
-class AMDILPointerManagerImpl
-{
+class AMDILEGPointerManagerImpl : public AMDILPointerManagerImpl {
protected:
// A pair that maps a name of string to a value.
typedef std::pair<StringRef, const Value*> StrValPair;
@@ -57,6 +94,8 @@
// argument in a function call.
typedef std::set<StrValPair> PtrSet;
+ typedef std::set<const Value*> ValueSet;
+
// A Byte set is the set of all base pointers that must
// be allocated to the arena path.
typedef PtrSet ByteSet;
@@ -113,19 +152,37 @@
// mappings for a given function.
typedef std::map<unsigned, RegValPair> RVPVec;
+ typedef SmallSet<const Value*, 1> SmallValSet;
+ // map a Value to the list of local arrays that it accesses
+ typedef std::map<unsigned, SmallValSet> Reg2ValSet;
+
+ // list of local array sets
+ typedef std::vector<SmallValSet> SmallValSets;
+
+ // map from a local array to the index of the local array set
+ // that it belongs
+ typedef std::map<const Value*, unsigned> Val2SetIDMap;
+
+ typedef std::map<unsigned, std::vector<MachineInstr*> > ValSetId2InstsMap;
+
+ // list of <local array, addri inst> pairs that makes it easy to find
+ // the only addri that corresponds to a local array
+ typedef std::pair<const GlobalValue*, MachineInstr*> GVInstPair;
+ typedef std::vector<GVInstPair> GVInstPairVec;
+
// Information related to the cacheability of instructions in a basic block.
// This is used during the parse phase of the pointer algorithm to track
// the reachability of stores within a basic block.
- class BlockCacheableInfo
- {
+ class BlockCacheableInfo {
public:
BlockCacheableInfo() :
mStoreReachesTop(false),
mStoreReachesExit(false),
mCacheableSet()
- {};
+ {
+ };
- bool storeReachesTop() const {
+ bool storeReachesTop() const {
return mStoreReachesTop;
}
bool storeReachesExit() const {
@@ -153,13 +210,11 @@
mStoreReachesExit = true;
return changedExit;
}
-
// Mark the block as having a store that reaches the exit of the
// block.
void setReachesExit() {
mStoreReachesExit = true;
}
-
// If the top or the exit of the block are not marked as reachable
// by a store, add the load to the list of cacheable loads.
void addPossiblyCacheableInst(MachineInstr *load) {
@@ -172,11 +227,10 @@
mCacheableSet.insert(load);
}
-
private:
- bool mStoreReachesTop; // Does a global store reach the top of this block?
- bool mStoreReachesExit;// Does a global store reach the exit of this block?
- CacheableInstrSet mCacheableSet; // The set of loads in the block not
+ bool mStoreReachesTop; // Does a global store reach the top of this block?
+ bool mStoreReachesExit; // Does a global store reach the exit of this block?
+ CacheableInstrSet mCacheableSet; // The set of loads in the block not
// reachable by a global store.
};
@@ -184,14 +238,6 @@
typedef std::map<MachineBasicBlock*, BlockCacheableInfo> MBBCacheableMap;
protected:
- MachineFunction& MF;
- TargetMachine &TM;
- AMDILMachineFunctionInfo *mMFI;
- const AMDILTargetMachine *ATM;
- const AMDILSubtarget *STM;
- AMDILKernelManager *KM;
- AMDILModuleInfo* mAMI;
-
// A set of all pointers are tracked in this map and
// if multiple pointers are detected, they go to the same
// set.
@@ -223,6 +269,9 @@
// somewhere in the pointer path.
ConflictSet conflictPtrs;
+ // Set of all the pointers that are local pointers.
+ ValueSet localPtrs;
+
// Set of all pointers that are images
ImageSet images;
@@ -251,21 +300,42 @@
// them to arena, otherwise we assign them to raw.
RVPVec lookupTable;
+ // A map that maps a register to a set of local pointers
+ Reg2ValSet localPtrMap;
+
+ // a list of local pointer sets
+ SmallValSets localPtrSets;
+
+ // map a local pointer to the index of the local pointer set that it belongs
+ Val2SetIDMap localPtr2SetIdMap;
+
+ // Maps a local pointer set to the set of load/store instructions that
+ // access local pointers in the set
+ ValSetId2InstsMap localSetId2InstMap;
+
+ // Maps a local pointer to the only Addri instruction that cor
+ GVInstPairVec localNAddriVec;
+
uint32_t numWriteImages;
+ bool doPerPointerLDS;
+
protected:
- StrValPair createStrValPair(const Value* ptr) {
+ StrValPair createStrValPair(const Value* ptr)
+ {
return std::make_pair(ptr ? ptr->getName() : StringRef(""), ptr);
}
+ // initialize localPtrSets and localPtr2SetIdMap
+ void initializeLocalPtrSets();
- std::string findSamplerName(TargetMachine &TM, MachineInstr* MI, unsigned &val);
+ std::string findSamplerName(MachineInstr* MI, unsigned &val);
+ std::string findSamplerNameFromReg(unsigned reg, unsigned &val);
- // Helper function that allocates the default resource ID for the
- // respective I/O types.
- void allocateDefaultID(TargetMachine &TM,
- AMDILAS::InstrResEnc &curRes,
- MachineInstr *MI,
- bool addID);
+ // Given a load or store instruction, if it's a local load or store,
+ // and if its pointer oper derives from multiple local pointers, then
+ // add the local pointers to the conflict local pointer set.
+ void detectConflictLocalPtrs(MachineInstr *MI,
+ unsigned reg, const AMDILSubtarget *STM);
// Function that parses the arguments and updates the lookupTable with the
// pointer -> register mapping. This function also checks for cacheable
@@ -293,37 +363,37 @@
unsigned dstReg);
// In this case we want to handle a load instruction.
- void parseLoadInst(TargetMachine &TM, MachineInstr *MI);
+ void parseLoadInst(MachineInstr *MI);
// In this case we want to handle a store instruction.
- void parseStoreInst(TargetMachine &TM, MachineInstr *MI);
+ void parseStoreInst(MachineInstr *MI);
// In this case we want to handle an atomic instruction.
- void parseAtomicInst(TargetMachine &TM, MachineInstr *MI);
+ void parseAtomicInst(MachineInstr *MI);
// In this case we want to handle a counter instruction.
- void parseAppendInst(TargetMachine &TM, MachineInstr *MI);
+ void parseAppendInst(MachineInstr *MI);
/// In this case we want to handle a semaphore instruction.
- void parseSemaInst(TargetMachine &TM, MachineInstr *MI);
+ void parseSemaInst(MachineInstr *MI);
// In this case we want to handle an Image instruction.
- void parseImageInst(TargetMachine &TM, MachineInstr *MI);
+ void parseImageInst(MachineInstr *MI);
// if addri's address is a local array, map addri's dest reg to
// the local array
void parseAddriInst(MachineInstr *MI);
// This case handles the rest of the instructions
- void parseInstruction(TargetMachine &TM, MachineInstr *MI);
+ void parseInstruction(MachineInstr *MI);
// This function parses the basic block and based on the instruction type,
// calls the function to finish parsing the instruction.
- void parseBasicBlock(TargetMachine &TM, MachineBasicBlock *MB);
+ void parseBasicBlock(MachineBasicBlock *MB);
// Follows the Reverse Post Order Traversal of the basic blocks to
// determine which order to parse basic blocks in.
- void parseFunction(TargetMachine &TM);
+ void parseFunction();
// Helper function that dumps to dbgs() information about
// a pointer set.
@@ -336,14 +406,14 @@
// Function that detects all the conflicting pointers and adds
// the pointers that are detected to the conflict set, otherwise
// they are added to the raw or byte set based on their usage.
- void detectConflictingPointers(TargetMachine &TM);
+ void detectConflictingPointers();
// Function that detects aliased constant pool operations.
void detectAliasedCPoolOps();
// Function that detects fully cacheable pointers. Fully cacheable pointers
// are pointers that have no writes to them and no-alias is specified.
- void detectFullyCacheablePointers(TargetMachine &TM);
+ void detectFullyCacheablePointers();
// Are any of the pointers in PtrSet also in the BytePtrs or the CachePtrs?
bool ptrSetIntersectsByteOrCache(PtrSet &cacheSet);
@@ -382,26 +452,38 @@
virtual void annotateCacheableInstrs();
+ virtual void annotateLocalPtrs();
+
// Annotate the instructions along various pointer paths. The paths that
// are handled are the raw, byte, cacheable and local pointer paths.
virtual void annotatePtrPath();
// Allocate MultiUAV pointer ID's for the raw/conflict pointers.
- void allocateMultiUAVPointers(TargetMachine &TM);
+ void allocateMultiUAVPointers();
-public:
- AMDILPointerManagerImpl(MachineFunction& mf, TargetMachine& tm);
- virtual ~AMDILPointerManagerImpl() {}
+ void replaceAddri();
- // The first thing we should do is to allocate the default
- // ID for each load/store/atomic instruction so that
- // it is correctly allocated. Everything else after this
- // is just an optimization to more efficiently allocate
- // resource ID's.
- virtual void allocateDefaultIDs(TargetMachine &TM);
+public:
+ AMDILEGPointerManagerImpl(MachineFunction& mf, const TargetMachine& tm);
+ ~AMDILEGPointerManagerImpl() {
+ }
// the main driver function
- bool perform();
-}; // class AMDILPointerManagerImpl
+ virtual bool perform();
+}; // class AMDILEGPointerManagerImpl
+
+class AMDILSIPointerManagerImpl : public AMDILEGPointerManagerImpl {
+public:
+ AMDILSIPointerManagerImpl(MachineFunction &mf, const TargetMachine &tm)
+ : AMDILEGPointerManagerImpl(mf, tm) {
+ }
+ virtual ~AMDILSIPointerManagerImpl() {
+ }
+protected:
+ virtual void annotateBytePtrs();
+ virtual void annotateRawPtrs();
+ virtual void annotateCacheablePtrs();
+ virtual void annotateCacheableInstrs();
+};
} // end llvm namespace
#endif // _AMDIL_POINTER_MANAGER_IMPL_H_
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILPrintfConvert.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILPrintfConvert.cpp?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILPrintfConvert.cpp (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILPrintfConvert.cpp Wed Sep 12 12:43:34 2012
@@ -11,8 +11,8 @@
//
//===----------------------------------------------------------------------===//
-#define DEBUG_TYPE "PrintfConvert"
-#ifdef DEBUG
+#define DEBUG_TYPE "printfconvert"
+#if !defined(NDEBUG)
#define DEBUGME (DebugFlag && isCurrentDebugType(DEBUG_TYPE))
#else
#define DEBUGME 0
@@ -49,7 +49,8 @@
bool doInitialization(Module &M);
bool doFinalization(Module &M);
void getAnalysisUsage(AnalysisUsage &AU) const;
- static const char* getConversionSpecifiers(const std::string& fmt,size_t num_ops);
+ static const char* getConversionSpecifiers(const std::string& fmt,
+ size_t num_ops);
private:
bool expandPrintf(BasicBlock::iterator *bbb);
AMDILMachineFunctionInfo *mMFI;
@@ -107,17 +108,21 @@
ConstantExpr *GEPinst = dyn_cast<ConstantExpr>(op);
if (GEPinst) {
GlobalVariable *GVar
- = dyn_cast<GlobalVariable>(GEPinst->getOperand(0));
+ = dyn_cast<GlobalVariable>(GEPinst->getOperand(0));
std::string str = "unknown";
if (GVar && GVar->hasInitializer()) {
ConstantDataArray *CA
- = dyn_cast<ConstantDataArray>(GVar->getInitializer());
+ = dyn_cast<ConstantDataArray>(GVar->getInitializer());
str = (CA->isString() ? CA->getAsString() : "unknown");
opConvSpecifiers = getConversionSpecifiers(str,num_ops - 2);
}
uint64_t id = (uint64_t)mMFI->addPrintfString(str,
- getAnalysis<MachineFunctionAnalysis>().getMF()
- .getMMI().getObjFileInfo<AMDILModuleInfo>().get_printf_offset());
+ getAnalysis<
+ MachineFunctionAnalysis>().
+ getMF()
+ .getMMI().getObjFileInfo<
+ AMDILModuleInfo>().
+ get_printf_offset());
std::string name = "___dumpStringID";
Function *nF = NULL;
std::vector<Type*> types;
@@ -125,13 +130,13 @@
nF = mF->getParent()->getFunction(name);
if (!nF) {
nF = Function::Create(
- FunctionType::get(
- Type::getVoidTy(mF->getContext()), types, false),
- GlobalValue::ExternalLinkage,
- name, mF->getParent());
+ FunctionType::get(
+ Type::getVoidTy(mF->getContext()), types, false),
+ GlobalValue::ExternalLinkage,
+ name, mF->getParent());
}
Constant *C = ConstantInt::get(
- Type::getInt32Ty(mF->getContext()), id, false);
+ Type::getInt32Ty(mF->getContext()), id, false);
CallInst *nCI = CallInst::Create(nF, C);
nCI->insertBefore(CI);
bytes = strlen(str.data());
@@ -161,10 +166,10 @@
Type *iType = NULL;
if (oType->isFloatTy()) {
iType = dyn_cast<Type>(
- Type::getInt32Ty(oType->getContext()));
+ Type::getInt32Ty(oType->getContext()));
} else {
iType = dyn_cast<Type>(
- Type::getInt64Ty(oType->getContext()));
+ Type::getInt64Ty(oType->getContext()));
}
op = new BitCastInst(op, iType, "printfBitCast", CI);
} else if (oType->getTypeID() == Type::VectorTyID) {
@@ -191,38 +196,38 @@
default:
eleCount = totalSize / 64;
iType = dyn_cast<Type>(
- Type::getInt64Ty(oType->getContext()));
+ Type::getInt64Ty(oType->getContext()));
break;
case 8:
if (eleCount >= 8) {
eleCount = totalSize / 64;
iType = dyn_cast<Type>(
- Type::getInt64Ty(oType->getContext()));
+ Type::getInt64Ty(oType->getContext()));
} else if (eleCount >= 3) {
eleCount = 1;
iType = dyn_cast<Type>(
- Type::getInt32Ty(oType->getContext()));
+ Type::getInt32Ty(oType->getContext()));
} else {
eleCount = 1;
iType = dyn_cast<Type>(
- Type::getInt16Ty(oType->getContext()));
+ Type::getInt16Ty(oType->getContext()));
}
break;
case 16:
if (eleCount >= 3) {
eleCount = totalSize / 64;
iType = dyn_cast<Type>(
- Type::getInt64Ty(oType->getContext()));
+ Type::getInt64Ty(oType->getContext()));
} else {
eleCount = 1;
iType = dyn_cast<Type>(
- Type::getInt32Ty(oType->getContext()));
+ Type::getInt32Ty(oType->getContext()));
}
break;
}
if (eleCount > 1) {
iType = dyn_cast<Type>(
- VectorType::get(iType, eleCount));
+ VectorType::get(iType, eleCount));
}
op = new BitCastInst(op, iType, "printfBitCast", CI);
}
@@ -258,10 +263,10 @@
nF = mF->getParent()->getFunction(name);
if (!nF) {
nF = Function::Create(
- FunctionType::get(
- Type::getVoidTy(mF->getContext()), types, false),
- GlobalValue::ExternalLinkage,
- name, mF->getParent());
+ FunctionType::get(
+ Type::getVoidTy(mF->getContext()), types, false),
+ GlobalValue::ExternalLinkage,
+ name, mF->getParent());
}
CallInst *nCI = CallInst::Create(nF, op);
nCI->insertBefore(CI);
@@ -290,7 +295,6 @@
&AMDILPrintfConvert::expandPrintf), this));
return mChanged;
}
-
const char*
AMDILPrintfConvert::getPassName() const
{
@@ -301,13 +305,11 @@
{
return false;
}
-
bool
AMDILPrintfConvert::doFinalization(Module &M)
{
return false;
}
-
void
AMDILPrintfConvert::getAnalysisUsage(AnalysisUsage &AU) const
{
@@ -316,16 +318,22 @@
AU.setPreservesAll();
}
const char*
-AMDILPrintfConvert::getConversionSpecifiers(const std::string& fmt,size_t num_ops)
+AMDILPrintfConvert::getConversionSpecifiers(const std::string& fmt,
+ size_t num_ops)
{
static const char* convSpecifiers = "cdieEfgGaosuxXp";
size_t curFmtSpecifierIdx = 0;
size_t prevFmtSpecifierIdx = 0;
size_t opIdx = 0;
char* opConvSpecifiers = new char[num_ops];
- while ((curFmtSpecifierIdx = fmt.find_first_of(convSpecifiers,curFmtSpecifierIdx)) != std::string::npos) {
+ while ((curFmtSpecifierIdx =
+ fmt.find_first_of(convSpecifiers,
+ curFmtSpecifierIdx)) != std::string::npos) {
bool argDump = false;
- const std::string curFmt = fmt.substr(prevFmtSpecifierIdx,curFmtSpecifierIdx - prevFmtSpecifierIdx);
+ const std::string curFmt = fmt.substr(
+ prevFmtSpecifierIdx,
+ curFmtSpecifierIdx -
+ prevFmtSpecifierIdx);
size_t pTag = curFmt.find_last_of("%");
if (pTag != std::string::npos) {
argDump = true;
@@ -340,7 +348,7 @@
}
if (opIdx == 0) {
delete[] opConvSpecifiers;
- return NULL;
+ return NULL;
}
return opConvSpecifiers;
}
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILProfiles.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILProfiles.td?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILProfiles.td (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILProfiles.td Wed Sep 12 12:43:34 2012
@@ -164,3 +164,15 @@
def SDTIL_Append : SDTypeProfile<1, 1, [
SDTCisVT<0, i32>, SDTCisPtrTy<1>
]>;
+
+//===----------------------------------------------------------------------===//
+// Atomic Load/Store Profile Types
+//===----------------------------------------------------------------------===//
+
+def SDTIL_AtomLoad : SDTypeProfile<1, 3, [
+ SDTCisPtrTy<1>, SDTCisInt<2>, SDTCisVT<3, i32>
+]>;
+
+def SDTIL_AtomStore : SDTypeProfile<0, 4, [
+ SDTCisPtrTy<0>, SDTCisInt<2>, SDTCisVT<3, i32>
+]>;
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterDefsScalar.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterDefsScalar.td?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterDefsScalar.td (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterDefsScalar.td Wed Sep 12 12:43:34 2012
@@ -775,6 +775,262 @@
def Ry191 : AMDILReg<191, "r191">, DwarfRegAlias<Rx191>;
def Rz191 : AMDILReg<191, "r191">, DwarfRegAlias<Rx191>;
def Rw191 : AMDILReg<191, "r191">, DwarfRegAlias<Rx191>;
+def Rx192 : AMDILReg<192, "r192">, DwarfRegNum<[192]>;
+def Ry192 : AMDILReg<192, "r192">, DwarfRegAlias<Rx192>;
+def Rz192 : AMDILReg<192, "r192">, DwarfRegAlias<Rx192>;
+def Rw192 : AMDILReg<192, "r192">, DwarfRegAlias<Rx192>;
+def Rx193 : AMDILReg<193, "r193">, DwarfRegNum<[193]>;
+def Ry193 : AMDILReg<193, "r193">, DwarfRegAlias<Rx193>;
+def Rz193 : AMDILReg<193, "r193">, DwarfRegAlias<Rx193>;
+def Rw193 : AMDILReg<193, "r193">, DwarfRegAlias<Rx193>;
+def Rx194 : AMDILReg<194, "r194">, DwarfRegNum<[194]>;
+def Ry194 : AMDILReg<194, "r194">, DwarfRegAlias<Rx194>;
+def Rz194 : AMDILReg<194, "r194">, DwarfRegAlias<Rx194>;
+def Rw194 : AMDILReg<194, "r194">, DwarfRegAlias<Rx194>;
+def Rx195 : AMDILReg<195, "r195">, DwarfRegNum<[195]>;
+def Ry195 : AMDILReg<195, "r195">, DwarfRegAlias<Rx195>;
+def Rz195 : AMDILReg<195, "r195">, DwarfRegAlias<Rx195>;
+def Rw195 : AMDILReg<195, "r195">, DwarfRegAlias<Rx195>;
+def Rx196 : AMDILReg<196, "r196">, DwarfRegNum<[196]>;
+def Ry196 : AMDILReg<196, "r196">, DwarfRegAlias<Rx196>;
+def Rz196 : AMDILReg<196, "r196">, DwarfRegAlias<Rx196>;
+def Rw196 : AMDILReg<196, "r196">, DwarfRegAlias<Rx196>;
+def Rx197 : AMDILReg<197, "r197">, DwarfRegNum<[197]>;
+def Ry197 : AMDILReg<197, "r197">, DwarfRegAlias<Rx197>;
+def Rz197 : AMDILReg<197, "r197">, DwarfRegAlias<Rx197>;
+def Rw197 : AMDILReg<197, "r197">, DwarfRegAlias<Rx197>;
+def Rx198 : AMDILReg<198, "r198">, DwarfRegNum<[198]>;
+def Ry198 : AMDILReg<198, "r198">, DwarfRegAlias<Rx198>;
+def Rz198 : AMDILReg<198, "r198">, DwarfRegAlias<Rx198>;
+def Rw198 : AMDILReg<198, "r198">, DwarfRegAlias<Rx198>;
+def Rx199 : AMDILReg<199, "r199">, DwarfRegNum<[199]>;
+def Ry199 : AMDILReg<199, "r199">, DwarfRegAlias<Rx199>;
+def Rz199 : AMDILReg<199, "r199">, DwarfRegAlias<Rx199>;
+def Rw199 : AMDILReg<199, "r199">, DwarfRegAlias<Rx199>;
+def Rx200 : AMDILReg<200, "r200">, DwarfRegNum<[200]>;
+def Ry200 : AMDILReg<200, "r200">, DwarfRegAlias<Rx200>;
+def Rz200 : AMDILReg<200, "r200">, DwarfRegAlias<Rx200>;
+def Rw200 : AMDILReg<200, "r200">, DwarfRegAlias<Rx200>;
+def Rx201 : AMDILReg<201, "r201">, DwarfRegNum<[201]>;
+def Ry201 : AMDILReg<201, "r201">, DwarfRegAlias<Rx201>;
+def Rz201 : AMDILReg<201, "r201">, DwarfRegAlias<Rx201>;
+def Rw201 : AMDILReg<201, "r201">, DwarfRegAlias<Rx201>;
+def Rx202 : AMDILReg<202, "r202">, DwarfRegNum<[202]>;
+def Ry202 : AMDILReg<202, "r202">, DwarfRegAlias<Rx202>;
+def Rz202 : AMDILReg<202, "r202">, DwarfRegAlias<Rx202>;
+def Rw202 : AMDILReg<202, "r202">, DwarfRegAlias<Rx202>;
+def Rx203 : AMDILReg<203, "r203">, DwarfRegNum<[203]>;
+def Ry203 : AMDILReg<203, "r203">, DwarfRegAlias<Rx203>;
+def Rz203 : AMDILReg<203, "r203">, DwarfRegAlias<Rx203>;
+def Rw203 : AMDILReg<203, "r203">, DwarfRegAlias<Rx203>;
+def Rx204 : AMDILReg<204, "r204">, DwarfRegNum<[204]>;
+def Ry204 : AMDILReg<204, "r204">, DwarfRegAlias<Rx204>;
+def Rz204 : AMDILReg<204, "r204">, DwarfRegAlias<Rx204>;
+def Rw204 : AMDILReg<204, "r204">, DwarfRegAlias<Rx204>;
+def Rx205 : AMDILReg<205, "r205">, DwarfRegNum<[205]>;
+def Ry205 : AMDILReg<205, "r205">, DwarfRegAlias<Rx205>;
+def Rz205 : AMDILReg<205, "r205">, DwarfRegAlias<Rx205>;
+def Rw205 : AMDILReg<205, "r205">, DwarfRegAlias<Rx205>;
+def Rx206 : AMDILReg<206, "r206">, DwarfRegNum<[206]>;
+def Ry206 : AMDILReg<206, "r206">, DwarfRegAlias<Rx206>;
+def Rz206 : AMDILReg<206, "r206">, DwarfRegAlias<Rx206>;
+def Rw206 : AMDILReg<206, "r206">, DwarfRegAlias<Rx206>;
+def Rx207 : AMDILReg<207, "r207">, DwarfRegNum<[207]>;
+def Ry207 : AMDILReg<207, "r207">, DwarfRegAlias<Rx207>;
+def Rz207 : AMDILReg<207, "r207">, DwarfRegAlias<Rx207>;
+def Rw207 : AMDILReg<207, "r207">, DwarfRegAlias<Rx207>;
+def Rx208 : AMDILReg<208, "r208">, DwarfRegNum<[208]>;
+def Ry208 : AMDILReg<208, "r208">, DwarfRegAlias<Rx208>;
+def Rz208 : AMDILReg<208, "r208">, DwarfRegAlias<Rx208>;
+def Rw208 : AMDILReg<208, "r208">, DwarfRegAlias<Rx208>;
+def Rx209 : AMDILReg<209, "r209">, DwarfRegNum<[209]>;
+def Ry209 : AMDILReg<209, "r209">, DwarfRegAlias<Rx209>;
+def Rz209 : AMDILReg<209, "r209">, DwarfRegAlias<Rx209>;
+def Rw209 : AMDILReg<209, "r209">, DwarfRegAlias<Rx209>;
+def Rx210 : AMDILReg<210, "r210">, DwarfRegNum<[210]>;
+def Ry210 : AMDILReg<210, "r210">, DwarfRegAlias<Rx210>;
+def Rz210 : AMDILReg<210, "r210">, DwarfRegAlias<Rx210>;
+def Rw210 : AMDILReg<210, "r210">, DwarfRegAlias<Rx210>;
+def Rx211 : AMDILReg<211, "r211">, DwarfRegNum<[211]>;
+def Ry211 : AMDILReg<211, "r211">, DwarfRegAlias<Rx211>;
+def Rz211 : AMDILReg<211, "r211">, DwarfRegAlias<Rx211>;
+def Rw211 : AMDILReg<211, "r211">, DwarfRegAlias<Rx211>;
+def Rx212 : AMDILReg<212, "r212">, DwarfRegNum<[212]>;
+def Ry212 : AMDILReg<212, "r212">, DwarfRegAlias<Rx212>;
+def Rz212 : AMDILReg<212, "r212">, DwarfRegAlias<Rx212>;
+def Rw212 : AMDILReg<212, "r212">, DwarfRegAlias<Rx212>;
+def Rx213 : AMDILReg<213, "r213">, DwarfRegNum<[213]>;
+def Ry213 : AMDILReg<213, "r213">, DwarfRegAlias<Rx213>;
+def Rz213 : AMDILReg<213, "r213">, DwarfRegAlias<Rx213>;
+def Rw213 : AMDILReg<213, "r213">, DwarfRegAlias<Rx213>;
+def Rx214 : AMDILReg<214, "r214">, DwarfRegNum<[214]>;
+def Ry214 : AMDILReg<214, "r214">, DwarfRegAlias<Rx214>;
+def Rz214 : AMDILReg<214, "r214">, DwarfRegAlias<Rx214>;
+def Rw214 : AMDILReg<214, "r214">, DwarfRegAlias<Rx214>;
+def Rx215 : AMDILReg<215, "r215">, DwarfRegNum<[215]>;
+def Ry215 : AMDILReg<215, "r215">, DwarfRegAlias<Rx215>;
+def Rz215 : AMDILReg<215, "r215">, DwarfRegAlias<Rx215>;
+def Rw215 : AMDILReg<215, "r215">, DwarfRegAlias<Rx215>;
+def Rx216 : AMDILReg<216, "r216">, DwarfRegNum<[216]>;
+def Ry216 : AMDILReg<216, "r216">, DwarfRegAlias<Rx216>;
+def Rz216 : AMDILReg<216, "r216">, DwarfRegAlias<Rx216>;
+def Rw216 : AMDILReg<216, "r216">, DwarfRegAlias<Rx216>;
+def Rx217 : AMDILReg<217, "r217">, DwarfRegNum<[217]>;
+def Ry217 : AMDILReg<217, "r217">, DwarfRegAlias<Rx217>;
+def Rz217 : AMDILReg<217, "r217">, DwarfRegAlias<Rx217>;
+def Rw217 : AMDILReg<217, "r217">, DwarfRegAlias<Rx217>;
+def Rx218 : AMDILReg<218, "r218">, DwarfRegNum<[218]>;
+def Ry218 : AMDILReg<218, "r218">, DwarfRegAlias<Rx218>;
+def Rz218 : AMDILReg<218, "r218">, DwarfRegAlias<Rx218>;
+def Rw218 : AMDILReg<218, "r218">, DwarfRegAlias<Rx218>;
+def Rx219 : AMDILReg<219, "r219">, DwarfRegNum<[219]>;
+def Ry219 : AMDILReg<219, "r219">, DwarfRegAlias<Rx219>;
+def Rz219 : AMDILReg<219, "r219">, DwarfRegAlias<Rx219>;
+def Rw219 : AMDILReg<219, "r219">, DwarfRegAlias<Rx219>;
+def Rx220 : AMDILReg<220, "r220">, DwarfRegNum<[220]>;
+def Ry220 : AMDILReg<220, "r220">, DwarfRegAlias<Rx220>;
+def Rz220 : AMDILReg<220, "r220">, DwarfRegAlias<Rx220>;
+def Rw220 : AMDILReg<220, "r220">, DwarfRegAlias<Rx220>;
+def Rx221 : AMDILReg<221, "r221">, DwarfRegNum<[221]>;
+def Ry221 : AMDILReg<221, "r221">, DwarfRegAlias<Rx221>;
+def Rz221 : AMDILReg<221, "r221">, DwarfRegAlias<Rx221>;
+def Rw221 : AMDILReg<221, "r221">, DwarfRegAlias<Rx221>;
+def Rx222 : AMDILReg<222, "r222">, DwarfRegNum<[222]>;
+def Ry222 : AMDILReg<222, "r222">, DwarfRegAlias<Rx222>;
+def Rz222 : AMDILReg<222, "r222">, DwarfRegAlias<Rx222>;
+def Rw222 : AMDILReg<222, "r222">, DwarfRegAlias<Rx222>;
+def Rx223 : AMDILReg<223, "r223">, DwarfRegNum<[223]>;
+def Ry223 : AMDILReg<223, "r223">, DwarfRegAlias<Rx223>;
+def Rz223 : AMDILReg<223, "r223">, DwarfRegAlias<Rx223>;
+def Rw223 : AMDILReg<223, "r223">, DwarfRegAlias<Rx223>;
+def Rx224 : AMDILReg<224, "r224">, DwarfRegNum<[224]>;
+def Ry224 : AMDILReg<224, "r224">, DwarfRegAlias<Rx224>;
+def Rz224 : AMDILReg<224, "r224">, DwarfRegAlias<Rx224>;
+def Rw224 : AMDILReg<224, "r224">, DwarfRegAlias<Rx224>;
+def Rx225 : AMDILReg<225, "r225">, DwarfRegNum<[225]>;
+def Ry225 : AMDILReg<225, "r225">, DwarfRegAlias<Rx225>;
+def Rz225 : AMDILReg<225, "r225">, DwarfRegAlias<Rx225>;
+def Rw225 : AMDILReg<225, "r225">, DwarfRegAlias<Rx225>;
+def Rx226 : AMDILReg<226, "r226">, DwarfRegNum<[226]>;
+def Ry226 : AMDILReg<226, "r226">, DwarfRegAlias<Rx226>;
+def Rz226 : AMDILReg<226, "r226">, DwarfRegAlias<Rx226>;
+def Rw226 : AMDILReg<226, "r226">, DwarfRegAlias<Rx226>;
+def Rx227 : AMDILReg<227, "r227">, DwarfRegNum<[227]>;
+def Ry227 : AMDILReg<227, "r227">, DwarfRegAlias<Rx227>;
+def Rz227 : AMDILReg<227, "r227">, DwarfRegAlias<Rx227>;
+def Rw227 : AMDILReg<227, "r227">, DwarfRegAlias<Rx227>;
+def Rx228 : AMDILReg<228, "r228">, DwarfRegNum<[228]>;
+def Ry228 : AMDILReg<228, "r228">, DwarfRegAlias<Rx228>;
+def Rz228 : AMDILReg<228, "r228">, DwarfRegAlias<Rx228>;
+def Rw228 : AMDILReg<228, "r228">, DwarfRegAlias<Rx228>;
+def Rx229 : AMDILReg<229, "r229">, DwarfRegNum<[229]>;
+def Ry229 : AMDILReg<229, "r229">, DwarfRegAlias<Rx229>;
+def Rz229 : AMDILReg<229, "r229">, DwarfRegAlias<Rx229>;
+def Rw229 : AMDILReg<229, "r229">, DwarfRegAlias<Rx229>;
+def Rx230 : AMDILReg<230, "r230">, DwarfRegNum<[230]>;
+def Ry230 : AMDILReg<230, "r230">, DwarfRegAlias<Rx230>;
+def Rz230 : AMDILReg<230, "r230">, DwarfRegAlias<Rx230>;
+def Rw230 : AMDILReg<230, "r230">, DwarfRegAlias<Rx230>;
+def Rx231 : AMDILReg<231, "r231">, DwarfRegNum<[231]>;
+def Ry231 : AMDILReg<231, "r231">, DwarfRegAlias<Rx231>;
+def Rz231 : AMDILReg<231, "r231">, DwarfRegAlias<Rx231>;
+def Rw231 : AMDILReg<231, "r231">, DwarfRegAlias<Rx231>;
+def Rx232 : AMDILReg<232, "r232">, DwarfRegNum<[232]>;
+def Ry232 : AMDILReg<232, "r232">, DwarfRegAlias<Rx232>;
+def Rz232 : AMDILReg<232, "r232">, DwarfRegAlias<Rx232>;
+def Rw232 : AMDILReg<232, "r232">, DwarfRegAlias<Rx232>;
+def Rx233 : AMDILReg<233, "r233">, DwarfRegNum<[233]>;
+def Ry233 : AMDILReg<233, "r233">, DwarfRegAlias<Rx233>;
+def Rz233 : AMDILReg<233, "r233">, DwarfRegAlias<Rx233>;
+def Rw233 : AMDILReg<233, "r233">, DwarfRegAlias<Rx233>;
+def Rx234 : AMDILReg<234, "r234">, DwarfRegNum<[234]>;
+def Ry234 : AMDILReg<234, "r234">, DwarfRegAlias<Rx234>;
+def Rz234 : AMDILReg<234, "r234">, DwarfRegAlias<Rx234>;
+def Rw234 : AMDILReg<234, "r234">, DwarfRegAlias<Rx234>;
+def Rx235 : AMDILReg<235, "r235">, DwarfRegNum<[235]>;
+def Ry235 : AMDILReg<235, "r235">, DwarfRegAlias<Rx235>;
+def Rz235 : AMDILReg<235, "r235">, DwarfRegAlias<Rx235>;
+def Rw235 : AMDILReg<235, "r235">, DwarfRegAlias<Rx235>;
+def Rx236 : AMDILReg<236, "r236">, DwarfRegNum<[236]>;
+def Ry236 : AMDILReg<236, "r236">, DwarfRegAlias<Rx236>;
+def Rz236 : AMDILReg<236, "r236">, DwarfRegAlias<Rx236>;
+def Rw236 : AMDILReg<236, "r236">, DwarfRegAlias<Rx236>;
+def Rx237 : AMDILReg<237, "r237">, DwarfRegNum<[237]>;
+def Ry237 : AMDILReg<237, "r237">, DwarfRegAlias<Rx237>;
+def Rz237 : AMDILReg<237, "r237">, DwarfRegAlias<Rx237>;
+def Rw237 : AMDILReg<237, "r237">, DwarfRegAlias<Rx237>;
+def Rx238 : AMDILReg<238, "r238">, DwarfRegNum<[238]>;
+def Ry238 : AMDILReg<238, "r238">, DwarfRegAlias<Rx238>;
+def Rz238 : AMDILReg<238, "r238">, DwarfRegAlias<Rx238>;
+def Rw238 : AMDILReg<238, "r238">, DwarfRegAlias<Rx238>;
+def Rx239 : AMDILReg<239, "r239">, DwarfRegNum<[239]>;
+def Ry239 : AMDILReg<239, "r239">, DwarfRegAlias<Rx239>;
+def Rz239 : AMDILReg<239, "r239">, DwarfRegAlias<Rx239>;
+def Rw239 : AMDILReg<239, "r239">, DwarfRegAlias<Rx239>;
+def Rx240 : AMDILReg<240, "r240">, DwarfRegNum<[240]>;
+def Ry240 : AMDILReg<240, "r240">, DwarfRegAlias<Rx240>;
+def Rz240 : AMDILReg<240, "r240">, DwarfRegAlias<Rx240>;
+def Rw240 : AMDILReg<240, "r240">, DwarfRegAlias<Rx240>;
+def Rx241 : AMDILReg<241, "r241">, DwarfRegNum<[241]>;
+def Ry241 : AMDILReg<241, "r241">, DwarfRegAlias<Rx241>;
+def Rz241 : AMDILReg<241, "r241">, DwarfRegAlias<Rx241>;
+def Rw241 : AMDILReg<241, "r241">, DwarfRegAlias<Rx241>;
+def Rx242 : AMDILReg<242, "r242">, DwarfRegNum<[242]>;
+def Ry242 : AMDILReg<242, "r242">, DwarfRegAlias<Rx242>;
+def Rz242 : AMDILReg<242, "r242">, DwarfRegAlias<Rx242>;
+def Rw242 : AMDILReg<242, "r242">, DwarfRegAlias<Rx242>;
+def Rx243 : AMDILReg<243, "r243">, DwarfRegNum<[243]>;
+def Ry243 : AMDILReg<243, "r243">, DwarfRegAlias<Rx243>;
+def Rz243 : AMDILReg<243, "r243">, DwarfRegAlias<Rx243>;
+def Rw243 : AMDILReg<243, "r243">, DwarfRegAlias<Rx243>;
+def Rx244 : AMDILReg<244, "r244">, DwarfRegNum<[244]>;
+def Ry244 : AMDILReg<244, "r244">, DwarfRegAlias<Rx244>;
+def Rz244 : AMDILReg<244, "r244">, DwarfRegAlias<Rx244>;
+def Rw244 : AMDILReg<244, "r244">, DwarfRegAlias<Rx244>;
+def Rx245 : AMDILReg<245, "r245">, DwarfRegNum<[245]>;
+def Ry245 : AMDILReg<245, "r245">, DwarfRegAlias<Rx245>;
+def Rz245 : AMDILReg<245, "r245">, DwarfRegAlias<Rx245>;
+def Rw245 : AMDILReg<245, "r245">, DwarfRegAlias<Rx245>;
+def Rx246 : AMDILReg<246, "r246">, DwarfRegNum<[246]>;
+def Ry246 : AMDILReg<246, "r246">, DwarfRegAlias<Rx246>;
+def Rz246 : AMDILReg<246, "r246">, DwarfRegAlias<Rx246>;
+def Rw246 : AMDILReg<246, "r246">, DwarfRegAlias<Rx246>;
+def Rx247 : AMDILReg<247, "r247">, DwarfRegNum<[247]>;
+def Ry247 : AMDILReg<247, "r247">, DwarfRegAlias<Rx247>;
+def Rz247 : AMDILReg<247, "r247">, DwarfRegAlias<Rx247>;
+def Rw247 : AMDILReg<247, "r247">, DwarfRegAlias<Rx247>;
+def Rx248 : AMDILReg<248, "r248">, DwarfRegNum<[248]>;
+def Ry248 : AMDILReg<248, "r248">, DwarfRegAlias<Rx248>;
+def Rz248 : AMDILReg<248, "r248">, DwarfRegAlias<Rx248>;
+def Rw248 : AMDILReg<248, "r248">, DwarfRegAlias<Rx248>;
+def Rx249 : AMDILReg<249, "r249">, DwarfRegNum<[249]>;
+def Ry249 : AMDILReg<249, "r249">, DwarfRegAlias<Rx249>;
+def Rz249 : AMDILReg<249, "r249">, DwarfRegAlias<Rx249>;
+def Rw249 : AMDILReg<249, "r249">, DwarfRegAlias<Rx249>;
+def Rx250 : AMDILReg<250, "r250">, DwarfRegNum<[250]>;
+def Ry250 : AMDILReg<250, "r250">, DwarfRegAlias<Rx250>;
+def Rz250 : AMDILReg<250, "r250">, DwarfRegAlias<Rx250>;
+def Rw250 : AMDILReg<250, "r250">, DwarfRegAlias<Rx250>;
+def Rx251 : AMDILReg<251, "r251">, DwarfRegNum<[251]>;
+def Ry251 : AMDILReg<251, "r251">, DwarfRegAlias<Rx251>;
+def Rz251 : AMDILReg<251, "r251">, DwarfRegAlias<Rx251>;
+def Rw251 : AMDILReg<251, "r251">, DwarfRegAlias<Rx251>;
+def Rx252 : AMDILReg<252, "r252">, DwarfRegNum<[252]>;
+def Ry252 : AMDILReg<252, "r252">, DwarfRegAlias<Rx252>;
+def Rz252 : AMDILReg<252, "r252">, DwarfRegAlias<Rx252>;
+def Rw252 : AMDILReg<252, "r252">, DwarfRegAlias<Rx252>;
+def Rx253 : AMDILReg<253, "r253">, DwarfRegNum<[253]>;
+def Ry253 : AMDILReg<253, "r253">, DwarfRegAlias<Rx253>;
+def Rz253 : AMDILReg<253, "r253">, DwarfRegAlias<Rx253>;
+def Rw253 : AMDILReg<253, "r253">, DwarfRegAlias<Rx253>;
+def Rx254 : AMDILReg<254, "r254">, DwarfRegNum<[254]>;
+def Ry254 : AMDILReg<254, "r254">, DwarfRegAlias<Rx254>;
+def Rz254 : AMDILReg<254, "r254">, DwarfRegAlias<Rx254>;
+def Rw254 : AMDILReg<254, "r254">, DwarfRegAlias<Rx254>;
+def Rx255 : AMDILReg<255, "r255">, DwarfRegNum<[255]>;
+def Ry255 : AMDILReg<255, "r255">, DwarfRegAlias<Rx255>;
+def Rz255 : AMDILReg<255, "r255">, DwarfRegAlias<Rx255>;
+def Rw255 : AMDILReg<255, "r255">, DwarfRegAlias<Rx255>;
def Rx1000 : AMDILReg<1000, "r1000">, DwarfRegNum<[1000]>;
def Ry1000 : AMDILReg<1000, "r1000">, DwarfRegAlias<Rx1000>;
def Rz1000 : AMDILReg<1000, "r1000">, DwarfRegAlias<Rx1000>;
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterDefsV2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterDefsV2.td?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterDefsV2.td (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterDefsV2.td Wed Sep 12 12:43:34 2012
@@ -393,6 +393,134 @@
def Rzw190 : AMDILRegWithSubReg<190, "r190", [Rz190, Rw190], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx190>;
def Rxy191 : AMDILRegWithSubReg<191, "r191", [Rx191, Ry191], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx191>;
def Rzw191 : AMDILRegWithSubReg<191, "r191", [Rz191, Rw191], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx191>;
+def Rxy192 : AMDILRegWithSubReg<192, "r192", [Rx192, Ry192], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx192>;
+def Rzw192 : AMDILRegWithSubReg<192, "r192", [Rz192, Rw192], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx192>;
+def Rxy193 : AMDILRegWithSubReg<193, "r193", [Rx193, Ry193], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx193>;
+def Rzw193 : AMDILRegWithSubReg<193, "r193", [Rz193, Rw193], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx193>;
+def Rxy194 : AMDILRegWithSubReg<194, "r194", [Rx194, Ry194], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx194>;
+def Rzw194 : AMDILRegWithSubReg<194, "r194", [Rz194, Rw194], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx194>;
+def Rxy195 : AMDILRegWithSubReg<195, "r195", [Rx195, Ry195], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx195>;
+def Rzw195 : AMDILRegWithSubReg<195, "r195", [Rz195, Rw195], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx195>;
+def Rxy196 : AMDILRegWithSubReg<196, "r196", [Rx196, Ry196], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx196>;
+def Rzw196 : AMDILRegWithSubReg<196, "r196", [Rz196, Rw196], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx196>;
+def Rxy197 : AMDILRegWithSubReg<197, "r197", [Rx197, Ry197], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx197>;
+def Rzw197 : AMDILRegWithSubReg<197, "r197", [Rz197, Rw197], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx197>;
+def Rxy198 : AMDILRegWithSubReg<198, "r198", [Rx198, Ry198], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx198>;
+def Rzw198 : AMDILRegWithSubReg<198, "r198", [Rz198, Rw198], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx198>;
+def Rxy199 : AMDILRegWithSubReg<199, "r199", [Rx199, Ry199], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx199>;
+def Rzw199 : AMDILRegWithSubReg<199, "r199", [Rz199, Rw199], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx199>;
+def Rxy200 : AMDILRegWithSubReg<200, "r200", [Rx200, Ry200], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx200>;
+def Rzw200 : AMDILRegWithSubReg<200, "r200", [Rz200, Rw200], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx200>;
+def Rxy201 : AMDILRegWithSubReg<201, "r201", [Rx201, Ry201], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx201>;
+def Rzw201 : AMDILRegWithSubReg<201, "r201", [Rz201, Rw201], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx201>;
+def Rxy202 : AMDILRegWithSubReg<202, "r202", [Rx202, Ry202], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx202>;
+def Rzw202 : AMDILRegWithSubReg<202, "r202", [Rz202, Rw202], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx202>;
+def Rxy203 : AMDILRegWithSubReg<203, "r203", [Rx203, Ry203], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx203>;
+def Rzw203 : AMDILRegWithSubReg<203, "r203", [Rz203, Rw203], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx203>;
+def Rxy204 : AMDILRegWithSubReg<204, "r204", [Rx204, Ry204], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx204>;
+def Rzw204 : AMDILRegWithSubReg<204, "r204", [Rz204, Rw204], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx204>;
+def Rxy205 : AMDILRegWithSubReg<205, "r205", [Rx205, Ry205], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx205>;
+def Rzw205 : AMDILRegWithSubReg<205, "r205", [Rz205, Rw205], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx205>;
+def Rxy206 : AMDILRegWithSubReg<206, "r206", [Rx206, Ry206], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx206>;
+def Rzw206 : AMDILRegWithSubReg<206, "r206", [Rz206, Rw206], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx206>;
+def Rxy207 : AMDILRegWithSubReg<207, "r207", [Rx207, Ry207], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx207>;
+def Rzw207 : AMDILRegWithSubReg<207, "r207", [Rz207, Rw207], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx207>;
+def Rxy208 : AMDILRegWithSubReg<208, "r208", [Rx208, Ry208], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx208>;
+def Rzw208 : AMDILRegWithSubReg<208, "r208", [Rz208, Rw208], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx208>;
+def Rxy209 : AMDILRegWithSubReg<209, "r209", [Rx209, Ry209], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx209>;
+def Rzw209 : AMDILRegWithSubReg<209, "r209", [Rz209, Rw209], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx209>;
+def Rxy210 : AMDILRegWithSubReg<210, "r210", [Rx210, Ry210], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx210>;
+def Rzw210 : AMDILRegWithSubReg<210, "r210", [Rz210, Rw210], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx210>;
+def Rxy211 : AMDILRegWithSubReg<211, "r211", [Rx211, Ry211], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx211>;
+def Rzw211 : AMDILRegWithSubReg<211, "r211", [Rz211, Rw211], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx211>;
+def Rxy212 : AMDILRegWithSubReg<212, "r212", [Rx212, Ry212], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx212>;
+def Rzw212 : AMDILRegWithSubReg<212, "r212", [Rz212, Rw212], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx212>;
+def Rxy213 : AMDILRegWithSubReg<213, "r213", [Rx213, Ry213], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx213>;
+def Rzw213 : AMDILRegWithSubReg<213, "r213", [Rz213, Rw213], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx213>;
+def Rxy214 : AMDILRegWithSubReg<214, "r214", [Rx214, Ry214], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx214>;
+def Rzw214 : AMDILRegWithSubReg<214, "r214", [Rz214, Rw214], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx214>;
+def Rxy215 : AMDILRegWithSubReg<215, "r215", [Rx215, Ry215], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx215>;
+def Rzw215 : AMDILRegWithSubReg<215, "r215", [Rz215, Rw215], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx215>;
+def Rxy216 : AMDILRegWithSubReg<216, "r216", [Rx216, Ry216], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx216>;
+def Rzw216 : AMDILRegWithSubReg<216, "r216", [Rz216, Rw216], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx216>;
+def Rxy217 : AMDILRegWithSubReg<217, "r217", [Rx217, Ry217], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx217>;
+def Rzw217 : AMDILRegWithSubReg<217, "r217", [Rz217, Rw217], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx217>;
+def Rxy218 : AMDILRegWithSubReg<218, "r218", [Rx218, Ry218], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx218>;
+def Rzw218 : AMDILRegWithSubReg<218, "r218", [Rz218, Rw218], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx218>;
+def Rxy219 : AMDILRegWithSubReg<219, "r219", [Rx219, Ry219], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx219>;
+def Rzw219 : AMDILRegWithSubReg<219, "r219", [Rz219, Rw219], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx219>;
+def Rxy220 : AMDILRegWithSubReg<220, "r220", [Rx220, Ry220], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx220>;
+def Rzw220 : AMDILRegWithSubReg<220, "r220", [Rz220, Rw220], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx220>;
+def Rxy221 : AMDILRegWithSubReg<221, "r221", [Rx221, Ry221], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx221>;
+def Rzw221 : AMDILRegWithSubReg<221, "r221", [Rz221, Rw221], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx221>;
+def Rxy222 : AMDILRegWithSubReg<222, "r222", [Rx222, Ry222], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx222>;
+def Rzw222 : AMDILRegWithSubReg<222, "r222", [Rz222, Rw222], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx222>;
+def Rxy223 : AMDILRegWithSubReg<223, "r223", [Rx223, Ry223], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx223>;
+def Rzw223 : AMDILRegWithSubReg<223, "r223", [Rz223, Rw223], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx223>;
+def Rxy224 : AMDILRegWithSubReg<224, "r224", [Rx224, Ry224], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx224>;
+def Rzw224 : AMDILRegWithSubReg<224, "r224", [Rz224, Rw224], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx224>;
+def Rxy225 : AMDILRegWithSubReg<225, "r225", [Rx225, Ry225], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx225>;
+def Rzw225 : AMDILRegWithSubReg<225, "r225", [Rz225, Rw225], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx225>;
+def Rxy226 : AMDILRegWithSubReg<226, "r226", [Rx226, Ry226], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx226>;
+def Rzw226 : AMDILRegWithSubReg<226, "r226", [Rz226, Rw226], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx226>;
+def Rxy227 : AMDILRegWithSubReg<227, "r227", [Rx227, Ry227], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx227>;
+def Rzw227 : AMDILRegWithSubReg<227, "r227", [Rz227, Rw227], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx227>;
+def Rxy228 : AMDILRegWithSubReg<228, "r228", [Rx228, Ry228], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx228>;
+def Rzw228 : AMDILRegWithSubReg<228, "r228", [Rz228, Rw228], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx228>;
+def Rxy229 : AMDILRegWithSubReg<229, "r229", [Rx229, Ry229], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx229>;
+def Rzw229 : AMDILRegWithSubReg<229, "r229", [Rz229, Rw229], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx229>;
+def Rxy230 : AMDILRegWithSubReg<230, "r230", [Rx230, Ry230], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx230>;
+def Rzw230 : AMDILRegWithSubReg<230, "r230", [Rz230, Rw230], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx230>;
+def Rxy231 : AMDILRegWithSubReg<231, "r231", [Rx231, Ry231], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx231>;
+def Rzw231 : AMDILRegWithSubReg<231, "r231", [Rz231, Rw231], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx231>;
+def Rxy232 : AMDILRegWithSubReg<232, "r232", [Rx232, Ry232], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx232>;
+def Rzw232 : AMDILRegWithSubReg<232, "r232", [Rz232, Rw232], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx232>;
+def Rxy233 : AMDILRegWithSubReg<233, "r233", [Rx233, Ry233], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx233>;
+def Rzw233 : AMDILRegWithSubReg<233, "r233", [Rz233, Rw233], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx233>;
+def Rxy234 : AMDILRegWithSubReg<234, "r234", [Rx234, Ry234], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx234>;
+def Rzw234 : AMDILRegWithSubReg<234, "r234", [Rz234, Rw234], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx234>;
+def Rxy235 : AMDILRegWithSubReg<235, "r235", [Rx235, Ry235], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx235>;
+def Rzw235 : AMDILRegWithSubReg<235, "r235", [Rz235, Rw235], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx235>;
+def Rxy236 : AMDILRegWithSubReg<236, "r236", [Rx236, Ry236], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx236>;
+def Rzw236 : AMDILRegWithSubReg<236, "r236", [Rz236, Rw236], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx236>;
+def Rxy237 : AMDILRegWithSubReg<237, "r237", [Rx237, Ry237], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx237>;
+def Rzw237 : AMDILRegWithSubReg<237, "r237", [Rz237, Rw237], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx237>;
+def Rxy238 : AMDILRegWithSubReg<238, "r238", [Rx238, Ry238], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx238>;
+def Rzw238 : AMDILRegWithSubReg<238, "r238", [Rz238, Rw238], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx238>;
+def Rxy239 : AMDILRegWithSubReg<239, "r239", [Rx239, Ry239], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx239>;
+def Rzw239 : AMDILRegWithSubReg<239, "r239", [Rz239, Rw239], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx239>;
+def Rxy240 : AMDILRegWithSubReg<240, "r240", [Rx240, Ry240], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx240>;
+def Rzw240 : AMDILRegWithSubReg<240, "r240", [Rz240, Rw240], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx240>;
+def Rxy241 : AMDILRegWithSubReg<241, "r241", [Rx241, Ry241], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx241>;
+def Rzw241 : AMDILRegWithSubReg<241, "r241", [Rz241, Rw241], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx241>;
+def Rxy242 : AMDILRegWithSubReg<242, "r242", [Rx242, Ry242], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx242>;
+def Rzw242 : AMDILRegWithSubReg<242, "r242", [Rz242, Rw242], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx242>;
+def Rxy243 : AMDILRegWithSubReg<243, "r243", [Rx243, Ry243], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx243>;
+def Rzw243 : AMDILRegWithSubReg<243, "r243", [Rz243, Rw243], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx243>;
+def Rxy244 : AMDILRegWithSubReg<244, "r244", [Rx244, Ry244], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx244>;
+def Rzw244 : AMDILRegWithSubReg<244, "r244", [Rz244, Rw244], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx244>;
+def Rxy245 : AMDILRegWithSubReg<245, "r245", [Rx245, Ry245], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx245>;
+def Rzw245 : AMDILRegWithSubReg<245, "r245", [Rz245, Rw245], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx245>;
+def Rxy246 : AMDILRegWithSubReg<246, "r246", [Rx246, Ry246], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx246>;
+def Rzw246 : AMDILRegWithSubReg<246, "r246", [Rz246, Rw246], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx246>;
+def Rxy247 : AMDILRegWithSubReg<247, "r247", [Rx247, Ry247], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx247>;
+def Rzw247 : AMDILRegWithSubReg<247, "r247", [Rz247, Rw247], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx247>;
+def Rxy248 : AMDILRegWithSubReg<248, "r248", [Rx248, Ry248], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx248>;
+def Rzw248 : AMDILRegWithSubReg<248, "r248", [Rz248, Rw248], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx248>;
+def Rxy249 : AMDILRegWithSubReg<249, "r249", [Rx249, Ry249], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx249>;
+def Rzw249 : AMDILRegWithSubReg<249, "r249", [Rz249, Rw249], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx249>;
+def Rxy250 : AMDILRegWithSubReg<250, "r250", [Rx250, Ry250], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx250>;
+def Rzw250 : AMDILRegWithSubReg<250, "r250", [Rz250, Rw250], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx250>;
+def Rxy251 : AMDILRegWithSubReg<251, "r251", [Rx251, Ry251], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx251>;
+def Rzw251 : AMDILRegWithSubReg<251, "r251", [Rz251, Rw251], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx251>;
+def Rxy252 : AMDILRegWithSubReg<252, "r252", [Rx252, Ry252], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx252>;
+def Rzw252 : AMDILRegWithSubReg<252, "r252", [Rz252, Rw252], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx252>;
+def Rxy253 : AMDILRegWithSubReg<253, "r253", [Rx253, Ry253], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx253>;
+def Rzw253 : AMDILRegWithSubReg<253, "r253", [Rz253, Rw253], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx253>;
+def Rxy254 : AMDILRegWithSubReg<254, "r254", [Rx254, Ry254], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx254>;
+def Rzw254 : AMDILRegWithSubReg<254, "r254", [Rz254, Rw254], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx254>;
+def Rxy255 : AMDILRegWithSubReg<255, "r255", [Rx255, Ry255], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx255>;
+def Rzw255 : AMDILRegWithSubReg<255, "r255", [Rz255, Rw255], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx255>;
def Rxy1000 : AMDILRegWithSubReg<1000, "r1000", [Rx1000, Ry1000], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx1000>;
def Rzw1000 : AMDILRegWithSubReg<1000, "r1000", [Rz1000, Rw1000], [sub_z_comp, sub_w_comp]>, DwarfRegAlias<Rx1000>;
def Rxy1001 : AMDILRegWithSubReg<1001, "r1001", [Rx1001, Ry1001], [sub_x_comp, sub_y_comp]>, DwarfRegAlias<Rx1001>;
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterDefsV4.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterDefsV4.td?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterDefsV4.td (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterDefsV4.td Wed Sep 12 12:43:34 2012
@@ -202,6 +202,70 @@
def R189 : AMDILRegWithSubReg<189, "r189", [Rxy189, Rzw189], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx189>;
def R190 : AMDILRegWithSubReg<190, "r190", [Rxy190, Rzw190], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx190>;
def R191 : AMDILRegWithSubReg<191, "r191", [Rxy191, Rzw191], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx191>;
+def R192 : AMDILRegWithSubReg<192, "r192", [Rxy192, Rzw192], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx192>;
+def R193 : AMDILRegWithSubReg<193, "r193", [Rxy193, Rzw193], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx193>;
+def R194 : AMDILRegWithSubReg<194, "r194", [Rxy194, Rzw194], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx194>;
+def R195 : AMDILRegWithSubReg<195, "r195", [Rxy195, Rzw195], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx195>;
+def R196 : AMDILRegWithSubReg<196, "r196", [Rxy196, Rzw196], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx196>;
+def R197 : AMDILRegWithSubReg<197, "r197", [Rxy197, Rzw197], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx197>;
+def R198 : AMDILRegWithSubReg<198, "r198", [Rxy198, Rzw198], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx198>;
+def R199 : AMDILRegWithSubReg<199, "r199", [Rxy199, Rzw199], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx199>;
+def R200 : AMDILRegWithSubReg<200, "r200", [Rxy200, Rzw200], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx200>;
+def R201 : AMDILRegWithSubReg<201, "r201", [Rxy201, Rzw201], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx201>;
+def R202 : AMDILRegWithSubReg<202, "r202", [Rxy202, Rzw202], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx202>;
+def R203 : AMDILRegWithSubReg<203, "r203", [Rxy203, Rzw203], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx203>;
+def R204 : AMDILRegWithSubReg<204, "r204", [Rxy204, Rzw204], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx204>;
+def R205 : AMDILRegWithSubReg<205, "r205", [Rxy205, Rzw205], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx205>;
+def R206 : AMDILRegWithSubReg<206, "r206", [Rxy206, Rzw206], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx206>;
+def R207 : AMDILRegWithSubReg<207, "r207", [Rxy207, Rzw207], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx207>;
+def R208 : AMDILRegWithSubReg<208, "r208", [Rxy208, Rzw208], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx208>;
+def R209 : AMDILRegWithSubReg<209, "r209", [Rxy209, Rzw209], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx209>;
+def R210 : AMDILRegWithSubReg<210, "r210", [Rxy210, Rzw210], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx210>;
+def R211 : AMDILRegWithSubReg<211, "r211", [Rxy211, Rzw211], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx211>;
+def R212 : AMDILRegWithSubReg<212, "r212", [Rxy212, Rzw212], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx212>;
+def R213 : AMDILRegWithSubReg<213, "r213", [Rxy213, Rzw213], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx213>;
+def R214 : AMDILRegWithSubReg<214, "r214", [Rxy214, Rzw214], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx214>;
+def R215 : AMDILRegWithSubReg<215, "r215", [Rxy215, Rzw215], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx215>;
+def R216 : AMDILRegWithSubReg<216, "r216", [Rxy216, Rzw216], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx216>;
+def R217 : AMDILRegWithSubReg<217, "r217", [Rxy217, Rzw217], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx217>;
+def R218 : AMDILRegWithSubReg<218, "r218", [Rxy218, Rzw218], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx218>;
+def R219 : AMDILRegWithSubReg<219, "r219", [Rxy219, Rzw219], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx219>;
+def R220 : AMDILRegWithSubReg<220, "r220", [Rxy220, Rzw220], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx220>;
+def R221 : AMDILRegWithSubReg<221, "r221", [Rxy221, Rzw221], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx221>;
+def R222 : AMDILRegWithSubReg<222, "r222", [Rxy222, Rzw222], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx222>;
+def R223 : AMDILRegWithSubReg<223, "r223", [Rxy223, Rzw223], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx223>;
+def R224 : AMDILRegWithSubReg<224, "r224", [Rxy224, Rzw224], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx224>;
+def R225 : AMDILRegWithSubReg<225, "r225", [Rxy225, Rzw225], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx225>;
+def R226 : AMDILRegWithSubReg<226, "r226", [Rxy226, Rzw226], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx226>;
+def R227 : AMDILRegWithSubReg<227, "r227", [Rxy227, Rzw227], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx227>;
+def R228 : AMDILRegWithSubReg<228, "r228", [Rxy228, Rzw228], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx228>;
+def R229 : AMDILRegWithSubReg<229, "r229", [Rxy229, Rzw229], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx229>;
+def R230 : AMDILRegWithSubReg<230, "r230", [Rxy230, Rzw230], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx230>;
+def R231 : AMDILRegWithSubReg<231, "r231", [Rxy231, Rzw231], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx231>;
+def R232 : AMDILRegWithSubReg<232, "r232", [Rxy232, Rzw232], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx232>;
+def R233 : AMDILRegWithSubReg<233, "r233", [Rxy233, Rzw233], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx233>;
+def R234 : AMDILRegWithSubReg<234, "r234", [Rxy234, Rzw234], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx234>;
+def R235 : AMDILRegWithSubReg<235, "r235", [Rxy235, Rzw235], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx235>;
+def R236 : AMDILRegWithSubReg<236, "r236", [Rxy236, Rzw236], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx236>;
+def R237 : AMDILRegWithSubReg<237, "r237", [Rxy237, Rzw237], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx237>;
+def R238 : AMDILRegWithSubReg<238, "r238", [Rxy238, Rzw238], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx238>;
+def R239 : AMDILRegWithSubReg<239, "r239", [Rxy239, Rzw239], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx239>;
+def R240 : AMDILRegWithSubReg<240, "r240", [Rxy240, Rzw240], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx240>;
+def R241 : AMDILRegWithSubReg<241, "r241", [Rxy241, Rzw241], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx241>;
+def R242 : AMDILRegWithSubReg<242, "r242", [Rxy242, Rzw242], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx242>;
+def R243 : AMDILRegWithSubReg<243, "r243", [Rxy243, Rzw243], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx243>;
+def R244 : AMDILRegWithSubReg<244, "r244", [Rxy244, Rzw244], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx244>;
+def R245 : AMDILRegWithSubReg<245, "r245", [Rxy245, Rzw245], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx245>;
+def R246 : AMDILRegWithSubReg<246, "r246", [Rxy246, Rzw246], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx246>;
+def R247 : AMDILRegWithSubReg<247, "r247", [Rxy247, Rzw247], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx247>;
+def R248 : AMDILRegWithSubReg<248, "r248", [Rxy248, Rzw248], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx248>;
+def R249 : AMDILRegWithSubReg<249, "r249", [Rxy249, Rzw249], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx249>;
+def R250 : AMDILRegWithSubReg<250, "r250", [Rxy250, Rzw250], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx250>;
+def R251 : AMDILRegWithSubReg<251, "r251", [Rxy251, Rzw251], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx251>;
+def R252 : AMDILRegWithSubReg<252, "r252", [Rxy252, Rzw252], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx252>;
+def R253 : AMDILRegWithSubReg<253, "r253", [Rxy253, Rzw253], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx253>;
+def R254 : AMDILRegWithSubReg<254, "r254", [Rxy254, Rzw254], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx254>;
+def R255 : AMDILRegWithSubReg<255, "r255", [Rxy255, Rzw255], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx255>;
def R1000 : AMDILRegWithSubReg<1000, "r1000", [Rxy1000, Rzw1000], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx1000>;
def R1001 : AMDILRegWithSubReg<1001, "r1001", [Rxy1001, Rzw1001], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx1001>;
def R1002 : AMDILRegWithSubReg<1002, "r1002", [Rxy1002, Rzw1002], [sub_xy_comp, sub_zw_comp]>, DwarfRegAlias<Rx1002>;
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterInfo.cpp?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterInfo.cpp (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterInfo.cpp Wed Sep 12 12:43:34 2012
@@ -20,7 +20,6 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Support/FormattedStream.h"
-
using namespace llvm;
AMDILRegisterInfo::AMDILRegisterInfo(AMDILTargetMachine &tm,
@@ -31,7 +30,6 @@
baseOffset = 0;
nextFuncOffset = 0;
}
-
const uint16_t*
AMDILRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const
{
@@ -43,7 +41,6 @@
//TODO(getCalleeSavedRegs);
return CalleeSavedRegs;
}
-
BitVector
AMDILRegisterInfo::getReservedRegs(const MachineFunction &MF) const
{
@@ -81,6 +78,9 @@
Reserved.set(AMDIL::CFG9);
Reserved.set(AMDIL::CFG10);
+ // Set PRINTF register as reserved.
+ Reserved.set(AMDIL::PRINTF);
+
// Reserve the live-ins for the function.
MachineBasicBlock::livein_iterator LII = MF.begin()->livein_begin();
MachineBasicBlock::livein_iterator LIE = MF.begin()->livein_end();
@@ -90,7 +90,6 @@
}
return Reserved;
}
-
const TargetRegisterClass* const*
AMDILRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const
{
@@ -107,7 +106,6 @@
{
MBB.erase(I);
}
-
// For each frame index we find, we store the offset in the stack which is
// being pushed back into the global buffer. The offset into the stack where
// the value is stored is copied into a new register and the frame index is
@@ -126,7 +124,7 @@
if (!MI.getOperand(x).isFI()) {
continue;
}
- bool def = isStoreInst(TM, &MI);
+ bool def = isPtrStoreInst(&MI);
int FrameIndex = MI.getOperand(x).getIndex();
int64_t Offset = MFI->getObjectOffset(FrameIndex);
//int64_t Size = MF.getFrameInfo()->getObjectSize(FrameIndex);
@@ -135,22 +133,37 @@
// instead of just a pointer. If we are size 4 then we can
// just do register copies since we don't need to worry about
// indexing dynamically
- MachineInstr *nMI = MF.CreateMachineInstr(
- TII.get(AMDIL::LOADCONST_i32), MI.getDebugLoc());
- nMI->addOperand(MachineOperand::CreateReg(AMDIL::DFP, true));
- nMI->addOperand(
- MachineOperand::CreateImm(Offset));
- MI.getParent()->insert(II, nMI);
- if (MI.getOperand(x).isReg() == false) {
- MI.getOperand(x).ChangeToRegister(
- nMI->getOperand(0).getReg(), def);
+ // FIXME: This needs to embed the literals directly instead of
+ // using DFP.
+ unsigned reg = (def && !x) ? AMDIL::T5 : AMDIL::DFP;
+ if (MI.getOpcode() != AMDIL::LOADFIi32) {
+ MachineInstr *nMI = MF.CreateMachineInstr(
+ TII.get(AMDIL::LOADFIi32), MI.getDebugLoc());
+ nMI->addOperand(MachineOperand::CreateReg(reg, true));
+ nMI->addOperand(
+ MachineOperand::CreateImm(Offset));
+ MI.getParent()->insert(II, nMI);
+ if (MI.getOperand(x).isReg() == false) {
+ MI.getOperand(x).ChangeToRegister(
+ nMI->getOperand(0).getReg(), false);
+ } else {
+ MI.getOperand(x).setReg(
+ nMI->getOperand(0).getReg());
+ }
} else {
- MI.getOperand(x).setReg(
- nMI->getOperand(0).getReg());
+ MI.getOperand(1).ChangeToImmediate(Offset);
}
}
}
-
+const TargetRegisterClass *
+AMDILRegisterInfo::getPointerRegClass(const MachineFunction &MF,
+ unsigned Kind) const
+{
+ assert(!Kind && "Unknown register class pointer specified!");
+ return TM.getSubtargetImpl()->is64bit()
+ ? &AMDIL::GPRI64RegClass
+ : &AMDIL::GPRI32RegClass;
+}
void
AMDILRegisterInfo::processFunctionBeforeFrameFinalized(
MachineFunction &MF) const
@@ -178,34 +191,28 @@
{
return AMDIL::RA;
}
-
unsigned int
AMDILRegisterInfo::getFrameRegister(const MachineFunction &MF) const
{
return AMDIL::FP;
}
-
unsigned int
AMDILRegisterInfo::getEHExceptionRegister() const
{
assert(0 && "What is the exception register");
return 0;
}
-
unsigned int
AMDILRegisterInfo::getEHHandlerRegister() const
{
assert(0 && "What is the exception handler register");
return 0;
}
-
-
int64_t
AMDILRegisterInfo::getStackSize() const
{
return nextFuncOffset - baseOffset;
}
-
#define GET_REGINFO_MC_DESC
#define GET_REGINFO_TARGET_DESC
#include "AMDILGenRegisterInfo.inc"
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterInfo.h?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterInfo.h (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterInfo.h Wed Sep 12 12:43:34 2012
@@ -20,25 +20,27 @@
#include "llvm/Target/TargetRegisterInfo.h"
#define GET_REGINFO_HEADER
#include "AMDILGenRegisterInfo.inc"
+
+#include "llvm/Config/config.h"
+
// See header file for explanation
namespace llvm
{
-
class AMDILTargetMachine;
class TargetInstrInfo;
class Type;
/// DWARFFlavour - Flavour of dwarf regnumbers
///
-namespace DWARFFlavour
-{
+namespace DWARFFlavour {
enum {
AMDIL_Generic = 0
};
}
-struct AMDILRegisterInfo : public AMDILGenRegisterInfo {
+struct AMDILRegisterInfo : public AMDILGenRegisterInfo
+{
AMDILTargetMachine &TM;
const TargetInstrInfo &TII;
@@ -51,6 +53,9 @@
getCalleeSavedRegClasses(
const MachineFunction *MF = 0) const;
+ virtual const TargetRegisterClass *
+ getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const;
+
BitVector
getReservedRegs(const MachineFunction &MF) const;
@@ -80,7 +85,6 @@
unsigned int
getEHHandlerRegister() const;
-
int64_t
getStackSize() const;
#if 0
@@ -89,7 +93,7 @@
return true;
}
bool
- requireFrameIndexScavenging(const MachineFunction&)const {
+ requireFrameIndexScavenging(const MachineFunction&) const {
return true;
}
bool
@@ -98,11 +102,10 @@
}
#endif
-private:
- mutable int64_t baseOffset;
- mutable int64_t nextFuncOffset;
+ private:
+ mutable int64_t baseOffset;
+ mutable int64_t nextFuncOffset;
};
-
} // end namespace llvm
#endif // AMDILREGISTERINFO_H_
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterInfo.td?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterInfo.td (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterInfo.td Wed Sep 12 12:43:34 2012
@@ -51,6 +51,7 @@
// r1027 is used as mem register
// r1026 is used as the return address register.
// r1030-r1039 are reserved for AMDILCFGStructurizer.
+// r1040 is reserved for printf implementation.
//def R1025 : AMDILReg<1025, "r1025">, DwarfRegNum<[1025]>;
//def R1024 : AMDILReg<1024, "r1024">, DwarfRegNum<[1024]>;
//def R1023 : AMDILReg<1023, "r1023">, DwarfRegNum<[1023]>;
@@ -81,6 +82,7 @@
def CFG8 : AMDILReg<5048, "r1037">, DwarfRegNum<[1037]>;
def CFG9 : AMDILReg<5052, "r1038">, DwarfRegNum<[1038]>;
def CFG10 : AMDILReg<5056, "r1039">, DwarfRegNum<[1039]>;
+def PRINTF : AMDILReg<5060, "r1040">, DwarfRegNum<[1040]>;
def GPRI8 : RegisterClass<"AMDIL", [i8], 8,
( add include "AMDILRegisterUsesScalar.td"
@@ -101,7 +103,7 @@
}
def GPRI32 : RegisterClass<"AMDIL", [i32], 32,
( add include "AMDILRegisterUsesScalar.td"
- , FP, RA, SDP, MEMx
+ , FP, RA, SDP, T5, MEMx
)>
{
let AltOrders = [(add (sequence "Rx%u", 65, 191), (sequence "Ry%u", 65, 191), (sequence "Rz%u", 65, 191), (sequence "Rw%u", 65, 191))];
@@ -258,7 +260,7 @@
}
def GPRV4I32 : RegisterClass<"AMDIL", [v4i32], 128,
( add include "AMDILRegisterUsesV4.td"
- , SP, T1, T2, T3, T4, T5, MEM
+ , SP, T1, T2, T3, T4, MEM
)>
{
let AltOrders = [(add (sequence "R%u", 65, 191))];
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterUsesScalar.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterUsesScalar.td?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterUsesScalar.td (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterUsesScalar.td Wed Sep 12 12:43:34 2012
@@ -11,4 +11,4 @@
//
//===----------------------------------------------------------------------===//
-Rx1, Ry1, Rz1, Rw1, Rx2, Ry2, Rz2, Rw2, Rx3, Ry3, Rz3, Rw3, Rx4, Ry4, Rz4, Rw4, Rx5, Ry5, Rz5, Rw5, Rx6, Ry6, Rz6, Rw6, Rx7, Ry7, Rz7, Rw7, Rx8, Ry8, Rz8, Rw8, Rx9, Ry9, Rz9, Rw9, Rx10, Ry10, Rz10, Rw10, Rx11, Ry11, Rz11, Rw11, Rx12, Ry12, Rz12, Rw12, Rx13, Ry13, Rz13, Rw13, Rx14, Ry14, Rz14, Rw14, Rx15, Ry15, Rz15, Rw15, Rx16, Ry16, Rz16, Rw16, Rx17, Ry17, Rz17, Rw17, Rx18, Ry18, Rz18, Rw18, Rx19, Ry19, Rz19, Rw19, Rx20, Ry20, Rz20, Rw20, Rx21, Ry21, Rz21, Rw21, Rx22, Ry22, Rz22, Rw22, Rx23, Ry23, Rz23, Rw23, Rx24, Ry24, Rz24, Rw24, Rx25, Ry25, Rz25, Rw25, Rx26, Ry26, Rz26, Rw26, Rx27, Ry27, Rz27, Rw27, Rx28, Ry28, Rz28, Rw28, Rx29, Ry29, Rz29, Rw29, Rx30, Ry30, Rz30, Rw30, Rx31, Ry31, Rz31, Rw31, Rx32, Ry32, Rz32, Rw32, Rx33, Ry33, Rz33, Rw33, Rx34, Ry34, Rz34, Rw34, Rx35, Ry35, Rz35, Rw35, Rx36, Ry36, Rz36, Rw36, Rx37, Ry37, Rz37, Rw37, Rx38, Ry38, Rz38, Rw38, Rx39, Ry39, Rz39, Rw39, Rx40, Ry40, Rz40, Rw40, Rx41, Ry41, Rz41, Rw41, Rx42, Ry42, Rz42, Rw42, Rx43, Ry43, Rz43,
Rw43, Rx44, Ry44, Rz44, Rw44, Rx45, Ry45, Rz45, Rw45, Rx46, Ry46, Rz46, Rw46, Rx47, Ry47, Rz47, Rw47, Rx48, Ry48, Rz48, Rw48, Rx49, Ry49, Rz49, Rw49, Rx50, Ry50, Rz50, Rw50, Rx51, Ry51, Rz51, Rw51, Rx52, Ry52, Rz52, Rw52, Rx53, Ry53, Rz53, Rw53, Rx54, Ry54, Rz54, Rw54, Rx55, Ry55, Rz55, Rw55, Rx56, Ry56, Rz56, Rw56, Rx57, Ry57, Rz57, Rw57, Rx58, Ry58, Rz58, Rw58, Rx59, Ry59, Rz59, Rw59, Rx60, Ry60, Rz60, Rw60, Rx61, Ry61, Rz61, Rw61, Rx62, Ry62, Rz62, Rw62, Rx63, Ry63, Rz63, Rw63, Rx64, Ry64, Rz64, Rw64, Rx65, Ry65, Rz65, Rw65, Rx66, Ry66, Rz66, Rw66, Rx67, Ry67, Rz67, Rw67, Rx68, Ry68, Rz68, Rw68, Rx69, Ry69, Rz69, Rw69, Rx70, Ry70, Rz70, Rw70, Rx71, Ry71, Rz71, Rw71, Rx72, Ry72, Rz72, Rw72, Rx73, Ry73, Rz73, Rw73, Rx74, Ry74, Rz74, Rw74, Rx75, Ry75, Rz75, Rw75, Rx76, Ry76, Rz76, Rw76, Rx77, Ry77, Rz77, Rw77, Rx78, Ry78, Rz78, Rw78, Rx79, Ry79, Rz79, Rw79, Rx80, Ry80, Rz80, Rw80, Rx81, Ry81, Rz81, Rw81, Rx82, Ry82, Rz82, Rw82, Rx83, Ry83, Rz83, Rw83, Rx84, Ry84, Rz84, Rw84
, Rx85, Ry85, Rz85, Rw85, Rx86, Ry86, Rz86, Rw86, Rx87, Ry87, Rz87, Rw87, Rx88, Ry88, Rz88, Rw88, Rx89, Ry89, Rz89, Rw89, Rx90, Ry90, Rz90, Rw90, Rx91, Ry91, Rz91, Rw91, Rx92, Ry92, Rz92, Rw92, Rx93, Ry93, Rz93, Rw93, Rx94, Ry94, Rz94, Rw94, Rx95, Ry95, Rz95, Rw95, Rx96, Ry96, Rz96, Rw96, Rx97, Ry97, Rz97, Rw97, Rx98, Ry98, Rz98, Rw98, Rx99, Ry99, Rz99, Rw99, Rx100, Ry100, Rz100, Rw100, Rx101, Ry101, Rz101, Rw101, Rx102, Ry102, Rz102, Rw102, Rx103, Ry103, Rz103, Rw103, Rx104, Ry104, Rz104, Rw104, Rx105, Ry105, Rz105, Rw105, Rx106, Ry106, Rz106, Rw106, Rx107, Ry107, Rz107, Rw107, Rx108, Ry108, Rz108, Rw108, Rx109, Ry109, Rz109, Rw109, Rx110, Ry110, Rz110, Rw110, Rx111, Ry111, Rz111, Rw111, Rx112, Ry112, Rz112, Rw112, Rx113, Ry113, Rz113, Rw113, Rx114, Ry114, Rz114, Rw114, Rx115, Ry115, Rz115, Rw115, Rx116, Ry116, Rz116, Rw116, Rx117, Ry117, Rz117, Rw117, Rx118, Ry118, Rz118, Rw118, Rx119, Ry119, Rz119, Rw119, Rx120, Ry120, Rz120, Rw120, Rx121, Ry121, Rz121, Rw121, Rx122, Ry12
2, Rz122, Rw122, Rx123, Ry123, Rz123, Rw123, Rx124, Ry124, Rz124, Rw124, Rx125, Ry125, Rz125, Rw125, Rx126, Ry126, Rz126, Rw126, Rx127, Ry127, Rz127, Rw127, Rx128, Ry128, Rz128, Rw128, Rx129, Ry129, Rz129, Rw129, Rx130, Ry130, Rz130, Rw130, Rx131, Ry131, Rz131, Rw131, Rx132, Ry132, Rz132, Rw132, Rx133, Ry133, Rz133, Rw133, Rx134, Ry134, Rz134, Rw134, Rx135, Ry135, Rz135, Rw135, Rx136, Ry136, Rz136, Rw136, Rx137, Ry137, Rz137, Rw137, Rx138, Ry138, Rz138, Rw138, Rx139, Ry139, Rz139, Rw139, Rx140, Ry140, Rz140, Rw140, Rx141, Ry141, Rz141, Rw141, Rx142, Ry142, Rz142, Rw142, Rx143, Ry143, Rz143, Rw143, Rx144, Ry144, Rz144, Rw144, Rx145, Ry145, Rz145, Rw145, Rx146, Ry146, Rz146, Rw146, Rx147, Ry147, Rz147, Rw147, Rx148, Ry148, Rz148, Rw148, Rx149, Ry149, Rz149, Rw149, Rx150, Ry150, Rz150, Rw150, Rx151, Ry151, Rz151, Rw151, Rx152, Ry152, Rz152, Rw152, Rx153, Ry153, Rz153, Rw153, Rx154, Ry154, Rz154, Rw154, Rx155, Ry155, Rz155, Rw155, Rx156, Ry156, Rz156, Rw156, Rx157, Ry157, Rz157,
Rw157, Rx158, Ry158, Rz158, Rw158, Rx159, Ry159, Rz159, Rw159, Rx160, Ry160, Rz160, Rw160, Rx161, Ry161, Rz161, Rw161, Rx162, Ry162, Rz162, Rw162, Rx163, Ry163, Rz163, Rw163, Rx164, Ry164, Rz164, Rw164, Rx165, Ry165, Rz165, Rw165, Rx166, Ry166, Rz166, Rw166, Rx167, Ry167, Rz167, Rw167, Rx168, Ry168, Rz168, Rw168, Rx169, Ry169, Rz169, Rw169, Rx170, Ry170, Rz170, Rw170, Rx171, Ry171, Rz171, Rw171, Rx172, Ry172, Rz172, Rw172, Rx173, Ry173, Rz173, Rw173, Rx174, Ry174, Rz174, Rw174, Rx175, Ry175, Rz175, Rw175, Rx176, Ry176, Rz176, Rw176, Rx177, Ry177, Rz177, Rw177, Rx178, Ry178, Rz178, Rw178, Rx179, Ry179, Rz179, Rw179, Rx180, Ry180, Rz180, Rw180, Rx181, Ry181, Rz181, Rw181, Rx182, Ry182, Rz182, Rw182, Rx183, Ry183, Rz183, Rw183, Rx184, Ry184, Rz184, Rw184, Rx185, Ry185, Rz185, Rw185, Rx186, Ry186, Rz186, Rw186, Rx187, Ry187, Rz187, Rw187, Rx188, Ry188, Rz188, Rw188, Rx189, Ry189, Rz189, Rw189, Rx190, Ry190, Rz190, Rw190, Rx191, Ry191, Rz191, Rw191, Rx1000, Ry1000, Rz1000, Rw100
0, Rx1001, Ry1001, Rz1001, Rw1001, Rx1002, Ry1002, Rz1002, Rw1002, Rx1003, Ry1003, Rz1003, Rw1003, Rx1004, Ry1004, Rz1004, Rw1004, Rx1005, Ry1005, Rz1005, Rw1005, Rx1006, Ry1006, Rz1006, Rw1006, Rx1007, Ry1007, Rz1007, Rw1007, Rx1008, Ry1008, Rz1008, Rw1008, Rx1009, Ry1009, Rz1009, Rw1009, Rx1010, Ry1010, Rz1010, Rw1010, Rx1011, Ry1011, Rz1011, Rw1011, Rx1012, Ry1012, Rz1012, Rw1012
\ No newline at end of file
+Rx1, Ry1, Rz1, Rw1, Rx2, Ry2, Rz2, Rw2, Rx3, Ry3, Rz3, Rw3, Rx4, Ry4, Rz4, Rw4, Rx5, Ry5, Rz5, Rw5, Rx6, Ry6, Rz6, Rw6, Rx7, Ry7, Rz7, Rw7, Rx8, Ry8, Rz8, Rw8, Rx9, Ry9, Rz9, Rw9, Rx10, Ry10, Rz10, Rw10, Rx11, Ry11, Rz11, Rw11, Rx12, Ry12, Rz12, Rw12, Rx13, Ry13, Rz13, Rw13, Rx14, Ry14, Rz14, Rw14, Rx15, Ry15, Rz15, Rw15, Rx16, Ry16, Rz16, Rw16, Rx17, Ry17, Rz17, Rw17, Rx18, Ry18, Rz18, Rw18, Rx19, Ry19, Rz19, Rw19, Rx20, Ry20, Rz20, Rw20, Rx21, Ry21, Rz21, Rw21, Rx22, Ry22, Rz22, Rw22, Rx23, Ry23, Rz23, Rw23, Rx24, Ry24, Rz24, Rw24, Rx25, Ry25, Rz25, Rw25, Rx26, Ry26, Rz26, Rw26, Rx27, Ry27, Rz27, Rw27, Rx28, Ry28, Rz28, Rw28, Rx29, Ry29, Rz29, Rw29, Rx30, Ry30, Rz30, Rw30, Rx31, Ry31, Rz31, Rw31, Rx32, Ry32, Rz32, Rw32, Rx33, Ry33, Rz33, Rw33, Rx34, Ry34, Rz34, Rw34, Rx35, Ry35, Rz35, Rw35, Rx36, Ry36, Rz36, Rw36, Rx37, Ry37, Rz37, Rw37, Rx38, Ry38, Rz38, Rw38, Rx39, Ry39, Rz39, Rw39, Rx40, Ry40, Rz40, Rw40, Rx41, Ry41, Rz41, Rw41, Rx42, Ry42, Rz42, Rw42, Rx43, Ry43, Rz43,
Rw43, Rx44, Ry44, Rz44, Rw44, Rx45, Ry45, Rz45, Rw45, Rx46, Ry46, Rz46, Rw46, Rx47, Ry47, Rz47, Rw47, Rx48, Ry48, Rz48, Rw48, Rx49, Ry49, Rz49, Rw49, Rx50, Ry50, Rz50, Rw50, Rx51, Ry51, Rz51, Rw51, Rx52, Ry52, Rz52, Rw52, Rx53, Ry53, Rz53, Rw53, Rx54, Ry54, Rz54, Rw54, Rx55, Ry55, Rz55, Rw55, Rx56, Ry56, Rz56, Rw56, Rx57, Ry57, Rz57, Rw57, Rx58, Ry58, Rz58, Rw58, Rx59, Ry59, Rz59, Rw59, Rx60, Ry60, Rz60, Rw60, Rx61, Ry61, Rz61, Rw61, Rx62, Ry62, Rz62, Rw62, Rx63, Ry63, Rz63, Rw63, Rx64, Ry64, Rz64, Rw64, Rx65, Ry65, Rz65, Rw65, Rx66, Ry66, Rz66, Rw66, Rx67, Ry67, Rz67, Rw67, Rx68, Ry68, Rz68, Rw68, Rx69, Ry69, Rz69, Rw69, Rx70, Ry70, Rz70, Rw70, Rx71, Ry71, Rz71, Rw71, Rx72, Ry72, Rz72, Rw72, Rx73, Ry73, Rz73, Rw73, Rx74, Ry74, Rz74, Rw74, Rx75, Ry75, Rz75, Rw75, Rx76, Ry76, Rz76, Rw76, Rx77, Ry77, Rz77, Rw77, Rx78, Ry78, Rz78, Rw78, Rx79, Ry79, Rz79, Rw79, Rx80, Ry80, Rz80, Rw80, Rx81, Ry81, Rz81, Rw81, Rx82, Ry82, Rz82, Rw82, Rx83, Ry83, Rz83, Rw83, Rx84, Ry84, Rz84, Rw84
, Rx85, Ry85, Rz85, Rw85, Rx86, Ry86, Rz86, Rw86, Rx87, Ry87, Rz87, Rw87, Rx88, Ry88, Rz88, Rw88, Rx89, Ry89, Rz89, Rw89, Rx90, Ry90, Rz90, Rw90, Rx91, Ry91, Rz91, Rw91, Rx92, Ry92, Rz92, Rw92, Rx93, Ry93, Rz93, Rw93, Rx94, Ry94, Rz94, Rw94, Rx95, Ry95, Rz95, Rw95, Rx96, Ry96, Rz96, Rw96, Rx97, Ry97, Rz97, Rw97, Rx98, Ry98, Rz98, Rw98, Rx99, Ry99, Rz99, Rw99, Rx100, Ry100, Rz100, Rw100, Rx101, Ry101, Rz101, Rw101, Rx102, Ry102, Rz102, Rw102, Rx103, Ry103, Rz103, Rw103, Rx104, Ry104, Rz104, Rw104, Rx105, Ry105, Rz105, Rw105, Rx106, Ry106, Rz106, Rw106, Rx107, Ry107, Rz107, Rw107, Rx108, Ry108, Rz108, Rw108, Rx109, Ry109, Rz109, Rw109, Rx110, Ry110, Rz110, Rw110, Rx111, Ry111, Rz111, Rw111, Rx112, Ry112, Rz112, Rw112, Rx113, Ry113, Rz113, Rw113, Rx114, Ry114, Rz114, Rw114, Rx115, Ry115, Rz115, Rw115, Rx116, Ry116, Rz116, Rw116, Rx117, Ry117, Rz117, Rw117, Rx118, Ry118, Rz118, Rw118, Rx119, Ry119, Rz119, Rw119, Rx120, Ry120, Rz120, Rw120, Rx121, Ry121, Rz121, Rw121, Rx122, Ry12
2, Rz122, Rw122, Rx123, Ry123, Rz123, Rw123, Rx124, Ry124, Rz124, Rw124, Rx125, Ry125, Rz125, Rw125, Rx126, Ry126, Rz126, Rw126, Rx127, Ry127, Rz127, Rw127, Rx128, Ry128, Rz128, Rw128, Rx129, Ry129, Rz129, Rw129, Rx130, Ry130, Rz130, Rw130, Rx131, Ry131, Rz131, Rw131, Rx132, Ry132, Rz132, Rw132, Rx133, Ry133, Rz133, Rw133, Rx134, Ry134, Rz134, Rw134, Rx135, Ry135, Rz135, Rw135, Rx136, Ry136, Rz136, Rw136, Rx137, Ry137, Rz137, Rw137, Rx138, Ry138, Rz138, Rw138, Rx139, Ry139, Rz139, Rw139, Rx140, Ry140, Rz140, Rw140, Rx141, Ry141, Rz141, Rw141, Rx142, Ry142, Rz142, Rw142, Rx143, Ry143, Rz143, Rw143, Rx144, Ry144, Rz144, Rw144, Rx145, Ry145, Rz145, Rw145, Rx146, Ry146, Rz146, Rw146, Rx147, Ry147, Rz147, Rw147, Rx148, Ry148, Rz148, Rw148, Rx149, Ry149, Rz149, Rw149, Rx150, Ry150, Rz150, Rw150, Rx151, Ry151, Rz151, Rw151, Rx152, Ry152, Rz152, Rw152, Rx153, Ry153, Rz153, Rw153, Rx154, Ry154, Rz154, Rw154, Rx155, Ry155, Rz155, Rw155, Rx156, Ry156, Rz156, Rw156, Rx157, Ry157, Rz157,
Rw157, Rx158, Ry158, Rz158, Rw158, Rx159, Ry159, Rz159, Rw159, Rx160, Ry160, Rz160, Rw160, Rx161, Ry161, Rz161, Rw161, Rx162, Ry162, Rz162, Rw162, Rx163, Ry163, Rz163, Rw163, Rx164, Ry164, Rz164, Rw164, Rx165, Ry165, Rz165, Rw165, Rx166, Ry166, Rz166, Rw166, Rx167, Ry167, Rz167, Rw167, Rx168, Ry168, Rz168, Rw168, Rx169, Ry169, Rz169, Rw169, Rx170, Ry170, Rz170, Rw170, Rx171, Ry171, Rz171, Rw171, Rx172, Ry172, Rz172, Rw172, Rx173, Ry173, Rz173, Rw173, Rx174, Ry174, Rz174, Rw174, Rx175, Ry175, Rz175, Rw175, Rx176, Ry176, Rz176, Rw176, Rx177, Ry177, Rz177, Rw177, Rx178, Ry178, Rz178, Rw178, Rx179, Ry179, Rz179, Rw179, Rx180, Ry180, Rz180, Rw180, Rx181, Ry181, Rz181, Rw181, Rx182, Ry182, Rz182, Rw182, Rx183, Ry183, Rz183, Rw183, Rx184, Ry184, Rz184, Rw184, Rx185, Ry185, Rz185, Rw185, Rx186, Ry186, Rz186, Rw186, Rx187, Ry187, Rz187, Rw187, Rx188, Ry188, Rz188, Rw188, Rx189, Ry189, Rz189, Rw189, Rx190, Ry190, Rz190, Rw190, Rx191, Ry191, Rz191, Rw191, Rx192, Ry192, Rz192, Rw192, R
x193, Ry193, Rz193, Rw193, Rx194, Ry194, Rz194, Rw194, Rx195, Ry195, Rz195, Rw195, Rx196, Ry196, Rz196, Rw196, Rx197, Ry197, Rz197, Rw197, Rx198, Ry198, Rz198, Rw198, Rx199, Ry199, Rz199, Rw199, Rx200, Ry200, Rz200, Rw200, Rx201, Ry201, Rz201, Rw201, Rx202, Ry202, Rz202, Rw202, Rx203, Ry203, Rz203, Rw203, Rx204, Ry204, Rz204, Rw204, Rx205, Ry205, Rz205, Rw205, Rx206, Ry206, Rz206, Rw206, Rx207, Ry207, Rz207, Rw207, Rx208, Ry208, Rz208, Rw208, Rx209, Ry209, Rz209, Rw209, Rx210, Ry210, Rz210, Rw210, Rx211, Ry211, Rz211, Rw211, Rx212, Ry212, Rz212, Rw212, Rx213, Ry213, Rz213, Rw213, Rx214, Ry214, Rz214, Rw214, Rx215, Ry215, Rz215, Rw215, Rx216, Ry216, Rz216, Rw216, Rx217, Ry217, Rz217, Rw217, Rx218, Ry218, Rz218, Rw218, Rx219, Ry219, Rz219, Rw219, Rx220, Ry220, Rz220, Rw220, Rx221, Ry221, Rz221, Rw221, Rx222, Ry222, Rz222, Rw222, Rx223, Ry223, Rz223, Rw223, Rx224, Ry224, Rz224, Rw224, Rx225, Ry225, Rz225, Rw225, Rx226, Ry226, Rz226, Rw226, Rx227, Ry227, Rz227, Rw227, Rx228, Ry2
28, Rz228, Rw228, Rx229, Ry229, Rz229, Rw229, Rx230, Ry230, Rz230, Rw230, Rx231, Ry231, Rz231, Rw231, Rx232, Ry232, Rz232, Rw232, Rx233, Ry233, Rz233, Rw233, Rx234, Ry234, Rz234, Rw234, Rx235, Ry235, Rz235, Rw235, Rx236, Ry236, Rz236, Rw236, Rx237, Ry237, Rz237, Rw237, Rx238, Ry238, Rz238, Rw238, Rx239, Ry239, Rz239, Rw239, Rx240, Ry240, Rz240, Rw240, Rx241, Ry241, Rz241, Rw241, Rx242, Ry242, Rz242, Rw242, Rx243, Ry243, Rz243, Rw243, Rx244, Ry244, Rz244, Rw244, Rx245, Ry245, Rz245, Rw245, Rx246, Ry246, Rz246, Rw246, Rx247, Ry247, Rz247, Rw247, Rx248, Ry248, Rz248, Rw248, Rx249, Ry249, Rz249, Rw249, Rx250, Ry250, Rz250, Rw250, Rx251, Ry251, Rz251, Rw251, Rx252, Ry252, Rz252, Rw252, Rx253, Ry253, Rz253, Rw253, Rx254, Ry254, Rz254, Rw254, Rx255, Ry255, Rz255, Rw255, Rx1000, Ry1000, Rz1000, Rw1000, Rx1001, Ry1001, Rz1001, Rw1001, Rx1002, Ry1002, Rz1002, Rw1002, Rx1003, Ry1003, Rz1003, Rw1003, Rx1004, Ry1004, Rz1004, Rw1004, Rx1005, Ry1005, Rz1005, Rw1005, Rx1006, Ry1006, Rz1006,
Rw1006, Rx1007, Ry1007, Rz1007, Rw1007, Rx1008, Ry1008, Rz1008, Rw1008, Rx1009, Ry1009, Rz1009, Rw1009, Rx1010, Ry1010, Rz1010, Rw1010, Rx1011, Ry1011, Rz1011, Rw1011, Rx1012, Ry1012, Rz1012, Rw1012
\ No newline at end of file
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterUsesScalarW.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterUsesScalarW.td?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterUsesScalarW.td (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterUsesScalarW.td Wed Sep 12 12:43:34 2012
@@ -11,4 +11,4 @@
//
//===----------------------------------------------------------------------===//
-Rw1, Rw2, Rw3, Rw4, Rw5, Rw6, Rw7, Rw8, Rw9, Rw10, Rw11, Rw12, Rw13, Rw14, Rw15, Rw16, Rw17, Rw18, Rw19, Rw20, Rw21, Rw22, Rw23, Rw24, Rw25, Rw26, Rw27, Rw28, Rw29, Rw30, Rw31, Rw32, Rw33, Rw34, Rw35, Rw36, Rw37, Rw38, Rw39, Rw40, Rw41, Rw42, Rw43, Rw44, Rw45, Rw46, Rw47, Rw48, Rw49, Rw50, Rw51, Rw52, Rw53, Rw54, Rw55, Rw56, Rw57, Rw58, Rw59, Rw60, Rw61, Rw62, Rw63, Rw64, Rw65, Rw66, Rw67, Rw68, Rw69, Rw70, Rw71, Rw72, Rw73, Rw74, Rw75, Rw76, Rw77, Rw78, Rw79, Rw80, Rw81, Rw82, Rw83, Rw84, Rw85, Rw86, Rw87, Rw88, Rw89, Rw90, Rw91, Rw92, Rw93, Rw94, Rw95, Rw96, Rw97, Rw98, Rw99, Rw100, Rw101, Rw102, Rw103, Rw104, Rw105, Rw106, Rw107, Rw108, Rw109, Rw110, Rw111, Rw112, Rw113, Rw114, Rw115, Rw116, Rw117, Rw118, Rw119, Rw120, Rw121, Rw122, Rw123, Rw124, Rw125, Rw126, Rw127, Rw128, Rw129, Rw130, Rw131, Rw132, Rw133, Rw134, Rw135, Rw136, Rw137, Rw138, Rw139, Rw140, Rw141, Rw142, Rw143, Rw144, Rw145, Rw146, Rw147, Rw148, Rw149, Rw150, Rw151, Rw152, Rw153, Rw154, Rw155, Rw156, Rw157
, Rw158, Rw159, Rw160, Rw161, Rw162, Rw163, Rw164, Rw165, Rw166, Rw167, Rw168, Rw169, Rw170, Rw171, Rw172, Rw173, Rw174, Rw175, Rw176, Rw177, Rw178, Rw179, Rw180, Rw181, Rw182, Rw183, Rw184, Rw185, Rw186, Rw187, Rw188, Rw189, Rw190, Rw191, Rw1000, Rw1001, Rw1002, Rw1003, Rw1004, Rw1005, Rw1006, Rw1007, Rw1008, Rw1009, Rw1010, Rw1011, Rw1012
\ No newline at end of file
+Rw1, Rw2, Rw3, Rw4, Rw5, Rw6, Rw7, Rw8, Rw9, Rw10, Rw11, Rw12, Rw13, Rw14, Rw15, Rw16, Rw17, Rw18, Rw19, Rw20, Rw21, Rw22, Rw23, Rw24, Rw25, Rw26, Rw27, Rw28, Rw29, Rw30, Rw31, Rw32, Rw33, Rw34, Rw35, Rw36, Rw37, Rw38, Rw39, Rw40, Rw41, Rw42, Rw43, Rw44, Rw45, Rw46, Rw47, Rw48, Rw49, Rw50, Rw51, Rw52, Rw53, Rw54, Rw55, Rw56, Rw57, Rw58, Rw59, Rw60, Rw61, Rw62, Rw63, Rw64, Rw65, Rw66, Rw67, Rw68, Rw69, Rw70, Rw71, Rw72, Rw73, Rw74, Rw75, Rw76, Rw77, Rw78, Rw79, Rw80, Rw81, Rw82, Rw83, Rw84, Rw85, Rw86, Rw87, Rw88, Rw89, Rw90, Rw91, Rw92, Rw93, Rw94, Rw95, Rw96, Rw97, Rw98, Rw99, Rw100, Rw101, Rw102, Rw103, Rw104, Rw105, Rw106, Rw107, Rw108, Rw109, Rw110, Rw111, Rw112, Rw113, Rw114, Rw115, Rw116, Rw117, Rw118, Rw119, Rw120, Rw121, Rw122, Rw123, Rw124, Rw125, Rw126, Rw127, Rw128, Rw129, Rw130, Rw131, Rw132, Rw133, Rw134, Rw135, Rw136, Rw137, Rw138, Rw139, Rw140, Rw141, Rw142, Rw143, Rw144, Rw145, Rw146, Rw147, Rw148, Rw149, Rw150, Rw151, Rw152, Rw153, Rw154, Rw155, Rw156, Rw157
, Rw158, Rw159, Rw160, Rw161, Rw162, Rw163, Rw164, Rw165, Rw166, Rw167, Rw168, Rw169, Rw170, Rw171, Rw172, Rw173, Rw174, Rw175, Rw176, Rw177, Rw178, Rw179, Rw180, Rw181, Rw182, Rw183, Rw184, Rw185, Rw186, Rw187, Rw188, Rw189, Rw190, Rw191, Rw192, Rw193, Rw194, Rw195, Rw196, Rw197, Rw198, Rw199, Rw200, Rw201, Rw202, Rw203, Rw204, Rw205, Rw206, Rw207, Rw208, Rw209, Rw210, Rw211, Rw212, Rw213, Rw214, Rw215, Rw216, Rw217, Rw218, Rw219, Rw220, Rw221, Rw222, Rw223, Rw224, Rw225, Rw226, Rw227, Rw228, Rw229, Rw230, Rw231, Rw232, Rw233, Rw234, Rw235, Rw236, Rw237, Rw238, Rw239, Rw240, Rw241, Rw242, Rw243, Rw244, Rw245, Rw246, Rw247, Rw248, Rw249, Rw250, Rw251, Rw252, Rw253, Rw254, Rw255, Rw1000, Rw1001, Rw1002, Rw1003, Rw1004, Rw1005, Rw1006, Rw1007, Rw1008, Rw1009, Rw1010, Rw1011, Rw1012
\ No newline at end of file
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterUsesScalarX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterUsesScalarX.td?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterUsesScalarX.td (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterUsesScalarX.td Wed Sep 12 12:43:34 2012
@@ -11,4 +11,4 @@
//
//===----------------------------------------------------------------------===//
-Rx1, Rx2, Rx3, Rx4, Rx5, Rx6, Rx7, Rx8, Rx9, Rx10, Rx11, Rx12, Rx13, Rx14, Rx15, Rx16, Rx17, Rx18, Rx19, Rx20, Rx21, Rx22, Rx23, Rx24, Rx25, Rx26, Rx27, Rx28, Rx29, Rx30, Rx31, Rx32, Rx33, Rx34, Rx35, Rx36, Rx37, Rx38, Rx39, Rx40, Rx41, Rx42, Rx43, Rx44, Rx45, Rx46, Rx47, Rx48, Rx49, Rx50, Rx51, Rx52, Rx53, Rx54, Rx55, Rx56, Rx57, Rx58, Rx59, Rx60, Rx61, Rx62, Rx63, Rx64, Rx65, Rx66, Rx67, Rx68, Rx69, Rx70, Rx71, Rx72, Rx73, Rx74, Rx75, Rx76, Rx77, Rx78, Rx79, Rx80, Rx81, Rx82, Rx83, Rx84, Rx85, Rx86, Rx87, Rx88, Rx89, Rx90, Rx91, Rx92, Rx93, Rx94, Rx95, Rx96, Rx97, Rx98, Rx99, Rx100, Rx101, Rx102, Rx103, Rx104, Rx105, Rx106, Rx107, Rx108, Rx109, Rx110, Rx111, Rx112, Rx113, Rx114, Rx115, Rx116, Rx117, Rx118, Rx119, Rx120, Rx121, Rx122, Rx123, Rx124, Rx125, Rx126, Rx127, Rx128, Rx129, Rx130, Rx131, Rx132, Rx133, Rx134, Rx135, Rx136, Rx137, Rx138, Rx139, Rx140, Rx141, Rx142, Rx143, Rx144, Rx145, Rx146, Rx147, Rx148, Rx149, Rx150, Rx151, Rx152, Rx153, Rx154, Rx155, Rx156, Rx157
, Rx158, Rx159, Rx160, Rx161, Rx162, Rx163, Rx164, Rx165, Rx166, Rx167, Rx168, Rx169, Rx170, Rx171, Rx172, Rx173, Rx174, Rx175, Rx176, Rx177, Rx178, Rx179, Rx180, Rx181, Rx182, Rx183, Rx184, Rx185, Rx186, Rx187, Rx188, Rx189, Rx190, Rx191, Rx1000, Rx1001, Rx1002, Rx1003, Rx1004, Rx1005, Rx1006, Rx1007, Rx1008, Rx1009, Rx1010, Rx1011, Rx1012
\ No newline at end of file
+Rx1, Rx2, Rx3, Rx4, Rx5, Rx6, Rx7, Rx8, Rx9, Rx10, Rx11, Rx12, Rx13, Rx14, Rx15, Rx16, Rx17, Rx18, Rx19, Rx20, Rx21, Rx22, Rx23, Rx24, Rx25, Rx26, Rx27, Rx28, Rx29, Rx30, Rx31, Rx32, Rx33, Rx34, Rx35, Rx36, Rx37, Rx38, Rx39, Rx40, Rx41, Rx42, Rx43, Rx44, Rx45, Rx46, Rx47, Rx48, Rx49, Rx50, Rx51, Rx52, Rx53, Rx54, Rx55, Rx56, Rx57, Rx58, Rx59, Rx60, Rx61, Rx62, Rx63, Rx64, Rx65, Rx66, Rx67, Rx68, Rx69, Rx70, Rx71, Rx72, Rx73, Rx74, Rx75, Rx76, Rx77, Rx78, Rx79, Rx80, Rx81, Rx82, Rx83, Rx84, Rx85, Rx86, Rx87, Rx88, Rx89, Rx90, Rx91, Rx92, Rx93, Rx94, Rx95, Rx96, Rx97, Rx98, Rx99, Rx100, Rx101, Rx102, Rx103, Rx104, Rx105, Rx106, Rx107, Rx108, Rx109, Rx110, Rx111, Rx112, Rx113, Rx114, Rx115, Rx116, Rx117, Rx118, Rx119, Rx120, Rx121, Rx122, Rx123, Rx124, Rx125, Rx126, Rx127, Rx128, Rx129, Rx130, Rx131, Rx132, Rx133, Rx134, Rx135, Rx136, Rx137, Rx138, Rx139, Rx140, Rx141, Rx142, Rx143, Rx144, Rx145, Rx146, Rx147, Rx148, Rx149, Rx150, Rx151, Rx152, Rx153, Rx154, Rx155, Rx156, Rx157
, Rx158, Rx159, Rx160, Rx161, Rx162, Rx163, Rx164, Rx165, Rx166, Rx167, Rx168, Rx169, Rx170, Rx171, Rx172, Rx173, Rx174, Rx175, Rx176, Rx177, Rx178, Rx179, Rx180, Rx181, Rx182, Rx183, Rx184, Rx185, Rx186, Rx187, Rx188, Rx189, Rx190, Rx191, Rx192, Rx193, Rx194, Rx195, Rx196, Rx197, Rx198, Rx199, Rx200, Rx201, Rx202, Rx203, Rx204, Rx205, Rx206, Rx207, Rx208, Rx209, Rx210, Rx211, Rx212, Rx213, Rx214, Rx215, Rx216, Rx217, Rx218, Rx219, Rx220, Rx221, Rx222, Rx223, Rx224, Rx225, Rx226, Rx227, Rx228, Rx229, Rx230, Rx231, Rx232, Rx233, Rx234, Rx235, Rx236, Rx237, Rx238, Rx239, Rx240, Rx241, Rx242, Rx243, Rx244, Rx245, Rx246, Rx247, Rx248, Rx249, Rx250, Rx251, Rx252, Rx253, Rx254, Rx255, Rx1000, Rx1001, Rx1002, Rx1003, Rx1004, Rx1005, Rx1006, Rx1007, Rx1008, Rx1009, Rx1010, Rx1011, Rx1012
\ No newline at end of file
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterUsesScalarY.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterUsesScalarY.td?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterUsesScalarY.td (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterUsesScalarY.td Wed Sep 12 12:43:34 2012
@@ -11,4 +11,4 @@
//
//===----------------------------------------------------------------------===//
-Ry1, Ry2, Ry3, Ry4, Ry5, Ry6, Ry7, Ry8, Ry9, Ry10, Ry11, Ry12, Ry13, Ry14, Ry15, Ry16, Ry17, Ry18, Ry19, Ry20, Ry21, Ry22, Ry23, Ry24, Ry25, Ry26, Ry27, Ry28, Ry29, Ry30, Ry31, Ry32, Ry33, Ry34, Ry35, Ry36, Ry37, Ry38, Ry39, Ry40, Ry41, Ry42, Ry43, Ry44, Ry45, Ry46, Ry47, Ry48, Ry49, Ry50, Ry51, Ry52, Ry53, Ry54, Ry55, Ry56, Ry57, Ry58, Ry59, Ry60, Ry61, Ry62, Ry63, Ry64, Ry65, Ry66, Ry67, Ry68, Ry69, Ry70, Ry71, Ry72, Ry73, Ry74, Ry75, Ry76, Ry77, Ry78, Ry79, Ry80, Ry81, Ry82, Ry83, Ry84, Ry85, Ry86, Ry87, Ry88, Ry89, Ry90, Ry91, Ry92, Ry93, Ry94, Ry95, Ry96, Ry97, Ry98, Ry99, Ry100, Ry101, Ry102, Ry103, Ry104, Ry105, Ry106, Ry107, Ry108, Ry109, Ry110, Ry111, Ry112, Ry113, Ry114, Ry115, Ry116, Ry117, Ry118, Ry119, Ry120, Ry121, Ry122, Ry123, Ry124, Ry125, Ry126, Ry127, Ry128, Ry129, Ry130, Ry131, Ry132, Ry133, Ry134, Ry135, Ry136, Ry137, Ry138, Ry139, Ry140, Ry141, Ry142, Ry143, Ry144, Ry145, Ry146, Ry147, Ry148, Ry149, Ry150, Ry151, Ry152, Ry153, Ry154, Ry155, Ry156, Ry157
, Ry158, Ry159, Ry160, Ry161, Ry162, Ry163, Ry164, Ry165, Ry166, Ry167, Ry168, Ry169, Ry170, Ry171, Ry172, Ry173, Ry174, Ry175, Ry176, Ry177, Ry178, Ry179, Ry180, Ry181, Ry182, Ry183, Ry184, Ry185, Ry186, Ry187, Ry188, Ry189, Ry190, Ry191, Ry1000, Ry1001, Ry1002, Ry1003, Ry1004, Ry1005, Ry1006, Ry1007, Ry1008, Ry1009, Ry1010, Ry1011, Ry1012
\ No newline at end of file
+Ry1, Ry2, Ry3, Ry4, Ry5, Ry6, Ry7, Ry8, Ry9, Ry10, Ry11, Ry12, Ry13, Ry14, Ry15, Ry16, Ry17, Ry18, Ry19, Ry20, Ry21, Ry22, Ry23, Ry24, Ry25, Ry26, Ry27, Ry28, Ry29, Ry30, Ry31, Ry32, Ry33, Ry34, Ry35, Ry36, Ry37, Ry38, Ry39, Ry40, Ry41, Ry42, Ry43, Ry44, Ry45, Ry46, Ry47, Ry48, Ry49, Ry50, Ry51, Ry52, Ry53, Ry54, Ry55, Ry56, Ry57, Ry58, Ry59, Ry60, Ry61, Ry62, Ry63, Ry64, Ry65, Ry66, Ry67, Ry68, Ry69, Ry70, Ry71, Ry72, Ry73, Ry74, Ry75, Ry76, Ry77, Ry78, Ry79, Ry80, Ry81, Ry82, Ry83, Ry84, Ry85, Ry86, Ry87, Ry88, Ry89, Ry90, Ry91, Ry92, Ry93, Ry94, Ry95, Ry96, Ry97, Ry98, Ry99, Ry100, Ry101, Ry102, Ry103, Ry104, Ry105, Ry106, Ry107, Ry108, Ry109, Ry110, Ry111, Ry112, Ry113, Ry114, Ry115, Ry116, Ry117, Ry118, Ry119, Ry120, Ry121, Ry122, Ry123, Ry124, Ry125, Ry126, Ry127, Ry128, Ry129, Ry130, Ry131, Ry132, Ry133, Ry134, Ry135, Ry136, Ry137, Ry138, Ry139, Ry140, Ry141, Ry142, Ry143, Ry144, Ry145, Ry146, Ry147, Ry148, Ry149, Ry150, Ry151, Ry152, Ry153, Ry154, Ry155, Ry156, Ry157
, Ry158, Ry159, Ry160, Ry161, Ry162, Ry163, Ry164, Ry165, Ry166, Ry167, Ry168, Ry169, Ry170, Ry171, Ry172, Ry173, Ry174, Ry175, Ry176, Ry177, Ry178, Ry179, Ry180, Ry181, Ry182, Ry183, Ry184, Ry185, Ry186, Ry187, Ry188, Ry189, Ry190, Ry191, Ry192, Ry193, Ry194, Ry195, Ry196, Ry197, Ry198, Ry199, Ry200, Ry201, Ry202, Ry203, Ry204, Ry205, Ry206, Ry207, Ry208, Ry209, Ry210, Ry211, Ry212, Ry213, Ry214, Ry215, Ry216, Ry217, Ry218, Ry219, Ry220, Ry221, Ry222, Ry223, Ry224, Ry225, Ry226, Ry227, Ry228, Ry229, Ry230, Ry231, Ry232, Ry233, Ry234, Ry235, Ry236, Ry237, Ry238, Ry239, Ry240, Ry241, Ry242, Ry243, Ry244, Ry245, Ry246, Ry247, Ry248, Ry249, Ry250, Ry251, Ry252, Ry253, Ry254, Ry255, Ry1000, Ry1001, Ry1002, Ry1003, Ry1004, Ry1005, Ry1006, Ry1007, Ry1008, Ry1009, Ry1010, Ry1011, Ry1012
\ No newline at end of file
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterUsesScalarZ.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterUsesScalarZ.td?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterUsesScalarZ.td (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterUsesScalarZ.td Wed Sep 12 12:43:34 2012
@@ -11,4 +11,4 @@
//
//===----------------------------------------------------------------------===//
-Rz1, Rz2, Rz3, Rz4, Rz5, Rz6, Rz7, Rz8, Rz9, Rz10, Rz11, Rz12, Rz13, Rz14, Rz15, Rz16, Rz17, Rz18, Rz19, Rz20, Rz21, Rz22, Rz23, Rz24, Rz25, Rz26, Rz27, Rz28, Rz29, Rz30, Rz31, Rz32, Rz33, Rz34, Rz35, Rz36, Rz37, Rz38, Rz39, Rz40, Rz41, Rz42, Rz43, Rz44, Rz45, Rz46, Rz47, Rz48, Rz49, Rz50, Rz51, Rz52, Rz53, Rz54, Rz55, Rz56, Rz57, Rz58, Rz59, Rz60, Rz61, Rz62, Rz63, Rz64, Rz65, Rz66, Rz67, Rz68, Rz69, Rz70, Rz71, Rz72, Rz73, Rz74, Rz75, Rz76, Rz77, Rz78, Rz79, Rz80, Rz81, Rz82, Rz83, Rz84, Rz85, Rz86, Rz87, Rz88, Rz89, Rz90, Rz91, Rz92, Rz93, Rz94, Rz95, Rz96, Rz97, Rz98, Rz99, Rz100, Rz101, Rz102, Rz103, Rz104, Rz105, Rz106, Rz107, Rz108, Rz109, Rz110, Rz111, Rz112, Rz113, Rz114, Rz115, Rz116, Rz117, Rz118, Rz119, Rz120, Rz121, Rz122, Rz123, Rz124, Rz125, Rz126, Rz127, Rz128, Rz129, Rz130, Rz131, Rz132, Rz133, Rz134, Rz135, Rz136, Rz137, Rz138, Rz139, Rz140, Rz141, Rz142, Rz143, Rz144, Rz145, Rz146, Rz147, Rz148, Rz149, Rz150, Rz151, Rz152, Rz153, Rz154, Rz155, Rz156, Rz157
, Rz158, Rz159, Rz160, Rz161, Rz162, Rz163, Rz164, Rz165, Rz166, Rz167, Rz168, Rz169, Rz170, Rz171, Rz172, Rz173, Rz174, Rz175, Rz176, Rz177, Rz178, Rz179, Rz180, Rz181, Rz182, Rz183, Rz184, Rz185, Rz186, Rz187, Rz188, Rz189, Rz190, Rz191, Rz1000, Rz1001, Rz1002, Rz1003, Rz1004, Rz1005, Rz1006, Rz1007, Rz1008, Rz1009, Rz1010, Rz1011, Rz1012
\ No newline at end of file
+Rz1, Rz2, Rz3, Rz4, Rz5, Rz6, Rz7, Rz8, Rz9, Rz10, Rz11, Rz12, Rz13, Rz14, Rz15, Rz16, Rz17, Rz18, Rz19, Rz20, Rz21, Rz22, Rz23, Rz24, Rz25, Rz26, Rz27, Rz28, Rz29, Rz30, Rz31, Rz32, Rz33, Rz34, Rz35, Rz36, Rz37, Rz38, Rz39, Rz40, Rz41, Rz42, Rz43, Rz44, Rz45, Rz46, Rz47, Rz48, Rz49, Rz50, Rz51, Rz52, Rz53, Rz54, Rz55, Rz56, Rz57, Rz58, Rz59, Rz60, Rz61, Rz62, Rz63, Rz64, Rz65, Rz66, Rz67, Rz68, Rz69, Rz70, Rz71, Rz72, Rz73, Rz74, Rz75, Rz76, Rz77, Rz78, Rz79, Rz80, Rz81, Rz82, Rz83, Rz84, Rz85, Rz86, Rz87, Rz88, Rz89, Rz90, Rz91, Rz92, Rz93, Rz94, Rz95, Rz96, Rz97, Rz98, Rz99, Rz100, Rz101, Rz102, Rz103, Rz104, Rz105, Rz106, Rz107, Rz108, Rz109, Rz110, Rz111, Rz112, Rz113, Rz114, Rz115, Rz116, Rz117, Rz118, Rz119, Rz120, Rz121, Rz122, Rz123, Rz124, Rz125, Rz126, Rz127, Rz128, Rz129, Rz130, Rz131, Rz132, Rz133, Rz134, Rz135, Rz136, Rz137, Rz138, Rz139, Rz140, Rz141, Rz142, Rz143, Rz144, Rz145, Rz146, Rz147, Rz148, Rz149, Rz150, Rz151, Rz152, Rz153, Rz154, Rz155, Rz156, Rz157
, Rz158, Rz159, Rz160, Rz161, Rz162, Rz163, Rz164, Rz165, Rz166, Rz167, Rz168, Rz169, Rz170, Rz171, Rz172, Rz173, Rz174, Rz175, Rz176, Rz177, Rz178, Rz179, Rz180, Rz181, Rz182, Rz183, Rz184, Rz185, Rz186, Rz187, Rz188, Rz189, Rz190, Rz191, Rz192, Rz193, Rz194, Rz195, Rz196, Rz197, Rz198, Rz199, Rz200, Rz201, Rz202, Rz203, Rz204, Rz205, Rz206, Rz207, Rz208, Rz209, Rz210, Rz211, Rz212, Rz213, Rz214, Rz215, Rz216, Rz217, Rz218, Rz219, Rz220, Rz221, Rz222, Rz223, Rz224, Rz225, Rz226, Rz227, Rz228, Rz229, Rz230, Rz231, Rz232, Rz233, Rz234, Rz235, Rz236, Rz237, Rz238, Rz239, Rz240, Rz241, Rz242, Rz243, Rz244, Rz245, Rz246, Rz247, Rz248, Rz249, Rz250, Rz251, Rz252, Rz253, Rz254, Rz255, Rz1000, Rz1001, Rz1002, Rz1003, Rz1004, Rz1005, Rz1006, Rz1007, Rz1008, Rz1009, Rz1010, Rz1011, Rz1012
\ No newline at end of file
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterUsesV2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterUsesV2.td?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterUsesV2.td (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterUsesV2.td Wed Sep 12 12:43:34 2012
@@ -11,4 +11,4 @@
//
//===----------------------------------------------------------------------===//
-Rxy1, Rzw1, Rxy2, Rzw2, Rxy3, Rzw3, Rxy4, Rzw4, Rxy5, Rzw5, Rxy6, Rzw6, Rxy7, Rzw7, Rxy8, Rzw8, Rxy9, Rzw9, Rxy10, Rzw10, Rxy11, Rzw11, Rxy12, Rzw12, Rxy13, Rzw13, Rxy14, Rzw14, Rxy15, Rzw15, Rxy16, Rzw16, Rxy17, Rzw17, Rxy18, Rzw18, Rxy19, Rzw19, Rxy20, Rzw20, Rxy21, Rzw21, Rxy22, Rzw22, Rxy23, Rzw23, Rxy24, Rzw24, Rxy25, Rzw25, Rxy26, Rzw26, Rxy27, Rzw27, Rxy28, Rzw28, Rxy29, Rzw29, Rxy30, Rzw30, Rxy31, Rzw31, Rxy32, Rzw32, Rxy33, Rzw33, Rxy34, Rzw34, Rxy35, Rzw35, Rxy36, Rzw36, Rxy37, Rzw37, Rxy38, Rzw38, Rxy39, Rzw39, Rxy40, Rzw40, Rxy41, Rzw41, Rxy42, Rzw42, Rxy43, Rzw43, Rxy44, Rzw44, Rxy45, Rzw45, Rxy46, Rzw46, Rxy47, Rzw47, Rxy48, Rzw48, Rxy49, Rzw49, Rxy50, Rzw50, Rxy51, Rzw51, Rxy52, Rzw52, Rxy53, Rzw53, Rxy54, Rzw54, Rxy55, Rzw55, Rxy56, Rzw56, Rxy57, Rzw57, Rxy58, Rzw58, Rxy59, Rzw59, Rxy60, Rzw60, Rxy61, Rzw61, Rxy62, Rzw62, Rxy63, Rzw63, Rxy64, Rzw64, Rxy65, Rzw65, Rxy66, Rzw66, Rxy67, Rzw67, Rxy68, Rzw68, Rxy69, Rzw69, Rxy70, Rzw70, Rxy71, Rzw71, Rxy72, Rzw72,
Rxy73, Rzw73, Rxy74, Rzw74, Rxy75, Rzw75, Rxy76, Rzw76, Rxy77, Rzw77, Rxy78, Rzw78, Rxy79, Rzw79, Rxy80, Rzw80, Rxy81, Rzw81, Rxy82, Rzw82, Rxy83, Rzw83, Rxy84, Rzw84, Rxy85, Rzw85, Rxy86, Rzw86, Rxy87, Rzw87, Rxy88, Rzw88, Rxy89, Rzw89, Rxy90, Rzw90, Rxy91, Rzw91, Rxy92, Rzw92, Rxy93, Rzw93, Rxy94, Rzw94, Rxy95, Rzw95, Rxy96, Rzw96, Rxy97, Rzw97, Rxy98, Rzw98, Rxy99, Rzw99, Rxy100, Rzw100, Rxy101, Rzw101, Rxy102, Rzw102, Rxy103, Rzw103, Rxy104, Rzw104, Rxy105, Rzw105, Rxy106, Rzw106, Rxy107, Rzw107, Rxy108, Rzw108, Rxy109, Rzw109, Rxy110, Rzw110, Rxy111, Rzw111, Rxy112, Rzw112, Rxy113, Rzw113, Rxy114, Rzw114, Rxy115, Rzw115, Rxy116, Rzw116, Rxy117, Rzw117, Rxy118, Rzw118, Rxy119, Rzw119, Rxy120, Rzw120, Rxy121, Rzw121, Rxy122, Rzw122, Rxy123, Rzw123, Rxy124, Rzw124, Rxy125, Rzw125, Rxy126, Rzw126, Rxy127, Rzw127, Rxy128, Rzw128, Rxy129, Rzw129, Rxy130, Rzw130, Rxy131, Rzw131, Rxy132, Rzw132, Rxy133, Rzw133, Rxy134, Rzw134, Rxy135, Rzw135, Rxy136, Rzw136, Rxy137, Rzw137, Rx
y138, Rzw138, Rxy139, Rzw139, Rxy140, Rzw140, Rxy141, Rzw141, Rxy142, Rzw142, Rxy143, Rzw143, Rxy144, Rzw144, Rxy145, Rzw145, Rxy146, Rzw146, Rxy147, Rzw147, Rxy148, Rzw148, Rxy149, Rzw149, Rxy150, Rzw150, Rxy151, Rzw151, Rxy152, Rzw152, Rxy153, Rzw153, Rxy154, Rzw154, Rxy155, Rzw155, Rxy156, Rzw156, Rxy157, Rzw157, Rxy158, Rzw158, Rxy159, Rzw159, Rxy160, Rzw160, Rxy161, Rzw161, Rxy162, Rzw162, Rxy163, Rzw163, Rxy164, Rzw164, Rxy165, Rzw165, Rxy166, Rzw166, Rxy167, Rzw167, Rxy168, Rzw168, Rxy169, Rzw169, Rxy170, Rzw170, Rxy171, Rzw171, Rxy172, Rzw172, Rxy173, Rzw173, Rxy174, Rzw174, Rxy175, Rzw175, Rxy176, Rzw176, Rxy177, Rzw177, Rxy178, Rzw178, Rxy179, Rzw179, Rxy180, Rzw180, Rxy181, Rzw181, Rxy182, Rzw182, Rxy183, Rzw183, Rxy184, Rzw184, Rxy185, Rzw185, Rxy186, Rzw186, Rxy187, Rzw187, Rxy188, Rzw188, Rxy189, Rzw189, Rxy190, Rzw190, Rxy191, Rzw191, Rxy1000, Rzw1000, Rxy1001, Rzw1001, Rxy1002, Rzw1002, Rxy1003, Rzw1003, Rxy1004, Rzw1004, Rxy1005, Rzw1005, Rxy1006, Rzw1006, R
xy1007, Rzw1007, Rxy1008, Rzw1008, Rxy1009, Rzw1009, Rxy1010, Rzw1010, Rxy1011, Rzw1011, Rxy1012, Rzw1012
\ No newline at end of file
+Rxy1, Rzw1, Rxy2, Rzw2, Rxy3, Rzw3, Rxy4, Rzw4, Rxy5, Rzw5, Rxy6, Rzw6, Rxy7, Rzw7, Rxy8, Rzw8, Rxy9, Rzw9, Rxy10, Rzw10, Rxy11, Rzw11, Rxy12, Rzw12, Rxy13, Rzw13, Rxy14, Rzw14, Rxy15, Rzw15, Rxy16, Rzw16, Rxy17, Rzw17, Rxy18, Rzw18, Rxy19, Rzw19, Rxy20, Rzw20, Rxy21, Rzw21, Rxy22, Rzw22, Rxy23, Rzw23, Rxy24, Rzw24, Rxy25, Rzw25, Rxy26, Rzw26, Rxy27, Rzw27, Rxy28, Rzw28, Rxy29, Rzw29, Rxy30, Rzw30, Rxy31, Rzw31, Rxy32, Rzw32, Rxy33, Rzw33, Rxy34, Rzw34, Rxy35, Rzw35, Rxy36, Rzw36, Rxy37, Rzw37, Rxy38, Rzw38, Rxy39, Rzw39, Rxy40, Rzw40, Rxy41, Rzw41, Rxy42, Rzw42, Rxy43, Rzw43, Rxy44, Rzw44, Rxy45, Rzw45, Rxy46, Rzw46, Rxy47, Rzw47, Rxy48, Rzw48, Rxy49, Rzw49, Rxy50, Rzw50, Rxy51, Rzw51, Rxy52, Rzw52, Rxy53, Rzw53, Rxy54, Rzw54, Rxy55, Rzw55, Rxy56, Rzw56, Rxy57, Rzw57, Rxy58, Rzw58, Rxy59, Rzw59, Rxy60, Rzw60, Rxy61, Rzw61, Rxy62, Rzw62, Rxy63, Rzw63, Rxy64, Rzw64, Rxy65, Rzw65, Rxy66, Rzw66, Rxy67, Rzw67, Rxy68, Rzw68, Rxy69, Rzw69, Rxy70, Rzw70, Rxy71, Rzw71, Rxy72, Rzw72,
Rxy73, Rzw73, Rxy74, Rzw74, Rxy75, Rzw75, Rxy76, Rzw76, Rxy77, Rzw77, Rxy78, Rzw78, Rxy79, Rzw79, Rxy80, Rzw80, Rxy81, Rzw81, Rxy82, Rzw82, Rxy83, Rzw83, Rxy84, Rzw84, Rxy85, Rzw85, Rxy86, Rzw86, Rxy87, Rzw87, Rxy88, Rzw88, Rxy89, Rzw89, Rxy90, Rzw90, Rxy91, Rzw91, Rxy92, Rzw92, Rxy93, Rzw93, Rxy94, Rzw94, Rxy95, Rzw95, Rxy96, Rzw96, Rxy97, Rzw97, Rxy98, Rzw98, Rxy99, Rzw99, Rxy100, Rzw100, Rxy101, Rzw101, Rxy102, Rzw102, Rxy103, Rzw103, Rxy104, Rzw104, Rxy105, Rzw105, Rxy106, Rzw106, Rxy107, Rzw107, Rxy108, Rzw108, Rxy109, Rzw109, Rxy110, Rzw110, Rxy111, Rzw111, Rxy112, Rzw112, Rxy113, Rzw113, Rxy114, Rzw114, Rxy115, Rzw115, Rxy116, Rzw116, Rxy117, Rzw117, Rxy118, Rzw118, Rxy119, Rzw119, Rxy120, Rzw120, Rxy121, Rzw121, Rxy122, Rzw122, Rxy123, Rzw123, Rxy124, Rzw124, Rxy125, Rzw125, Rxy126, Rzw126, Rxy127, Rzw127, Rxy128, Rzw128, Rxy129, Rzw129, Rxy130, Rzw130, Rxy131, Rzw131, Rxy132, Rzw132, Rxy133, Rzw133, Rxy134, Rzw134, Rxy135, Rzw135, Rxy136, Rzw136, Rxy137, Rzw137, Rx
y138, Rzw138, Rxy139, Rzw139, Rxy140, Rzw140, Rxy141, Rzw141, Rxy142, Rzw142, Rxy143, Rzw143, Rxy144, Rzw144, Rxy145, Rzw145, Rxy146, Rzw146, Rxy147, Rzw147, Rxy148, Rzw148, Rxy149, Rzw149, Rxy150, Rzw150, Rxy151, Rzw151, Rxy152, Rzw152, Rxy153, Rzw153, Rxy154, Rzw154, Rxy155, Rzw155, Rxy156, Rzw156, Rxy157, Rzw157, Rxy158, Rzw158, Rxy159, Rzw159, Rxy160, Rzw160, Rxy161, Rzw161, Rxy162, Rzw162, Rxy163, Rzw163, Rxy164, Rzw164, Rxy165, Rzw165, Rxy166, Rzw166, Rxy167, Rzw167, Rxy168, Rzw168, Rxy169, Rzw169, Rxy170, Rzw170, Rxy171, Rzw171, Rxy172, Rzw172, Rxy173, Rzw173, Rxy174, Rzw174, Rxy175, Rzw175, Rxy176, Rzw176, Rxy177, Rzw177, Rxy178, Rzw178, Rxy179, Rzw179, Rxy180, Rzw180, Rxy181, Rzw181, Rxy182, Rzw182, Rxy183, Rzw183, Rxy184, Rzw184, Rxy185, Rzw185, Rxy186, Rzw186, Rxy187, Rzw187, Rxy188, Rzw188, Rxy189, Rzw189, Rxy190, Rzw190, Rxy191, Rzw191, Rxy192, Rzw192, Rxy193, Rzw193, Rxy194, Rzw194, Rxy195, Rzw195, Rxy196, Rzw196, Rxy197, Rzw197, Rxy198, Rzw198, Rxy199, Rzw199,
Rxy200, Rzw200, Rxy201, Rzw201, Rxy202, Rzw202, Rxy203, Rzw203, Rxy204, Rzw204, Rxy205, Rzw205, Rxy206, Rzw206, Rxy207, Rzw207, Rxy208, Rzw208, Rxy209, Rzw209, Rxy210, Rzw210, Rxy211, Rzw211, Rxy212, Rzw212, Rxy213, Rzw213, Rxy214, Rzw214, Rxy215, Rzw215, Rxy216, Rzw216, Rxy217, Rzw217, Rxy218, Rzw218, Rxy219, Rzw219, Rxy220, Rzw220, Rxy221, Rzw221, Rxy222, Rzw222, Rxy223, Rzw223, Rxy224, Rzw224, Rxy225, Rzw225, Rxy226, Rzw226, Rxy227, Rzw227, Rxy228, Rzw228, Rxy229, Rzw229, Rxy230, Rzw230, Rxy231, Rzw231, Rxy232, Rzw232, Rxy233, Rzw233, Rxy234, Rzw234, Rxy235, Rzw235, Rxy236, Rzw236, Rxy237, Rzw237, Rxy238, Rzw238, Rxy239, Rzw239, Rxy240, Rzw240, Rxy241, Rzw241, Rxy242, Rzw242, Rxy243, Rzw243, Rxy244, Rzw244, Rxy245, Rzw245, Rxy246, Rzw246, Rxy247, Rzw247, Rxy248, Rzw248, Rxy249, Rzw249, Rxy250, Rzw250, Rxy251, Rzw251, Rxy252, Rzw252, Rxy253, Rzw253, Rxy254, Rzw254, Rxy255, Rzw255, Rxy1000, Rzw1000, Rxy1001, Rzw1001, Rxy1002, Rzw1002, Rxy1003, Rzw1003, Rxy1004, Rzw1004, Rx
y1005, Rzw1005, Rxy1006, Rzw1006, Rxy1007, Rzw1007, Rxy1008, Rzw1008, Rxy1009, Rzw1009, Rxy1010, Rzw1010, Rxy1011, Rzw1011, Rxy1012, Rzw1012
\ No newline at end of file
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterUsesV2XY.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterUsesV2XY.td?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterUsesV2XY.td (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterUsesV2XY.td Wed Sep 12 12:43:34 2012
@@ -11,4 +11,4 @@
//
//===----------------------------------------------------------------------===//
-Rxy1, Rxy2, Rxy3, Rxy4, Rxy5, Rxy6, Rxy7, Rxy8, Rxy9, Rxy10, Rxy11, Rxy12, Rxy13, Rxy14, Rxy15, Rxy16, Rxy17, Rxy18, Rxy19, Rxy20, Rxy21, Rxy22, Rxy23, Rxy24, Rxy25, Rxy26, Rxy27, Rxy28, Rxy29, Rxy30, Rxy31, Rxy32, Rxy33, Rxy34, Rxy35, Rxy36, Rxy37, Rxy38, Rxy39, Rxy40, Rxy41, Rxy42, Rxy43, Rxy44, Rxy45, Rxy46, Rxy47, Rxy48, Rxy49, Rxy50, Rxy51, Rxy52, Rxy53, Rxy54, Rxy55, Rxy56, Rxy57, Rxy58, Rxy59, Rxy60, Rxy61, Rxy62, Rxy63, Rxy64, Rxy65, Rxy66, Rxy67, Rxy68, Rxy69, Rxy70, Rxy71, Rxy72, Rxy73, Rxy74, Rxy75, Rxy76, Rxy77, Rxy78, Rxy79, Rxy80, Rxy81, Rxy82, Rxy83, Rxy84, Rxy85, Rxy86, Rxy87, Rxy88, Rxy89, Rxy90, Rxy91, Rxy92, Rxy93, Rxy94, Rxy95, Rxy96, Rxy97, Rxy98, Rxy99, Rxy100, Rxy101, Rxy102, Rxy103, Rxy104, Rxy105, Rxy106, Rxy107, Rxy108, Rxy109, Rxy110, Rxy111, Rxy112, Rxy113, Rxy114, Rxy115, Rxy116, Rxy117, Rxy118, Rxy119, Rxy120, Rxy121, Rxy122, Rxy123, Rxy124, Rxy125, Rxy126, Rxy127, Rxy128, Rxy129, Rxy130, Rxy131, Rxy132, Rxy133, Rxy134, Rxy135, Rxy136, Rxy137, R
xy138, Rxy139, Rxy140, Rxy141, Rxy142, Rxy143, Rxy144, Rxy145, Rxy146, Rxy147, Rxy148, Rxy149, Rxy150, Rxy151, Rxy152, Rxy153, Rxy154, Rxy155, Rxy156, Rxy157, Rxy158, Rxy159, Rxy160, Rxy161, Rxy162, Rxy163, Rxy164, Rxy165, Rxy166, Rxy167, Rxy168, Rxy169, Rxy170, Rxy171, Rxy172, Rxy173, Rxy174, Rxy175, Rxy176, Rxy177, Rxy178, Rxy179, Rxy180, Rxy181, Rxy182, Rxy183, Rxy184, Rxy185, Rxy186, Rxy187, Rxy188, Rxy189, Rxy190, Rxy191, Rxy1000, Rxy1001, Rxy1002, Rxy1003, Rxy1004, Rxy1005, Rxy1006, Rxy1007, Rxy1008, Rxy1009, Rxy1010, Rxy1011, Rxy1012
\ No newline at end of file
+Rxy1, Rxy2, Rxy3, Rxy4, Rxy5, Rxy6, Rxy7, Rxy8, Rxy9, Rxy10, Rxy11, Rxy12, Rxy13, Rxy14, Rxy15, Rxy16, Rxy17, Rxy18, Rxy19, Rxy20, Rxy21, Rxy22, Rxy23, Rxy24, Rxy25, Rxy26, Rxy27, Rxy28, Rxy29, Rxy30, Rxy31, Rxy32, Rxy33, Rxy34, Rxy35, Rxy36, Rxy37, Rxy38, Rxy39, Rxy40, Rxy41, Rxy42, Rxy43, Rxy44, Rxy45, Rxy46, Rxy47, Rxy48, Rxy49, Rxy50, Rxy51, Rxy52, Rxy53, Rxy54, Rxy55, Rxy56, Rxy57, Rxy58, Rxy59, Rxy60, Rxy61, Rxy62, Rxy63, Rxy64, Rxy65, Rxy66, Rxy67, Rxy68, Rxy69, Rxy70, Rxy71, Rxy72, Rxy73, Rxy74, Rxy75, Rxy76, Rxy77, Rxy78, Rxy79, Rxy80, Rxy81, Rxy82, Rxy83, Rxy84, Rxy85, Rxy86, Rxy87, Rxy88, Rxy89, Rxy90, Rxy91, Rxy92, Rxy93, Rxy94, Rxy95, Rxy96, Rxy97, Rxy98, Rxy99, Rxy100, Rxy101, Rxy102, Rxy103, Rxy104, Rxy105, Rxy106, Rxy107, Rxy108, Rxy109, Rxy110, Rxy111, Rxy112, Rxy113, Rxy114, Rxy115, Rxy116, Rxy117, Rxy118, Rxy119, Rxy120, Rxy121, Rxy122, Rxy123, Rxy124, Rxy125, Rxy126, Rxy127, Rxy128, Rxy129, Rxy130, Rxy131, Rxy132, Rxy133, Rxy134, Rxy135, Rxy136, Rxy137, R
xy138, Rxy139, Rxy140, Rxy141, Rxy142, Rxy143, Rxy144, Rxy145, Rxy146, Rxy147, Rxy148, Rxy149, Rxy150, Rxy151, Rxy152, Rxy153, Rxy154, Rxy155, Rxy156, Rxy157, Rxy158, Rxy159, Rxy160, Rxy161, Rxy162, Rxy163, Rxy164, Rxy165, Rxy166, Rxy167, Rxy168, Rxy169, Rxy170, Rxy171, Rxy172, Rxy173, Rxy174, Rxy175, Rxy176, Rxy177, Rxy178, Rxy179, Rxy180, Rxy181, Rxy182, Rxy183, Rxy184, Rxy185, Rxy186, Rxy187, Rxy188, Rxy189, Rxy190, Rxy191, Rxy192, Rxy193, Rxy194, Rxy195, Rxy196, Rxy197, Rxy198, Rxy199, Rxy200, Rxy201, Rxy202, Rxy203, Rxy204, Rxy205, Rxy206, Rxy207, Rxy208, Rxy209, Rxy210, Rxy211, Rxy212, Rxy213, Rxy214, Rxy215, Rxy216, Rxy217, Rxy218, Rxy219, Rxy220, Rxy221, Rxy222, Rxy223, Rxy224, Rxy225, Rxy226, Rxy227, Rxy228, Rxy229, Rxy230, Rxy231, Rxy232, Rxy233, Rxy234, Rxy235, Rxy236, Rxy237, Rxy238, Rxy239, Rxy240, Rxy241, Rxy242, Rxy243, Rxy244, Rxy245, Rxy246, Rxy247, Rxy248, Rxy249, Rxy250, Rxy251, Rxy252, Rxy253, Rxy254, Rxy255, Rxy1000, Rxy1001, Rxy1002, Rxy1003, Rxy1004, R
xy1005, Rxy1006, Rxy1007, Rxy1008, Rxy1009, Rxy1010, Rxy1011, Rxy1012
\ No newline at end of file
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterUsesV2ZW.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterUsesV2ZW.td?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterUsesV2ZW.td (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterUsesV2ZW.td Wed Sep 12 12:43:34 2012
@@ -11,4 +11,4 @@
//
//===----------------------------------------------------------------------===//
-Rzw1, Rzw2, Rzw3, Rzw4, Rzw5, Rzw6, Rzw7, Rzw8, Rzw9, Rzw10, Rzw11, Rzw12, Rzw13, Rzw14, Rzw15, Rzw16, Rzw17, Rzw18, Rzw19, Rzw20, Rzw21, Rzw22, Rzw23, Rzw24, Rzw25, Rzw26, Rzw27, Rzw28, Rzw29, Rzw30, Rzw31, Rzw32, Rzw33, Rzw34, Rzw35, Rzw36, Rzw37, Rzw38, Rzw39, Rzw40, Rzw41, Rzw42, Rzw43, Rzw44, Rzw45, Rzw46, Rzw47, Rzw48, Rzw49, Rzw50, Rzw51, Rzw52, Rzw53, Rzw54, Rzw55, Rzw56, Rzw57, Rzw58, Rzw59, Rzw60, Rzw61, Rzw62, Rzw63, Rzw64, Rzw65, Rzw66, Rzw67, Rzw68, Rzw69, Rzw70, Rzw71, Rzw72, Rzw73, Rzw74, Rzw75, Rzw76, Rzw77, Rzw78, Rzw79, Rzw80, Rzw81, Rzw82, Rzw83, Rzw84, Rzw85, Rzw86, Rzw87, Rzw88, Rzw89, Rzw90, Rzw91, Rzw92, Rzw93, Rzw94, Rzw95, Rzw96, Rzw97, Rzw98, Rzw99, Rzw100, Rzw101, Rzw102, Rzw103, Rzw104, Rzw105, Rzw106, Rzw107, Rzw108, Rzw109, Rzw110, Rzw111, Rzw112, Rzw113, Rzw114, Rzw115, Rzw116, Rzw117, Rzw118, Rzw119, Rzw120, Rzw121, Rzw122, Rzw123, Rzw124, Rzw125, Rzw126, Rzw127, Rzw128, Rzw129, Rzw130, Rzw131, Rzw132, Rzw133, Rzw134, Rzw135, Rzw136, Rzw137, R
zw138, Rzw139, Rzw140, Rzw141, Rzw142, Rzw143, Rzw144, Rzw145, Rzw146, Rzw147, Rzw148, Rzw149, Rzw150, Rzw151, Rzw152, Rzw153, Rzw154, Rzw155, Rzw156, Rzw157, Rzw158, Rzw159, Rzw160, Rzw161, Rzw162, Rzw163, Rzw164, Rzw165, Rzw166, Rzw167, Rzw168, Rzw169, Rzw170, Rzw171, Rzw172, Rzw173, Rzw174, Rzw175, Rzw176, Rzw177, Rzw178, Rzw179, Rzw180, Rzw181, Rzw182, Rzw183, Rzw184, Rzw185, Rzw186, Rzw187, Rzw188, Rzw189, Rzw190, Rzw191, Rzw1000, Rzw1001, Rzw1002, Rzw1003, Rzw1004, Rzw1005, Rzw1006, Rzw1007, Rzw1008, Rzw1009, Rzw1010, Rzw1011, Rzw1012
\ No newline at end of file
+Rzw1, Rzw2, Rzw3, Rzw4, Rzw5, Rzw6, Rzw7, Rzw8, Rzw9, Rzw10, Rzw11, Rzw12, Rzw13, Rzw14, Rzw15, Rzw16, Rzw17, Rzw18, Rzw19, Rzw20, Rzw21, Rzw22, Rzw23, Rzw24, Rzw25, Rzw26, Rzw27, Rzw28, Rzw29, Rzw30, Rzw31, Rzw32, Rzw33, Rzw34, Rzw35, Rzw36, Rzw37, Rzw38, Rzw39, Rzw40, Rzw41, Rzw42, Rzw43, Rzw44, Rzw45, Rzw46, Rzw47, Rzw48, Rzw49, Rzw50, Rzw51, Rzw52, Rzw53, Rzw54, Rzw55, Rzw56, Rzw57, Rzw58, Rzw59, Rzw60, Rzw61, Rzw62, Rzw63, Rzw64, Rzw65, Rzw66, Rzw67, Rzw68, Rzw69, Rzw70, Rzw71, Rzw72, Rzw73, Rzw74, Rzw75, Rzw76, Rzw77, Rzw78, Rzw79, Rzw80, Rzw81, Rzw82, Rzw83, Rzw84, Rzw85, Rzw86, Rzw87, Rzw88, Rzw89, Rzw90, Rzw91, Rzw92, Rzw93, Rzw94, Rzw95, Rzw96, Rzw97, Rzw98, Rzw99, Rzw100, Rzw101, Rzw102, Rzw103, Rzw104, Rzw105, Rzw106, Rzw107, Rzw108, Rzw109, Rzw110, Rzw111, Rzw112, Rzw113, Rzw114, Rzw115, Rzw116, Rzw117, Rzw118, Rzw119, Rzw120, Rzw121, Rzw122, Rzw123, Rzw124, Rzw125, Rzw126, Rzw127, Rzw128, Rzw129, Rzw130, Rzw131, Rzw132, Rzw133, Rzw134, Rzw135, Rzw136, Rzw137, R
zw138, Rzw139, Rzw140, Rzw141, Rzw142, Rzw143, Rzw144, Rzw145, Rzw146, Rzw147, Rzw148, Rzw149, Rzw150, Rzw151, Rzw152, Rzw153, Rzw154, Rzw155, Rzw156, Rzw157, Rzw158, Rzw159, Rzw160, Rzw161, Rzw162, Rzw163, Rzw164, Rzw165, Rzw166, Rzw167, Rzw168, Rzw169, Rzw170, Rzw171, Rzw172, Rzw173, Rzw174, Rzw175, Rzw176, Rzw177, Rzw178, Rzw179, Rzw180, Rzw181, Rzw182, Rzw183, Rzw184, Rzw185, Rzw186, Rzw187, Rzw188, Rzw189, Rzw190, Rzw191, Rzw192, Rzw193, Rzw194, Rzw195, Rzw196, Rzw197, Rzw198, Rzw199, Rzw200, Rzw201, Rzw202, Rzw203, Rzw204, Rzw205, Rzw206, Rzw207, Rzw208, Rzw209, Rzw210, Rzw211, Rzw212, Rzw213, Rzw214, Rzw215, Rzw216, Rzw217, Rzw218, Rzw219, Rzw220, Rzw221, Rzw222, Rzw223, Rzw224, Rzw225, Rzw226, Rzw227, Rzw228, Rzw229, Rzw230, Rzw231, Rzw232, Rzw233, Rzw234, Rzw235, Rzw236, Rzw237, Rzw238, Rzw239, Rzw240, Rzw241, Rzw242, Rzw243, Rzw244, Rzw245, Rzw246, Rzw247, Rzw248, Rzw249, Rzw250, Rzw251, Rzw252, Rzw253, Rzw254, Rzw255, Rzw1000, Rzw1001, Rzw1002, Rzw1003, Rzw1004, R
zw1005, Rzw1006, Rzw1007, Rzw1008, Rzw1009, Rzw1010, Rzw1011, Rzw1012
\ No newline at end of file
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterUsesV4.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterUsesV4.td?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterUsesV4.td (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILRegisterUsesV4.td Wed Sep 12 12:43:34 2012
@@ -11,4 +11,4 @@
//
//===----------------------------------------------------------------------===//
-R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61, R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76, R77, R78, R79, R80, R81, R82, R83, R84, R85, R86, R87, R88, R89, R90, R91, R92, R93, R94, R95, R96, R97, R98, R99, R100, R101, R102, R103, R104, R105, R106, R107, R108, R109, R110, R111, R112, R113, R114, R115, R116, R117, R118, R119, R120, R121, R122, R123, R124, R125, R126, R127, R128, R129, R130, R131, R132, R133, R134, R135, R136, R137, R138, R139, R140, R141, R142, R143, R144, R145, R146, R147, R148, R149, R150, R151, R152, R153, R154, R155, R156, R157, R158, R159, R160, R161, R162, R163, R164, R165, R166, R167, R168, R169, R170, R171, R172, R173, R174, R175, R176, R177, R178, R179, R180, R181, R182, R183,
R184, R185, R186, R187, R188, R189, R190, R191, R1000, R1001, R1002, R1003, R1004, R1005, R1006, R1007, R1008, R1009, R1010, R1011, R1012
\ No newline at end of file
+R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61, R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76, R77, R78, R79, R80, R81, R82, R83, R84, R85, R86, R87, R88, R89, R90, R91, R92, R93, R94, R95, R96, R97, R98, R99, R100, R101, R102, R103, R104, R105, R106, R107, R108, R109, R110, R111, R112, R113, R114, R115, R116, R117, R118, R119, R120, R121, R122, R123, R124, R125, R126, R127, R128, R129, R130, R131, R132, R133, R134, R135, R136, R137, R138, R139, R140, R141, R142, R143, R144, R145, R146, R147, R148, R149, R150, R151, R152, R153, R154, R155, R156, R157, R158, R159, R160, R161, R162, R163, R164, R165, R166, R167, R168, R169, R170, R171, R172, R173, R174, R175, R176, R177, R178, R179, R180, R181, R182, R183,
R184, R185, R186, R187, R188, R189, R190, R191, R192, R193, R194, R195, R196, R197, R198, R199, R200, R201, R202, R203, R204, R205, R206, R207, R208, R209, R210, R211, R212, R213, R214, R215, R216, R217, R218, R219, R220, R221, R222, R223, R224, R225, R226, R227, R228, R229, R230, R231, R232, R233, R234, R235, R236, R237, R238, R239, R240, R241, R242, R243, R244, R245, R246, R247, R248, R249, R250, R251, R252, R253, R254, R255, R1000, R1001, R1002, R1003, R1004, R1005, R1006, R1007, R1008, R1009, R1010, R1011, R1012
\ No newline at end of file
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSIAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSIAsmPrinter.cpp?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSIAsmPrinter.cpp (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSIAsmPrinter.cpp Wed Sep 12 12:43:34 2012
@@ -37,13 +37,11 @@
#include "llvm/Support/TargetRegistry.h"
using namespace llvm;
-
// TODO: Add support for verbose.
AMDILSIAsmPrinter::AMDILSIAsmPrinter(AMDIL_ASM_PRINTER_ARGUMENTS)
: AMDILAsmPrinter(ASM_PRINTER_ARGUMENTS)
{
}
-
AMDILSIAsmPrinter::~AMDILSIAsmPrinter()
{
}
@@ -82,7 +80,6 @@
}
emitMCallInst(MI, O, name);
}
-
bool
AMDILSIAsmPrinter::runOnMachineFunction(MachineFunction &lMF)
{
@@ -100,7 +97,6 @@
EmitFunctionBody();
return false;
}
-
void
AMDILSIAsmPrinter::EmitInstruction(const MachineInstr *II)
{
@@ -109,7 +105,7 @@
formatted_raw_ostream O(OFunStr);
const AMDILSubtarget *curTarget = mTM->getSubtargetImpl();
if (mDebugMode) {
- O << ";" ;
+ O << ";";
II->print(O);
}
if (isMacroFunc(II)) {
@@ -167,7 +163,7 @@
} else {
printOperand(II, x
, O
- );
+ );
}
if (!x) {
O << "), (";
@@ -201,8 +197,9 @@
} else {
mMFI->addCalledIntr(macronum);
}
+ } else if (II->getOpcode() == AMDIL::COPY) {
+ printCopy(II, O);
} else {
-
// Print the assembly for the instruction.
// We want to make sure that we do HW constants
// before we do arena segment
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSIAsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSIAsmPrinter.h?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSIAsmPrinter.h (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSIAsmPrinter.h Wed Sep 12 12:43:34 2012
@@ -53,7 +53,6 @@
//
virtual void
emitMacroFunc(const MachineInstr *MI, OSTREAM_TYPE &O);
-
-}; // AMDILSIAsmPrinter
+}; // AMDILSIAsmPrinter
} // end of llvm namespace
#endif // _AMDIL_SI_ASM_PRINTER_H_
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSIDevice.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSIDevice.cpp?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSIDevice.cpp (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSIDevice.cpp Wed Sep 12 12:43:34 2012
@@ -34,11 +34,9 @@
mDeviceFlag = OCL_DEVICE_CAPEVERDE;
}
}
-
AMDILSIDevice::~AMDILSIDevice()
{
}
-
void
AMDILSIDevice::setCaps()
{
@@ -47,10 +45,8 @@
mSWBits.reset(AMDILDeviceInfo::ArenaSegment);
mHWBits.reset(AMDILDeviceInfo::ArenaSegment);
mHWBits.set(AMDILDeviceInfo::ByteStores);
- if (mSTM->calVersion() >= CAL_VERSION_SC_140) {
- mHWBits.set(AMDILDeviceInfo::HW64BitDivMod);
- mSWBits.reset(AMDILDeviceInfo::HW64BitDivMod);
- }
+ mHWBits.set(AMDILDeviceInfo::HW64BitDivMod);
+ mSWBits.reset(AMDILDeviceInfo::HW64BitDivMod);
if (!mSTM->isApple()) {
if (mSTM->isOverride(AMDILDeviceInfo::Images)) {
mHWBits.set(AMDILDeviceInfo::Images);
@@ -58,40 +54,30 @@
} else {
mHWBits.set(AMDILDeviceInfo::Images);
}
- if (mSTM->calVersion() > CAL_VERSION_GLOBAL_RETURN_BUFFER) {
- mHWBits.set(AMDILDeviceInfo::CachedMem);
- }
+ mHWBits.set(AMDILDeviceInfo::CachedMem);
mHWBits.set(AMDILDeviceInfo::ByteLDSOps);
mSWBits.reset(AMDILDeviceInfo::ByteLDSOps);
mHWBits.set(AMDILDeviceInfo::LongOps);
mSWBits.reset(AMDILDeviceInfo::LongOps);
mHWBits.set(AMDILDeviceInfo::TmrReg);
mHWBits.set(AMDILDeviceInfo::PPAMode);
- // The software mode is enabled until global memory has
- // been verified, then we can enable constant/private/local/region
- // memory in hw mode.
- //mHWBits.reset(AMDILDeviceInfo::ConstantMem);
- //mHWBits.reset(AMDILDeviceInfo::PrivateMem);
- //mSWBits.set(AMDILDeviceInfo::ConstantMem);
- //mSWBits.set(AMDILDeviceInfo::PrivateMem);
- //mHWBits.set(AMDILDeviceInfo::LocalMem);
- //mHWBits.set(AMDILDeviceInfo::RegionMem);
+ mHWBits.set(AMDILDeviceInfo::ConstantMem);
+ mHWBits.set(AMDILDeviceInfo::PrivateMem);
+ mHWBits.set(AMDILDeviceInfo::LocalMem);
+ mHWBits.set(AMDILDeviceInfo::RegionMem);
}
-
uint32_t
AMDILSIDevice::getGeneration() const
{
return AMDILDeviceInfo::HD7XXX;
}
-
uint32_t
AMDILSIDevice::getMaxNumUAVs() const
{
return 1024;
}
uint32_t
-AMDILSIDevice::getResourceID(uint32_t id) const
-{
+AMDILSIDevice::getResourceID(uint32_t id) const {
switch(id) {
default:
assert(0 && "ID type passed in is unknown!");
@@ -124,34 +110,28 @@
return 0;
}
FunctionPass*
-AMDILSIDevice::getIOExpansion(
- TargetMachine& TM, CodeGenOpt::Level OptLevel) const
+AMDILSIDevice::getIOExpansion() const
{
- return new AMDILSIIOExpansion(TM, OptLevel);
+ return new AMDILSIIOExpansion();
}
-
AsmPrinter*
AMDILSIDevice::getAsmPrinter(AMDIL_ASM_PRINTER_ARGUMENTS) const
{
return new AMDILSIAsmPrinter(ASM_PRINTER_ARGUMENTS);
}
-
FunctionPass*
AMDILSIDevice::getPointerManager(
TargetMachine& TM, CodeGenOpt::Level OptLevel) const
{
- return new AMDILSIPointerManager(TM, OptLevel);
+ return new AMDILSIPointerManager();
}
-
AMDILSIDevice32::AMDILSIDevice32(AMDILSubtarget *ST)
: AMDILSIDevice(ST)
{
}
-
AMDILSIDevice32::~AMDILSIDevice32()
{
}
-
std::string
AMDILSIDevice32::getDataLayout() const
{
@@ -171,7 +151,6 @@
AMDILSIDevice64on32::~AMDILSIDevice64on32()
{
}
-
std::string
AMDILSIDevice64on32::getDataLayout() const
{
@@ -188,11 +167,9 @@
: AMDILSIDevice(ST)
{
}
-
AMDILSIDevice64::~AMDILSIDevice64()
{
}
-
std::string
AMDILSIDevice64::getDataLayout() const
{
@@ -203,4 +180,3 @@
"-v512:512:512-v1024:1024:1024-v2048:2048:2048"
"-n8:16:32:64");
}
-
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSIDevice.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSIDevice.h?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSIDevice.h (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSIDevice.h Wed Sep 12 12:43:34 2012
@@ -16,20 +16,17 @@
#ifndef _AMDILSIDEVICE_H_
#define _AMDILSIDEVICE_H_
#include "AMDILNIDevice.h"
-namespace llvm
-{
+namespace llvm {
class AMDILSubtarget;
// Device that matches the SI family. The SI family is a scalar architecture
// with a vector unit to do math. The SI device has 8/16 bit native load/store
// instructions, 1024 UAVs and no arena. It
//
-class AMDILSIDevice : public AMDILCaymanDevice
-{
+class AMDILSIDevice : public AMDILCaymanDevice {
protected:
AMDILSIDevice(AMDILSubtarget*);
- FunctionPass*
- getIOExpansion(TargetMachine&, CodeGenOpt::Level) const;
+ FunctionPass* getIOExpansion() const;
AsmPrinter*
getAsmPrinter(AMDIL_ASM_PRINTER_ARGUMENTS) const;
FunctionPass*
@@ -43,33 +40,30 @@
virtual std::string getDataLayout() const = 0;
protected:
virtual void setCaps();
-}; // AMDILSIDevice
-// 32bit SI device
-class AMDILSIDevice32 : public AMDILSIDevice
-{
+}; // AMDILSIDevice
+ // 32bit SI device
+class AMDILSIDevice32 : public AMDILSIDevice {
public:
AMDILSIDevice32(AMDILSubtarget*);
virtual ~AMDILSIDevice32();
virtual std::string getDataLayout() const;
-}; // AMDILSIDevice32
+}; // AMDILSIDevice32
#if 0
// 64bit ptr 32bit SI device
-class AMDILSIDevice64on32 : public AMDILSIDevice
-{
+class AMDILSIDevice64on32 : public AMDILSIDevice {
public:
AMDILSIDevice64on32(AMDILSubtarget*);
virtual ~AMDILSIDevice64on32();
virtual std::string getDataLayout() const;
-}; // AMDILSIDevice64on32
+}; // AMDILSIDevice64on32
#endif
// 64bit SI device
-class AMDILSIDevice64 : public AMDILSIDevice
-{
+class AMDILSIDevice64 : public AMDILSIDevice {
public:
AMDILSIDevice64(AMDILSubtarget*);
virtual ~AMDILSIDevice64();
virtual std::string getDataLayout() const;
-}; // AMDILSIDevice64
+}; // AMDILSIDevice64
static const unsigned int MAX_LDS_SIZE_1000 = AMDILDevice::MAX_LDS_SIZE_800;
} // namespace llvm
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSIIOExpansion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSIIOExpansion.cpp?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSIIOExpansion.cpp (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSIIOExpansion.cpp Wed Sep 12 12:43:34 2012
@@ -27,92 +27,117 @@
#include "llvm/Support/DebugLoc.h"
#include <cstdio>
using namespace llvm;
-AMDILSIIOExpansion::AMDILSIIOExpansion(TargetMachine &tm,
- CodeGenOpt::Level OptLevel) : AMDILEGIOExpansion(tm, OptLevel)
+
+namespace llvm
{
+extern void initializeAMDILSIIOExpansionPass(llvm::PassRegistry&);
}
-AMDILSIIOExpansion::~AMDILSIIOExpansion()
+char AMDILSIIOExpansion::ID = 0;
+INITIALIZE_PASS(AMDILSIIOExpansion, "si-io-expansion",
+ "AMDIL SI IO Expansion", false, false);
+
+AMDILSIIOExpansion::AMDILSIIOExpansion()
+ : MachineFunctionPass(ID)
{
+ initializeAMDILSIIOExpansionPass(*PassRegistry::getPassRegistry());
}
const char *AMDILSIIOExpansion::getPassName() const
{
return "AMDIL SI IO Expansion Pass";
}
-
+bool AMDILSIIOExpansion::runOnMachineFunction(MachineFunction& MF)
+{
+ AMDILSIIOExpansionImpl impl(MF);
+ return impl.run();
+}
bool
-AMDILSIIOExpansion::isCacheableOp(MachineInstr *MI)
+AMDILSIIOExpansionImpl::isCacheableOp(MachineInstr *MI)
{
AMDILAS::InstrResEnc curRes;
getAsmPrinterFlags(MI, curRes);
return curRes.bits.CacheableRead;
}
-
bool
-AMDILSIIOExpansion::isIOInstruction(TargetMachine &TM, MachineInstr *MI)
+AMDILSIIOExpansionImpl::isIOInstruction(MachineInstr *MI)
{
if (!MI) {
return false;
}
- if (is64BitImageInst(TM, MI)) {
+ if (is64BitImageInst(MI)) {
return true;
}
- return AMDILEGIOExpansion::isIOInstruction(MI);
+ switch (MI->getOpcode()) {
+ default:
+ return AMDILEGIOExpansionImpl::isIOInstruction(MI);
+ case AMDIL::ATOM_G_LOADi8:
+ case AMDIL::ATOM_G_STOREi8:
+ case AMDIL::ATOM64_G_LOADi8:
+ case AMDIL::ATOM64_G_STOREi8:
+ case AMDIL::ATOM_G_LOADi16:
+ case AMDIL::ATOM_G_STOREi16:
+ case AMDIL::ATOM64_G_LOADi16:
+ case AMDIL::ATOM64_G_STOREi16:
+ case AMDIL::ATOM_G_LOADi32:
+ case AMDIL::ATOM_G_STOREi32:
+ case AMDIL::ATOM64_G_LOADi32:
+ case AMDIL::ATOM64_G_STOREi32:
+ case AMDIL::ATOM_G_LOADv2i32:
+ case AMDIL::ATOM_G_STOREv2i32:
+ case AMDIL::ATOM64_G_LOADv2i32:
+ case AMDIL::ATOM64_G_STOREv2i32:
+ case AMDIL::ATOM_G_LOADv4i32:
+ case AMDIL::ATOM_G_STOREv4i32:
+ case AMDIL::ATOM64_G_LOADv4i32:
+ case AMDIL::ATOM64_G_STOREv4i32:
+ return false;
+ }
+ return AMDILEGIOExpansionImpl::isIOInstruction(MI);
}
-
void
-AMDILSIIOExpansion::expandIOInstruction(TargetMachine &TM, MachineInstr *MI)
+AMDILSIIOExpansionImpl::expandIOInstruction(MachineInstr *MI)
{
- assert(isIOInstruction(TM, MI) && "Must be an IO instruction to "
+ assert(isIOInstruction(MI) && "Must be an IO instruction to "
"be passed to this function!");
- if (is64BitImageInst(TM, MI)) {
- if (isReadImageInst(TM, MI) || isImageTXLDInst(TM, MI)) {
+ if (is64BitImageInst(MI)) {
+ if (isReadImageInst(MI) || isImageTXLDInst(MI)) {
expandImageLoad(mBB, MI);
return;
}
- if (isWriteImageInst(TM, MI)) {
+ if (isWriteImageInst(MI)) {
expandImageStore(mBB, MI);
return;
}
- if (isImageInfoInst(TM, MI)) {
+ if (isImageInfoInst(MI)) {
expandImageParam(mBB, MI);
return;
}
}
- AMDILEGIOExpansion::expandIOInstruction(MI);
+ AMDILEGIOExpansionImpl::expandIOInstruction(MI);
}
-
void
-AMDILSIIOExpansion::expandGlobalLoad(MachineInstr *MI)
+AMDILSIIOExpansionImpl::expandGlobalLoad(MachineInstr *MI)
{
- // These instructions are generated before the current MI.
- expandLoadStartCode(MI);
+ uint32_t addyReg = MI->getOperand(1).getReg();
+ uint32_t dataReg = MI->getOperand(0).getReg();
+ expandLoadStartCode(MI, addyReg);
DebugLoc DL = MI->getDebugLoc();
uint32_t ID = getPointerID(MI);
bool cacheable = isCacheableOp(MI);
- bool is64bit = is64bitLSOp(TM, MI);
- bool aligned = mSTM->calVersion() >= CAL_CACHED_ALIGNED_UAVS;
+ bool is64bit = is64bitLSOp(MI);
mKM->setOutputInst();
- uint32_t addyReg = (is64bit) ? AMDIL::Rxy1010 : AMDIL::Rx1010;
switch (getMemorySize(MI)) {
default:
if (cacheable) {
- if (aligned) {
- BuildMI(*mBB, MI, DL, mTII->get((is64bit) ?
- AMDIL::UAVRAWLOADCACHEDALIGNED64_v4i32
- : AMDIL::UAVRAWLOADCACHEDALIGNED_v4i32),
- AMDIL::R1011).addReg(addyReg).addImm(ID);
- } else {
- BuildMI(*mBB, MI, DL, mTII->get(
- (is64bit) ? AMDIL::UAVRAWLOADCACHED64_v4i32 :
- AMDIL::UAVRAWLOADCACHED_v4i32),
- AMDIL::R1011).addReg(addyReg).addImm(ID);
- }
+ BuildMI(*mBB, MI, DL, mTII->get((is64bit) ?
+ AMDIL::UAVRAW64LOADCACHEDALIGNEDv4i32
+ : AMDIL::UAVRAW32LOADCACHEDALIGNEDv4i32),
+ dataReg).addReg(addyReg).addImm(ID);
} else {
BuildMI(*mBB, MI, DL, mTII->get(
- (is64bit) ? AMDIL::UAVRAWLOAD_v4i32 :
- AMDIL::UAVRAWLOAD_v4i32),
- AMDIL::R1011)
+ (is64bit) ? AMDIL::UAVRAW64LOADv4i32 :
+ AMDIL::UAVRAW32LOADv4i32),
+ dataReg)
.addReg(addyReg)
.addImm(ID);
}
@@ -120,139 +145,133 @@
case 1:
if (cacheable) {
BuildMI(*mBB, MI, DL, mTII->get((isSWSExtLoadInst(MI)
- ? ((is64bit) ? AMDIL::UAVRAWLOADCACHED64_i8
- : AMDIL::UAVRAWLOADCACHED_i8) :
- ((is64bit) ? AMDIL::UAVRAWLOADCACHED64_u8
- : AMDIL::UAVRAWLOADCACHED_u8))),
- AMDIL::Rx1011)
- .addReg(addyReg)
- .addImm(ID);
+ ? ((is64bit) ? AMDIL::
+ UAVRAW64LOADCACHEDi8
+ : AMDIL::UAVRAW32LOADCACHEDi8) :
+ ((is64bit) ? AMDIL::UAVRAW64LOADCACHEDu8
+ : AMDIL::UAVRAW32LOADCACHEDu8))),
+ dataReg)
+ .addReg(addyReg)
+ .addImm(ID);
} else {
BuildMI(*mBB, MI, DL, mTII->get((isSWSExtLoadInst(MI)
- ? ((is64bit) ? AMDIL::UAVRAWLOAD64_i8 : AMDIL::UAVRAWLOAD_i8) :
- ((is64bit) ? AMDIL::UAVRAWLOAD64_u8 : AMDIL::UAVRAWLOAD_u8))),
- AMDIL::Rx1011)
- .addReg(addyReg)
- .addImm(ID);
+ ? ((is64bit) ? AMDIL::UAVRAW64LOADi8 :
+ AMDIL::UAVRAW32LOADi8) :
+ ((is64bit) ? AMDIL::UAVRAW64LOADu8 :
+ AMDIL::UAVRAW32LOADu8))),
+ dataReg)
+ .addReg(addyReg)
+ .addImm(ID);
}
break;
case 2:
if (cacheable) {
BuildMI(*mBB, MI, DL, mTII->get((isSWSExtLoadInst(MI)
- ? ((is64bit) ? AMDIL::UAVRAWLOADCACHED64_i16
- : AMDIL::UAVRAWLOADCACHED_i16) :
- ((is64bit) ? AMDIL::UAVRAWLOADCACHED64_u16
- : AMDIL::UAVRAWLOADCACHED_u16))),
- AMDIL::Rx1011)
- .addReg(addyReg)
- .addImm(ID);
+ ? ((is64bit) ? AMDIL::
+ UAVRAW64LOADCACHEDi16
+ : AMDIL::UAVRAW32LOADCACHEDi16) :
+ ((is64bit) ? AMDIL::
+ UAVRAW64LOADCACHEDu16
+ : AMDIL::UAVRAW32LOADCACHEDu16))),
+ dataReg)
+ .addReg(addyReg)
+ .addImm(ID);
} else {
BuildMI(*mBB, MI, DL, mTII->get((isSWSExtLoadInst(MI)
- ? ((is64bit) ? AMDIL::UAVRAWLOAD64_i16 : AMDIL::UAVRAWLOAD_i16) :
- ((is64bit) ? AMDIL::UAVRAWLOAD64_u16 : AMDIL::UAVRAWLOAD_u16))),
- AMDIL::Rx1011)
- .addReg(addyReg)
- .addImm(ID);
+ ? ((is64bit) ? AMDIL::UAVRAW64LOADi16 :
+ AMDIL::UAVRAW32LOADi16) :
+ ((is64bit) ? AMDIL::UAVRAW64LOADu16 :
+ AMDIL::UAVRAW32LOADu16))),
+ dataReg)
+ .addReg(addyReg)
+ .addImm(ID);
}
break;
case 4:
if (cacheable) {
BuildMI(*mBB, MI, DL, mTII->get(
- (is64bit) ? AMDIL::UAVRAWLOADCACHED64_i32 : AMDIL::UAVRAWLOADCACHED_i32),
- AMDIL::Rx1011)
+ (is64bit) ? AMDIL::UAVRAW64LOADCACHEDi32 : AMDIL::
+ UAVRAW32LOADCACHEDi32),
+ dataReg)
.addReg(addyReg)
.addImm(ID);
} else {
BuildMI(*mBB, MI, DL, mTII->get(
- (is64bit) ? AMDIL::UAVRAWLOAD64_i32 : AMDIL::UAVRAWLOAD_i32),
- AMDIL::Rx1011)
+ (is64bit) ? AMDIL::UAVRAW64LOADi32 : AMDIL::UAVRAW32LOADi32),
+ dataReg)
.addReg(addyReg)
.addImm(ID);
}
break;
case 8:
if (cacheable) {
- if (aligned) {
- BuildMI(*mBB, MI, DL, mTII->get(
- (is64bit) ? AMDIL::UAVRAWLOADCACHEDALIGNED64_v2i32
- : AMDIL::UAVRAWLOADCACHEDALIGNED_v2i32),
- AMDIL::Rxy1011).addReg(addyReg).addImm(ID);
- } else {
- BuildMI(*mBB, MI, DL, mTII->get(
- (is64bit) ? AMDIL::UAVRAWLOADCACHED64_v2i32 : AMDIL::UAVRAWLOADCACHED_v2i32),
- AMDIL::Rxy1011).addReg(addyReg).addImm(ID);
- }
+ BuildMI(*mBB, MI, DL, mTII->get(
+ (is64bit) ? AMDIL::UAVRAW64LOADCACHEDALIGNEDv2i32
+ : AMDIL::UAVRAW32LOADCACHEDALIGNEDv2i32),
+ AMDIL::Rxy1011).addReg(addyReg).addImm(ID);
} else {
BuildMI(*mBB, MI, DL, mTII->get(
- (is64bit) ? AMDIL::UAVRAWLOAD64_v2i32 : AMDIL::UAVRAWLOAD_v2i32),
- AMDIL::Rxy1011)
- .addReg(addyReg)
- .addImm(ID);
+ (is64bit) ? AMDIL::UAVRAW64LOADv2i32 : AMDIL::UAVRAW32LOADv2i32),
+ AMDIL::Rxy1011).addReg(addyReg).addImm(ID);
}
+ BuildMI(*mBB, MI, DL, mTII->get(AMDIL::COPY), dataReg)
+ .addReg(AMDIL::Rxy1011);
break;
};
- expandPackedData(MI);
- unsigned dataReg = expandExtendLoad(MI);
- if (!dataReg) {
- dataReg = getDataReg(MI);
- }
- BuildMI(*mBB, MI, MI->getDebugLoc(),
- mTII->get(getMoveInstFromID(
- MI->getDesc().OpInfo[0].RegClass)))
- .addOperand(MI->getOperand(0))
- .addReg(dataReg);
+ expandPackedData(MI, dataReg);
+ expandExtendLoad(MI, dataReg);
MI->getOperand(0).setReg(dataReg);
}
-
void
-AMDILSIIOExpansion::expandGlobalStore(MachineInstr *MI)
+AMDILSIIOExpansionImpl::expandGlobalStore(MachineInstr *MI)
{
+ uint32_t addyReg = MI->getOperand(1).getReg();
+ uint32_t dataReg = MI->getOperand(0).getReg();
// These instructions are expandted before the current MI.
- AMDIL789IOExpansion::expandStoreSetupCode(MI);
+ AMDIL789IOExpansionImpl::expandStoreSetupCode(MI, addyReg, dataReg);
uint32_t ID = getPointerID(MI);
mKM->setOutputInst();
- bool is64bit = is64bitLSOp(TM, MI);
+ bool is64bit = is64bitLSOp(MI);
DebugLoc DL = MI->getDebugLoc();
- uint32_t addyReg = (is64bit) ? AMDIL::Rxy1010 : AMDIL::Rx1010;
switch (getMemorySize(MI)) {
default:
BuildMI(*mBB, MI, DL, mTII->get(
- (is64bit) ? AMDIL::UAVRAWSTORE64_v4i32 :
- AMDIL::UAVRAWSTORE_v4i32), AMDIL::MEM)
+ (is64bit) ? AMDIL::UAVRAW64STOREv4i32 :
+ AMDIL::UAVRAW32STOREv4i32), AMDIL::MEM)
.addReg(addyReg)
- .addReg(AMDIL::R1011)
+ .addReg(dataReg)
.addImm(ID);
break;
case 1:
BuildMI(*mBB, MI, DL, mTII->get(
- (is64bit) ? AMDIL::UAVRAWSTORE64_i8 :
- AMDIL::UAVRAWSTORE_i8), AMDIL::MEMx)
+ (is64bit) ? AMDIL::UAVRAW64STOREi8 :
+ AMDIL::UAVRAW32STOREi8), AMDIL::MEMx)
.addReg(addyReg)
- .addReg(AMDIL::Rx1011)
+ .addReg(dataReg)
.addImm(ID);
break;
case 2:
BuildMI(*mBB, MI, DL, mTII->get(
- (is64bit) ? AMDIL::UAVRAWSTORE64_i16 :
- AMDIL::UAVRAWSTORE_i16), AMDIL::MEMx)
+ (is64bit) ? AMDIL::UAVRAW64STOREi16 :
+ AMDIL::UAVRAW32STOREi16), AMDIL::MEMx)
.addReg(addyReg)
- .addReg(AMDIL::Rx1011)
+ .addReg(dataReg)
.addImm(ID);
break;
case 4:
BuildMI(*mBB, MI, DL, mTII->get(
- (is64bit) ? AMDIL::UAVRAWSTORE64_i32 :
- AMDIL::UAVRAWSTORE_i32), AMDIL::MEMx)
+ (is64bit) ? AMDIL::UAVRAW64STOREi32 :
+ AMDIL::UAVRAW32STOREi32), AMDIL::MEMx)
.addReg(addyReg)
- .addReg(AMDIL::Rx1011)
+ .addReg(dataReg)
.addImm(ID);
break;
case 8:
BuildMI(*mBB, MI, DL, mTII->get(
- (is64bit) ? AMDIL::UAVRAWSTORE64_v2i32 :
- AMDIL::UAVRAWSTORE_v2i32), AMDIL::MEMxy)
+ (is64bit) ? AMDIL::UAVRAW64STOREv2i32 :
+ AMDIL::UAVRAW32STOREv2i32), AMDIL::MEMxy)
.addReg(addyReg)
- .addReg(AMDIL::Rxy1011)
+ .addReg(dataReg)
.addImm(ID);
break;
};
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSIIOExpansion.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSIIOExpansion.h?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSIIOExpansion.h (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSIIOExpansion.h Wed Sep 12 12:43:34 2012
@@ -14,29 +14,38 @@
#ifndef _AMDIL_SIIO_EXPANSION_H_
#define _AMDIL_SIIO_EXPANSION_H_
#include "AMDILIOExpansion.h"
-namespace llvm
-{
+namespace llvm {
// Class that expands IO instructions for the SI family of devices.
// The Global Load/Store functions need to be overloaded from the EG
// class as an arena is not a valid operation on SI, but are valid
// on the EG/NI devices.
-class AMDILSIIOExpansion : public AMDILEGIOExpansion
-{
+class AMDILSIIOExpansionImpl : public AMDILEGIOExpansionImpl {
public:
- AMDILSIIOExpansion(TargetMachine &tm, CodeGenOpt::Level OptLevel);
- virtual ~AMDILSIIOExpansion();
- const char* getPassName() const;
+ AMDILSIIOExpansionImpl(MachineFunction& mf)
+ : AMDILEGIOExpansionImpl(mf) {
+ };
+ virtual ~AMDILSIIOExpansionImpl() {
+ };
protected:
virtual bool
- isIOInstruction(TargetMachine &TM, MachineInstr *MI);
+ isIOInstruction(MachineInstr *MI);
virtual void
- expandIOInstruction(TargetMachine &TM, MachineInstr *MI);
+ expandIOInstruction(MachineInstr *MI);
void
expandGlobalStore(MachineInstr *MI);
void
expandGlobalLoad(MachineInstr *MI);
virtual bool
isCacheableOp(MachineInstr* MI);
-}; // class AMDILSIIOExpansion
+}; // class AMDILSIIOExpansionImpl
+
+class AMDILSIIOExpansion : public MachineFunctionPass {
+public:
+ static char ID;
+public:
+ AMDILSIIOExpansion();
+ virtual const char* getPassName() const;
+ bool runOnMachineFunction(MachineFunction &MF);
+};
} // namespace llvm
#endif // _AMDIL_SIIO_EXPANSION_H_
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSIPointerManager.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSIPointerManager.cpp?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSIPointerManager.cpp (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSIPointerManager.cpp Wed Sep 12 12:43:34 2012
@@ -41,21 +41,6 @@
#include <queue>
#include <iomanip>
using namespace llvm;
-namespace
-{
-class AMDILSIPointerManagerImpl : public AMDILPointerManagerImpl
-{
-public:
- AMDILSIPointerManagerImpl(MachineFunction &mf, TargetMachine &tm)
- : AMDILPointerManagerImpl(mf, tm) {}
- virtual ~AMDILSIPointerManagerImpl() {}
-protected:
- virtual void annotateBytePtrs();
- virtual void annotateRawPtrs();
- virtual void annotateCacheablePtrs();
- virtual void annotateCacheableInstrs();
-};
-}
// A byte pointer is a pointer that along the pointer path has a
// byte store assigned to it.
@@ -99,7 +84,7 @@
if (mAMI->isKernel(funcName)) {
const AMDILKernel *krnl = mAMI->getKernel(funcName);
curRes.bits.ResourceID = mAMI->getConstPtrCB(krnl,
- siBegin->second->getName());
+ siBegin->second->getName());
curRes.bits.HardwareInst = 1;
} else {
curRes.bits.ResourceID = STM->device()
@@ -111,7 +96,7 @@
// the device to use as the ResourceID
curRes.bits.ResourceID = STM->device()
->getResourceID(AMDILDevice::LDS_ID);
- if (isAtomicInst(TM, *miBegin)) {
+ if (isAtomicInst(*miBegin)) {
assert(curRes.bits.ResourceID && "Atomic resource ID "
"cannot be non-zero!");
MI->getOperand(MI->getNumOperands()-1)
@@ -123,7 +108,7 @@
// the device to use as the ResourceID
curRes.bits.ResourceID = STM->device()
->getResourceID(AMDILDevice::GDS_ID);
- if (isAtomicInst(TM, *miBegin)) {
+ if (isAtomicInst(*miBegin)) {
assert(curRes.bits.ResourceID && "Atomic resource ID "
"cannot be non-zero!");
(*miBegin)->getOperand((*miBegin)->getNumOperands()-1)
@@ -142,7 +127,8 @@
curRes.bits.ResourceID = STM->device()
->getResourceID(AMDILDevice::GLOBAL_ID);
if (MI->getOperand(MI->getNumOperands() - 1).isImm()) {
- MI->getOperand(MI->getNumOperands() - 1).setImm(curRes.bits.ResourceID);
+ MI->getOperand(MI->getNumOperands() - 1).setImm(
+ curRes.bits.ResourceID);
}
if (DEBUGME) {
dbgs() << "Annotating pointer as default. Inst: ";
@@ -159,7 +145,6 @@
}
}
}
-
// A raw pointer is any pointer that does not have byte store in its path.
// This function is unique to SI devices as arena is not part of it.
void
@@ -216,7 +201,7 @@
if (mAMI->isKernel(funcName)) {
const AMDILKernel *krnl = mAMI->getKernel(funcName);
curRes.bits.ResourceID = mAMI->getConstPtrCB(krnl,
- siBegin->second->getName());
+ siBegin->second->getName());
curRes.bits.HardwareInst = 1;
} else {
curRes.bits.ResourceID = STM->device()
@@ -228,7 +213,7 @@
// the device to use as the ResourceID
curRes.bits.ResourceID = STM->device()
->getResourceID(AMDILDevice::LDS_ID);
- if (isAtomicInst(TM, *miBegin)) {
+ if (isAtomicInst(*miBegin)) {
assert(curRes.bits.ResourceID && "Atomic resource ID "
"cannot be non-zero!");
(*miBegin)->getOperand((*miBegin)->getNumOperands()-1)
@@ -240,7 +225,7 @@
// the device to use as the ResourceID
curRes.bits.ResourceID = STM->device()
->getResourceID(AMDILDevice::GDS_ID);
- if (isAtomicInst(TM, *miBegin)) {
+ if (isAtomicInst(*miBegin)) {
assert(curRes.bits.ResourceID && "Atomic resource ID "
"cannot be non-zero!");
(*miBegin)->getOperand((*miBegin)->getNumOperands()-1)
@@ -260,7 +245,7 @@
curRes.bits.ResourceID = STM->device()
->getResourceID(AMDILDevice::GLOBAL_ID);
}
- if (isAtomicInst(TM, *miBegin)) {
+ if (isAtomicInst(*miBegin)) {
(*miBegin)->getOperand((*miBegin)->getNumOperands()-1)
.setImm(curRes.bits.ResourceID);
}
@@ -279,7 +264,6 @@
setAsmPrinterFlags(*miBegin, curRes);
}
}
-
}
// This function annotates the cacheable pointers with the
// CacheableRead bit.
@@ -333,18 +317,27 @@
setAsmPrinterFlags(*miBegin, curRes);
}
}
-
-AMDILSIPointerManager::AMDILSIPointerManager(
- TargetMachine &tm,
- CodeGenOpt::Level OL) :
- AMDILPointerManager(tm, OL)
+namespace llvm
{
+extern void initializeAMDILSIPointerManagerPass(llvm::PassRegistry&);
}
-AMDILSIPointerManager::~AMDILSIPointerManager()
+char AMDILSIPointerManager::ID = 0;
+INITIALIZE_PASS(AMDILSIPointerManager, "si-pointer-manager",
+ "AMDIL SI Pointer Manager", false, false);
+
+AMDILSIPointerManager::AMDILSIPointerManager()
+ : MachineFunctionPass(ID)
{
+ initializeAMDILSIPointerManagerPass(*PassRegistry::getPassRegistry());
+}
+void
+AMDILSIPointerManager::getAnalysisUsage(AnalysisUsage &AU) const
+{
+ AU.setPreservesAll();
+ AU.addRequiredID(MachineDominatorsID);
+ MachineFunctionPass::getAnalysisUsage(AU);
}
-
const char*
AMDILSIPointerManager::getPassName() const
{
@@ -359,10 +352,9 @@
MF.dump();
}
+ const TargetMachine& TM = MF.getTarget();
AMDILSIPointerManagerImpl impl(MF, TM);
bool changed = impl.perform();
- clearTempMIFlags(MF);
-
return changed;
}
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSIPointerManager.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSIPointerManager.h?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSIPointerManager.h (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSIPointerManager.h Wed Sep 12 12:43:34 2012
@@ -14,26 +14,27 @@
#ifndef _AMDIL_SI_POINTER_MANAGER_H_
#define _AMDIL_SI_POINTER_MANAGER_H_
#include "AMDILPointerManager.h"
-namespace llvm
-{
+namespace llvm {
class MachineFunction;
// The pointer manager for Southern Island
// devices. This pointer manager allocates and trackes
// cached memory, raw resources and
// whether multi-uav is utilized or not.
-class AMDILSIPointerManager : public AMDILPointerManager
+class AMDILSIPointerManager : public MachineFunctionPass
{
public:
- AMDILSIPointerManager(
- TargetMachine &tm,
- CodeGenOpt::Level OL);
- virtual ~AMDILSIPointerManager();
+ AMDILSIPointerManager();
+ virtual ~AMDILSIPointerManager() {
+ };
virtual const char*
getPassName() const;
virtual bool
runOnMachineFunction(MachineFunction &F);
+ virtual void
+ getAnalysisUsage(AnalysisUsage &AU) const;
+ static char ID;
private:
-}; // class AMDILEGPointerManager
+}; // class AMDILSIPointerManager
} // end llvm namespace
#endif // _AMDIL_SI_POINTER_MANAGER_H_
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSubtarget.cpp?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSubtarget.cpp (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSubtarget.cpp Wed Sep 12 12:43:34 2012
@@ -30,13 +30,16 @@
#define GET_SUBTARGETINFO_TARGET_DESC
#include "AMDILGenSubtarget.inc"
-AMDILSubtarget::AMDILSubtarget(llvm::StringRef TT, llvm::StringRef GPU, llvm::StringRef FS) : AMDILGenSubtargetInfo( TT, GPU, FS )
+AMDILSubtarget::AMDILSubtarget(llvm::StringRef TT,
+ llvm::StringRef GPU,
+ llvm::StringRef FS) : AMDILGenSubtargetInfo( TT,
+ GPU,
+ FS )
{
memset(CapsOverride, 0, sizeof(*CapsOverride)
* AMDILDeviceInfo::MaxNumberCapabilities);
mIs64bit = false;
mFlatAddress = false;
- mVersion = -1U;
mMetadata30 = false;
SmallVector<StringRef, DEFAULT_VEC_SLOTS> Features;
SplitString(FS, Features, ",");
@@ -63,20 +66,11 @@
useTest = true;
#endif
} else if (Features[x].startswith("+cal")) {
- SmallVector<StringRef, DEFAULT_VEC_SLOTS> version;
- SplitString(Features[x], version, "=");
- mVersion = ::atoi(version[1].data());
} else {
if (newFeatures.length() > 0) newFeatures += ',';
newFeatures += Features[x];
}
}
- // If we don't have a version then set it to
- // -1 which enables everything. This is for
- // offline devices.
- if (!mVersion) {
- mVersion = (uint32_t)-1;
- }
for (int x = 0; x < 3; ++x) {
if (!mDefaultSize[x]) {
mDefaultSize[x] = 1;
@@ -108,35 +102,29 @@
return CapsOverride[caps];
}
bool
-AMDILSubtarget::isApple() const
-{
+AMDILSubtarget::isApple() const {
return false;
}
-
bool
AMDILSubtarget::overridesFlatAS() const
{
return mFlatAddress;
}
-
bool
AMDILSubtarget::is64bit() const
{
return mIs64bit;
}
-
bool
AMDILSubtarget::isTargetELF() const
{
return false;
}
-
bool
AMDILSubtarget::supportMetadata30() const
{
return mMetadata30;
}
-
size_t
AMDILSubtarget::getDefaultSize(uint32_t dim) const
{
@@ -146,12 +134,6 @@
return mDefaultSize[dim];
}
}
-uint32_t
-AMDILSubtarget::calVersion() const
-{
- return mVersion;
-}
-
AMDILKernelManager*
AMDILSubtarget::getKernelManager() const
{
@@ -167,22 +149,23 @@
{
if (!mDevice) {
if (is64bit()) {
- return std::string("e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16"
- "-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:32:32"
- "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64"
- "-v96:128:128-v128:128:128-v192:256:256-v256:256:256"
- "-v512:512:512-v1024:1024:1024-v2048:2048:2048-a0:0:64");
+ return std::string(
+ "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16"
+ "-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:32:32"
+ "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64"
+ "-v96:128:128-v128:128:128-v192:256:256-v256:256:256"
+ "-v512:512:512-v1024:1024:1024-v2048:2048:2048-a0:0:64");
} else {
- return std::string("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16"
- "-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:32:32"
- "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64"
- "-v96:128:128-v128:128:128-v192:256:256-v256:256:256"
- "-v512:512:512-v1024:1024:1024-v2048:2048:2048-a0:0:64");
+ return std::string(
+ "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16"
+ "-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:32:32"
+ "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64"
+ "-v96:128:128-v128:128:128-v192:256:256-v256:256:256"
+ "-v512:512:512-v1024:1024:1024-v2048:2048:2048-a0:0:64");
}
}
return mDevice->getDataLayout();
}
-
std::string
AMDILSubtarget::getDeviceName() const
{
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSubtarget.h?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSubtarget.h (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSubtarget.h Wed Sep 12 12:43:34 2012
@@ -24,13 +24,11 @@
#include <string>
#include <cstdlib>
#define MAX_CB_SIZE (1 << 16)
-namespace llvm
-{
+namespace llvm {
class Module;
class AMDILKernelManager;
class AMDILDevice;
-class AMDILSubtarget : public AMDILGenSubtargetInfo
-{
+class AMDILSubtarget : public AMDILGenSubtargetInfo {
private:
bool CapsOverride[AMDILDeviceInfo::MaxNumberCapabilities];
mutable AMDILKernelManager *mKM;
@@ -60,8 +58,6 @@
std::string getDataLayout() const;
std::string getDeviceName() const;
virtual size_t getDefaultSize(uint32_t dim) const;
- // Return the version of CAL that the backend should target.
- uint32_t calVersion() const;
// ParseSubtargetFeatures - Parses features string setting specified
// subtarget options. Definition of function is
//auto generated by tblgen.
@@ -69,9 +65,7 @@
ParseSubtargetFeatures(
llvm::StringRef CPU,
llvm::StringRef FS);
-
};
-
} // end namespace llvm
#endif // AMDILSUBTARGET_H_
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSwizzleEncoder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSwizzleEncoder.cpp?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSwizzleEncoder.cpp (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSwizzleEncoder.cpp Wed Sep 12 12:43:34 2012
@@ -14,7 +14,7 @@
//
//===----------------------------------------------------------------------===//
-#define DEBUG_TYPE "SwizzleEncoder"
+#define DEBUG_TYPE "swizzleencoder"
#if !defined(NDEBUG)
#define DEBUGME (DebugFlag && isCurrentDebugType(DEBUG_TYPE))
#else
@@ -57,17 +57,12 @@
/// instruction.
static OpSwizzle getCustomDstSwizzle(MachineInstr *MI);
-/// Determine if the instruction is a custom vector instruction
-/// that needs a unique swizzle type.
-static bool isCustomVectorInst(MachineInstr *MI);
-
/// Encode the new swizzle for the vector instruction.
static void encodeVectorInst(MachineInstr *MI, bool mDebug);
/// Helper function to dump the operand for the machine instruction
/// and the relevant target flags.
static void dumpOperand(MachineInstr *MI, unsigned opNum);
-namespace llvm
-{
+namespace llvm {
FunctionPass*
createAMDILSwizzleEncoder(TargetMachine &TM, CodeGenOpt::Level OptLevel)
{
@@ -76,25 +71,22 @@
}
AMDILSwizzleEncoder::AMDILSwizzleEncoder(TargetMachine &tm,
- CodeGenOpt::Level OptLevel) :
+ CodeGenOpt::Level OptLevel) :
MachineFunctionPass(ID)
{
mDebug = DEBUGME;
opt = OptLevel;
}
-
const char* AMDILSwizzleEncoder::getPassName() const
{
return "AMD IL Swizzle Encoder Pass";
}
-
bool AMDILSwizzleEncoder::runOnMachineFunction(MachineFunction &MF)
{
// Encode swizzles in instruction operands.
encodeSwizzles(MF, mDebug);
return true;
}
-
/// Dump the operand swizzle information to the dbgs() stream.
void dumpOperand(MachineInstr *MI, unsigned opNum)
{
@@ -104,172 +96,98 @@
<< " Operand: " << opNum << " SwizID: "
<< (unsigned)swizID.bits.swizzle
<< " Swizzle: " << (swizID.bits.dst
- ? getDstSwizzle(swizID.bits.swizzle)
- : getSrcSwizzle(swizID.bits.swizzle)) << "\n";
-
+ ? getDstSwizzle(swizID.bits.swizzle)
+ : getSrcSwizzle(swizID.bits.swizzle)) << "\n";
}
-
// This function checks for instructions that don't have
// normal swizzle patterns to their source operands. These have to be
// handled on a case by case basis.
-bool isCustomSrcInst(MachineInstr *MI, unsigned opNum)
-{
+bool isCustomSrcInst(MachineInstr *MI, unsigned opNum) {
+ if (!MI->getDesc().getNumOperands()) return false;
unsigned opcode = MI->getOpcode();
- switch (opcode) {
- default:
- break;
- case AMDIL::LDSLOAD:
- case AMDIL::LDSLOAD_i8:
- case AMDIL::LDSLOAD_u8:
- case AMDIL::LDSLOAD_i16:
- case AMDIL::LDSLOAD_u16:
- case AMDIL::LDSSTORE:
- case AMDIL::LDSSTORE_i8:
- case AMDIL::LDSSTORE_i16:
- case AMDIL::GDSLOAD:
- case AMDIL::GDSSTORE:
- case AMDIL::SCRATCHLOAD:
- case AMDIL::CBLOAD:
- case AMDIL::UAVARENALOAD_i8:
- case AMDIL::UAVARENALOAD_i16:
- case AMDIL::UAVARENALOAD_i32:
- case AMDIL::UAVARENASTORE_i8:
- case AMDIL::UAVARENASTORE_i16:
- case AMDIL::UAVARENASTORE_i32:
- case AMDIL::LDSLOAD64:
- case AMDIL::LDSLOAD64_i8:
- case AMDIL::LDSLOAD64_u8:
- case AMDIL::LDSLOAD64_i16:
- case AMDIL::LDSLOAD64_u16:
- case AMDIL::LDSSTORE64:
- case AMDIL::LDSSTORE64_i8:
- case AMDIL::LDSSTORE64_i16:
- case AMDIL::GDSLOAD64:
- case AMDIL::GDSSTORE64:
- case AMDIL::SCRATCHLOAD64:
- case AMDIL::CBLOAD64:
- return true;
- case AMDIL::CMOVLOG_f64:
- case AMDIL::CMOVLOG_i64:
- return (opNum == 1) ? true : false;
- case AMDIL::SEMAPHORE_INIT:
- case AMDIL::SEMAPHORE_WAIT:
- case AMDIL::SEMAPHORE_SIGNAL:
- case AMDIL::APPEND_CONSUME:
- case AMDIL::APPEND_ALLOC:
- case AMDIL::APPEND64_CONSUME:
- case AMDIL::APPEND64_ALLOC:
- case AMDIL::LLO:
- case AMDIL::LLO_v2i64:
- case AMDIL::LHI:
- case AMDIL::LHI_v2i64:
- case AMDIL::LCREATE:
- case AMDIL::LCREATE_v2i64:
- case AMDIL::CALL:
- case AMDIL::RETURN:
- case AMDIL::RETDYN:
- case AMDIL::DHI:
- case AMDIL::DLO:
- case AMDIL::DCREATE:
- case AMDIL::DHI_v2f64:
- case AMDIL::DLO_v2f64:
- case AMDIL::DCREATE_v2f64:
- case AMDIL::HILO_BITOR_v2i32:
- case AMDIL::HILO_BITOR_v4i16:
- case AMDIL::HILO_BITOR_v2i64:
- case AMDIL::CONTINUE_LOGICALNZ_f64:
- case AMDIL::BREAK_LOGICALNZ_f64:
- case AMDIL::IF_LOGICALNZ_f64:
- case AMDIL::CONTINUE_LOGICALZ_f64:
- case AMDIL::BREAK_LOGICALZ_f64:
- case AMDIL::IF_LOGICALZ_f64:
- case AMDIL::CONTINUE_LOGICALNZ_i64:
- case AMDIL::BREAK_LOGICALNZ_i64:
- case AMDIL::IF_LOGICALNZ_i64:
- case AMDIL::CONTINUE_LOGICALZ_i64:
- case AMDIL::BREAK_LOGICALZ_i64:
- case AMDIL::IF_LOGICALZ_i64:
+ unsigned regClass = MI->getDesc().OpInfo[0].RegClass;
+ if ((isPtrLoadInst(MI) || isPtrStoreInst(MI))
+ && (isScratchInst(MI)
+ || isCBInst(MI)
+ || isUAVArenaInst(MI))
+ && (regClass == AMDIL::GPRI16RegClassID
+ || regClass == AMDIL::GPRI8RegClassID
+ || regClass == AMDIL::GPRI32RegClassID
+ || regClass == AMDIL::GPRF32RegClassID
+ )
+ && !isExtLoadInst(MI)
+ && !isTruncStoreInst(MI)) {
return true;
- case AMDIL::UBIT_INSERT_i32:
- case AMDIL::UBIT_INSERT_v2i32:
- case AMDIL::UBIT_INSERT_v4i32:
- return (opNum == 1 || opNum == 2);
- };
- return false;
-}
+ }
+ uint32_t maskVal =
+ (MI->getDesc().TSFlags & AMDID::SWZLMASK) >> AMDID::SWZLSHFT;
+ return (maskVal ? (maskVal & (1ULL << opNum)) : false);
+}
+#define GENERATE_1ARG_CASE(A) \
+case A ## r: \
+case A ## i:
+#define GENERATE_2ARG_CASE(A) \
+ GENERATE_1ARG_CASE(A ## r) \
+ GENERATE_1ARG_CASE(A ## i)
+#define GENERATE_3ARG_CASE(A) \
+ GENERATE_2ARG_CASE(A ## r) \
+ GENERATE_2ARG_CASE(A ## i)
+#define GENERATE_4ARG_CASE(A) \
+ GENERATE_3ARG_CASE(A ## r) \
+ GENERATE_3ARG_CASE(A ## i)
// This function returns the OpSwizzle with the custom swizzle set
// correclty for source operands.
-OpSwizzle getCustomSrcSwizzle(MachineInstr *MI, unsigned opNum)
-{
+OpSwizzle getCustomSrcSwizzle(MachineInstr *MI, unsigned opNum) {
OpSwizzle opSwiz;
opSwiz.u8all = 0;
unsigned opcode = MI->getOpcode();
unsigned reg = (MI->getOperand(opNum).isReg()
? MI->getOperand(opNum).getReg() : 0);
- switch (opcode) {
- default:
- break;
- case AMDIL::SCRATCHLOAD:
- case AMDIL::CBLOAD:
- case AMDIL::LDSLOAD:
- case AMDIL::LDSLOAD_i8:
- case AMDIL::LDSLOAD_u8:
- case AMDIL::LDSLOAD_i16:
- case AMDIL::LDSLOAD_u16:
- case AMDIL::GDSLOAD:
- case AMDIL::GDSSTORE:
- case AMDIL::LDSSTORE:
- case AMDIL::LDSSTORE_i8:
- case AMDIL::LDSSTORE_i16:
- case AMDIL::SCRATCHLOAD64:
- case AMDIL::CBLOAD64:
- case AMDIL::LDSLOAD64:
- case AMDIL::LDSLOAD64_i8:
- case AMDIL::LDSLOAD64_u8:
- case AMDIL::LDSLOAD64_i16:
- case AMDIL::LDSLOAD64_u16:
- case AMDIL::GDSLOAD64:
- case AMDIL::GDSSTORE64:
- case AMDIL::LDSSTORE64:
- case AMDIL::LDSSTORE64_i8:
- case AMDIL::LDSSTORE64_i16:
- opSwiz.bits.swizzle = (opNum == 1)
- ? AMDIL_SRC_XXXX: AMDIL_SRC_DFLT;
- break;
- case AMDIL::UAVARENALOAD_i8:
- case AMDIL::UAVARENALOAD_i16:
- case AMDIL::UAVARENALOAD_i32:
- case AMDIL::UAVARENASTORE_i8:
- case AMDIL::UAVARENASTORE_i16:
- case AMDIL::UAVARENASTORE_i32:
- if (isXComponentReg(reg)) {
- opSwiz.bits.swizzle = AMDIL_SRC_XXXX;
- } else if (isYComponentReg(reg)) {
- opSwiz.bits.swizzle = AMDIL_SRC_YYYY;
- } else if (isZComponentReg(reg)) {
- opSwiz.bits.swizzle = AMDIL_SRC_ZZZZ;
- } else if (isWComponentReg(reg)) {
- opSwiz.bits.swizzle = AMDIL_SRC_WWWW;
- }
- if (opNum != 1) {
- opSwiz.bits.swizzle = AMDIL_SRC_DFLT;
+ unsigned regClass = MI->getDesc().OpInfo[0].RegClass;
+ if ((isPtrLoadInst(MI) || isPtrStoreInst(MI))
+ && (isScratchInst(MI)
+ || isCBInst(MI)
+ || isUAVArenaInst(MI))
+ && (regClass == AMDIL::GPRI16RegClassID
+ || regClass == AMDIL::GPRI8RegClassID
+ || regClass == AMDIL::GPRI32RegClassID
+ || regClass == AMDIL::GPRF32RegClassID
+ )
+ && !isExtLoadInst(MI)
+ && !isTruncStoreInst(MI)) {
+ if (isUAVArenaInst(MI)) {
+ if (isXComponentReg(reg)) {
+ opSwiz.bits.swizzle = AMDIL_SRC_XXXX;
+ } else if (isYComponentReg(reg)) {
+ opSwiz.bits.swizzle = AMDIL_SRC_YYYY;
+ } else if (isZComponentReg(reg)) {
+ opSwiz.bits.swizzle = AMDIL_SRC_ZZZZ;
+ } else if (isWComponentReg(reg)) {
+ opSwiz.bits.swizzle = AMDIL_SRC_WWWW;
+ }
+ if (opNum != 1) {
+ opSwiz.bits.swizzle = AMDIL_SRC_DFLT;
+ }
+ } else {
+ opSwiz.bits.swizzle = (opNum == 1)
+ ? AMDIL_SRC_XXXX : AMDIL_SRC_DFLT;
}
- break;
- case AMDIL::SEMAPHORE_INIT:
- case AMDIL::SEMAPHORE_WAIT:
- case AMDIL::SEMAPHORE_SIGNAL:
- case AMDIL::APPEND_CONSUME:
- case AMDIL::APPEND_ALLOC:
- case AMDIL::APPEND64_CONSUME:
- case AMDIL::APPEND64_ALLOC:
- case AMDIL::CALL:
- case AMDIL::RETURN:
- case AMDIL::RETDYN:
+ return opSwiz;
+ }
+ if (isSemaphoreInst(MI)
+ || isAppendInst(MI)
+ || opcode == AMDIL::CALL
+ || opcode == AMDIL::RETURN
+ || opcode == AMDIL::RETDYN) {
opSwiz.bits.swizzle = AMDIL_SRC_DFLT;
+ return opSwiz;
+ }
+ switch (opcode) {
+ default:
break;
- case AMDIL::CMOVLOG_f64:
- case AMDIL::CMOVLOG_i64:
+ GENERATE_3ARG_CASE(AMDIL::SELECTf64)
+ GENERATE_3ARG_CASE(AMDIL::SELECTi64)
assert(opNum == 1 && "Only operand number 1 is custom!");
if (isZWComponentReg(reg)) {
opSwiz.bits.swizzle = AMDIL_SRC_ZZZZ;
@@ -277,8 +195,8 @@
opSwiz.bits.swizzle = AMDIL_SRC_XXXX;
}
break;
- case AMDIL::DHI:
- case AMDIL::LLO:
+ case AMDIL::DHIf64r:
+ case AMDIL::LLOi64r:
if (isZWComponentReg(reg)) {
opSwiz.bits.swizzle = AMDIL_SRC_Z000;
} else {
@@ -294,12 +212,12 @@
opSwiz.bits.swizzle += 3;
}
break;
- case AMDIL::DHI_v2f64:
- case AMDIL::LLO_v2i64:
+ case AMDIL::DHIv2f64r:
+ case AMDIL::LLOv2i64r:
opSwiz.bits.swizzle = AMDIL_SRC_XZXZ;
break;
- case AMDIL::DLO:
- case AMDIL::LHI:
+ case AMDIL::DLOf64r:
+ case AMDIL::LHIi64r:
if (isZWComponentReg(reg)) {
opSwiz.bits.swizzle = AMDIL_SRC_W000;
} else {
@@ -316,11 +234,12 @@
opSwiz.bits.swizzle += 2;
}
break;
- case AMDIL::DLO_v2f64:
- case AMDIL::LHI_v2i64:
+ case AMDIL::DLOv2f64r:
+ case AMDIL::LHIv2i64r:
opSwiz.bits.swizzle = AMDIL_SRC_YWYW;
break;
- case AMDIL::DCREATE: {
+ case AMDIL::DCREATEf64rr:
+ {
unsigned swiz = AMDIL_SRC_X000;
if (isWComponentReg(reg)) {
swiz = AMDIL_SRC_W000;
@@ -336,11 +255,12 @@
opSwiz.bits.swizzle = swiz + (opNum == 1);
}
break;
- case AMDIL::DCREATE_v2f64:
+ case AMDIL::DCREATEv2f64rr:
opSwiz.bits.swizzle = (opNum == 1)
? AMDIL_SRC_0X0Y : AMDIL_SRC_X0Y0;
break;
- case AMDIL::LCREATE: {
+ case AMDIL::LCREATEi64rr:
+ {
unsigned swiz1 = (opNum == 1) ? AMDIL_SRC_X000 : AMDIL_SRC_0X00;
if (MI->getOperand(opNum).isReg()) {
reg = MI->getOperand(opNum).getReg();
@@ -359,25 +279,25 @@
opSwiz.bits.swizzle = swiz1;
}
break;
- case AMDIL::LCREATE_v2i64:
+ case AMDIL::LCREATEv2i64rr:
if (isXYComponentReg(reg)) {
opSwiz.bits.swizzle = opNum + AMDIL_SRC_YWYW;
} else {
opSwiz.bits.swizzle = opNum + AMDIL_SRC_YZW0;
}
break;
- case AMDIL::CONTINUE_LOGICALNZ_f64:
- case AMDIL::BREAK_LOGICALNZ_f64:
- case AMDIL::IF_LOGICALNZ_f64:
- case AMDIL::CONTINUE_LOGICALZ_f64:
- case AMDIL::BREAK_LOGICALZ_f64:
- case AMDIL::IF_LOGICALZ_f64:
- case AMDIL::CONTINUE_LOGICALNZ_i64:
- case AMDIL::BREAK_LOGICALNZ_i64:
- case AMDIL::IF_LOGICALNZ_i64:
- case AMDIL::CONTINUE_LOGICALZ_i64:
- case AMDIL::BREAK_LOGICALZ_i64:
- case AMDIL::IF_LOGICALZ_i64:
+ case AMDIL::CONTINUE_LOGICALNZf64r:
+ case AMDIL::BREAK_LOGICALNZf64r:
+ case AMDIL::IF_LOGICALNZf64r:
+ case AMDIL::CONTINUE_LOGICALZf64r:
+ case AMDIL::BREAK_LOGICALZf64r:
+ case AMDIL::IF_LOGICALZf64r:
+ case AMDIL::CONTINUE_LOGICALNZi64r:
+ case AMDIL::BREAK_LOGICALNZi64r:
+ case AMDIL::IF_LOGICALNZi64r:
+ case AMDIL::CONTINUE_LOGICALZi64r:
+ case AMDIL::BREAK_LOGICALZi64r:
+ case AMDIL::IF_LOGICALZi64r:
assert(opNum == 0
&& "Only operand numbers 0 is custom!");
case AMDIL::SWITCH:
@@ -389,7 +309,7 @@
assert(!"Found a case we don't handle!");
}
break;
- case AMDIL::UBIT_INSERT_i32:
+ GENERATE_4ARG_CASE(AMDIL::UBIT_INSERTi32)
assert((opNum == 1 || opNum == 2)
&& "Only operand numbers 1 or 2 is custom!");
if (isXComponentReg(reg)) {
@@ -402,7 +322,7 @@
opSwiz.bits.swizzle = AMDIL_SRC_WWWW;
}
break;
- case AMDIL::UBIT_INSERT_v2i32:
+ GENERATE_4ARG_CASE(AMDIL::UBIT_INSERTv2i32)
assert((opNum == 1 || opNum == 2)
&& "Only operand numbers 1 or 2 is custom!");
if (isXYComponentReg(reg)) {
@@ -411,15 +331,15 @@
opSwiz.bits.swizzle = AMDIL_SRC_ZWZW;
}
break;
- case AMDIL::UBIT_INSERT_v4i32:
+ GENERATE_4ARG_CASE(AMDIL::UBIT_INSERTv4i32)
assert((opNum == 1 || opNum == 2)
&& "Only operand numbers 1 or 2 is custom!");
opSwiz.bits.swizzle = AMDIL_SRC_DFLT;
break;
- case AMDIL::HILO_BITOR_v4i16:
+ case AMDIL::HILO_BITORv4i16rr:
opSwiz.bits.swizzle = AMDIL_SRC_XZXZ + (opNum - 1);
break;
- case AMDIL::HILO_BITOR_v2i32:
+ case AMDIL::HILO_BITORv2i32rr:
if (isXComponentReg(reg)) {
opSwiz.bits.swizzle = AMDIL_SRC_X000;
} else if (isYComponentReg(reg)) {
@@ -438,7 +358,8 @@
opSwiz.bits.swizzle += 3;
}
break;
- case AMDIL::HILO_BITOR_v2i64: {
+ case AMDIL::HILO_BITORv2i64rr:
+ {
unsigned offset = 0;
if (isXYComponentReg(reg)) {
@@ -453,105 +374,60 @@
opSwiz.bits.swizzle = offset;
}
break;
- };
+ }
return opSwiz;
}
+#undef GENERATE_3ARG_CASE
+#undef GENERATE_4ARG_CASE
// This function checks for instructions that don't have
// normal swizzle patterns to their destination operand.
// These have to be handled on a case by case basis.
-bool isCustomDstInst(MachineInstr *MI)
-{
+bool isCustomDstInst(MachineInstr *MI) {
+ if (!MI->getDesc().getNumOperands()) return false;
unsigned opcode = MI->getOpcode();
- switch (opcode) {
- default:
- break;
- case AMDIL::UAVARENASTORE_i8:
- case AMDIL::UAVARENASTORE_i16:
- case AMDIL::UAVARENASTORE_i32:
- case AMDIL::UAVARENALOAD_i8:
- case AMDIL::UAVARENALOAD_i16:
- case AMDIL::UAVARENALOAD_i32:
- case AMDIL::LDSLOAD:
- case AMDIL::LDSLOAD_i8:
- case AMDIL::LDSLOAD_u8:
- case AMDIL::LDSLOAD_i16:
- case AMDIL::LDSLOAD_u16:
- case AMDIL::LDSSTORE:
- case AMDIL::LDSSTORE_i8:
- case AMDIL::LDSSTORE_i16:
- case AMDIL::GDSLOAD:
- case AMDIL::GDSSTORE:
- case AMDIL::SEMAPHORE_INIT:
- case AMDIL::SEMAPHORE_WAIT:
- case AMDIL::SEMAPHORE_SIGNAL:
- case AMDIL::APPEND_CONSUME:
- case AMDIL::APPEND_ALLOC:
- case AMDIL::HILO_BITOR_v4i16:
- case AMDIL::HILO_BITOR_v2i64:
- // 64 bit IO Instructions
- case AMDIL::LDSLOAD64:
- case AMDIL::LDSLOAD64_i8:
- case AMDIL::LDSLOAD64_u8:
- case AMDIL::LDSLOAD64_i16:
- case AMDIL::LDSLOAD64_u16:
- case AMDIL::LDSSTORE64:
- case AMDIL::LDSSTORE64_i8:
- case AMDIL::LDSSTORE64_i16:
- case AMDIL::GDSLOAD64:
- case AMDIL::GDSSTORE64:
- case AMDIL::APPEND64_CONSUME:
- case AMDIL::APPEND64_ALLOC:
+ unsigned regClass = MI->getDesc().OpInfo[0].RegClass;
+ if ((isPtrLoadInst(MI) || isPtrStoreInst(MI))
+ && ( (isLDSInst(MI)
+ && (MI->getDesc().OpInfo[1].RegClass == AMDIL::GPRI16RegClassID
+ || MI->getDesc().OpInfo[1].RegClass == AMDIL::GPRI8RegClassID
+ || MI->getDesc().OpInfo[1].RegClass == AMDIL::GPRI32RegClassID
+ || MI->getDesc().OpInfo[1].RegClass == AMDIL::GPRI64RegClassID
+ || MI->getDesc().OpInfo[1].RegClass == AMDIL::GPRF32RegClassID))
+ || isGDSInst(MI)
+ || isScratchInst(MI)
+ || isCBInst(MI)
+ || isUAVArenaInst(MI))
+ && !isExtLoadInst(MI)
+ && !isTruncStoreInst(MI)) {
return true;
}
-
- return false;
+ return MI->getDesc().TSFlags & (1ULL << AMDID::SWZLDST);
}
// This function returns the OpSwizzle with the custom swizzle set
// correclty for destination operands.
-OpSwizzle getCustomDstSwizzle(MachineInstr *MI)
-{
+OpSwizzle getCustomDstSwizzle(MachineInstr *MI) {
OpSwizzle opSwiz;
opSwiz.u8all = 0;
unsigned opcode = MI->getOpcode();
opSwiz.bits.dst = 1;
unsigned reg = MI->getOperand(0).isReg() ?
MI->getOperand(0).getReg() : 0;
- switch (opcode) {
- case AMDIL::LDSLOAD:
- case AMDIL::LDSLOAD_i8:
- case AMDIL::LDSLOAD_u8:
- case AMDIL::LDSLOAD_i16:
- case AMDIL::LDSLOAD_u16:
- case AMDIL::LDSSTORE:
- case AMDIL::LDSSTORE_i8:
- case AMDIL::LDSSTORE_i16:
- case AMDIL::UAVARENALOAD_i8:
- case AMDIL::UAVARENALOAD_i16:
- case AMDIL::UAVARENALOAD_i32:
- case AMDIL::UAVARENASTORE_i8:
- case AMDIL::UAVARENASTORE_i16:
- case AMDIL::UAVARENASTORE_i32:
- case AMDIL::GDSLOAD:
- case AMDIL::GDSSTORE:
- case AMDIL::SEMAPHORE_INIT:
- case AMDIL::SEMAPHORE_WAIT:
- case AMDIL::SEMAPHORE_SIGNAL:
- case AMDIL::APPEND_CONSUME:
- case AMDIL::APPEND_ALLOC:
- // 64 bit IO instructions
- case AMDIL::LDSLOAD64:
- case AMDIL::LDSLOAD64_i8:
- case AMDIL::LDSLOAD64_u8:
- case AMDIL::LDSLOAD64_i16:
- case AMDIL::LDSLOAD64_u16:
- case AMDIL::LDSSTORE64:
- case AMDIL::LDSSTORE64_i8:
- case AMDIL::LDSSTORE64_i16:
- case AMDIL::GDSLOAD64:
- case AMDIL::GDSSTORE64:
- case AMDIL::APPEND64_CONSUME:
- case AMDIL::APPEND64_ALLOC:
+ unsigned regClass = MI->getDesc().OpInfo[0].RegClass;
+ if (((isPtrLoadInst(MI) || isPtrStoreInst(MI))
+ && ((isLDSInst(MI)
+ && (MI->getDesc().OpInfo[1].RegClass == AMDIL::GPRI16RegClassID
+ || MI->getDesc().OpInfo[1].RegClass == AMDIL::GPRI8RegClassID
+ || MI->getDesc().OpInfo[1].RegClass == AMDIL::GPRI32RegClassID
+ || MI->getDesc().OpInfo[1].RegClass == AMDIL::GPRF32RegClassID))
+ || isGDSInst(MI)
+ || isScratchInst(MI)
+ || isCBInst(MI)
+ || isUAVArenaInst(MI))
+ && !isExtLoadInst(MI)
+ && !isTruncStoreInst(MI))
+ || isSemaphoreInst(MI)
+ || isAppendInst(MI)) {
opSwiz.bits.dst = 0;
if (isXComponentReg(reg)) {
opSwiz.bits.swizzle = AMDIL_SRC_XXXX;
@@ -562,9 +438,20 @@
} else if (isWComponentReg(reg)) {
opSwiz.bits.swizzle = AMDIL_SRC_WWWW;
}
- break;
- case AMDIL::HILO_BITOR_v4i16:
- case AMDIL::HILO_BITOR_v2i64:
+ if (isPtrStoreInst(MI) && isScratchInst(MI)) {
+ if (isXYComponentReg(reg)) {
+ opSwiz.bits.dst = 1;
+ opSwiz.bits.swizzle = AMDIL_DST_XY__;
+ } else if (isZWComponentReg(reg)) {
+ opSwiz.bits.dst = 1;
+ opSwiz.bits.swizzle = AMDIL_DST___ZW;
+ }
+ }
+ return opSwiz;
+ }
+ switch (opcode) {
+ case AMDIL::HILO_BITORv4i16rr:
+ case AMDIL::HILO_BITORv2i64rr:
if (isXYComponentReg(reg)) {
opSwiz.bits.swizzle = AMDIL_DST_XY__;
} else {
@@ -586,7 +473,6 @@
};
return opSwiz;
}
-
OpSwizzle getSrcSwizzleID(MachineInstr *MI, unsigned opNum)
{
assert(opNum < MI->getNumOperands() &&
@@ -612,7 +498,8 @@
curSwiz.bits.swizzle = AMDIL_SRC_XYXY;
} else if (isZWComponentReg(reg)) {
curSwiz.bits.swizzle = AMDIL_SRC_ZWZW;
- } else if (reg == AMDIL::R1011 && isMove(MI->getOpcode())) {
+ } else if (reg == AMDIL::R1011
+ && MI->getOpcode() == TargetOpcode::COPY) {
reg = MI->getOperand(0).getReg();
if (isXComponentReg(reg) || isYComponentReg(reg)
|| isZComponentReg(reg) || isWComponentReg(reg)) {
@@ -625,7 +512,6 @@
}
return curSwiz;
}
-
OpSwizzle getDstSwizzleID(MachineInstr *MI)
{
OpSwizzle curSwiz;
@@ -655,19 +541,9 @@
return curSwiz;
}
-
-/// All vector instructions except for VCREATE_* need to be handled
-/// with custom swizzle packing code.
-bool isCustomVectorInst(MachineInstr *MI)
-{
- unsigned opcode = MI->getOpcode();
- return (opcode >= AMDIL::VCONCAT_v2f32 && opcode <= AMDIL::VCONCAT_v4i8)
- || (opcode >= AMDIL::VEXTRACT_v2f32 && opcode <= AMDIL::VINSERT_v4i8);
-}
-
void encodeVectorInst(MachineInstr *MI, bool mDebug)
{
- assert(isCustomVectorInst(MI) && "Only a vector instruction can be"
+ assert(isVectorOpInst(MI) && "Only a vector instruction can be"
" used to generate a new vector instruction!");
unsigned opcode = MI->getOpcode();
// For all of the opcodes, the destination swizzle is the same.
@@ -678,16 +554,18 @@
unsigned offset = 0;
unsigned reg = MI->getOperand(0).getReg();
switch (opcode) {
- case AMDIL::VCONCAT_v2f32:
- case AMDIL::VCONCAT_v2i16:
- case AMDIL::VCONCAT_v2i32:
- case AMDIL::VCONCAT_v2i8:
+ GENERATE_2ARG_CASE(AMDIL::VCONCATv2f32)
+ GENERATE_2ARG_CASE(AMDIL::VCONCATv2i32)
+ GENERATE_2ARG_CASE(AMDIL::VCONCATv2i16)
+ GENERATE_2ARG_CASE(AMDIL::VCONCATv2i8)
if (isZWComponentReg(reg)) {
offset = 2;
}
for (unsigned x = 1; x < 3; ++x) {
- reg = MI->getOperand(x).getReg();
unsigned offset2 = 0;
+ if (MI->getOperand(x).isReg()) {
+ reg = MI->getOperand(x).getReg();
+ }
if (isXComponentReg(reg)) {
offset2 = 0;
} else if (isYComponentReg(reg)) {
@@ -701,14 +579,16 @@
MI->getOperand(x).setTargetFlags(srcID.u8all);
}
break;
- case AMDIL::VCONCAT_v2f64:
- case AMDIL::VCONCAT_v2i64:
- case AMDIL::VCONCAT_v4f32:
- case AMDIL::VCONCAT_v4i16:
- case AMDIL::VCONCAT_v4i32:
- case AMDIL::VCONCAT_v4i8:
+ GENERATE_2ARG_CASE(AMDIL::VCONCATv2f64)
+ GENERATE_2ARG_CASE(AMDIL::VCONCATv2i64)
+ GENERATE_2ARG_CASE(AMDIL::VCONCATv4f32)
+ GENERATE_2ARG_CASE(AMDIL::VCONCATv4i32)
+ GENERATE_2ARG_CASE(AMDIL::VCONCATv4i16)
+ GENERATE_2ARG_CASE(AMDIL::VCONCATv4i8)
for (unsigned x = 1; x < 3; ++x) {
- reg = MI->getOperand(x).getReg();
+ if (MI->getOperand(x).isReg()) {
+ reg = MI->getOperand(x).getReg();
+ }
if (isZWComponentReg(reg)) {
srcID.bits.swizzle = AMDIL_SRC_ZW00 + (x - 1);
} else {
@@ -717,10 +597,10 @@
MI->getOperand(x).setTargetFlags(srcID.u8all);
}
break;
- case AMDIL::VEXTRACT_v2f32:
- case AMDIL::VEXTRACT_v2i16:
- case AMDIL::VEXTRACT_v2i32:
- case AMDIL::VEXTRACT_v2i8:
+ GENERATE_1ARG_CASE(AMDIL::VEXTRACTv2f32)
+ GENERATE_1ARG_CASE(AMDIL::VEXTRACTv2i32)
+ GENERATE_1ARG_CASE(AMDIL::VEXTRACTv2i16)
+ GENERATE_1ARG_CASE(AMDIL::VEXTRACTv2i8)
assert(MI->getOperand(2).getImm() <= 2
&& "Invalid immediate value encountered for this formula!");
if (isXComponentReg(reg)) {
@@ -734,7 +614,9 @@
}
assert(MI->getOperand(2).getImm() <= 4
&& "Invalid immediate value encountered for this formula!");
- reg = MI->getOperand(1).getReg();
+ if (MI->getOperand(1).isReg()) {
+ reg = MI->getOperand(1).getReg();
+ }
if (isZWComponentReg(reg)) {
srcID.bits.swizzle = AMDIL_SRC_Z000;
} else {
@@ -744,10 +626,10 @@
MI->getOperand(1).setTargetFlags(srcID.u8all);
MI->getOperand(2).setTargetFlags(0);
break;
- case AMDIL::VEXTRACT_v4f32:
- case AMDIL::VEXTRACT_v4i16:
- case AMDIL::VEXTRACT_v4i32:
- case AMDIL::VEXTRACT_v4i8:
+ GENERATE_1ARG_CASE(AMDIL::VEXTRACTv4f32)
+ GENERATE_1ARG_CASE(AMDIL::VEXTRACTv4i32)
+ GENERATE_1ARG_CASE(AMDIL::VEXTRACTv4i16)
+ GENERATE_1ARG_CASE(AMDIL::VEXTRACTv4i8)
if (isXComponentReg(reg)) {
offset = 0;
} else if (isYComponentReg(reg)) {
@@ -767,8 +649,8 @@
MI->getOperand(1).setTargetFlags(srcID.u8all);
MI->getOperand(2).setTargetFlags(0);
break;
- case AMDIL::VEXTRACT_v2i64:
- case AMDIL::VEXTRACT_v2f64:
+ GENERATE_1ARG_CASE(AMDIL::VEXTRACTv2f64)
+ GENERATE_1ARG_CASE(AMDIL::VEXTRACTv2i64)
assert(MI->getOperand(2).getImm() <= 2
&& "Invalid immediate value encountered for this formula!");
if (isZWComponentReg(reg)) {
@@ -779,107 +661,118 @@
MI->getOperand(1).setTargetFlags(srcID.u8all);
MI->getOperand(2).setTargetFlags(0);
break;
- case AMDIL::VINSERT_v2f32:
- case AMDIL::VINSERT_v2i32:
- case AMDIL::VINSERT_v2i16:
- case AMDIL::VINSERT_v2i8: {
- unsigned swizVal = (unsigned)MI->getOperand(4).getImm();
- OpSwizzle src2ID;
- src2ID.u8all = 0;
- if (reg >= AMDIL::Rzw1 && reg < AMDIL::SDP) {
- offset = 2;
- }
+ GENERATE_2ARG_CASE(AMDIL::VINSERTv2f32)
+ GENERATE_2ARG_CASE(AMDIL::VINSERTv2i32)
+ GENERATE_2ARG_CASE(AMDIL::VINSERTv2i16)
+ GENERATE_2ARG_CASE(AMDIL::VINSERTv2i8)
+ {
+ unsigned swizVal = (unsigned)MI->getOperand(4).getImm();
+ OpSwizzle src2ID;
+ src2ID.u8all = 0;
+ if (reg >= AMDIL::Rzw1 && reg < AMDIL::SDP) {
+ offset = 2;
+ }
- unsigned offset1 = 0;
- reg = MI->getOperand(1).getReg();
- if (isZWComponentReg(reg)) {
- offset1 = 8;
- }
+ unsigned offset1 = 0;
+ if (MI->getOperand(1).isReg()) {
+ reg = MI->getOperand(1).getReg();
+ if (isZWComponentReg(reg)) {
+ offset1 = 8;
+ }
+ }
- unsigned offset2 = 0;
- reg = MI->getOperand(2).getReg();
- if (isYComponentReg(reg)) {
- offset2 = 4;
- } else if (isZComponentReg(reg)) {
- offset2 = 8;
- } else if (isWComponentReg(reg)) {
- offset2 = 12;
- }
- if (((swizVal >> 8) & 0xFF) == 1) {
- srcID.bits.swizzle = AMDIL_SRC_X000 + offset1 + offset;
- src2ID.bits.swizzle = AMDIL_SRC_0X00 + offset2 + offset;
- } else {
- srcID.bits.swizzle = AMDIL_SRC_0Y00 + offset1 + offset;
- src2ID.bits.swizzle = AMDIL_SRC_X000 + offset2 + offset;
- }
- MI->getOperand(1).setTargetFlags(srcID.u8all);
- MI->getOperand(2).setTargetFlags(src2ID.u8all);
- MI->getOperand(3).setTargetFlags(0);
- MI->getOperand(4).setTargetFlags(0);
- }
- break;
- case AMDIL::VINSERT_v4f32:
- case AMDIL::VINSERT_v4i16:
- case AMDIL::VINSERT_v4i32:
- case AMDIL::VINSERT_v4i8: {
- unsigned swizVal = (unsigned)MI->getOperand(4).getImm();
- OpSwizzle src2ID;
- src2ID.u8all = 0;
- if (reg >= AMDIL::Rzw1 && reg < AMDIL::SDP) {
- offset = 2;
- }
- unsigned offset2 = 0;
- reg = MI->getOperand(2).getReg();
- if (isYComponentReg(reg)) {
- offset2 = 4;
- } else if (isZComponentReg(reg)) {
- offset2 = 8;
- } else if (isWComponentReg(reg)) {
- offset2 = 12;
- } else if (isZWComponentReg(reg)) {
- offset2 = 2;
- }
- if ((swizVal >> 8 & 0xFF) == 1) {
- srcID.bits.swizzle = (!offset) ? AMDIL_SRC_X0ZW : AMDIL_SRC_XYZ0;
- src2ID.bits.swizzle = AMDIL_SRC_0X00 + offset2 + offset;
- } else if ((swizVal >> 16 & 0xFF) == 1) {
- srcID.bits.swizzle = AMDIL_SRC_XY0W;
- src2ID.bits.swizzle = AMDIL_SRC_00X0 + offset2;
- } else if ((swizVal >> 24 & 0xFF) == 1) {
- srcID.bits.swizzle = AMDIL_SRC_XYZ0;
- src2ID.bits.swizzle = AMDIL_SRC_000X + offset2;
- } else {
- srcID.bits.swizzle = (!offset) ? AMDIL_SRC_0YZW : AMDIL_SRC_XY0W;
- src2ID.bits.swizzle = AMDIL_SRC_X000 + offset2 + offset;
- }
- MI->getOperand(1).setTargetFlags(srcID.u8all);
- MI->getOperand(2).setTargetFlags(src2ID.u8all);
- MI->getOperand(3).setTargetFlags(0);
- MI->getOperand(4).setTargetFlags(0);
- }
- break;
- case AMDIL::VINSERT_v2f64:
- case AMDIL::VINSERT_v2i64: {
- unsigned swizVal = (unsigned)MI->getOperand(4).getImm();
- OpSwizzle src2ID;
- src2ID.u8all = 0;
- reg = MI->getOperand(2).getReg();
- if (isZWComponentReg(reg)) {
- offset = 2;
- }
- if (((swizVal >> 8) & 0xFF) == 1) {
- srcID.bits.swizzle = AMDIL_SRC_XY00;
- src2ID.bits.swizzle = AMDIL_SRC_00XY + offset;
- } else {
- srcID.bits.swizzle = AMDIL_SRC_00ZW;
- src2ID.bits.swizzle = AMDIL_SRC_XY00 + offset;
+ unsigned offset2 = 0;
+ if (MI->getOperand(2).isReg()) {
+ reg = MI->getOperand(2).getReg();
+ if (isYComponentReg(reg)) {
+ offset2 = 4;
+ } else if (isZComponentReg(reg)) {
+ offset2 = 8;
+ } else if (isWComponentReg(reg)) {
+ offset2 = 12;
+ }
+ }
+ if (((swizVal >> 8) & 0xFF) == 1) {
+ srcID.bits.swizzle = AMDIL_SRC_X000 + offset1 + offset;
+ src2ID.bits.swizzle = AMDIL_SRC_0X00 + offset2 + offset;
+ } else {
+ srcID.bits.swizzle = AMDIL_SRC_0Y00 + offset1 + offset;
+ src2ID.bits.swizzle = AMDIL_SRC_X000 + offset2 + offset;
+ }
+ MI->getOperand(1).setTargetFlags(srcID.u8all);
+ MI->getOperand(2).setTargetFlags(src2ID.u8all);
+ MI->getOperand(3).setTargetFlags(0);
+ MI->getOperand(4).setTargetFlags(0);
+ }
+ break;
+ GENERATE_2ARG_CASE(AMDIL::VINSERTv4f32)
+ GENERATE_2ARG_CASE(AMDIL::VINSERTv4i32)
+ GENERATE_2ARG_CASE(AMDIL::VINSERTv4i16)
+ GENERATE_2ARG_CASE(AMDIL::VINSERTv4i8)
+ {
+ unsigned swizVal = (unsigned)MI->getOperand(4).getImm();
+ OpSwizzle src2ID;
+ src2ID.u8all = 0;
+ if (reg >= AMDIL::Rzw1 && reg < AMDIL::SDP) {
+ offset = 2;
+ }
+ unsigned offset2 = 0;
+ if (MI->getOperand(2).isReg()) {
+ reg = MI->getOperand(2).getReg();
+ if (isYComponentReg(reg)) {
+ offset2 = 4;
+ } else if (isZComponentReg(reg)) {
+ offset2 = 8;
+ } else if (isWComponentReg(reg)) {
+ offset2 = 12;
+ } else if (isZWComponentReg(reg)) {
+ offset2 = 2;
+ }
+ }
+ if ((swizVal >> 8 & 0xFF) == 1) {
+ srcID.bits.swizzle = (!offset) ? AMDIL_SRC_X0ZW : AMDIL_SRC_XYZ0;
+ src2ID.bits.swizzle = AMDIL_SRC_0X00 + offset2 + offset;
+ } else if ((swizVal >> 16 & 0xFF) == 1) {
+ srcID.bits.swizzle = AMDIL_SRC_XY0W;
+ src2ID.bits.swizzle = AMDIL_SRC_00X0 + offset2;
+ } else if ((swizVal >> 24 & 0xFF) == 1) {
+ srcID.bits.swizzle = AMDIL_SRC_XYZ0;
+ src2ID.bits.swizzle = AMDIL_SRC_000X + offset2;
+ } else {
+ srcID.bits.swizzle = (!offset) ? AMDIL_SRC_0YZW : AMDIL_SRC_XY0W;
+ src2ID.bits.swizzle = AMDIL_SRC_X000 + offset2 + offset;
+ }
+ MI->getOperand(1).setTargetFlags(srcID.u8all);
+ MI->getOperand(2).setTargetFlags(src2ID.u8all);
+ MI->getOperand(3).setTargetFlags(0);
+ MI->getOperand(4).setTargetFlags(0);
+ }
+ break;
+ GENERATE_2ARG_CASE(AMDIL::VINSERTv2f64)
+ GENERATE_2ARG_CASE(AMDIL::VINSERTv2i64)
+ {
+ unsigned swizVal = (unsigned)MI->getOperand(4).getImm();
+ OpSwizzle src2ID;
+ src2ID.u8all = 0;
+ if (MI->getOperand(2).isReg()) {
+ reg = MI->getOperand(2).getReg();
+ if (isZWComponentReg(reg)) {
+ offset = 2;
+ }
+ }
+ if (((swizVal >> 8) & 0xFF) == 1) {
+ srcID.bits.swizzle = AMDIL_SRC_XY00;
+ src2ID.bits.swizzle = AMDIL_SRC_00XY + offset;
+ } else {
+ srcID.bits.swizzle = AMDIL_SRC_00ZW;
+ src2ID.bits.swizzle = AMDIL_SRC_XY00 + offset;
+ }
+ MI->getOperand(1).setTargetFlags(srcID.u8all);
+ MI->getOperand(2).setTargetFlags(src2ID.u8all);
+ MI->getOperand(3).setTargetFlags(0);
+ MI->getOperand(4).setTargetFlags(0);
}
- MI->getOperand(1).setTargetFlags(srcID.u8all);
- MI->getOperand(2).setTargetFlags(src2ID.u8all);
- MI->getOperand(3).setTargetFlags(0);
- MI->getOperand(4).setTargetFlags(0);
- }
- break;
+ break;
};
if (mDebug) {
for (unsigned i = 0; i < MI->getNumOperands(); ++i) {
@@ -888,7 +781,6 @@
dbgs() << "\n";
}
}
-
// This function loops through all of the instructions, skipping function
// calls, and encodes the swizzles in the operand.
void encodeSwizzles(MachineFunction &MF, bool mDebug)
@@ -908,7 +800,7 @@
dbgs() << "Encoding instruction: ";
MI->print(dbgs());
}
- if (isCustomVectorInst(MI)) {
+ if (isVectorOpInst(MI)) {
encodeVectorInst(MI, mDebug);
continue;
}
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSwizzleEncoder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSwizzleEncoder.h?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSwizzleEncoder.h (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSwizzleEncoder.h Wed Sep 12 12:43:34 2012
@@ -25,8 +25,7 @@
#include "llvm/Target/TargetMachine.h"
#include <set>
#include <map>
-namespace llvm
-{
+namespace llvm {
struct AMDILRegisterInfo;
class AMDILSwizzleEncoder : public MachineFunctionPass
{
@@ -36,9 +35,9 @@
bool runOnMachineFunction(MachineFunction &MF);
static char ID;
private:
- bool mDebug; ///< Flag to specify whether to dump debug information.
+ bool mDebug; ///< Flag to specify whether to dump debug information.
CodeGenOpt::Level opt;
-}; // class AMDILSwizzleEncoder
+}; // class AMDILSwizzleEncoder
char AMDILSwizzleEncoder::ID = 0;
} // end llvm namespace
#endif // _AMDIL_SWIZZLE_ENCODER_H_
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILTNDevice.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILTNDevice.cpp?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILTNDevice.cpp (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILTNDevice.cpp Wed Sep 12 12:43:34 2012
@@ -25,15 +25,12 @@
}
setCaps();
}
-
AMDILTrinityDevice::~AMDILTrinityDevice()
{
}
-
void
AMDILTrinityDevice::setCaps()
{
// Trinity inherits everything from Cayman. If there are any
// differences (like disabling FP64, do it here).
}
-
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILTNDevice.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILTNDevice.h?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILTNDevice.h (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILTNDevice.h Wed Sep 12 12:43:34 2012
@@ -15,8 +15,7 @@
#define _AMDILTNDEVICE_H_
#include "AMDILNIDevice.h"
#include "AMDILSubtarget.h"
-namespace llvm
-{
+namespace llvm {
class AMDILSubtarget;
//===---------------------------------------------------------------------===//
// NI generation of devices and their respective sub classes
@@ -26,14 +25,12 @@
// Like Cayman, they have a 4 wide ALU. They do support FP64, but this
// maybe not be advertised at the OpenCL API layer depending on
// performance.
-class AMDILTrinityDevice: public AMDILCaymanDevice
-{
+class AMDILTrinityDevice : public AMDILCaymanDevice {
public:
AMDILTrinityDevice(AMDILSubtarget*);
virtual ~AMDILTrinityDevice();
private:
virtual void setCaps();
-}; // AMDILTrinityDevice
-
+}; // AMDILTrinityDevice
} // namespace llvm
#endif // _AMDILTNDEVICE_H_
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILTargetMachine.cpp?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILTargetMachine.cpp (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILTargetMachine.cpp Wed Sep 12 12:43:34 2012
@@ -41,9 +41,7 @@
return new AMDILMCAsmInfo(TheTriple);
}
}
-
-extern "C" void LLVMInitializeAMDILTarget()
-{
+extern "C" void LLVMInitializeAMDILTarget() {
// Register the target
RegisterTargetMachine<TheAMDILTargetMachine> X(TheAMDILTarget);
@@ -54,42 +52,46 @@
//TargetRegistry::RegisterCodeEmitter(TheAMDILTarget,
//createAMDILMCCodeEmitter);
}
-
TheAMDILTargetMachine::TheAMDILTargetMachine(const Target &T,
- StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options,
- Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL)
+ StringRef TT,
+ StringRef CPU,
+ StringRef FS,
+ const TargetOptions &Options,
+ Reloc::Model RM,
+ CodeModel::Model CM,
+ CodeGenOpt::Level OL)
: AMDILTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL)
{
}
-
/// AMDILTargetMachine ctor -
///
AMDILTargetMachine::AMDILTargetMachine(const Target &T,
- StringRef TT, StringRef CPU, StringRef FS,
+ StringRef TT,
+ StringRef CPU,
+ StringRef FS,
const TargetOptions &Options,
- Reloc::Model RM, CodeModel::Model CM,
+ Reloc::Model RM,
+ CodeModel::Model CM,
CodeGenOpt::Level OL)
:
- LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
- Subtarget(TT, CPU, FS),
- DataLayout(Subtarget.getDataLayout()),
- FrameLowering(TargetFrameLowering::StackGrowsUp,
- Subtarget.device()->getStackAlignment(), 0),
- InstrInfo(*this), //JITInfo(*this),
- TLInfo(*this),
- IntrinsicInfo(this),
- ELFWriterInfo(false, true)
+ LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
+ Subtarget(TT, CPU, FS),
+ DataLayout(Subtarget.getDataLayout()),
+ FrameLowering(TargetFrameLowering::StackGrowsUp,
+ Subtarget.device()->getStackAlignment(), 0),
+ InstrInfo(*this), //JITInfo(*this),
+ TLInfo(*this),
+ IntrinsicInfo(this),
+ ELFWriterInfo(false, true)
{
setAsmVerbosityDefault(true);
setMCUseLoc(false);
}
-
AMDILTargetLowering*
AMDILTargetMachine::getTargetLowering() const
{
return const_cast<AMDILTargetLowering*>(&TLInfo);
}
-
const AMDILInstrInfo*
AMDILTargetMachine::getInstrInfo() const
{
@@ -100,37 +102,30 @@
{
return &FrameLowering;
}
-
const AMDILSubtarget*
AMDILTargetMachine::getSubtargetImpl() const
{
return &Subtarget;
}
-
const AMDILRegisterInfo*
AMDILTargetMachine::getRegisterInfo() const
{
return &InstrInfo.getRegisterInfo();
}
-
const TargetData*
AMDILTargetMachine::getTargetData() const
{
return &DataLayout;
}
-
const AMDILELFWriterInfo*
AMDILTargetMachine::getELFWriterInfo() const
{
return Subtarget.isTargetELF() ? &ELFWriterInfo : 0;
}
-
TargetPassConfig*
-AMDILTargetMachine::createPassConfig(PassManagerBase &PM)
-{
+AMDILTargetMachine::createPassConfig(PassManagerBase &PM) {
return new AMDILPassConfig(this, PM);
}
-
const AMDILIntrinsicInfo*
AMDILTargetMachine::getIntrinsicInfo() const
{
@@ -141,11 +136,6 @@
{
// Vector Coarsening as the current implementation does not support
// big endian yet.
- /* ---- TODO: WHAT TO DO WITH THIS???
- if (getAMDILTargetMachine().getOptLevel() != CodeGenOpt::None &&
- getAMDILTargetMachine().getTargetData()->isLittleEndian())
- addPass(createVectorCoarseningPass());
- */
return true;
}
@@ -173,19 +163,15 @@
llvm::RegisterScheduler::setDefault(&llvm::createSourceListDAGScheduler);
}
- addPass(createAMDILMachinePeephole(getAMDILTargetMachine(),
- getAMDILTargetMachine().getOptLevel()));
+ addPass(createAMDILMachinePeephole());
addPass(createAMDILPointerManager(getAMDILTargetMachine(),
getAMDILTargetMachine().getOptLevel()));
return false;
}
-
bool
-AMDILPassConfig::addPostRegAlloc()
-{
+AMDILPassConfig::addPostRegAlloc() {
return false; // -print-machineinstr should print after this.
}
-
/// addPreEmitPass - This pass may be implemented by targets that want to run
/// passes immediately before machine code is emitted. This should return
/// true if -print-machineinstrs should print out the code after the passes.
@@ -202,7 +188,6 @@
getAMDILTargetMachine().getOptLevel()));
return true;
}
-
void
AMDILTargetMachine::dump(OSTREAM_TYPE &O)
{
@@ -211,17 +196,15 @@
}
O << ";AMDIL Target Machine State Dump: \n";
}
-
void
AMDILTargetMachine::setDebug(bool debugMode)
{
mDebugMode = debugMode;
}
-
bool
AMDILTargetMachine::getDebug() const
{
return mDebugMode;
}
-
-extern "C" void LLVMInitializeAMDILTargetMC() {}
+extern "C" void LLVMInitializeAMDILTargetMC() {
+}
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILTargetMachine.h?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILTargetMachine.h (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILTargetMachine.h Wed Sep 12 12:43:34 2012
@@ -14,7 +14,6 @@
#ifndef AMDILTARGETMACHINE_H_
#define AMDILTARGETMACHINE_H_
-
#include "AMDIL.h"
#include "AMDILELFWriterInfo.h"
#include "AMDILFrameLowering.h"
@@ -37,7 +36,7 @@
{
private:
AMDILSubtarget Subtarget;
- const TargetData DataLayout; // Calculates type size & alignment
+ const TargetData DataLayout; // Calculates type size & alignment
AMDILFrameLowering FrameLowering;
AMDILInstrInfo InstrInfo;
AMDILTargetLowering TLInfo;
@@ -70,45 +69,37 @@
void dump(OSTREAM_TYPE &O);
void setDebug(bool debugMode);
bool getDebug() const;
+}; // AMDILTargetMachine
-
-}; // AMDILTargetMachine
-
-class TheAMDILTargetMachine : public AMDILTargetMachine
-{
+class TheAMDILTargetMachine : public AMDILTargetMachine {
public:
TheAMDILTargetMachine(const Target &T,
StringRef TT, StringRef CPU, StringRef FS,
const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
-}; // TheAMDILTargetMachine
-
+}; // TheAMDILTargetMachine
} // end namespace llvm
-namespace llvm
-{
-class AMDILPassConfig : public TargetPassConfig
-{
+namespace llvm {
+class AMDILPassConfig : public TargetPassConfig {
public:
AMDILPassConfig(AMDILTargetMachine *TM, PassManagerBase &PM)
- : TargetPassConfig(TM, PM) {}
+ : TargetPassConfig(TM, PM) {
+ }
AMDILTargetMachine &getAMDILTargetMachine() const {
return getTM<AMDILTargetMachine>();
}
-
const AMDILSubtarget &getAMDILSubtarget() const {
return *getAMDILTargetMachine().getSubtargetImpl();
}
-
// Pass Pipeline Configuration
virtual bool addPreEmitPass();
virtual bool addPreISel();
virtual bool addInstSelector();
virtual bool addPreRegAlloc();
virtual bool addPostRegAlloc();
-
};
} // end namespace llvm
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILUtilityFunctions.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILUtilityFunctions.cpp?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILUtilityFunctions.cpp (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILUtilityFunctions.cpp Wed Sep 12 12:43:34 2012
@@ -29,13 +29,10 @@
#include <queue>
#include <list>
using namespace llvm;
-int64_t GET_SCALAR_SIZE(llvm::Type *A)
-{
+int64_t GET_SCALAR_SIZE(llvm::Type *A) {
return A->getScalarSizeInBits();
}
-
-const TargetRegisterClass * getRegClassFromID(unsigned int ID)
-{
+const TargetRegisterClass * getRegClassFromID(unsigned int ID) {
switch (ID) {
default:
assert(0 && "Passed in ID does not match any register classes.");
@@ -74,91 +71,7 @@
return &AMDIL::GPRV2I64RegClass;
};
}
-
-unsigned int getMoveInstFromID(unsigned int ID)
-{
- switch (ID) {
- default:
- assert(0 && "Passed in ID does not match any move instructions.");
- case AMDIL::GPRI8RegClassID:
- return AMDIL::MOVE_i8;
- case AMDIL::GPRI16RegClassID:
- return AMDIL::MOVE_i16;
- case AMDIL::GPRI32RegClassID:
- return AMDIL::MOVE_i32;
- case AMDIL::GPRF32RegClassID:
- return AMDIL::MOVE_f32;
- case AMDIL::GPRI64RegClassID:
- return AMDIL::MOVE_i64;
- case AMDIL::GPRF64RegClassID:
- return AMDIL::MOVE_f64;
- case AMDIL::GPRV4F32RegClassID:
- return AMDIL::MOVE_v4f32;
- case AMDIL::GPRV4I8RegClassID:
- return AMDIL::MOVE_v4i8;
- case AMDIL::GPRV4I16RegClassID:
- return AMDIL::MOVE_v4i16;
- case AMDIL::GPRV4I32RegClassID:
- return AMDIL::MOVE_v4i32;
- case AMDIL::GPRV2F32RegClassID:
- return AMDIL::MOVE_v2f32;
- case AMDIL::GPRV2I8RegClassID:
- return AMDIL::MOVE_v2i8;
- case AMDIL::GPRV2I16RegClassID:
- return AMDIL::MOVE_v2i16;
- case AMDIL::GPRV2I32RegClassID:
- return AMDIL::MOVE_v2i32;
- case AMDIL::GPRV2F64RegClassID:
- return AMDIL::MOVE_v2f64;
- case AMDIL::GPRV2I64RegClassID:
- return AMDIL::MOVE_v2i64;
- };
- return -1;
-}
-
-unsigned int getPHIMoveInstFromID(unsigned int ID)
-{
- switch (ID) {
- default:
- assert(0 && "Passed in ID does not match any move instructions.");
- case AMDIL::GPRI8RegClassID:
- return AMDIL::PHIMOVE_i8;
- case AMDIL::GPRI16RegClassID:
- return AMDIL::PHIMOVE_i16;
- case AMDIL::GPRI32RegClassID:
- return AMDIL::PHIMOVE_i32;
- case AMDIL::GPRF32RegClassID:
- return AMDIL::PHIMOVE_f32;
- case AMDIL::GPRI64RegClassID:
- return AMDIL::PHIMOVE_i64;
- case AMDIL::GPRF64RegClassID:
- return AMDIL::PHIMOVE_f64;
- case AMDIL::GPRV4F32RegClassID:
- return AMDIL::PHIMOVE_v4f32;
- case AMDIL::GPRV4I8RegClassID:
- return AMDIL::PHIMOVE_v4i8;
- case AMDIL::GPRV4I16RegClassID:
- return AMDIL::PHIMOVE_v4i16;
- case AMDIL::GPRV4I32RegClassID:
- return AMDIL::PHIMOVE_v4i32;
- case AMDIL::GPRV2F32RegClassID:
- return AMDIL::PHIMOVE_v2f32;
- case AMDIL::GPRV2I8RegClassID:
- return AMDIL::PHIMOVE_v2i8;
- case AMDIL::GPRV2I16RegClassID:
- return AMDIL::PHIMOVE_v2i16;
- case AMDIL::GPRV2I32RegClassID:
- return AMDIL::PHIMOVE_v2i32;
- case AMDIL::GPRV2F64RegClassID:
- return AMDIL::PHIMOVE_v2f64;
- case AMDIL::GPRV2I64RegClassID:
- return AMDIL::PHIMOVE_v2i64;
- };
- return -1;
-}
-
-const TargetRegisterClass* getRegClassFromType(unsigned int type)
-{
+const TargetRegisterClass* getRegClassFromType(unsigned int type) {
switch (type) {
default:
assert(0 && "Passed in type does not match any register classes.");
@@ -196,23 +109,57 @@
return &AMDIL::GPRV2I64RegClass;
}
}
-
-void printSDNode(const SDNode *N)
+unsigned getRegClassFromName(const StringRef &name)
{
+ if (name.find("v4i32") != StringRef::npos) {
+ return AMDIL::GPRV4I32RegClassID;
+ } else if (name.find("v2i32") != StringRef::npos) {
+ return AMDIL::GPRV2I32RegClassID;
+ } else if (name.find("i32") != StringRef::npos) {
+ return AMDIL::GPRI32RegClassID;
+ } else if (name.find("v4f32") != StringRef::npos) {
+ return AMDIL::GPRV4F32RegClassID;
+ } else if (name.find("v2f32") != StringRef::npos) {
+ return AMDIL::GPRV2I32RegClassID;
+ } else if (name.find("f32") != StringRef::npos) {
+ return AMDIL::GPRF32RegClassID;
+ } else if (name.find("v4i16") != StringRef::npos) {
+ return AMDIL::GPRV4I16RegClassID;
+ } else if (name.find("v2i16") != StringRef::npos) {
+ return AMDIL::GPRV2I16RegClassID;
+ } else if (name.find("i16") != StringRef::npos) {
+ return AMDIL::GPRI16RegClassID;
+ } else if (name.find("v4i8") != StringRef::npos) {
+ return AMDIL::GPRV4I8RegClassID;
+ } else if (name.find("v2i8") != StringRef::npos) {
+ return AMDIL::GPRV2I8RegClassID;
+ } else if (name.find("i8") != StringRef::npos) {
+ return AMDIL::GPRI8RegClassID;
+ } else if (name.find("v2i64") != StringRef::npos) {
+ return AMDIL::GPRV2I64RegClassID;
+ } else if (name.find("i64") != StringRef::npos) {
+ return AMDIL::GPRI64RegClassID;
+ } else if (name.find("v2f64") != StringRef::npos) {
+ return AMDIL::GPRV2F64RegClassID;
+ } else if (name.find("f64") != StringRef::npos) {
+ return AMDIL::GPRF64RegClassID;
+ }
+ assert("Found a name that I couldn't determine a class for!");
+ return AMDIL::GPRI32RegClassID;
+}
+void printSDNode(const SDNode *N) {
printf("Opcode: %d isTargetOpcode: %d isMachineOpcode: %d\n",
N->getOpcode(), N->isTargetOpcode(), N->isMachineOpcode());
printf("Empty: %d OneUse: %d Size: %d NodeID: %d\n",
N->use_empty(), N->hasOneUse(), (int)N->use_size(), N->getNodeId());
for (unsigned int i = 0; i < N->getNumOperands(); ++i) {
printf("OperandNum: %d ValueCount: %d ValueType: %d\n",
- i, N->getNumValues(), N->getValueType(0) .getSimpleVT().SimpleTy);
+ i, N->getNumValues(), N->getValueType(0).getSimpleVT().SimpleTy);
printSDValue(N->getOperand(i), 0);
}
}
-
-void printSDValue(const SDValue &Op, int level)
-{
- printf("\nOp: %p OpCode: %d NumOperands: %d ", (void*)&Op, Op.getOpcode(),
+void printSDValue(const SDValue &Op, int level) {
+ printf("\nOp: %p OpCode: %d NumOperands: %d ", &Op, Op.getOpcode(),
Op.getNumOperands());
printf("IsTarget: %d IsMachine: %d ", Op.isTargetOpcode(),
Op.isMachineOpcode());
@@ -232,34 +179,19 @@
}
}
}
+#undef ExpandCaseToAllScalarTypes
+#define ExpandCaseToAllScalarTypes(Instr) \
+case Instr ## i8r: \
+case Instr ## i16r: \
+case Instr ## i32r: \
+case Instr ## i64r: \
+case Instr ## f32r: \
+case Instr ## f64r:
-bool isPHIMove(unsigned int opcode)
-{
+bool isMoveOrEquivalent(unsigned int opcode) {
switch (opcode) {
default:
return false;
- ExpandCaseToAllTypes(AMDIL::PHIMOVE);
- return true;
- }
- return false;
-}
-
-bool isMove(unsigned int opcode)
-{
- switch (opcode) {
- default:
- return false;
- ExpandCaseToAllTypes(AMDIL::MOVE);
- return true;
- }
- return false;
-}
-
-bool isMoveOrEquivalent(unsigned int opcode)
-{
- switch (opcode) {
- default:
- return isMove(opcode) || isPHIMove(opcode);
ExpandCaseToAllScalarTypes(AMDIL::IL_ASCHAR);
ExpandCaseToAllScalarTypes(AMDIL::IL_ASSHORT);
ExpandCaseToAllScalarTypes(AMDIL::IL_ASINT);
@@ -276,29 +208,23 @@
ExpandCaseToAllScalarTypes(AMDIL::IL_ASV4SHORT);
ExpandCaseToAllScalarTypes(AMDIL::IL_ASV4INT);
ExpandCaseToAllScalarTypes(AMDIL::IL_ASV4FLOAT);
- case AMDIL::INTTOANY_i8:
- case AMDIL::INTTOANY_i16:
- case AMDIL::INTTOANY_i32:
- case AMDIL::INTTOANY_f32:
- case AMDIL::DLO:
- case AMDIL::LLO:
- case AMDIL::LLO_v2i64:
+ case AMDIL::DLOf64r:
+ case AMDIL::LLOi64r:
+ case AMDIL::LLOv2i64r:
return true;
};
return false;
}
+#undef ExpandCaseToAllScalarTypes
-bool check_type(const Value *ptr, unsigned int addrspace)
-{
+bool check_type(const Value *ptr, unsigned int addrspace) {
if (!ptr) {
return false;
}
Type *ptrType = ptr->getType();
return dyn_cast<PointerType>(ptrType)->getAddressSpace() == addrspace;
}
-
-size_t getNumElements(Type * const T)
-{
+size_t getNumElements(Type * const T) {
size_t size = 0;
if (!T) {
return size;
@@ -335,9 +261,7 @@
};
return size;
}
-
-size_t getNumElements(StructType * const ST)
-{
+size_t getNumElements(StructType * const ST) {
size_t size = 0;
if (!ST) {
return size;
@@ -352,34 +276,24 @@
}
return size;
}
-
-size_t getNumElements(IntegerType * const IT)
-{
+size_t getNumElements(IntegerType * const IT) {
return (!IT) ? 0 : 1;
}
-
-size_t getNumElements(FunctionType * const FT)
-{
+size_t getNumElements(FunctionType * const FT) {
assert(0 && "Should not be able to calculate the number of "
"elements of a function type");
return 0;
}
-
-size_t getNumElements(ArrayType * const AT)
-{
+size_t getNumElements(ArrayType * const AT) {
return (!AT) ? 0
: (size_t)(getNumElements(AT->getElementType()) *
AT->getNumElements());
}
-
-size_t getNumElements(VectorType * const VT)
-{
+size_t getNumElements(VectorType * const VT) {
return (!VT) ? 0
: VT->getNumElements() * getNumElements(VT->getElementType());
}
-
-size_t getNumElements(PointerType * const PT)
-{
+size_t getNumElements(PointerType * const PT) {
size_t size = 0;
if (!PT) {
return size;
@@ -389,8 +303,6 @@
}
return size;
}
-
-
const llvm::Value *getBasePointerValue(const llvm::Value *V)
{
if (!V) {
@@ -431,9 +343,7 @@
}
return ret;
}
-
-const llvm::Value *getBasePointerValue(const llvm::MachineInstr *MI)
-{
+const llvm::Value *getBasePointerValue(const llvm::MachineInstr *MI) {
const Value *moVal = NULL;
if (!MI->memoperands_empty()) {
const MachineMemOperand *memOp = (*MI->memoperands_begin());
@@ -442,79 +352,52 @@
}
return moVal;
}
-
-bool commaPrint(int i, OSTREAM_TYPE &O)
-{
+bool commaPrint(int i, OSTREAM_TYPE &O) {
O << ":" << i;
return false;
}
-
-bool isLoadInst(TargetMachine &TM, const llvm::MachineInstr *MI)
-{
- if (strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "LOADCONST")) {
- return false;
- }
- return strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "LOAD");
+bool isLoadInst(const llvm::MachineInstr *MI) {
+ return !(MI->getDesc().TSFlags & (1ULL << AMDID::LOADCONST))
+ && (MI->getDesc().TSFlags & (1ULL << AMDID::LOAD));
+}
+bool isPtrLoadInst(const llvm::MachineInstr *MI) {
+ return isLoadInst(MI)
+ && !(MI->getDesc().TSFlags & (1ULL << AMDID::IMAGE));
}
-
bool isSWSExtLoadInst(const llvm::MachineInstr *MI)
{
- switch (MI->getOpcode()) {
- default:
- break;
- ExpandCaseToByteShortTypes(AMDIL::LOCALLOAD);
- ExpandCaseToByteShortTypes(AMDIL::GLOBALLOAD);
- ExpandCaseToByteShortTypes(AMDIL::REGIONLOAD);
- ExpandCaseToByteShortTypes(AMDIL::PRIVATELOAD);
- ExpandCaseToByteShortTypes(AMDIL::CPOOLLOAD);
- ExpandCaseToByteShortTypes(AMDIL::CONSTANTLOAD);
- return true;
- };
- return false;
+ return isPtrLoadInst(MI) && (MI->getDesc().TSFlags & (1ULL << AMDID::SWSEXTLD));
}
-
-bool isExtLoadInst(TargetMachine &TM, const llvm::MachineInstr *MI)
-{
- return strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "EXTLOAD");
+bool isExtLoadInst(const llvm::MachineInstr *MI) {
+ return isPtrLoadInst(MI) && (MI->getDesc().TSFlags & AMDID::EXTLOAD);
}
-
-bool isSExtLoadInst(TargetMachine &TM, const llvm::MachineInstr *MI)
-{
- return strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "SEXTLOAD");
+bool isSExtLoadInst(const llvm::MachineInstr *MI) {
+ return isPtrLoadInst(MI) && (MI->getDesc().TSFlags & (1ULL << AMDID::SEXTLOAD))
+ && !(MI->getDesc().TSFlags & (1ULL << AMDID::ZEXTLOAD));
}
-
-bool isAExtLoadInst(TargetMachine &TM, const llvm::MachineInstr *MI)
-{
- return strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "AEXTLOAD");
+bool isAExtLoadInst(const llvm::MachineInstr *MI) {
+ return isPtrLoadInst(MI) && (MI->getDesc().TSFlags & AMDID::AEXTLOAD);
}
-
-bool isZExtLoadInst(TargetMachine &TM, const llvm::MachineInstr *MI)
-{
- return strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "ZEXTLOAD");
+bool isZExtLoadInst(const llvm::MachineInstr *MI) {
+ return isPtrLoadInst(MI) && (MI->getDesc().TSFlags & (1ULL << AMDID::ZEXTLOAD))
+ && !(MI->getDesc().TSFlags & (1ULL << AMDID::SEXTLOAD));
}
-
-bool isStoreInst(TargetMachine &TM, const llvm::MachineInstr *MI)
-{
- return strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "STORE");
+bool isPtrStoreInst(const llvm::MachineInstr *MI) {
+ return isStoreInst(MI) && !(MI->getDesc().TSFlags & (1ULL << AMDID::IMAGE));
}
-
-bool isArenaInst(TargetMachine &TM, const llvm::MachineInstr *MI)
-{
- return strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "ARENA");
+bool isStoreInst(const llvm::MachineInstr *MI) {
+ return MI->getDesc().TSFlags & (1ULL << AMDID::STORE);
}
-
-bool isTruncStoreInst(TargetMachine &TM, const llvm::MachineInstr *MI)
-{
- return strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "TRUNCSTORE");
+bool isArenaInst(const llvm::MachineInstr *MI) {
+ return MI->getDesc().TSFlags & (1ULL << AMDID::ARENAUAV);
}
-
-bool isAtomicInst(TargetMachine &TM, const llvm::MachineInstr *MI)
-{
- return strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "ATOM");
+bool isTruncStoreInst(const llvm::MachineInstr *MI) {
+ return MI->getDesc().TSFlags & (1ULL << AMDID::TRUNCATE);
}
-
-bool isVolatileInst(const llvm::MachineInstr *MI)
-{
+bool isAtomicInst(const llvm::MachineInstr *MI) {
+ return MI->getDesc().TSFlags & (1ULL << AMDID::ATOMIC);
+}
+bool isVolatileInst(const llvm::MachineInstr *MI) {
if (!MI->memoperands_empty()) {
for (MachineInstr::mmo_iterator mob = MI->memoperands_begin(),
moe = MI->memoperands_end(); mob != moe; ++mob) {
@@ -526,158 +409,268 @@
}
return false;
}
-bool isGlobalInst(TargetMachine &TM, const llvm::MachineInstr *MI)
+bool isGlobalInst(const llvm::MachineInstr *MI)
{
- return strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "GLOBAL");
+ return MI->getDesc().TSFlags & (1ULL << AMDID::GLOBAL);
}
-bool isPrivateInst(TargetMachine &TM, const llvm::MachineInstr *MI)
+bool isPrivateInst(const llvm::MachineInstr *MI)
{
- return strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "PRIVATE");
+ return MI->getDesc().TSFlags & (1ULL << AMDID::PRIVATE);
}
-bool isConstantInst(TargetMachine &TM, const llvm::MachineInstr *MI)
+bool isConstantInst(const llvm::MachineInstr *MI)
{
- return strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "CONSTANT")
- || strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "CPOOL");
+ return (MI->getDesc().TSFlags & (1ULL << AMDID::CONSTANT))
+ || isConstantPoolInst(MI);
}
-bool is64bitLSOp(TargetMachine &TM, const llvm::MachineInstr *MI)
+bool is64bitLSOp(const llvm::MachineInstr *MI)
{
- return (isLoadInst(TM, MI) || isStoreInst(TM, MI))
- && strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "64_")
- && !strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "3264_");
+ return (isPtrLoadInst(MI) || isPtrStoreInst(MI))
+ && is64BitInst(MI);
}
-bool isConstantPoolInst(TargetMachine &TM, const llvm::MachineInstr *MI)
+bool isConstantPoolInst(const llvm::MachineInstr *MI)
{
- return strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "CPOOL");
+ return (MI->getDesc().TSFlags & (1ULL << AMDID::CPOOL));
}
-bool isRegionInst(TargetMachine &TM, const llvm::MachineInstr *MI)
+bool isRegionInst(const llvm::MachineInstr *MI)
{
- return strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "REGION");
+ return (MI->getDesc().TSFlags & (1ULL << AMDID::REGION));
}
-bool isLocalInst(TargetMachine &TM, const llvm::MachineInstr *MI)
+bool isGWSInst(const llvm::MachineInstr *MI)
{
- return strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "LOCAL");
+ return (MI->getDesc().TSFlags & (1ULL << AMDID::GWS));
}
-bool isImageInst(TargetMachine &TM, const llvm::MachineInstr *MI)
+bool isLocalInst(const llvm::MachineInstr *MI)
{
- return strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "IMAGE");
+ return MI->getDesc().TSFlags & (1ULL << AMDID::LOCAL);
}
-bool is64BitImageInst(TargetMachine &TM, const llvm::MachineInstr *MI)
+bool isLDSInst(const llvm::MachineInstr *MI)
{
- return isImageInst(TM, MI) &&
- strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "64_");
+ return MI->getDesc().TSFlags & (1ULL << AMDID::LDS);
}
-bool isReadImageInst(TargetMachine &TM, const llvm::MachineInstr *MI)
+bool isGDSInst(const llvm::MachineInstr *MI)
{
- return strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "IMAGE")
- && strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "READ");
+ return MI->getDesc().TSFlags & (1ULL << AMDID::GDS);
}
-bool isWriteImageInst(TargetMachine &TM, const llvm::MachineInstr *MI)
+bool isUAVArenaInst(const llvm::MachineInstr *MI)
{
- return strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "IMAGE")
- && strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "WRITE");
+ return MI->getDesc().TSFlags & (1ULL << AMDID::ARENAUAV);
}
-bool isImageInfoInst(TargetMachine &TM, const llvm::MachineInstr *MI)
+bool isUAVRawInst(const llvm::MachineInstr *MI)
{
- return isImageInst(TM, MI) &&
- strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "INFO");
+ return MI->getDesc().TSFlags & (1ULL << AMDID::RAWUAV);
}
-bool isImageInfo0Inst(TargetMachine &TM, const llvm::MachineInstr *MI)
+bool isCBInst(const llvm::MachineInstr *MI)
{
- return isImageInst(TM, MI) &&
- strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "INFO0");
+ return MI->getDesc().TSFlags & (1ULL << AMDID::CBMEM);
}
-bool isImageInfo1Inst(TargetMachine &TM, const llvm::MachineInstr *MI)
+bool isScratchInst(const llvm::MachineInstr *MI)
{
- return isImageInst(TM, MI) &&
- strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "INFO1");
+ return MI->getDesc().TSFlags & (1ULL << AMDID::SCRATCH);
}
-bool isImageTXLDInst(TargetMachine &TM, const llvm::MachineInstr *MI)
+bool isImageInst(const llvm::MachineInstr *MI)
{
- return isImageInst(TM, MI) &&
- strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "TXLD");
+ return MI->getDesc().TSFlags & (1ULL << AMDID::IMAGE);
}
-bool isSemaphoreInst(TargetMachine &TM, const llvm::MachineInstr *MI)
+bool is64BitImageInst(const llvm::MachineInstr *MI)
{
- return strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "SEMAPHORE");
+ return isImageInst(MI) && is64BitInst(MI);
}
-bool isAppendInst(TargetMachine &TM, const llvm::MachineInstr *MI)
+bool isReadImageInst(const llvm::MachineInstr *MI)
{
- return strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "APPEND");
+ return isImageInst(MI) && isLoadInst(MI) && !isImageTXLDInst(MI);
}
-bool isRegionAtomic(TargetMachine &TM, const llvm::MachineInstr *MI)
+bool isWriteImageInst(const llvm::MachineInstr *MI)
{
- return strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "ATOM_R");
+ return isImageInst(MI) && isStoreInst(MI);
}
-bool is64BitRegionAtomic(TargetMachine &TM, const llvm::MachineInstr *MI)
+bool isImageInfoInst(const llvm::MachineInstr* MI) {
+ return isImageInst(MI)
+ && (MI->getDesc().TSFlags & AMDID::INFO);
+}
+bool isImageInfo0Inst(const llvm::MachineInstr* MI) {
+ return isImageInst(MI)
+ && (MI->getDesc().TSFlags & (1ULL << AMDID::INFO0));
+}
+bool isImageInfo1Inst(const llvm::MachineInstr* MI) {
+ return isImageInst(MI)
+ && (MI->getDesc().TSFlags & (1ULL << AMDID::INFO1));
+}
+bool isImageTXLDInst(const llvm::MachineInstr* MI) {
+ return isImageInst(MI)
+ && MI->getDesc().TSFlags & (1ULL << AMDID::TXLD);
+}
+bool isSemaphoreInst(const llvm::MachineInstr *MI)
{
- return strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "ATOM64_R");
+ return MI->getDesc().TSFlags & (1ULL << AMDID::SEMA);
}
-bool isLocalAtomic(TargetMachine &TM, const llvm::MachineInstr *MI)
+bool isAppendInst(const llvm::MachineInstr *MI)
{
- return strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "ATOM_L");
+ return MI->getDesc().TSFlags & (1ULL << AMDID::APPEND);
}
-bool is64BitLocalAtomic(TargetMachine &TM, const llvm::MachineInstr *MI)
+bool isRegionAtomic(const llvm::MachineInstr *MI)
{
- return strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "ATOM64_L");
+ return isAtomicInst(MI) && isRegionInst(MI);
}
-bool isGlobalAtomic(TargetMachine &TM, const llvm::MachineInstr *MI)
+bool is64BitRegionAtomic(const llvm::MachineInstr *MI)
{
- return strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "ATOM_G")
- || isArenaAtomic(TM, MI);
+ return isRegionAtomic(MI) && is64BitInst(MI);
}
-bool is64BitGlobalAtomic(TargetMachine &TM, const llvm::MachineInstr *MI)
+bool isLocalAtomic(const llvm::MachineInstr *MI)
{
- return strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "ATOM64_G");
+ return isAtomicInst(MI) && isLocalInst(MI);
}
-bool isArenaAtomic(TargetMachine &TM, const llvm::MachineInstr *MI)
+bool is64BitLocalAtomic(const llvm::MachineInstr *MI)
{
- return strstr(TM.getInstrInfo()->getName(MI->getOpcode()), "ATOM_A");
+ return isLocalAtomic(MI) && is64BitInst(MI);
}
-
-bool isXComponentReg(unsigned reg)
+bool isGlobalAtomic(const llvm::MachineInstr *MI)
+{
+ return isAtomicInst(MI) && (isGlobalInst(MI)
+ || isArenaInst(MI));
+}
+bool is64BitGlobalAtomic(const llvm::MachineInstr *MI)
+{
+ return isGlobalAtomic(MI) && is64BitInst(MI);
+}
+bool isArenaAtomic(const llvm::MachineInstr *MI)
+{
+ return isAtomicInst(MI) && isArenaInst(MI);
+}
+bool is64BitInst(const llvm::MachineInstr *MI)
+{
+ return MI->getDesc().TSFlags & (1ULL << AMDID::ADDR64);
+}
+bool isPackedInst(const llvm::MachineInstr *MI)
+{
+ return MI->getDesc().TSFlags & (1ULL << AMDID::PACKED);
+}
+bool isSub32BitIOInst(const llvm::MachineInstr *MI)
+{
+ return MI->getDesc().TSFlags & (1ULL << AMDID::SUB32BITS);
+}
+bool isPackV2I8Inst(const llvm::MachineInstr *MI)
{
+ return (MI->getDesc().TSFlags & AMDID::TYPEMASK) == AMDID::TYPEV2I8
+ && isPackedInst(MI) && isStoreInst(MI);
+}
+bool isPackV2I16Inst(const llvm::MachineInstr *MI)
+{
+ return (MI->getDesc().TSFlags & AMDID::TYPEMASK) == AMDID::TYPEV2I16
+ && isPackedInst(MI) && isStoreInst(MI);
+}
+bool isPackV4I8Inst(const llvm::MachineInstr *MI)
+{
+ return (MI->getDesc().TSFlags & AMDID::TYPEMASK) == AMDID::TYPEV4I8
+ && isPackedInst(MI) && isStoreInst(MI);
+}
+bool isPackV4I16Inst(const llvm::MachineInstr *MI)
+{
+ return (MI->getDesc().TSFlags & AMDID::TYPEMASK) == AMDID::TYPEV4I16
+ && isPackedInst(MI) && isStoreInst(MI);
+}
+bool isUnpackV2I8Inst(const llvm::MachineInstr *MI)
+{
+ return (MI->getDesc().TSFlags & AMDID::TYPEMASK) == AMDID::TYPEV2I8
+ && isPackedInst(MI) && isLoadInst(MI);
+}
+bool isUnpackV2I16Inst(const llvm::MachineInstr *MI)
+{
+ return (MI->getDesc().TSFlags & AMDID::TYPEMASK) == AMDID::TYPEV2I16
+ && isPackedInst(MI) && isLoadInst(MI);
+}
+bool isUnpackV4I8Inst(const llvm::MachineInstr *MI)
+{
+ return (MI->getDesc().TSFlags & AMDID::TYPEMASK) == AMDID::TYPEV4I8
+ && isPackedInst(MI) && isLoadInst(MI);
+}
+bool isUnpackV4I16Inst(const llvm::MachineInstr *MI)
+{
+ return (MI->getDesc().TSFlags & AMDID::TYPEMASK) == AMDID::TYPEV4I16
+ && isPackedInst(MI) && isLoadInst(MI);
+}
+bool isVectorOpInst(const llvm::MachineInstr *MI)
+{
+ return MI->getDesc().TSFlags & (1ULL << AMDID::VECTOR);
+}
+bool
+isSkippedLiteral(const llvm::MachineInstr *MI, uint32_t opNum)
+{
+ uint32_t opcode = MI->getOpcode();
+ if ((opcode >= AMDIL::VEXTRACTv2f32i
+ && opcode <= AMDIL::VEXTRACTv4i8r)
+ && (opNum == 2)) {
+ return true;
+ } else if ((opcode >= AMDIL::VINSERTv2f32ii)
+ && (opcode <= AMDIL::VINSERTv4i8rr)
+ && ((opNum == 3) || (opNum == 4))) {
+ return true;
+ }
+ return false;
+}
+bool
+isBypassedLiteral(const llvm::MachineInstr *MI, uint32_t opNum)
+{
+ uint32_t opcode = MI->getOpcode();
+ if (((int)opNum == (int)(MI->getNumOperands() - 1))
+ && (isAtomicInst(MI)
+ || isScratchInst(MI)
+ || isLDSInst(MI)
+ || isGDSInst(MI)
+ || isUAVArenaInst(MI)
+ || isUAVRawInst(MI)
+ || isCBInst(MI)
+ || opcode == AMDIL::CASE)) {
+ return true;
+ } else if (opNum == 1 &&
+ (isAppendInst(MI)
+ || isReadImageInst(MI)
+ || isImageTXLDInst(MI)
+ || isCBInst(MI))) {
+ return true;
+ } else if (opNum == 0 &&
+ (isSemaphoreInst(MI)
+ || isReadImageInst(MI)
+ || isWriteImageInst(MI))) {
+ return true;
+ } else if (opNum == 3 && isReadImageInst(MI)) return true;
+
+ return false;
+}
+bool isXComponentReg(unsigned reg) {
return (reg >= AMDIL::Rx1 && reg < AMDIL::Rxy1)
|| reg == AMDIL::MEMx;
}
-bool isYComponentReg(unsigned reg)
-{
+bool isYComponentReg(unsigned reg) {
return (reg >= AMDIL::Ry1 && reg < AMDIL::Rz1);
}
-bool isZComponentReg(unsigned reg)
-{
+bool isZComponentReg(unsigned reg) {
return (reg >= AMDIL::Rz1 && reg < AMDIL::Rzw1);
}
-bool isWComponentReg(unsigned reg)
-{
+bool isWComponentReg(unsigned reg) {
return (reg >= AMDIL::Rw1 && reg < AMDIL::Rx1);
}
-bool isXYComponentReg(unsigned reg)
-{
+bool isXYComponentReg(unsigned reg) {
return (reg >= AMDIL::Rxy1 && reg < AMDIL::Ry1)
|| reg == AMDIL::MEMxy;
}
-bool isZWComponentReg(unsigned reg)
-{
+bool isZWComponentReg(unsigned reg) {
return (reg >= AMDIL::Rzw1 && reg < AMDIL::SDP);
}
-
-const char* getSrcSwizzle(unsigned idx)
-{
+const char* getSrcSwizzle(unsigned idx) {
const char *srcSwizzles[AMDIL_SRC_LAST] = {
"",
".x000", ".0x00", ".00x0", ".000x", ".y000", ".0y00", ".00y0", ".000y",
".z000", ".0z00", ".00z0", ".000z", ".w000", ".0w00", ".00w0", ".000w",
".xy00", ".00xy", ".zw00", ".00zw", ".xyz0", ".0xyz",
".xzxz", ".ywyw", ".x0y0", ".0x0y", ".0yzw", ".x0zw", ".xy0w",
- ".x" , ".y" , ".z" , ".w" , ".xyxy", ".zwzw", ".yzw0",
+ ".x", ".y", ".z", ".w", ".xyxy", ".zwzw", ".yzw0",
".z0w0", ".0z0w",
};
assert(idx < sizeof(srcSwizzles)/sizeof(srcSwizzles[0])
&& "Idx passed in is invalid!");
return srcSwizzles[idx];
}
-const char* getDstSwizzle(unsigned idx)
-{
+const char* getDstSwizzle(unsigned idx) {
const char *dstSwizzles[AMDIL_DST_LAST] = {
"", ".x___", "._y__", ".__z_", ".___w", ".xy__", ".__zw",
".xyz_"
@@ -707,7 +700,6 @@
MI->setFlags(lower);
MI->setAsmPrinterFlag((llvm::MachineInstr::CommentFlag)upper);
}
-
// symTab is a dummy arg to ease the transition...
const char *
getTypeName(Type *ptr, const char *symTab,
@@ -715,30 +707,33 @@
{
Type *name = ptr;
switch (ptr->getTypeID()) {
- case Type::StructTyID: {
+ case Type::StructTyID:
+ {
const StructType *ST = cast<StructType>(ptr);
if (!ST->isOpaque())
return "struct";
// ptr is a pre-LLVM 3.0 "opaque" type.
StringRef name = ST->getName();
- if (name.startswith( "struct._event_t" )) return "event";
- if (name.startswith( "struct._image1d_t" )) return "image1d";
+ if (name.startswith( "struct._event_t" )) return "event";
+ if (name.startswith( "struct._image1d_t" )) return "image1d";
if (name.startswith( "struct._image1d_array_t" )) return "image1d_array";
- if (name.startswith( "struct._image2d_t" )) return "image2d";
+ if (name.startswith( "struct._image2d_t" )) return "image2d";
if (name.startswith( "struct._image2d_array_t" )) return "image2d_array";
- if (name.startswith( "struct._image3d_t" )) return "image3d";
- if (name.startswith( "struct._sema_t" )) return "semaphore";
- if (name.startswith( "struct._counter32_t" )) return "counter32";
- if (name.startswith( "struct._counter64_t" )) return "counter64";
+ if (name.startswith( "struct._image3d_t" )) return "image3d";
+ if (name.startswith( "struct._sema_t" )) return "semaphore";
+ if (name.startswith( "struct._counter32_t" )) return "counter32";
+ if (name.startswith( "struct._counter64_t" )) return "counter64";
return "opaque";
break;
}
case Type::FloatTyID:
return "float";
- case Type::DoubleTyID: {
+ case Type::DoubleTyID:
+ {
return "double";
}
- case Type::IntegerTyID: {
+ case Type::IntegerTyID:
+ {
LLVMContext& ctx = ptr->getContext();
if (name == Type::getInt8Ty(ctx)) {
return (signedType) ? "i8" : "u8";
@@ -753,25 +748,29 @@
}
default:
break;
- case Type::ArrayTyID: {
+ case Type::ArrayTyID:
+ {
const ArrayType *AT = cast<ArrayType>(ptr);
name = AT->getElementType();
return getTypeName(name, symTab, mfi, signedType);
break;
}
- case Type::VectorTyID: {
+ case Type::VectorTyID:
+ {
const VectorType *VT = cast<VectorType>(ptr);
name = VT->getElementType();
return getTypeName(name, symTab, mfi, signedType);
break;
}
- case Type::PointerTyID: {
+ case Type::PointerTyID:
+ {
const PointerType *PT = cast<PointerType>(ptr);
name = PT->getElementType();
return getTypeName(name, symTab, mfi, signedType);
break;
}
- case Type::FunctionTyID: {
+ case Type::FunctionTyID:
+ {
const FunctionType *FT = cast<FunctionType>(ptr);
name = FT->getReturnType();
return getTypeName(name, symTab, mfi, signedType);
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILUtilityFunctions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILUtilityFunctions.h?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILUtilityFunctions.h (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILUtilityFunctions.h Wed Sep 12 12:43:34 2012
@@ -22,8 +22,7 @@
// Utility functions from ID
//
-namespace llvm
-{
+namespace llvm {
class TargetRegisterClass;
class TargetMachine;
class SDValue;
@@ -40,7 +39,6 @@
class OpaqueType;
class MachineInstr;
class AMDILMachineFunctionInfo;
-
}
enum SrcSwizzles {
AMDIL_SRC_DFLT = 0,
@@ -103,20 +101,16 @@
const llvm::TargetRegisterClass *getRegClassFromID(unsigned int ID);
-unsigned int getMoveInstFromID(unsigned int ID);
-unsigned int getPHIMoveInstFromID(unsigned int ID);
-
// Utility functions from Type.
const llvm::TargetRegisterClass *getRegClassFromType(unsigned int type);
unsigned int getTargetIndependentMoveFromType(unsigned int type);
+unsigned getRegClassFromName(const StringRef &name);
// Debug functions for SDNode and SDValue.
void printSDValue(const llvm::SDValue &Op, int level);
void printSDNode(const llvm::SDNode *N);
// Functions to check if an opcode is a specific type.
-bool isMove(unsigned int opcode);
-bool isPHIMove(unsigned int opcode);
bool isMoveOrEquivalent(unsigned int opcode);
// Function to check address space
@@ -144,41 +138,77 @@
int64_t GET_SCALAR_SIZE(llvm::Type* A);
// Helper functions that check the opcode for status information
-bool isLoadInst(llvm::TargetMachine &TM, const llvm::MachineInstr *MI);
-bool isExtLoadInst(llvm::TargetMachine &TM, const llvm::MachineInstr *MI);
+bool isLoadInst(const llvm::MachineInstr *MI);
+bool isPtrLoadInst(const llvm::MachineInstr *MI);
+bool isExtLoadInst(const llvm::MachineInstr *MI);
bool isSWSExtLoadInst(const llvm::MachineInstr *MI);
-bool isSExtLoadInst(llvm::TargetMachine &TM, const llvm::MachineInstr *MI);
-bool isZExtLoadInst(llvm::TargetMachine &TM, const llvm::MachineInstr *MI);
-bool isAExtLoadInst(llvm::TargetMachine &TM, const llvm::MachineInstr *MI);
-bool isStoreInst(llvm::TargetMachine &TM, const llvm::MachineInstr *MI);
-bool isTruncStoreInst(llvm::TargetMachine &TM, const llvm::MachineInstr *MI);
-bool isAtomicInst(llvm::TargetMachine &TM, const llvm::MachineInstr *MI);
+bool isSExtLoadInst(const llvm::MachineInstr *MI);
+bool isZExtLoadInst(const llvm::MachineInstr *MI);
+bool isAExtLoadInst(const llvm::MachineInstr *MI);
+bool isStoreInst(const llvm::MachineInstr *MI);
+bool isPtrStoreInst(const llvm::MachineInstr *MI);
+bool isTruncStoreInst(const llvm::MachineInstr *MI);
+bool isAtomicInst(const llvm::MachineInstr *MI);
bool isVolatileInst(const llvm::MachineInstr *MI);
-bool isGlobalInst(llvm::TargetMachine &TM, const llvm::MachineInstr *MI);
-bool isPrivateInst(llvm::TargetMachine &TM, const llvm::MachineInstr *MI);
-bool isConstantInst(llvm::TargetMachine &TM, const llvm::MachineInstr *MI);
-bool isConstantPoolInst(llvm::TargetMachine &TM, const llvm::MachineInstr *MI);
-bool isRegionInst(llvm::TargetMachine &TM, const llvm::MachineInstr *MI);
-bool isLocalInst(llvm::TargetMachine &TM, const llvm::MachineInstr *MI);
-bool isImageInst(llvm::TargetMachine &TM, const llvm::MachineInstr *MI);
-bool is64BitImageInst(llvm::TargetMachine &TM, const llvm::MachineInstr *MI);
-bool isWriteImageInst(llvm::TargetMachine &TM, const llvm::MachineInstr *MI);
-bool isReadImageInst(llvm::TargetMachine &TM, const llvm::MachineInstr *MI);
-bool isImageInfoInst(llvm::TargetMachine &TM, const llvm::MachineInstr *MI);
-bool isImageInfo0Inst(llvm::TargetMachine &TM, const llvm::MachineInstr *MI);
-bool isImageInfo1Inst(llvm::TargetMachine &TM, const llvm::MachineInstr *MI);
-bool isImageTXLDInst(llvm::TargetMachine &TM, const llvm::MachineInstr *MI);
-bool isAppendInst(llvm::TargetMachine &TM, const llvm::MachineInstr *MI);
-bool isSemaphoreInst(llvm::TargetMachine &TM, const llvm::MachineInstr *MI);
-bool isRegionAtomic(llvm::TargetMachine &TM, const llvm::MachineInstr *MI);
-bool is64BitRegionAtomic(llvm::TargetMachine &TM, const llvm::MachineInstr *MI);
-bool isLocalAtomic(llvm::TargetMachine &TM, const llvm::MachineInstr *MI);
-bool is64BitLocalAtomic(llvm::TargetMachine &TM, const llvm::MachineInstr *MI);
-bool isGlobalAtomic(llvm::TargetMachine &TM, const llvm::MachineInstr *MI);
-bool is64BitGlobalAtomic(llvm::TargetMachine &TM, const llvm::MachineInstr *MI);
-bool isArenaAtomic(llvm::TargetMachine &TM, const llvm::MachineInstr *MI);
-bool isArenaInst(llvm::TargetMachine &TM, const llvm::MachineInstr *MI);
-bool is64bitLSOp(llvm::TargetMachine &TM, const llvm::MachineInstr *MI);
+bool isGlobalInst(const llvm::MachineInstr *MI);
+bool isPrivateInst(const llvm::MachineInstr *MI);
+bool isConstantInst(const llvm::MachineInstr *MI);
+bool isConstantPoolInst(const llvm::MachineInstr *MI);
+bool isRegionInst(const llvm::MachineInstr *MI);
+bool isGWSInst(const llvm::MachineInstr *MI);
+bool isLocalInst(const llvm::MachineInstr *MI);
+bool isImageInst(const llvm::MachineInstr *MI);
+bool is64BitImageInst(const llvm::MachineInstr *MI);
+bool isWriteImageInst(const llvm::MachineInstr *MI);
+bool isReadImageInst(const llvm::MachineInstr *MI);
+bool isImageInfoInst(const llvm::MachineInstr *MI);
+bool isImageInfo0Inst(const llvm::MachineInstr *MI);
+bool isImageInfo1Inst(const llvm::MachineInstr *MI);
+bool isImageTXLDInst(const llvm::MachineInstr *MI);
+bool isAppendInst(const llvm::MachineInstr *MI);
+bool isSemaphoreInst(const llvm::MachineInstr *MI);
+bool isRegionAtomic(const llvm::MachineInstr *MI);
+bool is64BitRegionAtomic(const llvm::MachineInstr *MI);
+bool isLocalAtomic(const llvm::MachineInstr *MI);
+bool is64BitLocalAtomic(const llvm::MachineInstr *MI);
+bool isGlobalAtomic(const llvm::MachineInstr *MI);
+bool is64BitGlobalAtomic(const llvm::MachineInstr *MI);
+bool isArenaAtomic(const llvm::MachineInstr *MI);
+bool isArenaInst(const llvm::MachineInstr *MI);
+bool is64bitLSOp(const llvm::MachineInstr *MI);
+bool isLDSInst(const llvm::MachineInstr *MI);
+bool isGDSInst(const llvm::MachineInstr *MI);
+bool isUAVArenaInst(const llvm::MachineInstr *MI);
+bool isUAVRawInst(const llvm::MachineInstr *MI);
+bool isCBInst(const llvm::MachineInstr *MI);
+bool isScratchInst(const llvm::MachineInstr *MI);
+bool is64BitInst(const llvm::MachineInstr *MI);
+bool isPackedInst(const llvm::MachineInstr *MI);
+bool isSub32BitIOInst(const llvm::MachineInstr *MI);
+bool isPackV2I8Inst(const llvm::MachineInstr *MI);
+bool isPackV2I16Inst(const llvm::MachineInstr *MI);
+bool isPackV4I8Inst(const llvm::MachineInstr *MI);
+bool isPackV4I16Inst(const llvm::MachineInstr *MI);
+bool isUnpackV2I8Inst(const llvm::MachineInstr *MI);
+bool isUnpackV2I16Inst(const llvm::MachineInstr *MI);
+bool isUnpackV4I8Inst(const llvm::MachineInstr *MI);
+bool isUnpackV4I16Inst(const llvm::MachineInstr *MI);
+bool isVectorOpInst(const llvm::MachineInstr *MI);
+inline bool isAddriInst(const llvm::MachineInstr *MI) {
+ return MI->getOpcode() == llvm::AMDIL::ADDrp
+ || MI->getOpcode() == llvm::AMDIL::ADDi64rp;
+}
+inline bool isAddInst(const llvm::MachineInstr *MI) {
+ unsigned opcode = MI->getOpcode();
+ return opcode >= llvm::AMDIL::ADDf32rr && opcode <= llvm::AMDIL::ADDv4i8rr;
+}
+inline bool isCustomAddInst(const llvm::MachineInstr *MI) {
+ unsigned opcode = MI->getOpcode();
+ return opcode >= llvm::AMDIL::CUSTOM_ADDi16rr
+ && opcode <= llvm::AMDIL::CUSTOM_ADDv4i8rr;
+}
+bool isSkippedLiteral(const llvm::MachineInstr *MI, uint32_t op);
+bool isBypassedLiteral(const llvm::MachineInstr *MI, uint32_t op);
// Helper functions that check a registe for status information.
bool isXComponentReg(unsigned);
bool isYComponentReg(unsigned);
@@ -190,135 +220,134 @@
// Macros that are used to help with switch statements for various data types
// However, these macro's do not return anything unlike the second set below.
#define ExpandCaseTo32bitIntTypes(Instr) \
-case Instr##_i8: \
-case Instr##_i16: \
-case Instr##_i32:
+case Instr ## i8: \
+case Instr ## i16: \
+case Instr ## i32:
#define ExpandCaseTo32bitIntTruncTypes(Instr) \
-case Instr##_i16i8: \
-case Instr##_i32i8: \
-case Instr##_i32i16:
+case Instr ## i16i8r: \
+case Instr ## i32i8r: \
+case Instr ## i32i16r:
#define ExpandCaseToIntTypes(Instr) \
- ExpandCaseTo32bitIntTypes(Instr) \
-case Instr##_i64:
+ ExpandCaseTo32bitIntTypes(Instr) \
+case Instr ## i64:
#define ExpandCaseToIntTruncTypes(Instr) \
- ExpandCaseTo32bitIntTruncTypes(Instr) \
-case Instr##_i64i8: \
-case Instr##_i64i16: \
-case Instr##_i64i32:
+ ExpandCaseTo32bitIntTruncTypes(Instr) \
+case Instr ## i64i8r: \
+case Instr ## i64i16r: \
+case Instr ## i64i32r:
#define ExpandCaseToFloatTypes(Instr) \
- case Instr##_f32: \
-case Instr##_f64:
+case Instr ## f32: \
+case Instr ## f64:
#define ExpandCaseToFloatTruncTypes(Instr) \
-case Instr##_f64f32:
+case Instr ## f64f32r:
#define ExpandCaseTo32bitScalarTypes(Instr) \
- ExpandCaseTo32bitIntTypes(Instr) \
-case Instr##_f32:
+ ExpandCaseTo32bitIntTypes(Instr) \
+case Instr ## f32:
#define ExpandCaseToAllScalarTypes(Instr) \
- ExpandCaseToFloatTypes(Instr) \
-ExpandCaseToIntTypes(Instr)
+ ExpandCaseToFloatTypes(Instr) \
+ ExpandCaseToIntTypes(Instr)
#define ExpandCaseToAllScalarTruncTypes(Instr) \
- ExpandCaseToFloatTruncTypes(Instr) \
-ExpandCaseToIntTruncTypes(Instr)
+ ExpandCaseToFloatTruncTypes(Instr) \
+ ExpandCaseToIntTruncTypes(Instr)
// Vector versions of above macros
#define ExpandCaseToVectorIntTypes(Instr) \
- case Instr##_v2i8: \
-case Instr##_v4i8: \
-case Instr##_v2i16: \
-case Instr##_v4i16: \
-case Instr##_v2i32: \
-case Instr##_v4i32: \
-case Instr##_v2i64:
+case Instr ## v2i8: \
+case Instr ## v4i8: \
+case Instr ## v2i16: \
+case Instr ## v4i16: \
+case Instr ## v2i32: \
+case Instr ## v4i32: \
+case Instr ## v2i64:
#define ExpandCaseToVectorIntTruncTypes(Instr) \
-case Instr##_v2i16i8: \
-case Instr##_v4i16i8: \
-case Instr##_v2i32i8: \
-case Instr##_v4i32i8: \
-case Instr##_v2i32i16: \
-case Instr##_v4i32i16: \
-case Instr##_v2i64i8: \
-case Instr##_v2i64i16: \
-case Instr##_v2i64i32:
+case Instr ## v2i16i8r: \
+case Instr ## v4i16i8r: \
+case Instr ## v2i32i8r: \
+case Instr ## v4i32i8r: \
+case Instr ## v2i32i16r: \
+case Instr ## v4i32i16r: \
+case Instr ## v2i64i8r: \
+case Instr ## v2i64i16r: \
+case Instr ## v2i64i32r:
#define ExpandCaseToVectorFloatTypes(Instr) \
- case Instr##_v2f32: \
-case Instr##_v4f32: \
-case Instr##_v2f64:
+case Instr ## v2f32: \
+case Instr ## v4f32: \
+case Instr ## v2f64:
#define ExpandCaseToVectorFloatTruncTypes(Instr) \
-case Instr##_v2f64f32:
+case Instr ## v2f64f32r:
#define ExpandCaseToVectorByteTypes(Instr) \
- case Instr##_v4i8: \
-case Instr##_v2i16: \
-case Instr##_v4i16:
+case Instr ## v4i8: \
+case Instr ## v2i16: \
+case Instr ## v4i16:
#define ExpandCaseToAllVectorTypes(Instr) \
- ExpandCaseToVectorFloatTypes(Instr) \
-ExpandCaseToVectorIntTypes(Instr)
+ ExpandCaseToVectorFloatTypes(Instr) \
+ ExpandCaseToVectorIntTypes(Instr)
#define ExpandCaseToAllVectorTruncTypes(Instr) \
- ExpandCaseToVectorFloatTruncTypes(Instr) \
-ExpandCaseToVectorIntTruncTypes(Instr)
+ ExpandCaseToVectorFloatTruncTypes(Instr) \
+ ExpandCaseToVectorIntTruncTypes(Instr)
#define ExpandCaseToAllTypes(Instr) \
- ExpandCaseToAllVectorTypes(Instr) \
-ExpandCaseToAllScalarTypes(Instr)
+ ExpandCaseToAllVectorTypes(Instr) \
+ ExpandCaseToAllScalarTypes(Instr)
#define ExpandCaseToAllTruncTypes(Instr) \
- ExpandCaseToAllVectorTruncTypes(Instr) \
-ExpandCaseToAllScalarTruncTypes(Instr)
+ ExpandCaseToAllVectorTruncTypes(Instr) \
+ ExpandCaseToAllScalarTruncTypes(Instr)
#define ExpandCaseToPackedTypes(Instr) \
- case Instr##_v2i8: \
- case Instr##_v4i8: \
- case Instr##_v2i16: \
- case Instr##_v4i16:
+case Instr ## v2i8: \
+case Instr ## v4i8: \
+case Instr ## v2i16: \
+case Instr ## v4i16:
#define ExpandCaseToByteShortScalarTypes(Instr) \
- case Instr##_i8: \
- case Instr##_i16:
+case Instr ## i8: \
+case Instr ## i16:
#define ExpandCaseToByteShortTypes(Instr) \
- ExpandCaseToByteShortScalarTypes(Instr) \
- ExpandCaseToPackedTypes(Instr)
+ ExpandCaseToByteShortScalarTypes(Instr) \
+ ExpandCaseToPackedTypes(Instr)
#define ExpandCaseToI8Types(Instr) \
- case Instr##_i8: \
- case Instr##_v2i8: \
- case Instr##_v4i8:
+case Instr ## v2i8: \
+case Instr ## v4i8:
#define ExpandCaseToI16Types(Instr) \
- case Instr##_i16: \
- case Instr##_v2i16: \
- case Instr##_v4i16:
+case Instr ## i16: \
+case Instr ## v2i16: \
+case Instr ## v4i16:
// Macros that expand into case statements with return values
#define ExpandCaseTo32bitIntReturn(Instr, Return) \
-case Instr##_i8: return Return##_i8; \
-case Instr##_i16: return Return##_i16; \
-case Instr##_i32: return Return##_i32;
+case Instr ## i8: return Return ## i8; \
+case Instr ## i16: return Return ## i16; \
+case Instr ## i32: return Return ## i32;
#define ExpandCaseToIntReturn(Instr, Return) \
- ExpandCaseTo32bitIntReturn(Instr, Return) \
-case Instr##_i64: return Return##_i64;
+ ExpandCaseTo32bitIntReturn(Instr, Return) \
+case Instr ## i64: return Return ## i64;
#define ExpandCaseToFloatReturn(Instr, Return) \
- case Instr##_f32: return Return##_f32; \
-case Instr##_f64: return Return##_f64;
+case Instr ## f32: return Return ## f32; \
+case Instr ## f64: return Return ## f64;
#define ExpandCaseToAllScalarReturn(Instr, Return) \
- ExpandCaseToFloatReturn(Instr, Return) \
-ExpandCaseToIntReturn(Instr, Return)
+ ExpandCaseToFloatReturn(Instr, Return) \
+ ExpandCaseToIntReturn(Instr, Return)
// These macros expand to common groupings of RegClass ID's
#define ExpandCaseTo1CompRegID \
@@ -328,7 +357,7 @@
case AMDIL::GPRF32RegClassID:
#define ExpandCaseTo2CompRegID \
- case AMDIL::GPRI64RegClassID: \
+case AMDIL::GPRI64RegClassID: \
case AMDIL::GPRF64RegClassID: \
case AMDIL::GPRV2I8RegClassID: \
case AMDIL::GPRV2I16RegClassID: \
@@ -337,34 +366,36 @@
// Macros that expand to case statements for specific bitlengths
#define ExpandCaseTo8BitType(Instr) \
- case Instr##_i8:
+case Instr ## i8:
#define ExpandCaseTo16BitType(Instr) \
- case Instr##_v2i8: \
-case Instr##_i16:
+case Instr ## v2i8: \
+case Instr ## i16:
#define ExpandCaseTo32BitType(Instr) \
- case Instr##_v4i8: \
-case Instr##_v2i16: \
-case Instr##_i32: \
-case Instr##_f32:
+case Instr ## v4i8: \
+case Instr ## v2i16: \
+case Instr ## i32: \
+case Instr ## f32:
#define ExpandCaseTo64BitType(Instr) \
- case Instr##_v4i16: \
-case Instr##_v2i32: \
-case Instr##_v2f32: \
-case Instr##_i64: \
-case Instr##_f64:
+case Instr ## v4i16: \
+case Instr ## v2i32: \
+case Instr ## v2f32: \
+case Instr ## i64: \
+case Instr ## f64:
#define ExpandCaseTo128BitType(Instr) \
- case Instr##_v4i32: \
-case Instr##_v4f32: \
-case Instr##_v2i64: \
-case Instr##_v2f64:
+case Instr ## v4i32: \
+case Instr ## v4f32: \
+case Instr ## v2i64: \
+case Instr ## v2f64:
bool commaPrint(int i, OSTREAM_TYPE &O);
/// Helper function to get the currently get/set flags.
-void getAsmPrinterFlags(llvm::MachineInstr *MI, llvm::AMDILAS::InstrResEnc &curRes);
-void setAsmPrinterFlags(llvm::MachineInstr *MI, llvm::AMDILAS::InstrResEnc &curRes);
+void getAsmPrinterFlags(llvm::MachineInstr *MI,
+ llvm::AMDILAS::InstrResEnc &curRes);
+void setAsmPrinterFlags(llvm::MachineInstr *MI,
+ llvm::AMDILAS::InstrResEnc &curRes);
#endif // AMDILUTILITYFUNCTIONS_H_
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILVersion.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILVersion.td?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILVersion.td (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILVersion.td Wed Sep 12 12:43:34 2012
@@ -13,13 +13,13 @@
let TargetPrefix = "AMDIL", isTarget = 1 in {
def int_AMDIL_barrier : GCCBuiltin<"barrier">,
- BinaryIntNoRetInt;
+ BinaryIntNoRetInt;
def int_AMDIL_barrier_global : GCCBuiltin<"barrierGlobal">,
- BinaryIntNoRetInt;
+ BinaryIntNoRetInt;
def int_AMDIL_barrier_local : GCCBuiltin<"barrierLocal">,
- BinaryIntNoRetInt;
+ BinaryIntNoRetInt;
def int_AMDIL_barrier_region : GCCBuiltin<"barrierRegion">,
- BinaryIntNoRetInt;
+ BinaryIntNoRetInt;
def int_AMDIL_get_region_id : GCCBuiltin<"__amdil_get_region_id_int">,
Intrinsic<[llvm_v4i32_ty], [], []>;
def int_AMDIL_get_region_local_id : GCCBuiltin<"__amdil_get_region_local_id_int">,
@@ -32,29 +32,29 @@
let isCall=1, isNotDuplicable=1 in {
let Predicates=[hasRegionAS] in {
-def BARRIER_EGNI : BinaryOpNoRet<IL_OP_BARRIER, (outs),
- (ins GPRI32:$flag, GPRI32:$id),
- "fence_threads_memory_lds_gds", // FIXME: gws causes hang on SI
- [(int_AMDIL_barrier GPRI32:$flag, GPRI32:$id)]>;
+def BARRIER_EGNI : ILFormat<IL_OP_BARRIER, (outs),
+ (ins GPRI32:$flag, GPRI32:$id),
+ "fence_threads_memory_lds_gds", // FIXME: gws causes hang on SI
+ [(int_AMDIL_barrier GPRI32:$flag, GPRI32:$id)]>;
}
let Predicates=[noRegionAS] in {
-def BARRIER_7XX : BinaryOpNoRet<IL_OP_BARRIER, (outs),
- (ins GPRI32:$flag, GPRI32:$id),
- "fence_threads_memory_lds",
- [(int_AMDIL_barrier GPRI32:$flag, GPRI32:$id)]>;
+def BARRIER_7XX : ILFormat<IL_OP_BARRIER, (outs),
+ (ins GPRI32:$flag, GPRI32:$id),
+ "fence_threads_memory_lds",
+ [(int_AMDIL_barrier GPRI32:$flag, GPRI32:$id)]>;
}
-def BARRIER_LOCAL : BinaryOpNoRet<IL_OP_BARRIER_LOCAL, (outs),
- (ins GPRI32:$flag, GPRI32:$id),
- "fence_threads_lds",
- [(int_AMDIL_barrier_local GPRI32:$flag, GPRI32:$id)]>;
-
-def BARRIER_GLOBAL : BinaryOpNoRet<IL_OP_BARRIER_GLOBAL, (outs),
- (ins GPRI32:$flag, GPRI32:$id),
- "fence_threads_memory",
- [(int_AMDIL_barrier_global GPRI32:$flag, GPRI32:$id)]>;
+def BARRIER_LOCAL : ILFormat<IL_OP_BARRIER_LOCAL, (outs),
+ (ins GPRI32:$flag, GPRI32:$id),
+ "fence_threads_lds",
+ [(int_AMDIL_barrier_local GPRI32:$flag, GPRI32:$id)]>;
+
+def BARRIER_GLOBAL : ILFormat<IL_OP_BARRIER_GLOBAL, (outs),
+ (ins GPRI32:$flag, GPRI32:$id),
+ "fence_threads_memory",
+ [(int_AMDIL_barrier_global GPRI32:$flag, GPRI32:$id)]>;
-def BARRIER_REGION : BinaryOpNoRet<IL_OP_BARRIER_REGION, (outs),
+def BARRIER_REGION : ILFormat<IL_OP_BARRIER_REGION, (outs),
(ins GPRI32:$flag, GPRI32:$id),
"fence_threads_gds",
[(int_AMDIL_barrier_region GPRI32:$flag, GPRI32:$id)]>;
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/Processors.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/Processors.td?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/Processors.td (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/Processors.td Wed Sep 12 12:43:34 2012
@@ -7,7 +7,7 @@
//
//===----------------------------------------------------------------------===//
//
-//
+// AMDIL processors supported.
//
//===----------------------------------------------------------------------===//
@@ -23,12 +23,5 @@
def : Proc<"barts", [FeatureByteAddress, FeatureImages]>;
def : Proc<"turks", [FeatureByteAddress, FeatureImages]>;
def : Proc<"caicos", [FeatureByteAddress, FeatureImages]>;
-def : Proc<"kauai", [FeatureByteAddress, FeatureImages, FeatureFP64]>;
def : Proc<"cayman", [FeatureByteAddress, FeatureImages, FeatureFP64]>;
-def : Proc<"tahiti", [FeatureByteAddress, FeatureImages, FeatureFP64]>;
-def : Proc<"pitcairn", [FeatureByteAddress, FeatureImages, FeatureFP64]>;
-def : Proc<"capeverde", [FeatureByteAddress, FeatureImages, FeatureFP64]>;
-def : Proc<"trinity", [FeatureByteAddress, FeatureImages, FeatureFP64]>;
-def : Proc<"dogs", [FeatureByteAddress, FeatureImages, FeatureFP64]>;
-def : Proc<"cats", [FeatureByteAddress, FeatureImages, FeatureFP64]>;
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/TargetInfo/AMDILTargetInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/TargetInfo/AMDILTargetInfo.cpp?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/TargetInfo/AMDILTargetInfo.cpp (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/TargetInfo/AMDILTargetInfo.cpp Wed Sep 12 12:43:34 2012
@@ -54,10 +54,8 @@
/// The target for the AMDIL backend
Target llvm::TheAMDILTarget;
-
/// Extern function to initialize the targets for the AMDIL backend
-extern "C" void LLVMInitializeAMDILTargetInfo()
-{
+extern "C" void LLVMInitializeAMDILTargetInfo() {
RegisterTarget<Triple::amdil, false>
IL(TheAMDILTarget, "amdil", "ATI graphics cards");
}
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/macrodata.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/macrodata.cpp?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/macrodata.cpp (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/macrodata.cpp Wed Sep 12 12:43:34 2012
@@ -22,11 +22,7 @@
#include "macrodata.h"
#include "macrodb.h"
-
-
-namespace amd
-{
-
+namespace amd {
static const char *csMacroCallPattern = "mcall(";
static CMacroData sMacroDataDBObject;
@@ -42,38 +38,46 @@
InitMacroDB();
ResolveReferences();
}
-
CMacroData :: ~CMacroData()
{
-
- if ( mRefNbr ) {
+ if ( mRefNbr )
+ {
delete [] mRefNbr;
mRefNbr = 0;
}
- if ( mRefIndex ) {
+ if ( mRefIndex )
+ {
delete [] mRefIndex;
mRefIndex = 0;
}
- if ( mMacroRef ) {
+ if ( mMacroRef )
+ {
delete [] mMacroRef;
mMacroRef = 0;
}
}
-
-int CMacroData ::SearchForPattern(char *_SearchBuf, const char *_Pattern, int _PatLen)
+int CMacroData ::SearchForPattern(char *_SearchBuf,
+ const char *_Pattern,
+ int _PatLen)
{
int r = -1;
int BufLen = (int)strlen(_SearchBuf);
- for(int i = 0; i < BufLen - _PatLen; i++) {
- if (!memcmp(&_SearchBuf[i],_Pattern,_PatLen)) {
+ for(int i = 0; i < BufLen - _PatLen; i++)
+ {
+ if (!memcmp(&_SearchBuf[i],_Pattern,_PatLen))
+ {
r = i;
break;
}
}
return(r);
}
-
-int CMacroData ::ExtractString(int *_Pos0, int *_Pos1,char * _Name, char *_pBuf, const char*_Delim0, const char*_Delim1)
+int CMacroData ::ExtractString(int *_Pos0,
+ int *_Pos1,
+ char * _Name,
+ char *_pBuf,
+ const char*_Delim0,
+ const char*_Delim1)
{
int r = 0;
//int len = (int)strlen(_pBuf);
@@ -81,7 +85,8 @@
int len1 = (int)strlen(_Delim1);
*_Pos0 = SearchForPattern(_pBuf, _Delim0,len0 );
*_Pos1 = SearchForPattern(&_pBuf[(*_Pos0)+len0], _Delim1, len1);
- if ( *_Pos0 != -1 && *_Pos1 != -1 ) {
+ if ( *_Pos0 != -1 && *_Pos1 != -1 )
+ {
int nameLen = *_Pos1;
*_Pos1 += (*_Pos0)+len0;
memcpy(_Name, &_pBuf[(*_Pos0)+len0], nameLen);
@@ -90,16 +95,16 @@
}
return(r);
}
-
int CMacroData :: InitMacroDB( void )
{
int r = 1;
// count macros
- for(mMacroDBCounter = 0; amd::sMacroDB[mMacroDBCounter].Name[0] != 0; mMacroDBCounter++);
+ for(mMacroDBCounter = 0;
+ amd::sMacroDB[mMacroDBCounter].Name[0] != 0;
+ mMacroDBCounter++) ;
mInit = 1;
return (r);
}
-
int CMacroData :: NumberOfReferences( int Ord )
{
int r = 0;
@@ -107,19 +112,22 @@
int patLen = (int)strlen(csMacroCallPattern);
int pos = 0;
pMacro = (char*)sMacroDB[Ord].Body;
- while( 1 ) {
+ while( 1 )
+ {
pos = SearchForPattern(&pMacro[pos], csMacroCallPattern, patLen);
- if ( pos != -1) {
+ if ( pos != -1)
+ {
r++;
pos += patLen;
- } else {
+ }
+ else
+ {
break;
}
}
return(r);
}
-
int CMacroData :: InsertReferences( int Ord, int StartPos )
{
int r = 0;
@@ -128,19 +136,25 @@
int pos = 0;
pMacro = (char*)sMacroDB[Ord].Body;
r = 0;
- while( 1 ) {
+ while( 1 )
+ {
pos = SearchForPattern(&pMacro[pos], csMacroCallPattern, patLen);
- if ( pos != -1) {
+ if ( pos != -1)
+ {
char Nmbr[64];
int pos0,pos1;
- if (ExtractString(&pos0,&pos1,Nmbr, &pMacro[pos], csMacroCallPattern, ")") != -1) {
+ if (ExtractString(&pos0,&pos1,Nmbr, &pMacro[pos], csMacroCallPattern,
+ ")") != -1)
+ {
int newOrd;
sscanf(Nmbr,"%d",&newOrd);
mMacroRef[StartPos + r] = (char*)sMacroDB[newOrd].Body;
r++;
}
pos += patLen;
- } else {
+ }
+ else
+ {
break;
}
}
@@ -149,57 +163,60 @@
mMacroRef[StartPos + mRefNbr[Ord] - 1] = (char*)sMacroDB[Ord].Body;
return(r);
}
-
int CMacroData :: ResolveReferences( void )
{
int r = 1;
int totalRef;
int startPos;
- if ( mRefNbr ) {
+ if ( mRefNbr )
+ {
delete [] mRefNbr;
}
mRefNbr = new int [mMacroDBCounter];
- for(int i = 0; i < mMacroDBCounter; i++) {
+ for(int i = 0; i < mMacroDBCounter; i++)
+ {
// plus itself
mRefNbr[i] = NumberOfReferences(i) + 1;
}
// count total ref and set starting ref position per macro
totalRef = 0;
- for(int i = 0; i < mMacroDBCounter; i++) {
+ for(int i = 0; i < mMacroDBCounter; i++)
+ {
totalRef += mRefNbr[i];
}
-
- if ( mRefIndex ) {
+ if ( mRefIndex )
+ {
delete [] mRefIndex;
}
mRefIndex = new int [mMacroDBCounter];
-
- if ( mMacroRef ) {
+ if ( mMacroRef )
+ {
delete [] mMacroRef;
}
mMacroRef = new char*[totalRef];
startPos = 0;
- for( int i = 0; i < mMacroDBCounter; i++) {
+ for( int i = 0; i < mMacroDBCounter; i++)
+ {
InsertReferences( i, startPos );
mRefIndex[i] = startPos;
startPos += mRefNbr[i];
-
}
return (r);
}
-
-
int CMacroData :: MacroDBFindMacro( const char * _pcMacroNm )
{
int r = -1;
- if ( mInit ) {
- for ( int i = 0; i < mMacroDBCounter; i++) {
- if ( !strcmp(_pcMacroNm,sMacroDB[i].Name)) {
+ if ( mInit )
+ {
+ for ( int i = 0; i < mMacroDBCounter; i++)
+ {
+ if ( !strcmp(_pcMacroNm,sMacroDB[i].Name))
+ {
r = i;
break;
}
@@ -207,64 +224,61 @@
}
return(r);
}
-
const char *CMacroData :: MacroDBGetMacro( int _iMacroId )
{
const char *r = 0;
- if ( mInit && _iMacroId >= 0 && _iMacroId < mMacroDBCounter) {
+ if ( mInit && _iMacroId >= 0 && _iMacroId < mMacroDBCounter)
+ {
r = sMacroDB[_iMacroId].Body;
}
return r;
}
-
-const char ** CMacroData :: MacroDBGetMacroList( int *_MacroListCounter, int _iMacroId )
+const char ** CMacroData :: MacroDBGetMacroList( int *_MacroListCounter,
+ int _iMacroId )
{
const char **r = 0;
- if ( mInit && _MacroListCounter && _iMacroId >= 0 && _iMacroId < mMacroDBCounter) {
+ if ( mInit && _MacroListCounter && _iMacroId >= 0 && _iMacroId <
+ mMacroDBCounter)
+ {
int refPos = mRefIndex[_iMacroId];
r = (const char **)&mMacroRef[refPos];
*_MacroListCounter = mRefNbr[_iMacroId];
}
return(r);
}
-
int CMacroData :: MacroDBFindNumInputs( int _iMacroId )
{
int r = 0;
- if ( mInit && _iMacroId >=0 && _iMacroId < mMacroDBCounter) {
+ if ( mInit && _iMacroId >=0 && _iMacroId < mMacroDBCounter)
+ {
r = sMacroDB[_iMacroId].Inputs;
}
return r;
}
-
int CMacroData :: MacroDBFindNumOutputs( int _iMacroId )
{
int r = 0;
- if ( mInit && _iMacroId >=0 && _iMacroId < mMacroDBCounter) {
+ if ( mInit && _iMacroId >=0 && _iMacroId < mMacroDBCounter)
+ {
r = sMacroDB[_iMacroId].Outputs;
}
return r;
}
-
-
// public:
int MacroDBFindMacro( const char * _pcMacroNm )
{
return(sMacroDataDBObject.MacroDBFindMacro(_pcMacroNm));
}
-
const char ** MacroDBGetMacro( int *_MacroListCounter, int _iMacroId )
{
return(sMacroDataDBObject.MacroDBGetMacroList(_MacroListCounter, _iMacroId));
}
-
int MacroDBNumInputs(int _iMacroId)
{
return(sMacroDataDBObject.MacroDBFindNumInputs(_iMacroId));
}
-
int MacroDBNumOutputs(int _iMacroId)
{
return (sMacroDataDBObject.MacroDBFindNumOutputs(_iMacroId));
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/macrodata.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/macrodata.h?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/macrodata.h (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/macrodata.h Wed Sep 12 12:43:34 2012
@@ -21,8 +21,7 @@
#ifndef MACRODATA_HPP_
#define MACRODATA_HPP_
-namespace amd
-{
+namespace amd {
/*! \brief Returns macro ordinal.
*
* \details
@@ -37,10 +36,10 @@
const char *MacroPtr;
int MacrosCnt;
MacroPtrs = amd::MacroDBGetMacro(&MacrosCnt,ordinal);
- for( int i = 0; i < MacrosCnt; i++)
+ for( int i = 0; i < MacrosCnt; i++)
{
- MacroPtr = MacroPtrs[i];
- }
+ MacroPtr = MacroPtrs[i];
+ }
*/
const char ** MacroDBGetMacro( int *_MacroListCounter, int _iMacroId );
@@ -53,5 +52,4 @@
int MacroDBNumOutputs(int macronum);
} // namespace amd
-
#endif /*MACRODATA_HPP_*/
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/macrodb.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/macrodb.h?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/macrodb.h (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/macrodb.h Wed Sep 12 12:43:34 2012
@@ -21,11 +21,8 @@
#ifndef MACRODB_HPP_
#define MACRODB_HPP_
-namespace amd
-{
-
-namespace macrodata
-{
+namespace amd {
+namespace macrodata {
struct SMacroEntry {
const char* Name;
const char* Body;
@@ -34,8 +31,7 @@
};
}
-class CMacroData
-{
+class CMacroData {
public:
CMacroData();
~CMacroData();
@@ -57,16 +53,16 @@
int NumberOfReferences( int Ord );
int InsertReferences( int Ord, int StartPos );
int SearchForPattern(char *_SearchBuf, const char *_Pattern, int _PatLen);
- int ExtractString(int *_Pos0, int *_Pos1,char * _Name, char *_pBuf, const char*_Delim0, const char*_Delim1);
-
-
-
+ int ExtractString(int *_Pos0,
+ int *_Pos1,
+ char * _Name,
+ char *_pBuf,
+ const char*_Delim0,
+ const char*_Delim1);
};
-
// real macros
#include "macrodb_gen.h"
-
}
#endif /*MACRODB_HPP_*/
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/macrodb_gen.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/macrodb_gen.h?rev=163727&r1=163726&r2=163727&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/macrodb_gen.h (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/macrodb_gen.h Wed Sep 12 12:43:34 2012
@@ -16,54 +16,44 @@
/*
The time is Mon Jul 18 18:22:11 2011
*/
-const macrodata::SMacroEntry sMacroDB[] = {
- {
- "barrier",
+const macrodata::SMacroEntry sMacroDB[] =
+{
+ { "barrier",
"mdef(0)_out(1)_in(1)\n"
"mov r0, in0\n"
"fence_threads_memory_lds\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "barrierGlobal",
+ ,1,1},
+ { "barrierGlobal",
"mdef(1)_out(1)_in(1)\n"
"mov r0, in0\n"
"fence_threads_memory\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "barrierLocal",
+ ,1,1},
+ { "barrierLocal",
"mdef(2)_out(1)_in(1)\n"
"mov r0, in0\n"
"fence_threads_lds\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "read_mem_fence",
+ ,1,1},
+ { "read_mem_fence",
"mdef(3)_out(1)_in(1)\n"
"mov r0, in0\n"
"fence_lds_mem_read_only\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "write_mem_fence",
+ ,1,1},
+ { "write_mem_fence",
"mdef(4)_out(1)_in(1)\n"
"mov r0, in0\n"
"fence_lds_mem_write_only\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__acosh_f32",
+ ,1,1},
+ { "__acosh_f32",
"mdef(5)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r1.x___, r0.x\n"
@@ -189,10 +179,8 @@
"cmov_logical r0.x___, r1.y, l45, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__acospi_f32",
+ ,1,1},
+ { "__acospi_f32",
"mdef(6)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r1.x___, r0.x\n"
@@ -296,10 +284,8 @@
"mul_ieee r0.x___, r0.x, l27\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__acos_f32",
+ ,1,1},
+ { "__acos_f32",
"mdef(7)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r1.x___, r0.x\n"
@@ -376,10 +362,8 @@
"cmov_logical r0.x___, r1.y, l26, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_bitalign_1",
+ ,1,1},
+ { "__amdil_bitalign_1",
"mdef(8)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -387,10 +371,8 @@
"bitalign r0.x___, r0.x, r1.x, r2.x\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_bitalign_2",
+ ,3,1},
+ { "__amdil_bitalign_2",
"mdef(9)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -398,10 +380,8 @@
"bitalign r0.xy__, r0.xy, r1.xy, r2.xy\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_bitalign_3",
+ ,3,1},
+ { "__amdil_bitalign_3",
"mdef(10)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -409,10 +389,8 @@
"bitalign r0.xyz_, r0.xyz, r1.xyz, r2.xyz\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_bitalign_4",
+ ,3,1},
+ { "__amdil_bitalign_4",
"mdef(11)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -420,10 +398,8 @@
"bitalign r0, r0, r1, r2\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_bytealign_1",
+ ,3,1},
+ { "__amdil_bytealign_1",
"mdef(12)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -431,10 +407,8 @@
"bytealign r0.x___, r0.x, r1.x, r2.x\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_bytealign_2",
+ ,3,1},
+ { "__amdil_bytealign_2",
"mdef(13)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -442,10 +416,8 @@
"bytealign r0.xy__, r0.xy, r1.xy, r2.xy\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_bytealign_3",
+ ,3,1},
+ { "__amdil_bytealign_3",
"mdef(14)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -453,10 +425,8 @@
"bytealign r0.xyz_, r0.xyz, r1.xyz, r2.xyz\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_bytealign_4",
+ ,3,1},
+ { "__amdil_bytealign_4",
"mdef(15)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -464,10 +434,8 @@
"bytealign r0, r0, r1, r2\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_cmovl_1",
+ ,3,1},
+ { "__amdil_cmovl_1",
"mdef(16)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -475,10 +443,8 @@
"cmov_logical r0.x, r0.x, r1.x, r2.x\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_cmovl_2",
+ ,3,1},
+ { "__amdil_cmovl_2",
"mdef(17)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -486,10 +452,8 @@
"cmov_logical r0.xy, r0.xy, r1.xy, r2.xy\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_cmovl_3",
+ ,3,1},
+ { "__amdil_cmovl_3",
"mdef(18)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -497,10 +461,8 @@
"cmov_logical r0.xyz, r0.xyz, r1.xyz, r2.xyz\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_cmovl_4",
+ ,3,1},
+ { "__amdil_cmovl_4",
"mdef(19)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -508,29 +470,23 @@
"cmov_logical r0, r0, r1, r2\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_dfrexp",
+ ,3,1},
+ { "__amdil_dfrexp",
"mdef(20)_out(1)_in(1)\n"
"mov r0, in0\n"
"dfrexp r0, r0.xy\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_dldexp",
+ ,1,1},
+ { "__amdil_dldexp",
"mdef(21)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"dldexp r0.xy__, r0.xy, r1.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_dmad",
+ ,2,1},
+ { "__amdil_dmad",
"mdef(22)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -538,186 +494,146 @@
"dmad r0.xy__, r0.xy, r1.xy, r2.xy\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_dmax",
+ ,3,1},
+ { "__amdil_dmax",
"mdef(23)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"dmax r0.xy, r0.xy, r1.xy\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_dmin",
+ ,2,1},
+ { "__amdil_dmin",
"mdef(24)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"dmin r0.xy, r0.xy, r1.xy\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_dp2_ieee",
+ ,2,1},
+ { "__amdil_dp2_ieee",
"mdef(25)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"dp2_ieee r0.x___, r0, r1\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_dp3_ieee",
+ ,2,1},
+ { "__amdil_dp3_ieee",
"mdef(26)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"dp3_ieee r0.x___, r0, r1\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_dp4_ieee",
+ ,2,1},
+ { "__amdil_dp4_ieee",
"mdef(27)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"dp4_ieee r0.x___, r0, r1\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_drcp",
+ ,2,1},
+ { "__amdil_drcp",
"mdef(28)_out(1)_in(1)\n"
"mov r0, in0\n"
"drcp_zeroop(infinity) r0.xy__, r0.xy\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_drsq",
+ ,1,1},
+ { "__amdil_drsq",
"mdef(29)_out(1)_in(1)\n"
"mov r0, in0\n"
"drsq_zeroop(infinity) r0.xy__, r0.xy\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_fabs_1",
+ ,1,1},
+ { "__amdil_fabs_1",
"mdef(30)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r0.x, r0.x_abs\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_fabs_2",
+ ,1,1},
+ { "__amdil_fabs_2",
"mdef(31)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r0.xy, r0.xy_abs\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_fabs_3",
+ ,1,1},
+ { "__amdil_fabs_3",
"mdef(32)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r0.xyz, r0.xyz_abs\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_fabs_4",
+ ,1,1},
+ { "__amdil_fabs_4",
"mdef(33)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r0, r0_abs\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_ffb_hi_1",
+ ,1,1},
+ { "__amdil_ffb_hi_1",
"mdef(34)_out(1)_in(1)\n"
"mov r0, in0\n"
"ffb_hi r0.x, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_ffb_hi_2",
+ ,1,1},
+ { "__amdil_ffb_hi_2",
"mdef(35)_out(1)_in(1)\n"
"mov r0, in0\n"
"ffb_hi r0.xy, r0.xy\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_ffb_hi_3",
+ ,1,1},
+ { "__amdil_ffb_hi_3",
"mdef(36)_out(1)_in(1)\n"
"mov r0, in0\n"
"ffb_hi r0.xyz, r0.xyz\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_ffb_hi_4",
+ ,1,1},
+ { "__amdil_ffb_hi_4",
"mdef(37)_out(1)_in(1)\n"
"mov r0, in0\n"
"ffb_hi r0, r0\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_ffb_lo_1",
+ ,1,1},
+ { "__amdil_ffb_lo_1",
"mdef(38)_out(1)_in(1)\n"
"mov r0, in0\n"
"ffb_lo r0.x, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_ffb_lo_2",
+ ,1,1},
+ { "__amdil_ffb_lo_2",
"mdef(39)_out(1)_in(1)\n"
"mov r0, in0\n"
"ffb_lo r0.xy, r0.xy\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_ffb_lo_3",
+ ,1,1},
+ { "__amdil_ffb_lo_3",
"mdef(40)_out(1)_in(1)\n"
"mov r0, in0\n"
"ffb_lo r0.xyz, r0.xyz\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_ffb_lo_4",
+ ,1,1},
+ { "__amdil_ffb_lo_4",
"mdef(41)_out(1)_in(1)\n"
"mov r0, in0\n"
"ffb_lo r0, r0\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_float_to_half_near_f32",
+ ,1,1},
+ { "__amdil_float_to_half_near_f32",
"mdef(42)_out(1)_in(1)\n"
"mov r0, in0\n"
"dcl_literal l1, 0x007fffff, 0x007fffff, 0x007fffff, 0x007fffff\n"
@@ -777,10 +693,8 @@
"ior r0.x, r5.x, r10.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_float_to_half_near_v2f32",
+ ,1,1},
+ { "__amdil_float_to_half_near_v2f32",
"mdef(43)_out(1)_in(1)\n"
"mov r0, in0\n"
"dcl_literal l1, 0x007fffff, 0x007fffff, 0x007fffff, 0x007fffff\n"
@@ -840,10 +754,8 @@
"ior r0.xy, r5.xy, r10.xy\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_float_to_half_near_v4f32",
+ ,1,1},
+ { "__amdil_float_to_half_near_v4f32",
"mdef(44)_out(1)_in(1)\n"
"mov r0, in0\n"
"dcl_literal l1, 0x007fffff, 0x007fffff, 0x007fffff, 0x007fffff\n"
@@ -903,10 +815,8 @@
"ior r0, r5, r10\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_float_to_half_neg_inf_f32",
+ ,1,1},
+ { "__amdil_float_to_half_neg_inf_f32",
"mdef(45)_out(1)_in(1)\n"
"mov r0, in0\n"
"dcl_literal l1, 0x007fffff, 0x007fffff, 0x007fffff, 0x007fffff\n"
@@ -967,10 +877,8 @@
"ior r0.x, r5.x, r10.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_float_to_half_neg_inf_v2f32",
+ ,1,1},
+ { "__amdil_float_to_half_neg_inf_v2f32",
"mdef(46)_out(1)_in(1)\n"
"mov r0, in0\n"
"dcl_literal l1, 0x007fffff, 0x007fffff, 0x007fffff, 0x007fffff\n"
@@ -1031,10 +939,8 @@
"ior r0.xy, r5.xy, r10.xy\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_float_to_half_neg_inf_v4f32",
+ ,1,1},
+ { "__amdil_float_to_half_neg_inf_v4f32",
"mdef(47)_out(1)_in(1)\n"
"mov r0, in0\n"
"dcl_literal l1, 0x007fffff, 0x007fffff, 0x007fffff, 0x007fffff\n"
@@ -1095,10 +1001,8 @@
"ior r0, r5, r10\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_float_to_half_plus_inf_f32",
+ ,1,1},
+ { "__amdil_float_to_half_plus_inf_f32",
"mdef(48)_out(1)_in(1)\n"
"mov r0, in0\n"
"dcl_literal l1, 0x007fffff, 0x007fffff, 0x007fffff, 0x007fffff\n"
@@ -1159,10 +1063,8 @@
"ior r0.x, r5.x, r10.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_float_to_half_plus_inf_v2f32",
+ ,1,1},
+ { "__amdil_float_to_half_plus_inf_v2f32",
"mdef(49)_out(1)_in(1)\n"
"mov r0, in0\n"
"dcl_literal l1, 0x007fffff, 0x007fffff, 0x007fffff, 0x007fffff\n"
@@ -1223,10 +1125,8 @@
"ior r0.xy, r5.xy, r10.xy\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_float_to_half_plus_inf_v4f32",
+ ,1,1},
+ { "__amdil_float_to_half_plus_inf_v4f32",
"mdef(50)_out(1)_in(1)\n"
"mov r0, in0\n"
"dcl_literal l1, 0x007fffff, 0x007fffff, 0x007fffff, 0x007fffff\n"
@@ -1287,81 +1187,63 @@
"ior r0, r5, r10\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_float_to_int_flr_f32",
+ ,1,1},
+ { "__amdil_float_to_int_flr_f32",
"mdef(51)_out(1)_in(1)\n"
"mov r0, in0\n"
"round_neginf r0.x, r0.x\n"
"ftoi r0.x, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_float_to_int_flr_v2f32",
+ ,1,1},
+ { "__amdil_float_to_int_flr_v2f32",
"mdef(52)_out(1)_in(1)\n"
"mov r0, in0\n"
"round_neginf r0.xy, r0.xy\n"
"ftoi r0.xy, r0.xy\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_float_to_int_flr_v4f32",
+ ,1,1},
+ { "__amdil_float_to_int_flr_v4f32",
"mdef(53)_out(1)_in(1)\n"
"mov r0, in0\n"
"round_neginf r0, r0\n"
"ftoi r0, r0\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_f_2_u4",
+ ,1,1},
+ { "__amdil_f_2_u4",
"mdef(54)_out(1)_in(1)\n"
"mov r0, in0\n"
"f_2_u4 r0.x___, r0\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_global_id",
+ ,1,1},
+ { "__amdil_global_id",
"mdef(55)_out(1)_in(0)\n"
"mov r0.xyz, vAbsTid.xyz\n"
"mov out0, r0\n"
"mend\n"
- ,0,1
- },
- {
- "__amdil_global_id_flat",
+ ,0,1},
+ { "__amdil_global_id_flat",
"mdef(56)_out(1)_in(0)\n"
"mov r0.x, vAbsTidFlat.x\n"
"mov out0, r0\n"
"mend\n"
- ,0,1
- },
- {
- "__amdil_group_id",
+ ,0,1},
+ { "__amdil_group_id",
"mdef(57)_out(1)_in(0)\n"
"mov r0.xyz, vThreadGrpId.xyz\n"
"mov out0, r0\n"
"mend\n"
- ,0,1
- },
- {
- "__amdil_group_id_flat",
+ ,0,1},
+ { "__amdil_group_id_flat",
"mdef(58)_out(1)_in(0)\n"
"mov r0.x, vThreadGrpIdFlat.x\n"
"mov out0, r0\n"
"mend\n"
- ,0,1
- },
- {
- "__amdil_imad_1",
+ ,0,1},
+ { "__amdil_imad_1",
"mdef(59)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -1369,10 +1251,8 @@
"imad r0.x, r0.x, r1.x, r2.x\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_imad_2",
+ ,3,1},
+ { "__amdil_imad_2",
"mdef(60)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -1380,10 +1260,8 @@
"imad r0.xy, r0.xy, r1.xy, r2.xy\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_imad_3",
+ ,3,1},
+ { "__amdil_imad_3",
"mdef(61)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -1391,10 +1269,8 @@
"imad r0.xyz, r0.xyz, r1.xyz, r2.xyz\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_imad_4",
+ ,3,1},
+ { "__amdil_imad_4",
"mdef(62)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -1402,90 +1278,72 @@
"imad r0, r0, r1, r2\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_imax_1",
+ ,3,1},
+ { "__amdil_imax_1",
"mdef(63)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"imax r0.x, r0.x, r1.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_imax_2",
+ ,2,1},
+ { "__amdil_imax_2",
"mdef(64)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"imax r0.xy, r0.xy, r1.xy\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_imax_3",
+ ,2,1},
+ { "__amdil_imax_3",
"mdef(65)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"imax r0.xyz, r0.xyz, r1.xyz\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_imax_4",
+ ,2,1},
+ { "__amdil_imax_4",
"mdef(66)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"imax r0, r0, r1\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_imin_1",
+ ,2,1},
+ { "__amdil_imin_1",
"mdef(67)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"imin r0.x, r0.x, r1.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_imin_2",
+ ,2,1},
+ { "__amdil_imin_2",
"mdef(68)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"imin r0.xy, r0.xy, r1.xy\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_imin_3",
+ ,2,1},
+ { "__amdil_imin_3",
"mdef(69)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"imin r0.xyz, r0.xyz, r1.xyz\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_imin_4",
+ ,2,1},
+ { "__amdil_imin_4",
"mdef(70)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"imin r0, r0, r1\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_improved_div_f32",
+ ,2,1},
+ { "__amdil_improved_div_f32",
"mdef(71)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -1496,10 +1354,8 @@
"fma r0.x, r4.x, r2.x, r3.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_improved_div_v2f32",
+ ,2,1},
+ { "__amdil_improved_div_v2f32",
"mdef(72)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -1510,10 +1366,8 @@
"fma r0.xy, r4.xy, r2.xy, r3.xy\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_improved_div_v4f32",
+ ,2,1},
+ { "__amdil_improved_div_v4f32",
"mdef(73)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -1524,66 +1378,52 @@
"fma r0, r4, r2, r3\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_imul_high_1",
+ ,2,1},
+ { "__amdil_imul_high_1",
"mdef(74)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"imul_high r0.x, r0.x, r1.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_imul_high_2",
+ ,2,1},
+ { "__amdil_imul_high_2",
"mdef(75)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"imul_high r0.xy, r0.xy, r1.xy\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_imul_high_3",
+ ,2,1},
+ { "__amdil_imul_high_3",
"mdef(76)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"imul_high r0.xyz, r0.xyz, r1.xyz\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_imul_high_4",
+ ,2,1},
+ { "__amdil_imul_high_4",
"mdef(77)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"imul_high r0, r0, r1\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_local_id",
+ ,2,1},
+ { "__amdil_local_id",
"mdef(78)_out(1)_in(0)\n"
"mov r0.xyz, vTidInGrp.xyz\n"
"mov out0, r0\n"
"mend\n"
- ,0,1
- },
- {
- "__amdil_local_id_flat",
+ ,0,1},
+ { "__amdil_local_id_flat",
"mdef(79)_out(1)_in(0)\n"
"mov r0.x, vTidInGrpFlat.x\n"
"mov out0, r0\n"
"mend\n"
- ,0,1
- },
- {
- "__amdil_lpr_3",
+ ,0,1},
+ { "__amdil_lpr_3",
"mdef(80)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -1591,10 +1431,8 @@
"lrp r0.xyz_, r0.xyz, r1.xyz, r2.xyz\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_lrp_1",
+ ,3,1},
+ { "__amdil_lrp_1",
"mdef(81)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -1602,10 +1440,8 @@
"lrp r0.x___, r0.x, r1.x, r2.x\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_lrp_2",
+ ,3,1},
+ { "__amdil_lrp_2",
"mdef(82)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -1613,10 +1449,8 @@
"lrp r0.xy__, r0.xy, r1.xy, r2.xy\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_lrp_4",
+ ,3,1},
+ { "__amdil_lrp_4",
"mdef(83)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -1624,10 +1458,8 @@
"lrp r0, r0, r1, r2\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_mad_ieee_1",
+ ,3,1},
+ { "__amdil_mad_ieee_1",
"mdef(84)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -1635,10 +1467,8 @@
"mad_ieee r0.x, r0.x, r1.x, r2.x\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_mad_ieee_2",
+ ,3,1},
+ { "__amdil_mad_ieee_2",
"mdef(85)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -1646,10 +1476,8 @@
"mad_ieee r0.xy, r0.xy, r1.xy, r2.xy\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_mad_ieee_3",
+ ,3,1},
+ { "__amdil_mad_ieee_3",
"mdef(86)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -1657,10 +1485,8 @@
"mad_ieee r0.xyz, r0.xyz, r1.xyz, r2.xyz\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_mad_ieee_4",
+ ,3,1},
+ { "__amdil_mad_ieee_4",
"mdef(87)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -1668,306 +1494,240 @@
"mad_ieee r0, r0, r1, r2\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_max_ieee_1",
+ ,3,1},
+ { "__amdil_max_ieee_1",
"mdef(88)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"max_ieee r0.x, r0.x, r1.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_max_ieee_2",
+ ,2,1},
+ { "__amdil_max_ieee_2",
"mdef(89)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"max_ieee r0.xy, r0.xy, r1.xy\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_max_ieee_3",
+ ,2,1},
+ { "__amdil_max_ieee_3",
"mdef(90)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"max_ieee r0.xyz, r0.xyz, r1.xyz\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_max_ieee_4",
+ ,2,1},
+ { "__amdil_max_ieee_4",
"mdef(91)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"max_ieee r0, r0, r1\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_min_ieee_1",
+ ,2,1},
+ { "__amdil_min_ieee_1",
"mdef(92)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"min_ieee r0.x, r0.x, r1.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_min_ieee_2",
+ ,2,1},
+ { "__amdil_min_ieee_2",
"mdef(93)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"min_ieee r0.xy, r0.xy, r1.xy\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_min_ieee_3",
+ ,2,1},
+ { "__amdil_min_ieee_3",
"mdef(94)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"min_ieee r0.xyz, r0.xyz, r1.xyz\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_min_ieee_4",
+ ,2,1},
+ { "__amdil_min_ieee_4",
"mdef(95)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"min_ieee r0, r0, r1\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_rcp_1",
+ ,2,1},
+ { "__amdil_rcp_1",
"mdef(96)_out(1)_in(1)\n"
"mov r0, in0\n"
"rcp_zeroop(infinity) r0.x___, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_rcp_2",
+ ,1,1},
+ { "__amdil_rcp_2",
"mdef(97)_out(1)_in(1)\n"
"mov r0, in0\n"
"rcp_zeroop(infinity) r0.xy__, r0.xy\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_rcp_3",
+ ,1,1},
+ { "__amdil_rcp_3",
"mdef(98)_out(1)_in(1)\n"
"mov r0, in0\n"
"rcp_zeroop(infinity) r0.xyz_, r0.xyz\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_rcp_4",
+ ,1,1},
+ { "__amdil_rcp_4",
"mdef(99)_out(1)_in(1)\n"
"mov r0, in0\n"
"rcp_zeroop(infinity) r0, r0\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_round_nearest_1",
+ ,1,1},
+ { "__amdil_round_nearest_1",
"mdef(100)_out(1)_in(1)\n"
"mov r0, in0\n"
"round_nearest r0.x___, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_round_nearest_2",
+ ,1,1},
+ { "__amdil_round_nearest_2",
"mdef(101)_out(1)_in(1)\n"
"mov r0, in0\n"
"round_nearest r0.xy__, r0.xy\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_round_nearest_3",
+ ,1,1},
+ { "__amdil_round_nearest_3",
"mdef(102)_out(1)_in(1)\n"
"mov r0, in0\n"
"round_nearest r0.xyz_, r0.xyz\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_round_nearest_4",
+ ,1,1},
+ { "__amdil_round_nearest_4",
"mdef(103)_out(1)_in(1)\n"
"mov r0, in0\n"
"round_nearest r0, r0\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_round_neginf_1",
+ ,1,1},
+ { "__amdil_round_neginf_1",
"mdef(104)_out(1)_in(1)\n"
"mov r0, in0\n"
"round_neginf r0.x___, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_round_neginf_2",
+ ,1,1},
+ { "__amdil_round_neginf_2",
"mdef(105)_out(1)_in(1)\n"
"mov r0, in0\n"
"round_neginf r0.xy__, r0.xy\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_round_neginf_3",
+ ,1,1},
+ { "__amdil_round_neginf_3",
"mdef(106)_out(1)_in(1)\n"
"mov r0, in0\n"
"round_neginf r0.xyz_, r0.xyz\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_round_neginf_4",
+ ,1,1},
+ { "__amdil_round_neginf_4",
"mdef(107)_out(1)_in(1)\n"
"mov r0, in0\n"
"round_neginf r0, r0\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_round_plusinf_1",
+ ,1,1},
+ { "__amdil_round_plusinf_1",
"mdef(108)_out(1)_in(1)\n"
"mov r0, in0\n"
"round_plusinf r0.x___, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_round_plusinf_2",
+ ,1,1},
+ { "__amdil_round_plusinf_2",
"mdef(109)_out(1)_in(1)\n"
"mov r0, in0\n"
"round_plusinf r0.xy__, r0.xy\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_round_plusinf_3",
+ ,1,1},
+ { "__amdil_round_plusinf_3",
"mdef(110)_out(1)_in(1)\n"
"mov r0, in0\n"
"round_plusinf r0.xyz_, r0.xyz\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_round_plusinf_4",
+ ,1,1},
+ { "__amdil_round_plusinf_4",
"mdef(111)_out(1)_in(1)\n"
"mov r0, in0\n"
"round_plusinf r0, r0\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_round_z_1",
+ ,1,1},
+ { "__amdil_round_z_1",
"mdef(112)_out(1)_in(1)\n"
"mov r0, in0\n"
"round_z r0.x___, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_round_z_2",
+ ,1,1},
+ { "__amdil_round_z_2",
"mdef(113)_out(1)_in(1)\n"
"mov r0, in0\n"
"round_z r0.xy__, r0.xy\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_round_z_3",
+ ,1,1},
+ { "__amdil_round_z_3",
"mdef(114)_out(1)_in(1)\n"
"mov r0, in0\n"
"round_z r0.xyz_, r0.xyz\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_round_z_4",
+ ,1,1},
+ { "__amdil_round_z_4",
"mdef(115)_out(1)_in(1)\n"
"mov r0, in0\n"
"round_z r0, r0\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_rsq_vec_1",
+ ,1,1},
+ { "__amdil_rsq_vec_1",
"mdef(116)_out(1)_in(1)\n"
"mov r0, in0\n"
"rsq_vec r0.x___, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_rsq_vec_2",
+ ,1,1},
+ { "__amdil_rsq_vec_2",
"mdef(117)_out(1)_in(1)\n"
"mov r0, in0\n"
"rsq_vec r0.xy__, r0.xy\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_rsq_vec_3",
+ ,1,1},
+ { "__amdil_rsq_vec_3",
"mdef(118)_out(1)_in(1)\n"
"mov r0, in0\n"
"rsq_vec r0.xyz_, r0.xyz\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_rsq_vec_4",
+ ,1,1},
+ { "__amdil_rsq_vec_4",
"mdef(119)_out(1)_in(1)\n"
"mov r0, in0\n"
"rsq_vec r0, r0\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_sad4",
+ ,1,1},
+ { "__amdil_sad4",
"mdef(120)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -1975,10 +1735,8 @@
"sad4 r0.x___, r0, r1, r2.x\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_sadhi_1",
+ ,3,1},
+ { "__amdil_sadhi_1",
"mdef(121)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -1986,10 +1744,8 @@
"sadhi r0.x___, r0.x, r1.x, r2.x\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_sadhi_2",
+ ,3,1},
+ { "__amdil_sadhi_2",
"mdef(122)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -1997,10 +1753,8 @@
"sadhi r0.xy__, r0.xy, r1.xy, r2.xy\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_sadhi_3",
+ ,3,1},
+ { "__amdil_sadhi_3",
"mdef(123)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -2008,10 +1762,8 @@
"sadhi r0.xyz_, r0.xyz, r1.xyz, r2.xyz\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_sadhi_4",
+ ,3,1},
+ { "__amdil_sadhi_4",
"mdef(124)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -2019,10 +1771,8 @@
"sadhi r0, r0, r1, r2\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_sad_1",
+ ,3,1},
+ { "__amdil_sad_1",
"mdef(125)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -2030,10 +1780,8 @@
"sad r0.x___, r0.x, r1.x, r2.x\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_sad_2",
+ ,3,1},
+ { "__amdil_sad_2",
"mdef(126)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -2041,10 +1789,8 @@
"sad r0.xy__, r0.xy, r1.xy, r2.xy\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_sad_3",
+ ,3,1},
+ { "__amdil_sad_3",
"mdef(127)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -2052,10 +1798,8 @@
"sad r0.xyz_, r0.xyz, r1.xyz, r2.xyz\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_sad_4",
+ ,3,1},
+ { "__amdil_sad_4",
"mdef(128)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -2063,46 +1807,36 @@
"sad r0, r0, r1, r2\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_sqrt_vec_1",
+ ,3,1},
+ { "__amdil_sqrt_vec_1",
"mdef(129)_out(1)_in(1)\n"
"mov r0, in0\n"
"sqrt_vec r0.x___, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_sqrt_vec_2",
+ ,1,1},
+ { "__amdil_sqrt_vec_2",
"mdef(130)_out(1)_in(1)\n"
"mov r0, in0\n"
"sqrt_vec r0.xy__, r0.xy\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_sqrt_vec_3",
+ ,1,1},
+ { "__amdil_sqrt_vec_3",
"mdef(131)_out(1)_in(1)\n"
"mov r0, in0\n"
"sqrt_vec r0.xyz_, r0.xyz\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_sqrt_vec_4",
+ ,1,1},
+ { "__amdil_sqrt_vec_4",
"mdef(132)_out(1)_in(1)\n"
"mov r0, in0\n"
"sqrt_vec r0, r0\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_u4lerp_1",
+ ,1,1},
+ { "__amdil_u4lerp_1",
"mdef(133)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -2110,10 +1844,8 @@
"u4lerp r0.x___, r0.x, r1.x, r2.x\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_u4lerp_2",
+ ,3,1},
+ { "__amdil_u4lerp_2",
"mdef(134)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -2121,10 +1853,8 @@
"u4lerp r0.xy__, r0.xy, r1.xy, r2.xy\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_u4lerp_3",
+ ,3,1},
+ { "__amdil_u4lerp_3",
"mdef(135)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -2132,10 +1862,8 @@
"u4lerp r0.xyz_, r0.xyz, r1.xyz, r2.xyz\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_u4lerp_4",
+ ,3,1},
+ { "__amdil_u4lerp_4",
"mdef(136)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -2143,10 +1871,8 @@
"u4lerp r0, r0, r1, r2\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_umad24_1",
+ ,3,1},
+ { "__amdil_umad24_1",
"mdef(137)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -2154,10 +1880,8 @@
"umad24 r0.x, r0.x, r1.x, r2.x\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_umad24_2",
+ ,3,1},
+ { "__amdil_umad24_2",
"mdef(138)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -2165,10 +1889,8 @@
"umad24 r0.xy, r0.xy, r1.xy, r2.xy\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_umad24_3",
+ ,3,1},
+ { "__amdil_umad24_3",
"mdef(139)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -2176,10 +1898,8 @@
"umad24 r0.xyz, r0.xyz, r1.xyz, r2.xyz\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_umad24_4",
+ ,3,1},
+ { "__amdil_umad24_4",
"mdef(140)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -2187,10 +1907,8 @@
"umad24 r0, r0, r1, r2\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_umad_1",
+ ,3,1},
+ { "__amdil_umad_1",
"mdef(141)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -2198,10 +1916,8 @@
"umad r0.x, r0.x, r1.x, r2.x\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_umad_2",
+ ,3,1},
+ { "__amdil_umad_2",
"mdef(142)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -2209,10 +1925,8 @@
"umad r0.xy, r0.xy, r1.xy, r2.xy\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_umad_3",
+ ,3,1},
+ { "__amdil_umad_3",
"mdef(143)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -2220,10 +1934,8 @@
"umad r0.xyz, r0.xyz, r1.xyz, r2.xyz\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_umad_4",
+ ,3,1},
+ { "__amdil_umad_4",
"mdef(144)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -2231,323 +1943,255 @@
"umad r0, r0, r1, r2\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__amdil_umax_1",
+ ,3,1},
+ { "__amdil_umax_1",
"mdef(145)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"umax r0.x, r0.x, r1.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_umax_2",
+ ,2,1},
+ { "__amdil_umax_2",
"mdef(146)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"umax r0.xy, r0.xy, r1.xy\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_umax_3",
+ ,2,1},
+ { "__amdil_umax_3",
"mdef(147)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"umax r0.xyz, r0.xyz, r1.xyz\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_umax_4",
+ ,2,1},
+ { "__amdil_umax_4",
"mdef(148)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"umax r0, r0, r1\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_umin_1",
+ ,2,1},
+ { "__amdil_umin_1",
"mdef(149)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"umin r0.x, r0.x, r1.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_umin_2",
+ ,2,1},
+ { "__amdil_umin_2",
"mdef(150)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"umin r0.xy, r0.xy, r1.xy\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_umin_3",
+ ,2,1},
+ { "__amdil_umin_3",
"mdef(151)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"umin r0.xyz, r0.xyz, r1.xyz\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_umin_4",
+ ,2,1},
+ { "__amdil_umin_4",
"mdef(152)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"umin r0, r0, r1\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_umul24_1",
+ ,2,1},
+ { "__amdil_umul24_1",
"mdef(153)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"umul24 r0.x, r0.x, r1.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_umul24_2",
+ ,2,1},
+ { "__amdil_umul24_2",
"mdef(154)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"umul24 r0.xy, r0.xy, r1.xy\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_umul24_3",
+ ,2,1},
+ { "__amdil_umul24_3",
"mdef(155)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"umul24 r0.xyz, r0.xyz, r1.xyz\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_umul24_4",
+ ,2,1},
+ { "__amdil_umul24_4",
"mdef(156)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"umul24 r0, r0, r1\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_umul_high_1",
+ ,2,1},
+ { "__amdil_umul_high_1",
"mdef(157)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"umul_high r0.x, r0.x, r1.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_umul_high_2",
+ ,2,1},
+ { "__amdil_umul_high_2",
"mdef(158)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"umul_high r0.xy, r0.xy, r1.xy\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_umul_high_3",
+ ,2,1},
+ { "__amdil_umul_high_3",
"mdef(159)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"umul_high r0.xyz, r0.xyz, r1.xyz\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_umul_high_4",
+ ,2,1},
+ { "__amdil_umul_high_4",
"mdef(160)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"umul_high r0, r0, r1\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__amdil_unpack0_1",
+ ,2,1},
+ { "__amdil_unpack0_1",
"mdef(161)_out(1)_in(1)\n"
"mov r0, in0\n"
"unpack0 r0.x___, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_unpack0_2",
+ ,1,1},
+ { "__amdil_unpack0_2",
"mdef(162)_out(1)_in(1)\n"
"mov r0, in0\n"
"unpack0 r0.xy__, r0.xy\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_unpack0_3",
+ ,1,1},
+ { "__amdil_unpack0_3",
"mdef(163)_out(1)_in(1)\n"
"mov r0, in0\n"
"unpack0 r0.xyz_, r0.xyz\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_unpack0_4",
+ ,1,1},
+ { "__amdil_unpack0_4",
"mdef(164)_out(1)_in(1)\n"
"mov r0, in0\n"
"unpack0 r0, r0\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_unpack1_1",
+ ,1,1},
+ { "__amdil_unpack1_1",
"mdef(165)_out(1)_in(1)\n"
"mov r0, in0\n"
"unpack1 r0.x___, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_unpack1_2",
+ ,1,1},
+ { "__amdil_unpack1_2",
"mdef(166)_out(1)_in(1)\n"
"mov r0, in0\n"
"unpack1 r0.xy__, r0.xy\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_unpack1_3",
+ ,1,1},
+ { "__amdil_unpack1_3",
"mdef(167)_out(1)_in(1)\n"
"mov r0, in0\n"
"unpack1 r0.xyz_, r0.xyz\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_unpack1_4",
+ ,1,1},
+ { "__amdil_unpack1_4",
"mdef(168)_out(1)_in(1)\n"
"mov r0, in0\n"
"unpack1 r0, r0\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_unpack2_1",
+ ,1,1},
+ { "__amdil_unpack2_1",
"mdef(169)_out(1)_in(1)\n"
"mov r0, in0\n"
"unpack2 r0.x___, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_unpack2_2",
+ ,1,1},
+ { "__amdil_unpack2_2",
"mdef(170)_out(1)_in(1)\n"
"mov r0, in0\n"
"unpack2 r0.xy__, r0.xy\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_unpack2_3",
+ ,1,1},
+ { "__amdil_unpack2_3",
"mdef(171)_out(1)_in(1)\n"
"mov r0, in0\n"
"unpack2 r0.xyz_, r0.xyz\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_unpack2_4",
+ ,1,1},
+ { "__amdil_unpack2_4",
"mdef(172)_out(1)_in(1)\n"
"mov r0, in0\n"
"unpack2 r0, r0\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_unpack3_1",
+ ,1,1},
+ { "__amdil_unpack3_1",
"mdef(173)_out(1)_in(1)\n"
"mov r0, in0\n"
"unpack3 r0.x___, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_unpack3_2",
+ ,1,1},
+ { "__amdil_unpack3_2",
"mdef(174)_out(1)_in(1)\n"
"mov r0, in0\n"
"unpack3 r0.xy__, r0.xy\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_unpack3_3",
+ ,1,1},
+ { "__amdil_unpack3_3",
"mdef(175)_out(1)_in(1)\n"
"mov r0, in0\n"
"unpack3 r0.xyz_, r0.xyz\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amdil_unpack3_4",
+ ,1,1},
+ { "__amdil_unpack3_4",
"mdef(176)_out(1)_in(1)\n"
"mov r0, in0\n"
"unpack3 r0, r0\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__amd_early_exit",
+ ,1,1},
+ { "__amd_early_exit",
"mdef(177)_out(1)_in(1)\n"
"mov r0, in0\n"
"ret_logical_non_zero r0\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__asinh_f32",
+ ,1,1},
+ { "__asinh_f32",
"mdef(178)_out(1)_in(1)\n"
"mov r0, in0\n"
"dcl_literal l0, 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF\n"
@@ -2644,10 +2288,8 @@
"cmov_logical r0.x___, r1.w, l34, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__asinpi_f32",
+ ,1,1},
+ { "__asinpi_f32",
"mdef(179)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -2873,10 +2515,8 @@
"cmov_logical r0.x___, r0.y, l61, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__asin_f32",
+ ,1,1},
+ { "__asin_f32",
"mdef(180)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r1.x___, r0.x\n"
@@ -2953,10 +2593,8 @@
"cmov_logical r0.x___, r0.w, l26, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__atan2pi_f32",
+ ,1,1},
+ { "__atan2pi_f32",
"mdef(181)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -3405,10 +3043,8 @@
"cmov_logical r0.x___, r2.y, r0.y, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__atan2_f32",
+ ,2,1},
+ { "__atan2_f32",
"mdef(182)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -3757,10 +3393,8 @@
"cmov_logical r0.x___, r2.y, r0.y, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__atanh_f32",
+ ,2,1},
+ { "__atanh_f32",
"mdef(183)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r1.x ___, r0.x\n"
@@ -3863,10 +3497,8 @@
"cmov_logical r0.x___, r1.x, r0.z, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__atanpi_f32",
+ ,1,1},
+ { "__atanpi_f32",
"mdef(184)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -4080,10 +3712,8 @@
"cmov_logical r0.x___, r0.y, r0.x, r0.z\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__atan_f32",
+ ,1,1},
+ { "__atan_f32",
"mdef(185)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -4163,10 +3793,8 @@
"cmov_logical r0.x___, r0.y, r0.x, r0.z\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__cbrt_f32",
+ ,1,1},
+ { "__cbrt_f32",
"mdef(186)_out(1)_in(1)\n"
"mov r0, in0\n"
"dcl_literal l0, 0x00000000, 0x7FFFFFFF, 0x7F800000, 0x007FFFFF\n"
@@ -4349,19 +3977,15 @@
"cmov_logical r0.x___, r0.y, r0.x, r0.z\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__ceil_f32",
+ ,1,1},
+ { "__ceil_f32",
"mdef(187)_out(1)_in(1)\n"
"mov r0, in0\n"
"round_plusinf r0.x___, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__clamp_f32",
+ ,1,1},
+ { "__clamp_f32",
"mdef(188)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -4370,10 +3994,8 @@
"min r0.x___, r2.x, r0.w\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__copysign_f32",
+ ,3,1},
+ { "__copysign_f32",
"mdef(189)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -4384,10 +4006,8 @@
"ior r0.x___, r0.y, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__cosh_f32",
+ ,2,1},
+ { "__cosh_f32",
"mdef(190)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -4555,10 +4175,8 @@
"cmov_logical r0.x___, r0.y, r0.z, l45\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__cospi_f32",
+ ,1,1},
+ { "__cospi_f32",
"mdef(191)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -4663,10 +4281,8 @@
"cmov_logical r0.x___, r0.y, r0.x, r0.z\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__cos_f32",
+ ,1,1},
+ { "__cos_f32",
"mdef(192)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -5717,10 +5333,8 @@
"cmov_logical r0.x___, r0.y, r0.x, r0.z\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__cross_4f32",
+ ,1,1},
+ { "__cross_4f32",
"mdef(193)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -5762,10 +5376,8 @@
"add r0.xyz_, r2.xyzx, r0.xyzx\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__ddiv_f64",
+ ,2,1},
+ { "__ddiv_f64",
"mdef(194)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -5861,10 +5473,8 @@
"mov r0.xy, r10.xy\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__ddiv_f64_fma",
+ ,2,1},
+ { "__ddiv_f64_fma",
"mdef(195)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -5940,20 +5550,16 @@
"mov r0.xy, r10.xy\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__degrees_f32",
+ ,2,1},
+ { "__degrees_f32",
"mdef(196)_out(1)_in(1)\n"
"mov r0, in0\n"
"dcl_literal l0, 0x42652EE1, 0x00000000, 0x00000000, 0x00000000\n"
"mul_ieee r0.x___, r0.x, l0\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__distance_2f32",
+ ,1,1},
+ { "__distance_2f32",
"mdef(197)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -5962,10 +5568,8 @@
"sqrt_vec r0.x___, r2.y\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__distance_4f32",
+ ,2,1},
+ { "__distance_4f32",
"mdef(198)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -5976,10 +5580,8 @@
"sqrt_vec r0.x___, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__distance_f32",
+ ,2,1},
+ { "__distance_f32",
"mdef(199)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -5987,20 +5589,16 @@
"mov r0.x___, r2.y_abs\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__dot_2f32",
+ ,2,1},
+ { "__dot_2f32",
"mdef(200)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"dp2_ieee r0.x___, r1.xyxx, r0.xyxx\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__dot_3f32",
+ ,2,1},
+ { "__dot_3f32",
"mdef(201)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -6008,10 +5606,8 @@
"mad_ieee r0.x___, r1.z, r0.z, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__dot_4f32",
+ ,2,1},
+ { "__dot_4f32",
"mdef(202)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -6020,20 +5616,16 @@
"mad_ieee r0.x___, r1.w, r0.w, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__dot_f32",
+ ,2,1},
+ { "__dot_f32",
"mdef(203)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"mul_ieee r0.x___, r1.x, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__erfc_f32",
+ ,2,1},
+ { "__erfc_f32",
"mdef(204)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -6554,10 +6146,8 @@
"cmov_logical r0.x___, r0.y, r0.x, r0.z\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__erf_f32",
+ ,1,1},
+ { "__erf_f32",
"mdef(205)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -7080,10 +6670,8 @@
"cmov_logical r0.x___, r0.y, r0.x, r0.z\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__exp10_f32",
+ ,1,1},
+ { "__exp10_f32",
"mdef(206)_out(1)_in(1)\n"
"mov r0, in0\n"
"dcl_literal l0, 0x40549A78, 0x40549A78, 0x40549A78, 0x40549A78\n"
@@ -7230,10 +6818,8 @@
"cmov_logical r0.x___, r0.x, l50, r0.y\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__exp2_f32",
+ ,1,1},
+ { "__exp2_f32",
"mdef(207)_out(1)_in(1)\n"
"mov r0, in0\n"
"round_nearest r0._y__, r0.x\n"
@@ -7334,10 +6920,8 @@
"cmov_logical r0.x___, r0.z, r0.x, r0.y\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__expm1_f32",
+ ,1,1},
+ { "__expm1_f32",
"mdef(208)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r3.x___, r0.x\n"
@@ -7559,10 +7143,8 @@
"cmov_logical r0.x___, r3.z, l78, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__exp_f32",
+ ,1,1},
+ { "__exp_f32",
"mdef(209)_out(1)_in(1)\n"
"mov r0, in0\n"
"dcl_literal l0, 0x00000000, 0x00000000, 0xC2CFF1B5, 0x00000000\n"
@@ -7667,20 +7249,16 @@
"cmov_logical r0.x___, r0.z, r0.x, r0.y\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__fabs_f32",
+ ,1,1},
+ { "__fabs_f32",
"mdef(210)_out(1)_in(1)\n"
"mov r0, in0\n"
"dcl_literal l0, 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF\n"
"and r0.x___, r0.x, l0\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__fast_distance_2f32",
+ ,1,1},
+ { "__fast_distance_2f32",
"mdef(211)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -7689,10 +7267,8 @@
"sqrt_vec r0.x___, r2.y\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__fast_distance_4f32",
+ ,2,1},
+ { "__fast_distance_4f32",
"mdef(212)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -7703,10 +7279,8 @@
"sqrt_vec r0.x___, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__fast_distance_f32",
+ ,2,1},
+ { "__fast_distance_f32",
"mdef(213)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -7714,20 +7288,16 @@
"mov r0.x___, r2.y_abs\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__fast_length_2f32",
+ ,2,1},
+ { "__fast_length_2f32",
"mdef(214)_out(1)_in(1)\n"
"mov r0, in0\n"
"dp2_ieee r1._y__, r0.xyxx, r0.xyxx\n"
"sqrt_vec r0.x___, r1.y\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__fast_length_4f32",
+ ,1,1},
+ { "__fast_length_4f32",
"mdef(215)_out(1)_in(1)\n"
"mov r0, in0\n"
"dp2_ieee r0.x___, r0.xyxx, r0.xyxx\n"
@@ -7736,19 +7306,15 @@
"sqrt_vec r0.x___, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__fast_length_f32",
+ ,1,1},
+ { "__fast_length_f32",
"mdef(216)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r0.x___, r0.x_abs\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__fast_normalize_2f32",
+ ,1,1},
+ { "__fast_normalize_2f32",
"mdef(217)_out(1)_in(1)\n"
"mov r0, in0\n"
"dp2_ieee r2.x___, r0.xyxx, r0.xyxx\n"
@@ -7780,10 +7346,8 @@
"\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__fast_normalize_4f32",
+ ,1,1},
+ { "__fast_normalize_4f32",
"mdef(218)_out(1)_in(1)\n"
"mov r0, in0\n"
"dp2_ieee r2.x___, r0.xyxx, r0.xyxx\n"
@@ -7816,10 +7380,8 @@
"\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__fast_normalize_f32",
+ ,1,1},
+ { "__fast_normalize_f32",
"mdef(219)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r2.x___, r0.x_abs\n"
@@ -7851,10 +7413,8 @@
"\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__fdim_f32",
+ ,1,1},
+ { "__fdim_f32",
"mdef(220)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -8055,10 +7615,8 @@
"cmov_logical r0.x___, r0.w, r0.y, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__fdiv_f32",
+ ,2,1},
+ { "__fdiv_f32",
"mdef(221)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -8099,19 +7657,15 @@
"cmov_logical r0.x, r4.x, r4.y, r2.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__floor_f32",
+ ,2,1},
+ { "__floor_f32",
"mdef(222)_out(1)_in(1)\n"
"mov r0, in0\n"
"round_neginf r0.x___, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__fmax_f32",
+ ,1,1},
+ { "__fmax_f32",
"mdef(223)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -8145,10 +7699,8 @@
"cmov_logical r0.x___, r1.x, l5, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__fma_f32",
+ ,2,1},
+ { "__fma_f32",
"mdef(224)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -8284,10 +7836,8 @@
"mov r0.x, r23.x\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__fma_f64",
+ ,3,1},
+ { "__fma_f64",
"mdef(225)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -8295,10 +7845,8 @@
"dmad r0.xy__, r0.xy, r1.xy, r2.xy\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__fmin_f32",
+ ,3,1},
+ { "__fmin_f32",
"mdef(226)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -8334,10 +7882,8 @@
"cmov_logical r0.x___, r0.w, r0.x, r0.y\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__fmod_f32",
+ ,2,1},
+ { "__fmod_f32",
"mdef(227)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -8869,10 +8415,8 @@
"cmov_logical r0.x___, r0.z, r0.x, r0.y\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__fract_2f32f32",
+ ,2,1},
+ { "__fract_2f32f32",
"mdef(228)_out(1)_in(1)\n"
"mov r0, in0\n"
"round_z r1._y__, r0.x\n"
@@ -8924,10 +8468,8 @@
"cmov_logical r0.xy__, r0.w, l17, r0.xyxx\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__frexp_2f32f32",
+ ,1,1},
+ { "__frexp_2f32f32",
"mdef(229)_out(1)_in(1)\n"
"mov r0, in0\n"
"dcl_literal l0, 0x00000000, 0x80000000, 0x7FFFFFFF, 0x00000000\n"
@@ -8985,10 +8527,8 @@
"mov r0._y__, r2.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__ftol_i64",
+ ,1,1},
+ { "__ftol_i64",
"mdef(230)_out(1)_in(1)\n"
"mov r0, in0\n"
"dcl_literal l0, 0x7F800000, 0x80000000, 0x007FFFFF, 0x00000000\n"
@@ -9051,10 +8591,8 @@
"cmov_logical r0.xy__, r0.x, l21, r1.zwzz\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__ftoul_i64",
+ ,1,1},
+ { "__ftoul_i64",
"mdef(231)_out(1)_in(1)\n"
"mov r0, in0\n"
"dcl_literal l0, 0x7F800000, 0x007FFFFF, 0x80000000, 0x00000000\n"
@@ -9111,10 +8649,8 @@
"cmov_logical r0.xy__, r0.x, l20, r0.ywyy\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__ftz_2f32",
+ ,1,1},
+ { "__ftz_2f32",
"mdef(232)_out(1)_in(1)\n"
"mov r0, in0\n"
"dcl_literal l1, 0x7F800000, 0xFFFFFFFF, 0x80000000, 0x00000000\n"
@@ -9123,10 +8659,8 @@
"iand r0.xy__, r0.xy, r1.xy\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__ftz_4f32",
+ ,1,1},
+ { "__ftz_4f32",
"mdef(233)_out(1)_in(1)\n"
"mov r0, in0\n"
"dcl_literal l1, 0x7F800000, 0xFFFFFFFF, 0x80000000, 0x00000000\n"
@@ -9135,10 +8669,8 @@
"iand r0, r0, r1\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__ftz_f32",
+ ,1,1},
+ { "__ftz_f32",
"mdef(234)_out(1)_in(1)\n"
"mov r0, in0\n"
"dcl_literal l1, 0x7F800000, 0xFFFFFFFF, 0x80000000, 0x00000000\n"
@@ -9147,10 +8679,8 @@
"iand r0.x___, r0.x, r1.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__half_cos_f32",
+ ,1,1},
+ { "__half_cos_f32",
"mdef(235)_out(1)_in(1)\n"
"mov r0, in0\n"
"dcl_literal l0, 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF\n"
@@ -9361,10 +8891,8 @@
"cmov_logical r0.x___, r0.y, l56, r0.z\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__half_divide_f32",
+ ,1,1},
+ { "__half_divide_f32",
"mdef(236)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -9594,10 +9122,8 @@
"endif\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__half_exp10_f32",
+ ,2,1},
+ { "__half_exp10_f32",
"mdef(237)_out(1)_in(1)\n"
"mov r0, in0\n"
"dcl_literal l0, 0x421A209B, 0x421A209B, 0x421A209B, 0x421A209B\n"
@@ -9644,10 +9170,8 @@
"cmov_logical r0.x___, r0.x, l16, r0.y\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__half_exp2_f32",
+ ,1,1},
+ { "__half_exp2_f32",
"mdef(238)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -9695,10 +9219,8 @@
"cmov_logical r0.x___, r0.z, r0.x, r0.y\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__half_exp_f32",
+ ,1,1},
+ { "__half_exp_f32",
"mdef(239)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -9749,10 +9271,8 @@
"cmov_logical r0.x___, r0.z, r0.x, r0.y\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__half_log10_f32",
+ ,1,1},
+ { "__half_log10_f32",
"mdef(240)_out(1)_in(1)\n"
"mov r0, in0\n"
"dcl_literal l0, 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF\n"
@@ -9893,10 +9413,8 @@
"cmov_logical r0.x___, r1.y, r0.x, r0.y\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__half_log2_f32",
+ ,1,1},
+ { "__half_log2_f32",
"mdef(241)_out(1)_in(1)\n"
"mov r0, in0\n"
"dcl_literal l0, 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF\n"
@@ -10031,10 +9549,8 @@
"cmov_logical r0.x___, r1.y, r0.z, r0.y\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__half_log_f32",
+ ,1,1},
+ { "__half_log_f32",
"mdef(242)_out(1)_in(1)\n"
"mov r0, in0\n"
"dcl_literal l0, 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF\n"
@@ -10175,10 +9691,8 @@
"cmov_logical r0.x___, r1.y, r0.x, r0.y\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__half_powr_f32",
+ ,1,1},
+ { "__half_powr_f32",
"mdef(243)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -10735,10 +10249,8 @@
"cmov_logical r0.x___, r0.y, l194, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__half_recip_f32",
+ ,2,1},
+ { "__half_recip_f32",
"mdef(244)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r1.x___, r0.x\n"
@@ -10845,10 +10357,8 @@
"cmov_logical r0.x___, r0.x, r0.y, r0.w\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__half_rsqrt_f32",
+ ,1,1},
+ { "__half_rsqrt_f32",
"mdef(245)_out(1)_in(1)\n"
"mov r0, in0\n"
"dcl_literal l0, 0x00000000, 0x7FFFFFFF, 0x7F800000, 0x00000000\n"
@@ -10975,10 +10485,8 @@
"endif\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__half_sin_f32",
+ ,1,1},
+ { "__half_sin_f32",
"mdef(246)_out(1)_in(1)\n"
"mov r0, in0\n"
"dcl_literal l0, 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF\n"
@@ -11168,10 +10676,8 @@
"cmov_logical r0.x___, r0.y, l49, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__half_sqrt_f32",
+ ,1,1},
+ { "__half_sqrt_f32",
"mdef(247)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -11197,10 +10703,8 @@
"cmov_logical r0.x___, r0.y, r0.w, r0.z\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__half_tan_f32",
+ ,1,1},
+ { "__half_tan_f32",
"mdef(248)_out(1)_in(1)\n"
"mov r0, in0\n"
"dcl_literal l0, 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF\n"
@@ -11348,10 +10852,8 @@
"cmov_logical r0.x___, r0.y, l38, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__hwfma_f32",
+ ,1,1},
+ { "__hwfma_f32",
"mdef(249)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -11359,10 +10861,8 @@
"fma r0.x___, r0.x, r1.x, r2.x\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__hypot_f32",
+ ,3,1},
+ { "__hypot_f32",
"mdef(250)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -11725,10 +11225,8 @@
"cmov_logical r0.x___, r0.y, l100, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__ilogb_f32",
+ ,2,1},
+ { "__ilogb_f32",
"mdef(251)_out(1)_in(1)\n"
"mov r0, in0\n"
"dcl_literal l0, 0x7FFFFFFF, 0x7F800000, 0x00000000, 0x00000000\n"
@@ -11770,10 +11268,8 @@
"cmov_logical r0.x___, r0.w, l16, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__ldexp_f32i32",
+ ,1,1},
+ { "__ldexp_f32i32",
"mdef(252)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -11854,20 +11350,16 @@
"cmov_logical r0.x___, r0.z, r0.x, r0.y\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__length_2f32",
+ ,2,1},
+ { "__length_2f32",
"mdef(253)_out(1)_in(1)\n"
"mov r0, in0\n"
"dp2_ieee r1._y__, r0.xyxx, r0.xyxx\n"
"sqrt_vec r0.x___, r1.y\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__length_4f32",
+ ,1,1},
+ { "__length_4f32",
"mdef(254)_out(1)_in(1)\n"
"mov r0, in0\n"
"dp2_ieee r0.x___, r0.xyxx, r0.xyxx\n"
@@ -11876,19 +11368,15 @@
"sqrt_vec r0.x___, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__length_f32",
+ ,1,1},
+ { "__length_f32",
"mdef(255)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r0.x___, r0.x_abs\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__lgamma_f32",
+ ,1,1},
+ { "__lgamma_f32",
"mdef(256)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -12543,10 +12031,8 @@
"cmov_logical r0.x___, r0.x, l171, r0.y\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__lgamma_r_2f32f32",
+ ,1,1},
+ { "__lgamma_r_2f32f32",
"mdef(257)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r1.x___, r0.x_neg(xyzw)\n"
@@ -13238,226 +12724,176 @@
"mov r0.y, r1.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__load_128bit_global",
+ ,1,1},
+ { "__load_128bit_global",
"mdef(258)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r0, g[r0.x]\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__load_128bit_local",
+ ,1,1},
+ { "__load_128bit_local",
"mdef(259)_out(1)_in(1)\n"
"mov r0, in0\n"
"lds_load_vec_id(0) r0, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__load_128bit_private",
+ ,1,1},
+ { "__load_128bit_private",
"mdef(260)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r0, x0[r0.x]\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__load_128bit_uav",
+ ,1,1},
+ { "__load_128bit_uav",
"mdef(261)_out(1)_in(1)\n"
"mov r0, in0\n"
"uav_raw_load_id(0) r0, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__load_32bit_local",
+ ,1,1},
+ { "__load_32bit_local",
"mdef(262)_out(1)_in(1)\n"
"mov r0, in0\n"
"lds_load_id(0) r0.x, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__load_32bit_uav",
+ ,1,1},
+ { "__load_32bit_uav",
"mdef(263)_out(1)_in(1)\n"
"mov r0, in0\n"
"uav_raw_load_id(0) r0.x, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__load_64bit_local",
+ ,1,1},
+ { "__load_64bit_local",
"mdef(264)_out(1)_in(1)\n"
"mov r0, in0\n"
"lds_load_vec_id(0) r0.xy__, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__load_64bit_uav",
+ ,1,1},
+ { "__load_64bit_uav",
"mdef(265)_out(1)_in(1)\n"
"mov r0, in0\n"
"uav_raw_load_id(0) r0.xy, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__load_96bit_global",
+ ,1,1},
+ { "__load_96bit_global",
"mdef(266)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r0.xyz_, g[r0.x].xyz\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__load_96bit_local",
+ ,1,1},
+ { "__load_96bit_local",
"mdef(267)_out(1)_in(1)\n"
"mov r0, in0\n"
"lds_load_vec_id(0) r0.xyz_, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__load_96bit_private",
+ ,1,1},
+ { "__load_96bit_private",
"mdef(268)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r0.xyz_, x0[r0.x].xyz\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__load_96bit_uav",
+ ,1,1},
+ { "__load_96bit_uav",
"mdef(269)_out(1)_in(1)\n"
"mov r0, in0\n"
"uav_raw_load_id(0) r0.xyz, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__load_hi_64bit_global",
+ ,1,1},
+ { "__load_hi_64bit_global",
"mdef(270)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r0.xy__, g[r0.x].zw\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__load_hi_64bit_private",
+ ,1,1},
+ { "__load_hi_64bit_private",
"mdef(271)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r0.xy__, x0[r0.x].zw\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__load_lo_64bit_global",
+ ,1,1},
+ { "__load_lo_64bit_global",
"mdef(272)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r0.xy__, g[r0.x].xy\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__load_lo_64bit_private",
+ ,1,1},
+ { "__load_lo_64bit_private",
"mdef(273)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r0.xy__, x0[r0.x].xy\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__load_w_32bit_global",
+ ,1,1},
+ { "__load_w_32bit_global",
"mdef(274)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r0.x, g[r0.x].w\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__load_w_32bit_private",
+ ,1,1},
+ { "__load_w_32bit_private",
"mdef(275)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r0.x, x0[r0.x].w\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__load_x_32bit_global",
+ ,1,1},
+ { "__load_x_32bit_global",
"mdef(276)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r0.x, g[r0.x].x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__load_x_32bit_private",
+ ,1,1},
+ { "__load_x_32bit_private",
"mdef(277)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r0.x, x0[r0.x].x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__load_y_32bit_global",
+ ,1,1},
+ { "__load_y_32bit_global",
"mdef(278)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r0.x, g[r0.x].y\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__load_y_32bit_private",
+ ,1,1},
+ { "__load_y_32bit_private",
"mdef(279)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r0.x, x0[r0.x].y\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__load_z_32bit_global",
+ ,1,1},
+ { "__load_z_32bit_global",
"mdef(280)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r0.x, g[r0.x].z\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__load_z_32bit_private",
+ ,1,1},
+ { "__load_z_32bit_private",
"mdef(281)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r0.x, x0[r0.x].z\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__log10_f32",
+ ,1,1},
+ { "__log10_f32",
"mdef(282)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -13587,10 +13023,8 @@
"cmov_logical r0.x___, r0.z, r0.x, r0.y\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__log1p_f32",
+ ,1,1},
+ { "__log1p_f32",
"mdef(283)_out(1)_in(1)\n"
"mov r0, in0\n"
"dcl_literal l0, 0x00000000, 0x40000000, 0x3F800000, 0x00000000\n"
@@ -13853,10 +13287,8 @@
"cmov_logical r0.x___, r1.z, r0.y, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__log2_f32",
+ ,1,1},
+ { "__log2_f32",
"mdef(284)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -13983,10 +13415,8 @@
"cmov_logical r0.x___, r0.z, r0.x, r0.y\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__logb_f32",
+ ,1,1},
+ { "__logb_f32",
"mdef(285)_out(2)_in(1)\n"
"mov r0, in0\n"
"dcl_literal l0, 0x00000000, 0x7FFFFFFF, 0x7F800000, 0x00000000\n"
@@ -14030,10 +13460,8 @@
"mov out0, r0\n"
"mov out1, r1\n"
"mend\n"
- ,1,2
- },
- {
- "__log_f32",
+ ,1,2},
+ { "__log_f32",
"mdef(286)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -14163,10 +13591,8 @@
"cmov_logical r0.x___, r0.z, r0.x, r0.y\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__ltof_f32",
+ ,1,1},
+ { "__ltof_f32",
"mdef(287)_out(1)_in(1)\n"
"mov r0, in0\n"
"inot r0.__zw, r0.xxxy\n"
@@ -14315,10 +13741,8 @@
"ior r0.x___, r0.w, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__mad_f32",
+ ,1,1},
+ { "__mad_f32",
"mdef(288)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -14326,10 +13750,8 @@
"mad_ieee r0.x___, r0.x, r1.x, r2.x\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__mad_f64",
+ ,3,1},
+ { "__mad_f64",
"mdef(289)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -14337,10 +13759,8 @@
"dmad r0.xy__, r0.xy, r1.xy, r2.xy\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__max_f32",
+ ,3,1},
+ { "__max_f32",
"mdef(290)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -14348,10 +13768,8 @@
"max r0.x___, r0.y, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__min_f32",
+ ,2,1},
+ { "__min_f32",
"mdef(291)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -14359,10 +13777,8 @@
"min r0.x___, r0.y, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__mix_f32",
+ ,2,1},
+ { "__mix_f32",
"mdef(292)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -14371,10 +13787,8 @@
"mad_ieee r0.x___, r0.w, r2.x, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__modf_2f32f32",
+ ,3,1},
+ { "__modf_2f32f32",
"mdef(293)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r1.___w, r0.x\n"
@@ -14397,10 +13811,8 @@
"cmov_logical r0.xy__, r0.z, l4, r0.xyxx\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__mul_i64",
+ ,1,1},
+ { "__mul_i64",
"mdef(294)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -14412,10 +13824,8 @@
"iadd r0.xy, r7.x0, r6.0x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__mul_v2i64",
+ ,2,1},
+ { "__mul_v2i64",
"mdef(295)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -14427,10 +13837,8 @@
"iadd r0, r7.x0z0, r6.0x0z\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__nan_u32",
+ ,2,1},
+ { "__nan_u32",
"mdef(296)_out(1)_in(1)\n"
"mov r0, in0\n"
"dcl_literal l0, 0x007FFFFF, 0x007FFFFF, 0x007FFFFF, 0x007FFFFF\n"
@@ -14439,49 +13847,39 @@
"ior r0.x___, r0.x, l1\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__native_cos_f32",
+ ,1,1},
+ { "__native_cos_f32",
"mdef(297)_out(1)_in(1)\n"
"mov r0, in0\n"
"cos_vec r0.x___, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__native_divide_2f32",
+ ,1,1},
+ { "__native_divide_2f32",
"mdef(298)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"div_zeroop(infinity) r0.xy__, r0.xy, r1.xy\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__native_divide_4f32",
+ ,2,1},
+ { "__native_divide_4f32",
"mdef(299)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"div_zeroop(infinity) r0, r0, r1\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__native_divide_f32",
+ ,2,1},
+ { "__native_divide_f32",
"mdef(300)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"div_zeroop(infinity) r0.x___, r0.x, r1.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__native_exp10_2f32",
+ ,2,1},
+ { "__native_exp10_2f32",
"mdef(301)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -14490,10 +13888,8 @@
"exp_vec r0.xy__, r1.xy\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__native_exp10_4f32",
+ ,1,1},
+ { "__native_exp10_4f32",
"mdef(302)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -14502,10 +13898,8 @@
"exp_vec r0, r1\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__native_exp10_f32",
+ ,1,1},
+ { "__native_exp10_f32",
"mdef(303)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -14514,37 +13908,29 @@
"exp_vec r0.x___, r1.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__native_exp2_2f32",
+ ,1,1},
+ { "__native_exp2_2f32",
"mdef(304)_out(1)_in(1)\n"
"mov r0, in0\n"
"exp_vec r0.xy__, r0.xy\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__native_exp2_4f32",
+ ,1,1},
+ { "__native_exp2_4f32",
"mdef(305)_out(1)_in(1)\n"
"mov r0, in0\n"
"exp_vec r0, r0\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__native_exp2_f32",
+ ,1,1},
+ { "__native_exp2_f32",
"mdef(306)_out(1)_in(1)\n"
"mov r0, in0\n"
"exp_vec r0.x___, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__native_exp_2f32",
+ ,1,1},
+ { "__native_exp_2f32",
"mdef(307)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -14553,10 +13939,8 @@
"exp_vec r0.xy__, r1.xy\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__native_exp_4f32",
+ ,1,1},
+ { "__native_exp_4f32",
"mdef(308)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -14565,10 +13949,8 @@
"exp_vec r0, r1\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__native_exp_f32",
+ ,1,1},
+ { "__native_exp_f32",
"mdef(309)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -14577,10 +13959,8 @@
"exp_vec r0.x___, r0.y\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__native_log10_2f32",
+ ,1,1},
+ { "__native_log10_2f32",
"mdef(310)_out(1)_in(1)\n"
"mov r0, in0\n"
"log_vec r1.xy__, r0.x\n"
@@ -14589,10 +13969,8 @@
"mul_ieee r0.xy__, r1.xy, l0\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__native_log10_4f32",
+ ,1,1},
+ { "__native_log10_4f32",
"mdef(311)_out(1)_in(1)\n"
"mov r0, in0\n"
"log_vec r1, r0\n"
@@ -14601,10 +13979,8 @@
"mul_ieee r0, r1, l0\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__native_log10_f32",
+ ,1,1},
+ { "__native_log10_f32",
"mdef(312)_out(1)_in(1)\n"
"mov r0, in0\n"
"log_vec r1.x___, r0.x\n"
@@ -14613,37 +13989,29 @@
"mul_ieee r0.x___, r1.x, l0\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__native_log2_2f32",
+ ,1,1},
+ { "__native_log2_2f32",
"mdef(313)_out(1)_in(1)\n"
"mov r0, in0\n"
"log_vec r0.xy__, r0.xy\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__native_log2_4f32",
+ ,1,1},
+ { "__native_log2_4f32",
"mdef(314)_out(1)_in(1)\n"
"mov r0, in0\n"
"log_vec r0, r0\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__native_log2_f32",
+ ,1,1},
+ { "__native_log2_f32",
"mdef(315)_out(1)_in(1)\n"
"mov r0, in0\n"
"log_vec r0.x___, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__native_log_2f32",
+ ,1,1},
+ { "__native_log_2f32",
"mdef(316)_out(1)_in(1)\n"
"mov r0, in0\n"
"log_vec r1.xy__, r0.xy\n"
@@ -14652,10 +14020,8 @@
"mul_ieee r0.xy__, r1.xy, l0\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__native_log_4f32",
+ ,1,1},
+ { "__native_log_4f32",
"mdef(317)_out(1)_in(1)\n"
"mov r0, in0\n"
"log_vec r1, r0\n"
@@ -14664,10 +14030,8 @@
"mul_ieee r0, r1, l0\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__native_log_f32",
+ ,1,1},
+ { "__native_log_f32",
"mdef(318)_out(1)_in(1)\n"
"mov r0, in0\n"
"log_vec r1.x___, r0.x\n"
@@ -14676,10 +14040,8 @@
"mul_ieee r0.x___, r1.x, l0\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__native_powr_2f32",
+ ,1,1},
+ { "__native_powr_2f32",
"mdef(319)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -14694,10 +14056,8 @@
"cmov_logical r0.xy, r4.xy, l1, r3.xy\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__native_powr_4f32",
+ ,2,1},
+ { "__native_powr_4f32",
"mdef(320)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -14712,10 +14072,8 @@
"cmov_logical r0, r4, l1, r3\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__native_powr_f32",
+ ,2,1},
+ { "__native_powr_f32",
"mdef(321)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -14730,10 +14088,8 @@
"cmov_logical r0.x, r4.x, l1, r3.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__native_recip_2f32",
+ ,2,1},
+ { "__native_recip_2f32",
"mdef(322)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -14741,10 +14097,8 @@
"div_zeroop(infinity) r0.xy__, l0, r0.xy\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__native_recip_4f32",
+ ,1,1},
+ { "__native_recip_4f32",
"mdef(323)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -14752,10 +14106,8 @@
"div_zeroop(infinity) r0, l0, r0\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__native_recip_f32",
+ ,1,1},
+ { "__native_recip_f32",
"mdef(324)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -14763,91 +14115,71 @@
"div_zeroop(infinity) r0.x___, l0, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__native_rsqrt_2f32",
+ ,1,1},
+ { "__native_rsqrt_2f32",
"mdef(325)_out(1)_in(1)\n"
"mov r0, in0\n"
"rsq_vec r0.xy__, r0.xy\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__native_rsqrt_4f32",
+ ,1,1},
+ { "__native_rsqrt_4f32",
"mdef(326)_out(1)_in(1)\n"
"mov r0, in0\n"
"rsq_vec r0, r0\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__native_rsqrt_f32",
+ ,1,1},
+ { "__native_rsqrt_f32",
"mdef(327)_out(1)_in(1)\n"
"mov r0, in0\n"
"rsq_vec r0.x___, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__native_sin_2f32",
+ ,1,1},
+ { "__native_sin_2f32",
"mdef(328)_out(1)_in(1)\n"
"mov r0, in0\n"
"sin_vec r0.xy, r0.xy\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__native_sin_4f32",
+ ,1,1},
+ { "__native_sin_4f32",
"mdef(329)_out(1)_in(1)\n"
"mov r0, in0\n"
"sin_vec r0, r0\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__native_sin_f32",
+ ,1,1},
+ { "__native_sin_f32",
"mdef(330)_out(1)_in(1)\n"
"mov r0, in0\n"
"sin_vec r0.x___, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__native_sqrt_2f32",
+ ,1,1},
+ { "__native_sqrt_2f32",
"mdef(331)_out(1)_in(1)\n"
"mov r0, in0\n"
"sqrt_vec r0.xy__, r0.xy\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__native_sqrt_4f32",
+ ,1,1},
+ { "__native_sqrt_4f32",
"mdef(332)_out(1)_in(1)\n"
"mov r0, in0\n"
"sqrt_vec r0, r0\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__native_sqrt_f32",
+ ,1,1},
+ { "__native_sqrt_f32",
"mdef(333)_out(1)_in(1)\n"
"mov r0, in0\n"
"sqrt_vec r0.x___, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__native_tan_2f32",
+ ,1,1},
+ { "__native_tan_2f32",
"mdef(334)_out(1)_in(1)\n"
"mov r0, in0\n"
"sin_vec r1.xy__, r0.xy\n"
@@ -14855,10 +14187,8 @@
"div_zeroop(infinity) r0.xy__, r1.xy, r2.xy\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__native_tan_4f32",
+ ,1,1},
+ { "__native_tan_4f32",
"mdef(335)_out(1)_in(1)\n"
"mov r0, in0\n"
"sin_vec r1, r0\n"
@@ -14866,10 +14196,8 @@
"div_zeroop(infinity) r0, r1, r2\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__native_tan_f32",
+ ,1,1},
+ { "__native_tan_f32",
"mdef(336)_out(1)_in(1)\n"
"mov r0, in0\n"
"sin_vec r1.x___, r0.x\n"
@@ -14877,10 +14205,8 @@
"div_zeroop(infinity) r0.x___, r1.x, r2.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__nextafter_f32",
+ ,1,1},
+ { "__nextafter_f32",
"mdef(337)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -14919,10 +14245,8 @@
"cmov_logical r0.x___, r0.y, l8, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__normalize_2f32",
+ ,2,1},
+ { "__normalize_2f32",
"mdef(338)_out(1)_in(1)\n"
"mov r0, in0\n"
"dp2_ieee r2.x___, r0.xyxx, r0.xyxx\n"
@@ -14953,10 +14277,8 @@
"mov r0.__zw, l13\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__normalize_4f32",
+ ,1,1},
+ { "__normalize_4f32",
"mdef(339)_out(1)_in(1)\n"
"mov r0, in0\n"
"dp2_ieee r2.x___, r0.xyxx, r0.xyxx\n"
@@ -14988,10 +14310,8 @@
"cmov_logical r0, r2.x, l19, r0\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__normalize_f32",
+ ,1,1},
+ { "__normalize_f32",
"mdef(340)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r2.x___, r0.x_abs\n"
@@ -15022,10 +14342,8 @@
"mov r0._yzw, l6\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__pown_f32i32",
+ ,1,1},
+ { "__pown_f32i32",
"mdef(341)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -15658,10 +14976,8 @@
"cmov_logical r0.x___, r0.y, l212, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__powr_f32",
+ ,2,1},
+ { "__powr_f32",
"mdef(342)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -16196,10 +15512,8 @@
"cmov_logical r0.x___, r0.y, l187, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__pow_f32",
+ ,2,1},
+ { "__pow_f32",
"mdef(343)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -16808,10 +16122,8 @@
"cmov_logical r0.x___, r0.y, l205, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__radians_f32",
+ ,2,1},
+ { "__radians_f32",
"mdef(344)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -16819,10 +16131,8 @@
"mul_ieee r0.x___, r0.x, l0\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__reciprocal_f32",
+ ,1,1},
+ { "__reciprocal_f32",
"mdef(345)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r1.x___, r0.x\n"
@@ -16929,10 +16239,8 @@
"cmov_logical r0.x___, r0.x, r0.y, r0.w\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__remainder_f32",
+ ,1,1},
+ { "__remainder_f32",
"mdef(346)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -17663,10 +16971,8 @@
"cmov_logical r0.x___, r0.y, r1.z, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__remquo_2f32f32",
+ ,2,1},
+ { "__remquo_2f32f32",
"mdef(347)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -18410,10 +17716,8 @@
"cmov_logical r0.xy__, r0.w, r1.xyxx, r0.xzxx\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__rint_f32",
+ ,2,1},
+ { "__rint_f32",
"mdef(348)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -18429,10 +17733,8 @@
"cmov_logical r0.x___, r0.y, r0.x, r0.z\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__rootn_f32i32",
+ ,1,1},
+ { "__rootn_f32i32",
"mdef(349)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -19345,10 +18647,8 @@
"cmov_logical r0.x___, r0.y, l264, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__round_f32",
+ ,2,1},
+ { "__round_f32",
"mdef(350)_out(1)_in(1)\n"
"mov r0, in0\n"
"frc r0._y__, r0.x_abs\n"
@@ -19377,10 +18677,8 @@
"ior r0.x___, r0.w, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__rsqrt_f32",
+ ,1,1},
+ { "__rsqrt_f32",
"mdef(351)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -19511,10 +18809,8 @@
"endif\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__sabs_diff_i16",
+ ,1,1},
+ { "__sabs_diff_i16",
"mdef(352)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -19527,10 +18823,8 @@
"and r0.x___, r0.w, l1\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__sabs_diff_i32",
+ ,2,1},
+ { "__sabs_diff_i32",
"mdef(353)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -19541,10 +18835,8 @@
"iadd r0.x___, r1.x, r0.w_neg(xyzw)\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__sabs_diff_i8",
+ ,2,1},
+ { "__sabs_diff_i8",
"mdef(354)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -19557,37 +18849,29 @@
"and r0.x___, r0.w, l0\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__sabs_i16",
+ ,2,1},
+ { "__sabs_i16",
"mdef(355)_out(1)_in(1)\n"
"mov r0, in0\n"
"imax r0.x___, r0.x_neg(xyzw), r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__sabs_i32",
+ ,1,1},
+ { "__sabs_i32",
"mdef(356)_out(1)_in(1)\n"
"mov r0, in0\n"
"imax r0.x___, r0.x_neg(xyzw), r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__sabs_i8",
+ ,1,1},
+ { "__sabs_i8",
"mdef(357)_out(1)_in(1)\n"
"mov r0, in0\n"
"imax r0.x___, r0.x_neg(xyzw), r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__sadd_sat_i16",
+ ,1,1},
+ { "__sadd_sat_i16",
"mdef(358)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -19602,10 +18886,8 @@
"imin r0.x___, r0.w, l4\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__sadd_sat_i8",
+ ,2,1},
+ { "__sadd_sat_i8",
"mdef(359)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -19621,10 +18903,8 @@
"mov r0.x___, r1.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__sadd_sat_u32",
+ ,2,1},
+ { "__sadd_sat_u32",
"mdef(360)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -19649,10 +18929,8 @@
"cmov_logical r0.x___, r0.w, l9, r1.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__sall_i16",
+ ,2,1},
+ { "__sall_i16",
"mdef(361)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -19666,10 +18944,8 @@
"cmov_logical r0.x___, r0.z, l4, l5\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__sall_i32",
+ ,1,1},
+ { "__sall_i32",
"mdef(362)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -19683,10 +18959,8 @@
"cmov_logical r0.x___, r0.x, l7, l8\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__sall_i8",
+ ,1,1},
+ { "__sall_i8",
"mdef(363)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -19700,10 +18974,8 @@
"cmov_logical r0.x___, r0.z, l1, l2\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__sany_i16",
+ ,1,1},
+ { "__sany_i16",
"mdef(364)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -19717,10 +18989,8 @@
"cmov_logical r0.x___, r0.z, l4, l5\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__sany_i32",
+ ,1,1},
+ { "__sany_i32",
"mdef(365)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -19734,10 +19004,8 @@
"cmov_logical r0.x___, r0.x, l7, l8\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__sany_i8",
+ ,1,1},
+ { "__sany_i8",
"mdef(366)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -19750,10 +19018,8 @@
"cmov_logical r0.x___, r0.z, l1, l2\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__sclz_i16",
+ ,1,1},
+ { "__sclz_i16",
"mdef(367)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -19786,10 +19052,8 @@
"cmov_logical r0.x___, r0.z, r0.w, l18\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__sclz_i32",
+ ,1,1},
+ { "__sclz_i32",
"mdef(368)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -19857,10 +19121,8 @@
"cmov_logical r0.x___, r1.x, r0.w, r0.z\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__sclz_i8",
+ ,1,1},
+ { "__sclz_i8",
"mdef(369)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -19896,10 +19158,8 @@
"iadd r0.x___, r0.z, l9\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__sdiv_i16",
+ ,1,1},
+ { "__sdiv_i16",
"mdef(370)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -19931,10 +19191,8 @@
"mov r0.x___, r0.z\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__sdiv_i32",
+ ,2,1},
+ { "__sdiv_i32",
"mdef(371)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -19949,10 +19207,8 @@
"ixor r0.x, r0.x, r1.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__sdiv_i64",
+ ,2,1},
+ { "__sdiv_i64",
"mdef(372)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -21164,10 +20420,8 @@
"cmov_logical r0.xy__, r1.x, r0.zwzz, r0.xyxx\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__sdiv_i8",
+ ,2,1},
+ { "__sdiv_i8",
"mdef(373)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -21199,10 +20453,8 @@
"mov r0.x___, r0.z\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__shadd_i16",
+ ,2,1},
+ { "__shadd_i16",
"mdef(374)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -21214,10 +20466,8 @@
"ishr r0.x___, r0.w, l2\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__shadd_i32",
+ ,2,1},
+ { "__shadd_i32",
"mdef(375)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -21234,10 +20484,8 @@
"iadd r0.x___, r1.x, r0.w\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__shadd_i8",
+ ,2,1},
+ { "__shadd_i8",
"mdef(376)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -21250,10 +20498,8 @@
"mov r0.x___, r0.w\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__shl_apple_i64",
+ ,2,1},
+ { "__shl_apple_i64",
"mdef(377)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -21270,10 +20516,8 @@
"cmov_logical r0._y__, r3.x, r5.x, r9.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__shl_apple_v2i64",
+ ,2,1},
+ { "__shl_apple_v2i64",
"mdef(378)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -21290,10 +20534,8 @@
"cmov_logical r0._y_w, r3.0x0z, r5.0x0z, r9.0x0z\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__shl_i64",
+ ,2,1},
+ { "__shl_i64",
"mdef(379)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -21310,10 +20552,8 @@
"cmov_logical r0._y__, r3.x, r5.x, r9.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__shl_v2i64",
+ ,2,1},
+ { "__shl_v2i64",
"mdef(380)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -21330,10 +20570,8 @@
"cmov_logical r0._y_w, r3.0x0z, r5.0x0z, r9.0x0z\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__shr_apple_i64",
+ ,2,1},
+ { "__shr_apple_i64",
"mdef(381)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -21350,10 +20588,8 @@
"cmov_logical r0._y__, r3.x, l0.z, r5.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__shr_apple_v2i64",
+ ,2,1},
+ { "__shr_apple_v2i64",
"mdef(382)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -21370,10 +20606,8 @@
"cmov_logical r0._y_w, r3.0x0z, l0.z, r5.0x0z\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__shr_i64",
+ ,2,1},
+ { "__shr_i64",
"mdef(383)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -21390,10 +20624,8 @@
"cmov_logical r0._y__, r3.x, l0.z, r5.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__shr_v2i64",
+ ,2,1},
+ { "__shr_v2i64",
"mdef(384)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -21410,10 +20642,8 @@
"cmov_logical r0._y_w, r3.0x0z, l0.z, r5.0x0z\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__sign_f32",
+ ,2,1},
+ { "__sign_f32",
"mdef(385)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -21442,10 +20672,8 @@
"cmov_logical r0.x___, r0.z, l6, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__sincos_2f32f32",
+ ,1,1},
+ { "__sincos_2f32f32",
"mdef(386)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r0, r0.yxzw\n"
@@ -22503,10 +21731,8 @@
"cmov_logical r0.xy__, r1.y, l245, r0.yxyy\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__sinh_f32",
+ ,1,1},
+ { "__sinh_f32",
"mdef(387)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -22694,10 +21920,8 @@
"cmov_logical r0.x___, r0.x, r0.y_neg(xyzw), r0.y\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__sinpi_f32",
+ ,1,1},
+ { "__sinpi_f32",
"mdef(388)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -22832,10 +22056,8 @@
"cmov_logical r0.x___, r0.z, r0.x, r0.y\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__sin_f32",
+ ,1,1},
+ { "__sin_f32",
"mdef(389)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r0._y__, r0.x_abs\n"
@@ -23891,10 +23113,8 @@
"cmov_logical r0.x___, r0.z, r0.x, r0.y\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__smad24_i32",
+ ,1,1},
+ { "__smad24_i32",
"mdef(390)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -23911,10 +23131,8 @@
"imad r0.x___, r1.x, r1.y, r0.z\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__smad_hi_i16",
+ ,3,1},
+ { "__smad_hi_i16",
"mdef(391)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -23936,10 +23154,8 @@
"cmov_logical r0.x___, r1.y, r1.z, r1.x\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__smad_hi_i32",
+ ,3,1},
+ { "__smad_hi_i32",
"mdef(392)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -23997,10 +23213,8 @@
"iadd r0.x___, r1.x, r0.z\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__smad_hi_i8",
+ ,3,1},
+ { "__smad_hi_i8",
"mdef(393)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -24022,10 +23236,8 @@
"cmov_logical r0.x___, r1.y, r1.z, r1.x\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__smad_sat_i16",
+ ,3,1},
+ { "__smad_sat_i16",
"mdef(394)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -24043,10 +23255,8 @@
"mov r0.x___, r0.w\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__smad_sat_i32",
+ ,3,1},
+ { "__smad_sat_i32",
"mdef(395)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -24075,10 +23285,8 @@
"mov r0.x___, r0.w\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__smad_sat_i8",
+ ,3,1},
+ { "__smad_sat_i8",
"mdef(396)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -24096,10 +23304,8 @@
"mov r0.x___, r0.w\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__smax_i16",
+ ,3,1},
+ { "__smax_i16",
"mdef(397)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -24108,10 +23314,8 @@
"imax r0.x___, r0.y, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__smax_i32",
+ ,2,1},
+ { "__smax_i32",
"mdef(398)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -24120,10 +23324,8 @@
"imax r0.x___, r0.y, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__smax_i8",
+ ,2,1},
+ { "__smax_i8",
"mdef(399)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -24132,10 +23334,8 @@
"imax r0.x___, r0.y, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__smin_i16",
+ ,2,1},
+ { "__smin_i16",
"mdef(400)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -24144,10 +23344,8 @@
"imin r0.x___, r0.y, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__smin_i32",
+ ,2,1},
+ { "__smin_i32",
"mdef(401)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -24156,10 +23354,8 @@
"imin r0.x___, r0.y, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__smin_i8",
+ ,2,1},
+ { "__smin_i8",
"mdef(402)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -24168,10 +23364,8 @@
"imin r0.x___, r0.y, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__smod_i16",
+ ,2,1},
+ { "__smod_i16",
"mdef(403)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -24205,10 +23399,8 @@
"mov r0.x___, r0.z\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__smod_i32",
+ ,2,1},
+ { "__smod_i32",
"mdef(404)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -24224,10 +23416,8 @@
"ixor r0.x, r0.x, r1.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__smod_i64",
+ ,2,1},
+ { "__smod_i64",
"mdef(405)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -25347,10 +24537,8 @@
"cmov_logical r0.xy__, r1.x, r0.zwzz, r0.xyxx\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__smod_i8",
+ ,2,1},
+ { "__smod_i8",
"mdef(406)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -25384,10 +24572,8 @@
"mov r0.x___, r0.z\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__smoothstep_f32",
+ ,2,1},
+ { "__smoothstep_f32",
"mdef(407)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -25418,10 +24604,8 @@
"cmov_logical r0.x___, r0.z, l4, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__smul24_i32",
+ ,3,1},
+ { "__smul24_i32",
"mdef(408)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -25436,10 +24620,8 @@
"imul r0.x___, r1.x, r1.y\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__smul_hi_i16",
+ ,2,1},
+ { "__smul_hi_i16",
"mdef(409)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -25451,10 +24633,8 @@
"ishr r0.x___, r0.w, l2\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__smul_hi_i32",
+ ,2,1},
+ { "__smul_hi_i32",
"mdef(410)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -25506,10 +24686,8 @@
"cmov_logical r0.x___, r0.w, r1.x, r1.y\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__smul_hi_i8",
+ ,2,1},
+ { "__smul_hi_i8",
"mdef(411)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -25522,10 +24700,8 @@
"mov r0.x___, r0.w\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__sqrt_f32",
+ ,2,1},
+ { "__sqrt_f32",
"mdef(412)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -25658,10 +24834,8 @@
"endif\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__sqrt_f64",
+ ,1,1},
+ { "__sqrt_f64",
"mdef(413)_out(1)_in(1)\n"
"mov r0, in0\n"
"dcl_literal l1, 0x00000001, 0x3ff00000, 0x000fffff, 0x3ff80000\n"
@@ -25695,10 +24869,8 @@
"cmov_logical r0.xy, r10.ww, r0.xy, r1.xy\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__sqrt_f64_7XX",
+ ,1,1},
+ { "__sqrt_f64_7XX",
"mdef(414)_out(1)_in(1)\n"
"mov r0, in0\n"
"dcl_literal l1, 0x00000001, 0x3ff00000, 0x40000000, 0x3fe00000\n"
@@ -25739,10 +24911,8 @@
"cmov_logical r0.xy, r10.ww, r0.xy, r20.xy\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__sra_apple_i64",
+ ,1,1},
+ { "__sra_apple_i64",
"mdef(415)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -25760,10 +24930,8 @@
"cmov_logical r0._y__, r3.x, r6.x, r5.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__sra_apple_v2i64",
+ ,2,1},
+ { "__sra_apple_v2i64",
"mdef(416)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -25781,10 +24949,8 @@
"cmov_logical r0._y_w, r3.0x0z, r6.0x0z, r5.0x0z\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__sra_i64",
+ ,2,1},
+ { "__sra_i64",
"mdef(417)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -25802,10 +24968,8 @@
"cmov_logical r0._y__, r3.x, r6.x, r5.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__sra_v2i64",
+ ,2,1},
+ { "__sra_v2i64",
"mdef(418)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -25823,10 +24987,8 @@
"cmov_logical r0._y_w, r3.0x0z, r6.0x0z, r5.0x0z\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__srhadd_i16",
+ ,2,1},
+ { "__srhadd_i16",
"mdef(419)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -25841,10 +25003,8 @@
"ishr r0.x___, r0.w, l5\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__srhadd_i32",
+ ,2,1},
+ { "__srhadd_i32",
"mdef(420)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -25861,10 +25021,8 @@
"iadd r0.x___, r1.x, r0.w\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__srhadd_i8",
+ ,2,1},
+ { "__srhadd_i8",
"mdef(421)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -25880,10 +25038,8 @@
"mov r0.x___, r0.w\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__srotate_i16",
+ ,2,1},
+ { "__srotate_i16",
"mdef(422)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -25909,10 +25065,8 @@
"ishr r0.x___, r0.w, l12\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__srotate_i32",
+ ,2,1},
+ { "__srotate_i32",
"mdef(423)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -25929,10 +25083,8 @@
"ior r0.x___, r1.x, r0.w\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__srotate_i8",
+ ,2,1},
+ { "__srotate_i8",
"mdef(424)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -25958,10 +25110,8 @@
"ishr r0.x___, r0.w, l4\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__ssub_sat_i16",
+ ,2,1},
+ { "__ssub_sat_i16",
"mdef(425)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -25976,10 +25126,8 @@
"imin r0.x___, r0.w, l4\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__ssub_sat_i32",
+ ,2,1},
+ { "__ssub_sat_i32",
"mdef(426)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -26004,10 +25152,8 @@
"cmov_logical r0.x___, r0.w, l9, r1.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__ssub_sat_i8",
+ ,2,1},
+ { "__ssub_sat_i8",
"mdef(427)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -26022,10 +25168,8 @@
"imin r0.x___, r0.w, l1\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__step_f32",
+ ,2,1},
+ { "__step_f32",
"mdef(428)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -26037,226 +25181,176 @@
"cmov_logical r0.x___, r0.z, l0, l1\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__store_128bit_global",
+ ,2,1},
+ { "__store_128bit_global",
"mdef(429)_out(0)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"mov g[r0.x], r1\n"
"mend\n"
- ,2,0
- },
- {
- "__store_128bit_local",
+ ,2,0},
+ { "__store_128bit_local",
"mdef(430)_out(0)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"lds_store_vec_id(0) mem, r0.x, r0.x, r1\n"
"mend\n"
- ,2,0
- },
- {
- "__store_128bit_private",
+ ,2,0},
+ { "__store_128bit_private",
"mdef(431)_out(0)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"mov x0[r0.x], r1\n"
"mend\n"
- ,2,0
- },
- {
- "__store_128bit_uav",
+ ,2,0},
+ { "__store_128bit_uav",
"mdef(432)_out(0)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"uav_raw_store_id(0) mem0, r0.x, r1\n"
"mend\n"
- ,2,0
- },
- {
- "__store_32bit_local",
+ ,2,0},
+ { "__store_32bit_local",
"mdef(433)_out(0)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"lds_store_id(0) mem, r0.x, r0.x, r1\n"
"mend\n"
- ,2,0
- },
- {
- "__store_32bit_uav",
+ ,2,0},
+ { "__store_32bit_uav",
"mdef(434)_out(0)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"uav_raw_store_id(0) mem0.x, r0.x, r1\n"
"mend\n"
- ,2,0
- },
- {
- "__store_64bit_local",
+ ,2,0},
+ { "__store_64bit_local",
"mdef(435)_out(0)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"lds_store_vec_id(0) mem.xy__, r0.x, r0.x, r1\n"
"mend\n"
- ,2,0
- },
- {
- "__store_64bit_uav",
+ ,2,0},
+ { "__store_64bit_uav",
"mdef(436)_out(0)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"uav_raw_store_id(0) mem0.xy, r0.x, r1\n"
"mend\n"
- ,2,0
- },
- {
- "__store_96bit_global",
+ ,2,0},
+ { "__store_96bit_global",
"mdef(437)_out(0)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"mov g[r0.x].xyz_, r1\n"
"mend\n"
- ,2,0
- },
- {
- "__store_96bit_local",
+ ,2,0},
+ { "__store_96bit_local",
"mdef(438)_out(0)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"lds_store_vec_id(0) mem.xyz_, r0.x, r0.x, r1\n"
"mend\n"
- ,2,0
- },
- {
- "__store_96bit_private",
+ ,2,0},
+ { "__store_96bit_private",
"mdef(439)_out(0)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"mov x0[r0.x].xyz_, r1\n"
"mend\n"
- ,2,0
- },
- {
- "__store_96bit_uav",
+ ,2,0},
+ { "__store_96bit_uav",
"mdef(440)_out(0)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"uav_raw_store_id(0) mem0.xyz, r0.x, r1\n"
"mend\n"
- ,2,0
- },
- {
- "__store_hi_64bit_global",
+ ,2,0},
+ { "__store_hi_64bit_global",
"mdef(441)_out(0)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"mov g[r0.x].__zw, r1.00xy\n"
"mend\n"
- ,2,0
- },
- {
- "__store_hi_64bit_private",
+ ,2,0},
+ { "__store_hi_64bit_private",
"mdef(442)_out(0)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"mov x0[r0.x].__zw, r1.00xy\n"
"mend\n"
- ,2,0
- },
- {
- "__store_lo_64bit_global",
+ ,2,0},
+ { "__store_lo_64bit_global",
"mdef(443)_out(0)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"mov g[r0.x].xy__, r1.xy\n"
"mend\n"
- ,2,0
- },
- {
- "__store_lo_64bit_private",
+ ,2,0},
+ { "__store_lo_64bit_private",
"mdef(444)_out(0)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"mov x0[r0.x].xy__, r1.xy\n"
"mend\n"
- ,2,0
- },
- {
- "__store_w_32bit_global",
+ ,2,0},
+ { "__store_w_32bit_global",
"mdef(445)_out(0)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"mov g[r0.x].w, r1.x\n"
"mend\n"
- ,2,0
- },
- {
- "__store_w_32bit_private",
+ ,2,0},
+ { "__store_w_32bit_private",
"mdef(446)_out(0)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"mov x0[r0.x].w, r1.x\n"
"mend\n"
- ,2,0
- },
- {
- "__store_x_32bit_global",
+ ,2,0},
+ { "__store_x_32bit_global",
"mdef(447)_out(0)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"mov g[r0.x].x, r1.x\n"
"mend\n"
- ,2,0
- },
- {
- "__store_x_32bit_private",
+ ,2,0},
+ { "__store_x_32bit_private",
"mdef(448)_out(0)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"mov x0[r0.x].x, r1.x\n"
"mend\n"
- ,2,0
- },
- {
- "__store_y_32bit_global",
+ ,2,0},
+ { "__store_y_32bit_global",
"mdef(449)_out(0)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"mov g[r0.x].y, r1.x\n"
"mend\n"
- ,2,0
- },
- {
- "__store_y_32bit_private",
+ ,2,0},
+ { "__store_y_32bit_private",
"mdef(450)_out(0)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"mov x0[r0.x].y, r1.x\n"
"mend\n"
- ,2,0
- },
- {
- "__store_z_32bit_global",
+ ,2,0},
+ { "__store_z_32bit_global",
"mdef(451)_out(0)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"mov g[r0.x].z, r1.x\n"
"mend\n"
- ,2,0
- },
- {
- "__store_z_32bit_private",
+ ,2,0},
+ { "__store_z_32bit_private",
"mdef(452)_out(0)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"mov x0[r0.x].z, r1.x\n"
"mend\n"
- ,2,0
- },
- {
- "__tanh_f32",
+ ,2,0},
+ { "__tanh_f32",
"mdef(453)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r0._y__, r0.x_abs\n"
@@ -26587,10 +25681,8 @@
"cmov_logical r0.x___, r0.y, r0.z, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__tanpi_f32",
+ ,1,1},
+ { "__tanpi_f32",
"mdef(454)_out(1)_in(1)\n"
"mov r0, in0\n"
"add r0._y__, r0.x_abs, r0.x_abs\n"
@@ -26687,10 +25779,8 @@
"cmov_logical r0.x___, r1.x, l33, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__tan_f32",
+ ,1,1},
+ { "__tan_f32",
"mdef(455)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r0._y__, r0.x_abs\n"
@@ -27713,10 +26803,8 @@
"cmov_logical r0.x___, r0.z, r0.x, r0.y\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__tgamma_f32",
+ ,1,1},
+ { "__tgamma_f32",
"mdef(456)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -29202,19 +28290,15 @@
"cmov_logical r0.x___, r0.x, l379, r0.y\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__trunc_f32",
+ ,1,1},
+ { "__trunc_f32",
"mdef(457)_out(1)_in(1)\n"
"mov r0, in0\n"
"round_z r0.x___, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__uabs_diff_u16",
+ ,1,1},
+ { "__uabs_diff_u16",
"mdef(458)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -29227,10 +28311,8 @@
"and r0.x___, r0.w, l1\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__uabs_diff_u32",
+ ,2,1},
+ { "__uabs_diff_u32",
"mdef(459)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -29241,10 +28323,8 @@
"iadd r0.x___, r1.x, r0.w_neg(xyzw)\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__uabs_diff_u8",
+ ,2,1},
+ { "__uabs_diff_u8",
"mdef(460)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -29257,37 +28337,29 @@
"and r0.x___, r0.w, l0\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__uabs_u16",
+ ,2,1},
+ { "__uabs_u16",
"mdef(461)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r0, r0\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__uabs_u32",
+ ,1,1},
+ { "__uabs_u32",
"mdef(462)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r0, r0\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__uabs_u8",
+ ,1,1},
+ { "__uabs_u8",
"mdef(463)_out(1)_in(1)\n"
"mov r0, in0\n"
"mov r0, r0\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__uadd_sat_i32",
+ ,1,1},
+ { "__uadd_sat_i32",
"mdef(464)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -29300,10 +28372,8 @@
"cmov_logical r0.x___, r1.x, l10, r0.w\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__uadd_sat_u16",
+ ,2,1},
+ { "__uadd_sat_u16",
"mdef(465)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -29315,10 +28385,8 @@
"umin r0.x___, r0.w, l5\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__uadd_sat_u8",
+ ,2,1},
+ { "__uadd_sat_u8",
"mdef(466)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -29330,10 +28398,8 @@
"umin r0.x___, r1.x, l2\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__uall_u16",
+ ,2,1},
+ { "__uall_u16",
"mdef(467)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -29347,10 +28413,8 @@
"cmov_logical r0.x___, r0.z, l4, l5\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__uall_u32",
+ ,1,1},
+ { "__uall_u32",
"mdef(468)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -29364,10 +28428,8 @@
"cmov_logical r0.x___, r0.x, l7, l8\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__uall_u8",
+ ,1,1},
+ { "__uall_u8",
"mdef(469)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -29381,10 +28443,8 @@
"cmov_logical r0.x___, r0.z, l1, l2\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__uany_i16",
+ ,1,1},
+ { "__uany_i16",
"mdef(470)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -29398,10 +28458,8 @@
"cmov_logical r0.x___, r0.z, l4, l5\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__uany_i32",
+ ,1,1},
+ { "__uany_i32",
"mdef(471)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -29415,10 +28473,8 @@
"cmov_logical r0.x___, r0.x, l7, l8\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__uany_u8",
+ ,1,1},
+ { "__uany_u8",
"mdef(472)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -29431,10 +28487,8 @@
"cmov_logical r0.x___, r0.z, l1, l2\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__uclz_u16",
+ ,1,1},
+ { "__uclz_u16",
"mdef(473)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -29467,10 +28521,8 @@
"cmov_logical r0.x___, r0.z, r0.w, l18\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__uclz_u32",
+ ,1,1},
+ { "__uclz_u32",
"mdef(474)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -29538,10 +28590,8 @@
"cmov_logical r0.x___, r1.x, r0.w, r0.z\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__uclz_u8",
+ ,1,1},
+ { "__uclz_u8",
"mdef(475)_out(1)_in(1)\n"
"mov r0, in0\n"
"\n"
@@ -29577,10 +28627,8 @@
"iadd r0.x___, r0.z, l9\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__udiv_i16",
+ ,1,1},
+ { "__udiv_i16",
"mdef(476)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -29597,20 +28645,16 @@
"mov r0.x___, r0.z\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__udiv_i32",
+ ,2,1},
+ { "__udiv_i32",
"mdef(477)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
"udiv r0.x, r0.x, r1.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__udiv_i64",
+ ,2,1},
+ { "__udiv_i64",
"mdef(478)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -30809,10 +29853,8 @@
"cmov_logical r0.xy__, r1.w, l340, r0.xyxx\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__udiv_i8",
+ ,2,1},
+ { "__udiv_i8",
"mdef(479)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -30829,10 +29871,8 @@
"mov r0.x___, r0.z\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__uhadd_u16",
+ ,2,1},
+ { "__uhadd_u16",
"mdef(480)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -30844,10 +29884,8 @@
"ushr r0.x___, r0.w, l3\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__uhadd_u32",
+ ,2,1},
+ { "__uhadd_u32",
"mdef(481)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -30864,10 +29902,8 @@
"iadd r0.x___, r1.x, r0.w\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__uhadd_u8",
+ ,2,1},
+ { "__uhadd_u8",
"mdef(482)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -30879,10 +29915,8 @@
"ushr r0.x___, r1.x, l1\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__ultof_f32",
+ ,2,1},
+ { "__ultof_f32",
"mdef(483)_out(1)_in(1)\n"
"mov r0, in0\n"
"dcl_literal l1, 0x0000000E, 0x0000000E, 0x0000000E, 0x0000000E\n"
@@ -31019,10 +30053,8 @@
"cmov_logical r0.x___, r0.x, l56, r0.w\n"
"mov out0, r0\n"
"mend\n"
- ,1,1
- },
- {
- "__umad24_u32",
+ ,1,1},
+ { "__umad24_u32",
"mdef(484)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -31037,10 +30069,8 @@
"iadd r0.x___, r1.x, r0.z\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__umad_hi_u16",
+ ,3,1},
+ { "__umad_hi_u16",
"mdef(485)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -31058,10 +30088,8 @@
"and r0.x___, r1.x, l9\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__umad_hi_u32",
+ ,3,1},
+ { "__umad_hi_u32",
"mdef(486)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -31096,10 +30124,8 @@
"iadd r0.x___, r1.x, r0.z\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__umad_hi_u8",
+ ,3,1},
+ { "__umad_hi_u8",
"mdef(487)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -31117,10 +30143,8 @@
"and r0.x___, r1.x, l4\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__umad_sat_u16",
+ ,3,1},
+ { "__umad_sat_u16",
"mdef(488)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -31136,10 +30160,8 @@
"mov r0.x___, r0.w\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__umad_sat_u32",
+ ,3,1},
+ { "__umad_sat_u32",
"mdef(489)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -31156,10 +30178,8 @@
"mov r0.x___, r0.w\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__umad_sat_u8",
+ ,3,1},
+ { "__umad_sat_u8",
"mdef(490)_out(1)_in(3)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -31175,10 +30195,8 @@
"mov r0.x___, r0.w\n"
"mov out0, r0\n"
"mend\n"
- ,3,1
- },
- {
- "__umax_u16",
+ ,3,1},
+ { "__umax_u16",
"mdef(491)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -31187,10 +30205,8 @@
"umax r0.x___, r0.y, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__umax_u32",
+ ,2,1},
+ { "__umax_u32",
"mdef(492)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -31199,10 +30215,8 @@
"umax r0.x___, r0.y, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__umax_u8",
+ ,2,1},
+ { "__umax_u8",
"mdef(493)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -31211,10 +30225,8 @@
"umax r0.x___, r0.y, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__umin_u16",
+ ,2,1},
+ { "__umin_u16",
"mdef(494)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -31223,10 +30235,8 @@
"umin r0.x___, r0.y, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__umin_u32",
+ ,2,1},
+ { "__umin_u32",
"mdef(495)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -31235,10 +30245,8 @@
"umin r0.x___, r0.y, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__umin_u8",
+ ,2,1},
+ { "__umin_u8",
"mdef(496)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -31247,10 +30255,8 @@
"umin r0.x___, r0.y, r0.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__umod_i16",
+ ,2,1},
+ { "__umod_i16",
"mdef(497)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -31269,10 +30275,8 @@
"mov r0.x___, r0.z\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__umod_i32",
+ ,2,1},
+ { "__umod_i32",
"mdef(498)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -31281,10 +30285,8 @@
"iadd r0.x, r0.x, r2.x_neg(xyzw)\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__umod_i64",
+ ,2,1},
+ { "__umod_i64",
"mdef(499)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -32387,10 +31389,8 @@
"cmov_logical r0.xy__, r1.w, l307, r0.xyxx\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__umod_i8",
+ ,2,1},
+ { "__umod_i8",
"mdef(500)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -32409,10 +31409,8 @@
"mov r0.x___, r0.z\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__umul24_u32",
+ ,2,1},
+ { "__umul24_u32",
"mdef(501)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -32424,10 +31422,8 @@
"umul r1.x___, r1.x, r1.y\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__umul_hi_u16",
+ ,2,1},
+ { "__umul_hi_u16",
"mdef(502)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -32440,10 +31436,8 @@
"ushr r0.x___, r0.w, l3\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__umul_hi_u32",
+ ,2,1},
+ { "__umul_hi_u32",
"mdef(503)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -32475,10 +31469,8 @@
"iadd r0.x___, r0.w, r1.x\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__umul_hi_u8",
+ ,2,1},
+ { "__umul_hi_u8",
"mdef(504)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -32490,10 +31482,8 @@
"ushr r0.x___, r0.w, l1\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__urhadd_u16",
+ ,2,1},
+ { "__urhadd_u16",
"mdef(505)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -32508,10 +31498,8 @@
"ushr r0.x___, r0.w, l7\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__urhadd_u32",
+ ,2,1},
+ { "__urhadd_u32",
"mdef(506)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -32528,10 +31516,8 @@
"iadd r0.x___, r1.x, r0.w\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__urhadd_u8",
+ ,2,1},
+ { "__urhadd_u8",
"mdef(507)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -32546,10 +31532,8 @@
"ushr r0.x___, r0.w, l3\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__urotate_u16",
+ ,2,1},
+ { "__urotate_u16",
"mdef(508)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -32569,10 +31553,8 @@
"and r0.x___, r0.w, l15\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__urotate_u32",
+ ,2,1},
+ { "__urotate_u32",
"mdef(509)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -32589,10 +31571,8 @@
"ior r0.x___, r1.x, r0.w\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__urotate_u8",
+ ,2,1},
+ { "__urotate_u8",
"mdef(510)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -32612,10 +31592,8 @@
"and r0.x___, r0.w, l7\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__usub_sat_u16",
+ ,2,1},
+ { "__usub_sat_u16",
"mdef(511)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -32627,10 +31605,8 @@
"umin r0.x___, r0.w, l5\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__usub_sat_u32",
+ ,2,1},
+ { "__usub_sat_u32",
"mdef(512)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -32643,10 +31619,8 @@
"cmov_logical r0.__z_, r1.x, l10, r0.w\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
- {
- "__usub_sat_u8",
+ ,2,1},
+ { "__usub_sat_u8",
"mdef(513)_out(1)_in(2)\n"
"mov r0, in0\n"
"mov r1, in1\n"
@@ -32658,8 +31632,7 @@
"umin r0.x___, r0.w, l2\n"
"mov out0, r0\n"
"mend\n"
- ,2,1
- },
+ ,2,1},
{ "", NULL }
};
#endif // _macrodb_gen_HPP_
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