[llvm-branch-commits] [llvm-branch] r167125 - /llvm/branches/R600/lib/Target/AMDGPU/SIInstrInfo.cpp

[Tom Stellard]

Author: tstellar
Date: Wed Oct 31 10:26:12 2012
New Revision: 167125

URL: http://llvm.org/viewvc/llvm-project?rev=167125&view=rev
Log:
SI: Handle more cases in copyPhysReg callback

Also add assertions failing in unhandled cases.

Patch by: Michel Dänzer

Reviewed-by: Tom Stellard <thomas.stellar at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer at amd.com>

Modified:
    llvm/branches/R600/lib/Target/AMDGPU/SIInstrInfo.cpp

Modified: llvm/branches/R600/lib/Target/AMDGPU/SIInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/AMDGPU/SIInstrInfo.cpp?rev=167125&r1=167124&r2=167125&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/AMDGPU/SIInstrInfo.cpp (original)
+++ llvm/branches/R600/lib/Target/AMDGPU/SIInstrInfo.cpp Wed Oct 31 10:26:12 2012
@@ -38,14 +38,26 @@
                            unsigned DestReg, unsigned SrcReg,
                            bool KillSrc) const
 {
-
   // If we are trying to copy to or from SCC, there is a bug somewhere else in
   // the backend.  While it may be theoretically possible to do this, it should
   // never be necessary.
   assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
 
-  BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
-   .addReg(SrcReg, getKillRegState(KillSrc));
+  if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
+    assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
+    BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
+            .addReg(SrcReg, getKillRegState(KillSrc));
+  } else if (AMDGPU::VReg_32RegClass.contains(DestReg)) {
+    assert(AMDGPU::VReg_32RegClass.contains(SrcReg) ||
+	   AMDGPU::SReg_32RegClass.contains(SrcReg));
+    BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
+            .addReg(SrcReg, getKillRegState(KillSrc));
+  } else {
+    assert(AMDGPU::SReg_32RegClass.contains(DestReg));
+    assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
+    BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
+            .addReg(SrcReg, getKillRegState(KillSrc));
+  }
 }
 
 MachineInstr * SIInstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg,