[llvm-branch-commits] [llvm-branch] r167123 - /llvm/branches/R600/lib/Target/AMDGPU/SIISelLowering.cpp

[Tom Stellard]

Author: tstellar
Date: Wed Oct 31 10:26:10 2012
New Revision: 167123

URL: http://llvm.org/viewvc/llvm-project?rev=167123&view=rev
Log:
SI: Use SReg_64RegClass for i64 register class

Fixes invalid code being generated, trying to copy from VGPRs to SGPRs.

Patch by: Michel Dänzer

Reviewed-by: Tom Stellard <thomas.stellar at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer at amd.com>

Modified:
    llvm/branches/R600/lib/Target/AMDGPU/SIISelLowering.cpp

Modified: llvm/branches/R600/lib/Target/AMDGPU/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/AMDGPU/SIISelLowering.cpp?rev=167123&r1=167122&r2=167123&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/AMDGPU/SIISelLowering.cpp (original)
+++ llvm/branches/R600/lib/Target/AMDGPU/SIISelLowering.cpp Wed Oct 31 10:26:10 2012
@@ -31,7 +31,7 @@
   addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
   addRegisterClass(MVT::f32, &AMDGPU::VReg_32RegClass);
   addRegisterClass(MVT::i32, &AMDGPU::VReg_32RegClass);
-  addRegisterClass(MVT::i64, &AMDGPU::VReg_64RegClass);
+  addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
   addRegisterClass(MVT::i1, &AMDGPU::SCCRegRegClass);
   addRegisterClass(MVT::i1, &AMDGPU::VCCRegRegClass);