[llvm-branch-commits] [llvm-branch] r165525 - in /llvm/branches/R600: lib/Target/AMDGPU/R600Instructions.td test/CodeGen/R600/sdiv.ll

[Tom Stellard]

Author: tstellar
Date: Tue Oct  9 13:49:02 2012
New Revision: 165525

URL: http://llvm.org/viewvc/llvm-project?rev=165525&view=rev
Log:
R600: Add a pattern for:  (selectcc i32, -1, i32, i32, SETGT)

This is now lowered to a CNDGE_INT instruction.

Added:
    llvm/branches/R600/test/CodeGen/R600/sdiv.ll
Modified:
    llvm/branches/R600/lib/Target/AMDGPU/R600Instructions.td

Modified: llvm/branches/R600/lib/Target/AMDGPU/R600Instructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/AMDGPU/R600Instructions.td?rev=165525&r1=165524&r2=165525&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/AMDGPU/R600Instructions.td (original)
+++ llvm/branches/R600/lib/Target/AMDGPU/R600Instructions.td Tue Oct  9 13:49:02 2012
@@ -1377,6 +1377,13 @@
 // ISel Patterns
 //===----------------------------------------------------------------------===//
 
+//CNDGE_INT extra pattern
+def : Pat <
+  (selectcc (i32 R600_Reg32:$src0), -1, (i32 R600_Reg32:$src1),
+                                        (i32 R600_Reg32:$src2), COND_GT),
+  (CNDGE_INT R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2)
+>;
+
 // KIL Patterns
 def KILP : Pat <
   (int_AMDGPU_kilp),

Added: llvm/branches/R600/test/CodeGen/R600/sdiv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/CodeGen/R600/sdiv.ll?rev=165525&view=auto
==============================================================================
--- llvm/branches/R600/test/CodeGen/R600/sdiv.ll (added)
+++ llvm/branches/R600/test/CodeGen/R600/sdiv.ll Tue Oct  9 13:49:02 2012
@@ -0,0 +1,21 @@
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+
+; The code generated by sdiv is long and complex and may frequently change.
+; The goal of this test is to make sure the ISel doesn't fail.
+;
+; This program was previously failing to compile when one of the selectcc
+; opcodes generated by the sdiv lowering was being legalized and optimized to:
+; selectcc Remainder -1, 0, -1, SETGT
+; This was fixed by adding an additional pattern in R600Instructions.td to
+; match this pattern with a CNDGE_INT.
+
+; CHECK: RETURN
+
+define void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
+  %den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
+  %num = load i32 addrspace(1) * %in
+  %den = load i32 addrspace(1) * %den_ptr
+  %result = sdiv i32 %num, %den
+  store i32 %result, i32 addrspace(1)* %out
+  ret void
+}