[llvm-branch-commits] [llvm-branch] r165522 - in /llvm/branches/R600/test/CodeGen/R600: add.v4i32.ll and.v4i32.ll fdiv.v4f32.ll fsub.v4f32.ll setcc.v4i32.ll udiv.v4i32.ll urem.v4i32.ll
Tom Stellard
thomas.stellard at amd.com
Tue Oct 9 11:48:58 PDT 2012
Author: tstellar
Date: Tue Oct 9 13:48:58 2012
New Revision: 165522
URL: http://llvm.org/viewvc/llvm-project?rev=165522&view=rev
Log:
R600: Add tests for a few vector operations
These were supposed to be commited with:
"R600: Handle more vector arithmetic instructions"
Added:
llvm/branches/R600/test/CodeGen/R600/add.v4i32.ll
llvm/branches/R600/test/CodeGen/R600/and.v4i32.ll
llvm/branches/R600/test/CodeGen/R600/fdiv.v4f32.ll
llvm/branches/R600/test/CodeGen/R600/fsub.v4f32.ll
llvm/branches/R600/test/CodeGen/R600/setcc.v4i32.ll
llvm/branches/R600/test/CodeGen/R600/udiv.v4i32.ll
llvm/branches/R600/test/CodeGen/R600/urem.v4i32.ll
Added: llvm/branches/R600/test/CodeGen/R600/add.v4i32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/CodeGen/R600/add.v4i32.ll?rev=165522&view=auto
==============================================================================
--- llvm/branches/R600/test/CodeGen/R600/add.v4i32.ll (added)
+++ llvm/branches/R600/test/CodeGen/R600/add.v4i32.ll Tue Oct 9 13:48:58 2012
@@ -0,0 +1,15 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+
+;CHECK: ADD_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;CHECK: ADD_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;CHECK: ADD_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;CHECK: ADD_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+
+define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
+ %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
+ %a = load <4 x i32> addrspace(1) * %in
+ %b = load <4 x i32> addrspace(1) * %b_ptr
+ %result = add <4 x i32> %a, %b
+ store <4 x i32> %result, <4 x i32> addrspace(1)* %out
+ ret void
+}
Added: llvm/branches/R600/test/CodeGen/R600/and.v4i32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/CodeGen/R600/and.v4i32.ll?rev=165522&view=auto
==============================================================================
--- llvm/branches/R600/test/CodeGen/R600/and.v4i32.ll (added)
+++ llvm/branches/R600/test/CodeGen/R600/and.v4i32.ll Tue Oct 9 13:48:58 2012
@@ -0,0 +1,15 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+
+;CHECK: AND_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;CHECK: AND_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;CHECK: AND_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;CHECK: AND_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+
+define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
+ %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
+ %a = load <4 x i32> addrspace(1) * %in
+ %b = load <4 x i32> addrspace(1) * %b_ptr
+ %result = and <4 x i32> %a, %b
+ store <4 x i32> %result, <4 x i32> addrspace(1)* %out
+ ret void
+}
Added: llvm/branches/R600/test/CodeGen/R600/fdiv.v4f32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/CodeGen/R600/fdiv.v4f32.ll?rev=165522&view=auto
==============================================================================
--- llvm/branches/R600/test/CodeGen/R600/fdiv.v4f32.ll (added)
+++ llvm/branches/R600/test/CodeGen/R600/fdiv.v4f32.ll Tue Oct 9 13:48:58 2012
@@ -0,0 +1,19 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+
+;CHECK: RECIP_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;CHECK: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;CHECK: RECIP_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;CHECK: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;CHECK: RECIP_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;CHECK: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;CHECK: RECIP_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;CHECK: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+
+define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
+ %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
+ %a = load <4 x float> addrspace(1) * %in
+ %b = load <4 x float> addrspace(1) * %b_ptr
+ %result = fdiv <4 x float> %a, %b
+ store <4 x float> %result, <4 x float> addrspace(1)* %out
+ ret void
+}
Added: llvm/branches/R600/test/CodeGen/R600/fsub.v4f32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/CodeGen/R600/fsub.v4f32.ll?rev=165522&view=auto
==============================================================================
--- llvm/branches/R600/test/CodeGen/R600/fsub.v4f32.ll (added)
+++ llvm/branches/R600/test/CodeGen/R600/fsub.v4f32.ll Tue Oct 9 13:48:58 2012
@@ -0,0 +1,15 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+
+;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+
+define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
+ %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
+ %a = load <4 x float> addrspace(1) * %in
+ %b = load <4 x float> addrspace(1) * %b_ptr
+ %result = fsub <4 x float> %a, %b
+ store <4 x float> %result, <4 x float> addrspace(1)* %out
+ ret void
+}
Added: llvm/branches/R600/test/CodeGen/R600/setcc.v4i32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/CodeGen/R600/setcc.v4i32.ll?rev=165522&view=auto
==============================================================================
--- llvm/branches/R600/test/CodeGen/R600/setcc.v4i32.ll (added)
+++ llvm/branches/R600/test/CodeGen/R600/setcc.v4i32.ll Tue Oct 9 13:48:58 2012
@@ -0,0 +1,12 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+;CHECK: SETE_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+
+define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
+ %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
+ %a = load <4 x i32> addrspace(1) * %in
+ %b = load <4 x i32> addrspace(1) * %b_ptr
+ %result = icmp eq <4 x i32> %a, %b
+ %sext = sext <4 x i1> %result to <4 x i32>
+ store <4 x i32> %sext, <4 x i32> addrspace(1)* %out
+ ret void
+}
Added: llvm/branches/R600/test/CodeGen/R600/udiv.v4i32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/CodeGen/R600/udiv.v4i32.ll?rev=165522&view=auto
==============================================================================
--- llvm/branches/R600/test/CodeGen/R600/udiv.v4i32.ll (added)
+++ llvm/branches/R600/test/CodeGen/R600/udiv.v4i32.ll Tue Oct 9 13:48:58 2012
@@ -0,0 +1,15 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+
+;The code generated by udiv is long and complex and may frequently change.
+;The goal of this test is to make sure the ISel doesn't fail when it gets
+;a v4i32 udiv
+;CHECK: RETURN
+
+define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
+ %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
+ %a = load <4 x i32> addrspace(1) * %in
+ %b = load <4 x i32> addrspace(1) * %b_ptr
+ %result = udiv <4 x i32> %a, %b
+ store <4 x i32> %result, <4 x i32> addrspace(1)* %out
+ ret void
+}
Added: llvm/branches/R600/test/CodeGen/R600/urem.v4i32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/CodeGen/R600/urem.v4i32.ll?rev=165522&view=auto
==============================================================================
--- llvm/branches/R600/test/CodeGen/R600/urem.v4i32.ll (added)
+++ llvm/branches/R600/test/CodeGen/R600/urem.v4i32.ll Tue Oct 9 13:48:58 2012
@@ -0,0 +1,15 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+
+;The code generated by urem is long and complex and may frequently change.
+;The goal of this test is to make sure the ISel doesn't fail when it gets
+;a v4i32 urem
+;CHECK: RETURN
+
+define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
+ %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
+ %a = load <4 x i32> addrspace(1) * %in
+ %b = load <4 x i32> addrspace(1) * %b_ptr
+ %result = urem <4 x i32> %a, %b
+ store <4 x i32> %result, <4 x i32> addrspace(1)* %out
+ ret void
+}
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