[llvm-branch-commits] [llvm-branch] r161996 - in /llvm/branches/AMDILBackend: ./ lib/Target/AMDIL/ test/CodeGen/AMDIL/
Victor Oliveira
Victor.Oliveira at amd.com
Wed Aug 15 15:39:43 PDT 2012
Author: victorm
Date: Wed Aug 15 17:39:43 2012
New Revision: 161996
URL: http://llvm.org/viewvc/llvm-project?rev=161996&view=rev
Log:
Tests for AMDIL and minor fixes.
Added:
llvm/branches/AMDILBackend/test/CodeGen/AMDIL/
llvm/branches/AMDILBackend/test/CodeGen/AMDIL/empty_file.ll
llvm/branches/AMDILBackend/test/CodeGen/AMDIL/empty_func.ll
llvm/branches/AMDILBackend/test/CodeGen/AMDIL/empty_kernel.ll
llvm/branches/AMDILBackend/test/CodeGen/AMDIL/exit.ll
llvm/branches/AMDILBackend/test/CodeGen/AMDIL/ld.ll
llvm/branches/AMDILBackend/test/CodeGen/AMDIL/lit.local.cfg
llvm/branches/AMDILBackend/test/CodeGen/AMDIL/mov.ll
llvm/branches/AMDILBackend/test/CodeGen/AMDIL/mul.ll
llvm/branches/AMDILBackend/test/CodeGen/AMDIL/shl.ll
llvm/branches/AMDILBackend/test/CodeGen/AMDIL/shr.ll
llvm/branches/AMDILBackend/test/CodeGen/AMDIL/st.ll
llvm/branches/AMDILBackend/test/CodeGen/AMDIL/sub.ll
llvm/branches/AMDILBackend/test/CodeGen/AMDIL/sub.s
llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_barts.ll
llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_caicos.ll
llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_cayman.ll
llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_cedar.ll
llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_cypress.ll
llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_juniper.ll
llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_redwood.ll
llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_rv710.ll
llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_rv730.ll
llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_rv770.ll
llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_turks.ll
Modified:
llvm/branches/AMDILBackend/CMakeLists.txt
llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSubtarget.cpp
Modified: llvm/branches/AMDILBackend/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/CMakeLists.txt?rev=161996&r1=161995&r2=161996&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/CMakeLists.txt (original)
+++ llvm/branches/AMDILBackend/CMakeLists.txt Wed Aug 15 17:39:43 2012
@@ -128,10 +128,15 @@
set( LLVM_TARGETS_TO_BUILD ${LLVM_ALL_TARGETS} )
endif()
+set(LLVM_TARGETS_TO_BUILD
+ ${LLVM_TARGETS_TO_BUILD}
+ ${LLVM_EXPERIMENTAL_TARGETS_TO_BUILD})
+
set(LLVM_ENUM_TARGETS "")
foreach(c ${LLVM_TARGETS_TO_BUILD})
list(FIND LLVM_ALL_TARGETS ${c} idx)
- if( idx LESS 0 )
+ list(FIND LLVM_EXPERIMENTAL_TARGETS_TO_BUILD ${c} idy)
+ if( idx LESS 0 AND idy LESS 0 )
message(FATAL_ERROR "The target `${c}' does not exist.
It should be one of\n${LLVM_ALL_TARGETS}")
else()
@@ -139,11 +144,6 @@
endif()
endforeach(c)
-set(LLVM_TARGETS_TO_BUILD
- ${LLVM_TARGETS_TO_BUILD}
- ${LLVM_EXPERIMENTAL_TARGETS_TO_BUILD}
- )
-
set(llvm_builded_incs_dir ${LLVM_BINARY_DIR}/include/llvm)
include(AddLLVMDefinitions)
Modified: llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSubtarget.cpp?rev=161996&r1=161995&r2=161996&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSubtarget.cpp (original)
+++ llvm/branches/AMDILBackend/lib/Target/AMDIL/AMDILSubtarget.cpp Wed Aug 15 17:39:43 2012
@@ -30,12 +30,10 @@
#define GET_SUBTARGETINFO_TARGET_DESC
#include "AMDILGenSubtarget.inc"
-AMDILSubtarget::AMDILSubtarget(llvm::StringRef TT, llvm::StringRef CPU, llvm::StringRef FS) : AMDILGenSubtargetInfo( TT, CPU, FS )
+AMDILSubtarget::AMDILSubtarget(llvm::StringRef TT, llvm::StringRef GPU, llvm::StringRef FS) : AMDILGenSubtargetInfo( TT, GPU, FS )
{
memset(CapsOverride, 0, sizeof(*CapsOverride)
* AMDILDeviceInfo::MaxNumberCapabilities);
- // Default card
- std::string GPU = "rv770";
mIs64bit = false;
mFlatAddress = false;
mVersion = -1U;
@@ -69,7 +67,6 @@
SplitString(Features[x], version, "=");
mVersion = ::atoi(version[1].data());
} else {
- GPU = CPU;
if (newFeatures.length() > 0) newFeatures += ',';
newFeatures += Features[x];
}
Added: llvm/branches/AMDILBackend/test/CodeGen/AMDIL/empty_file.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/test/CodeGen/AMDIL/empty_file.ll?rev=161996&view=auto
==============================================================================
--- llvm/branches/AMDILBackend/test/CodeGen/AMDIL/empty_file.ll (added)
+++ llvm/branches/AMDILBackend/test/CodeGen/AMDIL/empty_file.ll Wed Aug 15 17:39:43 2012
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=amdil | FileCheck %s
+; CHECK: il_cs_2_0
+; CHECK-NEXT: dcl_cb cb0[15]
+; CHECK-NEXT: dcl_literal l0, 0x00000004, 0x00000001, 0x00000002, 0x00000003
+; CHECK-NEXT: dcl_literal l1, 0x00FFFFFF, 0xFFFFFFFF, 0xFFFFFFFE, 0xFFFFFFFD
+; CHECK-NEXT: dcl_literal l2, 0x0000FFFF, 0xFFFFFFFE, 0x000000FF, 0xFFFFFFFC
+; CHECK-NEXT: dcl_literal l3, 0x00000018, 0x00000010, 0x00000008, 0xFFFFFFFF
+; CHECK-NEXT: dcl_literal l4, 0xFFFFFF00, 0xFFFF0000, 0xFF00FFFF, 0xFFFF00FF
+; CHECK-NEXT: dcl_literal l5, 0x00000000, 0x00000004, 0x00000008, 0x0000000C
+; CHECK-NEXT: dcl_literal l6, 0x00000020, 0x00000020, 0x00000020, 0x00000020
+; CHECK-NEXT: dcl_literal l7, 0x00000018, 0x0000001F, 0x00000010, 0x0000001F
+; CHECK-NEXT: dcl_literal l8, 0x80000000, 0x80000000, 0x80000000, 0x80000000
+; CHECK-NEXT: ;$$$$$$$$$$
+; CHECK-NEXT: endmain
+; CHECK: end
Added: llvm/branches/AMDILBackend/test/CodeGen/AMDIL/empty_func.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/test/CodeGen/AMDIL/empty_func.ll?rev=161996&view=auto
==============================================================================
--- llvm/branches/AMDILBackend/test/CodeGen/AMDIL/empty_func.ll (added)
+++ llvm/branches/AMDILBackend/test/CodeGen/AMDIL/empty_func.ll Wed Aug 15 17:39:43 2012
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=amdil | FileCheck %s
+; CHECK: il_cs_2_0
+; CHECK-NEXT: dcl_cb cb0[15] ; Constant buffer that holds ABI data
+; CHECK-NEXT: dcl_literal l0, 0x00000004, 0x00000001, 0x00000002, 0x00000003
+; CHECK-NEXT: dcl_literal l1, 0x00FFFFFF, 0xFFFFFFFF, 0xFFFFFFFE, 0xFFFFFFFD
+; CHECK-NEXT: dcl_literal l2, 0x0000FFFF, 0xFFFFFFFE, 0x000000FF, 0xFFFFFFFC
+; CHECK-NEXT: dcl_literal l3, 0x00000018, 0x00000010, 0x00000008, 0xFFFFFFFF
+; CHECK-NEXT: dcl_literal l4, 0xFFFFFF00, 0xFFFF0000, 0xFF00FFFF, 0xFFFF00FF
+; CHECK-NEXT: dcl_literal l5, 0x00000000, 0x00000004, 0x00000008, 0x0000000C
+; CHECK-NEXT: dcl_literal l6, 0x00000020, 0x00000020, 0x00000020, 0x00000020
+; CHECK-NEXT: dcl_literal l7, 0x00000018, 0x0000001F, 0x00000010, 0x0000001F
+; CHECK-NEXT: dcl_literal l8, 0x80000000, 0x80000000, 0x80000000, 0x80000000
+; CHECK: endmain
+; CHECK: .text
+; CHECK: .global at foo
+; CHECK: func 1024
+; CHECK: ret_dyn
+; CHECK: ret
+; CHECK: endfunc
+; CHECK: end
+
+define void @foo() {
+ ret void
+}
Added: llvm/branches/AMDILBackend/test/CodeGen/AMDIL/empty_kernel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/test/CodeGen/AMDIL/empty_kernel.ll?rev=161996&view=auto
==============================================================================
--- llvm/branches/AMDILBackend/test/CodeGen/AMDIL/empty_kernel.ll (added)
+++ llvm/branches/AMDILBackend/test/CodeGen/AMDIL/empty_kernel.ll Wed Aug 15 17:39:43 2012
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=amdil | FileCheck %s
+; CHECK: il_cs_2_0
+; CHECK-NEXT: dcl_cb cb0[15] ; Constant buffer that holds ABI data
+; CHECK-NEXT: dcl_literal l0, 0x00000004, 0x00000001, 0x00000002, 0x00000003
+; CHECK-NEXT: dcl_literal l1, 0x00FFFFFF, 0xFFFFFFFF, 0xFFFFFFFE, 0xFFFFFFFD
+; CHECK-NEXT: dcl_literal l2, 0x0000FFFF, 0xFFFFFFFE, 0x000000FF, 0xFFFFFFFC
+; CHECK-NEXT: dcl_literal l3, 0x00000018, 0x00000010, 0x00000008, 0xFFFFFFFF
+; CHECK-NEXT: dcl_literal l4, 0xFFFFFF00, 0xFFFF0000, 0xFF00FFFF, 0xFFFF00FF
+; CHECK-NEXT: dcl_literal l5, 0x00000000, 0x00000004, 0x00000008, 0x0000000C
+; CHECK-NEXT: dcl_literal l6, 0x00000020, 0x00000020, 0x00000020, 0x00000020
+; CHECK-NEXT: dcl_literal l7, 0x00000018, 0x0000001F, 0x00000010, 0x0000001F
+; CHECK-NEXT: dcl_literal l8, 0x80000000, 0x80000000, 0x80000000, 0x80000000
+; CHECK: endmain
+; CHECK: .text
+; CHECK: .global at __OpenCL_foo_Kernel
+; CHECK: func 1024
+; CHECK: ret_dyn
+; CHECK: ret
+; CHECK: endfunc
+; CHECK: end
+
+define void @__OpenCL_foo_Kernel() {
+ ret void
+}
+
Added: llvm/branches/AMDILBackend/test/CodeGen/AMDIL/exit.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/test/CodeGen/AMDIL/exit.ll?rev=161996&view=auto
==============================================================================
--- llvm/branches/AMDILBackend/test/CodeGen/AMDIL/exit.ll (added)
+++ llvm/branches/AMDILBackend/test/CodeGen/AMDIL/exit.ll Wed Aug 15 17:39:43 2012
@@ -0,0 +1,26 @@
+; RUN: llc < %s -march=amdil | FileCheck %s
+
+define void @t1(i32* %p, i32 %x) {
+; CHECK: mov r1011, r1.y
+; CHECK-NEXT: mov r1010.x___, r1.x
+; CHECK-NEXT: ishr r1007.x___, r1010.x, l12
+; CHECK-NEXT: iand r1008.x___, r1007.x, l13
+; CHECK-NEXT: ishr r1007.x___, r1007.x, l12
+; CHECK-NEXT: switch r1008.x
+; CHECK-NEXT: default
+; CHECK-NEXT: mov x1[r1007.x].x___, r1011.x
+; CHECK-NEXT: break
+; CHECK-NEXT: case 1
+; CHECK-NEXT: mov x1[r1007.x]._y__, r1011.x
+; CHECK-NEXT: break
+; CHECK-NEXT: case 2
+; CHECK-NEXT: mov x1[r1007.x].__z_, r1011.x
+; CHECK-NEXT: break
+; CHECK-NEXT: case 3
+; CHECK-NEXT: mov x1[r1007.x].___w, r1011.x
+; CHECK-NEXT: break
+; CHECK-NEXT: endswitch
+
+ store i32 %x, i32* %p
+ ret void
+}
Added: llvm/branches/AMDILBackend/test/CodeGen/AMDIL/ld.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/test/CodeGen/AMDIL/ld.ll?rev=161996&view=auto
==============================================================================
--- llvm/branches/AMDILBackend/test/CodeGen/AMDIL/ld.ll (added)
+++ llvm/branches/AMDILBackend/test/CodeGen/AMDIL/ld.ll Wed Aug 15 17:39:43 2012
@@ -0,0 +1,780 @@
+; RUN: llc < %s -march=amdil | FileCheck %s
+
+ at array_i16 = global [10 x i16] zeroinitializer
+ at array_constant_i16 = addrspace(1) constant [10 x i16] zeroinitializer
+ at array_local_i16 = addrspace(2) global [10 x i16] zeroinitializer
+ at array_shared_i16 = addrspace(4) global [10 x i16] zeroinitializer
+ at array_i32 = global [10 x i32] zeroinitializer
+ at array_constant_i32 = addrspace(1) constant [10 x i32] zeroinitializer
+ at array_local_i32 = addrspace(2) global [10 x i32] zeroinitializer
+ at array_shared_i32 = addrspace(4) global [10 x i32] zeroinitializer
+ at array_i64 = global [10 x i64] zeroinitializer
+ at array_constant_i64 = addrspace(1) constant [10 x i64] zeroinitializer
+ at array_local_i64 = addrspace(2) global [10 x i64] zeroinitializer
+ at array_shared_i64 = addrspace(4) global [10 x i64] zeroinitializer
+ at array_float = global [10 x float] zeroinitializer
+ at array_constant_float = addrspace(1) constant [10 x float] zeroinitializer
+ at array_local_float = addrspace(2) global [10 x float] zeroinitializer
+ at array_shared_float = addrspace(4) global [10 x float] zeroinitializer
+ at array_double = global [10 x double] zeroinitializer
+ at array_constant_double = addrspace(1) constant [10 x double] zeroinitializer
+ at array_local_double = addrspace(2) global [10 x double] zeroinitializer
+ at array_shared_double = addrspace(4) global [10 x double] zeroinitializer
+
+define i16 @t1_u16(i16* %p) {
+ ; CHECK: t1_u16
+ ; CHECK: mov r1010.x___, r1.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l12
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l13
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l12
+ ; CHECK-NEXT: iadd r1008, r1008.x, l14
+ ; CHECK-NEXT: ieq r1008, r1008, l15
+ ; CHECK-NEXT: mov r1011, x1[r1007.x]
+ ; CHECK-NEXT: cmov_logical r1011.x___, r1008.y, r1011.y, r1011.x
+ ; CHECK-NEXT: cmov_logical r1011.x___, r1008.z, r1011.z, r1011.x
+ ; CHECK-NEXT: cmov_logical r1011.x___, r1008.w, r1011.w, r1011.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l16
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l16
+ ; CHECK-NEXT: ishr r1007.x___, r1011.x, l17
+ ; CHECK-NEXT: cmov_logical r1011.x___, r1008.x, r1007.x, r1011.x
+ ; CHECK-NEXT: mov r65.x___, r1011.x
+ ; CHECK-NEXT: mov r1.x___, r65.x
+
+ %x = load i16* %p
+ ret i16 %x
+}
+
+define i32 @t1_u32(i32* %p) {
+
+ ; CHECK: t1_u32
+ ; CHECK: mov r1010.x___, r1.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l12
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l13
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l12
+ ; CHECK-NEXT: iadd r1008, r1008.x, l14
+ ; CHECK-NEXT: ieq r1008, r1008, l15
+ ; CHECK-NEXT: mov r1011, x1[r1007.x]
+ ; CHECK-NEXT: cmov_logical r1011.x___, r1008.y, r1011.y, r1011.x
+ ; CHECK-NEXT: cmov_logical r1011.x___, r1008.z, r1011.z, r1011.x
+ ; CHECK-NEXT: cmov_logical r1011.x___, r1008.w, r1011.w, r1011.x
+ ; CHECK-NEXT: mov r65.x___, r1011.x
+ ; CHECK-NEXT: mov r1.x___, r65.x
+
+ %x = load i32* %p
+ ret i32 %x
+}
+
+define i64 @t1_u64(i64* %p) {
+
+ ; CHECK: t1_u64
+ ; CHECK: mov r1010.x___, r1.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l12
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l13
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l13
+ ; CHECK-NEXT: iadd r1008, r1008.x, l14
+ ; CHECK-NEXT: ieq r1008, r1008, l15
+ ; CHECK-NEXT: mov r1011, x1[r1007.x]
+ ; CHECK-NEXT: cmov_logical r1011.xy__, r1008.x, r1011.xyxy, r1011.zwzw
+ ; CHECK-NEXT: mov r65.xy__, r1011.xyxy
+ ; CHECK-NEXT: mov r1.xy__, r65.xyxy
+
+ %x = load i64* %p
+ ret i64 %x
+}
+
+define float @t1_f32(float* %p) {
+
+ ; CHECK: t1_f32
+ ; CHECK: mov r1010.x___, r1.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l12
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l13
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l12
+ ; CHECK-NEXT: iadd r1008, r1008.x, l14
+ ; CHECK-NEXT: ieq r1008, r1008, l15
+ ; CHECK-NEXT: mov r1011, x1[r1007.x]
+ ; CHECK-NEXT: cmov_logical r1011.x___, r1008.y, r1011.y, r1011.x
+ ; CHECK-NEXT: cmov_logical r1011.x___, r1008.z, r1011.z, r1011.x
+ ; CHECK-NEXT: cmov_logical r1011.x___, r1008.w, r1011.w, r1011.x
+ ; CHECK-NEXT: mov r65.x___, r1011.x
+ ; CHECK-NEXT: mov r1.x___, r65.x
+
+ %x = load float* %p
+ ret float %x
+}
+
+define double @t1_f64(double* %p) {
+
+
+ ; CHECK: t1_f64
+ ; CHECK: mov r1010.x___, r1.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l12
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l13
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l13
+ ; CHECK-NEXT: iadd r1008, r1008.x, l14
+ ; CHECK-NEXT: ieq r1008, r1008, l15
+ ; CHECK-NEXT: mov r1011, x1[r1007.x]
+ ; CHECK-NEXT: cmov_logical r1011.xy__, r1008.x, r1011.xyxy, r1011.zwzw
+ ; CHECK-NEXT: mov r65.xy__, r1011.xyxy
+ ; CHECK-NEXT: mov r1.xy__, r65.xyxy
+
+ %x = load double* %p
+ ret double %x
+}
+
+define i16 @t2_u16(i16* %p) {
+
+
+ ; CHECK: t2_u16
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: iadd r65.x___, r1.x, r65.x
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l12
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l13
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l12
+ ; CHECK-NEXT: iadd r1008, r1008.x, l14
+ ; CHECK-NEXT: ieq r1008, r1008, l15
+ ; CHECK-NEXT: mov r1011, x1[r1007.x]
+ ; CHECK-NEXT: cmov_logical r1011.x___, r1008.y, r1011.y, r1011.x
+ ; CHECK-NEXT: cmov_logical r1011.x___, r1008.z, r1011.z, r1011.x
+ ; CHECK-NEXT: cmov_logical r1011.x___, r1008.w, r1011.w, r1011.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l16
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l16
+ ; CHECK-NEXT: ishr r1007.x___, r1011.x, l17
+ ; CHECK-NEXT: cmov_logical r1011.x___, r1008.x, r1007.x, r1011.x
+ ; CHECK-NEXT: mov r65.x___, r1011.x
+ ; CHECK-NEXT: mov r1.x___, r65.x
+
+ %i = getelementptr i16* %p, i32 1
+ %x = load i16* %i
+ ret i16 %x
+}
+
+define i32 @t2_u32(i32* %p) {
+
+
+ ; CHECK: t2_u32
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: iadd r65.x___, r1.x, r65.x
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l13
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l14
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l13
+ ; CHECK-NEXT: iadd r1008, r1008.x, l15
+ ; CHECK-NEXT: ieq r1008, r1008, l16
+ ; CHECK-NEXT: mov r1011, x1[r1007.x]
+ ; CHECK-NEXT: cmov_logical r1011.x___, r1008.y, r1011.y, r1011.x
+ ; CHECK-NEXT: cmov_logical r1011.x___, r1008.z, r1011.z, r1011.x
+ ; CHECK-NEXT: cmov_logical r1011.x___, r1008.w, r1011.w, r1011.x
+ ; CHECK-NEXT: mov r65.x___, r1011.x
+ ; CHECK-NEXT: mov r1.x___, r65.x
+
+
+ %i = getelementptr i32* %p, i32 1
+ %x = load i32* %i
+ ret i32 %x
+}
+
+define i64 @t2_u64(i64* %p) {
+
+
+ ; CHECK: t2_u64
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: iadd r65.x___, r1.x, r65.x
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l13
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l14
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l14
+ ; CHECK-NEXT: iadd r1008, r1008.x, l15
+ ; CHECK-NEXT: ieq r1008, r1008, l16
+ ; CHECK-NEXT: mov r1011, x1[r1007.x]
+ ; CHECK-NEXT: cmov_logical r1011.xy__, r1008.x, r1011.xyxy, r1011.zwzw
+ ; CHECK-NEXT: mov r65.xy__, r1011.xyxy
+ ; CHECK-NEXT: mov r1.xy__, r65.xyxy
+
+ %i = getelementptr i64* %p, i32 1
+ %x = load i64* %i
+ ret i64 %x
+}
+
+define float @t2_f32(float* %p) {
+
+
+ ; CHECK: t2_f32
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: iadd r65.x___, r1.x, r65.x
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l13
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l14
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l13
+ ; CHECK-NEXT: iadd r1008, r1008.x, l15
+ ; CHECK-NEXT: ieq r1008, r1008, l16
+ ; CHECK-NEXT: mov r1011, x1[r1007.x]
+ ; CHECK-NEXT: cmov_logical r1011.x___, r1008.y, r1011.y, r1011.x
+ ; CHECK-NEXT: cmov_logical r1011.x___, r1008.z, r1011.z, r1011.x
+ ; CHECK-NEXT: cmov_logical r1011.x___, r1008.w, r1011.w, r1011.x
+ ; CHECK-NEXT: mov r65.x___, r1011.x
+ ; CHECK-NEXT: mov r1.x___, r65.x
+
+ %i = getelementptr float* %p, i32 1
+ %x = load float* %i
+ ret float %x
+}
+
+define double @t2_f64(double* %p) {
+
+
+ ; CHECK: t2_f64
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: iadd r65.x___, r1.x, r65.x
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l13
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l14
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l14
+ ; CHECK-NEXT: iadd r1008, r1008.x, l15
+ ; CHECK-NEXT: ieq r1008, r1008, l16
+ ; CHECK-NEXT: mov r1011, x1[r1007.x]
+ ; CHECK-NEXT: cmov_logical r1011.xy__, r1008.x, r1011.xyxy, r1011.zwzw
+ ; CHECK-NEXT: mov r65.xy__, r1011.xyxy
+ ; CHECK-NEXT: mov r1.xy__, r65.xyxy
+
+ %i = getelementptr double* %p, i32 1
+ %x = load double* %i
+ ret double %x
+}
+
+define i16 @t3_u16(i16* %p, i32 %q) {
+
+
+ ; CHECK: t3_u16
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: ishl r65.x___, r1.y, r65.x
+ ; CHECK-NEXT: iadd r65.x___, r1.x, r65.x
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l13
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l14
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l13
+ ; CHECK-NEXT: iadd r1008, r1008.x, l15
+ ; CHECK-NEXT: ieq r1008, r1008, l16
+ ; CHECK-NEXT: mov r1011, x1[r1007.x]
+ ; CHECK-NEXT: cmov_logical r1011.x___, r1008.y, r1011.y, r1011.x
+ ; CHECK-NEXT: cmov_logical r1011.x___, r1008.z, r1011.z, r1011.x
+ ; CHECK-NEXT: cmov_logical r1011.x___, r1008.w, r1011.w, r1011.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l12
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l12
+ ; CHECK-NEXT: ishr r1007.x___, r1011.x, l17
+ ; CHECK-NEXT: cmov_logical r1011.x___, r1008.x, r1007.x, r1011.x
+ ; CHECK-NEXT: mov r65.x___, r1011.x
+ ; CHECK-NEXT: mov r1.x___, r65.x
+
+ %i = getelementptr i16* %p, i32 %q
+ %x = load i16* %i
+ ret i16 %x
+}
+
+define i32 @t3_u32(i32* %p, i32 %q) {
+
+
+ ; CHECK: t3_u32
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: ishl r65.x___, r1.y, r65.x
+ ; CHECK-NEXT: iadd r65.x___, r1.x, r65.x
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l12
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l13
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l12
+ ; CHECK-NEXT: iadd r1008, r1008.x, l14
+ ; CHECK-NEXT: ieq r1008, r1008, l15
+ ; CHECK-NEXT: mov r1011, x1[r1007.x]
+ ; CHECK-NEXT: cmov_logical r1011.x___, r1008.y, r1011.y, r1011.x
+ ; CHECK-NEXT: cmov_logical r1011.x___, r1008.z, r1011.z, r1011.x
+ ; CHECK-NEXT: cmov_logical r1011.x___, r1008.w, r1011.w, r1011.x
+ ; CHECK-NEXT: mov r65.x___, r1011.x
+ ; CHECK-NEXT: mov r1.x___, r65.x
+
+ %i = getelementptr i32* %p, i32 %q
+ %x = load i32* %i
+ ret i32 %x
+}
+
+define i64 @t3_u64(i64* %p, i32 %q) {
+
+
+ ; CHECK: t3_u64
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: ishl r65.x___, r1.y, r65.x
+ ; CHECK-NEXT: iadd r65.x___, r1.x, r65.x
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l12
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l13
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l13
+ ; CHECK-NEXT: iadd r1008, r1008.x, l14
+ ; CHECK-NEXT: ieq r1008, r1008, l15
+ ; CHECK-NEXT: mov r1011, x1[r1007.x]
+ ; CHECK-NEXT: cmov_logical r1011.xy__, r1008.x, r1011.xyxy, r1011.zwzw
+ ; CHECK-NEXT: mov r65.xy__, r1011.xyxy
+ ; CHECK-NEXT: mov r1.xy__, r65.xyxy
+
+ %i = getelementptr i64* %p, i32 %q
+ %x = load i64* %i
+ ret i64 %x
+}
+
+define float @t3_f32(float* %p, i32 %q) {
+
+
+ ; CHECK: t3_f32
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: ishl r65.x___, r1.y, r65.x
+ ; CHECK-NEXT: iadd r65.x___, r1.x, r65.x
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l12
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l13
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l12
+ ; CHECK-NEXT: iadd r1008, r1008.x, l14
+ ; CHECK-NEXT: ieq r1008, r1008, l15
+ ; CHECK-NEXT: mov r1011, x1[r1007.x]
+ ; CHECK-NEXT: cmov_logical r1011.x___, r1008.y, r1011.y, r1011.x
+ ; CHECK-NEXT: cmov_logical r1011.x___, r1008.z, r1011.z, r1011.x
+ ; CHECK-NEXT: cmov_logical r1011.x___, r1008.w, r1011.w, r1011.x
+ ; CHECK-NEXT: mov r65.x___, r1011.x
+ ; CHECK-NEXT: mov r1.x___, r65.x
+
+ %i = getelementptr float* %p, i32 %q
+ %x = load float* %i
+ ret float %x
+}
+
+define double @t3_f64(double* %p, i32 %q) {
+
+
+ ; CHECK: t3_f64
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: ishl r65.x___, r1.y, r65.x
+ ; CHECK-NEXT: iadd r65.x___, r1.x, r65.x
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l12
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l13
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l13
+ ; CHECK-NEXT: iadd r1008, r1008.x, l14
+ ; CHECK-NEXT: ieq r1008, r1008, l15
+ ; CHECK-NEXT: mov r1011, x1[r1007.x]
+ ; CHECK-NEXT: cmov_logical r1011.xy__, r1008.x, r1011.xyxy, r1011.zwzw
+ ; CHECK-NEXT: mov r65.xy__, r1011.xyxy
+ ; CHECK-NEXT: mov r1.xy__, r65.xyxy
+
+ %i = getelementptr double* %p, i32 %q
+ %x = load double* %i
+ ret double %x
+}
+
+define i16 @t4_global_u16() {
+
+
+ ; CHECK: t4_global_u16
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: iand r1008.x___, r1010.x, l13
+ ; CHECK-NEXT: ishr r1008.x___, r1008.x, l14
+ ; CHECK-NEXT: iand r1010.x___, r1010.x, l15
+ ; CHECK-NEXT: cmov_logical r1008.x___, r1008.x, l17, l16
+ ; CHECK-NEXT: uav_raw_load_id(0) r1011.x___, r1010.x
+ ; CHECK-NEXT: ishr r1011.x___, r1011.x, r1008.x
+ ; CHECK-NEXT: mov r65.x___, r1011.x
+ ; CHECK-NEXT: mov r1.x___, r65.x
+
+ %i = getelementptr [10 x i16]* @array_i16, i32 0, i32 0
+ %x = load i16* %i
+ ret i16 %x
+}
+
+define i32 @t4_global_u32() {
+
+
+ ; CHECK: t4_global_u32
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: uav_raw_load_id(0) r1011.x___, r1010.x
+ ; CHECK-NEXT: mov r65.x___, r1011.x
+ ; CHECK-NEXT: mov r1.x___, r65.x
+
+ %i = getelementptr [10 x i32]* @array_i32, i32 0, i32 0
+ %x = load i32* %i
+ ret i32 %x
+}
+
+define i64 @t4_global_u64() {
+
+
+ ; CHECK: t4_global_u64
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: uav_raw_load_id(0) r1011.xy__, r1010.x
+ ; CHECK-NEXT: mov r65.xy__, r1011.xyxy
+ ; CHECK-NEXT: mov r1.xy__, r65.xyxy
+
+ %i = getelementptr [10 x i64]* @array_i64, i32 0, i32 0
+ %x = load i64* %i
+ ret i64 %x
+}
+
+define float @t4_global_f32() {
+
+
+ ; CHECK: t4_global_f32
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: uav_raw_load_id(0) r1011.x___, r1010.x
+ ; CHECK-NEXT: mov r65.x___, r1011.x
+ ; CHECK-NEXT: mov r1.x___, r65.x
+
+ %i = getelementptr [10 x float]* @array_float, i32 0, i32 0
+ %x = load float* %i
+ ret float %x
+}
+
+define double @t4_global_f64() {
+
+
+ ; CHECK: t4_global_f64
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: uav_raw_load_id(0) r1011.xy__, r1010.x
+ ; CHECK-NEXT: mov r65.xy__, r1011.xyxy
+ ; CHECK-NEXT: mov r1.xy__, r65.xyxy
+
+ %i = getelementptr [10 x double]* @array_double, i32 0, i32 0
+ %x = load double* %i
+ ret double %x
+}
+
+define i16 @t4_const_u16() {
+
+
+ ; CHECK: t4_const_u16
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: iand r1008.x___, r1010.x, l13
+ ; CHECK-NEXT: ishr r1008.x___, r1008.x, l14
+ ; CHECK-NEXT: iand r1010.x___, r1010.x, l15
+ ; CHECK-NEXT: cmov_logical r1008.x___, r1008.x, l17, l16
+ ; CHECK-NEXT: uav_raw_load_id(0) r1011.x___, r1010.x
+ ; CHECK-NEXT: ishr r1011.x___, r1011.x, r1008.x
+ ; CHECK-NEXT: mov r65.x___, r1011.x
+ ; CHECK-NEXT: mov r1.x___, r65.x
+
+ %i = getelementptr [10 x i16] addrspace(1)* @array_constant_i16, i32 0, i32 0
+ %x = load i16 addrspace(1)* %i
+ ret i16 %x
+}
+
+define i32 @t4_const_u32() {
+
+
+ ; CHECK: t4_const_u32
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: uav_raw_load_id(0) r1011.x___, r1010.x
+ ; CHECK-NEXT: mov r65.x___, r1011.x
+ ; CHECK-NEXT: mov r1.x___, r65.x
+
+ %i = getelementptr [10 x i32] addrspace(1)* @array_constant_i32, i32 0, i32 0
+ %x = load i32 addrspace(1)* %i
+ ret i32 %x
+}
+
+define i64 @t4_const_u64() {
+
+
+ ; CHECK: t4_const_u64
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: uav_raw_load_id(0) r1011.xy__, r1010.x
+ ; CHECK-NEXT: mov r65.xy__, r1011.xyxy
+ ; CHECK-NEXT: mov r1.xy__, r65.xyxy
+
+ %i = getelementptr [10 x i64] addrspace(1)* @array_constant_i64, i32 0, i32 0
+ %x = load i64 addrspace(1)* %i
+ ret i64 %x
+}
+
+define float @t4_const_f32() {
+
+
+ ; CHECK: t4_const_f32
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: uav_raw_load_id(0) r1011.x___, r1010.x
+ ; CHECK-NEXT: mov r65.x___, r1011.x
+ ; CHECK-NEXT: mov r1.x___, r65.x
+
+
+ %i = getelementptr [10 x float] addrspace(1)* @array_constant_float, i32 0, i32 0
+ %x = load float addrspace(1)* %i
+ ret float %x
+}
+
+define double @t4_const_f64() {
+
+
+ ; CHECK: t4_const_f64
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: uav_raw_load_id(0) r1011.xy__, r1010.x
+ ; CHECK-NEXT: mov r65.xy__, r1011.xyxy
+ ; CHECK-NEXT: mov r1.xy__, r65.xyxy
+
+ %i = getelementptr [10 x double] addrspace(1)* @array_constant_double, i32 0, i32 0
+ %x = load double addrspace(1)* %i
+ ret double %x
+}
+
+define i16 @t4_local_u16() {
+
+
+ ; CHECK: t4_local_u16
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: iand r1008.x___, r1010.x, l13
+ ; CHECK-NEXT: ishr r1008.x___, r1008.x, l14
+ ; CHECK-NEXT: iand r1010.x___, r1010.x, l15
+ ; CHECK-NEXT: cmov_logical r1008.x___, r1008.x, l17, l16
+ ; CHECK-NEXT: uav_raw_load_id(0) r1011.x___, r1010.x
+ ; CHECK-NEXT: ishr r1011.x___, r1011.x, r1008.x
+ ; CHECK-NEXT: mov r65.x___, r1011.x
+ ; CHECK-NEXT: mov r1.x___, r65.x
+
+ %i = getelementptr [10 x i16] addrspace(2)* @array_local_i16, i32 0, i32 0
+ %x = load i16 addrspace(2)* %i
+ ret i16 %x
+}
+
+define i32 @t4_local_u32() {
+
+
+ ; CHECK: t4_local_u32
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: uav_raw_load_id(0) r1011.x___, r1010.x
+ ; CHECK-NEXT: mov r65.x___, r1011.x
+ ; CHECK-NEXT: mov r1.x___, r65.x
+
+ %i = getelementptr [10 x i32] addrspace(2)* @array_local_i32, i32 0, i32 0
+ %x = load i32 addrspace(2)* %i
+ ret i32 %x
+}
+
+define i64 @t4_local_u64() {
+
+
+ ; CHECK: t4_local_u64
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: uav_raw_load_id(0) r1011.xy__, r1010.x
+ ; CHECK-NEXT: mov r65.xy__, r1011.xyxy
+ ; CHECK-NEXT: mov r1.xy__, r65.xyxy
+
+ %i = getelementptr [10 x i64] addrspace(2)* @array_local_i64, i32 0, i32 0
+ %x = load i64 addrspace(2)* %i
+ ret i64 %x
+}
+
+define float @t4_local_f32() {
+
+
+ ; CHECK: t4_local_f32
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: uav_raw_load_id(0) r1011.x___, r1010.x
+ ; CHECK-NEXT: mov r65.x___, r1011.x
+ ; CHECK-NEXT: mov r1.x___, r65.x
+
+ %i = getelementptr [10 x float] addrspace(2)* @array_local_float, i32 0, i32 0
+ %x = load float addrspace(2)* %i
+ ret float %x
+}
+
+define double @t4_local_f64() {
+
+
+ ; CHECK: t4_local_f64
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: uav_raw_load_id(0) r1011.xy__, r1010.x
+ ; CHECK-NEXT: mov r65.xy__, r1011.xyxy
+ ; CHECK-NEXT: mov r1.xy__, r65.xyxy
+
+ %i = getelementptr [10 x double] addrspace(2)* @array_local_double, i32 0, i32 0
+ %x = load double addrspace(2)* %i
+ ret double %x
+}
+
+define i16 @t4_shared_u16() {
+
+
+ ; CHECK: t4_shared_u16
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r1.x___, r65.x
+
+ %i = getelementptr [10 x i16] addrspace(4)* @array_shared_i16, i32 0, i32 0
+ %x = load i16 addrspace(4)* %i
+ ret i16 %x
+}
+
+define i32 @t4_shared_u32() {
+
+
+ ; CHECK: t4_shared_u32
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r1.x___, r65.x
+
+ %i = getelementptr [10 x i32] addrspace(4)* @array_shared_i32, i32 0, i32 0
+ %x = load i32 addrspace(4)* %i
+ ret i32 %x
+}
+
+define i64 @t4_shared_u64() {
+
+
+ ; CHECK: t4_shared_u64
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r1.xy__, r65.xyxy
+
+ %i = getelementptr [10 x i64] addrspace(4)* @array_shared_i64, i32 0, i32 0
+ %x = load i64 addrspace(4)* %i
+ ret i64 %x
+}
+
+define float @t4_shared_f32() {
+
+
+ ; CHECK: t4_shared_f32
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r1.x___, r65.x
+
+ %i = getelementptr [10 x float] addrspace(4)* @array_shared_float, i32 0, i32 0
+ %x = load float addrspace(4)* %i
+ ret float %x
+}
+
+define double @t4_shared_f64() {
+
+
+ ; CHECK: t4_shared_f64
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r1.xy__, r65.xyxy
+
+ %i = getelementptr [10 x double] addrspace(4)* @array_shared_double, i32 0, i32 0
+ %x = load double addrspace(4)* %i
+ ret double %x
+}
+
+define i16 @t5_u16() {
+
+
+ ; CHECK: t5_u16
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r66.x___, l13
+ ; CHECK-NEXT: iadd r65.x___, r66.x, r65.x
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: iand r1008.x___, r1010.x, l14
+ ; CHECK-NEXT: ishr r1008.x___, r1008.x, l15
+ ; CHECK-NEXT: iand r1010.x___, r1010.x, l16
+ ; CHECK-NEXT: cmov_logical r1008.x___, r1008.x, l18, l17
+ ; CHECK-NEXT: uav_raw_load_id(0) r1011.x___, r1010.x
+ ; CHECK-NEXT: ishr r1011.x___, r1011.x, r1008.x
+ ; CHECK-NEXT: mov r65.x___, r1011.x
+ ; CHECK-NEXT: mov r1.x___, r65.x
+
+ %i = getelementptr [10 x i16]* @array_i16, i32 0, i32 1
+ %x = load i16* %i
+ ret i16 %x
+}
+
+define i32 @t5_u32() {
+
+
+ ; CHECK: t5_u32
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r66.x___, l13
+ ; CHECK-NEXT: iadd r65.x___, r66.x, r65.x
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: uav_raw_load_id(0) r1011.x___, r1010.x
+ ; CHECK-NEXT: mov r65.x___, r1011.x
+ ; CHECK-NEXT: mov r1.x___, r65.x
+
+ %i = getelementptr [10 x i32]* @array_i32, i32 0, i32 1
+ %x = load i32* %i
+ ret i32 %x
+}
+
+define i64 @t5_u64() {
+
+
+ ; CHECK: t5_u64
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r66.x___, l13
+ ; CHECK-NEXT: iadd r65.x___, r66.x, r65.x
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: uav_raw_load_id(0) r1011.xy__, r1010.x
+ ; CHECK-NEXT: mov r65.xy__, r1011.xyxy
+ ; CHECK-NEXT: mov r1.xy__, r65.xyxy
+
+ %i = getelementptr [10 x i64]* @array_i64, i32 0, i32 1
+ %x = load i64* %i
+ ret i64 %x
+}
+
+define float @t5_f32() {
+
+
+ ; CHECK: t5_f32
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r66.x___, l13
+ ; CHECK-NEXT: iadd r65.x___, r66.x, r65.x
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: uav_raw_load_id(0) r1011.x___, r1010.x
+ ; CHECK-NEXT: mov r65.x___, r1011.x
+ ; CHECK-NEXT: mov r1.x___, r65.x
+
+ %i = getelementptr [10 x float]* @array_float, i32 0, i32 1
+ %x = load float* %i
+ ret float %x
+}
+
+define double @t5_f64() {
+
+
+ ; CHECK: t5_f64
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r66.x___, l13
+ ; CHECK-NEXT: iadd r65.x___, r66.x, r65.x
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: uav_raw_load_id(0) r1011.xy__, r1010.x
+ ; CHECK-NEXT: mov r65.xy__, r1011.xyxy
+ ; CHECK-NEXT: mov r1.xy__, r65.xyxy
+
+ %i = getelementptr [10 x double]* @array_double, i32 0, i32 1
+ %x = load double* %i
+ ret double %x
+}
+
+;CHECK: .global at array_i16:416
+;CHECK: .global at array_constant_i16:752
+;CHECK: .global at array_local_i16:784
+;CHECK: .global at array_shared_i16:128
+;CHECK: .global at array_i32:368
+;CHECK: .global at array_constant_i32:656
+;CHECK: .global at array_local_i32:704
+;CHECK: .global at array_shared_i32:0
+;CHECK: .global at array_i64:528
+;CHECK: .global at array_constant_i64:896
+;CHECK: .global at array_local_i64:976
+;CHECK: .global at array_shared_i64:240
+;CHECK: .global at array_float:608
+;CHECK: .global at array_constant_float:1056
+;CHECK: .global at array_local_float:1104
+;CHECK: .global at array_shared_float:320
+;CHECK: .global at array_double:816
+;CHECK: .global at array_constant_double:48
+;CHECK: .global at array_local_double:160
+;CHECK: .global at array_shared_double:448
Added: llvm/branches/AMDILBackend/test/CodeGen/AMDIL/lit.local.cfg
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/test/CodeGen/AMDIL/lit.local.cfg?rev=161996&view=auto
==============================================================================
--- llvm/branches/AMDILBackend/test/CodeGen/AMDIL/lit.local.cfg (added)
+++ llvm/branches/AMDILBackend/test/CodeGen/AMDIL/lit.local.cfg Wed Aug 15 17:39:43 2012
@@ -0,0 +1,5 @@
+config.suffixes = ['.ll', '.c', '.cpp']
+
+targets = set(config.root.targets_to_build.split())
+if not 'AMDIL' in targets:
+ config.unsupported = True
Added: llvm/branches/AMDILBackend/test/CodeGen/AMDIL/mov.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/test/CodeGen/AMDIL/mov.ll?rev=161996&view=auto
==============================================================================
--- llvm/branches/AMDILBackend/test/CodeGen/AMDIL/mov.ll (added)
+++ llvm/branches/AMDILBackend/test/CodeGen/AMDIL/mov.ll Wed Aug 15 17:39:43 2012
@@ -0,0 +1,93 @@
+; RUN: llc < %s -march=amdil | FileCheck %s
+; CHECK: il_cs_2_0
+; CHECK-NEXT: dcl_cb cb0[15]
+; CHECK-NEXT: dcl_literal l0, 0x00000004, 0x00000001, 0x00000002, 0x00000003
+; CHECK-NEXT: dcl_literal l1, 0x00FFFFFF, 0xFFFFFFFF, 0xFFFFFFFE, 0xFFFFFFFD
+; CHECK-NEXT: dcl_literal l2, 0x0000FFFF, 0xFFFFFFFE, 0x000000FF, 0xFFFFFFFC
+; CHECK-NEXT: dcl_literal l3, 0x00000018, 0x00000010, 0x00000008, 0xFFFFFFFF
+; CHECK-NEXT: dcl_literal l4, 0xFFFFFF00, 0xFFFF0000, 0xFF00FFFF, 0xFFFF00FF
+; CHECK-NEXT: dcl_literal l5, 0x00000000, 0x00000004, 0x00000008, 0x0000000C
+; CHECK-NEXT: dcl_literal l6, 0x00000020, 0x00000020, 0x00000020, 0x00000020
+; CHECK-NEXT: dcl_literal l7, 0x00000018, 0x0000001F, 0x00000010, 0x0000001F
+; CHECK-NEXT: dcl_literal l8, 0x80000000, 0x80000000, 0x80000000, 0x80000000
+
+define i16 @t1_u16() {
+; CHECK: mov r65.x___, l12
+; CHECK: mov r1.x___, r65.x
+; CHECK: ret_dyn
+; CHECK: ret
+
+ ret i16 0
+}
+
+define i32 @t1_u32() {
+; CHECK: mov r65.x___, l12
+; CHECK: mov r1.x___, r65.x
+; CHECK: ret_dyn
+; CHECK: ret
+
+ ret i32 0
+}
+
+define i64 @t1_u64() {
+; CHECK: mov r65.xy__, l12
+; CHECK: mov r1.xy__, r65.xyxy
+; CHECK: ret_dyn
+; CHECK: ret
+
+ ret i64 0
+}
+
+define float @t1_f32() {
+; CHECK: mov r65.x___, l12
+; CHECK: mov r1.x___, r65.x
+; CHECK: ret_dyn
+; CHECK: ret
+
+ ret float 0.0
+}
+
+define double @t1_f64() {
+; CHECK: mov r65.xy__, l12
+; CHECK: mov r1.xy__, r65.xyxy
+; CHECK: ret_dyn
+; CHECK: ret
+
+ ret double 0.0
+}
+
+define i16 @t2_u16(i16 %x) {
+; CHECK: ret_dyn
+; CHECK: ret
+
+ ret i16 %x
+}
+
+define i32 @t2_u32(i32 %x) {
+; CHECK: ret_dyn
+; CHECK: ret
+
+ ret i32 %x
+}
+
+define i64 @t2_u64(i64 %x) {
+; CHECK: ret_dyn
+; CHECK: ret
+
+ ret i64 %x
+}
+
+define float @t3_f32(float %x) {
+; CHECK: ret_dyn
+; CHECK: ret
+
+ ret float %x
+}
+
+define double @t3_f64(double %x) {
+; CHECK: ret_dyn
+; CHECK: ret
+
+ ret double %x
+}
+
Added: llvm/branches/AMDILBackend/test/CodeGen/AMDIL/mul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/test/CodeGen/AMDIL/mul.ll?rev=161996&view=auto
==============================================================================
--- llvm/branches/AMDILBackend/test/CodeGen/AMDIL/mul.ll (added)
+++ llvm/branches/AMDILBackend/test/CodeGen/AMDIL/mul.ll Wed Aug 15 17:39:43 2012
@@ -0,0 +1,22 @@
+; RUN: llc < %s -march=amdil | FileCheck %s
+
+define float @t1_f32(float %x, float %y) {
+; CHECK: mul_ieee r65.x___, r1.x, r1.y
+; CHECK: mov r1.x___, r65.x
+; CHECK: ret_dyn
+; CHECK: ret
+
+ %z = fmul float %x, %y
+ ret float %z
+}
+
+define float @t2_f32(float %x) {
+; CHECK: mov r65.x___, l12
+; CHECK: mul_ieee r65.x___, r1.x, r65.x
+; CHECK: mov r1.x___, r65.x
+; CHECK: ret_dyn
+; CHECK: ret
+
+ %z = fmul float %x, 5.0
+ ret float %z
+}
Added: llvm/branches/AMDILBackend/test/CodeGen/AMDIL/shl.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/test/CodeGen/AMDIL/shl.ll?rev=161996&view=auto
==============================================================================
--- llvm/branches/AMDILBackend/test/CodeGen/AMDIL/shl.ll (added)
+++ llvm/branches/AMDILBackend/test/CodeGen/AMDIL/shl.ll Wed Aug 15 17:39:43 2012
@@ -0,0 +1,26 @@
+; RUN: llc < %s -march=amdil | FileCheck %s
+
+define i32 @t1(i32 %x, i32 %y) {
+; CHECK: ishl r65.x___, r1.x, r1.y
+; CHECK-NEXT: mov r1.x___, r65.x
+
+ %z = shl i32 %x, %y
+ ret i32 %z
+}
+
+define i32 @t2(i32 %x) {
+; CHECK: mov r65.x___, l12
+; CHECK-NEXT: ishl r65.x___, r1.x, r65.x
+
+ %z = shl i32 %x, 3
+ ret i32 %z
+}
+
+define i32 @t3(i32 %x) {
+; CHECK: mov r65.x___, l12
+; CHECK-NEXT: ishl r65.x___, r65.x, r1.x
+; CHECK-NEXT: mov r1.x___, r65.x
+
+ %z = shl i32 3, %x
+ ret i32 %z
+}
Added: llvm/branches/AMDILBackend/test/CodeGen/AMDIL/shr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/test/CodeGen/AMDIL/shr.ll?rev=161996&view=auto
==============================================================================
--- llvm/branches/AMDILBackend/test/CodeGen/AMDIL/shr.ll (added)
+++ llvm/branches/AMDILBackend/test/CodeGen/AMDIL/shr.ll Wed Aug 15 17:39:43 2012
@@ -0,0 +1,52 @@
+; RUN: llc < %s -march=amdil | FileCheck %s
+
+define i32 @t1(i32 %x, i32 %y) {
+; CHECK: ushr r65.x___, r1.x, r1.y
+; CHECK-NEXT: mov r1.x___, r65.x
+
+ %z = lshr i32 %x, %y
+ ret i32 %z
+}
+
+define i32 @t2(i32 %x) {
+; CHECK: mov r65.x___, l12
+; CHECK-NEXT: ushr r65.x___, r1.x, r65.x
+; CHECK-NEXT: mov r1.x___, r65.x
+
+ %z = lshr i32 %x, 3
+ ret i32 %z
+}
+
+define i32 @t3(i32 %x) {
+; CHECK: mov r65.x___, l12
+; CHECK-NEXT: ushr r65.x___, r65.x, r1.x
+; CHECK-NEXT: mov r1.x___, r65.x
+
+ %z = lshr i32 3, %x
+ ret i32 %z
+}
+
+define i32 @t4(i32 %x, i32 %y) {
+; CHECK: ishr r65.x___, r1.x, r1.y
+; CHECK-NEXT: mov r1.x___, r65.x
+
+ %z = ashr i32 %x, %y
+ ret i32 %z
+}
+
+define i32 @t5(i32 %x) {
+; CHECK: mov r65.x___, l12
+; CHECK-NEXT: ishr r65.x___, r1.x, r65.x
+
+ %z = ashr i32 %x, 3
+ ret i32 %z
+}
+
+define i32 @t6(i32 %x) {
+; CHECK: mov r65.x___, l12
+; CHECK-NEXT: ishr r65.x___, r65.x, r1.x
+; CHECK-NEXT: mov r1.x___, r65.x
+
+ %z = ashr i32 -3, %x
+ ret i32 %z
+}
Added: llvm/branches/AMDILBackend/test/CodeGen/AMDIL/st.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/test/CodeGen/AMDIL/st.ll?rev=161996&view=auto
==============================================================================
--- llvm/branches/AMDILBackend/test/CodeGen/AMDIL/st.ll (added)
+++ llvm/branches/AMDILBackend/test/CodeGen/AMDIL/st.ll Wed Aug 15 17:39:43 2012
@@ -0,0 +1,964 @@
+; RUN: llc < %s -march=amdil | FileCheck %s
+
+ at array_i16 = global [10 x i16] zeroinitializer
+ at array_constant_i16 = addrspace(1) constant [10 x i16] zeroinitializer
+ at array_local_i16 = addrspace(2) global [10 x i16] zeroinitializer
+ at array_shared_i16 = addrspace(1) global [10 x i16] zeroinitializer
+ at array_i32 = global [10 x i32] zeroinitializer
+ at array_constant_i32 = addrspace(1) constant [10 x i32] zeroinitializer
+ at array_local_i32 = addrspace(2) global [10 x i32] zeroinitializer
+ at array_shared_i32 = addrspace(1) global [10 x i32] zeroinitializer
+ at array_i64 = global [10 x i64] zeroinitializer
+ at array_constant_i64 = addrspace(1) constant [10 x i64] zeroinitializer
+ at array_local_i64 = addrspace(2) global [10 x i64] zeroinitializer
+ at array_shared_i64 = addrspace(1) global [10 x i64] zeroinitializer
+ at array_float = global [10 x float] zeroinitializer
+ at array_constant_float = addrspace(1) constant [10 x float] zeroinitializer
+ at array_local_float = addrspace(2) global [10 x float] zeroinitializer
+ at array_shared_float = addrspace(1) global [10 x float] zeroinitializer
+ at array_double = global [10 x double] zeroinitializer
+ at array_constant_double = addrspace(1) constant [10 x double] zeroinitializer
+ at array_local_double = addrspace(2) global [10 x double] zeroinitializer
+ at array_shared_double = addrspace(1) global [10 x double] zeroinitializer
+
+define void @t1_u16(i16* %p, i16 %x) {
+
+ ; CHECK: t1_u16
+ ; CHECK: mov r1011, r1.y
+ ; CHECK-NEXT: mov r1010.x___, r1.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l12
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l13
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l12
+ ; CHECK-NEXT: iadd r1008, r1008.x, l14
+ ; CHECK-NEXT: ieq r1008, r1008, l15
+ ; CHECK-NEXT: mov r1002, x1[r1007.x]
+ ; CHECK-NEXT: cmov_logical r1002.x___, r1008.y, r1002.y, r1002.x
+ ; CHECK-NEXT: cmov_logical r1002.x___, r1008.z, r1002.z, r1002.x
+ ; CHECK-NEXT: cmov_logical r1002.x___, r1008.w, r1002.w, r1002.x
+ ; CHECK-NEXT: ishr r1003.x___, r1010.x, l16
+ ; CHECK-NEXT: iand r1003.x___, r1003.x, l16
+ ; CHECK-NEXT: ishr r1001.x___, r1002.x, l17
+ ; CHECK-NEXT: cmov_logical r1002.x___, r1003.x, r1002.x, r1011.x
+ ; CHECK-NEXT: cmov_logical r1001.x___, r1003.x, r1011.x, r1001.x
+ ; CHECK-NEXT: iand r1002.x___, r1002.x, l18
+ ; CHECK-NEXT: iand r1001.x___, r1001.x, l18
+ ; CHECK-NEXT: ishl r1001.x___, r1001.x, l17
+ ; CHECK-NEXT: ior r1011.x___, r1002.x, r1001.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l12
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l13
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l12
+ ; CHECK-NEXT: switch r1008.x
+ ; CHECK-NEXT: default
+ ; CHECK-NEXT: mov x1[r1007.x].x___, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 1
+ ; CHECK-NEXT: mov x1[r1007.x]._y__, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 2
+ ; CHECK-NEXT: mov x1[r1007.x].__z_, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 3
+ ; CHECK-NEXT: mov x1[r1007.x].___w, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: endswitch
+
+ store i16 %x, i16* %p
+ ret void
+}
+
+define void @t1_u32(i32* %p, i32 %x) {
+
+ ; CHECK: t1_u32
+ ; CHECK: mov r1011, r1.y
+ ; CHECK-NEXT: mov r1010.x___, r1.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l12
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l13
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l12
+ ; CHECK-NEXT: switch r1008.x
+ ; CHECK-NEXT: default
+ ; CHECK-NEXT: mov x1[r1007.x].x___, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 1
+ ; CHECK-NEXT: mov x1[r1007.x]._y__, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 2
+ ; CHECK-NEXT: mov x1[r1007.x].__z_, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 3
+ ; CHECK-NEXT: mov x1[r1007.x].___w, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: endswitch
+
+ store i32 %x, i32* %p
+ ret void
+}
+
+define void @t1_u64(i64* %p, i64 %x) {
+
+ ; CHECK: t1_u64
+ ; CHECK: mov r1011, r1.zwzw
+ ; CHECK-NEXT: mov r1010.x___, r1.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l12
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l13
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l13
+ ; CHECK-NEXT: switch r1008.x
+ ; CHECK-NEXT: default
+ ; CHECK-NEXT: mov x1[r1007.x].xy__, r1011.xyxy
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 1
+ ; CHECK-NEXT: mov x1[r1007.x].__zw, r1011.xyxy
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: endswitch
+
+ store i64 %x, i64* %p
+ ret void
+}
+
+define void @t1_f32(float* %p, float %x) {
+
+ ; CHECK: t1_f32
+ ; CHECK: mov r1011, r1.y
+ ; CHECK-NEXT: mov r1010.x___, r1.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l12
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l13
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l12
+ ; CHECK-NEXT: switch r1008.x
+ ; CHECK-NEXT: default
+ ; CHECK-NEXT: mov x1[r1007.x].x___, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 1
+ ; CHECK-NEXT: mov x1[r1007.x]._y__, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 2
+ ; CHECK-NEXT: mov x1[r1007.x].__z_, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 3
+ ; CHECK-NEXT: mov x1[r1007.x].___w, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: endswitch
+
+ store float %x, float* %p
+ ret void
+}
+
+define void @t1_f64(double* %p, double %x) {
+
+ ; CHECK: t1_f64
+ ; CHECK: mov r1011, r1.zwzw
+ ; CHECK-NEXT: mov r1010.x___, r1.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l12
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l13
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l13
+ ; CHECK-NEXT: switch r1008.x
+ ; CHECK-NEXT: default
+ ; CHECK-NEXT: mov x1[r1007.x].xy__, r1011.xyxy
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 1
+ ; CHECK-NEXT: mov x1[r1007.x].__zw, r1011.xyxy
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: endswitch
+
+ store double %x, double* %p
+ ret void
+}
+
+define void @t2_u16(i16* %p, i16 %x) {
+
+ ; CHECK: t2_u16
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: iadd r65.x___, r1.x, r65.x
+ ; CHECK-NEXT: mov r1011, r1.y
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l12
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l13
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l12
+ ; CHECK-NEXT: iadd r1008, r1008.x, l14
+ ; CHECK-NEXT: ieq r1008, r1008, l15
+ ; CHECK-NEXT: mov r1002, x1[r1007.x]
+ ; CHECK-NEXT: cmov_logical r1002.x___, r1008.y, r1002.y, r1002.x
+ ; CHECK-NEXT: cmov_logical r1002.x___, r1008.z, r1002.z, r1002.x
+ ; CHECK-NEXT: cmov_logical r1002.x___, r1008.w, r1002.w, r1002.x
+ ; CHECK-NEXT: ishr r1003.x___, r1010.x, l16
+ ; CHECK-NEXT: iand r1003.x___, r1003.x, l16
+ ; CHECK-NEXT: ishr r1001.x___, r1002.x, l17
+ ; CHECK-NEXT: cmov_logical r1002.x___, r1003.x, r1002.x, r1011.x
+ ; CHECK-NEXT: cmov_logical r1001.x___, r1003.x, r1011.x, r1001.x
+ ; CHECK-NEXT: iand r1002.x___, r1002.x, l18
+ ; CHECK-NEXT: iand r1001.x___, r1001.x, l18
+ ; CHECK-NEXT: ishl r1001.x___, r1001.x, l17
+ ; CHECK-NEXT: ior r1011.x___, r1002.x, r1001.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l12
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l13
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l12
+ ; CHECK-NEXT: switch r1008.x
+ ; CHECK-NEXT: default
+ ; CHECK-NEXT: mov x1[r1007.x].x___, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 1
+ ; CHECK-NEXT: mov x1[r1007.x]._y__, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 2
+ ; CHECK-NEXT: mov x1[r1007.x].__z_, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 3
+ ; CHECK-NEXT: mov x1[r1007.x].___w, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: endswitch
+
+ %i = getelementptr i16* %p, i32 1
+ store i16 %x, i16* %i
+ ret void
+}
+
+define void @t2_u32(i32* %p, i32 %x) {
+
+ ; CHECK: t2_u32
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: iadd r65.x___, r1.x, r65.x
+ ; CHECK-NEXT: mov r1011, r1.y
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l13
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l14
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l13
+ ; CHECK-NEXT: switch r1008.x
+ ; CHECK-NEXT: default
+ ; CHECK-NEXT: mov x1[r1007.x].x___, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 1
+ ; CHECK-NEXT: mov x1[r1007.x]._y__, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 2
+ ; CHECK-NEXT: mov x1[r1007.x].__z_, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 3
+ ; CHECK-NEXT: mov x1[r1007.x].___w, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: endswitch
+
+ %i = getelementptr i32* %p, i32 1
+ store i32 %x, i32* %i
+ ret void
+}
+
+define void @t2_u64(i64* %p, i64 %x) {
+
+ ; CHECK: t2_u64
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: iadd r65.x___, r1.x, r65.x
+ ; CHECK-NEXT: mov r1011, r1.zwzw
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l13
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l14
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l14
+ ; CHECK-NEXT: switch r1008.x
+ ; CHECK-NEXT: default
+ ; CHECK-NEXT: mov x1[r1007.x].xy__, r1011.xyxy
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 1
+ ; CHECK-NEXT: mov x1[r1007.x].__zw, r1011.xyxy
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: endswitch
+
+ %i = getelementptr i64* %p, i32 1
+ store i64 %x, i64* %i
+ ret void
+}
+
+define void @t2_f32(float* %p, float %x) {
+
+ ; CHECK: t2_f32
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: iadd r65.x___, r1.x, r65.x
+ ; CHECK-NEXT: mov r1011, r1.y
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l13
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l14
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l13
+ ; CHECK-NEXT: switch r1008.x
+ ; CHECK-NEXT: default
+ ; CHECK-NEXT: mov x1[r1007.x].x___, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 1
+ ; CHECK-NEXT: mov x1[r1007.x]._y__, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 2
+ ; CHECK-NEXT: mov x1[r1007.x].__z_, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 3
+ ; CHECK-NEXT: mov x1[r1007.x].___w, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: endswitch
+
+ %i = getelementptr float* %p, i32 1
+ store float %x, float* %i
+ ret void
+}
+
+define void @t2_f64(double* %p, double %x) {
+
+ ; CHECK: t2_f64
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: iadd r65.x___, r1.x, r65.x
+ ; CHECK-NEXT: mov r1011, r1.zwzw
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l13
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l14
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l14
+ ; CHECK-NEXT: switch r1008.x
+ ; CHECK-NEXT: default
+ ; CHECK-NEXT: mov x1[r1007.x].xy__, r1011.xyxy
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 1
+ ; CHECK-NEXT: mov x1[r1007.x].__zw, r1011.xyxy
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: endswitch
+
+ %i = getelementptr double* %p, i32 1
+ store double %x, double* %i
+ ret void
+}
+
+define void @t3_u16(i16* %p, i32 %q, i16 %x) {
+
+ ; CHECK: t3_u16
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: ishl r65.x___, r1.y, r65.x
+ ; CHECK-NEXT: iadd r65.x___, r1.x, r65.x
+ ; CHECK-NEXT: mov r1011, r1.z
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l13
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l14
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l13
+ ; CHECK-NEXT: iadd r1008, r1008.x, l15
+ ; CHECK-NEXT: ieq r1008, r1008, l16
+ ; CHECK-NEXT: mov r1002, x1[r1007.x]
+ ; CHECK-NEXT: cmov_logical r1002.x___, r1008.y, r1002.y, r1002.x
+ ; CHECK-NEXT: cmov_logical r1002.x___, r1008.z, r1002.z, r1002.x
+ ; CHECK-NEXT: cmov_logical r1002.x___, r1008.w, r1002.w, r1002.x
+ ; CHECK-NEXT: ishr r1003.x___, r1010.x, l12
+ ; CHECK-NEXT: iand r1003.x___, r1003.x, l12
+ ; CHECK-NEXT: ishr r1001.x___, r1002.x, l17
+ ; CHECK-NEXT: cmov_logical r1002.x___, r1003.x, r1002.x, r1011.x
+ ; CHECK-NEXT: cmov_logical r1001.x___, r1003.x, r1011.x, r1001.x
+ ; CHECK-NEXT: iand r1002.x___, r1002.x, l18
+ ; CHECK-NEXT: iand r1001.x___, r1001.x, l18
+ ; CHECK-NEXT: ishl r1001.x___, r1001.x, l17
+ ; CHECK-NEXT: ior r1011.x___, r1002.x, r1001.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l13
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l14
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l13
+ ; CHECK-NEXT: switch r1008.x
+ ; CHECK-NEXT: default
+ ; CHECK-NEXT: mov x1[r1007.x].x___, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 1
+ ; CHECK-NEXT: mov x1[r1007.x]._y__, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 2
+ ; CHECK-NEXT: mov x1[r1007.x].__z_, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 3
+ ; CHECK-NEXT: mov x1[r1007.x].___w, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: endswitch
+
+ %i = getelementptr i16* %p, i32 %q
+ store i16 %x, i16* %i
+ ret void
+}
+
+define void @t3_u32(i32* %p, i32 %q, i32 %x) {
+
+ ; CHECK: t3_u32
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: ishl r65.x___, r1.y, r65.x
+ ; CHECK-NEXT: iadd r65.x___, r1.x, r65.x
+ ; CHECK-NEXT: mov r1011, r1.z
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l12
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l13
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l12
+ ; CHECK-NEXT: switch r1008.x
+ ; CHECK-NEXT: default
+ ; CHECK-NEXT: mov x1[r1007.x].x___, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 1
+ ; CHECK-NEXT: mov x1[r1007.x]._y__, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 2
+ ; CHECK-NEXT: mov x1[r1007.x].__z_, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 3
+ ; CHECK-NEXT: mov x1[r1007.x].___w, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: endswitch
+
+ %i = getelementptr i32* %p, i32 %q
+ store i32 %x, i32* %i
+ ret void
+}
+
+define void @t3_u64(i64* %p, i32 %q, i64 %x) {
+
+ ; CHECK: t3_u64
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: ishl r65.x___, r1.y, r65.x
+ ; CHECK-NEXT: iadd r65.x___, r1.x, r65.x
+ ; CHECK-NEXT: mov r1011, r1.zwzw
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l12
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l13
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l13
+ ; CHECK-NEXT: switch r1008.x
+ ; CHECK-NEXT: default
+ ; CHECK-NEXT: mov x1[r1007.x].xy__, r1011.xyxy
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 1
+ ; CHECK-NEXT: mov x1[r1007.x].__zw, r1011.xyxy
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: endswitch
+
+ %i = getelementptr i64* %p, i32 %q
+ store i64 %x, i64* %i
+ ret void
+}
+
+define void @t3_f32(float* %p, i32 %q, float %x) {
+
+ ; CHECK: t3_f32
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: ishl r65.x___, r1.y, r65.x
+ ; CHECK-NEXT: iadd r65.x___, r1.x, r65.x
+ ; CHECK-NEXT: mov r1011, r1.z
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l12
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l13
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l12
+ ; CHECK-NEXT: switch r1008.x
+ ; CHECK-NEXT: default
+ ; CHECK-NEXT: mov x1[r1007.x].x___, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 1
+ ; CHECK-NEXT: mov x1[r1007.x]._y__, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 2
+ ; CHECK-NEXT: mov x1[r1007.x].__z_, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 3
+ ; CHECK-NEXT: mov x1[r1007.x].___w, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: endswitch
+
+ %i = getelementptr float* %p, i32 %q
+ store float %x, float* %i
+ ret void
+}
+
+define void @t3_f64(double* %p, i32 %q, double %x) {
+
+ ; CHECK: t3_f64
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: ishl r65.x___, r1.y, r65.x
+ ; CHECK-NEXT: iadd r65.x___, r1.x, r65.x
+ ; CHECK-NEXT: mov r1011, r1.zwzw
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l12
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l13
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l13
+ ; CHECK-NEXT: switch r1008.x
+ ; CHECK-NEXT: default
+ ; CHECK-NEXT: mov x1[r1007.x].xy__, r1011.xyxy
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 1
+ ; CHECK-NEXT: mov x1[r1007.x].__zw, r1011.xyxy
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: endswitch
+
+ %i = getelementptr double* %p, i32 %q
+ store double %x, double* %i
+ ret void
+}
+
+define void @t4_global_u16(i16 %x) {
+
+ ; CHECK: t4_global_u16
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r1011, r1.x
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l13
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l14
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l13
+ ; CHECK-NEXT: iadd r1008, r1008.x, l15
+ ; CHECK-NEXT: ieq r1008, r1008, l16
+ ; CHECK-NEXT: mov r1002, x1[r1007.x]
+ ; CHECK-NEXT: cmov_logical r1002.x___, r1008.y, r1002.y, r1002.x
+ ; CHECK-NEXT: cmov_logical r1002.x___, r1008.z, r1002.z, r1002.x
+ ; CHECK-NEXT: cmov_logical r1002.x___, r1008.w, r1002.w, r1002.x
+ ; CHECK-NEXT: ishr r1003.x___, r1010.x, l17
+ ; CHECK-NEXT: iand r1003.x___, r1003.x, l17
+ ; CHECK-NEXT: ishr r1001.x___, r1002.x, l18
+ ; CHECK-NEXT: cmov_logical r1002.x___, r1003.x, r1002.x, r1011.x
+ ; CHECK-NEXT: cmov_logical r1001.x___, r1003.x, r1011.x, r1001.x
+ ; CHECK-NEXT: iand r1002.x___, r1002.x, l19
+ ; CHECK-NEXT: iand r1001.x___, r1001.x, l19
+ ; CHECK-NEXT: ishl r1001.x___, r1001.x, l18
+ ; CHECK-NEXT: ior r1011.x___, r1002.x, r1001.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l13
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l14
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l13
+ ; CHECK-NEXT: switch r1008.x
+ ; CHECK-NEXT: default
+ ; CHECK-NEXT: mov x1[r1007.x].x___, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 1
+ ; CHECK-NEXT: mov x1[r1007.x]._y__, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 2
+ ; CHECK-NEXT: mov x1[r1007.x].__z_, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 3
+ ; CHECK-NEXT: mov x1[r1007.x].___w, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: endswitch
+
+ %i = getelementptr [10 x i16]* @array_i16, i16 0, i16 0
+ store i16 %x, i16* %i
+ ret void
+}
+
+define void @t4_global_u32(i32 %x) {
+
+ ; CHECK: t4_global_u32
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r1011, r1.x
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l13
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l14
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l13
+ ; CHECK-NEXT: switch r1008.x
+ ; CHECK-NEXT: default
+ ; CHECK-NEXT: mov x1[r1007.x].x___, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 1
+ ; CHECK-NEXT: mov x1[r1007.x]._y__, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 2
+ ; CHECK-NEXT: mov x1[r1007.x].__z_, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 3
+ ; CHECK-NEXT: mov x1[r1007.x].___w, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: endswitch
+
+ %i = getelementptr [10 x i32]* @array_i32, i32 0, i32 0
+ store i32 %x, i32* %i
+ ret void
+}
+
+define void @t4_global_u64(i64 %x) {
+
+ ; CHECK: t4_global_u64
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r1011, r1.xyxy
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l13
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l14
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l14
+ ; CHECK-NEXT: switch r1008.x
+ ; CHECK-NEXT: default
+ ; CHECK-NEXT: mov x1[r1007.x].xy__, r1011.xyxy
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 1
+ ; CHECK-NEXT: mov x1[r1007.x].__zw, r1011.xyxy
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: endswitch
+
+ %i = getelementptr [10 x i64]* @array_i64, i32 0, i32 0
+ store i64 %x, i64* %i
+ ret void
+}
+
+define void @t4_global_f32(float %x) {
+
+ ; CHECK: t4_global_f32
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r1011, r1.x
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l13
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l14
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l13
+ ; CHECK-NEXT: switch r1008.x
+ ; CHECK-NEXT: default
+ ; CHECK-NEXT: mov x1[r1007.x].x___, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 1
+ ; CHECK-NEXT: mov x1[r1007.x]._y__, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 2
+ ; CHECK-NEXT: mov x1[r1007.x].__z_, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 3
+ ; CHECK-NEXT: mov x1[r1007.x].___w, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: endswitch
+
+ %i = getelementptr [10 x float]* @array_float, i32 0, i32 0
+ store float %x, float* %i
+ ret void
+}
+
+define void @t4_global_f64(double %x) {
+
+ ; CHECK: t4_global_f64
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r1011, r1.xyxy
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l13
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l14
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l14
+ ; CHECK-NEXT: switch r1008.x
+ ; CHECK-NEXT: default
+ ; CHECK-NEXT: mov x1[r1007.x].xy__, r1011.xyxy
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 1
+ ; CHECK-NEXT: mov x1[r1007.x].__zw, r1011.xyxy
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: endswitch
+
+ %i = getelementptr [10 x double]* @array_double, i32 0, i32 0
+ store double %x, double* %i
+ ret void
+}
+
+define void @t4_local_u16(i16 %x) {
+
+ ; CHECK: t4_local_u16
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r1011, r1.x
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l13
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l14
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l13
+ ; CHECK-NEXT: iadd r1008, r1008.x, l15
+ ; CHECK-NEXT: ieq r1008, r1008, l16
+ ; CHECK-NEXT: mov r1002, x1[r1007.x]
+ ; CHECK-NEXT: cmov_logical r1002.x___, r1008.y, r1002.y, r1002.x
+ ; CHECK-NEXT: cmov_logical r1002.x___, r1008.z, r1002.z, r1002.x
+ ; CHECK-NEXT: cmov_logical r1002.x___, r1008.w, r1002.w, r1002.x
+ ; CHECK-NEXT: ishr r1003.x___, r1010.x, l17
+ ; CHECK-NEXT: iand r1003.x___, r1003.x, l17
+ ; CHECK-NEXT: ishr r1001.x___, r1002.x, l18
+ ; CHECK-NEXT: cmov_logical r1002.x___, r1003.x, r1002.x, r1011.x
+ ; CHECK-NEXT: cmov_logical r1001.x___, r1003.x, r1011.x, r1001.x
+ ; CHECK-NEXT: iand r1002.x___, r1002.x, l19
+ ; CHECK-NEXT: iand r1001.x___, r1001.x, l19
+ ; CHECK-NEXT: ishl r1001.x___, r1001.x, l18
+ ; CHECK-NEXT: ior r1011.x___, r1002.x, r1001.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l13
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l14
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l13
+ ; CHECK-NEXT: switch r1008.x
+ ; CHECK-NEXT: default
+ ; CHECK-NEXT: mov x1[r1007.x].x___, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 1
+ ; CHECK-NEXT: mov x1[r1007.x]._y__, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 2
+ ; CHECK-NEXT: mov x1[r1007.x].__z_, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 3
+ ; CHECK-NEXT: mov x1[r1007.x].___w, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: endswitch
+
+ %i = getelementptr [10 x i16] addrspace(2)* @array_local_i16, i32 0, i32 0
+ store i16 %x, i16 addrspace(2)* %i
+ ret void
+}
+
+define void @t4_local_u32(i32 %x) {
+
+ ; CHECK: t4_local_u32
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r1011, r1.x
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l13
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l14
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l13
+ ; CHECK-NEXT: switch r1008.x
+ ; CHECK-NEXT: default
+ ; CHECK-NEXT: mov x1[r1007.x].x___, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 1
+ ; CHECK-NEXT: mov x1[r1007.x]._y__, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 2
+ ; CHECK-NEXT: mov x1[r1007.x].__z_, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 3
+ ; CHECK-NEXT: mov x1[r1007.x].___w, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: endswitch
+
+ %i = getelementptr [10 x i32] addrspace(2)* @array_local_i32, i32 0, i32 0
+ store i32 %x, i32 addrspace(2)* %i
+ ret void
+}
+
+define void @t4_local_u64(i64 %x) {
+
+ ; CHECK: t4_local_u64
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r1011, r1.xyxy
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l13
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l14
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l14
+ ; CHECK-NEXT: switch r1008.x
+ ; CHECK-NEXT: default
+ ; CHECK-NEXT: mov x1[r1007.x].xy__, r1011.xyxy
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 1
+ ; CHECK-NEXT: mov x1[r1007.x].__zw, r1011.xyxy
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: endswitch
+
+ %i = getelementptr [10 x i64] addrspace(2)* @array_local_i64, i32 0, i32 0
+ store i64 %x, i64 addrspace(2)* %i
+ ret void
+}
+
+define void @t4_local_f32(float %x) {
+
+ ; CHECK: t4_local_f32
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r1011, r1.x
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l13
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l14
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l13
+ ; CHECK-NEXT: switch r1008.x
+ ; CHECK-NEXT: default
+ ; CHECK-NEXT: mov x1[r1007.x].x___, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 1
+ ; CHECK-NEXT: mov x1[r1007.x]._y__, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 2
+ ; CHECK-NEXT: mov x1[r1007.x].__z_, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 3
+ ; CHECK-NEXT: mov x1[r1007.x].___w, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: endswitch
+
+ %i = getelementptr [10 x float] addrspace(2)* @array_local_float, i32 0, i32 0
+ store float %x, float addrspace(2)* %i
+ ret void
+}
+
+define void @t4_local_f64(double %x) {
+
+ ; CHECK: t4_local_f64
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r1011, r1.xyxy
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l13
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l14
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l14
+ ; CHECK-NEXT: switch r1008.x
+ ; CHECK-NEXT: default
+ ; CHECK-NEXT: mov x1[r1007.x].xy__, r1011.xyxy
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 1
+ ; CHECK-NEXT: mov x1[r1007.x].__zw, r1011.xyxy
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: endswitch
+
+ %i = getelementptr [10 x double] addrspace(2)* @array_local_double, i32 0, i32 0
+ store double %x, double addrspace(2)* %i
+ ret void
+}
+
+define void @t5_u16(i16 %x) {
+
+ ; CHECK: t5_u16
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r66.x___, l13
+ ; CHECK-NEXT: iadd r65.x___, r66.x, r65.x
+ ; CHECK-NEXT: mov r1011, r1.x
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l12
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l14
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l12
+ ; CHECK-NEXT: iadd r1008, r1008.x, l15
+ ; CHECK-NEXT: ieq r1008, r1008, l16
+ ; CHECK-NEXT: mov r1002, x1[r1007.x]
+ ; CHECK-NEXT: cmov_logical r1002.x___, r1008.y, r1002.y, r1002.x
+ ; CHECK-NEXT: cmov_logical r1002.x___, r1008.z, r1002.z, r1002.x
+ ; CHECK-NEXT: cmov_logical r1002.x___, r1008.w, r1002.w, r1002.x
+ ; CHECK-NEXT: ishr r1003.x___, r1010.x, l17
+ ; CHECK-NEXT: iand r1003.x___, r1003.x, l17
+ ; CHECK-NEXT: ishr r1001.x___, r1002.x, l18
+ ; CHECK-NEXT: cmov_logical r1002.x___, r1003.x, r1002.x, r1011.x
+ ; CHECK-NEXT: cmov_logical r1001.x___, r1003.x, r1011.x, r1001.x
+ ; CHECK-NEXT: iand r1002.x___, r1002.x, l19
+ ; CHECK-NEXT: iand r1001.x___, r1001.x, l19
+ ; CHECK-NEXT: ishl r1001.x___, r1001.x, l18
+ ; CHECK-NEXT: ior r1011.x___, r1002.x, r1001.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l12
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l14
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l12
+ ; CHECK-NEXT: switch r1008.x
+ ; CHECK-NEXT: default
+ ; CHECK-NEXT: mov x1[r1007.x].x___, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 1
+ ; CHECK-NEXT: mov x1[r1007.x]._y__, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 2
+ ; CHECK-NEXT: mov x1[r1007.x].__z_, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 3
+ ; CHECK-NEXT: mov x1[r1007.x].___w, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: endswitch
+
+ %i = getelementptr [10 x i16]* @array_i16, i32 0, i32 1
+ store i16 %x, i16* %i
+ ret void
+}
+
+define void @t5_u32(i32 %x) {
+
+ ; CHECK: t5_u32
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r66.x___, l13
+ ; CHECK-NEXT: iadd r65.x___, r66.x, r65.x
+ ; CHECK-NEXT: mov r1011, r1.x
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l14
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l15
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l14
+ ; CHECK-NEXT: switch r1008.x
+ ; CHECK-NEXT: default
+ ; CHECK-NEXT: mov x1[r1007.x].x___, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 1
+ ; CHECK-NEXT: mov x1[r1007.x]._y__, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 2
+ ; CHECK-NEXT: mov x1[r1007.x].__z_, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 3
+ ; CHECK-NEXT: mov x1[r1007.x].___w, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: endswitch
+
+ %i = getelementptr [10 x i32]* @array_i32, i32 0, i32 1
+ store i32 %x, i32* %i
+ ret void
+}
+
+define void @t5_u64(i64 %x) {
+
+ ; CHECK: t5_u64
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r66.x___, l13
+ ; CHECK-NEXT: iadd r65.x___, r66.x, r65.x
+ ; CHECK-NEXT: mov r1011, r1.xyxy
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l14
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l15
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l15
+ ; CHECK-NEXT: switch r1008.x
+ ; CHECK-NEXT: default
+ ; CHECK-NEXT: mov x1[r1007.x].xy__, r1011.xyxy
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 1
+ ; CHECK-NEXT: mov x1[r1007.x].__zw, r1011.xyxy
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: endswitch
+
+ %i = getelementptr [10 x i64]* @array_i64, i32 0, i32 1
+ store i64 %x, i64* %i
+ ret void
+}
+
+define void @t5_f32(float %x) {
+
+ ; CHECK: t5_f32
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r66.x___, l13
+ ; CHECK-NEXT: iadd r65.x___, r66.x, r65.x
+ ; CHECK-NEXT: mov r1011, r1.x
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l14
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l15
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l14
+ ; CHECK-NEXT: switch r1008.x
+ ; CHECK-NEXT: default
+ ; CHECK-NEXT: mov x1[r1007.x].x___, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 1
+ ; CHECK-NEXT: mov x1[r1007.x]._y__, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 2
+ ; CHECK-NEXT: mov x1[r1007.x].__z_, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 3
+ ; CHECK-NEXT: mov x1[r1007.x].___w, r1011.x
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: endswitch
+
+ %i = getelementptr [10 x float]* @array_float, i32 0, i32 1
+ store float %x, float* %i
+ ret void
+}
+
+define void @t5_f64(double %x) {
+
+ ; CHECK: t5_f64
+ ; CHECK: mov r65.x___, l12
+ ; CHECK-NEXT: mov r66.x___, l13
+ ; CHECK-NEXT: iadd r65.x___, r66.x, r65.x
+ ; CHECK-NEXT: mov r1011, r1.xyxy
+ ; CHECK-NEXT: mov r1010.x___, r65.x
+ ; CHECK-NEXT: ishr r1007.x___, r1010.x, l14
+ ; CHECK-NEXT: iand r1008.x___, r1007.x, l15
+ ; CHECK-NEXT: ishr r1007.x___, r1007.x, l15
+ ; CHECK-NEXT: switch r1008.x
+ ; CHECK-NEXT: default
+ ; CHECK-NEXT: mov x1[r1007.x].xy__, r1011.xyxy
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: case 1
+ ; CHECK-NEXT: mov x1[r1007.x].__zw, r1011.xyxy
+ ; CHECK-NEXT: break
+ ; CHECK-NEXT: endswitch
+
+ %i = getelementptr [10 x double]* @array_double, i32 0, i32 1
+ store double %x, double* %i
+ ret void
+}
+
+; CHECK: .global at array_i16:496
+; CHECK: .global at array_constant_i16
+; CHECK: .global at array_local_i16:256
+; CHECK: .global at array_shared_i16
+; CHECK: .global at array_i32:448
+; CHECK: .global at array_constant_i32
+; CHECK: .global at array_local_i32:208
+; CHECK: .global at array_shared_i32
+; CHECK: .global at array_i64:0
+; CHECK: .global at array_constant_i64
+; CHECK: .global at array_local_i64:368
+; CHECK: .global at array_shared_i64
+; CHECK: .global at array_float:160
+; CHECK: .global at array_constant_float
+; CHECK: .global at array_local_float:528
+; CHECK: .global at array_shared_float
+; CHECK: .global at array_double:288
+; CHECK: .global at array_constant_double
+; CHECK: .global at array_local_double:80
+; CHECK: .global at array_shared_double
Added: llvm/branches/AMDILBackend/test/CodeGen/AMDIL/sub.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/test/CodeGen/AMDIL/sub.ll?rev=161996&view=auto
==============================================================================
--- llvm/branches/AMDILBackend/test/CodeGen/AMDIL/sub.ll (added)
+++ llvm/branches/AMDILBackend/test/CodeGen/AMDIL/sub.ll Wed Aug 15 17:39:43 2012
@@ -0,0 +1,91 @@
+; RUN: llc < %s -march=amdil | FileCheck %s
+
+define i16 @t1_u16(i16 %x, i16 %y) {
+; CHECK: mov r66.x___, r1.y
+; CHECK-NEXT: mov r65.x___, l12
+; CHECK-NEXT: ishl r66.x___, r66.x, r65.x
+; CHECK-NEXT: ishr r65.x___, r66.x, r65.x
+; CHECK-NEXT: mov r65.x___, r65.x
+; CHECK-NEXT: inegate r65.x___, r65.x
+; CHECK-NEXT: iadd r65.x___, r1.x, r65.x
+; CHECK-NEXT: mov r1.x___, r65.x
+; CHECK-NEXT: ret_dyn
+; CHECK-NEXT: ret
+
+ %z = sub i16 %x, %y
+ ret i16 %z
+}
+
+define i32 @t1_u32(i32 %x, i32 %y) {
+; CHECK: inegate r65.x___, r1.y
+; CHECK-NEXT: iadd r65.x___, r1.x, r65.x
+; CHECK-NEXT: mov r1.x___, r65.x
+; CHECK-NEXT: ret_dyn
+; CHECK-NEXT: ret
+
+ %z = sub i32 %x, %y
+ ret i32 %z
+}
+
+define float @t1_f32(float %x, float %y) {
+; CHECK: sub r65.x___, r1.x, r1.y
+; CHECK-NEXT: mov r1.x___, r65.x
+; CHECK-NEXT: ret_dyn
+; CHECK-NEXT: ret
+
+ %z = fsub float %x, %y
+ ret float %z
+}
+
+define i16 @t2_u16(i16 %x) {
+; CHECK: mov r65.x___, l12
+; CHECK-NEXT: iadd r65.x___, r1.x, r65.x
+; CHECK-NEXT: mov r1.x___, r65.x
+; CHECK-NEXT: ret_dyn
+; CHECK-NEXT: ret
+
+ %z = sub i16 %x, 1
+ ret i16 %z
+}
+
+define i32 @t2_u32(i32 %x) {
+; CHECK: mov r65.x___, l12
+; CHECK-NEXT: iadd r65.x___, r1.x, r65.x
+; CHECK-NEXT: mov r1.x___, r65.x
+; CHECK-NEXT: ret_dyn
+; CHECK-NEXT: ret
+
+ %z = sub i32 %x, 1
+ ret i32 %z
+}
+
+define i64 @t2_u64(i64 %x) {
+; CHECK: mov r66.xy__, l12
+; CHECK-NEXT: mov r65.x___, r66.y000
+; CHECK-NEXT: mov r67.x___, r1.y000
+; CHECK-NEXT: iadd r65.x___, r67.x, r65.x
+; CHECK-NEXT: mov r67.x___, r66.x000
+; CHECK-NEXT: mov r66.x___, r1.x000
+; CHECK-NEXT: iadd r66.x___, r66.x, r67.x
+; CHECK-NEXT: ult r67.x___, r66.x, r67.x
+; CHECK-NEXT: inegate r67.x___, r67.x
+; CHECK-NEXT: iadd r65.x___, r65.x, r67.x
+; CHECK-NEXT: iadd r65.xy__, r66.x000, r65.0x00
+; CHECK-NEXT: mov r1.xy__, r65.xyxy
+; CHECK-NEXT: ret_dyn
+; CHECK-NEXT: ret
+
+ %z = sub i64 %x, 1
+ ret i64 %z
+}
+
+define float @t2_f32(float %x) {
+; CHECK: mov r65.x___, l12
+; CHECK-NEXT: add r65.x___, r1.x, r65.x
+; CHECK-NEXT: mov r1.x___, r65.x
+; CHECK-NEXT: ret_dyn
+; CHECK-NEXT: ret
+
+ %z = fsub float %x, 1.0
+ ret float %z
+}
Added: llvm/branches/AMDILBackend/test/CodeGen/AMDIL/sub.s
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/test/CodeGen/AMDIL/sub.s?rev=161996&view=auto
==============================================================================
--- llvm/branches/AMDILBackend/test/CodeGen/AMDIL/sub.s (added)
+++ llvm/branches/AMDILBackend/test/CodeGen/AMDIL/sub.s Wed Aug 15 17:39:43 2012
@@ -0,0 +1,137 @@
+il_cs_2_0
+dcl_cb cb0[15] ; Constant buffer that holds ABI data
+dcl_literal l0, 0x00000004, 0x00000001, 0x00000002, 0x00000003
+dcl_literal l1, 0x00FFFFFF, 0xFFFFFFFF, 0xFFFFFFFE, 0xFFFFFFFD
+dcl_literal l2, 0x0000FFFF, 0xFFFFFFFE, 0x000000FF, 0xFFFFFFFC
+dcl_literal l3, 0x00000018, 0x00000010, 0x00000008, 0xFFFFFFFF
+dcl_literal l4, 0xFFFFFF00, 0xFFFF0000, 0xFF00FFFF, 0xFFFF00FF
+dcl_literal l5, 0x00000000, 0x00000004, 0x00000008, 0x0000000C
+dcl_literal l6, 0x00000020, 0x00000020, 0x00000020, 0x00000020
+dcl_literal l7, 0x00000018, 0x0000001F, 0x00000010, 0x0000001F
+dcl_literal l8, 0x80000000, 0x80000000, 0x80000000, 0x80000000
+;$$$$$$$$$$
+endmain
+;DEBUGSTART
+ .file "/home/voliveir/work/llvm-branch-2/test/CodeGen/AMDIL/sub.ll"
+ .text
+.global at t1_u16
+;DEBUGEND
+func 1024 ; t1_u16 ; @t1_u16
+; BB#0:
+ mov r66.x___, r1.y
+ mov r65.x___, l12
+ ishl r66.x___, r66.x, r65.x
+ ishr r65.x___, r66.x, r65.x
+ mov r65.x___, r65.x
+ inegate r65.x___, r65.x
+ iadd r65.x___, r1.x, r65.x
+ mov r1.x___, r65.x
+ ret_dyn
+ret
+endfunc ; t1_u16
+;ARGSTART:t1_u16
+;uniqueid:1024
+;ARGEND:t1_u16
+;DEBUGSTART
+
+.global at t1_u32
+;DEBUGEND
+func 1025 ; t1_u32 ; @t1_u32
+; BB#0:
+ inegate r65.x___, r1.y
+ iadd r65.x___, r1.x, r65.x
+ mov r1.x___, r65.x
+ ret_dyn
+ret
+endfunc ; t1_u32
+;ARGSTART:t1_u32
+;uniqueid:1025
+;ARGEND:t1_u32
+;DEBUGSTART
+
+.global at t1_f32
+;DEBUGEND
+func 1026 ; t1_f32 ; @t1_f32
+; BB#0:
+ sub r65.x___, r1.x, r1.y
+ mov r1.x___, r65.x
+ ret_dyn
+ret
+endfunc ; t1_f32
+;ARGSTART:t1_f32
+;uniqueid:1026
+;ARGEND:t1_f32
+;DEBUGSTART
+
+.global at t2_u16
+;DEBUGEND
+func 1027 ; t2_u16 ; @t2_u16
+; BB#0:
+ mov r65.x___, l12
+ iadd r65.x___, r1.x, r65.x
+ mov r1.x___, r65.x
+ ret_dyn
+ret
+endfunc ; t2_u16
+;ARGSTART:t2_u16
+;uniqueid:1027
+;ARGEND:t2_u16
+;DEBUGSTART
+
+.global at t2_u32
+;DEBUGEND
+func 1028 ; t2_u32 ; @t2_u32
+; BB#0:
+ mov r65.x___, l12
+ iadd r65.x___, r1.x, r65.x
+ mov r1.x___, r65.x
+ ret_dyn
+ret
+endfunc ; t2_u32
+;ARGSTART:t2_u32
+;uniqueid:1028
+;ARGEND:t2_u32
+;DEBUGSTART
+
+.global at t2_u64
+;DEBUGEND
+func 1029 ; t2_u64 ; @t2_u64
+; BB#0:
+ mov r66.xy__, l12
+ mov r65.x___, r66.y000
+ mov r67.x___, r1.y000
+ iadd r65.x___, r67.x, r65.x
+ mov r67.x___, r66.x000
+ mov r66.x___, r1.x000
+ iadd r66.x___, r66.x, r67.x
+ ult r67.x___, r66.x, r67.x
+ inegate r67.x___, r67.x
+ iadd r65.x___, r65.x, r67.x
+ iadd r65.xy__, r66.x000, r65.0x00
+ mov r1.xy__, r65.xyxy
+ ret_dyn
+ret
+endfunc ; t2_u64
+;ARGSTART:t2_u64
+;uniqueid:1029
+;ARGEND:t2_u64
+;DEBUGSTART
+
+.global at t2_f32
+;DEBUGEND
+func 1030 ; t2_f32 ; @t2_f32
+; BB#0:
+ mov r65.x___, l12
+ add r65.x___, r1.x, r65.x
+ mov r1.x___, r65.x
+ ret_dyn
+ret
+endfunc ; t2_f32
+;ARGSTART:t2_f32
+;uniqueid:1030
+;ARGEND:t2_f32
+;DEBUGSTART
+
+;DEBUGEND
+
+end
Added: llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_barts.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_barts.ll?rev=161996&view=auto
==============================================================================
--- llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_barts.ll (added)
+++ llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_barts.ll Wed Aug 15 17:39:43 2012
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=amdil -mcpu=barts | FileCheck %s
+; CHECK: ;device:barts
+; ModuleID = '_temp_0_cypress_optimized.bc'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:32:32-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-a0:0:64"
+target triple = "amdil-pc-amdopencl"
+
+%0 = type { i8*, i8*, i8*, i8*, i32 }
+
+ at sgv = internal addrspace(2) constant [1 x i8] zeroinitializer
+ at fgv = internal addrspace(2) constant [1 x i8] zeroinitializer
+ at lvgv = internal constant [0 x i8*] zeroinitializer
+ at llvm.global.annotations = appending global [1 x %0] [%0 { i8* bitcast (void ()* @__OpenCL_foo_kernel to i8*), i8* bitcast ([1 x i8] addrspace(2)* @sgv to i8*), i8* bitcast ([1 x i8] addrspace(2)* @fgv to i8*), i8* bitcast ([0 x i8*]* @lvgv to i8*), i32 0 }], section "llvm.metadata"
+
+define void @__OpenCL_foo_kernel() nounwind readnone {
+entry:
+ ret void
+}
Added: llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_caicos.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_caicos.ll?rev=161996&view=auto
==============================================================================
--- llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_caicos.ll (added)
+++ llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_caicos.ll Wed Aug 15 17:39:43 2012
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=amdil -mcpu=caicos | FileCheck %s
+; CHECK: ;device:caicos
+; ModuleID = '_temp_0_cypress_optimized.bc'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:32:32-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-a0:0:64"
+target triple = "amdil-pc-amdopencl"
+
+%0 = type { i8*, i8*, i8*, i8*, i32 }
+
+ at sgv = internal addrspace(2) constant [1 x i8] zeroinitializer
+ at fgv = internal addrspace(2) constant [1 x i8] zeroinitializer
+ at lvgv = internal constant [0 x i8*] zeroinitializer
+ at llvm.global.annotations = appending global [1 x %0] [%0 { i8* bitcast (void ()* @__OpenCL_foo_kernel to i8*), i8* bitcast ([1 x i8] addrspace(2)* @sgv to i8*), i8* bitcast ([1 x i8] addrspace(2)* @fgv to i8*), i8* bitcast ([0 x i8*]* @lvgv to i8*), i32 0 }], section "llvm.metadata"
+
+define void @__OpenCL_foo_kernel() nounwind readnone {
+entry:
+ ret void
+}
Added: llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_cayman.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_cayman.ll?rev=161996&view=auto
==============================================================================
--- llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_cayman.ll (added)
+++ llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_cayman.ll Wed Aug 15 17:39:43 2012
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=amdil -mcpu=cayman | FileCheck %s
+; CHECK: ;device:cayman
+; ModuleID = '_temp_0_cypress_optimized.bc'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:32:32-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-a0:0:64"
+target triple = "amdil-pc-amdopencl"
+
+%0 = type { i8*, i8*, i8*, i8*, i32 }
+
+ at sgv = internal addrspace(2) constant [1 x i8] zeroinitializer
+ at fgv = internal addrspace(2) constant [1 x i8] zeroinitializer
+ at lvgv = internal constant [0 x i8*] zeroinitializer
+ at llvm.global.annotations = appending global [1 x %0] [%0 { i8* bitcast (void ()* @__OpenCL_foo_kernel to i8*), i8* bitcast ([1 x i8] addrspace(2)* @sgv to i8*), i8* bitcast ([1 x i8] addrspace(2)* @fgv to i8*), i8* bitcast ([0 x i8*]* @lvgv to i8*), i32 0 }], section "llvm.metadata"
+
+define void @__OpenCL_foo_kernel() nounwind readnone {
+entry:
+ ret void
+}
Added: llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_cedar.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_cedar.ll?rev=161996&view=auto
==============================================================================
--- llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_cedar.ll (added)
+++ llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_cedar.ll Wed Aug 15 17:39:43 2012
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=amdil -mcpu=cedar | FileCheck %s
+; CHECK: ;device:cedar
+; ModuleID = '_temp_0_cypress_optimized.bc'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:32:32-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-a0:0:64"
+target triple = "amdil-pc-amdopencl"
+
+%0 = type { i8*, i8*, i8*, i8*, i32 }
+
+ at sgv = internal addrspace(2) constant [1 x i8] zeroinitializer
+ at fgv = internal addrspace(2) constant [1 x i8] zeroinitializer
+ at lvgv = internal constant [0 x i8*] zeroinitializer
+ at llvm.global.annotations = appending global [1 x %0] [%0 { i8* bitcast (void ()* @__OpenCL_foo_kernel to i8*), i8* bitcast ([1 x i8] addrspace(2)* @sgv to i8*), i8* bitcast ([1 x i8] addrspace(2)* @fgv to i8*), i8* bitcast ([0 x i8*]* @lvgv to i8*), i32 0 }], section "llvm.metadata"
+
+define void @__OpenCL_foo_kernel() nounwind readnone {
+entry:
+ ret void
+}
Added: llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_cypress.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_cypress.ll?rev=161996&view=auto
==============================================================================
--- llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_cypress.ll (added)
+++ llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_cypress.ll Wed Aug 15 17:39:43 2012
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=amdil -mcpu=cypress | FileCheck %s
+; CHECK: ;device:cypress
+; ModuleID = '_temp_0_cypress_optimized.bc'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:32:32-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-a0:0:64"
+target triple = "amdil-pc-amdopencl"
+
+%0 = type { i8*, i8*, i8*, i8*, i32 }
+
+ at sgv = internal addrspace(2) constant [1 x i8] zeroinitializer
+ at fgv = internal addrspace(2) constant [1 x i8] zeroinitializer
+ at lvgv = internal constant [0 x i8*] zeroinitializer
+ at llvm.global.annotations = appending global [1 x %0] [%0 { i8* bitcast (void ()* @__OpenCL_foo_kernel to i8*), i8* bitcast ([1 x i8] addrspace(2)* @sgv to i8*), i8* bitcast ([1 x i8] addrspace(2)* @fgv to i8*), i8* bitcast ([0 x i8*]* @lvgv to i8*), i32 0 }], section "llvm.metadata"
+
+define void @__OpenCL_foo_kernel() nounwind readnone {
+entry:
+ ret void
+}
Added: llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_juniper.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_juniper.ll?rev=161996&view=auto
==============================================================================
--- llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_juniper.ll (added)
+++ llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_juniper.ll Wed Aug 15 17:39:43 2012
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=amdil -mcpu=juniper | FileCheck %s
+; CHECK: ;device:juniper
+; ModuleID = '_temp_0_cypress_optimized.bc'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:32:32-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-a0:0:64"
+target triple = "amdil-pc-amdopencl"
+
+%0 = type { i8*, i8*, i8*, i8*, i32 }
+
+ at sgv = internal addrspace(2) constant [1 x i8] zeroinitializer
+ at fgv = internal addrspace(2) constant [1 x i8] zeroinitializer
+ at lvgv = internal constant [0 x i8*] zeroinitializer
+ at llvm.global.annotations = appending global [1 x %0] [%0 { i8* bitcast (void ()* @__OpenCL_foo_kernel to i8*), i8* bitcast ([1 x i8] addrspace(2)* @sgv to i8*), i8* bitcast ([1 x i8] addrspace(2)* @fgv to i8*), i8* bitcast ([0 x i8*]* @lvgv to i8*), i32 0 }], section "llvm.metadata"
+
+define void @__OpenCL_foo_kernel() nounwind readnone {
+entry:
+ ret void
+}
Added: llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_redwood.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_redwood.ll?rev=161996&view=auto
==============================================================================
--- llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_redwood.ll (added)
+++ llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_redwood.ll Wed Aug 15 17:39:43 2012
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=amdil -mcpu=redwood | FileCheck %s
+; CHECK: ;device:redwood
+; ModuleID = '_temp_0_cypress_optimized.bc'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:32:32-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-a0:0:64"
+target triple = "amdil-pc-amdopencl"
+
+%0 = type { i8*, i8*, i8*, i8*, i32 }
+
+ at sgv = internal addrspace(2) constant [1 x i8] zeroinitializer
+ at fgv = internal addrspace(2) constant [1 x i8] zeroinitializer
+ at lvgv = internal constant [0 x i8*] zeroinitializer
+ at llvm.global.annotations = appending global [1 x %0] [%0 { i8* bitcast (void ()* @__OpenCL_foo_kernel to i8*), i8* bitcast ([1 x i8] addrspace(2)* @sgv to i8*), i8* bitcast ([1 x i8] addrspace(2)* @fgv to i8*), i8* bitcast ([0 x i8*]* @lvgv to i8*), i32 0 }], section "llvm.metadata"
+
+define void @__OpenCL_foo_kernel() nounwind readnone {
+entry:
+ ret void
+}
Added: llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_rv710.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_rv710.ll?rev=161996&view=auto
==============================================================================
--- llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_rv710.ll (added)
+++ llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_rv710.ll Wed Aug 15 17:39:43 2012
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=amdil -mcpu=rv710 | FileCheck %s
+; CHECK: ;device:rv710
+; ModuleID = '_temp_0_cypress_optimized.bc'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:32:32-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-a0:0:64"
+target triple = "amdil-pc-amdopencl"
+
+%0 = type { i8*, i8*, i8*, i8*, i32 }
+
+ at sgv = internal addrspace(2) constant [1 x i8] zeroinitializer
+ at fgv = internal addrspace(2) constant [1 x i8] zeroinitializer
+ at lvgv = internal constant [0 x i8*] zeroinitializer
+ at llvm.global.annotations = appending global [1 x %0] [%0 { i8* bitcast (void ()* @__OpenCL_foo_kernel to i8*), i8* bitcast ([1 x i8] addrspace(2)* @sgv to i8*), i8* bitcast ([1 x i8] addrspace(2)* @fgv to i8*), i8* bitcast ([0 x i8*]* @lvgv to i8*), i32 0 }], section "llvm.metadata"
+
+define void @__OpenCL_foo_kernel() nounwind readnone {
+entry:
+ ret void
+}
Added: llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_rv730.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_rv730.ll?rev=161996&view=auto
==============================================================================
--- llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_rv730.ll (added)
+++ llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_rv730.ll Wed Aug 15 17:39:43 2012
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=amdil -mcpu=rv730 | FileCheck %s
+; CHECK: ;device:rv730
+; ModuleID = '_temp_0_cypress_optimized.bc'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:32:32-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-a0:0:64"
+target triple = "amdil-pc-amdopencl"
+
+%0 = type { i8*, i8*, i8*, i8*, i32 }
+
+ at sgv = internal addrspace(2) constant [1 x i8] zeroinitializer
+ at fgv = internal addrspace(2) constant [1 x i8] zeroinitializer
+ at lvgv = internal constant [0 x i8*] zeroinitializer
+ at llvm.global.annotations = appending global [1 x %0] [%0 { i8* bitcast (void ()* @__OpenCL_foo_kernel to i8*), i8* bitcast ([1 x i8] addrspace(2)* @sgv to i8*), i8* bitcast ([1 x i8] addrspace(2)* @fgv to i8*), i8* bitcast ([0 x i8*]* @lvgv to i8*), i32 0 }], section "llvm.metadata"
+
+define void @__OpenCL_foo_kernel() nounwind readnone {
+entry:
+ ret void
+}
Added: llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_rv770.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_rv770.ll?rev=161996&view=auto
==============================================================================
--- llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_rv770.ll (added)
+++ llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_rv770.ll Wed Aug 15 17:39:43 2012
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=amdil -mcpu=rv770 | FileCheck %s
+; CHECK: ;device:rv770
+; ModuleID = '_temp_0_cypress_optimized.bc'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:32:32-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-a0:0:64"
+target triple = "amdil-pc-amdopencl"
+
+%0 = type { i8*, i8*, i8*, i8*, i32 }
+
+ at sgv = internal addrspace(2) constant [1 x i8] zeroinitializer
+ at fgv = internal addrspace(2) constant [1 x i8] zeroinitializer
+ at lvgv = internal constant [0 x i8*] zeroinitializer
+ at llvm.global.annotations = appending global [1 x %0] [%0 { i8* bitcast (void ()* @__OpenCL_foo_kernel to i8*), i8* bitcast ([1 x i8] addrspace(2)* @sgv to i8*), i8* bitcast ([1 x i8] addrspace(2)* @fgv to i8*), i8* bitcast ([0 x i8*]* @lvgv to i8*), i32 0 }], section "llvm.metadata"
+
+define void @__OpenCL_foo_kernel() nounwind readnone {
+entry:
+ ret void
+}
Added: llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_turks.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_turks.ll?rev=161996&view=auto
==============================================================================
--- llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_turks.ll (added)
+++ llvm/branches/AMDILBackend/test/CodeGen/AMDIL/target_turks.ll Wed Aug 15 17:39:43 2012
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=amdil -mcpu=turks | FileCheck %s
+; CHECK: ;device:turks
+; ModuleID = '_temp_0_cypress_optimized.bc'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:32:32-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-a0:0:64"
+target triple = "amdil-pc-amdopencl"
+
+%0 = type { i8*, i8*, i8*, i8*, i32 }
+
+ at sgv = internal addrspace(2) constant [1 x i8] zeroinitializer
+ at fgv = internal addrspace(2) constant [1 x i8] zeroinitializer
+ at lvgv = internal constant [0 x i8*] zeroinitializer
+ at llvm.global.annotations = appending global [1 x %0] [%0 { i8* bitcast (void ()* @__OpenCL_foo_kernel to i8*), i8* bitcast ([1 x i8] addrspace(2)* @sgv to i8*), i8* bitcast ([1 x i8] addrspace(2)* @fgv to i8*), i8* bitcast ([0 x i8*]* @lvgv to i8*), i32 0 }], section "llvm.metadata"
+
+define void @__OpenCL_foo_kernel() nounwind readnone {
+entry:
+ ret void
+}
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