[llvm-branch-commits] [llvm-branch] r142808 - in /llvm/branches/release_30: ./ lib/Target/ARM/ARMInstrThumb2.td

[Bill Wendling]

Author: void
Date: Mon Oct 24 12:33:07 2011
New Revision: 142808

URL: http://llvm.org/viewvc/llvm-project?rev=142808&view=rev
Log:
Merging r142801:
------------------------------------------------------------------------
r142801 | grosbach | 2011-10-24 10:16:24 -0700 (Mon, 24 Oct 2011) | 4 lines

Thumb2 LDM instructions can target PC. Make sure to encode it.

PR11220

------------------------------------------------------------------------

Modified:
    llvm/branches/release_30/   (props changed)
    llvm/branches/release_30/lib/Target/ARM/ARMInstrThumb2.td

Propchange: llvm/branches/release_30/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Mon Oct 24 12:33:07 2011
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:142039,142055,142058,142112,142123,142125,142165,142168,142243,142350,142482,142486,142489,142491-142493,142537,142550,142559,142573-142574
+/llvm/trunk:142039,142055,142058,142112,142123,142125,142165,142168,142243,142350,142482,142486,142489,142491-142493,142537,142550,142559,142573-142574,142801

Modified: llvm/branches/release_30/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_30/lib/Target/ARM/ARMInstrThumb2.td?rev=142808&r1=142807&r2=142808&view=diff
==============================================================================
--- llvm/branches/release_30/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/branches/release_30/lib/Target/ARM/ARMInstrThumb2.td Mon Oct 24 12:33:07 2011
@@ -1538,8 +1538,7 @@
     let Inst{21}    = 0;        // No writeback
     let Inst{20}    = L_bit;
     let Inst{19-16} = Rn;
-    let Inst{15}    = 0;
-    let Inst{14-0}  = regs{14-0};
+    let Inst{15-0}  = regs;
   }
   def IA_UPD :
     T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
@@ -1554,8 +1553,7 @@
     let Inst{21}    = 1;        // Writeback
     let Inst{20}    = L_bit;
     let Inst{19-16} = Rn;
-    let Inst{15}    = 0;
-    let Inst{14-0}  = regs{14-0};
+    let Inst{15-0}  = regs;
   }
   def DB :
     T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
@@ -1570,8 +1568,7 @@
     let Inst{21}    = 0;        // No writeback
     let Inst{20}    = L_bit;
     let Inst{19-16} = Rn;
-    let Inst{15}    = 0;
-    let Inst{14-0}  = regs{14-0};
+    let Inst{15-0}  = regs;
   }
   def DB_UPD :
     T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
@@ -1586,8 +1583,7 @@
     let Inst{21}    = 1;        // Writeback
     let Inst{20}    = L_bit;
     let Inst{19-16} = Rn;
-    let Inst{15}    = 0;
-    let Inst{14-0}  = regs{14-0};
+    let Inst{15-0}  = regs;
   }
 }