[llvm-branch-commits] [llvm-branch] r142609 - in /llvm/branches/release_30: ./ lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/X86/X86FrameLowering.cpp lib/Target/X86/X86ISelLowering.cpp
Bill Wendling
isanbard at gmail.com
Thu Oct 20 13:28:08 PDT 2011
Author: void
Date: Thu Oct 20 15:28:08 2011
New Revision: 142609
URL: http://llvm.org/viewvc/llvm-project?rev=142609&view=rev
Log:
Merging r142350:
------------------------------------------------------------------------
r142350 | baldrick | 2011-10-18 05:44:00 -0700 (Tue, 18 Oct 2011) | 3 lines
Fix a bunch of unused variable warnings when doing a release
build with gcc-4.6.
------------------------------------------------------------------------
Modified:
llvm/branches/release_30/ (props changed)
llvm/branches/release_30/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
llvm/branches/release_30/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/branches/release_30/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/branches/release_30/lib/Target/ARM/ARMISelLowering.cpp
llvm/branches/release_30/lib/Target/X86/X86FrameLowering.cpp
llvm/branches/release_30/lib/Target/X86/X86ISelLowering.cpp
Propchange: llvm/branches/release_30/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Thu Oct 20 15:28:08 2011
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:142039,142055,142058,142112,142123,142125,142165,142168,142243,142482,142486,142489,142491-142493,142537,142550,142559
+/llvm/trunk:142039,142055,142058,142112,142123,142125,142165,142168,142243,142350,142482,142486,142489,142491-142493,142537,142550,142559
Modified: llvm/branches/release_30/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_30/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp?rev=142609&r1=142608&r2=142609&view=diff
==============================================================================
--- llvm/branches/release_30/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp (original)
+++ llvm/branches/release_30/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp Thu Oct 20 15:28:08 2011
@@ -266,7 +266,6 @@
// Implement VSELECT in terms of XOR, AND, OR
// on platforms which do not support blend natively.
EVT VT = Op.getOperand(0).getValueType();
- EVT OVT = Op.getOperand(1).getValueType();
DebugLoc DL = Op.getDebugLoc();
SDValue Mask = Op.getOperand(0);
@@ -280,7 +279,8 @@
!TLI.isOperationLegalOrCustom(ISD::OR, VT))
return DAG.UnrollVectorOp(Op.getNode());
- assert(VT.getSizeInBits() == OVT.getSizeInBits() && "Invalid mask size");
+ assert(VT.getSizeInBits() == Op.getOperand(1).getValueType().getSizeInBits()
+ && "Invalid mask size");
// Bitcast the operands to be the same type as the mask.
// This is needed when we select between FP types because
// the mask is a vector of integers.
Modified: llvm/branches/release_30/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_30/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=142609&r1=142608&r2=142609&view=diff
==============================================================================
--- llvm/branches/release_30/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/branches/release_30/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Oct 20 15:28:08 2011
@@ -2800,6 +2800,7 @@
EVT.getVectorNumElements() == VT.getVectorNumElements()) &&
"Vector element counts must match in FP_ROUND_INREG");
assert(EVT.bitsLE(VT) && "Not rounding down!");
+ (void)EVT;
if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding.
break;
}
Modified: llvm/branches/release_30/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_30/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=142609&r1=142608&r2=142609&view=diff
==============================================================================
--- llvm/branches/release_30/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/branches/release_30/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Thu Oct 20 15:28:08 2011
@@ -2474,7 +2474,7 @@
size_t numCmps = Clusterify(Cases, SI);
DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
<< ". Total compares: " << numCmps << '\n');
- numCmps = 0;
+ (void)numCmps;
// Get the Value to be switched on and default basic blocks, which will be
// inserted into CaseBlock records, representing basic blocks in the binary
Modified: llvm/branches/release_30/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_30/lib/Target/ARM/ARMISelLowering.cpp?rev=142609&r1=142608&r2=142609&view=diff
==============================================================================
--- llvm/branches/release_30/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/branches/release_30/lib/Target/ARM/ARMISelLowering.cpp Thu Oct 20 15:28:08 2011
@@ -4900,9 +4900,9 @@
static void
ReplaceATOMIC_OP_64(SDNode *Node, SmallVectorImpl<SDValue>& Results,
SelectionDAG &DAG, unsigned NewOp) {
- EVT T = Node->getValueType(0);
DebugLoc dl = Node->getDebugLoc();
- assert (T == MVT::i64 && "Only know how to expand i64 atomics");
+ assert (Node->getValueType(0) == MVT::i64 &&
+ "Only know how to expand i64 atomics");
SmallVector<SDValue, 6> Ops;
Ops.push_back(Node->getOperand(0)); // Chain
Modified: llvm/branches/release_30/lib/Target/X86/X86FrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_30/lib/Target/X86/X86FrameLowering.cpp?rev=142609&r1=142608&r2=142609&view=diff
==============================================================================
--- llvm/branches/release_30/lib/Target/X86/X86FrameLowering.cpp (original)
+++ llvm/branches/release_30/lib/Target/X86/X86FrameLowering.cpp Thu Oct 20 15:28:08 2011
@@ -1113,9 +1113,7 @@
// Skip the saved EBP.
Offset += RI->getSlotSize();
} else {
- unsigned Align = MFI->getObjectAlignment(FI);
- assert((-(Offset + StackSize)) % Align == 0);
- Align = 0;
+ assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
return Offset + StackSize;
}
// FIXME: Support tail calls
@@ -1267,7 +1265,7 @@
true);
assert(FrameIdx == MFI->getObjectIndexBegin() &&
"Slot for EBP register must be last in order to be found!");
- FrameIdx = 0;
+ (void)FrameIdx;
}
}
Modified: llvm/branches/release_30/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_30/lib/Target/X86/X86ISelLowering.cpp?rev=142609&r1=142608&r2=142609&view=diff
==============================================================================
--- llvm/branches/release_30/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/release_30/lib/Target/X86/X86ISelLowering.cpp Thu Oct 20 15:28:08 2011
@@ -1753,6 +1753,7 @@
// places.
assert(VA.getValNo() != LastVal &&
"Don't support value assigned to multiple locs yet");
+ (void)LastVal;
LastVal = VA.getValNo();
if (VA.isRegLoc()) {
@@ -10477,9 +10478,9 @@
void X86TargetLowering::
ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG, unsigned NewOp) const {
- EVT T = Node->getValueType(0);
DebugLoc dl = Node->getDebugLoc();
- assert (T == MVT::i64 && "Only know how to expand i64 atomics");
+ assert (Node->getValueType(0) == MVT::i64 &&
+ "Only know how to expand i64 atomics");
SDValue Chain = Node->getOperand(0);
SDValue In1 = Node->getOperand(1);
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