[llvm-branch-commits] [llvm-branch] r136040 - in /llvm/branches/exception-handling-rewrite: ./ cmake/modules/ docs/ include/llvm-c/ include/llvm-c/Transforms/ include/llvm/ include/llvm/Analysis/ include/llvm/Bitcode/ include/llvm/CodeGen/ include/llvm/MC/ include/llvm/MC/MCParser/ include/llvm/Support/ include/llvm/Target/ lib/Analysis/ lib/AsmParser/ lib/Bitcode/Reader/ lib/Bitcode/Writer/ lib/CodeGen/ lib/CodeGen/AsmPrinter/ lib/CodeGen/SelectionDAG/ lib/MC/ lib/MC/MCDisassembler/ lib/MC/MCParser/ lib/Support/ lib/Target/ ...
Bill Wendling
isanbard at gmail.com
Mon Jul 25 18:29:48 PDT 2011
Author: void
Date: Mon Jul 25 20:29:47 2011
New Revision: 136040
URL: http://llvm.org/viewvc/llvm-project?rev=136040&view=rev
Log:
Merge with ToT.
Added:
llvm/branches/exception-handling-rewrite/include/llvm/Analysis/BlockFrequencyInfo.h
- copied unchanged from r136038, llvm/trunk/include/llvm/Analysis/BlockFrequencyInfo.h
llvm/branches/exception-handling-rewrite/include/llvm/CodeGen/MachineBlockFrequencyInfo.h
- copied unchanged from r136038, llvm/trunk/include/llvm/CodeGen/MachineBlockFrequencyInfo.h
llvm/branches/exception-handling-rewrite/include/llvm/MC/MCAsmBackend.h
- copied unchanged from r136038, llvm/trunk/include/llvm/MC/MCAsmBackend.h
llvm/branches/exception-handling-rewrite/include/llvm/MC/MCTargetAsmLexer.h
- copied unchanged from r136038, llvm/trunk/include/llvm/MC/MCTargetAsmLexer.h
llvm/branches/exception-handling-rewrite/include/llvm/MC/MCTargetAsmParser.h
- copied unchanged from r136038, llvm/trunk/include/llvm/MC/MCTargetAsmParser.h
llvm/branches/exception-handling-rewrite/include/llvm/Support/BlockFrequency.h
- copied unchanged from r136038, llvm/trunk/include/llvm/Support/BlockFrequency.h
llvm/branches/exception-handling-rewrite/lib/Analysis/BlockFrequencyInfo.cpp
- copied unchanged from r136038, llvm/trunk/lib/Analysis/BlockFrequencyInfo.cpp
llvm/branches/exception-handling-rewrite/lib/CodeGen/MachineBlockFrequencyInfo.cpp
- copied unchanged from r136038, llvm/trunk/lib/CodeGen/MachineBlockFrequencyInfo.cpp
llvm/branches/exception-handling-rewrite/lib/MC/MCAsmBackend.cpp
- copied unchanged from r136038, llvm/trunk/lib/MC/MCAsmBackend.cpp
llvm/branches/exception-handling-rewrite/lib/MC/MCParser/MCTargetAsmParser.cpp
- copied unchanged from r136038, llvm/trunk/lib/MC/MCParser/MCTargetAsmParser.cpp
llvm/branches/exception-handling-rewrite/lib/MC/MCTargetAsmLexer.cpp
- copied unchanged from r136038, llvm/trunk/lib/MC/MCTargetAsmLexer.cpp
llvm/branches/exception-handling-rewrite/lib/Support/BlockFrequency.cpp
- copied unchanged from r136038, llvm/trunk/lib/Support/BlockFrequency.cpp
llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MCTargetDesc/MBlazeAsmBackend.cpp
- copied unchanged from r136038, llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeAsmBackend.cpp
llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MCTargetDesc/MBlazeBaseInfo.h
- copied unchanged from r136038, llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeBaseInfo.h
llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MCTargetDesc/MBlazeMCCodeEmitter.cpp
- copied unchanged from r136038, llvm/trunk/lib/Target/MBlaze/MCTargetDesc/MBlazeMCCodeEmitter.cpp
llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
- copied unchanged from r136038, llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/MCTargetDesc/PPCBaseInfo.h
- copied unchanged from r136038, llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCBaseInfo.h
llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h
- copied unchanged from r136038, llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h
llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
- copied unchanged from r136038, llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/MCTargetDesc/PPCPredicates.cpp
- copied unchanged from r136038, llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCPredicates.cpp
llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/MCTargetDesc/PPCPredicates.h
- copied unchanged from r136038, llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCPredicates.h
llvm/branches/exception-handling-rewrite/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
- copied unchanged from r136038, llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
llvm/branches/exception-handling-rewrite/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
- copied unchanged from r136038, llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
llvm/branches/exception-handling-rewrite/lib/Target/X86/MCTargetDesc/X86FixupKinds.h
- copied unchanged from r136038, llvm/trunk/lib/Target/X86/MCTargetDesc/X86FixupKinds.h
llvm/branches/exception-handling-rewrite/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
- copied unchanged from r136038, llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
llvm/branches/exception-handling-rewrite/lib/Target/X86/MCTargetDesc/X86MachObjectWriter.cpp
- copied unchanged from r136038, llvm/trunk/lib/Target/X86/MCTargetDesc/X86MachObjectWriter.cpp
llvm/branches/exception-handling-rewrite/test/Transforms/ScalarRepl/lifetime.ll
- copied unchanged from r136038, llvm/trunk/test/Transforms/ScalarRepl/lifetime.ll
llvm/branches/exception-handling-rewrite/tools/llvmc/examples/CMakeLists.txt
- copied unchanged from r136038, llvm/trunk/tools/llvmc/examples/CMakeLists.txt
llvm/branches/exception-handling-rewrite/tools/llvmc/examples/Hello/CMakeLists.txt
- copied unchanged from r136038, llvm/trunk/tools/llvmc/examples/Hello/CMakeLists.txt
llvm/branches/exception-handling-rewrite/tools/llvmc/examples/Simple/CMakeLists.txt
- copied unchanged from r136038, llvm/trunk/tools/llvmc/examples/Simple/CMakeLists.txt
llvm/branches/exception-handling-rewrite/tools/llvmc/examples/Skeleton/CMakeLists.txt
- copied unchanged from r136038, llvm/trunk/tools/llvmc/examples/Skeleton/CMakeLists.txt
llvm/branches/exception-handling-rewrite/tools/llvmc/examples/mcc16/CMakeLists.txt
- copied unchanged from r136038, llvm/trunk/tools/llvmc/examples/mcc16/CMakeLists.txt
llvm/branches/exception-handling-rewrite/tools/llvmc/src/CMakeLists.txt
- copied unchanged from r136038, llvm/trunk/tools/llvmc/src/CMakeLists.txt
Removed:
llvm/branches/exception-handling-rewrite/include/llvm/Analysis/BlockFrequency.h
llvm/branches/exception-handling-rewrite/include/llvm/CodeGen/MachineBlockFrequency.h
llvm/branches/exception-handling-rewrite/include/llvm/MC/TargetAsmBackend.h
llvm/branches/exception-handling-rewrite/include/llvm/MC/TargetAsmLexer.h
llvm/branches/exception-handling-rewrite/include/llvm/MC/TargetAsmParser.h
llvm/branches/exception-handling-rewrite/lib/Analysis/BlockFrequency.cpp
llvm/branches/exception-handling-rewrite/lib/CodeGen/MachineBlockFrequency.cpp
llvm/branches/exception-handling-rewrite/lib/MC/MCParser/TargetAsmParser.cpp
llvm/branches/exception-handling-rewrite/lib/MC/TargetAsmBackend.cpp
llvm/branches/exception-handling-rewrite/lib/MC/TargetAsmLexer.cpp
llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeAsmBackend.cpp
llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp
llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCAsmBackend.cpp
llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCFixupKinds.h
llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCMCCodeEmitter.cpp
llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCPredicates.cpp
llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCPredicates.h
llvm/branches/exception-handling-rewrite/lib/Target/X86/X86AsmBackend.cpp
llvm/branches/exception-handling-rewrite/lib/Target/X86/X86FixupKinds.h
llvm/branches/exception-handling-rewrite/lib/Target/X86/X86MCCodeEmitter.cpp
llvm/branches/exception-handling-rewrite/lib/Target/X86/X86MachObjectWriter.cpp
Modified:
llvm/branches/exception-handling-rewrite/ (props changed)
llvm/branches/exception-handling-rewrite/cmake/modules/AddLLVM.cmake
llvm/branches/exception-handling-rewrite/cmake/modules/LLVMLibDeps.cmake
llvm/branches/exception-handling-rewrite/cmake/modules/TableGen.cmake
llvm/branches/exception-handling-rewrite/docs/CodeGenerator.html
llvm/branches/exception-handling-rewrite/docs/LangRef.html
llvm/branches/exception-handling-rewrite/docs/ReleaseNotes.html
llvm/branches/exception-handling-rewrite/docs/SourceLevelDebugging.html
llvm/branches/exception-handling-rewrite/include/llvm-c/Target.h
llvm/branches/exception-handling-rewrite/include/llvm-c/Transforms/Scalar.h
llvm/branches/exception-handling-rewrite/include/llvm/Analysis/BlockFrequencyImpl.h
llvm/branches/exception-handling-rewrite/include/llvm/Bitcode/LLVMBitCodes.h
llvm/branches/exception-handling-rewrite/include/llvm/Constants.h
llvm/branches/exception-handling-rewrite/include/llvm/InitializePasses.h
llvm/branches/exception-handling-rewrite/include/llvm/Instruction.def
llvm/branches/exception-handling-rewrite/include/llvm/Instructions.h
llvm/branches/exception-handling-rewrite/include/llvm/MC/MCAssembler.h
llvm/branches/exception-handling-rewrite/include/llvm/MC/MCObjectStreamer.h
llvm/branches/exception-handling-rewrite/include/llvm/MC/MCParser/MCAsmLexer.h
llvm/branches/exception-handling-rewrite/include/llvm/MC/MCParser/MCAsmParser.h
llvm/branches/exception-handling-rewrite/include/llvm/MC/MCStreamer.h
llvm/branches/exception-handling-rewrite/include/llvm/Support/BranchProbability.h
llvm/branches/exception-handling-rewrite/include/llvm/Support/IRBuilder.h
llvm/branches/exception-handling-rewrite/include/llvm/Support/InstVisitor.h
llvm/branches/exception-handling-rewrite/include/llvm/Support/NoFolder.h
llvm/branches/exception-handling-rewrite/include/llvm/Support/TypeBuilder.h
llvm/branches/exception-handling-rewrite/include/llvm/Target/TargetRegistry.h
llvm/branches/exception-handling-rewrite/lib/Analysis/Analysis.cpp
llvm/branches/exception-handling-rewrite/lib/Analysis/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Analysis/ConstantFolding.cpp
llvm/branches/exception-handling-rewrite/lib/Analysis/InstructionSimplify.cpp
llvm/branches/exception-handling-rewrite/lib/Analysis/PHITransAddr.cpp
llvm/branches/exception-handling-rewrite/lib/AsmParser/LLLexer.cpp
llvm/branches/exception-handling-rewrite/lib/AsmParser/LLParser.cpp
llvm/branches/exception-handling-rewrite/lib/AsmParser/LLParser.h
llvm/branches/exception-handling-rewrite/lib/AsmParser/LLToken.h
llvm/branches/exception-handling-rewrite/lib/Bitcode/Reader/BitcodeReader.cpp
llvm/branches/exception-handling-rewrite/lib/Bitcode/Writer/BitcodeWriter.cpp
llvm/branches/exception-handling-rewrite/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
llvm/branches/exception-handling-rewrite/lib/CodeGen/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/CodeGen/CodeGen.cpp
llvm/branches/exception-handling-rewrite/lib/CodeGen/LLVMTargetMachine.cpp
llvm/branches/exception-handling-rewrite/lib/CodeGen/RegAllocGreedy.cpp
llvm/branches/exception-handling-rewrite/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/branches/exception-handling-rewrite/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/branches/exception-handling-rewrite/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
llvm/branches/exception-handling-rewrite/lib/CodeGen/SjLjEHPrepare.cpp
llvm/branches/exception-handling-rewrite/lib/MC/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/MC/ELFObjectWriter.cpp
llvm/branches/exception-handling-rewrite/lib/MC/MCAsmStreamer.cpp
llvm/branches/exception-handling-rewrite/lib/MC/MCAssembler.cpp
llvm/branches/exception-handling-rewrite/lib/MC/MCDisassembler/Disassembler.cpp
llvm/branches/exception-handling-rewrite/lib/MC/MCDisassembler/EDDisassembler.cpp
llvm/branches/exception-handling-rewrite/lib/MC/MCDisassembler/EDDisassembler.h
llvm/branches/exception-handling-rewrite/lib/MC/MCELF.cpp
llvm/branches/exception-handling-rewrite/lib/MC/MCELFStreamer.cpp
llvm/branches/exception-handling-rewrite/lib/MC/MCELFStreamer.h
llvm/branches/exception-handling-rewrite/lib/MC/MCExpr.cpp
llvm/branches/exception-handling-rewrite/lib/MC/MCMachOStreamer.cpp
llvm/branches/exception-handling-rewrite/lib/MC/MCObjectStreamer.cpp
llvm/branches/exception-handling-rewrite/lib/MC/MCParser/AsmParser.cpp
llvm/branches/exception-handling-rewrite/lib/MC/MCParser/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/MC/MCParser/COFFAsmParser.cpp
llvm/branches/exception-handling-rewrite/lib/MC/MCParser/ELFAsmParser.cpp
llvm/branches/exception-handling-rewrite/lib/MC/MCParser/MCAsmParser.cpp
llvm/branches/exception-handling-rewrite/lib/MC/MCPureStreamer.cpp
llvm/branches/exception-handling-rewrite/lib/MC/MachObjectWriter.cpp
llvm/branches/exception-handling-rewrite/lib/MC/WinCOFFObjectWriter.cpp
llvm/branches/exception-handling-rewrite/lib/MC/WinCOFFStreamer.cpp
llvm/branches/exception-handling-rewrite/lib/Support/BranchProbability.cpp
llvm/branches/exception-handling-rewrite/lib/Support/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/ARM/ARM.h
llvm/branches/exception-handling-rewrite/lib/Target/ARM/ARMAsmPrinter.cpp
llvm/branches/exception-handling-rewrite/lib/Target/ARM/ARMInstrFormats.td
llvm/branches/exception-handling-rewrite/lib/Target/ARM/ARMInstrInfo.td
llvm/branches/exception-handling-rewrite/lib/Target/ARM/ARMInstrThumb2.td
llvm/branches/exception-handling-rewrite/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp
llvm/branches/exception-handling-rewrite/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/branches/exception-handling-rewrite/lib/Target/ARM/AsmParser/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/ARM/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
llvm/branches/exception-handling-rewrite/lib/Target/ARM/Disassembler/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
llvm/branches/exception-handling-rewrite/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
llvm/branches/exception-handling-rewrite/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
llvm/branches/exception-handling-rewrite/lib/Target/ARM/InstPrinter/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
llvm/branches/exception-handling-rewrite/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h
llvm/branches/exception-handling-rewrite/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
llvm/branches/exception-handling-rewrite/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
llvm/branches/exception-handling-rewrite/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp
llvm/branches/exception-handling-rewrite/lib/Target/ARM/MCTargetDesc/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/Alpha/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/Alpha/MCTargetDesc/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/Alpha/TargetInfo/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/Blackfin/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/Blackfin/MCTargetDesc/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/CBackend/CBackend.cpp
llvm/branches/exception-handling-rewrite/lib/Target/CBackend/TargetInfo/CBackendTargetInfo.cpp
llvm/branches/exception-handling-rewrite/lib/Target/CellSPU/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/CellSPU/MCTargetDesc/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/CppBackend/CPPBackend.cpp
llvm/branches/exception-handling-rewrite/lib/Target/CppBackend/TargetInfo/CppBackendTargetInfo.cpp
llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/AsmParser/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/AsmParser/MBlazeAsmLexer.cpp
llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp
llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/Disassembler/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp
llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/InstPrinter/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlaze.h
llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeAsmPrinter.cpp
llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeISelLowering.cpp
llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeInstrInfo.h
llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeRegisterInfo.cpp
llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeRegisterInfo.h
llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeTargetMachine.cpp
llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MCTargetDesc/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp
llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.h
llvm/branches/exception-handling-rewrite/lib/Target/MSP430/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/MSP430/InstPrinter/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/MSP430/MCTargetDesc/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp
llvm/branches/exception-handling-rewrite/lib/Target/MSP430/MSP430AsmPrinter.cpp
llvm/branches/exception-handling-rewrite/lib/Target/Mips/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/Mips/InstPrinter/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/Mips/MCTargetDesc/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
llvm/branches/exception-handling-rewrite/lib/Target/Mips/MipsAsmPrinter.cpp
llvm/branches/exception-handling-rewrite/lib/Target/PTX/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/PTX/MCTargetDesc/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/PTX/PTXMCAsmStreamer.cpp
llvm/branches/exception-handling-rewrite/lib/Target/PTX/PTXTargetMachine.cpp
llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/InstPrinter/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPC.h
llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCAsmPrinter.cpp
llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCBranchSelector.cpp
llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCCodeEmitter.cpp
llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCFrameLowering.cpp
llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCRegisterInfo.cpp
llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCRegisterInfo.h
llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCTargetMachine.cpp
llvm/branches/exception-handling-rewrite/lib/Target/Sparc/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/Sparc/MCTargetDesc/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/SystemZ/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/SystemZ/MCTargetDesc/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/Target.cpp
llvm/branches/exception-handling-rewrite/lib/Target/X86/AsmParser/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/X86/AsmParser/X86AsmLexer.cpp
llvm/branches/exception-handling-rewrite/lib/Target/X86/AsmParser/X86AsmParser.cpp
llvm/branches/exception-handling-rewrite/lib/Target/X86/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/X86/Disassembler/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/X86/InstPrinter/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/X86/InstPrinter/X86InstComments.cpp
llvm/branches/exception-handling-rewrite/lib/Target/X86/MCTargetDesc/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
llvm/branches/exception-handling-rewrite/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
llvm/branches/exception-handling-rewrite/lib/Target/X86/README.txt
llvm/branches/exception-handling-rewrite/lib/Target/X86/X86.h
llvm/branches/exception-handling-rewrite/lib/Target/X86/X86AsmPrinter.cpp
llvm/branches/exception-handling-rewrite/lib/Target/X86/X86CodeEmitter.cpp
llvm/branches/exception-handling-rewrite/lib/Target/X86/X86FrameLowering.cpp
llvm/branches/exception-handling-rewrite/lib/Target/X86/X86FrameLowering.h
llvm/branches/exception-handling-rewrite/lib/Target/X86/X86ISelLowering.cpp
llvm/branches/exception-handling-rewrite/lib/Target/X86/X86InstrFormats.td
llvm/branches/exception-handling-rewrite/lib/Target/X86/X86InstrFragmentsSIMD.td
llvm/branches/exception-handling-rewrite/lib/Target/X86/X86InstrInfo.cpp
llvm/branches/exception-handling-rewrite/lib/Target/X86/X86InstrInfo.h
llvm/branches/exception-handling-rewrite/lib/Target/X86/X86InstrSSE.td
llvm/branches/exception-handling-rewrite/lib/Target/X86/X86MCInstLower.cpp
llvm/branches/exception-handling-rewrite/lib/Target/X86/X86TargetMachine.cpp
llvm/branches/exception-handling-rewrite/lib/Target/XCore/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Target/XCore/MCTargetDesc/CMakeLists.txt
llvm/branches/exception-handling-rewrite/lib/Transforms/IPO/ArgumentPromotion.cpp
llvm/branches/exception-handling-rewrite/lib/Transforms/IPO/GlobalOpt.cpp
llvm/branches/exception-handling-rewrite/lib/Transforms/InstCombine/InstCombineCasts.cpp
llvm/branches/exception-handling-rewrite/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
llvm/branches/exception-handling-rewrite/lib/Transforms/InstCombine/InstCombinePHI.cpp
llvm/branches/exception-handling-rewrite/lib/Transforms/InstCombine/InstructionCombining.cpp
llvm/branches/exception-handling-rewrite/lib/Transforms/Instrumentation/PathProfiling.cpp
llvm/branches/exception-handling-rewrite/lib/Transforms/Scalar/SCCP.cpp
llvm/branches/exception-handling-rewrite/lib/Transforms/Scalar/Scalar.cpp
llvm/branches/exception-handling-rewrite/lib/Transforms/Scalar/ScalarReplAggregates.cpp
llvm/branches/exception-handling-rewrite/lib/Transforms/Utils/CodeExtractor.cpp
llvm/branches/exception-handling-rewrite/lib/Transforms/Utils/LoopUnroll.cpp
llvm/branches/exception-handling-rewrite/lib/Transforms/Utils/LowerInvoke.cpp
llvm/branches/exception-handling-rewrite/lib/VMCore/AsmWriter.cpp
llvm/branches/exception-handling-rewrite/lib/VMCore/ConstantFold.cpp
llvm/branches/exception-handling-rewrite/lib/VMCore/Constants.cpp
llvm/branches/exception-handling-rewrite/lib/VMCore/Instruction.cpp
llvm/branches/exception-handling-rewrite/lib/VMCore/Instructions.cpp
llvm/branches/exception-handling-rewrite/lib/VMCore/Verifier.cpp
llvm/branches/exception-handling-rewrite/test/CodeGen/X86/avx-256-splat.ll
llvm/branches/exception-handling-rewrite/test/CodeGen/X86/avx-256.ll
llvm/branches/exception-handling-rewrite/test/CodeGen/X86/extractelement-load.ll
llvm/branches/exception-handling-rewrite/test/CodeGen/X86/palignr.ll
llvm/branches/exception-handling-rewrite/test/MC/ARM/basic-arm-instructions.s
llvm/branches/exception-handling-rewrite/test/MC/ARM/diagnostics.s
llvm/branches/exception-handling-rewrite/test/MC/AsmParser/labels.s
llvm/branches/exception-handling-rewrite/tools/llvm-mc/llvm-mc.cpp
llvm/branches/exception-handling-rewrite/tools/llvm-objdump/MCFunction.cpp
llvm/branches/exception-handling-rewrite/tools/llvm-objdump/MCFunction.h
llvm/branches/exception-handling-rewrite/tools/llvm-objdump/llvm-objdump.cpp
llvm/branches/exception-handling-rewrite/tools/llvmc/CMakeLists.txt
llvm/branches/exception-handling-rewrite/tools/llvmc/examples/mcc16/Hooks.cpp
llvm/branches/exception-handling-rewrite/tools/lto/LTOCodeGenerator.cpp
llvm/branches/exception-handling-rewrite/tools/lto/LTOModule.cpp
llvm/branches/exception-handling-rewrite/unittests/Transforms/Utils/Cloning.cpp
llvm/branches/exception-handling-rewrite/utils/TableGen/AsmMatcherEmitter.cpp
llvm/branches/exception-handling-rewrite/utils/TableGen/EDEmitter.cpp
Propchange: llvm/branches/exception-handling-rewrite/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Mon Jul 25 20:29:47 2011
@@ -1,2 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
+/llvm/trunk:135898-136038
Modified: llvm/branches/exception-handling-rewrite/cmake/modules/AddLLVM.cmake
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/cmake/modules/AddLLVM.cmake?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/cmake/modules/AddLLVM.cmake (original)
+++ llvm/branches/exception-handling-rewrite/cmake/modules/AddLLVM.cmake Mon Jul 25 20:29:47 2011
@@ -124,16 +124,9 @@
macro(add_llvm_target target_name)
- if( TABLEGEN_OUTPUT )
- add_custom_target(${target_name}Table_gen
- DEPENDS ${TABLEGEN_OUTPUT})
- add_dependencies(${target_name}Table_gen ${LLVM_COMMON_DEPENDS})
- endif( TABLEGEN_OUTPUT )
- include_directories(BEFORE ${CMAKE_CURRENT_BINARY_DIR})
+ include_directories(BEFORE
+ ${CMAKE_CURRENT_BINARY_DIR}
+ ${CMAKE_CURRENT_SOURCE_DIR})
add_llvm_library(LLVM${target_name} ${ARGN} ${TABLEGEN_OUTPUT})
- if ( TABLEGEN_OUTPUT )
- add_dependencies(LLVM${target_name} ${target_name}Table_gen)
- set_target_properties(${target_name}Table_gen PROPERTIES FOLDER "Tablegenning")
- endif (TABLEGEN_OUTPUT)
set( CURRENT_LLVM_TARGET LLVM${target_name} )
endmacro(add_llvm_target)
Modified: llvm/branches/exception-handling-rewrite/cmake/modules/LLVMLibDeps.cmake
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/cmake/modules/LLVMLibDeps.cmake?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/cmake/modules/LLVMLibDeps.cmake (original)
+++ llvm/branches/exception-handling-rewrite/cmake/modules/LLVMLibDeps.cmake Mon Jul 25 20:29:47 2011
@@ -1,7 +1,7 @@
-set(MSVC_LIB_DEPS_LLVMARMAsmParser LLVMARMCodeGen LLVMARMDesc LLVMARMInfo LLVMMC LLVMMCParser LLVMSupport LLVMTarget)
+set(MSVC_LIB_DEPS_LLVMARMAsmParser LLVMARMDesc LLVMARMInfo LLVMMC LLVMMCParser LLVMSupport)
set(MSVC_LIB_DEPS_LLVMARMAsmPrinter LLVMMC LLVMSupport)
set(MSVC_LIB_DEPS_LLVMARMCodeGen LLVMARMAsmPrinter LLVMARMDesc LLVMARMInfo LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget)
-set(MSVC_LIB_DEPS_LLVMARMDesc LLVMARMInfo LLVMMC LLVMSupport)
+set(MSVC_LIB_DEPS_LLVMARMDesc LLVMARMAsmPrinter LLVMARMInfo LLVMMC LLVMSupport)
set(MSVC_LIB_DEPS_LLVMARMDisassembler LLVMARMDesc LLVMARMInfo LLVMMC LLVMSupport)
set(MSVC_LIB_DEPS_LLVMARMInfo LLVMMC LLVMSupport LLVMTarget)
set(MSVC_LIB_DEPS_LLVMAlphaCodeGen LLVMAlphaDesc LLVMAlphaInfo LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget)
@@ -31,23 +31,23 @@
set(MSVC_LIB_DEPS_LLVMInterpreter LLVMCodeGen LLVMCore LLVMExecutionEngine LLVMSupport LLVMTarget)
set(MSVC_LIB_DEPS_LLVMJIT LLVMCodeGen LLVMCore LLVMExecutionEngine LLVMMC LLVMSupport LLVMTarget)
set(MSVC_LIB_DEPS_LLVMLinker LLVMArchive LLVMBitReader LLVMCore LLVMSupport LLVMTransformUtils)
-set(MSVC_LIB_DEPS_LLVMMBlazeAsmParser LLVMMBlazeCodeGen LLVMMBlazeInfo LLVMMC LLVMMCParser LLVMSupport LLVMTarget)
+set(MSVC_LIB_DEPS_LLVMMBlazeAsmParser LLVMMBlazeInfo LLVMMC LLVMMCParser LLVMSupport)
set(MSVC_LIB_DEPS_LLVMMBlazeAsmPrinter LLVMMC LLVMSupport)
set(MSVC_LIB_DEPS_LLVMMBlazeCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMBlazeAsmPrinter LLVMMBlazeDesc LLVMMBlazeInfo LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget)
-set(MSVC_LIB_DEPS_LLVMMBlazeDesc LLVMMBlazeInfo LLVMMC LLVMSupport)
-set(MSVC_LIB_DEPS_LLVMMBlazeDisassembler LLVMMBlazeCodeGen LLVMMBlazeDesc LLVMMBlazeInfo LLVMMC)
+set(MSVC_LIB_DEPS_LLVMMBlazeDesc LLVMMBlazeAsmPrinter LLVMMBlazeInfo LLVMMC LLVMSupport)
+set(MSVC_LIB_DEPS_LLVMMBlazeDisassembler LLVMMBlazeDesc LLVMMBlazeInfo LLVMMC LLVMSupport)
set(MSVC_LIB_DEPS_LLVMMBlazeInfo LLVMMC LLVMSupport LLVMTarget)
set(MSVC_LIB_DEPS_LLVMMC LLVMSupport)
-set(MSVC_LIB_DEPS_LLVMMCDisassembler LLVMARMAsmParser LLVMARMCodeGen LLVMARMDesc LLVMARMDisassembler LLVMARMInfo LLVMAlphaCodeGen LLVMAlphaDesc LLVMAlphaInfo LLVMBlackfinCodeGen LLVMBlackfinDesc LLVMBlackfinInfo LLVMCBackend LLVMCBackendInfo LLVMCellSPUCodeGen LLVMCellSPUDesc LLVMCellSPUInfo LLVMCppBackend LLVMCppBackendInfo LLVMMBlazeAsmParser LLVMMBlazeCodeGen LLVMMBlazeDesc LLVMMBlazeDisassembler LLVMMBlazeInfo LLVMMC LLVMMCParser LLVMMSP430CodeGen LLVMMSP430Desc LLVMMSP430Info LLVMMipsCodeGen LLVMMipsDesc LLVMMipsInfo LLVMPTXCodeGen LLVMPTXDesc LLVMPTXInfo LLVMPowerPCCodeGen LLVMPowerPCDesc LLVMPowerPCInfo LLVMSparcCodeGen LLVMSparcDesc LLVMSparcInfo LLVMSupport LLVMSystemZCodeGen LLVMSystemZDesc LLVMSystemZInfo LLVMTarget LLVMX86AsmParser LLVMX86CodeGen LLVMX86Desc LLVMX86Disassembler LLVMX86Info LLVMXCoreCodeGen LLVMXCoreDesc LLVMXCoreInfo)
+set(MSVC_LIB_DEPS_LLVMMCDisassembler LLVMARMAsmParser LLVMARMDesc LLVMARMDisassembler LLVMARMInfo LLVMAlphaDesc LLVMAlphaInfo LLVMBlackfinDesc LLVMBlackfinInfo LLVMCBackendInfo LLVMCellSPUDesc LLVMCellSPUInfo LLVMCppBackendInfo LLVMMBlazeAsmParser LLVMMBlazeDesc LLVMMBlazeDisassembler LLVMMBlazeInfo LLVMMC LLVMMCParser LLVMMSP430Desc LLVMMSP430Info LLVMMipsDesc LLVMMipsInfo LLVMPTXDesc LLVMPTXInfo LLVMPowerPCDesc LLVMPowerPCInfo LLVMSparcDesc LLVMSparcInfo LLVMSupport LLVMSystemZDesc LLVMSystemZInfo LLVMTarget LLVMX86AsmParser LLVMX86Desc LLVMX86Disassembler LLVMX86Info LLVMXCoreDesc LLVMXCoreInfo)
set(MSVC_LIB_DEPS_LLVMMCJIT LLVMCore LLVMExecutionEngine LLVMRuntimeDyld LLVMSupport LLVMTarget)
set(MSVC_LIB_DEPS_LLVMMCParser LLVMMC LLVMSupport)
set(MSVC_LIB_DEPS_LLVMMSP430AsmPrinter LLVMMC LLVMSupport)
set(MSVC_LIB_DEPS_LLVMMSP430CodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMMSP430AsmPrinter LLVMMSP430Desc LLVMMSP430Info LLVMSelectionDAG LLVMSupport LLVMTarget)
-set(MSVC_LIB_DEPS_LLVMMSP430Desc LLVMMC LLVMMSP430Info)
+set(MSVC_LIB_DEPS_LLVMMSP430Desc LLVMMC LLVMMSP430AsmPrinter LLVMMSP430Info)
set(MSVC_LIB_DEPS_LLVMMSP430Info LLVMMC LLVMSupport LLVMTarget)
set(MSVC_LIB_DEPS_LLVMMipsAsmPrinter LLVMMC LLVMSupport)
set(MSVC_LIB_DEPS_LLVMMipsCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMMipsAsmPrinter LLVMMipsDesc LLVMMipsInfo LLVMSelectionDAG LLVMSupport LLVMTarget)
-set(MSVC_LIB_DEPS_LLVMMipsDesc LLVMMC LLVMMipsInfo LLVMSupport)
+set(MSVC_LIB_DEPS_LLVMMipsDesc LLVMMC LLVMMipsAsmPrinter LLVMMipsInfo LLVMSupport)
set(MSVC_LIB_DEPS_LLVMMipsInfo LLVMMC LLVMSupport LLVMTarget)
set(MSVC_LIB_DEPS_LLVMObject LLVMSupport)
set(MSVC_LIB_DEPS_LLVMPTXCodeGen LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMPTXDesc LLVMPTXInfo LLVMSelectionDAG LLVMSupport LLVMTarget)
@@ -55,7 +55,7 @@
set(MSVC_LIB_DEPS_LLVMPTXInfo LLVMMC LLVMSupport LLVMTarget)
set(MSVC_LIB_DEPS_LLVMPowerPCAsmPrinter LLVMMC LLVMSupport)
set(MSVC_LIB_DEPS_LLVMPowerPCCodeGen LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMPowerPCAsmPrinter LLVMPowerPCDesc LLVMPowerPCInfo LLVMSelectionDAG LLVMSupport LLVMTarget)
-set(MSVC_LIB_DEPS_LLVMPowerPCDesc LLVMMC LLVMPowerPCInfo LLVMSupport)
+set(MSVC_LIB_DEPS_LLVMPowerPCDesc LLVMMC LLVMPowerPCAsmPrinter LLVMPowerPCInfo LLVMSupport)
set(MSVC_LIB_DEPS_LLVMPowerPCInfo LLVMMC LLVMSupport LLVMTarget)
set(MSVC_LIB_DEPS_LLVMRuntimeDyld LLVMObject LLVMSupport)
set(MSVC_LIB_DEPS_LLVMScalarOpts LLVMAnalysis LLVMCore LLVMInstCombine LLVMSupport LLVMTarget LLVMTransformUtils)
@@ -69,10 +69,10 @@
set(MSVC_LIB_DEPS_LLVMSystemZInfo LLVMMC LLVMSupport LLVMTarget)
set(MSVC_LIB_DEPS_LLVMTarget LLVMCore LLVMMC LLVMSupport)
set(MSVC_LIB_DEPS_LLVMTransformUtils LLVMAnalysis LLVMCore LLVMSupport LLVMTarget LLVMipa)
-set(MSVC_LIB_DEPS_LLVMX86AsmParser LLVMMC LLVMMCParser LLVMSupport LLVMTarget LLVMX86Info)
+set(MSVC_LIB_DEPS_LLVMX86AsmParser LLVMMC LLVMMCParser LLVMSupport LLVMX86Info)
set(MSVC_LIB_DEPS_LLVMX86AsmPrinter LLVMMC LLVMSupport LLVMX86Utils)
set(MSVC_LIB_DEPS_LLVMX86CodeGen LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget LLVMX86AsmPrinter LLVMX86Desc LLVMX86Info LLVMX86Utils)
-set(MSVC_LIB_DEPS_LLVMX86Desc LLVMMC LLVMSupport LLVMX86Info)
+set(MSVC_LIB_DEPS_LLVMX86Desc LLVMMC LLVMSupport LLVMX86AsmPrinter LLVMX86Info)
set(MSVC_LIB_DEPS_LLVMX86Disassembler LLVMMC LLVMSupport LLVMX86Info)
set(MSVC_LIB_DEPS_LLVMX86Info LLVMMC LLVMSupport LLVMTarget)
set(MSVC_LIB_DEPS_LLVMX86Utils LLVMCore LLVMSupport)
Modified: llvm/branches/exception-handling-rewrite/cmake/modules/TableGen.cmake
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/cmake/modules/TableGen.cmake?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/cmake/modules/TableGen.cmake (original)
+++ llvm/branches/exception-handling-rewrite/cmake/modules/TableGen.cmake Mon Jul 25 20:29:47 2011
@@ -44,3 +44,12 @@
set_source_files_properties(${CMAKE_CURRENT_BINARY_DIR}/${ofn}
PROPERTIES GENERATED 1)
endmacro(tablegen)
+
+function(add_public_tablegen_target target)
+ # Creates a target for publicly exporting tablegen dependencies.
+ if( TABLEGEN_OUTPUT )
+ add_custom_target(${target}
+ DEPENDS ${TABLEGEN_OUTPUT})
+ add_dependencies(${target} ${LLVM_COMMON_DEPENDS})
+ endif( TABLEGEN_OUTPUT )
+endfunction()
Modified: llvm/branches/exception-handling-rewrite/docs/CodeGenerator.html
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/docs/CodeGenerator.html?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/docs/CodeGenerator.html (original)
+++ llvm/branches/exception-handling-rewrite/docs/CodeGenerator.html Mon Jul 25 20:29:47 2011
@@ -1805,7 +1805,117 @@
<h3>
<a name="proepicode">Prolog/Epilog Code Insertion</a>
</h3>
-<div><p>To Be Written</p></div>
+
+<!-- _______________________________________________________________________ -->
+<h4>
+ <a name="compact_unwind">Compact Unwind</a>
+</h4>
+
+<div>
+
+<p>Unwinding out of a function is done virually via DWARF encodings. These
+ encodings exist in two forms: a Common Information Entry (CIE) and a Frame
+ Description Entry (FDE). These two tables contain the information necessary
+ for the unwinder to restore the state of the computer to before the function
+ was called. However, the tables themselves are rather large. LLVM can use a
+ "compact unwind" encoding to represent the virtual unwinding.</p>
+
+<p>The compact unwind encoding is a 32-bit value, which is encoded in an
+ architecture-specific way. It specifies which registers to restore and from
+ where, and how to unwind out of the funciton. When the linker creates a final
+ linked image, it will create a <code>__TEXT,__unwind_info</code>
+ section. This section is a small and fast way for the runtime to access
+ unwind info for any given function. If we emit compact unwind info for the
+ function, that compact unwind info will be encoded in
+ the <code>__TEXT,__unwind_info</code> section. If we emit DWARF unwind info,
+ the <code>__TEXT,__unwind_info</code> section will contain the offset of the
+ FDE in the <code>__TEXT,__eh_frame</code> section in the final linked
+ image.</p>
+
+<p>For X86, there are three modes for the compact unwind encoding:</p>
+
+<ul>
+ <dt><i>Function with a Frame Pointer (<code>EBP</code> or <code>RBP</code>)</i></dt>
+ <dd><p><code>EBP/RBP</code>-based frame, where <code>EBP/RBP</code> is pushed
+ onto the stack immediately after the return address,
+ then <code>ESP/RSP</code> is moved to <code>EBP/RBP</code>. Thus to
+ unwind, <code>ESP/RSP</code> is restored with the
+ current <code>EBP/RBP</code> value, then <code>EBP/RBP</code> is restored
+ by popping the stack, and the return is done by popping the stack once
+ more into the PC. All non-volatile registers that need to be restored must
+ have been saved in a small range on the stack that
+ starts <code>EBP-4</code> to <code>EBP-1020</code> (<code>RBP-8</code>
+ to <code>RBP-1020</code>). The offset (divided by 4) is encoded in bits
+ 16-23 (mask: <code>0x00FF0000</code>). The registers saved are encoded in
+ bits 0-14 (mask: <code>0x00007FFF</code>) as five 3-bit entries from the
+ following table:</p>
+<table border="1" cellspacing="0">
+ <tr>
+ <th>Compact Number</th>
+ <th>i386 Register</th>
+ <th>x86-64 Regiser</th>
+ </tr>
+ <tr>
+ <td>1</td>
+ <td><code>EBX</code></td>
+ <td><code>RBX</code></td>
+ </tr>
+ <tr>
+ <td>2</td>
+ <td><code>ECX</code></td>
+ <td><code>R12</code></td>
+ </tr>
+ <tr>
+ <td>3</td>
+ <td><code>EDX</code></td>
+ <td><code>R13</code></td>
+ </tr>
+ <tr>
+ <td>4</td>
+ <td><code>EDI</code></td>
+ <td><code>R14</code></td>
+ </tr>
+ <tr>
+ <td>5</td>
+ <td><code>ESI</code></td>
+ <td><code>R15</code></td>
+ </tr>
+ <tr>
+ <td>6</td>
+ <td><code>EBP</code></td>
+ <td><code>RBP</code></td>
+ </tr>
+</table>
+
+</dd>
+
+ <dt><i>Frameless with a Small Constant Stack Size (<code>EBP</code>
+ or <code>RBP</code> is not used as a frame pointer)</i></dt>
+ <dd><p>To return, a constant (encoded in the compact unwind encoding) is added
+ to the <code>ESP/RSP</code>. Then the return is done by popping the stack
+ into the PC. All non-volatile registers that need to be restored must have
+ been saved on the stack immediately after the return address. The stack
+ size (divided by 4) is encoded in bits 16-23
+ (mask: <code>0x00FF0000</code>). There is a maximum stack size of 1024
+ bytes. The number of registers saved is encoded in bits 9-12
+ (mask: <code>0x00001C00</code>). Bits 0-9 (mask:
+ <code>0x000003FF</code>) contain which registers were saved and their
+ order. (See the <code>encodeCompactUnwindRegistersWithoutFrame()</code>
+ function in <code>lib/Target/X86FrameLowering.cpp</code> for the encoding
+ algorithm.)</p></dd>
+
+ <dt><i>Frameless with a Large Constant Stack Size (<code>EBP</code>
+ or <code>RBP</code> is not used as a frame pointer)</i></dt>
+ <dd><p>This case is like the "Frameless with a Small Constant Stack Size"
+ case, but the stack size is too large to encode in the compact unwind
+ encoding. Instead it requires that the function contains "<code>subl
+ $nnnnnn, %esp</code>" in its prolog. The compact encoding contains the
+ offset to the <code>$nnnnnn</code> value in the function in bits 9-12
+ (mask: <code>0x00001C00</code>).</p></dd>
+</ul>
+
+</div>
+
<!-- ======================================================================= -->
<h3>
<a name="latemco">Late Machine Code Optimizations</a>
Modified: llvm/branches/exception-handling-rewrite/docs/LangRef.html
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/docs/LangRef.html?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/docs/LangRef.html (original)
+++ llvm/branches/exception-handling-rewrite/docs/LangRef.html Mon Jul 25 20:29:47 2011
@@ -170,6 +170,7 @@
<li><a href="#i_alloca">'<tt>alloca</tt>' Instruction</a></li>
<li><a href="#i_load">'<tt>load</tt>' Instruction</a></li>
<li><a href="#i_store">'<tt>store</tt>' Instruction</a></li>
+ <li><a href="#i_fence">'<tt>fence</tt>' Instruction</a></li>
<li><a href="#i_getelementptr">'<tt>getelementptr</tt>' Instruction</a></li>
</ol>
</li>
@@ -1247,6 +1248,14 @@
function that doesn't have an <tt>sspreq</tt> attribute or which has
an <tt>ssp</tt> attribute, then the resulting function will have
an <tt>sspreq</tt> attribute.</dd>
+
+ <dt><tt><b><a name="uwtable">uwtable</a></b></tt></dt>
+ <dd>This attribute indicates that the ABI being targeted requires that
+ an unwind table entry be produce for this function even if we can
+ show that no exceptions passes by it. This is normally the case for
+ the ELF x86-64 abi, but it can be disabled for some compilation
+ units.</dd>
+
</dl>
</div>
@@ -4544,6 +4553,63 @@
</div>
<!-- _______________________________________________________________________ -->
+<div class="doc_subsubsection"> <a name="i_fence">'<tt>fence</tt>'
+Instruction</a> </div>
+
+<div class="doc_text">
+
+<h5>Syntax:</h5>
+<pre>
+ fence [singlethread] <ordering> <i>; yields {void}</i>
+</pre>
+
+<h5>Overview:</h5>
+<p>The '<tt>fence</tt>' instruction is used to introduce happens-before edges
+between operations.</p>
+
+<h5>Arguments:</h5> <p>'<code>fence</code>' instructions take an <a
+href="#ordering">ordering</a> argument which defines what
+<i>synchronizes-with</i> edges they add. They can only be given
+<code>acquire</code>, <code>release</code>, <code>acq_rel</code>, and
+<code>seq_cst</code> orderings.</p>
+
+<h5>Semantics:</h5>
+<p>A fence <var>A</var> which has (at least) <code>release</code> ordering
+semantics <i>synchronizes with</i> a fence <var>B</var> with (at least)
+<code>acquire</code> ordering semantics if and only if there exist atomic
+operations <var>X</var> and <var>Y</var>, both operating on some atomic object
+<var>M</var>, such that <var>A</var> is sequenced before <var>X</var>,
+<var>X</var> modifies <var>M</var> (either directly or through some side effect
+of a sequence headed by <var>X</var>), <var>Y</var> is sequenced before
+<var>B</var>, and <var>Y</var> observes <var>M</var>. This provides a
+<i>happens-before</i> dependency between <var>A</var> and <var>B</var>. Rather
+than an explicit <code>fence</code>, one (but not both) of the atomic operations
+<var>X</var> or <var>Y</var> might provide a <code>release</code> or
+<code>acquire</code> (resp.) ordering constraint and still
+<i>synchronize-with</i> the explicit <code>fence</code> and establish the
+<i>happens-before</i> edge.</p>
+
+<p>A <code>fence</code> which has <code>seq_cst</code> ordering, in addition to
+having both <code>acquire</code> and <code>release</code> semantics specified
+above, participates in the global program order of other <code>seq_cst</code>
+operations and/or fences.</p>
+
+<p>The optional "<a href="#singlethread"><code>singlethread</code></a>" argument
+specifies that the fence only synchronizes with other fences in the same
+thread. (This is useful for interacting with signal handlers.)</p>
+
+<p>FIXME: This instruction is a work in progress; until it is finished, use
+ llvm.memory.barrier.
+
+<h5>Example:</h5>
+<pre>
+ fence acquire <i>; yields {void}</i>
+ fence singlethread seq_cst <i>; yields {void}</i>
+</pre>
+
+</div>
+
+<!-- _______________________________________________________________________ -->
<h4>
<a name="i_getelementptr">'<tt>getelementptr</tt>' Instruction</a>
</h4>
Modified: llvm/branches/exception-handling-rewrite/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/docs/ReleaseNotes.html?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/docs/ReleaseNotes.html (original)
+++ llvm/branches/exception-handling-rewrite/docs/ReleaseNotes.html Mon Jul 25 20:29:47 2011
@@ -639,6 +639,9 @@
<li><code>FindInsertedValue</code> (in <code>llvm/Analysis/ValueTracking.h</code>)</li>
<li><code>gep_type_begin</code> (in <code>llvm/Support/GetElementPtrTypeIterator.h</code>)</li>
<li><code>gep_type_end</code> (in <code>llvm/Support/GetElementPtrTypeIterator.h</code>)</li>
+<li><code>GetElementPtrInst::Create</code></li>
+<li><code>GetElementPtrInst::CreateInBounds</code></li>
+<li><code>GetElementPtrInst::getIndexedType</code></li>
<li><code>InsertValueInst::Create</code></li>
<li><code>InsertValueInst::getIndices</code></li>
<li><code>InvokeInst::Create</code></li>
Modified: llvm/branches/exception-handling-rewrite/docs/SourceLevelDebugging.html
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/docs/SourceLevelDebugging.html?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/docs/SourceLevelDebugging.html (original)
+++ llvm/branches/exception-handling-rewrite/docs/SourceLevelDebugging.html Mon Jul 25 20:29:47 2011
@@ -298,8 +298,8 @@
of tags are loosely bound to the tag values of DWARF information entries.
However, that does not restrict the use of the information supplied to DWARF
targets. To facilitate versioning of debug information, the tag is augmented
- with the current debug version (LLVMDebugVersion = 8 << 16 or 0x80000 or
- 524288.)</a></p>
+ with the current debug version (LLVMDebugVersion = 8 << 16 or
+ 0x80000 or 524288.)</a></p>
<p>The details of the various descriptors follow.</p>
Modified: llvm/branches/exception-handling-rewrite/include/llvm-c/Target.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/include/llvm-c/Target.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/include/llvm-c/Target.h (original)
+++ llvm/branches/exception-handling-rewrite/include/llvm-c/Target.h Mon Jul 25 20:29:47 2011
@@ -29,6 +29,7 @@
enum LLVMByteOrdering { LLVMBigEndian, LLVMLittleEndian };
typedef struct LLVMOpaqueTargetData *LLVMTargetDataRef;
+typedef struct LLVMOpaqueTargetLibraryInfotData *LLVMTargetLibraryInfoRef;
typedef struct LLVMStructLayout *LLVMStructLayoutRef;
/* Declare all of the target-initialization functions that are available. */
@@ -90,6 +91,11 @@
See the method llvm::PassManagerBase::add. */
void LLVMAddTargetData(LLVMTargetDataRef, LLVMPassManagerRef);
+/** Adds target library information to a pass manager. This does not take
+ ownership of the target library info.
+ See the method llvm::PassManagerBase::add. */
+void LLVMAddTargetLibraryInfo(LLVMTargetLibraryInfoRef, LLVMPassManagerRef);
+
/** Converts target data to a target layout string. The string must be disposed
with LLVMDisposeMessage.
See the constructor llvm::TargetData::TargetData. */
@@ -157,6 +163,7 @@
namespace llvm {
class TargetData;
+ class TargetLibraryInfo;
inline TargetData *unwrap(LLVMTargetDataRef P) {
return reinterpret_cast<TargetData*>(P);
@@ -165,6 +172,15 @@
inline LLVMTargetDataRef wrap(const TargetData *P) {
return reinterpret_cast<LLVMTargetDataRef>(const_cast<TargetData*>(P));
}
+
+ inline TargetLibraryInfo *unwrap(LLVMTargetLibraryInfoRef P) {
+ return reinterpret_cast<TargetLibraryInfo*>(P);
+ }
+
+ inline LLVMTargetLibraryInfoRef wrap(const TargetLibraryInfo *P) {
+ TargetLibraryInfo *X = const_cast<TargetLibraryInfo*>(P);
+ return reinterpret_cast<LLVMTargetLibraryInfoRef>(X);
+ }
}
#endif /* defined(__cplusplus) */
Modified: llvm/branches/exception-handling-rewrite/include/llvm-c/Transforms/Scalar.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/include/llvm-c/Transforms/Scalar.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/include/llvm-c/Transforms/Scalar.h (original)
+++ llvm/branches/exception-handling-rewrite/include/llvm-c/Transforms/Scalar.h Mon Jul 25 20:29:47 2011
@@ -107,6 +107,9 @@
/** See llvm::createEarlyCSEPass function */
void LLVMAddEarlyCSEPass(LLVMPassManagerRef PM);
+/** See llvm::createLowerExpectIntrinsicPass function */
+void LLVMAddLowerExpectIntrinsicPass(LLVMPassManagerRef PM);
+
/** See llvm::createTypeBasedAliasAnalysisPass function */
void LLVMAddTypeBasedAliasAnalysisPass(LLVMPassManagerRef PM);
Removed: llvm/branches/exception-handling-rewrite/include/llvm/Analysis/BlockFrequency.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/include/llvm/Analysis/BlockFrequency.h?rev=136039&view=auto
==============================================================================
--- llvm/branches/exception-handling-rewrite/include/llvm/Analysis/BlockFrequency.h (original)
+++ llvm/branches/exception-handling-rewrite/include/llvm/Analysis/BlockFrequency.h (removed)
@@ -1,53 +0,0 @@
-//========-------- BlockFrequency.h - Block Frequency Analysis -------========//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// Loops should be simplified before this analysis.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_ANALYSIS_BLOCKFREQUENCY_H
-#define LLVM_ANALYSIS_BLOCKFREQUENCY_H
-
-#include "llvm/Pass.h"
-#include <climits>
-
-namespace llvm {
-
-class BranchProbabilityInfo;
-template<class BlockT, class FunctionT, class BranchProbInfoT>
-class BlockFrequencyImpl;
-
-/// BlockFrequency pass uses BlockFrequencyImpl implementation to estimate
-/// IR basic block frequencies.
-class BlockFrequency : public FunctionPass {
-
- BlockFrequencyImpl<BasicBlock, Function, BranchProbabilityInfo> *BFI;
-
-public:
- static char ID;
-
- BlockFrequency();
-
- ~BlockFrequency();
-
- void getAnalysisUsage(AnalysisUsage &AU) const;
-
- bool runOnFunction(Function &F);
-
- /// getblockFreq - Return block frequency. Return 0 if we don't have the
- /// information. Please note that initial frequency is equal to 1024. It means
- /// that we should not rely on the value itself, but only on the comparison to
- /// the other block frequencies. We do this to avoid using of floating points.
- ///
- uint32_t getBlockFreq(BasicBlock *BB);
-};
-
-}
-
-#endif
Modified: llvm/branches/exception-handling-rewrite/include/llvm/Analysis/BlockFrequencyImpl.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/include/llvm/Analysis/BlockFrequencyImpl.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/include/llvm/Analysis/BlockFrequencyImpl.h (original)
+++ llvm/branches/exception-handling-rewrite/include/llvm/Analysis/BlockFrequencyImpl.h Mon Jul 25 20:29:47 2011
@@ -29,8 +29,8 @@
namespace llvm {
-class BlockFrequency;
-class MachineBlockFrequency;
+class BlockFrequencyInfo;
+class MachineBlockFrequencyInfo;
/// BlockFrequencyImpl implements block frequency algorithm for IR and
/// Machine Instructions. Algorithm starts with value 1024 (START_FREQ)
@@ -263,8 +263,8 @@
}
}
- friend class BlockFrequency;
- friend class MachineBlockFrequency;
+ friend class BlockFrequencyInfo;
+ friend class MachineBlockFrequencyInfo;
void doFunction(FunctionT *fn, BlockProbInfoT *bpi) {
Fn = fn;
Modified: llvm/branches/exception-handling-rewrite/include/llvm/Bitcode/LLVMBitCodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/include/llvm/Bitcode/LLVMBitCodes.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/include/llvm/Bitcode/LLVMBitCodes.h (original)
+++ llvm/branches/exception-handling-rewrite/include/llvm/Bitcode/LLVMBitCodes.h Mon Jul 25 20:29:47 2011
@@ -218,6 +218,23 @@
PEO_EXACT = 0
};
+ /// Encoded AtomicOrdering values.
+ enum AtomicOrderingCodes {
+ ORDERING_NOTATOMIC = 0,
+ ORDERING_UNORDERED = 1,
+ ORDERING_MONOTONIC = 2,
+ ORDERING_ACQUIRE = 3,
+ ORDERING_RELEASE = 4,
+ ORDERING_ACQREL = 5,
+ ORDERING_SEQCST = 6
+ };
+
+ /// Encoded SynchronizationScope values.
+ enum AtomicSynchScopeCodes {
+ SYNCHSCOPE_SINGLETHREAD = 0,
+ SYNCHSCOPE_CROSSTHREAD = 1
+ };
+
// The function body block (FUNCTION_BLOCK_ID) describes function bodies. It
// can contain a constant block (CONSTANTS_BLOCK_ID).
enum FunctionCodes {
@@ -266,9 +283,9 @@
FUNC_CODE_INST_CALL = 34, // CALL: [attr, fnty, fnid, args...]
- FUNC_CODE_INST_LANDINGPAD = 35, // LANDINGPAD: [ty, val, num, id0,val0 ...]
-
- FUNC_CODE_DEBUG_LOC = 36 // DEBUG_LOC: [Line,Col,ScopeVal, IAVal]
+ FUNC_CODE_DEBUG_LOC = 35, // DEBUG_LOC: [Line,Col,ScopeVal, IAVal]
+ FUNC_CODE_INST_FENCE = 36, // FENCE: [ordering, synchscope]
+ FUNC_CODE_INST_LANDINGPAD = 37 // LANDINGPAD: [ty, val, num, id0,val0 ...]
};
} // End bitc namespace
} // End llvm namespace
Removed: llvm/branches/exception-handling-rewrite/include/llvm/CodeGen/MachineBlockFrequency.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/include/llvm/CodeGen/MachineBlockFrequency.h?rev=136039&view=auto
==============================================================================
--- llvm/branches/exception-handling-rewrite/include/llvm/CodeGen/MachineBlockFrequency.h (original)
+++ llvm/branches/exception-handling-rewrite/include/llvm/CodeGen/MachineBlockFrequency.h (removed)
@@ -1,53 +0,0 @@
-//====----- MachineBlockFrequency.h - MachineBlock Frequency Analysis ----====//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// Loops should be simplified before this analysis.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_CODEGEN_MACHINEBLOCKFREQUENCY_H
-#define LLVM_CODEGEN_MACHINEBLOCKFREQUENCY_H
-
-#include "llvm/CodeGen/MachineFunctionPass.h"
-#include <climits>
-
-namespace llvm {
-
-class MachineBranchProbabilityInfo;
-template<class BlockT, class FunctionT, class BranchProbInfoT>
-class BlockFrequencyImpl;
-
-/// MachineBlockFrequency pass uses BlockFrequencyImpl implementation to estimate
-/// machine basic block frequencies.
-class MachineBlockFrequency : public MachineFunctionPass {
-
- BlockFrequencyImpl<MachineBasicBlock, MachineFunction, MachineBranchProbabilityInfo> *MBFI;
-
-public:
- static char ID;
-
- MachineBlockFrequency();
-
- ~MachineBlockFrequency();
-
- void getAnalysisUsage(AnalysisUsage &AU) const;
-
- bool runOnMachineFunction(MachineFunction &F);
-
- /// getblockFreq - Return block frequency. Return 0 if we don't have the
- /// information. Please note that initial frequency is equal to 1024. It means
- /// that we should not rely on the value itself, but only on the comparison to
- /// the other block frequencies. We do this to avoid using of floating points.
- ///
- uint32_t getBlockFreq(MachineBasicBlock *MBB);
-};
-
-}
-
-#endif
Modified: llvm/branches/exception-handling-rewrite/include/llvm/Constants.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/include/llvm/Constants.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/include/llvm/Constants.h (original)
+++ llvm/branches/exception-handling-rewrite/include/llvm/Constants.h Mon Jul 25 20:29:47 2011
@@ -329,7 +329,7 @@
std::vector<Constant*> >;
ConstantArray(const ConstantArray &); // DO NOT IMPLEMENT
protected:
- ConstantArray(ArrayType *T, const std::vector<Constant*> &Val);
+ ConstantArray(ArrayType *T, ArrayRef<Constant *> Val);
public:
// ConstantArray accessors
static Constant *get(ArrayType *T, ArrayRef<Constant*> V);
@@ -400,7 +400,7 @@
std::vector<Constant*> >;
ConstantStruct(const ConstantStruct &); // DO NOT IMPLEMENT
protected:
- ConstantStruct(StructType *T, const std::vector<Constant*> &Val);
+ ConstantStruct(StructType *T, ArrayRef<Constant *> Val);
public:
// ConstantStruct accessors
static Constant *get(StructType *T, ArrayRef<Constant*> V);
@@ -461,7 +461,7 @@
std::vector<Constant*> >;
ConstantVector(const ConstantVector &); // DO NOT IMPLEMENT
protected:
- ConstantVector(VectorType *T, const std::vector<Constant*> &Val);
+ ConstantVector(VectorType *T, ArrayRef<Constant *> Val);
public:
// ConstantVector accessors
static Constant *get(ArrayRef<Constant*> V);
Modified: llvm/branches/exception-handling-rewrite/include/llvm/InitializePasses.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/include/llvm/InitializePasses.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/include/llvm/InitializePasses.h (original)
+++ llvm/branches/exception-handling-rewrite/include/llvm/InitializePasses.h Mon Jul 25 20:29:47 2011
@@ -65,7 +65,7 @@
void initializeBasicAliasAnalysisPass(PassRegistry&);
void initializeBasicCallGraphPass(PassRegistry&);
void initializeBlockExtractorPassPass(PassRegistry&);
-void initializeBlockFrequencyPass(PassRegistry&);
+void initializeBlockFrequencyInfoPass(PassRegistry&);
void initializeBlockPlacementPass(PassRegistry&);
void initializeBranchProbabilityInfoPass(PassRegistry&);
void initializeBreakCriticalEdgesPass(PassRegistry&);
@@ -145,7 +145,7 @@
void initializeLowerInvokePass(PassRegistry&);
void initializeLowerSetJmpPass(PassRegistry&);
void initializeLowerSwitchPass(PassRegistry&);
-void initializeMachineBlockFrequencyPass(PassRegistry&);
+void initializeMachineBlockFrequencyInfoPass(PassRegistry&);
void initializeMachineBranchProbabilityInfoPass(PassRegistry&);
void initializeMachineCSEPass(PassRegistry&);
void initializeMachineDominatorTreePass(PassRegistry&);
Modified: llvm/branches/exception-handling-rewrite/include/llvm/Instruction.def
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/include/llvm/Instruction.def?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/include/llvm/Instruction.def (original)
+++ llvm/branches/exception-handling-rewrite/include/llvm/Instruction.def Mon Jul 25 20:29:47 2011
@@ -134,43 +134,44 @@
HANDLE_MEMORY_INST(28, Load , LoadInst ) // Memory manipulation instrs
HANDLE_MEMORY_INST(29, Store , StoreInst )
HANDLE_MEMORY_INST(30, GetElementPtr, GetElementPtrInst)
- LAST_MEMORY_INST(30)
+HANDLE_MEMORY_INST(31, Fence , FenceInst )
+ LAST_MEMORY_INST(31)
// Cast operators ...
// NOTE: The order matters here because CastInst::isEliminableCastPair
// NOTE: (see Instructions.cpp) encodes a table based on this ordering.
- FIRST_CAST_INST(31)
-HANDLE_CAST_INST(31, Trunc , TruncInst ) // Truncate integers
-HANDLE_CAST_INST(32, ZExt , ZExtInst ) // Zero extend integers
-HANDLE_CAST_INST(33, SExt , SExtInst ) // Sign extend integers
-HANDLE_CAST_INST(34, FPToUI , FPToUIInst ) // floating point -> UInt
-HANDLE_CAST_INST(35, FPToSI , FPToSIInst ) // floating point -> SInt
-HANDLE_CAST_INST(36, UIToFP , UIToFPInst ) // UInt -> floating point
-HANDLE_CAST_INST(37, SIToFP , SIToFPInst ) // SInt -> floating point
-HANDLE_CAST_INST(38, FPTrunc , FPTruncInst ) // Truncate floating point
-HANDLE_CAST_INST(39, FPExt , FPExtInst ) // Extend floating point
-HANDLE_CAST_INST(40, PtrToInt, PtrToIntInst) // Pointer -> Integer
-HANDLE_CAST_INST(41, IntToPtr, IntToPtrInst) // Integer -> Pointer
-HANDLE_CAST_INST(42, BitCast , BitCastInst ) // Type cast
- LAST_CAST_INST(42)
+ FIRST_CAST_INST(32)
+HANDLE_CAST_INST(32, Trunc , TruncInst ) // Truncate integers
+HANDLE_CAST_INST(33, ZExt , ZExtInst ) // Zero extend integers
+HANDLE_CAST_INST(34, SExt , SExtInst ) // Sign extend integers
+HANDLE_CAST_INST(35, FPToUI , FPToUIInst ) // floating point -> UInt
+HANDLE_CAST_INST(36, FPToSI , FPToSIInst ) // floating point -> SInt
+HANDLE_CAST_INST(37, UIToFP , UIToFPInst ) // UInt -> floating point
+HANDLE_CAST_INST(38, SIToFP , SIToFPInst ) // SInt -> floating point
+HANDLE_CAST_INST(39, FPTrunc , FPTruncInst ) // Truncate floating point
+HANDLE_CAST_INST(40, FPExt , FPExtInst ) // Extend floating point
+HANDLE_CAST_INST(41, PtrToInt, PtrToIntInst) // Pointer -> Integer
+HANDLE_CAST_INST(42, IntToPtr, IntToPtrInst) // Integer -> Pointer
+HANDLE_CAST_INST(43, BitCast , BitCastInst ) // Type cast
+ LAST_CAST_INST(43)
// Other operators...
- FIRST_OTHER_INST(43)
-HANDLE_OTHER_INST(43, ICmp , ICmpInst ) // Integer comparison instruction
-HANDLE_OTHER_INST(44, FCmp , FCmpInst ) // Floating point comparison instr.
-HANDLE_OTHER_INST(45, PHI , PHINode ) // PHI node instruction
-HANDLE_OTHER_INST(46, Call , CallInst ) // Call a function
-HANDLE_OTHER_INST(47, Select , SelectInst ) // select instruction
-HANDLE_OTHER_INST(48, UserOp1, Instruction) // May be used internally in a pass
-HANDLE_OTHER_INST(49, UserOp2, Instruction) // Internal to passes only
-HANDLE_OTHER_INST(50, VAArg , VAArgInst ) // vaarg instruction
-HANDLE_OTHER_INST(51, ExtractElement, ExtractElementInst)// extract from vector
-HANDLE_OTHER_INST(52, InsertElement, InsertElementInst) // insert into vector
-HANDLE_OTHER_INST(53, ShuffleVector, ShuffleVectorInst) // shuffle two vectors.
-HANDLE_OTHER_INST(54, ExtractValue, ExtractValueInst)// extract from aggregate
-HANDLE_OTHER_INST(55, InsertValue, InsertValueInst) // insert into aggregate
-HANDLE_OTHER_INST(56, LandingPad, LandingPadInst) // Landing pad instruction.
- LAST_OTHER_INST(56)
+ FIRST_OTHER_INST(44)
+HANDLE_OTHER_INST(44, ICmp , ICmpInst ) // Integer comparison instruction
+HANDLE_OTHER_INST(45, FCmp , FCmpInst ) // Floating point comparison instr.
+HANDLE_OTHER_INST(46, PHI , PHINode ) // PHI node instruction
+HANDLE_OTHER_INST(47, Call , CallInst ) // Call a function
+HANDLE_OTHER_INST(48, Select , SelectInst ) // select instruction
+HANDLE_OTHER_INST(49, UserOp1, Instruction) // May be used internally in a pass
+HANDLE_OTHER_INST(50, UserOp2, Instruction) // Internal to passes only
+HANDLE_OTHER_INST(51, VAArg , VAArgInst ) // vaarg instruction
+HANDLE_OTHER_INST(52, ExtractElement, ExtractElementInst)// extract from vector
+HANDLE_OTHER_INST(53, InsertElement, InsertElementInst) // insert into vector
+HANDLE_OTHER_INST(54, ShuffleVector, ShuffleVectorInst) // shuffle two vectors.
+HANDLE_OTHER_INST(55, ExtractValue, ExtractValueInst)// extract from aggregate
+HANDLE_OTHER_INST(56, InsertValue, InsertValueInst) // insert into aggregate
+HANDLE_OTHER_INST(57, LandingPad, LandingPadInst) // Landing pad instruction.
+ LAST_OTHER_INST(57)
#undef FIRST_TERM_INST
#undef HANDLE_TERM_INST
Modified: llvm/branches/exception-handling-rewrite/include/llvm/Instructions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/include/llvm/Instructions.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/include/llvm/Instructions.h (original)
+++ llvm/branches/exception-handling-rewrite/include/llvm/Instructions.h Mon Jul 25 20:29:47 2011
@@ -22,6 +22,7 @@
#include "llvm/CallingConv.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/SmallVector.h"
+#include "llvm/Support/ErrorHandling.h"
#include <iterator>
namespace llvm {
@@ -31,6 +32,22 @@
class APInt;
class LLVMContext;
+enum AtomicOrdering {
+ NotAtomic = 0,
+ Unordered = 1,
+ Monotonic = 2,
+ // Consume = 3, // Not specified yet.
+ Acquire = 4,
+ Release = 5,
+ AcquireRelease = 6,
+ SequentiallyConsistent = 7
+};
+
+enum SynchronizationScope {
+ SingleThread = 0,
+ CrossThread = 1
+};
+
//===----------------------------------------------------------------------===//
// AllocaInst Class
//===----------------------------------------------------------------------===//
@@ -269,6 +286,82 @@
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(StoreInst, Value)
//===----------------------------------------------------------------------===//
+// FenceInst Class
+//===----------------------------------------------------------------------===//
+
+/// FenceInst - an instruction for ordering other memory operations
+///
+class FenceInst : public Instruction {
+ void *operator new(size_t, unsigned); // DO NOT IMPLEMENT
+ void Init(AtomicOrdering Ordering, SynchronizationScope SynchScope);
+protected:
+ virtual FenceInst *clone_impl() const;
+public:
+ // allocate space for exactly zero operands
+ void *operator new(size_t s) {
+ return User::operator new(s, 0);
+ }
+
+ // Ordering may only be Acquire, Release, AcquireRelease, or
+ // SequentiallyConsistent.
+ FenceInst(LLVMContext &C, AtomicOrdering Ordering,
+ SynchronizationScope SynchScope = CrossThread,
+ Instruction *InsertBefore = 0);
+ FenceInst(LLVMContext &C, AtomicOrdering Ordering,
+ SynchronizationScope SynchScope,
+ BasicBlock *InsertAtEnd);
+
+ /// Returns the ordering effect of this fence.
+ AtomicOrdering getOrdering() const {
+ return AtomicOrdering(getSubclassDataFromInstruction() >> 1);
+ }
+
+ /// Set the ordering constraint on this fence. May only be Acquire, Release,
+ /// AcquireRelease, or SequentiallyConsistent.
+ void setOrdering(AtomicOrdering Ordering) {
+ switch (Ordering) {
+ case Acquire:
+ case Release:
+ case AcquireRelease:
+ case SequentiallyConsistent:
+ setInstructionSubclassData((getSubclassDataFromInstruction() & 1) |
+ (Ordering << 1));
+ return;
+ default:
+ llvm_unreachable("FenceInst ordering must be Acquire, Release,"
+ " AcquireRelease, or SequentiallyConsistent");
+ }
+ }
+
+ SynchronizationScope getSynchScope() const {
+ return SynchronizationScope(getSubclassDataFromInstruction() & 1);
+ }
+
+ /// Specify whether this fence orders other operations with respect to all
+ /// concurrently executing threads, or only with respect to signal handlers
+ /// executing in the same thread.
+ void setSynchScope(SynchronizationScope xthread) {
+ setInstructionSubclassData((getSubclassDataFromInstruction() & ~1) |
+ xthread);
+ }
+
+ // Methods for support type inquiry through isa, cast, and dyn_cast:
+ static inline bool classof(const FenceInst *) { return true; }
+ static inline bool classof(const Instruction *I) {
+ return I->getOpcode() == Instruction::Fence;
+ }
+ static inline bool classof(const Value *V) {
+ return isa<Instruction>(V) && classof(cast<Instruction>(V));
+ }
+private:
+ // Shadow Instruction::setInstructionSubclassData with a private forwarding
+ // method so that subclasses cannot accidentally use it.
+ void setInstructionSubclassData(unsigned short D) {
+ Instruction::setInstructionSubclassData(D);
+ }
+};
+
+//===----------------------------------------------------------------------===//
// GetElementPtrInst Class
//===----------------------------------------------------------------------===//
@@ -285,149 +378,51 @@
///
class GetElementPtrInst : public Instruction {
GetElementPtrInst(const GetElementPtrInst &GEPI);
- void init(Value *Ptr, Value* const *Idx, unsigned NumIdx,
- const Twine &NameStr);
- void init(Value *Ptr, Value *Idx, const Twine &NameStr);
-
- template<typename RandomAccessIterator>
- void init(Value *Ptr,
- RandomAccessIterator IdxBegin,
- RandomAccessIterator IdxEnd,
- const Twine &NameStr,
- // This argument ensures that we have an iterator we can
- // do arithmetic on in constant time
- std::random_access_iterator_tag) {
- unsigned NumIdx = static_cast<unsigned>(std::distance(IdxBegin, IdxEnd));
-
- if (NumIdx > 0) {
- // This requires that the iterator points to contiguous memory.
- init(Ptr, &*IdxBegin, NumIdx, NameStr); // FIXME: for the general case
- // we have to build an array here
- }
- else {
- init(Ptr, 0, NumIdx, NameStr);
- }
- }
-
- /// getIndexedType - Returns the type of the element that would be loaded with
- /// a load instruction with the specified parameters.
- ///
- /// Null is returned if the indices are invalid for the specified
- /// pointer type.
- ///
- template<typename RandomAccessIterator>
- static Type *getIndexedType(Type *Ptr,
- RandomAccessIterator IdxBegin,
- RandomAccessIterator IdxEnd,
- // This argument ensures that we
- // have an iterator we can do
- // arithmetic on in constant time
- std::random_access_iterator_tag) {
- unsigned NumIdx = static_cast<unsigned>(std::distance(IdxBegin, IdxEnd));
-
- if (NumIdx > 0)
- // This requires that the iterator points to contiguous memory.
- return getIndexedType(Ptr, &*IdxBegin, NumIdx);
- else
- return getIndexedType(Ptr, (Value *const*)0, NumIdx);
- }
+ void init(Value *Ptr, ArrayRef<Value *> IdxList, const Twine &NameStr);
/// Constructors - Create a getelementptr instruction with a base pointer an
/// list of indices. The first ctor can optionally insert before an existing
/// instruction, the second appends the new instruction to the specified
/// BasicBlock.
- template<typename RandomAccessIterator>
- inline GetElementPtrInst(Value *Ptr, RandomAccessIterator IdxBegin,
- RandomAccessIterator IdxEnd,
- unsigned Values,
- const Twine &NameStr,
+ inline GetElementPtrInst(Value *Ptr, ArrayRef<Value *> IdxList,
+ unsigned Values, const Twine &NameStr,
Instruction *InsertBefore);
- template<typename RandomAccessIterator>
- inline GetElementPtrInst(Value *Ptr,
- RandomAccessIterator IdxBegin,
- RandomAccessIterator IdxEnd,
- unsigned Values,
- const Twine &NameStr, BasicBlock *InsertAtEnd);
-
- /// Constructors - These two constructors are convenience methods because one
- /// and two index getelementptr instructions are so common.
- GetElementPtrInst(Value *Ptr, Value *Idx, const Twine &NameStr = "",
- Instruction *InsertBefore = 0);
- GetElementPtrInst(Value *Ptr, Value *Idx,
- const Twine &NameStr, BasicBlock *InsertAtEnd);
+ inline GetElementPtrInst(Value *Ptr, ArrayRef<Value *> IdxList,
+ unsigned Values, const Twine &NameStr,
+ BasicBlock *InsertAtEnd);
protected:
virtual GetElementPtrInst *clone_impl() const;
public:
- template<typename RandomAccessIterator>
- static GetElementPtrInst *Create(Value *Ptr, RandomAccessIterator IdxBegin,
- RandomAccessIterator IdxEnd,
+ static GetElementPtrInst *Create(Value *Ptr, ArrayRef<Value *> IdxList,
const Twine &NameStr = "",
Instruction *InsertBefore = 0) {
- typename std::iterator_traits<RandomAccessIterator>::difference_type
- Values = 1 + std::distance(IdxBegin, IdxEnd);
+ unsigned Values = 1 + unsigned(IdxList.size());
return new(Values)
- GetElementPtrInst(Ptr, IdxBegin, IdxEnd, Values, NameStr, InsertBefore);
+ GetElementPtrInst(Ptr, IdxList, Values, NameStr, InsertBefore);
}
- template<typename RandomAccessIterator>
- static GetElementPtrInst *Create(Value *Ptr,
- RandomAccessIterator IdxBegin,
- RandomAccessIterator IdxEnd,
+ static GetElementPtrInst *Create(Value *Ptr, ArrayRef<Value *> IdxList,
const Twine &NameStr,
BasicBlock *InsertAtEnd) {
- typename std::iterator_traits<RandomAccessIterator>::difference_type
- Values = 1 + std::distance(IdxBegin, IdxEnd);
+ unsigned Values = 1 + unsigned(IdxList.size());
return new(Values)
- GetElementPtrInst(Ptr, IdxBegin, IdxEnd, Values, NameStr, InsertAtEnd);
- }
-
- /// Constructors - These two creators are convenience methods because one
- /// index getelementptr instructions are so common.
- static GetElementPtrInst *Create(Value *Ptr, Value *Idx,
- const Twine &NameStr = "",
- Instruction *InsertBefore = 0) {
- return new(2) GetElementPtrInst(Ptr, Idx, NameStr, InsertBefore);
- }
- static GetElementPtrInst *Create(Value *Ptr, Value *Idx,
- const Twine &NameStr,
- BasicBlock *InsertAtEnd) {
- return new(2) GetElementPtrInst(Ptr, Idx, NameStr, InsertAtEnd);
+ GetElementPtrInst(Ptr, IdxList, Values, NameStr, InsertAtEnd);
}
/// Create an "inbounds" getelementptr. See the documentation for the
/// "inbounds" flag in LangRef.html for details.
- template<typename RandomAccessIterator>
static GetElementPtrInst *CreateInBounds(Value *Ptr,
- RandomAccessIterator IdxBegin,
- RandomAccessIterator IdxEnd,
+ ArrayRef<Value *> IdxList,
const Twine &NameStr = "",
Instruction *InsertBefore = 0) {
- GetElementPtrInst *GEP = Create(Ptr, IdxBegin, IdxEnd,
- NameStr, InsertBefore);
+ GetElementPtrInst *GEP = Create(Ptr, IdxList, NameStr, InsertBefore);
GEP->setIsInBounds(true);
return GEP;
}
- template<typename RandomAccessIterator>
static GetElementPtrInst *CreateInBounds(Value *Ptr,
- RandomAccessIterator IdxBegin,
- RandomAccessIterator IdxEnd,
- const Twine &NameStr,
- BasicBlock *InsertAtEnd) {
- GetElementPtrInst *GEP = Create(Ptr, IdxBegin, IdxEnd,
- NameStr, InsertAtEnd);
- GEP->setIsInBounds(true);
- return GEP;
- }
- static GetElementPtrInst *CreateInBounds(Value *Ptr, Value *Idx,
- const Twine &NameStr = "",
- Instruction *InsertBefore = 0) {
- GetElementPtrInst *GEP = Create(Ptr, Idx, NameStr, InsertBefore);
- GEP->setIsInBounds(true);
- return GEP;
- }
- static GetElementPtrInst *CreateInBounds(Value *Ptr, Value *Idx,
+ ArrayRef<Value *> IdxList,
const Twine &NameStr,
BasicBlock *InsertAtEnd) {
- GetElementPtrInst *GEP = Create(Ptr, Idx, NameStr, InsertAtEnd);
+ GetElementPtrInst *GEP = Create(Ptr, IdxList, NameStr, InsertAtEnd);
GEP->setIsInBounds(true);
return GEP;
}
@@ -446,23 +441,9 @@
/// Null is returned if the indices are invalid for the specified
/// pointer type.
///
- template<typename RandomAccessIterator>
- static Type *getIndexedType(Type *Ptr, RandomAccessIterator IdxBegin,
- RandomAccessIterator IdxEnd) {
- return getIndexedType(Ptr, IdxBegin, IdxEnd,
- typename std::iterator_traits<RandomAccessIterator>::
- iterator_category());
- }
-
- // FIXME: Use ArrayRef
- static Type *getIndexedType(Type *Ptr,
- Value* const *Idx, unsigned NumIdx);
- static Type *getIndexedType(Type *Ptr,
- Constant* const *Idx, unsigned NumIdx);
-
- static Type *getIndexedType(Type *Ptr,
- uint64_t const *Idx, unsigned NumIdx);
- static Type *getIndexedType(Type *Ptr, Value *Idx);
+ static Type *getIndexedType(Type *Ptr, ArrayRef<Value *> IdxList);
+ static Type *getIndexedType(Type *Ptr, ArrayRef<Constant *> IdxList);
+ static Type *getIndexedType(Type *Ptr, ArrayRef<uint64_t> IdxList);
inline op_iterator idx_begin() { return op_begin()+1; }
inline const_op_iterator idx_begin() const { return op_begin()+1; }
@@ -530,43 +511,33 @@
public VariadicOperandTraits<GetElementPtrInst, 1> {
};
-template<typename RandomAccessIterator>
GetElementPtrInst::GetElementPtrInst(Value *Ptr,
- RandomAccessIterator IdxBegin,
- RandomAccessIterator IdxEnd,
+ ArrayRef<Value *> IdxList,
unsigned Values,
const Twine &NameStr,
Instruction *InsertBefore)
: Instruction(PointerType::get(checkGEPType(
- getIndexedType(Ptr->getType(),
- IdxBegin, IdxEnd)),
+ getIndexedType(Ptr->getType(), IdxList)),
cast<PointerType>(Ptr->getType())
->getAddressSpace()),
GetElementPtr,
OperandTraits<GetElementPtrInst>::op_end(this) - Values,
Values, InsertBefore) {
- init(Ptr, IdxBegin, IdxEnd, NameStr,
- typename std::iterator_traits<RandomAccessIterator>
- ::iterator_category());
+ init(Ptr, IdxList, NameStr);
}
-template<typename RandomAccessIterator>
GetElementPtrInst::GetElementPtrInst(Value *Ptr,
- RandomAccessIterator IdxBegin,
- RandomAccessIterator IdxEnd,
+ ArrayRef<Value *> IdxList,
unsigned Values,
const Twine &NameStr,
BasicBlock *InsertAtEnd)
: Instruction(PointerType::get(checkGEPType(
- getIndexedType(Ptr->getType(),
- IdxBegin, IdxEnd)),
+ getIndexedType(Ptr->getType(), IdxList)),
cast<PointerType>(Ptr->getType())
->getAddressSpace()),
GetElementPtr,
OperandTraits<GetElementPtrInst>::op_end(this) - Values,
Values, InsertAtEnd) {
- init(Ptr, IdxBegin, IdxEnd, NameStr,
- typename std::iterator_traits<RandomAccessIterator>
- ::iterator_category());
+ init(Ptr, IdxList, NameStr);
}
Modified: llvm/branches/exception-handling-rewrite/include/llvm/MC/MCAssembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/include/llvm/MC/MCAssembler.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/include/llvm/MC/MCAssembler.h (original)
+++ llvm/branches/exception-handling-rewrite/include/llvm/MC/MCAssembler.h Mon Jul 25 20:29:47 2011
@@ -10,14 +10,14 @@
#ifndef LLVM_MC_MCASSEMBLER_H
#define LLVM_MC_MCASSEMBLER_H
+#include "llvm/MC/MCFixup.h"
+#include "llvm/MC/MCInst.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallString.h"
#include "llvm/ADT/ilist.h"
#include "llvm/ADT/ilist_node.h"
#include "llvm/Support/Casting.h"
-#include "llvm/MC/MCFixup.h"
-#include "llvm/MC/MCInst.h"
#include "llvm/Support/DataTypes.h"
#include <vector> // FIXME: Shouldn't be needed.
@@ -36,7 +36,7 @@
class MCSymbol;
class MCSymbolData;
class MCValue;
-class TargetAsmBackend;
+class MCAsmBackend;
class MCFragment : public ilist_node<MCFragment> {
friend class MCAsmLayout;
@@ -660,7 +660,7 @@
MCContext &Context;
- TargetAsmBackend &Backend;
+ MCAsmBackend &Backend;
MCCodeEmitter &Emitter;
@@ -780,14 +780,14 @@
// concrete and require clients to pass in a target like object. The other
// option is to make this abstract, and have targets provide concrete
// implementations as we do with AsmParser.
- MCAssembler(MCContext &Context_, TargetAsmBackend &Backend_,
+ MCAssembler(MCContext &Context_, MCAsmBackend &Backend_,
MCCodeEmitter &Emitter_, MCObjectWriter &Writer_,
raw_ostream &OS);
~MCAssembler();
MCContext &getContext() const { return Context; }
- TargetAsmBackend &getBackend() const { return Backend; }
+ MCAsmBackend &getBackend() const { return Backend; }
MCCodeEmitter &getEmitter() const { return Emitter; }
Modified: llvm/branches/exception-handling-rewrite/include/llvm/MC/MCObjectStreamer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/include/llvm/MC/MCObjectStreamer.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/include/llvm/MC/MCObjectStreamer.h (original)
+++ llvm/branches/exception-handling-rewrite/include/llvm/MC/MCObjectStreamer.h Mon Jul 25 20:29:47 2011
@@ -19,7 +19,7 @@
class MCExpr;
class MCFragment;
class MCDataFragment;
-class TargetAsmBackend;
+class MCAsmBackend;
class raw_ostream;
/// \brief Streaming object file generation interface.
@@ -36,9 +36,9 @@
virtual void EmitInstToData(const MCInst &Inst) = 0;
protected:
- MCObjectStreamer(MCContext &Context, TargetAsmBackend &TAB,
+ MCObjectStreamer(MCContext &Context, MCAsmBackend &TAB,
raw_ostream &_OS, MCCodeEmitter *_Emitter);
- MCObjectStreamer(MCContext &Context, TargetAsmBackend &TAB,
+ MCObjectStreamer(MCContext &Context, MCAsmBackend &TAB,
raw_ostream &_OS, MCCodeEmitter *_Emitter,
MCAssembler *_Assembler);
~MCObjectStreamer();
Modified: llvm/branches/exception-handling-rewrite/include/llvm/MC/MCParser/MCAsmLexer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/include/llvm/MC/MCParser/MCAsmLexer.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/include/llvm/MC/MCParser/MCAsmLexer.h (original)
+++ llvm/branches/exception-handling-rewrite/include/llvm/MC/MCParser/MCAsmLexer.h Mon Jul 25 20:29:47 2011
@@ -36,7 +36,7 @@
// Real values.
Real,
- // Register values (stored in IntVal). Only used by TargetAsmLexer.
+ // Register values (stored in IntVal). Only used by MCTargetAsmLexer.
Register,
// No-value.
Modified: llvm/branches/exception-handling-rewrite/include/llvm/MC/MCParser/MCAsmParser.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/include/llvm/MC/MCParser/MCAsmParser.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/include/llvm/MC/MCParser/MCAsmParser.h (original)
+++ llvm/branches/exception-handling-rewrite/include/llvm/MC/MCParser/MCAsmParser.h Mon Jul 25 20:29:47 2011
@@ -20,11 +20,11 @@
class MCContext;
class MCExpr;
class MCStreamer;
+class MCTargetAsmParser;
class SMLoc;
class SourceMgr;
class StringRef;
class Target;
-class TargetAsmParser;
class Twine;
/// MCAsmParser - Generic assembler parser interface, for use by target specific
@@ -37,7 +37,7 @@
MCAsmParser(const MCAsmParser &); // DO NOT IMPLEMENT
void operator=(const MCAsmParser &); // DO NOT IMPLEMENT
- TargetAsmParser *TargetParser;
+ MCTargetAsmParser *TargetParser;
unsigned ShowParsedOperands : 1;
@@ -60,8 +60,8 @@
/// getStreamer - Return the output streamer for the assembler.
virtual MCStreamer &getStreamer() = 0;
- TargetAsmParser &getTargetParser() const { return *TargetParser; }
- void setTargetParser(TargetAsmParser &P);
+ MCTargetAsmParser &getTargetParser() const { return *TargetParser; }
+ void setTargetParser(MCTargetAsmParser &P);
bool getShowParsedOperands() const { return ShowParsedOperands; }
void setShowParsedOperands(bool Value) { ShowParsedOperands = Value; }
Modified: llvm/branches/exception-handling-rewrite/include/llvm/MC/MCStreamer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/include/llvm/MC/MCStreamer.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/include/llvm/MC/MCStreamer.h (original)
+++ llvm/branches/exception-handling-rewrite/include/llvm/MC/MCStreamer.h Mon Jul 25 20:29:47 2011
@@ -22,6 +22,7 @@
#include "llvm/ADT/SmallVector.h"
namespace llvm {
+ class MCAsmBackend;
class MCAsmInfo;
class MCCodeEmitter;
class MCContext;
@@ -31,7 +32,6 @@
class MCSection;
class MCSymbol;
class StringRef;
- class TargetAsmBackend;
class TargetLoweringObjectFile;
class Twine;
class raw_ostream;
@@ -563,14 +563,14 @@
bool useCFI,
MCInstPrinter *InstPrint = 0,
MCCodeEmitter *CE = 0,
- TargetAsmBackend *TAB = 0,
+ MCAsmBackend *TAB = 0,
bool ShowInst = false);
/// createMachOStreamer - Create a machine code streamer which will generate
/// Mach-O format object files.
///
/// Takes ownership of \arg TAB and \arg CE.
- MCStreamer *createMachOStreamer(MCContext &Ctx, TargetAsmBackend &TAB,
+ MCStreamer *createMachOStreamer(MCContext &Ctx, MCAsmBackend &TAB,
raw_ostream &OS, MCCodeEmitter *CE,
bool RelaxAll = false);
@@ -579,13 +579,13 @@
///
/// Takes ownership of \arg TAB and \arg CE.
MCStreamer *createWinCOFFStreamer(MCContext &Ctx,
- TargetAsmBackend &TAB,
+ MCAsmBackend &TAB,
MCCodeEmitter &CE, raw_ostream &OS,
bool RelaxAll = false);
/// createELFStreamer - Create a machine code streamer which will generate
/// ELF format object files.
- MCStreamer *createELFStreamer(MCContext &Ctx, TargetAsmBackend &TAB,
+ MCStreamer *createELFStreamer(MCContext &Ctx, MCAsmBackend &TAB,
raw_ostream &OS, MCCodeEmitter *CE,
bool RelaxAll, bool NoExecStack);
@@ -599,7 +599,7 @@
/// "pure" MC object files, for use with MC-JIT and testing tools.
///
/// Takes ownership of \arg TAB and \arg CE.
- MCStreamer *createPureStreamer(MCContext &Ctx, TargetAsmBackend &TAB,
+ MCStreamer *createPureStreamer(MCContext &Ctx, MCAsmBackend &TAB,
raw_ostream &OS, MCCodeEmitter *CE);
} // end namespace llvm
Removed: llvm/branches/exception-handling-rewrite/include/llvm/MC/TargetAsmBackend.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/include/llvm/MC/TargetAsmBackend.h?rev=136039&view=auto
==============================================================================
--- llvm/branches/exception-handling-rewrite/include/llvm/MC/TargetAsmBackend.h (original)
+++ llvm/branches/exception-handling-rewrite/include/llvm/MC/TargetAsmBackend.h (removed)
@@ -1,131 +0,0 @@
-//===-- llvm/MC/TargetAsmBackend.h - Target Asm Backend ---------*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_TARGET_TARGETASMBACKEND_H
-#define LLVM_TARGET_TARGETASMBACKEND_H
-
-#include "llvm/MC/MCDirectives.h"
-#include "llvm/MC/MCFixup.h"
-#include "llvm/MC/MCFixupKindInfo.h"
-#include "llvm/Support/DataTypes.h"
-
-namespace llvm {
-class MCELFObjectTargetWriter;
-class MCFixup;
-class MCInst;
-class MCObjectWriter;
-class MCSection;
-template<typename T>
-class SmallVectorImpl;
-class raw_ostream;
-
-/// TargetAsmBackend - Generic interface to target specific assembler backends.
-class TargetAsmBackend {
- TargetAsmBackend(const TargetAsmBackend &); // DO NOT IMPLEMENT
- void operator=(const TargetAsmBackend &); // DO NOT IMPLEMENT
-protected: // Can only create subclasses.
- TargetAsmBackend();
-
- unsigned HasReliableSymbolDifference : 1;
-
-public:
- virtual ~TargetAsmBackend();
-
- /// createObjectWriter - Create a new MCObjectWriter instance for use by the
- /// assembler backend to emit the final object file.
- virtual MCObjectWriter *createObjectWriter(raw_ostream &OS) const = 0;
-
- /// createELFObjectTargetWriter - Create a new ELFObjectTargetWriter to enable
- /// non-standard ELFObjectWriters.
- virtual MCELFObjectTargetWriter *createELFObjectTargetWriter() const {
- assert(0 && "createELFObjectTargetWriter is not supported by asm backend");
- return 0;
- }
-
- /// hasReliableSymbolDifference - Check whether this target implements
- /// accurate relocations for differences between symbols. If not, differences
- /// between symbols will always be relocatable expressions and any references
- /// to temporary symbols will be assumed to be in the same atom, unless they
- /// reside in a different section.
- ///
- /// This should always be true (since it results in fewer relocations with no
- /// loss of functionality), but is currently supported as a way to maintain
- /// exact object compatibility with Darwin 'as' (on non-x86_64). It should
- /// eventually should be eliminated.
- bool hasReliableSymbolDifference() const {
- return HasReliableSymbolDifference;
- }
-
- /// doesSectionRequireSymbols - Check whether the given section requires that
- /// all symbols (even temporaries) have symbol table entries.
- virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
- return false;
- }
-
- /// isSectionAtomizable - Check whether the given section can be split into
- /// atoms.
- ///
- /// \see MCAssembler::isSymbolLinkerVisible().
- virtual bool isSectionAtomizable(const MCSection &Section) const {
- return true;
- }
-
- /// @name Target Fixup Interfaces
- /// @{
-
- /// getNumFixupKinds - Get the number of target specific fixup kinds.
- virtual unsigned getNumFixupKinds() const = 0;
-
- /// getFixupKindInfo - Get information on a fixup kind.
- virtual const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const;
-
- /// @}
-
- /// ApplyFixup - Apply the \arg Value for given \arg Fixup into the provided
- /// data fragment, at the offset specified by the fixup and following the
- /// fixup kind as appropriate.
- virtual void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
- uint64_t Value) const = 0;
-
- /// @}
-
- /// @name Target Relaxation Interfaces
- /// @{
-
- /// MayNeedRelaxation - Check whether the given instruction may need
- /// relaxation.
- ///
- /// \param Inst - The instruction to test.
- virtual bool MayNeedRelaxation(const MCInst &Inst) const = 0;
-
- /// RelaxInstruction - Relax the instruction in the given fragment to the next
- /// wider instruction.
- ///
- /// \param Inst - The instruction to relax, which may be the same as the
- /// output.
- /// \parm Res [output] - On return, the relaxed instruction.
- virtual void RelaxInstruction(const MCInst &Inst, MCInst &Res) const = 0;
-
- /// @}
-
- /// WriteNopData - Write an (optimal) nop sequence of Count bytes to the given
- /// output. If the target cannot generate such a sequence, it should return an
- /// error.
- ///
- /// \return - True on success.
- virtual bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const = 0;
-
- /// HandleAssemblerFlag - Handle any target-specific assembler flags.
- /// By default, do nothing.
- virtual void HandleAssemblerFlag(MCAssemblerFlag Flag) {}
-};
-
-} // End llvm namespace
-
-#endif
Removed: llvm/branches/exception-handling-rewrite/include/llvm/MC/TargetAsmLexer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/include/llvm/MC/TargetAsmLexer.h?rev=136039&view=auto
==============================================================================
--- llvm/branches/exception-handling-rewrite/include/llvm/MC/TargetAsmLexer.h (original)
+++ llvm/branches/exception-handling-rewrite/include/llvm/MC/TargetAsmLexer.h (removed)
@@ -1,89 +0,0 @@
-//===-- llvm/Target/TargetAsmLexer.h - Target Assembly Lexer ----*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_TARGET_TARGETASMLEXER_H
-#define LLVM_TARGET_TARGETASMLEXER_H
-
-#include "llvm/MC/MCParser/MCAsmLexer.h"
-
-namespace llvm {
-class Target;
-
-/// TargetAsmLexer - Generic interface to target specific assembly lexers.
-class TargetAsmLexer {
- /// The current token
- AsmToken CurTok;
-
- /// The location and description of the current error
- SMLoc ErrLoc;
- std::string Err;
-
- TargetAsmLexer(const TargetAsmLexer &); // DO NOT IMPLEMENT
- void operator=(const TargetAsmLexer &); // DO NOT IMPLEMENT
-protected: // Can only create subclasses.
- TargetAsmLexer(const Target &);
-
- virtual AsmToken LexToken() = 0;
-
- void SetError(const SMLoc &errLoc, const std::string &err) {
- ErrLoc = errLoc;
- Err = err;
- }
-
- /// TheTarget - The Target that this machine was created for.
- const Target &TheTarget;
- MCAsmLexer *Lexer;
-
-public:
- virtual ~TargetAsmLexer();
-
- const Target &getTarget() const { return TheTarget; }
-
- /// InstallLexer - Set the lexer to get tokens from lower-level lexer \arg L.
- void InstallLexer(MCAsmLexer &L) {
- Lexer = &L;
- }
-
- MCAsmLexer *getLexer() {
- return Lexer;
- }
-
- /// Lex - Consume the next token from the input stream and return it.
- const AsmToken &Lex() {
- return CurTok = LexToken();
- }
-
- /// getTok - Get the current (last) lexed token.
- const AsmToken &getTok() {
- return CurTok;
- }
-
- /// getErrLoc - Get the current error location
- const SMLoc &getErrLoc() {
- return ErrLoc;
- }
-
- /// getErr - Get the current error string
- const std::string &getErr() {
- return Err;
- }
-
- /// getKind - Get the kind of current token.
- AsmToken::TokenKind getKind() const { return CurTok.getKind(); }
-
- /// is - Check if the current token has kind \arg K.
- bool is(AsmToken::TokenKind K) const { return CurTok.is(K); }
-
- /// isNot - Check if the current token has kind \arg K.
- bool isNot(AsmToken::TokenKind K) const { return CurTok.isNot(K); }
-};
-
-} // End llvm namespace
-
-#endif
Removed: llvm/branches/exception-handling-rewrite/include/llvm/MC/TargetAsmParser.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/include/llvm/MC/TargetAsmParser.h?rev=136039&view=auto
==============================================================================
--- llvm/branches/exception-handling-rewrite/include/llvm/MC/TargetAsmParser.h (original)
+++ llvm/branches/exception-handling-rewrite/include/llvm/MC/TargetAsmParser.h (removed)
@@ -1,85 +0,0 @@
-//===-- llvm/Target/TargetAsmParser.h - Target Assembly Parser --*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_TARGET_TARGETPARSER_H
-#define LLVM_TARGET_TARGETPARSER_H
-
-#include "llvm/MC/MCParser/MCAsmParserExtension.h"
-
-namespace llvm {
-class MCStreamer;
-class StringRef;
-class SMLoc;
-class AsmToken;
-class MCParsedAsmOperand;
-template <typename T> class SmallVectorImpl;
-
-/// TargetAsmParser - Generic interface to target specific assembly parsers.
-class TargetAsmParser : public MCAsmParserExtension {
- TargetAsmParser(const TargetAsmParser &); // DO NOT IMPLEMENT
- void operator=(const TargetAsmParser &); // DO NOT IMPLEMENT
-protected: // Can only create subclasses.
- TargetAsmParser();
-
- /// AvailableFeatures - The current set of available features.
- unsigned AvailableFeatures;
-
-public:
- virtual ~TargetAsmParser();
-
- unsigned getAvailableFeatures() const { return AvailableFeatures; }
- void setAvailableFeatures(unsigned Value) { AvailableFeatures = Value; }
-
- virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
- SMLoc &EndLoc) = 0;
-
- /// ParseInstruction - Parse one assembly instruction.
- ///
- /// The parser is positioned following the instruction name. The target
- /// specific instruction parser should parse the entire instruction and
- /// construct the appropriate MCInst, or emit an error. On success, the entire
- /// line should be parsed up to and including the end-of-statement token. On
- /// failure, the parser is not required to read to the end of the line.
- //
- /// \param Name - The instruction name.
- /// \param NameLoc - The source location of the name.
- /// \param Operands [out] - The list of parsed operands, this returns
- /// ownership of them to the caller.
- /// \return True on failure.
- virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
- SmallVectorImpl<MCParsedAsmOperand*> &Operands) = 0;
-
- /// ParseDirective - Parse a target specific assembler directive
- ///
- /// The parser is positioned following the directive name. The target
- /// specific directive parser should parse the entire directive doing or
- /// recording any target specific work, or return true and do nothing if the
- /// directive is not target specific. If the directive is specific for
- /// the target, the entire line is parsed up to and including the
- /// end-of-statement token and false is returned.
- ///
- /// \param DirectiveID - the identifier token of the directive.
- virtual bool ParseDirective(AsmToken DirectiveID) = 0;
-
- /// MatchAndEmitInstruction - Recognize a series of operands of a parsed
- /// instruction as an actual MCInst and emit it to the specified MCStreamer.
- /// This returns false on success and returns true on failure to match.
- ///
- /// On failure, the target parser is responsible for emitting a diagnostic
- /// explaining the match failure.
- virtual bool
- MatchAndEmitInstruction(SMLoc IDLoc,
- SmallVectorImpl<MCParsedAsmOperand*> &Operands,
- MCStreamer &Out) = 0;
-
-};
-
-} // End llvm namespace
-
-#endif
Modified: llvm/branches/exception-handling-rewrite/include/llvm/Support/BranchProbability.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/include/llvm/Support/BranchProbability.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/include/llvm/Support/BranchProbability.h (original)
+++ llvm/branches/exception-handling-rewrite/include/llvm/Support/BranchProbability.h Mon Jul 25 20:29:47 2011
@@ -1,4 +1,4 @@
-//===- BranchProbability.h - Branch Probability Analysis --------*- C++ -*-===//
+//===- BranchProbability.h - Branch Probability Wrapper ---------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -34,13 +34,13 @@
uint32_t getNumerator() const { return N; }
uint32_t getDenominator() const { return D; }
-
+
// Return (1 - Probability).
BranchProbability getCompl() {
return BranchProbability(D - N, D);
}
- raw_ostream &print(raw_ostream &OS) const;
+ void print(raw_ostream &OS) const;
void dump() const;
};
Modified: llvm/branches/exception-handling-rewrite/include/llvm/Support/IRBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/include/llvm/Support/IRBuilder.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/include/llvm/Support/IRBuilder.h (original)
+++ llvm/branches/exception-handling-rewrite/include/llvm/Support/IRBuilder.h Mon Jul 25 20:29:47 2011
@@ -762,6 +762,10 @@
StoreInst *CreateStore(Value *Val, Value *Ptr, bool isVolatile = false) {
return Insert(new StoreInst(Val, Ptr, isVolatile));
}
+ FenceInst *CreateFence(AtomicOrdering Ordering,
+ SynchronizationScope SynchScope = CrossThread) {
+ return Insert(new FenceInst(Context, Ordering, SynchScope));
+ }
Value *CreateGEP(Value *Ptr, ArrayRef<Value *> IdxList,
const Twine &Name = "") {
if (Constant *PC = dyn_cast<Constant>(Ptr)) {
@@ -773,9 +777,7 @@
if (i == e)
return Insert(Folder.CreateGetElementPtr(PC, IdxList), Name);
}
- return Insert(GetElementPtrInst::Create(Ptr, IdxList.begin(),
- IdxList.end()),
- Name);
+ return Insert(GetElementPtrInst::Create(Ptr, IdxList), Name);
}
Value *CreateInBoundsGEP(Value *Ptr, ArrayRef<Value *> IdxList,
const Twine &Name = "") {
@@ -788,9 +790,7 @@
if (i == e)
return Insert(Folder.CreateInBoundsGetElementPtr(PC, IdxList), Name);
}
- return Insert(GetElementPtrInst::CreateInBounds(Ptr, IdxList.begin(),
- IdxList.end()),
- Name);
+ return Insert(GetElementPtrInst::CreateInBounds(Ptr, IdxList), Name);
}
Value *CreateGEP(Value *Ptr, Value *Idx, const Twine &Name = "") {
if (Constant *PC = dyn_cast<Constant>(Ptr))
@@ -831,7 +831,7 @@
if (Constant *PC = dyn_cast<Constant>(Ptr))
return Insert(Folder.CreateGetElementPtr(PC, Idxs), Name);
- return Insert(GetElementPtrInst::Create(Ptr, Idxs, Idxs+2), Name);
+ return Insert(GetElementPtrInst::Create(Ptr, Idxs), Name);
}
Value *CreateConstInBoundsGEP2_32(Value *Ptr, unsigned Idx0, unsigned Idx1,
const Twine &Name = "") {
@@ -843,7 +843,7 @@
if (Constant *PC = dyn_cast<Constant>(Ptr))
return Insert(Folder.CreateInBoundsGetElementPtr(PC, Idxs), Name);
- return Insert(GetElementPtrInst::CreateInBounds(Ptr, Idxs, Idxs+2), Name);
+ return Insert(GetElementPtrInst::CreateInBounds(Ptr, Idxs), Name);
}
Value *CreateConstGEP1_64(Value *Ptr, uint64_t Idx0, const Twine &Name = "") {
Value *Idx = ConstantInt::get(Type::getInt64Ty(Context), Idx0);
@@ -872,7 +872,7 @@
if (Constant *PC = dyn_cast<Constant>(Ptr))
return Insert(Folder.CreateGetElementPtr(PC, Idxs), Name);
- return Insert(GetElementPtrInst::Create(Ptr, Idxs, Idxs+2), Name);
+ return Insert(GetElementPtrInst::Create(Ptr, Idxs), Name);
}
Value *CreateConstInBoundsGEP2_64(Value *Ptr, uint64_t Idx0, uint64_t Idx1,
const Twine &Name = "") {
@@ -884,7 +884,7 @@
if (Constant *PC = dyn_cast<Constant>(Ptr))
return Insert(Folder.CreateInBoundsGetElementPtr(PC, Idxs), Name);
- return Insert(GetElementPtrInst::CreateInBounds(Ptr, Idxs, Idxs+2), Name);
+ return Insert(GetElementPtrInst::CreateInBounds(Ptr, Idxs), Name);
}
Value *CreateStructGEP(Value *Ptr, unsigned Idx, const Twine &Name = "") {
return CreateConstInBoundsGEP2_32(Ptr, 0, Idx, Name);
Modified: llvm/branches/exception-handling-rewrite/include/llvm/Support/InstVisitor.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/include/llvm/Support/InstVisitor.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/include/llvm/Support/InstVisitor.h (original)
+++ llvm/branches/exception-handling-rewrite/include/llvm/Support/InstVisitor.h Mon Jul 25 20:29:47 2011
@@ -170,6 +170,7 @@
RetTy visitAllocaInst(AllocaInst &I) { DELEGATE(Instruction); }
RetTy visitLoadInst(LoadInst &I) { DELEGATE(Instruction); }
RetTy visitStoreInst(StoreInst &I) { DELEGATE(Instruction); }
+ RetTy visitFenceInst(FenceInst &I) { DELEGATE(Instruction); }
RetTy visitGetElementPtrInst(GetElementPtrInst &I){ DELEGATE(Instruction); }
RetTy visitPHINode(PHINode &I) { DELEGATE(Instruction); }
RetTy visitTruncInst(TruncInst &I) { DELEGATE(CastInst); }
Modified: llvm/branches/exception-handling-rewrite/include/llvm/Support/NoFolder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/include/llvm/Support/NoFolder.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/include/llvm/Support/NoFolder.h (original)
+++ llvm/branches/exception-handling-rewrite/include/llvm/Support/NoFolder.h Mon Jul 25 20:29:47 2011
@@ -183,7 +183,7 @@
}
Instruction *CreateGetElementPtr(Constant *C,
ArrayRef<Value *> IdxList) const {
- return GetElementPtrInst::Create(C, IdxList.begin(), IdxList.end());
+ return GetElementPtrInst::Create(C, IdxList);
}
Constant *CreateInBoundsGetElementPtr(Constant *C,
@@ -192,7 +192,7 @@
}
Instruction *CreateInBoundsGetElementPtr(Constant *C,
ArrayRef<Value *> IdxList) const {
- return GetElementPtrInst::CreateInBounds(C, IdxList.begin(), IdxList.end());
+ return GetElementPtrInst::CreateInBounds(C, IdxList);
}
//===--------------------------------------------------------------------===//
Modified: llvm/branches/exception-handling-rewrite/include/llvm/Support/TypeBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/include/llvm/Support/TypeBuilder.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/include/llvm/Support/TypeBuilder.h (original)
+++ llvm/branches/exception-handling-rewrite/include/llvm/Support/TypeBuilder.h Mon Jul 25 20:29:47 2011
@@ -18,7 +18,6 @@
#include "llvm/DerivedTypes.h"
#include "llvm/LLVMContext.h"
#include <limits.h>
-#include <vector>
namespace llvm {
@@ -254,9 +253,9 @@
template<typename R, typename A1, bool cross> class TypeBuilder<R(A1), cross> {
public:
static FunctionType *get(LLVMContext &Context) {
- std::vector<Type*> params;
- params.reserve(1);
- params.push_back(TypeBuilder<A1, cross>::get(Context));
+ Type *params[] = {
+ TypeBuilder<A1, cross>::get(Context),
+ };
return FunctionType::get(TypeBuilder<R, cross>::get(Context),
params, false);
}
@@ -265,10 +264,10 @@
class TypeBuilder<R(A1, A2), cross> {
public:
static FunctionType *get(LLVMContext &Context) {
- std::vector<Type*> params;
- params.reserve(2);
- params.push_back(TypeBuilder<A1, cross>::get(Context));
- params.push_back(TypeBuilder<A2, cross>::get(Context));
+ Type *params[] = {
+ TypeBuilder<A1, cross>::get(Context),
+ TypeBuilder<A2, cross>::get(Context),
+ };
return FunctionType::get(TypeBuilder<R, cross>::get(Context),
params, false);
}
@@ -277,11 +276,11 @@
class TypeBuilder<R(A1, A2, A3), cross> {
public:
static FunctionType *get(LLVMContext &Context) {
- std::vector<Type*> params;
- params.reserve(3);
- params.push_back(TypeBuilder<A1, cross>::get(Context));
- params.push_back(TypeBuilder<A2, cross>::get(Context));
- params.push_back(TypeBuilder<A3, cross>::get(Context));
+ Type *params[] = {
+ TypeBuilder<A1, cross>::get(Context),
+ TypeBuilder<A2, cross>::get(Context),
+ TypeBuilder<A3, cross>::get(Context),
+ };
return FunctionType::get(TypeBuilder<R, cross>::get(Context),
params, false);
}
@@ -292,12 +291,12 @@
class TypeBuilder<R(A1, A2, A3, A4), cross> {
public:
static FunctionType *get(LLVMContext &Context) {
- std::vector<Type*> params;
- params.reserve(4);
- params.push_back(TypeBuilder<A1, cross>::get(Context));
- params.push_back(TypeBuilder<A2, cross>::get(Context));
- params.push_back(TypeBuilder<A3, cross>::get(Context));
- params.push_back(TypeBuilder<A4, cross>::get(Context));
+ Type *params[] = {
+ TypeBuilder<A1, cross>::get(Context),
+ TypeBuilder<A2, cross>::get(Context),
+ TypeBuilder<A3, cross>::get(Context),
+ TypeBuilder<A4, cross>::get(Context),
+ };
return FunctionType::get(TypeBuilder<R, cross>::get(Context),
params, false);
}
@@ -308,13 +307,13 @@
class TypeBuilder<R(A1, A2, A3, A4, A5), cross> {
public:
static FunctionType *get(LLVMContext &Context) {
- std::vector<Type*> params;
- params.reserve(5);
- params.push_back(TypeBuilder<A1, cross>::get(Context));
- params.push_back(TypeBuilder<A2, cross>::get(Context));
- params.push_back(TypeBuilder<A3, cross>::get(Context));
- params.push_back(TypeBuilder<A4, cross>::get(Context));
- params.push_back(TypeBuilder<A5, cross>::get(Context));
+ Type *params[] = {
+ TypeBuilder<A1, cross>::get(Context),
+ TypeBuilder<A2, cross>::get(Context),
+ TypeBuilder<A3, cross>::get(Context),
+ TypeBuilder<A4, cross>::get(Context),
+ TypeBuilder<A5, cross>::get(Context),
+ };
return FunctionType::get(TypeBuilder<R, cross>::get(Context),
params, false);
}
@@ -330,9 +329,9 @@
class TypeBuilder<R(A1, ...), cross> {
public:
static FunctionType *get(LLVMContext &Context) {
- std::vector<Type*> params;
- params.reserve(1);
- params.push_back(TypeBuilder<A1, cross>::get(Context));
+ Type *params[] = {
+ TypeBuilder<A1, cross>::get(Context),
+ };
return FunctionType::get(TypeBuilder<R, cross>::get(Context), params, true);
}
};
@@ -340,10 +339,10 @@
class TypeBuilder<R(A1, A2, ...), cross> {
public:
static FunctionType *get(LLVMContext &Context) {
- std::vector<Type*> params;
- params.reserve(2);
- params.push_back(TypeBuilder<A1, cross>::get(Context));
- params.push_back(TypeBuilder<A2, cross>::get(Context));
+ Type *params[] = {
+ TypeBuilder<A1, cross>::get(Context),
+ TypeBuilder<A2, cross>::get(Context),
+ };
return FunctionType::get(TypeBuilder<R, cross>::get(Context),
params, true);
}
@@ -352,11 +351,11 @@
class TypeBuilder<R(A1, A2, A3, ...), cross> {
public:
static FunctionType *get(LLVMContext &Context) {
- std::vector<Type*> params;
- params.reserve(3);
- params.push_back(TypeBuilder<A1, cross>::get(Context));
- params.push_back(TypeBuilder<A2, cross>::get(Context));
- params.push_back(TypeBuilder<A3, cross>::get(Context));
+ Type *params[] = {
+ TypeBuilder<A1, cross>::get(Context),
+ TypeBuilder<A2, cross>::get(Context),
+ TypeBuilder<A3, cross>::get(Context),
+ };
return FunctionType::get(TypeBuilder<R, cross>::get(Context),
params, true);
}
@@ -367,12 +366,12 @@
class TypeBuilder<R(A1, A2, A3, A4, ...), cross> {
public:
static FunctionType *get(LLVMContext &Context) {
- std::vector<Type*> params;
- params.reserve(4);
- params.push_back(TypeBuilder<A1, cross>::get(Context));
- params.push_back(TypeBuilder<A2, cross>::get(Context));
- params.push_back(TypeBuilder<A3, cross>::get(Context));
- params.push_back(TypeBuilder<A4, cross>::get(Context));
+ Type *params[] = {
+ TypeBuilder<A1, cross>::get(Context),
+ TypeBuilder<A2, cross>::get(Context),
+ TypeBuilder<A3, cross>::get(Context),
+ TypeBuilder<A4, cross>::get(Context),
+ };
return FunctionType::get(TypeBuilder<R, cross>::get(Context),
params, true);
}
@@ -383,13 +382,13 @@
class TypeBuilder<R(A1, A2, A3, A4, A5, ...), cross> {
public:
static FunctionType *get(LLVMContext &Context) {
- std::vector<Type*> params;
- params.reserve(5);
- params.push_back(TypeBuilder<A1, cross>::get(Context));
- params.push_back(TypeBuilder<A2, cross>::get(Context));
- params.push_back(TypeBuilder<A3, cross>::get(Context));
- params.push_back(TypeBuilder<A4, cross>::get(Context));
- params.push_back(TypeBuilder<A5, cross>::get(Context));
+ Type *params[] = {
+ TypeBuilder<A1, cross>::get(Context),
+ TypeBuilder<A2, cross>::get(Context),
+ TypeBuilder<A3, cross>::get(Context),
+ TypeBuilder<A4, cross>::get(Context),
+ TypeBuilder<A5, cross>::get(Context),
+ };
return FunctionType::get(TypeBuilder<R, cross>::get(Context),
params, true);
}
Modified: llvm/branches/exception-handling-rewrite/include/llvm/Target/TargetRegistry.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/include/llvm/Target/TargetRegistry.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/include/llvm/Target/TargetRegistry.h (original)
+++ llvm/branches/exception-handling-rewrite/include/llvm/Target/TargetRegistry.h Mon Jul 25 20:29:47 2011
@@ -28,9 +28,11 @@
class AsmPrinter;
class Module;
class MCAssembler;
+ class MCAsmBackend;
class MCAsmInfo;
class MCAsmParser;
class MCCodeEmitter;
+ class MCCodeGenInfo;
class MCContext;
class MCDisassembler;
class MCInstPrinter;
@@ -38,10 +40,8 @@
class MCRegisterInfo;
class MCStreamer;
class MCSubtargetInfo;
- class MCCodeGenInfo;
- class TargetAsmBackend;
- class TargetAsmLexer;
- class TargetAsmParser;
+ class MCTargetAsmLexer;
+ class MCTargetAsmParser;
class TargetMachine;
class raw_ostream;
class formatted_raw_ostream;
@@ -51,7 +51,7 @@
bool useLoc, bool useCFI,
MCInstPrinter *InstPrint,
MCCodeEmitter *CE,
- TargetAsmBackend *TAB,
+ MCAsmBackend *TAB,
bool ShowInst);
/// Target - Wrapper for Target specific information.
@@ -86,27 +86,27 @@
CodeModel::Model CM);
typedef AsmPrinter *(*AsmPrinterCtorTy)(TargetMachine &TM,
MCStreamer &Streamer);
- typedef TargetAsmBackend *(*AsmBackendCtorTy)(const Target &T,
- const std::string &TT);
- typedef TargetAsmLexer *(*AsmLexerCtorTy)(const Target &T,
- const MCAsmInfo &MAI);
- typedef TargetAsmParser *(*AsmParserCtorTy)(MCSubtargetInfo &STI,
- MCAsmParser &P);
+ typedef MCAsmBackend *(*MCAsmBackendCtorTy)(const Target &T, StringRef TT);
+ typedef MCTargetAsmLexer *(*MCAsmLexerCtorTy)(const Target &T,
+ const MCRegisterInfo &MRI,
+ const MCAsmInfo &MAI);
+ typedef MCTargetAsmParser *(*MCAsmParserCtorTy)(MCSubtargetInfo &STI,
+ MCAsmParser &P);
typedef MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T);
typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const Target &T,
unsigned SyntaxVariant,
const MCAsmInfo &MAI);
- typedef MCCodeEmitter *(*CodeEmitterCtorTy)(const MCInstrInfo &II,
- const MCSubtargetInfo &STI,
- MCContext &Ctx);
- typedef MCStreamer *(*ObjectStreamerCtorTy)(const Target &T,
- const std::string &TT,
- MCContext &Ctx,
- TargetAsmBackend &TAB,
- raw_ostream &_OS,
- MCCodeEmitter *_Emitter,
- bool RelaxAll,
- bool NoExecStack);
+ typedef MCCodeEmitter *(*MCCodeEmitterCtorTy)(const MCInstrInfo &II,
+ const MCSubtargetInfo &STI,
+ MCContext &Ctx);
+ typedef MCStreamer *(*MCObjectStreamerCtorTy)(const Target &T,
+ StringRef TT,
+ MCContext &Ctx,
+ MCAsmBackend &TAB,
+ raw_ostream &_OS,
+ MCCodeEmitter *_Emitter,
+ bool RelaxAll,
+ bool NoExecStack);
typedef MCStreamer *(*AsmStreamerCtorTy)(MCContext &Ctx,
formatted_raw_ostream &OS,
bool isVerboseAsm,
@@ -114,7 +114,7 @@
bool useCFI,
MCInstPrinter *InstPrint,
MCCodeEmitter *CE,
- TargetAsmBackend *TAB,
+ MCAsmBackend *TAB,
bool ShowInst);
private:
@@ -159,17 +159,17 @@
/// TargetMachine, if registered.
TargetMachineCtorTy TargetMachineCtorFn;
- /// AsmBackendCtorFn - Construction function for this target's
- /// TargetAsmBackend, if registered.
- AsmBackendCtorTy AsmBackendCtorFn;
-
- /// AsmLexerCtorFn - Construction function for this target's TargetAsmLexer,
- /// if registered.
- AsmLexerCtorTy AsmLexerCtorFn;
-
- /// AsmParserCtorFn - Construction function for this target's
- /// TargetAsmParser, if registered.
- AsmParserCtorTy AsmParserCtorFn;
+ /// MCAsmBackendCtorFn - Construction function for this target's
+ /// MCAsmBackend, if registered.
+ MCAsmBackendCtorTy MCAsmBackendCtorFn;
+
+ /// MCAsmLexerCtorFn - Construction function for this target's
+ /// MCTargetAsmLexer, if registered.
+ MCAsmLexerCtorTy MCAsmLexerCtorFn;
+
+ /// MCAsmParserCtorFn - Construction function for this target's
+ /// MCTargetAsmParser, if registered.
+ MCAsmParserCtorTy MCAsmParserCtorFn;
/// AsmPrinterCtorFn - Construction function for this target's AsmPrinter,
/// if registered.
@@ -183,13 +183,13 @@
/// MCInstPrinter, if registered.
MCInstPrinterCtorTy MCInstPrinterCtorFn;
- /// CodeEmitterCtorFn - Construction function for this target's CodeEmitter,
- /// if registered.
- CodeEmitterCtorTy CodeEmitterCtorFn;
-
- /// ObjectStreamerCtorFn - Construction function for this target's
- /// ObjectStreamer, if registered.
- ObjectStreamerCtorTy ObjectStreamerCtorFn;
+ /// MCCodeEmitterCtorFn - Construction function for this target's
+ /// CodeEmitter, if registered.
+ MCCodeEmitterCtorTy MCCodeEmitterCtorFn;
+
+ /// MCObjectStreamerCtorFn - Construction function for this target's
+ /// MCObjectStreamer, if registered.
+ MCObjectStreamerCtorTy MCObjectStreamerCtorFn;
/// AsmStreamerCtorFn - Construction function for this target's
/// AsmStreamer, if registered (default = llvm::createAsmStreamer).
@@ -220,14 +220,14 @@
/// hasTargetMachine - Check if this target supports code generation.
bool hasTargetMachine() const { return TargetMachineCtorFn != 0; }
- /// hasAsmBackend - Check if this target supports .o generation.
- bool hasAsmBackend() const { return AsmBackendCtorFn != 0; }
+ /// hasMCAsmBackend - Check if this target supports .o generation.
+ bool hasMCAsmBackend() const { return MCAsmBackendCtorFn != 0; }
- /// hasAsmLexer - Check if this target supports .s lexing.
- bool hasAsmLexer() const { return AsmLexerCtorFn != 0; }
+ /// hasMCAsmLexer - Check if this target supports .s lexing.
+ bool hasMCAsmLexer() const { return MCAsmLexerCtorFn != 0; }
/// hasAsmParser - Check if this target supports .s parsing.
- bool hasAsmParser() const { return AsmParserCtorFn != 0; }
+ bool hasMCAsmParser() const { return MCAsmParserCtorFn != 0; }
/// hasAsmPrinter - Check if this target supports .s printing.
bool hasAsmPrinter() const { return AsmPrinterCtorFn != 0; }
@@ -238,11 +238,11 @@
/// hasMCInstPrinter - Check if this target has an instruction printer.
bool hasMCInstPrinter() const { return MCInstPrinterCtorFn != 0; }
- /// hasCodeEmitter - Check if this target supports instruction encoding.
- bool hasCodeEmitter() const { return CodeEmitterCtorFn != 0; }
+ /// hasMCCodeEmitter - Check if this target supports instruction encoding.
+ bool hasMCCodeEmitter() const { return MCCodeEmitterCtorFn != 0; }
- /// hasObjectStreamer - Check if this target supports streaming to files.
- bool hasObjectStreamer() const { return ObjectStreamerCtorFn != 0; }
+ /// hasMCObjectStreamer - Check if this target supports streaming to files.
+ bool hasMCObjectStreamer() const { return MCObjectStreamerCtorFn != 0; }
/// hasAsmStreamer - Check if this target supports streaming to files.
bool hasAsmStreamer() const { return AsmStreamerCtorFn != 0; }
@@ -321,33 +321,34 @@
return TargetMachineCtorFn(*this, Triple, CPU, Features, RM, CM);
}
- /// createAsmBackend - Create a target specific assembly parser.
+ /// createMCAsmBackend - Create a target specific assembly parser.
///
/// \arg Triple - The target triple string.
/// \arg Backend - The target independent assembler object.
- TargetAsmBackend *createAsmBackend(const std::string &Triple) const {
- if (!AsmBackendCtorFn)
+ MCAsmBackend *createMCAsmBackend(StringRef Triple) const {
+ if (!MCAsmBackendCtorFn)
return 0;
- return AsmBackendCtorFn(*this, Triple);
+ return MCAsmBackendCtorFn(*this, Triple);
}
- /// createAsmLexer - Create a target specific assembly lexer.
+ /// createMCAsmLexer - Create a target specific assembly lexer.
///
- TargetAsmLexer *createAsmLexer(const MCAsmInfo &MAI) const {
- if (!AsmLexerCtorFn)
+ MCTargetAsmLexer *createMCAsmLexer(const MCRegisterInfo &MRI,
+ const MCAsmInfo &MAI) const {
+ if (!MCAsmLexerCtorFn)
return 0;
- return AsmLexerCtorFn(*this, MAI);
+ return MCAsmLexerCtorFn(*this, MRI, MAI);
}
- /// createAsmParser - Create a target specific assembly parser.
+ /// createMCAsmParser - Create a target specific assembly parser.
///
/// \arg Parser - The target independent parser implementation to use for
/// parsing and lexing.
- TargetAsmParser *createAsmParser(MCSubtargetInfo &STI,
- MCAsmParser &Parser) const {
- if (!AsmParserCtorFn)
+ MCTargetAsmParser *createMCAsmParser(MCSubtargetInfo &STI,
+ MCAsmParser &Parser) const {
+ if (!MCAsmParserCtorFn)
return 0;
- return AsmParserCtorFn(STI, Parser);
+ return MCAsmParserCtorFn(STI, Parser);
}
/// createAsmPrinter - Create a target specific assembly printer pass. This
@@ -372,16 +373,16 @@
}
- /// createCodeEmitter - Create a target specific code emitter.
- MCCodeEmitter *createCodeEmitter(const MCInstrInfo &II,
- const MCSubtargetInfo &STI,
- MCContext &Ctx) const {
- if (!CodeEmitterCtorFn)
+ /// createMCCodeEmitter - Create a target specific code emitter.
+ MCCodeEmitter *createMCCodeEmitter(const MCInstrInfo &II,
+ const MCSubtargetInfo &STI,
+ MCContext &Ctx) const {
+ if (!MCCodeEmitterCtorFn)
return 0;
- return CodeEmitterCtorFn(II, STI, Ctx);
+ return MCCodeEmitterCtorFn(II, STI, Ctx);
}
- /// createObjectStreamer - Create a target specific MCStreamer.
+ /// createMCObjectStreamer - Create a target specific MCStreamer.
///
/// \arg TT - The target triple.
/// \arg Ctx - The target context.
@@ -390,16 +391,16 @@
/// \arg _Emitter - The target independent assembler object.Takes ownership.
/// \arg RelaxAll - Relax all fixups?
/// \arg NoExecStack - Mark file as not needing a executable stack.
- MCStreamer *createObjectStreamer(const std::string &TT, MCContext &Ctx,
- TargetAsmBackend &TAB,
- raw_ostream &_OS,
- MCCodeEmitter *_Emitter,
- bool RelaxAll,
- bool NoExecStack) const {
- if (!ObjectStreamerCtorFn)
+ MCStreamer *createMCObjectStreamer(StringRef TT, MCContext &Ctx,
+ MCAsmBackend &TAB,
+ raw_ostream &_OS,
+ MCCodeEmitter *_Emitter,
+ bool RelaxAll,
+ bool NoExecStack) const {
+ if (!MCObjectStreamerCtorFn)
return 0;
- return ObjectStreamerCtorFn(*this, TT, Ctx, TAB, _OS, _Emitter, RelaxAll,
- NoExecStack);
+ return MCObjectStreamerCtorFn(*this, TT, Ctx, TAB, _OS, _Emitter,
+ RelaxAll, NoExecStack);
}
/// createAsmStreamer - Create a target specific MCStreamer.
@@ -410,7 +411,7 @@
bool useCFI,
MCInstPrinter *InstPrint,
MCCodeEmitter *CE,
- TargetAsmBackend *TAB,
+ MCAsmBackend *TAB,
bool ShowInst) const {
// AsmStreamerCtorFn is default to llvm::createAsmStreamer
return AsmStreamerCtorFn(Ctx, OS, isVerboseAsm, useLoc, useCFI,
@@ -603,7 +604,7 @@
T.TargetMachineCtorFn = Fn;
}
- /// RegisterAsmBackend - Register a TargetAsmBackend implementation for the
+ /// RegisterMCAsmBackend - Register a MCAsmBackend implementation for the
/// given target.
///
/// Clients are responsible for ensuring that registration doesn't occur
@@ -612,12 +613,12 @@
///
/// @param T - The target being registered.
/// @param Fn - A function to construct an AsmBackend for the target.
- static void RegisterAsmBackend(Target &T, Target::AsmBackendCtorTy Fn) {
- if (!T.AsmBackendCtorFn)
- T.AsmBackendCtorFn = Fn;
+ static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn) {
+ if (!T.MCAsmBackendCtorFn)
+ T.MCAsmBackendCtorFn = Fn;
}
- /// RegisterAsmLexer - Register a TargetAsmLexer implementation for the
+ /// RegisterMCAsmLexer - Register a MCTargetAsmLexer implementation for the
/// given target.
///
/// Clients are responsible for ensuring that registration doesn't occur
@@ -625,24 +626,24 @@
/// this is done by initializing all targets at program startup.
///
/// @param T - The target being registered.
- /// @param Fn - A function to construct an AsmLexer for the target.
- static void RegisterAsmLexer(Target &T, Target::AsmLexerCtorTy Fn) {
- if (!T.AsmLexerCtorFn)
- T.AsmLexerCtorFn = Fn;
+ /// @param Fn - A function to construct an MCAsmLexer for the target.
+ static void RegisterMCAsmLexer(Target &T, Target::MCAsmLexerCtorTy Fn) {
+ if (!T.MCAsmLexerCtorFn)
+ T.MCAsmLexerCtorFn = Fn;
}
- /// RegisterAsmParser - Register a TargetAsmParser implementation for the
- /// given target.
+ /// RegisterMCAsmParser - Register a MCTargetAsmParser implementation for
+ /// the given target.
///
/// Clients are responsible for ensuring that registration doesn't occur
/// while another thread is attempting to access the registry. Typically
/// this is done by initializing all targets at program startup.
///
/// @param T - The target being registered.
- /// @param Fn - A function to construct an AsmParser for the target.
- static void RegisterAsmParser(Target &T, Target::AsmParserCtorTy Fn) {
- if (!T.AsmParserCtorFn)
- T.AsmParserCtorFn = Fn;
+ /// @param Fn - A function to construct an MCTargetAsmParser for the target.
+ static void RegisterMCAsmParser(Target &T, Target::MCAsmParserCtorTy Fn) {
+ if (!T.MCAsmParserCtorFn)
+ T.MCAsmParserCtorFn = Fn;
}
/// RegisterAsmPrinter - Register an AsmPrinter implementation for the given
@@ -690,7 +691,7 @@
T.MCInstPrinterCtorFn = Fn;
}
- /// RegisterCodeEmitter - Register a MCCodeEmitter implementation for the
+ /// RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the
/// given target.
///
/// Clients are responsible for ensuring that registration doesn't occur
@@ -699,13 +700,14 @@
///
/// @param T - The target being registered.
/// @param Fn - A function to construct an MCCodeEmitter for the target.
- static void RegisterCodeEmitter(Target &T, Target::CodeEmitterCtorTy Fn) {
- if (!T.CodeEmitterCtorFn)
- T.CodeEmitterCtorFn = Fn;
+ static void RegisterMCCodeEmitter(Target &T,
+ Target::MCCodeEmitterCtorTy Fn) {
+ if (!T.MCCodeEmitterCtorFn)
+ T.MCCodeEmitterCtorFn = Fn;
}
- /// RegisterObjectStreamer - Register a object code MCStreamer implementation
- /// for the given target.
+ /// RegisterMCObjectStreamer - Register a object code MCStreamer
+ /// implementation for the given target.
///
/// Clients are responsible for ensuring that registration doesn't occur
/// while another thread is attempting to access the registry. Typically
@@ -713,9 +715,10 @@
///
/// @param T - The target being registered.
/// @param Fn - A function to construct an MCStreamer for the target.
- static void RegisterObjectStreamer(Target &T, Target::ObjectStreamerCtorTy Fn) {
- if (!T.ObjectStreamerCtorFn)
- T.ObjectStreamerCtorFn = Fn;
+ static void RegisterMCObjectStreamer(Target &T,
+ Target::MCObjectStreamerCtorTy Fn) {
+ if (!T.MCObjectStreamerCtorFn)
+ T.MCObjectStreamerCtorFn = Fn;
}
/// RegisterAsmStreamer - Register an assembly MCStreamer implementation
@@ -954,63 +957,64 @@
}
};
- /// RegisterAsmBackend - Helper template for registering a target specific
+ /// RegisterMCAsmBackend - Helper template for registering a target specific
/// assembler backend. Usage:
///
- /// extern "C" void LLVMInitializeFooAsmBackend() {
+ /// extern "C" void LLVMInitializeFooMCAsmBackend() {
/// extern Target TheFooTarget;
- /// RegisterAsmBackend<FooAsmLexer> X(TheFooTarget);
+ /// RegisterMCAsmBackend<FooAsmLexer> X(TheFooTarget);
/// }
- template<class AsmBackendImpl>
- struct RegisterAsmBackend {
- RegisterAsmBackend(Target &T) {
- TargetRegistry::RegisterAsmBackend(T, &Allocator);
+ template<class MCAsmBackendImpl>
+ struct RegisterMCAsmBackend {
+ RegisterMCAsmBackend(Target &T) {
+ TargetRegistry::RegisterMCAsmBackend(T, &Allocator);
}
private:
- static TargetAsmBackend *Allocator(const Target &T,
- const std::string &Triple) {
- return new AsmBackendImpl(T, Triple);
+ static MCAsmBackend *Allocator(const Target &T, StringRef Triple) {
+ return new MCAsmBackendImpl(T, Triple);
}
};
- /// RegisterAsmLexer - Helper template for registering a target specific
+ /// RegisterMCAsmLexer - Helper template for registering a target specific
/// assembly lexer, for use in the target machine initialization
/// function. Usage:
///
- /// extern "C" void LLVMInitializeFooAsmLexer() {
+ /// extern "C" void LLVMInitializeFooMCAsmLexer() {
/// extern Target TheFooTarget;
- /// RegisterAsmLexer<FooAsmLexer> X(TheFooTarget);
+ /// RegisterMCAsmLexer<FooMCAsmLexer> X(TheFooTarget);
/// }
- template<class AsmLexerImpl>
- struct RegisterAsmLexer {
- RegisterAsmLexer(Target &T) {
- TargetRegistry::RegisterAsmLexer(T, &Allocator);
+ template<class MCAsmLexerImpl>
+ struct RegisterMCAsmLexer {
+ RegisterMCAsmLexer(Target &T) {
+ TargetRegistry::RegisterMCAsmLexer(T, &Allocator);
}
private:
- static TargetAsmLexer *Allocator(const Target &T, const MCAsmInfo &MAI) {
- return new AsmLexerImpl(T, MAI);
+ static MCTargetAsmLexer *Allocator(const Target &T,
+ const MCRegisterInfo &MRI,
+ const MCAsmInfo &MAI) {
+ return new MCAsmLexerImpl(T, MRI, MAI);
}
};
- /// RegisterAsmParser - Helper template for registering a target specific
+ /// RegisterMCAsmParser - Helper template for registering a target specific
/// assembly parser, for use in the target machine initialization
/// function. Usage:
///
- /// extern "C" void LLVMInitializeFooAsmParser() {
+ /// extern "C" void LLVMInitializeFooMCAsmParser() {
/// extern Target TheFooTarget;
- /// RegisterAsmParser<FooAsmParser> X(TheFooTarget);
+ /// RegisterMCAsmParser<FooAsmParser> X(TheFooTarget);
/// }
- template<class AsmParserImpl>
- struct RegisterAsmParser {
- RegisterAsmParser(Target &T) {
- TargetRegistry::RegisterAsmParser(T, &Allocator);
+ template<class MCAsmParserImpl>
+ struct RegisterMCAsmParser {
+ RegisterMCAsmParser(Target &T) {
+ TargetRegistry::RegisterMCAsmParser(T, &Allocator);
}
private:
- static TargetAsmParser *Allocator(MCSubtargetInfo &STI, MCAsmParser &P) {
- return new AsmParserImpl(STI, P);
+ static MCTargetAsmParser *Allocator(MCSubtargetInfo &STI, MCAsmParser &P) {
+ return new MCAsmParserImpl(STI, P);
}
};
@@ -1034,25 +1038,25 @@
}
};
- /// RegisterCodeEmitter - Helper template for registering a target specific
+ /// RegisterMCCodeEmitter - Helper template for registering a target specific
/// machine code emitter, for use in the target initialization
/// function. Usage:
///
- /// extern "C" void LLVMInitializeFooCodeEmitter() {
+ /// extern "C" void LLVMInitializeFooMCCodeEmitter() {
/// extern Target TheFooTarget;
- /// RegisterCodeEmitter<FooCodeEmitter> X(TheFooTarget);
+ /// RegisterMCCodeEmitter<FooCodeEmitter> X(TheFooTarget);
/// }
- template<class CodeEmitterImpl>
- struct RegisterCodeEmitter {
- RegisterCodeEmitter(Target &T) {
- TargetRegistry::RegisterCodeEmitter(T, &Allocator);
+ template<class MCCodeEmitterImpl>
+ struct RegisterMCCodeEmitter {
+ RegisterMCCodeEmitter(Target &T) {
+ TargetRegistry::RegisterMCCodeEmitter(T, &Allocator);
}
private:
static MCCodeEmitter *Allocator(const MCInstrInfo &II,
const MCSubtargetInfo &STI,
MCContext &Ctx) {
- return new CodeEmitterImpl();
+ return new MCCodeEmitterImpl();
}
};
Modified: llvm/branches/exception-handling-rewrite/lib/Analysis/Analysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Analysis/Analysis.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Analysis/Analysis.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Analysis/Analysis.cpp Mon Jul 25 20:29:47 2011
@@ -23,7 +23,7 @@
initializeAliasSetPrinterPass(Registry);
initializeNoAAPass(Registry);
initializeBasicAliasAnalysisPass(Registry);
- initializeBlockFrequencyPass(Registry);
+ initializeBlockFrequencyInfoPass(Registry);
initializeBranchProbabilityInfoPass(Registry);
initializeCFGViewerPass(Registry);
initializeCFGPrinterPass(Registry);
Removed: llvm/branches/exception-handling-rewrite/lib/Analysis/BlockFrequency.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Analysis/BlockFrequency.cpp?rev=136039&view=auto
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Analysis/BlockFrequency.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Analysis/BlockFrequency.cpp (removed)
@@ -1,59 +0,0 @@
-//=======-------- BlockFrequency.cpp - Block Frequency Analysis -------=======//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// Loops should be simplified before this analysis.
-//
-//===----------------------------------------------------------------------===//
-
-#include "llvm/InitializePasses.h"
-#include "llvm/Analysis/BlockFrequencyImpl.h"
-#include "llvm/Analysis/BlockFrequency.h"
-#include "llvm/Analysis/LoopInfo.h"
-#include "llvm/Analysis/Passes.h"
-#include "llvm/Analysis/BranchProbabilityInfo.h"
-
-using namespace llvm;
-
-INITIALIZE_PASS_BEGIN(BlockFrequency, "block-freq", "Block Frequency Analysis",
- true, true)
-INITIALIZE_PASS_DEPENDENCY(BranchProbabilityInfo)
-INITIALIZE_PASS_END(BlockFrequency, "block-freq", "Block Frequency Analysis",
- true, true)
-
-char BlockFrequency::ID = 0;
-
-
-BlockFrequency::BlockFrequency() : FunctionPass(ID) {
- initializeBlockFrequencyPass(*PassRegistry::getPassRegistry());
- BFI = new BlockFrequencyImpl<BasicBlock, Function, BranchProbabilityInfo>();
-}
-
-BlockFrequency::~BlockFrequency() {
- delete BFI;
-}
-
-void BlockFrequency::getAnalysisUsage(AnalysisUsage &AU) const {
- AU.addRequired<BranchProbabilityInfo>();
- AU.setPreservesAll();
-}
-
-bool BlockFrequency::runOnFunction(Function &F) {
- BranchProbabilityInfo &BPI = getAnalysis<BranchProbabilityInfo>();
- BFI->doFunction(&F, &BPI);
- return false;
-}
-
-/// getblockFreq - Return block frequency. Return 0 if we don't have the
-/// information. Please note that initial frequency is equal to 1024. It means
-/// that we should not rely on the value itself, but only on the comparison to
-/// the other block frequencies. We do this to avoid using of floating points.
-///
-uint32_t BlockFrequency::getBlockFreq(BasicBlock *BB) {
- return BFI->getBlockFreq(BB);
-}
Modified: llvm/branches/exception-handling-rewrite/lib/Analysis/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Analysis/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Analysis/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Analysis/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -6,7 +6,7 @@
AliasSetTracker.cpp
Analysis.cpp
BasicAliasAnalysis.cpp
- BlockFrequency.cpp
+ BlockFrequencyInfo.cpp
BranchProbabilityInfo.cpp
CFGPrinter.cpp
CaptureTracking.cpp
Modified: llvm/branches/exception-handling-rewrite/lib/Analysis/ConstantFolding.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Analysis/ConstantFolding.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Analysis/ConstantFolding.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Analysis/ConstantFolding.cpp Mon Jul 25 20:29:47 2011
@@ -547,8 +547,7 @@
for (unsigned i = 1, e = Ops.size(); i != e; ++i) {
if ((i == 1 ||
!isa<StructType>(GetElementPtrInst::getIndexedType(Ops[0]->getType(),
- Ops.data() + 1,
- i-1))) &&
+ Ops.slice(1, i-1)))) &&
Ops[i]->getType() != IntPtrTy) {
Any = true;
NewIdxs.push_back(ConstantExpr::getCast(CastInst::getCastOpcode(Ops[i],
Modified: llvm/branches/exception-handling-rewrite/lib/Analysis/InstructionSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Analysis/InstructionSimplify.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Analysis/InstructionSimplify.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Analysis/InstructionSimplify.cpp Mon Jul 25 20:29:47 2011
@@ -2230,8 +2230,7 @@
if (isa<UndefValue>(Ops[0])) {
// Compute the (pointer) type returned by the GEP instruction.
- Type *LastType = GetElementPtrInst::getIndexedType(PtrTy, Ops.data() + 1,
- Ops.size() - 1);
+ Type *LastType = GetElementPtrInst::getIndexedType(PtrTy, Ops.slice(1));
Type *GEPTy = PointerType::get(LastType, PtrTy->getAddressSpace());
return UndefValue::get(GEPTy);
}
Modified: llvm/branches/exception-handling-rewrite/lib/Analysis/PHITransAddr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Analysis/PHITransAddr.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Analysis/PHITransAddr.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Analysis/PHITransAddr.cpp Mon Jul 25 20:29:47 2011
@@ -407,9 +407,9 @@
}
GetElementPtrInst *Result =
- GetElementPtrInst::Create(GEPOps[0], GEPOps.begin()+1, GEPOps.end(),
- InVal->getName()+".phi.trans.insert",
- PredBB->getTerminator());
+ GetElementPtrInst::Create(GEPOps[0], makeArrayRef(GEPOps).slice(1),
+ InVal->getName()+".phi.trans.insert",
+ PredBB->getTerminator());
Result->setIsInBounds(GEP->isInBounds());
NewInsts.push_back(Result);
return Result;
Modified: llvm/branches/exception-handling-rewrite/lib/AsmParser/LLLexer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/AsmParser/LLLexer.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/AsmParser/LLLexer.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/AsmParser/LLLexer.cpp Mon Jul 25 20:29:47 2011
@@ -506,6 +506,15 @@
KEYWORD(deplibs);
KEYWORD(datalayout);
KEYWORD(volatile);
+ KEYWORD(atomic);
+ KEYWORD(unordered);
+ KEYWORD(monotonic);
+ KEYWORD(acquire);
+ KEYWORD(release);
+ KEYWORD(acq_rel);
+ KEYWORD(seq_cst);
+ KEYWORD(singlethread);
+
KEYWORD(nuw);
KEYWORD(nsw);
KEYWORD(exact);
@@ -635,6 +644,7 @@
INSTKEYWORD(alloca, Alloca);
INSTKEYWORD(load, Load);
INSTKEYWORD(store, Store);
+ INSTKEYWORD(fence, Fence);
INSTKEYWORD(getelementptr, GetElementPtr);
INSTKEYWORD(extractelement, ExtractElement);
Modified: llvm/branches/exception-handling-rewrite/lib/AsmParser/LLParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/AsmParser/LLParser.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/AsmParser/LLParser.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/AsmParser/LLParser.cpp Mon Jul 25 20:29:47 2011
@@ -1145,6 +1145,32 @@
return false;
}
+/// ParseScopeAndOrdering
+/// if isAtomic: ::= 'singlethread'? AtomicOrdering
+/// else: ::=
+///
+/// This sets Scope and Ordering to the parsed values.
+bool LLParser::ParseScopeAndOrdering(bool isAtomic, SynchronizationScope &Scope,
+ AtomicOrdering &Ordering) {
+ if (!isAtomic)
+ return false;
+
+ Scope = CrossThread;
+ if (EatIfPresent(lltok::kw_singlethread))
+ Scope = SingleThread;
+ switch (Lex.getKind()) {
+ default: return TokError("Expected ordering on atomic instruction");
+ case lltok::kw_unordered: Ordering = Unordered; break;
+ case lltok::kw_monotonic: Ordering = Monotonic; break;
+ case lltok::kw_acquire: Ordering = Acquire; break;
+ case lltok::kw_release: Ordering = Release; break;
+ case lltok::kw_acq_rel: Ordering = AcquireRelease; break;
+ case lltok::kw_seq_cst: Ordering = SequentiallyConsistent; break;
+ }
+ Lex.Lex();
+ return false;
+}
+
/// ParseOptionalStackAlignment
/// ::= /* empty */
/// ::= 'alignstack' '(' 4 ')'
@@ -2274,9 +2300,7 @@
return Error(ID.Loc, "getelementptr requires pointer operand");
ArrayRef<Constant *> Indices(Elts.begin() + 1, Elts.end());
- if (!GetElementPtrInst::getIndexedType(Elts[0]->getType(),
- (Value**)(Elts.data() + 1),
- Elts.size() - 1))
+ if (!GetElementPtrInst::getIndexedType(Elts[0]->getType(), Indices))
return Error(ID.Loc, "invalid indices for getelementptr");
ID.ConstantVal = ConstantExpr::getGetElementPtr(Elts[0], Indices,
InBounds);
@@ -2928,6 +2952,7 @@
case lltok::kw_alloca: return ParseAlloc(Inst, PFS);
case lltok::kw_load: return ParseLoad(Inst, PFS, false);
case lltok::kw_store: return ParseStore(Inst, PFS, false);
+ case lltok::kw_fence: return ParseFence(Inst, PFS);
case lltok::kw_volatile:
if (EatIfPresent(lltok::kw_load))
return ParseLoad(Inst, PFS, true);
@@ -3695,6 +3720,23 @@
return AteExtraComma ? InstExtraComma : InstNormal;
}
+/// ParseFence
+/// ::= 'fence' 'singlethread'? AtomicOrdering
+int LLParser::ParseFence(Instruction *&Inst, PerFunctionState &PFS) {
+ AtomicOrdering Ordering = NotAtomic;
+ SynchronizationScope Scope = CrossThread;
+ if (ParseScopeAndOrdering(true /*Always atomic*/, Scope, Ordering))
+ return true;
+
+ if (Ordering == Unordered)
+ return TokError("fence cannot be unordered");
+ if (Ordering == Monotonic)
+ return TokError("fence cannot be monotonic");
+
+ Inst = new FenceInst(Context, Ordering, Scope);
+ return InstNormal;
+}
+
/// ParseGetElementPtr
/// ::= 'getelementptr' 'inbounds'? TypeAndValue (',' TypeAndValue)*
int LLParser::ParseGetElementPtr(Instruction *&Inst, PerFunctionState &PFS) {
@@ -3720,10 +3762,9 @@
Indices.push_back(Val);
}
- if (!GetElementPtrInst::getIndexedType(Ptr->getType(),
- Indices.begin(), Indices.end()))
+ if (!GetElementPtrInst::getIndexedType(Ptr->getType(), Indices))
return Error(Loc, "invalid getelementptr indices");
- Inst = GetElementPtrInst::Create(Ptr, Indices.begin(), Indices.end());
+ Inst = GetElementPtrInst::Create(Ptr, Indices);
if (InBounds)
cast<GetElementPtrInst>(Inst)->setIsInBounds(true);
return AteExtraComma ? InstExtraComma : InstNormal;
Modified: llvm/branches/exception-handling-rewrite/lib/AsmParser/LLParser.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/AsmParser/LLParser.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/AsmParser/LLParser.h (original)
+++ llvm/branches/exception-handling-rewrite/lib/AsmParser/LLParser.h Mon Jul 25 20:29:47 2011
@@ -15,6 +15,7 @@
#define LLVM_ASMPARSER_LLPARSER_H
#include "LLLexer.h"
+#include "llvm/Instructions.h"
#include "llvm/Module.h"
#include "llvm/Type.h"
#include "llvm/ADT/DenseMap.h"
@@ -178,6 +179,8 @@
bool ParseOptionalVisibility(unsigned &Visibility);
bool ParseOptionalCallingConv(CallingConv::ID &CC);
bool ParseOptionalAlignment(unsigned &Alignment);
+ bool ParseScopeAndOrdering(bool isAtomic, SynchronizationScope &Scope,
+ AtomicOrdering &Ordering);
bool ParseOptionalStackAlignment(unsigned &Alignment);
bool ParseOptionalCommaAlign(unsigned &Alignment, bool &AteExtraComma);
bool ParseIndexList(SmallVectorImpl<unsigned> &Indices,bool &AteExtraComma);
@@ -362,6 +365,7 @@
int ParseAlloc(Instruction *&I, PerFunctionState &PFS);
int ParseLoad(Instruction *&I, PerFunctionState &PFS, bool isVolatile);
int ParseStore(Instruction *&I, PerFunctionState &PFS, bool isVolatile);
+ int ParseFence(Instruction *&I, PerFunctionState &PFS);
int ParseGetElementPtr(Instruction *&I, PerFunctionState &PFS);
int ParseExtractValue(Instruction *&I, PerFunctionState &PFS);
int ParseInsertValue(Instruction *&I, PerFunctionState &PFS);
Modified: llvm/branches/exception-handling-rewrite/lib/AsmParser/LLToken.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/AsmParser/LLToken.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/AsmParser/LLToken.h (original)
+++ llvm/branches/exception-handling-rewrite/lib/AsmParser/LLToken.h Mon Jul 25 20:29:47 2011
@@ -53,6 +53,9 @@
kw_deplibs,
kw_datalayout,
kw_volatile,
+ kw_atomic,
+ kw_unordered, kw_monotonic, kw_acquire, kw_release, kw_acq_rel, kw_seq_cst,
+ kw_singlethread,
kw_nuw,
kw_nsw,
kw_exact,
@@ -123,7 +126,7 @@
kw_ret, kw_br, kw_switch, kw_indirectbr, kw_invoke, kw_unwind, kw_resume,
kw_unreachable,
- kw_alloca, kw_load, kw_store, kw_getelementptr,
+ kw_alloca, kw_load, kw_store, kw_fence, kw_getelementptr,
kw_extractelement, kw_insertelement, kw_shufflevector,
kw_extractvalue, kw_insertvalue, kw_blockaddress,
Modified: llvm/branches/exception-handling-rewrite/lib/Bitcode/Reader/BitcodeReader.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Bitcode/Reader/BitcodeReader.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Bitcode/Reader/BitcodeReader.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Bitcode/Reader/BitcodeReader.cpp Mon Jul 25 20:29:47 2011
@@ -131,6 +131,27 @@
}
}
+static AtomicOrdering GetDecodedOrdering(unsigned Val) {
+ switch (Val) {
+ case bitc::ORDERING_NOTATOMIC: return NotAtomic;
+ case bitc::ORDERING_UNORDERED: return Unordered;
+ case bitc::ORDERING_MONOTONIC: return Monotonic;
+ case bitc::ORDERING_ACQUIRE: return Acquire;
+ case bitc::ORDERING_RELEASE: return Release;
+ case bitc::ORDERING_ACQREL: return AcquireRelease;
+ default: // Map unknown orderings to sequentially-consistent.
+ case bitc::ORDERING_SEQCST: return SequentiallyConsistent;
+ }
+}
+
+static SynchronizationScope GetDecodedSynchScope(unsigned Val) {
+ switch (Val) {
+ case bitc::SYNCHSCOPE_SINGLETHREAD: return SingleThread;
+ default: // Map unknown scopes to cross-thread.
+ case bitc::SYNCHSCOPE_CROSSTHREAD: return CrossThread;
+ }
+}
+
namespace llvm {
namespace {
/// @brief A class for maintaining the slot number definition
@@ -2181,7 +2202,7 @@
GEPIdx.push_back(Op);
}
- I = GetElementPtrInst::Create(BasePtr, GEPIdx.begin(), GEPIdx.end());
+ I = GetElementPtrInst::Create(BasePtr, GEPIdx);
InstructionList.push_back(I);
if (BitCode == bitc::FUNC_CODE_INST_INBOUNDS_GEP)
cast<GetElementPtrInst>(I)->setIsInBounds(true);
@@ -2572,6 +2593,18 @@
InstructionList.push_back(I);
break;
}
+ case bitc::FUNC_CODE_INST_FENCE: { // FENCE:[ordering, synchscope]
+ if (2 != Record.size())
+ return Error("Invalid FENCE record");
+ AtomicOrdering Ordering = GetDecodedOrdering(Record[0]);
+ if (Ordering == NotAtomic || Ordering == Unordered ||
+ Ordering == Monotonic)
+ return Error("Invalid FENCE record");
+ SynchronizationScope SynchScope = GetDecodedSynchScope(Record[1]);
+ I = new FenceInst(Context, Ordering, SynchScope);
+ InstructionList.push_back(I);
+ break;
+ }
case bitc::FUNC_CODE_INST_CALL: {
// CALL: [paramattrs, cc, fnty, fnid, arg0, arg1...]
if (Record.size() < 3)
Modified: llvm/branches/exception-handling-rewrite/lib/Bitcode/Writer/BitcodeWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Bitcode/Writer/BitcodeWriter.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Bitcode/Writer/BitcodeWriter.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Bitcode/Writer/BitcodeWriter.cpp Mon Jul 25 20:29:47 2011
@@ -101,6 +101,27 @@
}
}
+static unsigned GetEncodedOrdering(AtomicOrdering Ordering) {
+ switch (Ordering) {
+ default: llvm_unreachable("Unknown atomic ordering");
+ case NotAtomic: return bitc::ORDERING_NOTATOMIC;
+ case Unordered: return bitc::ORDERING_UNORDERED;
+ case Monotonic: return bitc::ORDERING_MONOTONIC;
+ case Acquire: return bitc::ORDERING_ACQUIRE;
+ case Release: return bitc::ORDERING_RELEASE;
+ case AcquireRelease: return bitc::ORDERING_ACQREL;
+ case SequentiallyConsistent: return bitc::ORDERING_SEQCST;
+ }
+}
+
+static unsigned GetEncodedSynchScope(SynchronizationScope SynchScope) {
+ switch (SynchScope) {
+ default: llvm_unreachable("Unknown synchronization scope");
+ case SingleThread: return bitc::SYNCHSCOPE_SINGLETHREAD;
+ case CrossThread: return bitc::SYNCHSCOPE_CROSSTHREAD;
+ }
+}
+
static void WriteStringRecord(unsigned Code, StringRef Str,
unsigned AbbrevToUse, BitstreamWriter &Stream) {
SmallVector<unsigned, 64> Vals;
@@ -1164,6 +1185,11 @@
Vals.push_back(Log2_32(cast<StoreInst>(I).getAlignment())+1);
Vals.push_back(cast<StoreInst>(I).isVolatile());
break;
+ case Instruction::Fence:
+ Code = bitc::FUNC_CODE_INST_FENCE;
+ Vals.push_back(GetEncodedOrdering(cast<FenceInst>(I).getOrdering()));
+ Vals.push_back(GetEncodedSynchScope(cast<FenceInst>(I).getSynchScope()));
+ break;
case Instruction::Call: {
const CallInst &CI = cast<CallInst>(I);
PointerType *PTy = cast<PointerType>(CI.getCalledValue()->getType());
Modified: llvm/branches/exception-handling-rewrite/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp Mon Jul 25 20:29:47 2011
@@ -23,7 +23,7 @@
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCSymbol.h"
-#include "llvm/MC/TargetAsmParser.h"
+#include "llvm/MC/MCTargetAsmParser.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegistry.h"
#include "llvm/ADT/OwningPtr.h"
@@ -121,7 +121,8 @@
STI(TM.getTarget().createMCSubtargetInfo(TM.getTargetTriple(),
TM.getTargetCPU(),
TM.getTargetFeatureString()));
- OwningPtr<TargetAsmParser> TAP(TM.getTarget().createAsmParser(*STI, *Parser));
+ OwningPtr<MCTargetAsmParser>
+ TAP(TM.getTarget().createMCAsmParser(*STI, *Parser));
if (!TAP)
report_fatal_error("Inline asm not supported by this streamer because"
" we don't have an asm parser for this target\n");
Modified: llvm/branches/exception-handling-rewrite/lib/CodeGen/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/CodeGen/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/CodeGen/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/CodeGen/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -33,7 +33,7 @@
LocalStackSlotAllocation.cpp
LowerSubregs.cpp
MachineBasicBlock.cpp
- MachineBlockFrequency.cpp
+ MachineBlockFrequencyInfo.cpp
MachineBranchProbabilityInfo.cpp
MachineCSE.cpp
MachineDominators.cpp
Modified: llvm/branches/exception-handling-rewrite/lib/CodeGen/CodeGen.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/CodeGen/CodeGen.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/CodeGen/CodeGen.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/CodeGen/CodeGen.cpp Mon Jul 25 20:29:47 2011
@@ -27,6 +27,7 @@
initializeLiveIntervalsPass(Registry);
initializeLiveStacksPass(Registry);
initializeLiveVariablesPass(Registry);
+ initializeMachineBlockFrequencyInfoPass(Registry);
initializeMachineCSEPass(Registry);
initializeMachineDominatorTreePass(Registry);
initializeMachineLICMPass(Registry);
Modified: llvm/branches/exception-handling-rewrite/lib/CodeGen/LLVMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/CodeGen/LLVMTargetMachine.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/CodeGen/LLVMTargetMachine.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/CodeGen/LLVMTargetMachine.cpp Mon Jul 25 20:29:47 2011
@@ -137,11 +137,11 @@
// Create a code emitter if asked to show the encoding.
MCCodeEmitter *MCE = 0;
- TargetAsmBackend *TAB = 0;
+ MCAsmBackend *MAB = 0;
if (ShowMCEncoding) {
const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
- MCE = getTarget().createCodeEmitter(*getInstrInfo(), STI, *Context);
- TAB = getTarget().createAsmBackend(getTargetTriple());
+ MCE = getTarget().createMCCodeEmitter(*getInstrInfo(), STI, *Context);
+ MAB = getTarget().createMCAsmBackend(getTargetTriple());
}
MCStreamer *S = getTarget().createAsmStreamer(*Context, Out,
@@ -149,7 +149,7 @@
hasMCUseLoc(),
hasMCUseCFI(),
InstPrinter,
- MCE, TAB,
+ MCE, MAB,
ShowMCInst);
AsmStreamer.reset(S);
break;
@@ -158,16 +158,16 @@
// Create the code emitter for the target if it exists. If not, .o file
// emission fails.
const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
- MCCodeEmitter *MCE = getTarget().createCodeEmitter(*getInstrInfo(), STI,
- *Context);
- TargetAsmBackend *TAB = getTarget().createAsmBackend(getTargetTriple());
- if (MCE == 0 || TAB == 0)
+ MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(*getInstrInfo(), STI,
+ *Context);
+ MCAsmBackend *MAB = getTarget().createMCAsmBackend(getTargetTriple());
+ if (MCE == 0 || MAB == 0)
return true;
- AsmStreamer.reset(getTarget().createObjectStreamer(getTargetTriple(),
- *Context, *TAB, Out, MCE,
- hasMCRelaxAll(),
- hasMCNoExecStack()));
+ AsmStreamer.reset(getTarget().createMCObjectStreamer(getTargetTriple(),
+ *Context, *MAB, Out,
+ MCE, hasMCRelaxAll(),
+ hasMCNoExecStack()));
AsmStreamer.get()->InitSections();
break;
}
@@ -236,16 +236,16 @@
// Create the code emitter for the target if it exists. If not, .o file
// emission fails.
const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
- MCCodeEmitter *MCE = getTarget().createCodeEmitter(*getInstrInfo(),STI, *Ctx);
- TargetAsmBackend *TAB = getTarget().createAsmBackend(getTargetTriple());
- if (MCE == 0 || TAB == 0)
+ MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(*getInstrInfo(),STI, *Ctx);
+ MCAsmBackend *MAB = getTarget().createMCAsmBackend(getTargetTriple());
+ if (MCE == 0 || MAB == 0)
return true;
OwningPtr<MCStreamer> AsmStreamer;
- AsmStreamer.reset(getTarget().createObjectStreamer(getTargetTriple(), *Ctx,
- *TAB, Out, MCE,
- hasMCRelaxAll(),
- hasMCNoExecStack()));
+ AsmStreamer.reset(getTarget().createMCObjectStreamer(getTargetTriple(), *Ctx,
+ *MAB, Out, MCE,
+ hasMCRelaxAll(),
+ hasMCNoExecStack()));
AsmStreamer.get()->InitSections();
// Create the AsmPrinter, which takes ownership of AsmStreamer if successful.
Removed: llvm/branches/exception-handling-rewrite/lib/CodeGen/MachineBlockFrequency.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/CodeGen/MachineBlockFrequency.cpp?rev=136039&view=auto
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/CodeGen/MachineBlockFrequency.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/CodeGen/MachineBlockFrequency.cpp (removed)
@@ -1,60 +0,0 @@
-//====----- MachineBlockFrequency.cpp - Machine Block Frequency Analysis ----====//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// Loops should be simplified before this analysis.
-//
-//===----------------------------------------------------------------------===//
-
-#include "llvm/InitializePasses.h"
-#include "llvm/Analysis/BlockFrequencyImpl.h"
-#include "llvm/CodeGen/MachineBlockFrequency.h"
-#include "llvm/CodeGen/Passes.h"
-#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
-
-using namespace llvm;
-
-INITIALIZE_PASS_BEGIN(MachineBlockFrequency, "machine-block-freq",
- "Machine Block Frequency Analysis", true, true)
-INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
-INITIALIZE_PASS_END(MachineBlockFrequency, "machine-block-freq",
- "Machine Block Frequency Analysis", true, true)
-
-char MachineBlockFrequency::ID = 0;
-
-
-MachineBlockFrequency::MachineBlockFrequency() : MachineFunctionPass(ID) {
- initializeMachineBlockFrequencyPass(*PassRegistry::getPassRegistry());
- MBFI = new BlockFrequencyImpl<MachineBasicBlock, MachineFunction,
- MachineBranchProbabilityInfo>();
-}
-
-MachineBlockFrequency::~MachineBlockFrequency() {
- delete MBFI;
-}
-
-void MachineBlockFrequency::getAnalysisUsage(AnalysisUsage &AU) const {
- AU.addRequired<MachineBranchProbabilityInfo>();
- AU.setPreservesAll();
- MachineFunctionPass::getAnalysisUsage(AU);
-}
-
-bool MachineBlockFrequency::runOnMachineFunction(MachineFunction &F) {
- MachineBranchProbabilityInfo &MBPI = getAnalysis<MachineBranchProbabilityInfo>();
- MBFI->doFunction(&F, &MBPI);
- return false;
-}
-
-/// getblockFreq - Return block frequency. Return 0 if we don't have the
-/// information. Please note that initial frequency is equal to 1024. It means
-/// that we should not rely on the value itself, but only on the comparison to
-/// the other block frequencies. We do this to avoid using of floating points.
-///
-uint32_t MachineBlockFrequency::getBlockFreq(MachineBasicBlock *MBB) {
- return MBFI->getBlockFreq(MBB);
-}
Modified: llvm/branches/exception-handling-rewrite/lib/CodeGen/RegAllocGreedy.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/CodeGen/RegAllocGreedy.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/CodeGen/RegAllocGreedy.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/CodeGen/RegAllocGreedy.cpp Mon Jul 25 20:29:47 2011
@@ -90,12 +90,26 @@
// range splitting algorithm terminates, something that is otherwise hard to
// ensure.
enum LiveRangeStage {
- RS_New, ///< Never seen before.
- RS_First, ///< First time in the queue.
- RS_Second, ///< Second time in the queue.
- RS_Global, ///< Produced by global splitting.
- RS_Local, ///< Produced by local splitting.
- RS_Spill ///< Produced by spilling.
+ /// Newly created live range that has never been queued.
+ RS_New,
+
+ /// Only attempt assignment and eviction. Then requeue as RS_Split.
+ RS_Assign,
+
+ /// Attempt live range splitting if assignment is impossible.
+ RS_Split,
+
+ /// Attempt more aggressive live range splitting that is guaranteed to make
+ /// progress. This is used for split products that may not be making
+ /// progress.
+ RS_Split2,
+
+ /// Live range will be spilled. No more splitting will be attempted.
+ RS_Spill,
+
+ /// There is nothing more we can do to this live range. Abort compilation
+ /// if it can't be assigned.
+ RS_Done
};
static const char *const StageName[];
@@ -234,12 +248,12 @@
#ifndef NDEBUG
const char *const RAGreedy::StageName[] = {
- "RS_New",
- "RS_First",
- "RS_Second",
- "RS_Global",
- "RS_Local",
- "RS_Spill"
+ "RS_New",
+ "RS_Assign",
+ "RS_Split",
+ "RS_Split2",
+ "RS_Spill",
+ "RS_Done"
};
#endif
@@ -327,8 +341,10 @@
void RAGreedy::LRE_DidCloneVirtReg(unsigned New, unsigned Old) {
// LRE may clone a virtual register because dead code elimination causes it to
- // be split into connected components. Ensure that the new register gets the
+ // be split into connected components. The new components are much smaller
+ // than the original, so they should get a new chance at being assigned.
// same stage as the parent.
+ ExtraRegInfo[Old].Stage = RS_Assign;
ExtraRegInfo.grow(New);
ExtraRegInfo[New] = ExtraRegInfo[Old];
}
@@ -351,9 +367,9 @@
ExtraRegInfo.grow(Reg);
if (ExtraRegInfo[Reg].Stage == RS_New)
- ExtraRegInfo[Reg].Stage = RS_First;
+ ExtraRegInfo[Reg].Stage = RS_Assign;
- if (ExtraRegInfo[Reg].Stage == RS_Second)
+ if (ExtraRegInfo[Reg].Stage == RS_Split)
// Unsplit ranges that couldn't be allocated immediately are deferred until
// everything else has been allocated. Long ranges are allocated last so
// they are split against realistic interference.
@@ -443,7 +459,7 @@
/// @param BreaksHint True when B is already assigned to its preferred register.
bool RAGreedy::shouldEvict(LiveInterval &A, bool IsHint,
LiveInterval &B, bool BreaksHint) {
- bool CanSplit = getStage(B) <= RS_Second;
+ bool CanSplit = getStage(B) < RS_Spill;
// Be fairly aggressive about following hints as long as the evictee can be
// split.
@@ -488,7 +504,7 @@
if (TargetRegisterInfo::isPhysicalRegister(Intf->reg))
return false;
// Never evict spill products. They cannot split or spill.
- if (getStage(*Intf) == RS_Spill)
+ if (getStage(*Intf) == RS_Done)
return false;
// Once a live range becomes small enough, it is urgent that we find a
// register for it. This is indicated by an infinite spill weight. These
@@ -974,18 +990,18 @@
// Remainder interval. Don't try splitting again, spill if it doesn't
// allocate.
if (IntvMap[i] == 0) {
- setStage(Reg, RS_Global);
+ setStage(Reg, RS_Spill);
continue;
}
// Main interval. Allow repeated splitting as long as the number of live
- // blocks is strictly decreasing.
+ // blocks is strictly decreasing. Otherwise force per-block splitting.
if (IntvMap[i] == MainIntv) {
if (SA->countLiveBlocks(&Reg) >= OrigBlocks) {
DEBUG(dbgs() << "Main interval covers the same " << OrigBlocks
<< " blocks as original.\n");
// Don't allow repeated splitting as a safe guard against looping.
- setStage(Reg, RS_Global);
+ setStage(Reg, RS_Split2);
}
continue;
}
@@ -1172,17 +1188,17 @@
//
// Instead we use these rules:
//
- // 1. Allow any split for ranges with getStage() < RS_Local. (Except for the
+ // 1. Allow any split for ranges with getStage() < RS_Split2. (Except for the
// noop split, of course).
- // 2. Require progress be made for ranges with getStage() >= RS_Local. All
+ // 2. Require progress be made for ranges with getStage() == RS_Split2. All
// the new ranges must have fewer instructions than before the split.
- // 3. New ranges with the same number of instructions are marked RS_Local,
+ // 3. New ranges with the same number of instructions are marked RS_Split2,
// smaller ranges are marked RS_New.
//
// These rules allow a 3 -> 2+3 split once, which we need. They also prevent
// excessive splitting and infinite loops.
//
- bool ProgressRequired = getStage(VirtReg) >= RS_Local;
+ bool ProgressRequired = getStage(VirtReg) >= RS_Split2;
// Best split candidate.
unsigned BestBefore = NumGaps;
@@ -1301,7 +1317,7 @@
DebugVars->splitRegister(VirtReg.reg, LREdit.regs());
// If the new range has the same number of instructions as before, mark it as
- // RS_Local so the next split will be forced to make progress. Otherwise,
+ // RS_Split2 so the next split will be forced to make progress. Otherwise,
// leave the new intervals as RS_New so they can compete.
bool LiveBefore = BestBefore != 0 || BI.LiveIn;
bool LiveAfter = BestAfter != NumGaps || BI.LiveOut;
@@ -1311,7 +1327,7 @@
assert(!ProgressRequired && "Didn't make progress when it was required.");
for (unsigned i = 0, e = IntvMap.size(); i != e; ++i)
if (IntvMap[i] == 1) {
- setStage(*LREdit.get(i), RS_Local);
+ setStage(*LREdit.get(i), RS_Split2);
DEBUG(dbgs() << PrintReg(LREdit.get(i)->reg));
}
DEBUG(dbgs() << '\n');
@@ -1339,9 +1355,8 @@
NamedRegionTimer T("Global Splitting", TimerGroupName, TimePassesIsEnabled);
- // Don't iterate global splitting.
- // Move straight to spilling if this range was produced by a global split.
- if (getStage(VirtReg) >= RS_Global)
+ // Ranges must be Split2 or less.
+ if (getStage(VirtReg) >= RS_Spill)
return 0;
SA->analyze(&VirtReg);
@@ -1357,10 +1372,14 @@
return PhysReg;
}
- // First try to split around a region spanning multiple blocks.
- unsigned PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs);
- if (PhysReg || !NewVRegs.empty())
- return PhysReg;
+ // First try to split around a region spanning multiple blocks. RS_Split2
+ // ranges already made dubious progress with region splitting, so they go
+ // straight to single block splitting.
+ if (getStage(VirtReg) < RS_Split2) {
+ unsigned PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs);
+ if (PhysReg || !NewVRegs.empty())
+ return PhysReg;
+ }
// Then isolate blocks with multiple uses.
SplitAnalysis::BlockPtrSet Blocks;
@@ -1368,7 +1387,7 @@
LiveRangeEdit LREdit(VirtReg, NewVRegs, this);
SE->reset(LREdit);
SE->splitSingleBlocks(Blocks);
- setStage(NewVRegs.begin(), NewVRegs.end(), RS_Global);
+ setStage(NewVRegs.begin(), NewVRegs.end(), RS_Spill);
if (VerifyEnabled)
MF->verify(this, "After splitting live range around basic blocks");
}
@@ -1394,9 +1413,9 @@
<< " Cascade " << ExtraRegInfo[VirtReg.reg].Cascade << '\n');
// Try to evict a less worthy live range, but only for ranges from the primary
- // queue. The RS_Second ranges already failed to do this, and they should not
+ // queue. The RS_Split ranges already failed to do this, and they should not
// get a second chance until they have been split.
- if (Stage != RS_Second)
+ if (Stage != RS_Split)
if (unsigned PhysReg = tryEvict(VirtReg, Order, NewVRegs))
return PhysReg;
@@ -1405,8 +1424,8 @@
// The first time we see a live range, don't try to split or spill.
// Wait until the second time, when all smaller ranges have been allocated.
// This gives a better picture of the interference to split around.
- if (Stage == RS_First) {
- setStage(VirtReg, RS_Second);
+ if (Stage < RS_Split) {
+ setStage(VirtReg, RS_Split);
DEBUG(dbgs() << "wait for second round\n");
NewVRegs.push_back(&VirtReg);
return 0;
@@ -1414,7 +1433,7 @@
// If we couldn't allocate a register from spilling, there is probably some
// invalid inline assembly. The base class wil report it.
- if (Stage >= RS_Spill || !VirtReg.isSpillable())
+ if (Stage >= RS_Done || !VirtReg.isSpillable())
return ~0u;
// Try splitting VirtReg or interferences.
@@ -1426,7 +1445,7 @@
NamedRegionTimer T("Spiller", TimerGroupName, TimePassesIsEnabled);
LiveRangeEdit LRE(VirtReg, NewVRegs, this);
spiller().spill(LRE);
- setStage(NewVRegs.begin(), NewVRegs.end(), RS_Spill);
+ setStage(NewVRegs.begin(), NewVRegs.end(), RS_Done);
if (VerifyEnabled)
MF->verify(this, "After spilling");
Modified: llvm/branches/exception-handling-rewrite/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Jul 25 20:29:47 2011
@@ -6896,7 +6896,7 @@
// If Idx was -1 above, Elt is going to be -1, so just return undef.
if (Elt == -1)
- return DAG.getUNDEF(LN0->getBasePtr().getValueType());
+ return DAG.getUNDEF(LVT);
unsigned Align = LN0->getAlignment();
if (NewLoad) {
Modified: llvm/branches/exception-handling-rewrite/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Mon Jul 25 20:29:47 2011
@@ -3220,6 +3220,10 @@
DAG.setRoot(StoreNode);
}
+void SelectionDAGBuilder::visitFence(const FenceInst &I) {
+ llvm_unreachable("Not implemented yet");
+}
+
/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
/// node.
void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
Modified: llvm/branches/exception-handling-rewrite/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h (original)
+++ llvm/branches/exception-handling-rewrite/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h Mon Jul 25 20:29:47 2011
@@ -506,6 +506,7 @@
void visitAlloca(const AllocaInst &I);
void visitLoad(const LoadInst &I);
void visitStore(const StoreInst &I);
+ void visitFence(const FenceInst &I);
void visitPHI(const PHINode &I);
void visitCall(const CallInst &I);
bool visitMemCmpCall(const CallInst &I);
Modified: llvm/branches/exception-handling-rewrite/lib/CodeGen/SjLjEHPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/CodeGen/SjLjEHPrepare.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/CodeGen/SjLjEHPrepare.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/CodeGen/SjLjEHPrepare.cpp Mon Jul 25 20:29:47 2011
@@ -386,22 +386,20 @@
// We need to also keep around a reference to the call_site field
Idxs[0] = Zero;
Idxs[1] = ConstantInt::get(Int32Ty, 1);
- CallSite = GetElementPtrInst::Create(FunctionContext, Idxs, Idxs+2,
- "call_site",
+ CallSite = GetElementPtrInst::Create(FunctionContext, Idxs, "call_site",
EntryBB->getTerminator());
// The exception selector comes back in context->data[1]
Idxs[1] = ConstantInt::get(Int32Ty, 2);
- Value *FCData = GetElementPtrInst::Create(FunctionContext, Idxs, Idxs+2,
- "fc_data",
+ Value *FCData = GetElementPtrInst::Create(FunctionContext, Idxs, "fc_data",
EntryBB->getTerminator());
Idxs[1] = ConstantInt::get(Int32Ty, 1);
- Value *SelectorAddr = GetElementPtrInst::Create(FCData, Idxs, Idxs+2,
+ Value *SelectorAddr = GetElementPtrInst::Create(FCData, Idxs,
"exc_selector_gep",
EntryBB->getTerminator());
// The exception value comes back in context->data[0]
Idxs[1] = Zero;
- Value *ExceptionAddr = GetElementPtrInst::Create(FCData, Idxs, Idxs+2,
+ Value *ExceptionAddr = GetElementPtrInst::Create(FCData, Idxs,
"exception_gep",
EntryBB->getTerminator());
@@ -466,8 +464,7 @@
Idxs[0] = Zero;
Idxs[1] = ConstantInt::get(Int32Ty, 4);
Value *LSDAFieldPtr =
- GetElementPtrInst::Create(FunctionContext, Idxs, Idxs+2,
- "lsda_gep",
+ GetElementPtrInst::Create(FunctionContext, Idxs, "lsda_gep",
EntryBB->getTerminator());
Value *LSDA = CallInst::Create(LSDAAddrFn, "lsda_addr",
EntryBB->getTerminator());
@@ -475,8 +472,7 @@
Idxs[1] = ConstantInt::get(Int32Ty, 3);
Value *PersonalityFieldPtr =
- GetElementPtrInst::Create(FunctionContext, Idxs, Idxs+2,
- "lsda_gep",
+ GetElementPtrInst::Create(FunctionContext, Idxs, "lsda_gep",
EntryBB->getTerminator());
new StoreInst(PersonalityFn, PersonalityFieldPtr, true,
EntryBB->getTerminator());
@@ -484,12 +480,11 @@
// Save the frame pointer.
Idxs[1] = ConstantInt::get(Int32Ty, 5);
Value *JBufPtr
- = GetElementPtrInst::Create(FunctionContext, Idxs, Idxs+2,
- "jbuf_gep",
+ = GetElementPtrInst::Create(FunctionContext, Idxs, "jbuf_gep",
EntryBB->getTerminator());
Idxs[1] = ConstantInt::get(Int32Ty, 0);
Value *FramePtr =
- GetElementPtrInst::Create(JBufPtr, Idxs, Idxs+2, "jbuf_fp_gep",
+ GetElementPtrInst::Create(JBufPtr, Idxs, "jbuf_fp_gep",
EntryBB->getTerminator());
Value *Val = CallInst::Create(FrameAddrFn,
@@ -501,7 +496,7 @@
// Save the stack pointer.
Idxs[1] = ConstantInt::get(Int32Ty, 2);
Value *StackPtr =
- GetElementPtrInst::Create(JBufPtr, Idxs, Idxs+2, "jbuf_sp_gep",
+ GetElementPtrInst::Create(JBufPtr, Idxs, "jbuf_sp_gep",
EntryBB->getTerminator());
Val = CallInst::Create(StackAddrFn, "sp", EntryBB->getTerminator());
Modified: llvm/branches/exception-handling-rewrite/lib/MC/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/MC/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/MC/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/MC/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -38,8 +38,8 @@
WinCOFFStreamer.cpp
WinCOFFObjectWriter.cpp
SubtargetFeature.cpp
- TargetAsmBackend.cpp
- TargetAsmLexer.cpp
+ MCAsmBackend.cpp
+ MCTargetAsmLexer.cpp
)
add_subdirectory(MCParser)
Modified: llvm/branches/exception-handling-rewrite/lib/MC/ELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/MC/ELFObjectWriter.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/MC/ELFObjectWriter.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/MC/ELFObjectWriter.cpp Mon Jul 25 20:29:47 2011
@@ -15,12 +15,12 @@
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/StringMap.h"
#include "llvm/ADT/Twine.h"
+#include "llvm/MC/MCAsmBackend.h"
#include "llvm/MC/MCAsmLayout.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCSectionELF.h"
#include "llvm/MC/MCValue.h"
-#include "llvm/MC/TargetAsmBackend.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/ELF.h"
@@ -28,7 +28,7 @@
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringSwitch.h"
-#include "../Target/X86/X86FixupKinds.h"
+#include "../Target/X86/MCTargetDesc/X86FixupKinds.h"
#include "../Target/ARM/MCTargetDesc/ARMFixupKinds.h"
#include <vector>
Modified: llvm/branches/exception-handling-rewrite/lib/MC/MCAsmStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/MC/MCAsmStreamer.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/MC/MCAsmStreamer.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/MC/MCAsmStreamer.cpp Mon Jul 25 20:29:47 2011
@@ -19,7 +19,7 @@
#include "llvm/MC/MCSectionCOFF.h"
#include "llvm/MC/MCSectionMachO.h"
#include "llvm/MC/MCSymbol.h"
-#include "llvm/MC/TargetAsmBackend.h"
+#include "llvm/MC/MCAsmBackend.h"
#include "llvm/ADT/OwningPtr.h"
#include "llvm/ADT/SmallString.h"
#include "llvm/ADT/StringExtras.h"
@@ -41,7 +41,7 @@
private:
OwningPtr<MCInstPrinter> InstPrinter;
OwningPtr<MCCodeEmitter> Emitter;
- OwningPtr<TargetAsmBackend> AsmBackend;
+ OwningPtr<MCAsmBackend> AsmBackend;
SmallString<128> CommentToEmit;
raw_svector_ostream CommentStream;
@@ -64,7 +64,7 @@
MCAsmStreamer(MCContext &Context, formatted_raw_ostream &os,
bool isVerboseAsm, bool useLoc, bool useCFI,
MCInstPrinter *printer, MCCodeEmitter *emitter,
- TargetAsmBackend *asmbackend,
+ MCAsmBackend *asmbackend,
bool showInst)
: MCStreamer(Context), OS(os), MAI(Context.getAsmInfo()),
InstPrinter(printer), Emitter(emitter), AsmBackend(asmbackend),
@@ -1262,8 +1262,8 @@
formatted_raw_ostream &OS,
bool isVerboseAsm, bool useLoc,
bool useCFI, MCInstPrinter *IP,
- MCCodeEmitter *CE, TargetAsmBackend *TAB,
+ MCCodeEmitter *CE, MCAsmBackend *MAB,
bool ShowInst) {
return new MCAsmStreamer(Context, OS, isVerboseAsm, useLoc, useCFI,
- IP, CE, TAB, ShowInst);
+ IP, CE, MAB, ShowInst);
}
Modified: llvm/branches/exception-handling-rewrite/lib/MC/MCAssembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/MC/MCAssembler.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/MC/MCAssembler.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/MC/MCAssembler.cpp Mon Jul 25 20:29:47 2011
@@ -18,7 +18,7 @@
#include "llvm/MC/MCSymbol.h"
#include "llvm/MC/MCValue.h"
#include "llvm/MC/MCDwarf.h"
-#include "llvm/MC/TargetAsmBackend.h"
+#include "llvm/MC/MCAsmBackend.h"
#include "llvm/ADT/OwningPtr.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringExtras.h"
@@ -194,7 +194,7 @@
/* *** */
-MCAssembler::MCAssembler(MCContext &Context_, TargetAsmBackend &Backend_,
+MCAssembler::MCAssembler(MCContext &Context_, MCAsmBackend &Backend_,
MCCodeEmitter &Emitter_, MCObjectWriter &Writer_,
raw_ostream &OS_)
: Context(Context_), Backend(Backend_), Emitter(Emitter_), Writer(Writer_),
Modified: llvm/branches/exception-handling-rewrite/lib/MC/MCDisassembler/Disassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/MC/MCDisassembler/Disassembler.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/MC/MCDisassembler/Disassembler.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/MC/MCDisassembler/Disassembler.cpp Mon Jul 25 20:29:47 2011
@@ -38,7 +38,6 @@
// Initialize targets and assembly printers/parsers.
llvm::InitializeAllTargetInfos();
llvm::InitializeAllTargetMCs();
- llvm::InitializeAllAsmPrinters();
llvm::InitializeAllAsmParsers();
llvm::InitializeAllDisassemblers();
Modified: llvm/branches/exception-handling-rewrite/lib/MC/MCDisassembler/EDDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/MC/MCDisassembler/EDDisassembler.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/MC/MCDisassembler/EDDisassembler.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/MC/MCDisassembler/EDDisassembler.cpp Mon Jul 25 20:29:47 2011
@@ -28,14 +28,12 @@
#include "llvm/MC/MCParser/AsmLexer.h"
#include "llvm/MC/MCParser/MCAsmParser.h"
#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
-#include "llvm/MC/TargetAsmLexer.h"
-#include "llvm/MC/TargetAsmParser.h"
+#include "llvm/MC/MCTargetAsmLexer.h"
+#include "llvm/MC/MCTargetAsmParser.h"
#include "llvm/Support/MemoryBuffer.h"
#include "llvm/Support/MemoryObject.h"
#include "llvm/Support/SourceMgr.h"
#include "llvm/Target/TargetRegistry.h"
-#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSelect.h"
using namespace llvm;
@@ -107,9 +105,7 @@
sInitialized = true;
InitializeAllTargetInfos();
- InitializeAllTargets();
InitializeAllTargetMCs();
- InitializeAllAsmPrinters();
InitializeAllAsmParsers();
InitializeAllDisassemblers();
}
@@ -170,29 +166,18 @@
if (!Tgt)
return;
- std::string CPU;
- std::string featureString;
- TargetMachine.reset(Tgt->createTargetMachine(tripleString, CPU,
- featureString));
+ MRI.reset(Tgt->createMCRegInfo(tripleString));
- // FIXME: It shouldn't be using TargetRegisterInfo!
- const TargetRegisterInfo *registerInfo = TargetMachine->getRegisterInfo();
-
- if (!registerInfo)
+ if (!MRI)
return;
-
- initMaps(*registerInfo);
+
+ initMaps(*MRI);
AsmInfo.reset(Tgt->createMCAsmInfo(tripleString));
if (!AsmInfo)
return;
- MRI.reset(Tgt->createMCRegInfo(tripleString));
-
- if (!MRI)
- return;
-
Disassembler.reset(Tgt->createMCDisassembler());
if (!Disassembler)
@@ -208,10 +193,10 @@
return;
GenericAsmLexer.reset(new AsmLexer(*AsmInfo));
- SpecificAsmLexer.reset(Tgt->createAsmLexer(*AsmInfo));
+ SpecificAsmLexer.reset(Tgt->createMCAsmLexer(*MRI, *AsmInfo));
SpecificAsmLexer->InstallLexer(*GenericAsmLexer);
- initMaps(*TargetMachine->getRegisterInfo());
+ initMaps(*MRI);
Valid = true;
}
@@ -273,7 +258,7 @@
}
}
-void EDDisassembler::initMaps(const TargetRegisterInfo ®isterInfo) {
+void EDDisassembler::initMaps(const MCRegisterInfo ®isterInfo) {
unsigned numRegisters = registerInfo.getNumRegs();
unsigned registerIndex;
@@ -383,8 +368,8 @@
StringRef triple = tripleFromArch(Key.Arch);
OwningPtr<MCSubtargetInfo> STI(Tgt->createMCSubtargetInfo(triple, "", ""));
- OwningPtr<TargetAsmParser> TargetParser(Tgt->createAsmParser(*STI,
- *genericParser));
+ OwningPtr<MCTargetAsmParser>
+ TargetParser(Tgt->createMCAsmParser(*STI, *genericParser));
AsmToken OpcodeToken = genericParser->Lex();
AsmToken NextToken = genericParser->Lex(); // consume next token, because specificParser expects us to
Modified: llvm/branches/exception-handling-rewrite/lib/MC/MCDisassembler/EDDisassembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/MC/MCDisassembler/EDDisassembler.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/MC/MCDisassembler/EDDisassembler.h (original)
+++ llvm/branches/exception-handling-rewrite/lib/MC/MCDisassembler/EDDisassembler.h Mon Jul 25 20:29:47 2011
@@ -41,13 +41,11 @@
class MCRegisterInfo;
class MCStreamer;
class MCSubtargetInfo;
+class MCTargetAsmLexer;
+class MCTargetAsmParser;
template <typename T> class SmallVectorImpl;
class SourceMgr;
class Target;
-class TargetAsmLexer;
-class TargetAsmParser;
-class TargetMachine;
-class TargetRegisterInfo;
struct EDInstInfo;
struct EDInst;
@@ -137,8 +135,6 @@
CPUKey Key;
/// The LLVM target corresponding to the disassembler
const llvm::Target *Tgt;
- /// The target machine instance.
- llvm::OwningPtr<llvm::TargetMachine> TargetMachine;
/// The assembly information for the target architecture
llvm::OwningPtr<const llvm::MCAsmInfo> AsmInfo;
// The register information for the target architecture.
@@ -163,7 +159,7 @@
/// The target-specific lexer for use in tokenizing strings, in
/// target-independent and target-specific portions
llvm::OwningPtr<llvm::AsmLexer> GenericAsmLexer;
- llvm::OwningPtr<llvm::TargetAsmLexer> SpecificAsmLexer;
+ llvm::OwningPtr<llvm::MCTargetAsmLexer> SpecificAsmLexer;
/// The guard for the above
llvm::sys::Mutex ParserMutex;
/// The LLVM number used for the target disassembly syntax variant
@@ -219,7 +215,7 @@
/// info
///
/// @arg registerInfo - the register information to use as a source
- void initMaps(const llvm::TargetRegisterInfo ®isterInfo);
+ void initMaps(const llvm::MCRegisterInfo ®isterInfo);
/// nameWithRegisterID - Returns the name (owned by the EDDisassembler) of a
/// register for a given register ID, or NULL on failure
///
Modified: llvm/branches/exception-handling-rewrite/lib/MC/MCELF.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/MC/MCELF.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/MC/MCELF.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/MC/MCELF.cpp Mon Jul 25 20:29:47 2011
@@ -15,7 +15,6 @@
#include "llvm/MC/MCAssembler.h"
#include "llvm/MC/MCELFSymbolFlags.h"
#include "llvm/MC/MCFixupKindInfo.h"
-#include "llvm/MC/TargetAsmBackend.h"
#include "llvm/Support/ELF.h"
namespace llvm {
Modified: llvm/branches/exception-handling-rewrite/lib/MC/MCELFStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/MC/MCELFStreamer.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/MC/MCELFStreamer.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/MC/MCELFStreamer.cpp Mon Jul 25 20:29:47 2011
@@ -21,7 +21,7 @@
#include "llvm/MC/MCSection.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/MC/MCValue.h"
-#include "llvm/MC/TargetAsmBackend.h"
+#include "llvm/MC/MCAsmBackend.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ELF.h"
#include "llvm/Support/ErrorHandling.h"
@@ -374,10 +374,10 @@
this->MCObjectStreamer::Finish();
}
-MCStreamer *llvm::createELFStreamer(MCContext &Context, TargetAsmBackend &TAB,
+MCStreamer *llvm::createELFStreamer(MCContext &Context, MCAsmBackend &MAB,
raw_ostream &OS, MCCodeEmitter *CE,
bool RelaxAll, bool NoExecStack) {
- MCELFStreamer *S = new MCELFStreamer(Context, TAB, OS, CE);
+ MCELFStreamer *S = new MCELFStreamer(Context, MAB, OS, CE);
if (RelaxAll)
S->getAssembler().setRelaxAll(true);
if (NoExecStack)
Modified: llvm/branches/exception-handling-rewrite/lib/MC/MCELFStreamer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/MC/MCELFStreamer.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/MC/MCELFStreamer.h (original)
+++ llvm/branches/exception-handling-rewrite/lib/MC/MCELFStreamer.h Mon Jul 25 20:29:47 2011
@@ -25,11 +25,11 @@
class MCELFStreamer : public MCObjectStreamer {
public:
- MCELFStreamer(MCContext &Context, TargetAsmBackend &TAB,
+ MCELFStreamer(MCContext &Context, MCAsmBackend &TAB,
raw_ostream &OS, MCCodeEmitter *Emitter)
: MCObjectStreamer(Context, TAB, OS, Emitter) {}
- MCELFStreamer(MCContext &Context, TargetAsmBackend &TAB,
+ MCELFStreamer(MCContext &Context, MCAsmBackend &TAB,
raw_ostream &OS, MCCodeEmitter *Emitter,
MCAssembler *Assembler)
: MCObjectStreamer(Context, TAB, OS, Emitter, Assembler) {}
Modified: llvm/branches/exception-handling-rewrite/lib/MC/MCExpr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/MC/MCExpr.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/MC/MCExpr.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/MC/MCExpr.cpp Mon Jul 25 20:29:47 2011
@@ -16,7 +16,6 @@
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/MC/MCValue.h"
-#include "llvm/MC/TargetAsmBackend.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
Modified: llvm/branches/exception-handling-rewrite/lib/MC/MCMachOStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/MC/MCMachOStreamer.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/MC/MCMachOStreamer.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/MC/MCMachOStreamer.cpp Mon Jul 25 20:29:47 2011
@@ -20,7 +20,7 @@
#include "llvm/MC/MCMachOSymbolFlags.h"
#include "llvm/MC/MCSectionMachO.h"
#include "llvm/MC/MCDwarf.h"
-#include "llvm/MC/TargetAsmBackend.h"
+#include "llvm/MC/MCAsmBackend.h"
#include "llvm/Support/Dwarf.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
@@ -34,9 +34,9 @@
virtual void EmitInstToData(const MCInst &Inst);
public:
- MCMachOStreamer(MCContext &Context, TargetAsmBackend &TAB,
+ MCMachOStreamer(MCContext &Context, MCAsmBackend &MAB,
raw_ostream &OS, MCCodeEmitter *Emitter)
- : MCObjectStreamer(Context, TAB, OS, Emitter) {}
+ : MCObjectStreamer(Context, MAB, OS, Emitter) {}
/// @name MCStreamer Interface
/// @{
@@ -207,8 +207,8 @@
case MCSA_ELF_TypeCommon:
case MCSA_ELF_TypeNoType:
case MCSA_ELF_TypeGnuUniqueObject:
- case MCSA_IndirectSymbol:
case MCSA_Hidden:
+ case MCSA_IndirectSymbol:
case MCSA_Internal:
case MCSA_Protected:
case MCSA_Weak:
@@ -410,10 +410,10 @@
this->MCObjectStreamer::Finish();
}
-MCStreamer *llvm::createMachOStreamer(MCContext &Context, TargetAsmBackend &TAB,
+MCStreamer *llvm::createMachOStreamer(MCContext &Context, MCAsmBackend &MAB,
raw_ostream &OS, MCCodeEmitter *CE,
bool RelaxAll) {
- MCMachOStreamer *S = new MCMachOStreamer(Context, TAB, OS, CE);
+ MCMachOStreamer *S = new MCMachOStreamer(Context, MAB, OS, CE);
if (RelaxAll)
S->getAssembler().setRelaxAll(true);
return S;
Modified: llvm/branches/exception-handling-rewrite/lib/MC/MCObjectStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/MC/MCObjectStreamer.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/MC/MCObjectStreamer.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/MC/MCObjectStreamer.cpp Mon Jul 25 20:29:47 2011
@@ -17,10 +17,10 @@
#include "llvm/MC/MCDwarf.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCSymbol.h"
-#include "llvm/MC/TargetAsmBackend.h"
+#include "llvm/MC/MCAsmBackend.h"
using namespace llvm;
-MCObjectStreamer::MCObjectStreamer(MCContext &Context, TargetAsmBackend &TAB,
+MCObjectStreamer::MCObjectStreamer(MCContext &Context, MCAsmBackend &TAB,
raw_ostream &OS, MCCodeEmitter *Emitter_)
: MCStreamer(Context),
Assembler(new MCAssembler(Context, TAB,
@@ -30,7 +30,7 @@
{
}
-MCObjectStreamer::MCObjectStreamer(MCContext &Context, TargetAsmBackend &TAB,
+MCObjectStreamer::MCObjectStreamer(MCContext &Context, MCAsmBackend &TAB,
raw_ostream &OS, MCCodeEmitter *Emitter_,
MCAssembler *_Assembler)
: MCStreamer(Context), Assembler(_Assembler), CurSectionData(0)
Modified: llvm/branches/exception-handling-rewrite/lib/MC/MCParser/AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/MC/MCParser/AsmParser.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/MC/MCParser/AsmParser.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/MC/MCParser/AsmParser.cpp Mon Jul 25 20:29:47 2011
@@ -18,6 +18,7 @@
#include "llvm/ADT/Twine.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCDwarf.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCParser/AsmCond.h"
#include "llvm/MC/MCParser/AsmLexer.h"
@@ -27,8 +28,7 @@
#include "llvm/MC/MCSectionMachO.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSymbol.h"
-#include "llvm/MC/MCDwarf.h"
-#include "llvm/MC/TargetAsmParser.h"
+#include "llvm/MC/MCTargetAsmParser.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/MemoryBuffer.h"
@@ -1117,15 +1117,8 @@
if (IDVal == ".globl" || IDVal == ".global")
return ParseDirectiveSymbolAttribute(MCSA_Global);
- // ELF only? Should it be here?
- if (IDVal == ".local")
- return ParseDirectiveSymbolAttribute(MCSA_Local);
- if (IDVal == ".hidden")
- return ParseDirectiveSymbolAttribute(MCSA_Hidden);
if (IDVal == ".indirect_symbol")
return ParseDirectiveSymbolAttribute(MCSA_IndirectSymbol);
- if (IDVal == ".internal")
- return ParseDirectiveSymbolAttribute(MCSA_Internal);
if (IDVal == ".lazy_reference")
return ParseDirectiveSymbolAttribute(MCSA_LazyReference);
if (IDVal == ".no_dead_strip")
@@ -1134,12 +1127,8 @@
return ParseDirectiveSymbolAttribute(MCSA_SymbolResolver);
if (IDVal == ".private_extern")
return ParseDirectiveSymbolAttribute(MCSA_PrivateExtern);
- if (IDVal == ".protected")
- return ParseDirectiveSymbolAttribute(MCSA_Protected);
if (IDVal == ".reference")
return ParseDirectiveSymbolAttribute(MCSA_Reference);
- if (IDVal == ".weak")
- return ParseDirectiveSymbolAttribute(MCSA_Weak);
if (IDVal == ".weak_definition")
return ParseDirectiveSymbolAttribute(MCSA_WeakDefinition);
if (IDVal == ".weak_reference")
Modified: llvm/branches/exception-handling-rewrite/lib/MC/MCParser/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/MC/MCParser/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/MC/MCParser/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/MC/MCParser/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -7,5 +7,5 @@
MCAsmLexer.cpp
MCAsmParser.cpp
MCAsmParserExtension.cpp
- TargetAsmParser.cpp
+ MCTargetAsmParser.cpp
)
Modified: llvm/branches/exception-handling-rewrite/lib/MC/MCParser/COFFAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/MC/MCParser/COFFAsmParser.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/MC/MCParser/COFFAsmParser.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/MC/MCParser/COFFAsmParser.cpp Mon Jul 25 20:29:47 2011
@@ -8,6 +8,7 @@
//===----------------------------------------------------------------------===//
#include "llvm/MC/MCParser/MCAsmParserExtension.h"
+#include "llvm/ADT/StringSwitch.h"
#include "llvm/ADT/Twine.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCContext.h"
@@ -16,7 +17,7 @@
#include "llvm/MC/MCSectionCOFF.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCExpr.h"
-#include "llvm/MC/TargetAsmParser.h"
+#include "llvm/MC/MCTargetAsmParser.h"
#include "llvm/Support/COFF.h"
using namespace llvm;
@@ -72,6 +73,7 @@
".seh_pushframe");
AddDirectiveHandler<&COFFAsmParser::ParseSEHDirectiveEndProlog>(
".seh_endprologue");
+ AddDirectiveHandler<&COFFAsmParser::ParseDirectiveSymbolAttribute>(".weak");
}
bool ParseSectionDirectiveText(StringRef, SMLoc) {
@@ -118,12 +120,44 @@
bool ParseAtUnwindOrAtExcept(bool &unwind, bool &except);
bool ParseSEHRegisterNumber(unsigned &RegNo);
+ bool ParseDirectiveSymbolAttribute(StringRef Directive, SMLoc);
public:
COFFAsmParser() {}
};
} // end annonomous namespace.
+/// ParseDirectiveSymbolAttribute
+/// ::= { ".weak", ... } [ identifier ( , identifier )* ]
+bool COFFAsmParser::ParseDirectiveSymbolAttribute(StringRef Directive, SMLoc) {
+ MCSymbolAttr Attr = StringSwitch<MCSymbolAttr>(Directive)
+ .Case(".weak", MCSA_Weak)
+ .Default(MCSA_Invalid);
+ assert(Attr != MCSA_Invalid && "unexpected symbol attribute directive!");
+ if (getLexer().isNot(AsmToken::EndOfStatement)) {
+ for (;;) {
+ StringRef Name;
+
+ if (getParser().ParseIdentifier(Name))
+ return TokError("expected identifier in directive");
+
+ MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);
+
+ getStreamer().EmitSymbolAttribute(Sym, Attr);
+
+ if (getLexer().is(AsmToken::EndOfStatement))
+ break;
+
+ if (getLexer().isNot(AsmToken::Comma))
+ return TokError("unexpected token in directive");
+ Lex();
+ }
+ }
+
+ Lex();
+ return false;
+}
+
bool COFFAsmParser::ParseSectionSwitch(StringRef Section,
unsigned Characteristics,
SectionKind Kind) {
Modified: llvm/branches/exception-handling-rewrite/lib/MC/MCParser/ELFAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/MC/MCParser/ELFAsmParser.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/MC/MCParser/ELFAsmParser.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/MC/MCParser/ELFAsmParser.cpp Mon Jul 25 20:29:47 2011
@@ -47,12 +47,17 @@
AddDirectiveHandler<&ELFAsmParser::ParseSectionDirectiveRoData>(".rodata");
AddDirectiveHandler<&ELFAsmParser::ParseSectionDirectiveTData>(".tdata");
AddDirectiveHandler<&ELFAsmParser::ParseSectionDirectiveTBSS>(".tbss");
- AddDirectiveHandler<&ELFAsmParser::ParseSectionDirectiveDataRel>(".data.rel");
- AddDirectiveHandler<&ELFAsmParser::ParseSectionDirectiveDataRelRo>(".data.rel.ro");
- AddDirectiveHandler<&ELFAsmParser::ParseSectionDirectiveDataRelRoLocal>(".data.rel.ro.local");
- AddDirectiveHandler<&ELFAsmParser::ParseSectionDirectiveEhFrame>(".eh_frame");
+ AddDirectiveHandler<
+ &ELFAsmParser::ParseSectionDirectiveDataRel>(".data.rel");
+ AddDirectiveHandler<
+ &ELFAsmParser::ParseSectionDirectiveDataRelRo>(".data.rel.ro");
+ AddDirectiveHandler<
+ &ELFAsmParser::ParseSectionDirectiveDataRelRoLocal>(".data.rel.ro.local");
+ AddDirectiveHandler<
+ &ELFAsmParser::ParseSectionDirectiveEhFrame>(".eh_frame");
AddDirectiveHandler<&ELFAsmParser::ParseDirectiveSection>(".section");
- AddDirectiveHandler<&ELFAsmParser::ParseDirectivePushSection>(".pushsection");
+ AddDirectiveHandler<
+ &ELFAsmParser::ParseDirectivePushSection>(".pushsection");
AddDirectiveHandler<&ELFAsmParser::ParseDirectivePopSection>(".popsection");
AddDirectiveHandler<&ELFAsmParser::ParseDirectiveSize>(".size");
AddDirectiveHandler<&ELFAsmParser::ParseDirectivePrevious>(".previous");
@@ -60,6 +65,14 @@
AddDirectiveHandler<&ELFAsmParser::ParseDirectiveIdent>(".ident");
AddDirectiveHandler<&ELFAsmParser::ParseDirectiveSymver>(".symver");
AddDirectiveHandler<&ELFAsmParser::ParseDirectiveWeakref>(".weakref");
+ AddDirectiveHandler<&ELFAsmParser::ParseDirectiveSymbolAttribute>(".weak");
+ AddDirectiveHandler<&ELFAsmParser::ParseDirectiveSymbolAttribute>(".local");
+ AddDirectiveHandler<
+ &ELFAsmParser::ParseDirectiveSymbolAttribute>(".protected");
+ AddDirectiveHandler<
+ &ELFAsmParser::ParseDirectiveSymbolAttribute>(".internal");
+ AddDirectiveHandler<
+ &ELFAsmParser::ParseDirectiveSymbolAttribute>(".hidden");
}
// FIXME: Part of this logic is duplicated in the MCELFStreamer. What is
@@ -129,6 +142,7 @@
bool ParseDirectiveIdent(StringRef, SMLoc);
bool ParseDirectiveSymver(StringRef, SMLoc);
bool ParseDirectiveWeakref(StringRef, SMLoc);
+ bool ParseDirectiveSymbolAttribute(StringRef, SMLoc);
private:
bool ParseSectionName(StringRef &SectionName);
@@ -136,6 +150,41 @@
}
+/// ParseDirectiveSymbolAttribute
+/// ::= { ".local", ".weak", ... } [ identifier ( , identifier )* ]
+bool ELFAsmParser::ParseDirectiveSymbolAttribute(StringRef Directive, SMLoc) {
+ MCSymbolAttr Attr = StringSwitch<MCSymbolAttr>(Directive)
+ .Case(".weak", MCSA_Weak)
+ .Case(".local", MCSA_Local)
+ .Case(".hidden", MCSA_Hidden)
+ .Case(".internal", MCSA_Internal)
+ .Case(".protected", MCSA_Protected)
+ .Default(MCSA_Invalid);
+ assert(Attr != MCSA_Invalid && "unexpected symbol attribute directive!");
+ if (getLexer().isNot(AsmToken::EndOfStatement)) {
+ for (;;) {
+ StringRef Name;
+
+ if (getParser().ParseIdentifier(Name))
+ return TokError("expected identifier in directive");
+
+ MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);
+
+ getStreamer().EmitSymbolAttribute(Sym, Attr);
+
+ if (getLexer().is(AsmToken::EndOfStatement))
+ break;
+
+ if (getLexer().isNot(AsmToken::Comma))
+ return TokError("unexpected token in directive");
+ Lex();
+ }
+ }
+
+ Lex();
+ return false;
+}
+
bool ELFAsmParser::ParseSectionSwitch(StringRef Section, unsigned Type,
unsigned Flags, SectionKind Kind) {
if (getLexer().isNot(AsmToken::EndOfStatement))
Modified: llvm/branches/exception-handling-rewrite/lib/MC/MCParser/MCAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/MC/MCParser/MCAsmParser.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/MC/MCParser/MCAsmParser.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/MC/MCParser/MCAsmParser.cpp Mon Jul 25 20:29:47 2011
@@ -10,7 +10,7 @@
#include "llvm/MC/MCParser/MCAsmParser.h"
#include "llvm/MC/MCParser/MCAsmLexer.h"
#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
-#include "llvm/MC/TargetAsmParser.h"
+#include "llvm/MC/MCTargetAsmParser.h"
#include "llvm/Support/SourceMgr.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Support/Debug.h"
@@ -23,7 +23,7 @@
MCAsmParser::~MCAsmParser() {
}
-void MCAsmParser::setTargetParser(TargetAsmParser &P) {
+void MCAsmParser::setTargetParser(MCTargetAsmParser &P) {
assert(!TargetParser && "Target parser is already initialized!");
TargetParser = &P;
TargetParser->Initialize(*this);
Removed: llvm/branches/exception-handling-rewrite/lib/MC/MCParser/TargetAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/MC/MCParser/TargetAsmParser.cpp?rev=136039&view=auto
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/MC/MCParser/TargetAsmParser.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/MC/MCParser/TargetAsmParser.cpp (removed)
@@ -1,19 +0,0 @@
-//===-- TargetAsmParser.cpp - Target Assembly Parser -----------------------==//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#include "llvm/MC/TargetAsmParser.h"
-using namespace llvm;
-
-TargetAsmParser::TargetAsmParser()
- : AvailableFeatures(0)
-{
-}
-
-TargetAsmParser::~TargetAsmParser() {
-}
Modified: llvm/branches/exception-handling-rewrite/lib/MC/MCPureStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/MC/MCPureStreamer.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/MC/MCPureStreamer.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/MC/MCPureStreamer.cpp Mon Jul 25 20:29:47 2011
@@ -28,7 +28,7 @@
virtual void EmitInstToData(const MCInst &Inst);
public:
- MCPureStreamer(MCContext &Context, TargetAsmBackend &TAB,
+ MCPureStreamer(MCContext &Context, MCAsmBackend &TAB,
raw_ostream &OS, MCCodeEmitter *Emitter)
: MCObjectStreamer(Context, TAB, OS, Emitter) {}
@@ -228,7 +228,7 @@
this->MCObjectStreamer::Finish();
}
-MCStreamer *llvm::createPureStreamer(MCContext &Context, TargetAsmBackend &TAB,
+MCStreamer *llvm::createPureStreamer(MCContext &Context, MCAsmBackend &MAB,
raw_ostream &OS, MCCodeEmitter *CE) {
- return new MCPureStreamer(Context, TAB, OS, CE);
+ return new MCPureStreamer(Context, MAB, OS, CE);
}
Modified: llvm/branches/exception-handling-rewrite/lib/MC/MachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/MC/MachObjectWriter.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/MC/MachObjectWriter.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/MC/MachObjectWriter.cpp Mon Jul 25 20:29:47 2011
@@ -12,6 +12,7 @@
#include "llvm/ADT/StringMap.h"
#include "llvm/ADT/Twine.h"
#include "llvm/MC/MCAssembler.h"
+#include "llvm/MC/MCAsmBackend.h"
#include "llvm/MC/MCAsmLayout.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCObjectWriter.h"
@@ -19,7 +20,6 @@
#include "llvm/MC/MCSymbol.h"
#include "llvm/MC/MCMachOSymbolFlags.h"
#include "llvm/MC/MCValue.h"
-#include "llvm/MC/TargetAsmBackend.h"
#include "llvm/Object/MachOFormat.h"
#include "llvm/Support/ErrorHandling.h"
Removed: llvm/branches/exception-handling-rewrite/lib/MC/TargetAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/MC/TargetAsmBackend.cpp?rev=136039&view=auto
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/MC/TargetAsmBackend.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/MC/TargetAsmBackend.cpp (removed)
@@ -1,37 +0,0 @@
-//===-- TargetAsmBackend.cpp - Target Assembly Backend ---------------------==//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#include "llvm/MC/TargetAsmBackend.h"
-using namespace llvm;
-
-TargetAsmBackend::TargetAsmBackend()
- : HasReliableSymbolDifference(false)
-{
-}
-
-TargetAsmBackend::~TargetAsmBackend() {
-}
-
-const MCFixupKindInfo &
-TargetAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
- static const MCFixupKindInfo Builtins[] = {
- { "FK_Data_1", 0, 8, 0 },
- { "FK_Data_2", 0, 16, 0 },
- { "FK_Data_4", 0, 32, 0 },
- { "FK_Data_8", 0, 64, 0 },
- { "FK_PCRel_1", 0, 8, MCFixupKindInfo::FKF_IsPCRel },
- { "FK_PCRel_2", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
- { "FK_PCRel_4", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
- { "FK_PCRel_8", 0, 64, MCFixupKindInfo::FKF_IsPCRel }
- };
-
- assert((size_t)Kind <= sizeof(Builtins) / sizeof(Builtins[0]) &&
- "Unknown fixup kind");
- return Builtins[Kind];
-}
Removed: llvm/branches/exception-handling-rewrite/lib/MC/TargetAsmLexer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/MC/TargetAsmLexer.cpp?rev=136039&view=auto
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/MC/TargetAsmLexer.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/MC/TargetAsmLexer.cpp (removed)
@@ -1,14 +0,0 @@
-//===-- llvm/MC/TargetAsmLexer.cpp - Target Assembly Lexer ----------------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#include "llvm/MC/TargetAsmLexer.h"
-using namespace llvm;
-
-TargetAsmLexer::TargetAsmLexer(const Target &T) : TheTarget(T), Lexer(NULL) {}
-TargetAsmLexer::~TargetAsmLexer() {}
Modified: llvm/branches/exception-handling-rewrite/lib/MC/WinCOFFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/MC/WinCOFFObjectWriter.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/MC/WinCOFFObjectWriter.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/MC/WinCOFFObjectWriter.cpp Mon Jul 25 20:29:47 2011
@@ -33,7 +33,7 @@
#include "llvm/Support/TimeValue.h"
-#include "../Target/X86/X86FixupKinds.h"
+#include "../Target/X86/MCTargetDesc/X86FixupKinds.h"
#include <cstdio>
Modified: llvm/branches/exception-handling-rewrite/lib/MC/WinCOFFStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/MC/WinCOFFStreamer.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/MC/WinCOFFStreamer.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/MC/WinCOFFStreamer.cpp Mon Jul 25 20:29:47 2011
@@ -24,7 +24,7 @@
#include "llvm/MC/MCCodeEmitter.h"
#include "llvm/MC/MCSectionCOFF.h"
#include "llvm/MC/MCWin64EH.h"
-#include "llvm/MC/TargetAsmBackend.h"
+#include "llvm/MC/MCAsmBackend.h"
#include "llvm/Target/TargetRegistry.h"
#include "llvm/ADT/StringMap.h"
@@ -40,7 +40,7 @@
MCSymbol const *CurSymbol;
WinCOFFStreamer(MCContext &Context,
- TargetAsmBackend &TAB,
+ MCAsmBackend &MAB,
MCCodeEmitter &CE,
raw_ostream &OS);
@@ -123,10 +123,10 @@
} // end anonymous namespace.
WinCOFFStreamer::WinCOFFStreamer(MCContext &Context,
- TargetAsmBackend &TAB,
+ MCAsmBackend &MAB,
MCCodeEmitter &CE,
raw_ostream &OS)
- : MCObjectStreamer(Context, TAB, OS, &CE)
+ : MCObjectStreamer(Context, MAB, OS, &CE)
, CurSymbol(NULL) {
}
@@ -395,11 +395,11 @@
namespace llvm
{
MCStreamer *createWinCOFFStreamer(MCContext &Context,
- TargetAsmBackend &TAB,
+ MCAsmBackend &MAB,
MCCodeEmitter &CE,
raw_ostream &OS,
bool RelaxAll) {
- WinCOFFStreamer *S = new WinCOFFStreamer(Context, TAB, CE, OS);
+ WinCOFFStreamer *S = new WinCOFFStreamer(Context, MAB, CE, OS);
S->getAssembler().setRelaxAll(RelaxAll);
return S;
}
Modified: llvm/branches/exception-handling-rewrite/lib/Support/BranchProbability.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Support/BranchProbability.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Support/BranchProbability.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Support/BranchProbability.cpp Mon Jul 25 20:29:47 2011
@@ -24,9 +24,8 @@
D = d;
}
-raw_ostream &BranchProbability::print(raw_ostream &OS) const {
+void BranchProbability::print(raw_ostream &OS) const {
OS << N << " / " << D << " = " << ((double)N / D);
- return OS;
}
void BranchProbability::dump() const {
Modified: llvm/branches/exception-handling-rewrite/lib/Support/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Support/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Support/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Support/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -9,6 +9,7 @@
APInt.cpp
APSInt.cpp
Allocator.cpp
+ BlockFrequency.cpp
BranchProbability.cpp
circular_raw_ostream.cpp
CommandLine.cpp
Modified: llvm/branches/exception-handling-rewrite/lib/Target/ARM/ARM.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/ARM/ARM.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/ARM/ARM.h (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/ARM/ARM.h Mon Jul 25 20:29:47 2011
@@ -29,13 +29,7 @@
class FunctionPass;
class JITCodeEmitter;
class MachineInstr;
-class MCCodeEmitter;
class MCInst;
-class MCInstrInfo;
-class MCObjectWriter;
-class MCSubtargetInfo;
-class TargetAsmBackend;
-class formatted_raw_ostream;
FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM,
CodeGenOpt::Level OptLevel);
Modified: llvm/branches/exception-handling-rewrite/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/ARM/ARMAsmPrinter.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/ARM/ARMAsmPrinter.cpp Mon Jul 25 20:29:47 2011
@@ -1815,20 +1815,9 @@
// Target Registry Stuff
//===----------------------------------------------------------------------===//
-static MCInstPrinter *createARMMCInstPrinter(const Target &T,
- unsigned SyntaxVariant,
- const MCAsmInfo &MAI) {
- if (SyntaxVariant == 0)
- return new ARMInstPrinter(MAI);
- return 0;
-}
-
// Force static initialization.
extern "C" void LLVMInitializeARMAsmPrinter() {
RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
-
- TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
- TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);
}
Modified: llvm/branches/exception-handling-rewrite/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/ARM/ARMInstrFormats.td?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/ARM/ARMInstrFormats.td Mon Jul 25 20:29:47 2011
@@ -131,39 +131,15 @@
// ARM special operands.
//
-def CondCodeOperand : AsmOperandClass {
- let Name = "CondCode";
- let SuperClasses = [];
-}
-
-def CCOutOperand : AsmOperandClass {
- let Name = "CCOut";
- let SuperClasses = [];
-}
-
-def MemBarrierOptOperand : AsmOperandClass {
- let Name = "MemBarrierOpt";
- let SuperClasses = [];
- let ParserMethod = "tryParseMemBarrierOptOperand";
-}
-
-def ProcIFlagsOperand : AsmOperandClass {
- let Name = "ProcIFlags";
- let SuperClasses = [];
- let ParserMethod = "tryParseProcIFlagsOperand";
-}
-
-def MSRMaskOperand : AsmOperandClass {
- let Name = "MSRMask";
- let SuperClasses = [];
- let ParserMethod = "tryParseMSRMaskOperand";
-}
-
// ARM imod and iflag operands, used only by the CPS instruction.
def imod_op : Operand<i32> {
let PrintMethod = "printCPSIMod";
}
+def ProcIFlagsOperand : AsmOperandClass {
+ let Name = "ProcIFlags";
+ let ParserMethod = "parseProcIFlagsOperand";
+}
def iflags_op : Operand<i32> {
let PrintMethod = "printCPSIFlag";
let ParserMatchClass = ProcIFlagsOperand;
@@ -171,6 +147,7 @@
// ARM Predicate operand. Default to 14 = always (AL). Second part is CC
// register whose default is 0 (no register).
+def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; }
def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
(ops (i32 14), (i32 zero_reg))> {
let PrintMethod = "printPredicateOperand";
@@ -178,6 +155,7 @@
}
// Conditional code result for instructions whose 's' bit is set, e.g. subs.
+def CCOutOperand : AsmOperandClass { let Name = "CCOut"; }
def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
let EncoderMethod = "getCCOutOpValue";
let PrintMethod = "printSBitModifierOperand";
@@ -202,6 +180,10 @@
let ParserMatchClass = SetEndAsmOperand;
}
+def MSRMaskOperand : AsmOperandClass {
+ let Name = "MSRMask";
+ let ParserMethod = "parseMSRMaskOperand";
+}
def msr_mask : Operand<i32> {
let PrintMethod = "printMSRMaskOperand";
let ParserMatchClass = MSRMaskOperand;
Modified: llvm/branches/exception-handling-rewrite/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/ARM/ARMInstrInfo.td?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/ARM/ARMInstrInfo.td Mon Jul 25 20:29:47 2011
@@ -347,33 +347,21 @@
// A list of registers separated by comma. Used by load/store multiple.
-def RegListAsmOperand : AsmOperandClass {
- let Name = "RegList";
- let SuperClasses = [];
-}
-
-def DPRRegListAsmOperand : AsmOperandClass {
- let Name = "DPRRegList";
- let SuperClasses = [];
-}
-
-def SPRRegListAsmOperand : AsmOperandClass {
- let Name = "SPRRegList";
- let SuperClasses = [];
-}
-
+def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
def reglist : Operand<i32> {
let EncoderMethod = "getRegisterListOpValue";
let ParserMatchClass = RegListAsmOperand;
let PrintMethod = "printRegisterList";
}
+def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
def dpr_reglist : Operand<i32> {
let EncoderMethod = "getRegisterListOpValue";
let ParserMatchClass = DPRRegListAsmOperand;
let PrintMethod = "printRegisterList";
}
+def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
def spr_reglist : Operand<i32> {
let EncoderMethod = "getRegisterListOpValue";
let ParserMatchClass = SPRRegListAsmOperand;
@@ -406,44 +394,40 @@
let EncoderMethod = "getRotImmOpValue";
}
-def ShifterAsmOperand : AsmOperandClass {
- let Name = "Shifter";
- let SuperClasses = [];
-}
-
// shift_imm: An integer that encodes a shift amount and the type of shift
-// (currently either asr or lsl) using the same encoding used for the
-// immediates in so_reg operands.
+// (asr or lsl). The 6-bit immediate encodes as:
+// {5} 0 ==> lsl
+// 1 asr
+// {4-0} imm5 shift amount.
+// asr #32 encoded as imm5 == 0.
+def ShifterImmAsmOperand : AsmOperandClass {
+ let Name = "ShifterImm";
+ let ParserMethod = "parseShifterImm";
+}
def shift_imm : Operand<i32> {
let PrintMethod = "printShiftImmOperand";
- let ParserMatchClass = ShifterAsmOperand;
-}
-
-def ShiftedRegAsmOperand : AsmOperandClass {
- let Name = "ShiftedReg";
-}
-
-def ShiftedImmAsmOperand : AsmOperandClass {
- let Name = "ShiftedImm";
+ let ParserMatchClass = ShifterImmAsmOperand;
}
// shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
+def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
def so_reg_reg : Operand<i32>, // reg reg imm
ComplexPattern<i32, 3, "SelectRegShifterOperand",
[shl, srl, sra, rotr]> {
let EncoderMethod = "getSORegRegOpValue";
let PrintMethod = "printSORegRegOperand";
let ParserMatchClass = ShiftedRegAsmOperand;
- let MIOperandInfo = (ops GPR, GPR, shift_imm);
+ let MIOperandInfo = (ops GPR, GPR, i32imm);
}
+def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
def so_reg_imm : Operand<i32>, // reg imm
ComplexPattern<i32, 2, "SelectImmShifterOperand",
[shl, srl, sra, rotr]> {
let EncoderMethod = "getSORegImmOpValue";
let PrintMethod = "printSORegImmOperand";
let ParserMatchClass = ShiftedImmAsmOperand;
- let MIOperandInfo = (ops GPR, shift_imm);
+ let MIOperandInfo = (ops GPR, i32imm);
}
// FIXME: Does this need to be distinct from so_reg?
@@ -452,7 +436,7 @@
[shl,srl,sra,rotr]> {
let EncoderMethod = "getSORegRegOpValue";
let PrintMethod = "printSORegRegOperand";
- let MIOperandInfo = (ops GPR, GPR, shift_imm);
+ let MIOperandInfo = (ops GPR, GPR, i32imm);
}
// FIXME: Does this need to be distinct from so_reg?
@@ -461,7 +445,7 @@
[shl,srl,sra,rotr]> {
let EncoderMethod = "getSORegImmOpValue";
let PrintMethod = "printSORegImmOperand";
- let MIOperandInfo = (ops GPR, shift_imm);
+ let MIOperandInfo = (ops GPR, i32imm);
}
@@ -559,24 +543,21 @@
def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
def imm1_32 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 32; }],
imm1_32_XFORM> {
- let PrintMethod = "printImm1_32Operand";
+ let PrintMethod = "printImmPlusOneOperand";
let ParserMatchClass = Imm1_32AsmOperand;
}
-// Define ARM specific addressing modes.
-
-def MemMode2AsmOperand : AsmOperandClass {
- let Name = "MemMode2";
- let SuperClasses = [];
- let ParserMethod = "tryParseMemMode2Operand";
-}
-
-def MemMode3AsmOperand : AsmOperandClass {
- let Name = "MemMode3";
- let SuperClasses = [];
- let ParserMethod = "tryParseMemMode3Operand";
+def imm1_16_XFORM: SDNodeXForm<imm, [{
+ return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
+}]>;
+def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
+def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
+ imm1_16_XFORM> {
+ let PrintMethod = "printImmPlusOneOperand";
+ let ParserMatchClass = Imm1_16AsmOperand;
}
+// Define ARM specific addressing modes.
// addrmode_imm12 := reg +/- imm12
//
def addrmode_imm12 : Operand<i32>,
@@ -602,6 +583,10 @@
// addrmode2 := reg +/- imm12
// := reg +/- reg shop imm
//
+def MemMode2AsmOperand : AsmOperandClass {
+ let Name = "MemMode2";
+ let ParserMethod = "parseMemMode2Operand";
+}
def addrmode2 : Operand<i32>,
ComplexPattern<i32, 3, "SelectAddrMode2", []> {
let EncoderMethod = "getAddrMode2OpValue";
@@ -621,6 +606,10 @@
// addrmode3 := reg +/- reg
// addrmode3 := reg +/- imm8
//
+def MemMode3AsmOperand : AsmOperandClass {
+ let Name = "MemMode3";
+ let ParserMethod = "parseMemMode3Operand";
+}
def addrmode3 : Operand<i32>,
ComplexPattern<i32, 3, "SelectAddrMode3", []> {
let EncoderMethod = "getAddrMode3OpValue";
@@ -644,13 +633,9 @@
let PrintMethod = "printLdStmModeOperand";
}
-def MemMode5AsmOperand : AsmOperandClass {
- let Name = "MemMode5";
- let SuperClasses = [];
-}
-
// addrmode5 := reg +/- imm8*4
//
+def MemMode5AsmOperand : AsmOperandClass { let Name = "MemMode5"; }
def addrmode5 : Operand<i32>,
ComplexPattern<i32, 2, "SelectAddrMode5", []> {
let PrintMethod = "printAddrMode5Operand";
@@ -702,15 +687,11 @@
let MIOperandInfo = (ops GPR, i32imm);
}
-def MemMode7AsmOperand : AsmOperandClass {
- let Name = "MemMode7";
- let SuperClasses = [];
-}
-
// addrmode7 := reg
// Used by load/store exclusive instructions. Useful to enable right assembly
// parsing and printing. Not used for any codegen matching.
//
+def MemMode7AsmOperand : AsmOperandClass { let Name = "MemMode7"; }
def addrmode7 : Operand<i32> {
let PrintMethod = "printAddrMode7Operand";
let MIOperandInfo = (ops GPR);
@@ -723,21 +704,17 @@
def CoprocNumAsmOperand : AsmOperandClass {
let Name = "CoprocNum";
- let SuperClasses = [];
- let ParserMethod = "tryParseCoprocNumOperand";
+ let ParserMethod = "parseCoprocNumOperand";
}
-
-def CoprocRegAsmOperand : AsmOperandClass {
- let Name = "CoprocReg";
- let SuperClasses = [];
- let ParserMethod = "tryParseCoprocRegOperand";
-}
-
def p_imm : Operand<i32> {
let PrintMethod = "printPImmediate";
let ParserMatchClass = CoprocNumAsmOperand;
}
+def CoprocRegAsmOperand : AsmOperandClass {
+ let Name = "CoprocReg";
+ let ParserMethod = "parseCoprocRegOperand";
+}
def c_imm : Operand<i32> {
let PrintMethod = "printCImmediate";
let ParserMatchClass = CoprocRegAsmOperand;
@@ -2727,8 +2704,8 @@
// Signed/Unsigned saturate -- for disassembly only
-def SSAT : AI<(outs GPR:$Rd), (ins imm1_32:$sat_imm, GPR:$a, shift_imm:$sh),
- SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh", []> {
+def SSAT : AI<(outs GPR:$Rd), (ins imm1_32:$sat_imm, GPR:$Rn, shift_imm:$sh),
+ SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
bits<4> Rd;
bits<5> sat_imm;
bits<4> Rn;
@@ -2737,12 +2714,12 @@
let Inst{5-4} = 0b01;
let Inst{20-16} = sat_imm;
let Inst{15-12} = Rd;
- let Inst{11-7} = sh{7-3};
- let Inst{6} = sh{0};
+ let Inst{11-7} = sh{4-0};
+ let Inst{6} = sh{5};
let Inst{3-0} = Rn;
}
-def SSAT16 : AI<(outs GPR:$Rd), (ins imm1_32:$sat_imm, GPR:$Rn), SatFrm,
+def SSAT16 : AI<(outs GPR:$Rd), (ins imm1_16:$sat_imm, GPR:$Rn), SatFrm,
NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
bits<4> Rd;
bits<4> sat_imm;
@@ -2754,9 +2731,8 @@
let Inst{3-0} = Rn;
}
-def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
- SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
- [/* For disassembly only; pattern left blank */]> {
+def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn, shift_imm:$sh),
+ SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
bits<4> Rd;
bits<5> sat_imm;
bits<4> Rn;
@@ -2764,8 +2740,8 @@
let Inst{27-21} = 0b0110111;
let Inst{5-4} = 0b01;
let Inst{15-12} = Rd;
- let Inst{11-7} = sh{7-3};
- let Inst{6} = sh{0};
+ let Inst{11-7} = sh{4-0};
+ let Inst{6} = sh{5};
let Inst{20-16} = sat_imm;
let Inst{3-0} = Rn;
}
@@ -3488,6 +3464,10 @@
// Atomic operations intrinsics
//
+def MemBarrierOptOperand : AsmOperandClass {
+ let Name = "MemBarrierOpt";
+ let ParserMethod = "parseMemBarrierOptOperand";
+}
def memb_opt : Operand<i32> {
let PrintMethod = "printMemBOption";
let ParserMatchClass = MemBarrierOptOperand;
@@ -4313,3 +4293,7 @@
def : InstAlias<"rsc${s}${p} $Rdn, $shift",
(RSCrsr GPR:$Rdn, GPR:$Rdn, so_reg_reg:$shift, pred:$p,
cc_out:$s)>, Requires<[IsARM]>;
+
+// SSAT optional shift operand.
+def : InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
+ (SSAT GPR:$Rd, imm1_32:$sat_imm, GPR:$Rn, 0, pred:$p)>;
Modified: llvm/branches/exception-handling-rewrite/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/ARM/ARMInstrThumb2.td?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/ARM/ARMInstrThumb2.td Mon Jul 25 20:29:47 2011
@@ -1918,8 +1918,8 @@
let Inst{11-8} = Rd;
let Inst{19-16} = Rn;
- let Inst{4-0} = sat_imm{4-0};
- let Inst{21} = sh{6};
+ let Inst{4-0} = sat_imm;
+ let Inst{21} = sh{5};
let Inst{14-12} = sh{4-2};
let Inst{7-6} = sh{1-0};
}
@@ -1935,7 +1935,7 @@
}
def t2SSAT16: T2SatI<
- (outs rGPR:$Rd), (ins imm1_32:$sat_imm, rGPR:$Rn), NoItinerary,
+ (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary,
"ssat16", "\t$Rd, $sat_imm, $Rn",
[/* For disassembly only; pattern left blank */]>,
Requires<[IsThumb2, HasThumb2DSP]> {
Modified: llvm/branches/exception-handling-rewrite/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp Mon Jul 25 20:29:47 2011
@@ -7,15 +7,14 @@
//
//===----------------------------------------------------------------------===//
-#include "ARM.h"
-#include "ARMTargetMachine.h"
+#include "MCTargetDesc/ARMBaseInfo.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCParser/MCAsmLexer.h"
#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
-#include "llvm/MC/TargetAsmLexer.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/MC/MCTargetAsmLexer.h"
-#include "llvm/Target/TargetMachine.h" // FIXME
#include "llvm/Target/TargetRegistry.h"
#include "llvm/ADT/OwningPtr.h"
@@ -30,7 +29,7 @@
namespace {
-class ARMBaseAsmLexer : public TargetAsmLexer {
+class ARMBaseAsmLexer : public MCTargetAsmLexer {
const MCAsmInfo &AsmInfo;
const AsmToken &lexDefinite() {
@@ -43,7 +42,7 @@
rmap_ty RegisterMap;
- void InitRegisterMap(const TargetRegisterInfo *info) {
+ void InitRegisterMap(const MCRegisterInfo *info) {
unsigned numRegs = info->getNumRegs();
for (unsigned i = 0; i < numRegs; ++i) {
@@ -77,33 +76,23 @@
}
public:
ARMBaseAsmLexer(const Target &T, const MCAsmInfo &MAI)
- : TargetAsmLexer(T), AsmInfo(MAI) {
+ : MCTargetAsmLexer(T), AsmInfo(MAI) {
}
};
class ARMAsmLexer : public ARMBaseAsmLexer {
public:
- ARMAsmLexer(const Target &T, const MCAsmInfo &MAI)
+ ARMAsmLexer(const Target &T, const MCRegisterInfo &MRI, const MCAsmInfo &MAI)
: ARMBaseAsmLexer(T, MAI) {
- std::string tripleString("arm-unknown-unknown");
- std::string featureString;
- std::string CPU;
- OwningPtr<const TargetMachine>
- targetMachine(T.createTargetMachine(tripleString, CPU, featureString));
- InitRegisterMap(targetMachine->getRegisterInfo());
+ InitRegisterMap(&MRI);
}
};
class ThumbAsmLexer : public ARMBaseAsmLexer {
public:
- ThumbAsmLexer(const Target &T, const MCAsmInfo &MAI)
+ ThumbAsmLexer(const Target &T, const MCRegisterInfo &MRI,const MCAsmInfo &MAI)
: ARMBaseAsmLexer(T, MAI) {
- std::string tripleString("thumb-unknown-unknown");
- std::string featureString;
- std::string CPU;
- OwningPtr<const TargetMachine>
- targetMachine(T.createTargetMachine(tripleString, CPU, featureString));
- InitRegisterMap(targetMachine->getRegisterInfo());
+ InitRegisterMap(&MRI);
}
};
@@ -149,6 +138,6 @@
}
extern "C" void LLVMInitializeARMAsmLexer() {
- RegisterAsmLexer<ARMAsmLexer> X(TheARMTarget);
- RegisterAsmLexer<ThumbAsmLexer> Y(TheThumbTarget);
+ RegisterMCAsmLexer<ARMAsmLexer> X(TheARMTarget);
+ RegisterMCAsmLexer<ThumbAsmLexer> Y(TheThumbTarget);
}
Modified: llvm/branches/exception-handling-rewrite/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Jul 25 20:29:47 2011
@@ -7,9 +7,7 @@
//
//===----------------------------------------------------------------------===//
-#include "ARM.h"
-#include "ARMBaseRegisterInfo.h"
-#include "ARMSubtarget.h"
+#include "MCTargetDesc/ARMBaseInfo.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "MCTargetDesc/ARMMCExpr.h"
#include "llvm/MC/MCParser/MCAsmLexer.h"
@@ -20,12 +18,14 @@
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/MC/TargetAsmParser.h"
+#include "llvm/MC/MCTargetAsmParser.h"
#include "llvm/Target/TargetRegistry.h"
#include "llvm/Support/SourceMgr.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/ADT/OwningPtr.h"
+#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/StringSwitch.h"
@@ -37,7 +37,7 @@
class ARMOperand;
-class ARMAsmParser : public TargetAsmParser {
+class ARMAsmParser : public MCTargetAsmParser {
MCSubtargetInfo &STI;
MCAsmParser &Parser;
@@ -104,19 +104,19 @@
/// }
- OperandMatchResultTy tryParseCoprocNumOperand(
+ OperandMatchResultTy parseCoprocNumOperand(
SmallVectorImpl<MCParsedAsmOperand*>&);
- OperandMatchResultTy tryParseCoprocRegOperand(
+ OperandMatchResultTy parseCoprocRegOperand(
SmallVectorImpl<MCParsedAsmOperand*>&);
- OperandMatchResultTy tryParseMemBarrierOptOperand(
+ OperandMatchResultTy parseMemBarrierOptOperand(
SmallVectorImpl<MCParsedAsmOperand*>&);
- OperandMatchResultTy tryParseProcIFlagsOperand(
+ OperandMatchResultTy parseProcIFlagsOperand(
SmallVectorImpl<MCParsedAsmOperand*>&);
- OperandMatchResultTy tryParseMSRMaskOperand(
+ OperandMatchResultTy parseMSRMaskOperand(
SmallVectorImpl<MCParsedAsmOperand*>&);
- OperandMatchResultTy tryParseMemMode2Operand(
+ OperandMatchResultTy parseMemMode2Operand(
SmallVectorImpl<MCParsedAsmOperand*>&);
- OperandMatchResultTy tryParseMemMode3Operand(
+ OperandMatchResultTy parseMemMode3Operand(
SmallVectorImpl<MCParsedAsmOperand*>&);
OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
StringRef Op, int Low, int High);
@@ -127,6 +127,7 @@
return parsePKHImm(O, "asr", 1, 32);
}
OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
+ OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
// Asm Match Converter Methods
bool CvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
@@ -140,7 +141,7 @@
public:
ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
- : TargetAsmParser(), STI(_STI), Parser(_Parser) {
+ : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
MCAsmParserExtension::Initialize(_Parser);
// Initialize the set of available features.
@@ -153,6 +154,11 @@
};
} // end anonymous namespace
+namespace llvm {
+ // FIXME: TableGen this?
+ extern MCRegisterClass ARMMCRegisterClasses[]; // In ARMGenRegisterInfo.inc.
+}
+
namespace {
/// ARMOperand - Instances of this class represent a parsed ARM machine
@@ -174,7 +180,7 @@
SPRRegisterList,
ShiftedRegister,
ShiftedImmediate,
- Shifter,
+ ShifterImmediate,
Token
} Kind;
@@ -234,20 +240,20 @@
} Mem;
struct {
- ARM_AM::ShiftOpc ShiftTy;
+ bool isASR;
unsigned Imm;
- } Shift;
+ } ShifterImm;
struct {
ARM_AM::ShiftOpc ShiftTy;
unsigned SrcReg;
unsigned ShiftReg;
unsigned ShiftImm;
- } ShiftedReg;
+ } RegShiftedReg;
struct {
ARM_AM::ShiftOpc ShiftTy;
unsigned SrcReg;
unsigned ShiftImm;
- } ShiftedImm;
+ } RegShiftedImm;
};
ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
@@ -291,14 +297,14 @@
case ProcIFlags:
IFlags = o.IFlags;
break;
- case Shifter:
- Shift = o.Shift;
+ case ShifterImmediate:
+ ShifterImm = o.ShifterImm;
break;
case ShiftedRegister:
- ShiftedReg = o.ShiftedReg;
+ RegShiftedReg = o.RegShiftedReg;
break;
case ShiftedImmediate:
- ShiftedImm = o.ShiftedImm;
+ RegShiftedImm = o.RegShiftedImm;
break;
}
}
@@ -427,6 +433,14 @@
int64_t Value = CE->getValue();
return Value >= 0 && Value < 32;
}
+ bool isImm1_16() const {
+ if (Kind != Immediate)
+ return false;
+ const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+ if (!CE) return false;
+ int64_t Value = CE->getValue();
+ return Value > 0 && Value < 17;
+ }
bool isImm1_32() const {
if (Kind != Immediate)
return false;
@@ -500,9 +514,9 @@
bool isToken() const { return Kind == Token; }
bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
bool isMemory() const { return Kind == Memory; }
- bool isShifter() const { return Kind == Shifter; }
- bool isShiftedReg() const { return Kind == ShiftedRegister; }
- bool isShiftedImm() const { return Kind == ShiftedImmediate; }
+ bool isShifterImm() const { return Kind == ShifterImmediate; }
+ bool isRegShiftedReg() const { return Kind == ShiftedRegister; }
+ bool isRegShiftedImm() const { return Kind == ShiftedImmediate; }
bool isMemMode2() const {
if (getMemAddrMode() != ARMII::AddrMode2)
return false;
@@ -633,28 +647,28 @@
Inst.addOperand(MCOperand::CreateReg(getReg()));
}
- void addShiftedRegOperands(MCInst &Inst, unsigned N) const {
+ void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 3 && "Invalid number of operands!");
- assert(isShiftedReg() && "addShiftedRegOperands() on non ShiftedReg!");
- Inst.addOperand(MCOperand::CreateReg(ShiftedReg.SrcReg));
- Inst.addOperand(MCOperand::CreateReg(ShiftedReg.ShiftReg));
+ assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
+ Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
+ Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
Inst.addOperand(MCOperand::CreateImm(
- ARM_AM::getSORegOpc(ShiftedReg.ShiftTy, ShiftedReg.ShiftImm)));
+ ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
}
- void addShiftedImmOperands(MCInst &Inst, unsigned N) const {
+ void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
- assert(isShiftedImm() && "addShiftedImmOperands() on non ShiftedImm!");
- Inst.addOperand(MCOperand::CreateReg(ShiftedImm.SrcReg));
+ assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
+ Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
Inst.addOperand(MCOperand::CreateImm(
- ARM_AM::getSORegOpc(ShiftedImm.ShiftTy, ShiftedImm.ShiftImm)));
+ ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
}
- void addShifterOperands(MCInst &Inst, unsigned N) const {
+ void addShifterImmOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateImm(
- ARM_AM::getSORegOpc(Shift.ShiftTy, 0)));
+ Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
+ ShifterImm.Imm));
}
void addRegListOperands(MCInst &Inst, unsigned N) const {
@@ -698,6 +712,14 @@
addExpr(Inst, getImm());
}
+ void addImm1_16Operands(MCInst &Inst, unsigned N) const {
+ assert(N == 1 && "Invalid number of operands!");
+ // The constant encodes as the immediate-1, and we store in the instruction
+ // the bits as encoded, so subtract off one here.
+ const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+ Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
+ }
+
void addImm1_32Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
// The constant encodes as the immediate-1, and we store in the instruction
@@ -935,10 +957,10 @@
unsigned ShiftImm,
SMLoc S, SMLoc E) {
ARMOperand *Op = new ARMOperand(ShiftedRegister);
- Op->ShiftedReg.ShiftTy = ShTy;
- Op->ShiftedReg.SrcReg = SrcReg;
- Op->ShiftedReg.ShiftReg = ShiftReg;
- Op->ShiftedReg.ShiftImm = ShiftImm;
+ Op->RegShiftedReg.ShiftTy = ShTy;
+ Op->RegShiftedReg.SrcReg = SrcReg;
+ Op->RegShiftedReg.ShiftReg = ShiftReg;
+ Op->RegShiftedReg.ShiftImm = ShiftImm;
Op->StartLoc = S;
Op->EndLoc = E;
return Op;
@@ -949,18 +971,19 @@
unsigned ShiftImm,
SMLoc S, SMLoc E) {
ARMOperand *Op = new ARMOperand(ShiftedImmediate);
- Op->ShiftedImm.ShiftTy = ShTy;
- Op->ShiftedImm.SrcReg = SrcReg;
- Op->ShiftedImm.ShiftImm = ShiftImm;
+ Op->RegShiftedImm.ShiftTy = ShTy;
+ Op->RegShiftedImm.SrcReg = SrcReg;
+ Op->RegShiftedImm.ShiftImm = ShiftImm;
Op->StartLoc = S;
Op->EndLoc = E;
return Op;
}
- static ARMOperand *CreateShifter(ARM_AM::ShiftOpc ShTy,
+ static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
SMLoc S, SMLoc E) {
- ARMOperand *Op = new ARMOperand(Shifter);
- Op->Shift.ShiftTy = ShTy;
+ ARMOperand *Op = new ARMOperand(ShifterImmediate);
+ Op->ShifterImm.isASR = isASR;
+ Op->ShifterImm.Imm = Imm;
Op->StartLoc = S;
Op->EndLoc = E;
return Op;
@@ -971,9 +994,11 @@
SMLoc StartLoc, SMLoc EndLoc) {
KindTy Kind = RegisterList;
- if (ARM::DPRRegClass.contains(Regs.front().first))
+ if (llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].
+ contains(Regs.front().first))
Kind = DPRRegisterList;
- else if (ARM::SPRRegClass.contains(Regs.front().first))
+ else if (llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].
+ contains(Regs.front().first))
Kind = SPRRegisterList;
ARMOperand *Op = new ARMOperand(Kind);
@@ -1120,22 +1145,23 @@
case Register:
OS << "<register " << getReg() << ">";
break;
- case Shifter:
- OS << "<shifter " << ARM_AM::getShiftOpcStr(Shift.ShiftTy) << ">";
+ case ShifterImmediate:
+ OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
+ << " #" << ShifterImm.Imm << ">";
break;
case ShiftedRegister:
OS << "<so_reg_reg "
- << ShiftedReg.SrcReg
- << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(ShiftedReg.ShiftImm))
- << ", " << ShiftedReg.ShiftReg << ", "
- << ARM_AM::getSORegOffset(ShiftedReg.ShiftImm)
+ << RegShiftedReg.SrcReg
+ << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
+ << ", " << RegShiftedReg.ShiftReg << ", "
+ << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
<< ">";
break;
case ShiftedImmediate:
OS << "<so_reg_imm "
- << ShiftedImm.SrcReg
- << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(ShiftedImm.ShiftImm))
- << ", " << ARM_AM::getSORegOffset(ShiftedImm.ShiftImm)
+ << RegShiftedImm.SrcReg
+ << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
+ << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
<< ">";
break;
case RegisterList:
@@ -1282,7 +1308,7 @@
if (ShiftReg && ShiftTy != ARM_AM::rrx)
Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
- ShiftReg, Imm,
+ ShiftReg, Imm,
S, Parser.getTok().getLoc()));
else
Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
@@ -1360,11 +1386,11 @@
return -1;
}
-/// tryParseCoprocNumOperand - Try to parse an coprocessor number operand. The
+/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
/// token must be an Identifier when called, and if it is a coprocessor
/// number, the token is eaten and the operand is added to the operand list.
ARMAsmParser::OperandMatchResultTy ARMAsmParser::
-tryParseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
+parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
SMLoc S = Parser.getTok().getLoc();
const AsmToken &Tok = Parser.getTok();
assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
@@ -1378,11 +1404,11 @@
return MatchOperand_Success;
}
-/// tryParseCoprocRegOperand - Try to parse an coprocessor register operand. The
+/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
/// token must be an Identifier when called, and if it is a coprocessor
/// number, the token is eaten and the operand is added to the operand list.
ARMAsmParser::OperandMatchResultTy ARMAsmParser::
-tryParseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
+parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
SMLoc S = Parser.getTok().getLoc();
const AsmToken &Tok = Parser.getTok();
assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
@@ -1480,9 +1506,9 @@
return false;
}
-/// tryParseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
+/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
ARMAsmParser::OperandMatchResultTy ARMAsmParser::
-tryParseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
+parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
SMLoc S = Parser.getTok().getLoc();
const AsmToken &Tok = Parser.getTok();
assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
@@ -1511,9 +1537,9 @@
return MatchOperand_Success;
}
-/// tryParseProcIFlagsOperand - Try to parse iflags from CPS instruction.
+/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
ARMAsmParser::OperandMatchResultTy ARMAsmParser::
-tryParseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
+parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
SMLoc S = Parser.getTok().getLoc();
const AsmToken &Tok = Parser.getTok();
assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
@@ -1540,9 +1566,9 @@
return MatchOperand_Success;
}
-/// tryParseMSRMaskOperand - Try to parse mask flags from MSR instruction.
+/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
ARMAsmParser::OperandMatchResultTy ARMAsmParser::
-tryParseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
+parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
SMLoc S = Parser.getTok().getLoc();
const AsmToken &Tok = Parser.getTok();
assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
@@ -1606,9 +1632,9 @@
return MatchOperand_Success;
}
-/// tryParseMemMode2Operand - Try to parse memory addressing mode 2 operand.
+/// parseMemMode2Operand - Try to parse memory addressing mode 2 operand.
ARMAsmParser::OperandMatchResultTy ARMAsmParser::
-tryParseMemMode2Operand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
+parseMemMode2Operand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
assert(Parser.getTok().is(AsmToken::LBrac) && "Token is not a \"[\"");
if (ParseMemory(Operands, ARMII::AddrMode2))
@@ -1617,9 +1643,9 @@
return MatchOperand_Success;
}
-/// tryParseMemMode3Operand - Try to parse memory addressing mode 3 operand.
+/// parseMemMode3Operand - Try to parse memory addressing mode 3 operand.
ARMAsmParser::OperandMatchResultTy ARMAsmParser::
-tryParseMemMode3Operand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
+parseMemMode3Operand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
assert(Parser.getTok().is(AsmToken::LBrac) && "Token is not a \"[\"");
if (ParseMemory(Operands, ARMII::AddrMode3))
@@ -1698,6 +1724,73 @@
return MatchOperand_Success;
}
+/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
+/// instructions. Legal values are:
+/// lsl #n 'n' in [0,31]
+/// asr #n 'n' in [1,32]
+/// n == 32 encoded as n == 0.
+ARMAsmParser::OperandMatchResultTy ARMAsmParser::
+parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
+ const AsmToken &Tok = Parser.getTok();
+ SMLoc S = Tok.getLoc();
+ if (Tok.isNot(AsmToken::Identifier)) {
+ Error(S, "shift operator 'asr' or 'lsl' expected");
+ return MatchOperand_ParseFail;
+ }
+ StringRef ShiftName = Tok.getString();
+ bool isASR;
+ if (ShiftName == "lsl" || ShiftName == "LSL")
+ isASR = false;
+ else if (ShiftName == "asr" || ShiftName == "ASR")
+ isASR = true;
+ else {
+ Error(S, "shift operator 'asr' or 'lsl' expected");
+ return MatchOperand_ParseFail;
+ }
+ Parser.Lex(); // Eat the operator.
+
+ // A '#' and a shift amount.
+ if (Parser.getTok().isNot(AsmToken::Hash)) {
+ Error(Parser.getTok().getLoc(), "'#' expected");
+ return MatchOperand_ParseFail;
+ }
+ Parser.Lex(); // Eat hash token.
+
+ const MCExpr *ShiftAmount;
+ SMLoc E = Parser.getTok().getLoc();
+ if (getParser().ParseExpression(ShiftAmount)) {
+ Error(E, "malformed shift expression");
+ return MatchOperand_ParseFail;
+ }
+ const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
+ if (!CE) {
+ Error(E, "shift amount must be an immediate");
+ return MatchOperand_ParseFail;
+ }
+
+ int64_t Val = CE->getValue();
+ if (isASR) {
+ // Shift amount must be in [1,32]
+ if (Val < 1 || Val > 32) {
+ Error(E, "'asr' shift amount must be in range [1,32]");
+ return MatchOperand_ParseFail;
+ }
+ // asr #32 encoded as asr #0.
+ if (Val == 32) Val = 0;
+ } else {
+ // Shift amount must be in [1,32]
+ if (Val < 0 || Val > 31) {
+ Error(E, "'lsr' shift amount must be in range [0,31]");
+ return MatchOperand_ParseFail;
+ }
+ }
+
+ E = Parser.getTok().getLoc();
+ Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
+
+ return MatchOperand_Success;
+}
+
/// CvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
/// when they refer multiple MIOperands inside a single one.
@@ -2572,8 +2665,8 @@
/// Force static initialization.
extern "C" void LLVMInitializeARMAsmParser() {
- RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
- RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
+ RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
+ RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
LLVMInitializeARMAsmLexer();
}
Modified: llvm/branches/exception-handling-rewrite/lib/Target/ARM/AsmParser/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/ARM/AsmParser/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/ARM/AsmParser/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/ARM/AsmParser/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -4,4 +4,4 @@
ARMAsmLexer.cpp
ARMAsmParser.cpp
)
-
+add_dependencies(LLVMARMAsmParser ARMCommonTableGen)
Modified: llvm/branches/exception-handling-rewrite/lib/Target/ARM/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/ARM/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/ARM/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/ARM/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -13,6 +13,7 @@
tablegen(ARMGenSubtargetInfo.inc -gen-subtarget)
tablegen(ARMGenEDInfo.inc -gen-enhanced-disassembly-info)
tablegen(ARMGenDecoderTables.inc -gen-arm-decoder)
+add_public_tablegen_target(ARMCommonTableGen)
add_llvm_target(ARMCodeGen
ARMAsmPrinter.cpp
Modified: llvm/branches/exception-handling-rewrite/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Mon Jul 25 20:29:47 2011
@@ -1732,17 +1732,11 @@
decodeRm(insn))));
if (NumOpsAdded == 4) {
- ARM_AM::ShiftOpc Opc = (slice(insn, 6, 6) != 0 ? ARM_AM::asr : ARM_AM::lsl);
+ // Inst{6} encodes the shift type.
+ bool isASR = slice(insn, 6, 6);
// Inst{11-7} encodes the imm5 shift amount.
unsigned ShAmt = slice(insn, 11, 7);
- if (ShAmt == 0) {
- // A8.6.183. Possible ASR shift amount of 32...
- if (Opc == ARM_AM::asr)
- ShAmt = 32;
- else
- Opc = ARM_AM::no_shift;
- }
- MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(Opc, ShAmt)));
+ MI.addOperand(MCOperand::CreateImm(isASR << 5 | ShAmt));
}
return true;
}
Modified: llvm/branches/exception-handling-rewrite/lib/Target/ARM/Disassembler/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/ARM/Disassembler/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/ARM/Disassembler/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/ARM/Disassembler/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -11,4 +11,4 @@
PROPERTY COMPILE_FLAGS "/Od"
)
endif()
-add_dependencies(LLVMARMDisassembler ARMCodeGenTable_gen)
+add_dependencies(LLVMARMDisassembler ARMCommonTableGen)
Modified: llvm/branches/exception-handling-rewrite/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h Mon Jul 25 20:29:47 2011
@@ -1615,17 +1615,11 @@
decodeRn(insn))));
if (NumOpsAdded == 4) {
- ARM_AM::ShiftOpc Opc = (slice(insn, 21, 21) != 0 ?
- ARM_AM::asr : ARM_AM::lsl);
- // Inst{14-12:7-6} encodes the imm5 shift amount.
- unsigned ShAmt = slice(insn, 14, 12) << 2 | slice(insn, 7, 6);
- if (ShAmt == 0) {
- if (Opc == ARM_AM::asr)
- ShAmt = 32;
- else
- Opc = ARM_AM::no_shift;
- }
- MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(Opc, ShAmt)));
+ // Inst{6} encodes the shift type.
+ bool isASR = slice(insn, 6, 6);
+ // Inst{11-7} encodes the imm5 shift amount.
+ unsigned ShAmt = slice(insn, 11, 7);
+ MI.addOperand(MCOperand::CreateImm(isASR << 5 | ShAmt));
}
return true;
}
Modified: llvm/branches/exception-handling-rewrite/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Mon Jul 25 20:29:47 2011
@@ -450,20 +450,12 @@
void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
unsigned ShiftOp = MI->getOperand(OpNum).getImm();
- ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
- switch (Opc) {
- case ARM_AM::no_shift:
- return;
- case ARM_AM::lsl:
- O << ", lsl #";
- break;
- case ARM_AM::asr:
- O << ", asr #";
- break;
- default:
- assert(0 && "unexpected shift opcode for shift immediate operand");
- }
- O << ARM_AM::getSORegOffset(ShiftOp);
+ bool isASR = (ShiftOp & (1 << 5)) != 0;
+ unsigned Amt = ShiftOp & 0x1f;
+ if (isASR)
+ O << ", asr #" << (Amt == 0 ? 32 : Amt);
+ else if (Amt)
+ O << ", lsl #" << Amt;
}
void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
@@ -838,8 +830,8 @@
O << "#0x" << utohexstr(Val);
}
-void ARMInstPrinter::printImm1_32Operand(const MCInst *MI, unsigned OpNum,
- raw_ostream &O) {
+void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
+ raw_ostream &O) {
unsigned Imm = MI->getOperand(OpNum).getImm();
O << "#" << Imm + 1;
}
Modified: llvm/branches/exception-handling-rewrite/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/ARM/InstPrinter/ARMInstPrinter.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/ARM/InstPrinter/ARMInstPrinter.h (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/ARM/InstPrinter/ARMInstPrinter.h Mon Jul 25 20:29:47 2011
@@ -114,7 +114,7 @@
void printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printNEONModImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
- void printImm1_32Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
+ void printImmPlusOneOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printPCLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O);
};
Modified: llvm/branches/exception-handling-rewrite/lib/Target/ARM/InstPrinter/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/ARM/InstPrinter/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/ARM/InstPrinter/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/ARM/InstPrinter/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -3,4 +3,4 @@
add_llvm_library(LLVMARMAsmPrinter
ARMInstPrinter.cpp
)
-add_dependencies(LLVMARMAsmPrinter ARMCodeGenTable_gen)
+add_dependencies(LLVMARMAsmPrinter ARMCommonTableGen)
Modified: llvm/branches/exception-handling-rewrite/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp Mon Jul 25 20:29:47 2011
@@ -19,7 +19,7 @@
#include "llvm/MC/MCObjectWriter.h"
#include "llvm/MC/MCSectionELF.h"
#include "llvm/MC/MCSectionMachO.h"
-#include "llvm/MC/TargetAsmBackend.h"
+#include "llvm/MC/MCAsmBackend.h"
#include "llvm/Object/MachOFormat.h"
#include "llvm/Support/ELF.h"
#include "llvm/Support/ErrorHandling.h"
@@ -34,10 +34,10 @@
/*HasRelocationAddend*/ false) {}
};
-class ARMAsmBackend : public TargetAsmBackend {
+class ARMAsmBackend : public MCAsmBackend {
bool isThumbMode; // Currently emitting Thumb code.
public:
- ARMAsmBackend(const Target &T) : TargetAsmBackend(), isThumbMode(false) {}
+ ARMAsmBackend(const Target &T) : MCAsmBackend(), isThumbMode(false) {}
unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
@@ -80,7 +80,7 @@
};
if (Kind < FirstTargetFixupKind)
- return TargetAsmBackend::getFixupKindInfo(Kind);
+ return MCAsmBackend::getFixupKindInfo(Kind);
assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
"Invalid kind!");
@@ -491,8 +491,7 @@
} // end anonymous namespace
-TargetAsmBackend *llvm::createARMAsmBackend(const Target &T,
- const std::string &TT) {
+MCAsmBackend *llvm::createARMAsmBackend(const Target &T, StringRef TT) {
Triple TheTriple(TT);
if (TheTriple.isOSDarwin()) {
Modified: llvm/branches/exception-handling-rewrite/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h Mon Jul 25 20:29:47 2011
@@ -20,9 +20,6 @@
#include "ARMMCTargetDesc.h"
#include "llvm/Support/ErrorHandling.h"
-// Note that the following auto-generated files only defined enum types, and
-// so are safe to include here.
-
namespace llvm {
// Enums corresponding to ARM condition codes
Modified: llvm/branches/exception-handling-rewrite/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Mon Jul 25 20:29:47 2011
@@ -13,6 +13,7 @@
#include "ARMMCTargetDesc.h"
#include "ARMMCAsmInfo.h"
+#include "InstPrinter/ARMInstPrinter.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCStreamer.h"
@@ -131,8 +132,8 @@
}
// This is duplicated code. Refactor this.
-static MCStreamer *createMCStreamer(const Target &T, const std::string &TT,
- MCContext &Ctx, TargetAsmBackend &TAB,
+static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
+ MCContext &Ctx, MCAsmBackend &MAB,
raw_ostream &OS,
MCCodeEmitter *Emitter,
bool RelaxAll,
@@ -140,14 +141,22 @@
Triple TheTriple(TT);
if (TheTriple.isOSDarwin())
- return createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll);
+ return createMachOStreamer(Ctx, MAB, OS, Emitter, RelaxAll);
if (TheTriple.isOSWindows()) {
llvm_unreachable("ARM does not support Windows COFF format");
return NULL;
}
- return createELFStreamer(Ctx, TAB, OS, Emitter, RelaxAll, NoExecStack);
+ return createELFStreamer(Ctx, MAB, OS, Emitter, RelaxAll, NoExecStack);
+}
+
+static MCInstPrinter *createARMMCInstPrinter(const Target &T,
+ unsigned SyntaxVariant,
+ const MCAsmInfo &MAI) {
+ if (SyntaxVariant == 0)
+ return new ARMInstPrinter(MAI);
+ return 0;
}
@@ -176,14 +185,18 @@
ARM_MC::createARMMCSubtargetInfo);
// Register the MC Code Emitter
- TargetRegistry::RegisterCodeEmitter(TheARMTarget, createARMMCCodeEmitter);
- TargetRegistry::RegisterCodeEmitter(TheThumbTarget, createARMMCCodeEmitter);
+ TargetRegistry::RegisterMCCodeEmitter(TheARMTarget, createARMMCCodeEmitter);
+ TargetRegistry::RegisterMCCodeEmitter(TheThumbTarget, createARMMCCodeEmitter);
// Register the asm backend.
- TargetRegistry::RegisterAsmBackend(TheARMTarget, createARMAsmBackend);
- TargetRegistry::RegisterAsmBackend(TheThumbTarget, createARMAsmBackend);
+ TargetRegistry::RegisterMCAsmBackend(TheARMTarget, createARMAsmBackend);
+ TargetRegistry::RegisterMCAsmBackend(TheThumbTarget, createARMAsmBackend);
// Register the object streamer.
- TargetRegistry::RegisterObjectStreamer(TheARMTarget, createMCStreamer);
- TargetRegistry::RegisterObjectStreamer(TheThumbTarget, createMCStreamer);
+ TargetRegistry::RegisterMCObjectStreamer(TheARMTarget, createMCStreamer);
+ TargetRegistry::RegisterMCObjectStreamer(TheThumbTarget, createMCStreamer);
+
+ // Register the MCInstPrinter.
+ TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
+ TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);
}
Modified: llvm/branches/exception-handling-rewrite/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h Mon Jul 25 20:29:47 2011
@@ -18,6 +18,7 @@
#include <string>
namespace llvm {
+class MCAsmBackend;
class MCCodeEmitter;
class MCContext;
class MCInstrInfo;
@@ -25,7 +26,6 @@
class MCSubtargetInfo;
class StringRef;
class Target;
-class TargetAsmBackend;
class raw_ostream;
extern Target TheARMTarget, TheThumbTarget;
@@ -44,7 +44,7 @@
const MCSubtargetInfo &STI,
MCContext &Ctx);
-TargetAsmBackend *createARMAsmBackend(const Target&, const std::string &);
+MCAsmBackend *createARMAsmBackend(const Target &T, StringRef TT);
/// createARMMachObjectWriter - Construct an ARM Mach-O object writer.
MCObjectWriter *createARMMachObjectWriter(raw_ostream &OS,
Modified: llvm/branches/exception-handling-rewrite/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp Mon Jul 25 20:29:47 2011
@@ -17,7 +17,6 @@
#include "llvm/MC/MCFixup.h"
#include "llvm/MC/MCFixupKindInfo.h"
#include "llvm/MC/MCValue.h"
-#include "llvm/MC/TargetAsmBackend.h"
#include "llvm/Object/MachOFormat.h"
#include "llvm/Support/ErrorHandling.h"
using namespace llvm;
Modified: llvm/branches/exception-handling-rewrite/lib/Target/ARM/MCTargetDesc/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/ARM/MCTargetDesc/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/ARM/MCTargetDesc/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/ARM/MCTargetDesc/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -6,6 +6,7 @@
ARMMCExpr.cpp
ARMMachObjectWriter.cpp
)
+add_dependencies(LLVMARMDesc ARMCommonTableGen)
# Hack: we need to include 'main' target directory to grab private headers
include_directories(${CMAKE_CURRENT_SOURCE_DIR}/.. ${CMAKE_CURRENT_BINARY_DIR}/..)
Modified: llvm/branches/exception-handling-rewrite/lib/Target/Alpha/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/Alpha/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/Alpha/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/Alpha/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -6,6 +6,7 @@
tablegen(AlphaGenDAGISel.inc -gen-dag-isel)
tablegen(AlphaGenCallingConv.inc -gen-callingconv)
tablegen(AlphaGenSubtargetInfo.inc -gen-subtarget)
+add_public_tablegen_target(AlphaCommonTableGen)
add_llvm_target(AlphaCodeGen
AlphaAsmPrinter.cpp
Modified: llvm/branches/exception-handling-rewrite/lib/Target/Alpha/MCTargetDesc/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/Alpha/MCTargetDesc/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/Alpha/MCTargetDesc/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/Alpha/MCTargetDesc/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -2,3 +2,4 @@
AlphaMCTargetDesc.cpp
AlphaMCAsmInfo.cpp
)
+add_dependencies(LLVMAlphaDesc AlphaCommonTableGen)
Modified: llvm/branches/exception-handling-rewrite/lib/Target/Alpha/TargetInfo/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/Alpha/TargetInfo/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/Alpha/TargetInfo/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/Alpha/TargetInfo/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -3,5 +3,4 @@
add_llvm_library(LLVMAlphaInfo
AlphaTargetInfo.cpp
)
-
-add_dependencies(LLVMAlphaInfo AlphaCodeGenTable_gen)
+add_dependencies(LLVMAlphaInfo AlphaCommonTableGen)
Modified: llvm/branches/exception-handling-rewrite/lib/Target/Blackfin/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/Blackfin/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/Blackfin/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/Blackfin/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -7,6 +7,7 @@
tablegen(BlackfinGenSubtargetInfo.inc -gen-subtarget)
tablegen(BlackfinGenCallingConv.inc -gen-callingconv)
tablegen(BlackfinGenIntrinsics.inc -gen-tgt-intrinsic)
+add_public_tablegen_target(BlackfinCommonTableGen)
add_llvm_target(BlackfinCodeGen
BlackfinAsmPrinter.cpp
Modified: llvm/branches/exception-handling-rewrite/lib/Target/Blackfin/MCTargetDesc/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/Blackfin/MCTargetDesc/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/Blackfin/MCTargetDesc/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/Blackfin/MCTargetDesc/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -2,3 +2,4 @@
BlackfinMCTargetDesc.cpp
BlackfinMCAsmInfo.cpp
)
+add_dependencies(LLVMBlackfinDesc BlackfinCommonTableGen)
Modified: llvm/branches/exception-handling-rewrite/lib/Target/CBackend/CBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/CBackend/CBackend.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/CBackend/CBackend.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/CBackend/CBackend.cpp Mon Jul 25 20:29:47 2011
@@ -64,8 +64,6 @@
RegisterTargetMachine<CTargetMachine> X(TheCBackendTarget);
}
-extern "C" void LLVMInitializeCBackendTargetMC() {}
-
namespace {
class CBEMCAsmInfo : public MCAsmInfo {
public:
Modified: llvm/branches/exception-handling-rewrite/lib/Target/CBackend/TargetInfo/CBackendTargetInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/CBackend/TargetInfo/CBackendTargetInfo.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/CBackend/TargetInfo/CBackendTargetInfo.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/CBackend/TargetInfo/CBackendTargetInfo.cpp Mon Jul 25 20:29:47 2011
@@ -17,3 +17,5 @@
extern "C" void LLVMInitializeCBackendTargetInfo() {
RegisterTarget<> X(TheCBackendTarget, "c", "C backend");
}
+
+extern "C" void LLVMInitializeCBackendTargetMC() {}
Modified: llvm/branches/exception-handling-rewrite/lib/Target/CellSPU/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/CellSPU/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/CellSPU/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/CellSPU/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -7,6 +7,7 @@
tablegen(SPUGenDAGISel.inc -gen-dag-isel)
tablegen(SPUGenSubtargetInfo.inc -gen-subtarget)
tablegen(SPUGenCallingConv.inc -gen-callingconv)
+add_public_tablegen_target(CellSPUCommonTableGen)
add_llvm_target(CellSPUCodeGen
SPUAsmPrinter.cpp
Modified: llvm/branches/exception-handling-rewrite/lib/Target/CellSPU/MCTargetDesc/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/CellSPU/MCTargetDesc/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/CellSPU/MCTargetDesc/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/CellSPU/MCTargetDesc/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -2,3 +2,4 @@
SPUMCTargetDesc.cpp
SPUMCAsmInfo.cpp
)
+add_dependencies(LLVMCellSPUDesc CellSPUCommonTableGen)
Modified: llvm/branches/exception-handling-rewrite/lib/Target/CppBackend/CPPBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/CppBackend/CPPBackend.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/CppBackend/CPPBackend.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/CppBackend/CPPBackend.cpp Mon Jul 25 20:29:47 2011
@@ -77,8 +77,6 @@
RegisterTargetMachine<CPPTargetMachine> X(TheCppBackendTarget);
}
-extern "C" void LLVMInitializeCppBackendTargetMC() {}
-
namespace {
typedef std::vector<Type*> TypeList;
typedef std::map<Type*,std::string> TypeMap;
Modified: llvm/branches/exception-handling-rewrite/lib/Target/CppBackend/TargetInfo/CppBackendTargetInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/CppBackend/TargetInfo/CppBackendTargetInfo.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/CppBackend/TargetInfo/CppBackendTargetInfo.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/CppBackend/TargetInfo/CppBackendTargetInfo.cpp Mon Jul 25 20:29:47 2011
@@ -24,3 +24,5 @@
"C++ backend",
&CppBackend_TripleMatchQuality);
}
+
+extern "C" void LLVMInitializeCppBackendTargetMC() {}
Modified: llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/AsmParser/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/AsmParser/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/AsmParser/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/AsmParser/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -5,4 +5,5 @@
MBlazeAsmLexer.cpp
MBlazeAsmParser.cpp
)
+add_dependencies(LLVMMBlazeAsmParser MBlazeCommonTableGen)
Modified: llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/AsmParser/MBlazeAsmLexer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/AsmParser/MBlazeAsmLexer.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/AsmParser/MBlazeAsmLexer.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/AsmParser/MBlazeAsmLexer.cpp Mon Jul 25 20:29:47 2011
@@ -7,8 +7,7 @@
//
//===----------------------------------------------------------------------===//
-#include "MBlaze.h"
-#include "MBlazeTargetMachine.h"
+#include "MCTargetDesc/MBlazeBaseInfo.h"
#include "llvm/ADT/OwningPtr.h"
#include "llvm/ADT/SmallVector.h"
@@ -17,9 +16,9 @@
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCParser/MCAsmLexer.h"
#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
-#include "llvm/MC/TargetAsmLexer.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/MC/MCTargetAsmLexer.h"
-#include "llvm/Target/TargetMachine.h" // FIXME
#include "llvm/Target/TargetRegistry.h"
#include <string>
@@ -29,7 +28,7 @@
namespace {
- class MBlazeBaseAsmLexer : public TargetAsmLexer {
+ class MBlazeBaseAsmLexer : public MCTargetAsmLexer {
const MCAsmInfo &AsmInfo;
const AsmToken &lexDefinite() {
@@ -42,7 +41,7 @@
rmap_ty RegisterMap;
- void InitRegisterMap(const TargetRegisterInfo *info) {
+ void InitRegisterMap(const MCRegisterInfo *info) {
unsigned numRegs = info->getNumRegs();
for (unsigned i = 0; i < numRegs; ++i) {
@@ -76,20 +75,16 @@
}
public:
MBlazeBaseAsmLexer(const Target &T, const MCAsmInfo &MAI)
- : TargetAsmLexer(T), AsmInfo(MAI) {
+ : MCTargetAsmLexer(T), AsmInfo(MAI) {
}
};
class MBlazeAsmLexer : public MBlazeBaseAsmLexer {
public:
- MBlazeAsmLexer(const Target &T, const MCAsmInfo &MAI)
+ MBlazeAsmLexer(const Target &T, const MCRegisterInfo &MRI,
+ const MCAsmInfo &MAI)
: MBlazeBaseAsmLexer(T, MAI) {
- std::string tripleString("mblaze-unknown-unknown");
- std::string featureString;
- std::string CPU;
- OwningPtr<const TargetMachine>
- targetMachine(T.createTargetMachine(tripleString, CPU, featureString));
- InitRegisterMap(targetMachine->getRegisterInfo());
+ InitRegisterMap(&MRI);
}
};
}
@@ -123,6 +118,6 @@
}
extern "C" void LLVMInitializeMBlazeAsmLexer() {
- RegisterAsmLexer<MBlazeAsmLexer> X(TheMBlazeTarget);
+ RegisterMCAsmLexer<MBlazeAsmLexer> X(TheMBlazeTarget);
}
Modified: llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp Mon Jul 25 20:29:47 2011
@@ -7,17 +7,14 @@
//
//===----------------------------------------------------------------------===//
-#include "MBlaze.h"
-#include "MBlazeSubtarget.h"
-#include "MBlazeRegisterInfo.h"
-#include "MBlazeISelLowering.h"
+#include "MCTargetDesc/MBlazeBaseInfo.h"
#include "llvm/MC/MCParser/MCAsmLexer.h"
#include "llvm/MC/MCParser/MCAsmParser.h"
#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
-#include "llvm/MC/TargetAsmParser.h"
+#include "llvm/MC/MCTargetAsmParser.h"
#include "llvm/Target/TargetRegistry.h"
#include "llvm/Support/SourceMgr.h"
#include "llvm/Support/raw_ostream.h"
@@ -30,7 +27,7 @@
namespace {
struct MBlazeOperand;
-class MBlazeAsmParser : public TargetAsmParser {
+class MBlazeAsmParser : public MCTargetAsmParser {
MCAsmParser &Parser;
MCAsmParser &getParser() const { return Parser; }
@@ -64,7 +61,7 @@
public:
MBlazeAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
- : TargetAsmParser(), Parser(_Parser) {}
+ : MCTargetAsmParser(), Parser(_Parser) {}
virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands);
@@ -286,19 +283,19 @@
break;
case Register:
OS << "<register R";
- OS << MBlazeRegisterInfo::getRegisterNumbering(getReg()) << ">";
+ OS << getMBlazeRegisterNumbering(getReg()) << ">";
break;
case Token:
OS << "'" << getToken() << "'";
break;
case Memory: {
OS << "<memory R";
- OS << MBlazeRegisterInfo::getRegisterNumbering(getMemBase());
+ OS << getMBlazeRegisterNumbering(getMemBase());
OS << ", ";
unsigned RegOff = getMemOffReg();
if (RegOff)
- OS << "R" << MBlazeRegisterInfo::getRegisterNumbering(RegOff);
+ OS << "R" << getMBlazeRegisterNumbering(RegOff);
else
OS << getMemOff();
OS << ">";
@@ -558,7 +555,7 @@
/// Force static initialization.
extern "C" void LLVMInitializeMBlazeAsmParser() {
- RegisterAsmParser<MBlazeAsmParser> X(TheMBlazeTarget);
+ RegisterMCAsmParser<MBlazeAsmParser> X(TheMBlazeTarget);
LLVMInitializeMBlazeAsmLexer();
}
Modified: llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -10,6 +10,7 @@
tablegen(MBlazeGenSubtargetInfo.inc -gen-subtarget)
tablegen(MBlazeGenIntrinsics.inc -gen-tgt-intrinsic)
tablegen(MBlazeGenEDInfo.inc -gen-enhanced-disassembly-info)
+add_public_tablegen_target(MBlazeCommonTableGen)
add_llvm_target(MBlazeCodeGen
MBlazeDelaySlotFiller.cpp
@@ -24,10 +25,8 @@
MBlazeIntrinsicInfo.cpp
MBlazeSelectionDAGInfo.cpp
MBlazeAsmPrinter.cpp
- MBlazeAsmBackend.cpp
MBlazeMCInstLower.cpp
MBlazeELFWriterInfo.cpp
- MBlazeMCCodeEmitter.cpp
)
add_subdirectory(AsmParser)
Modified: llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/Disassembler/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/Disassembler/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/Disassembler/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/Disassembler/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -13,4 +13,4 @@
)
endif()
-add_dependencies(LLVMMBlazeDisassembler MBlazeCodeGenTable_gen)
+add_dependencies(LLVMMBlazeDisassembler MBlazeCommonTableGen)
Modified: llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp Mon Jul 25 20:29:47 2011
@@ -60,27 +60,27 @@
};
static unsigned getRD(uint32_t insn) {
- if (!MBlazeRegisterInfo::isRegister((insn>>21)&0x1F))
+ if (!isMBlazeRegister((insn>>21)&0x1F))
return UNSUPPORTED;
- return MBlazeRegisterInfo::getRegisterFromNumbering((insn>>21)&0x1F);
+ return getMBlazeRegisterFromNumbering((insn>>21)&0x1F);
}
static unsigned getRA(uint32_t insn) {
- if (!MBlazeRegisterInfo::getRegisterFromNumbering((insn>>16)&0x1F))
+ if (!getMBlazeRegisterFromNumbering((insn>>16)&0x1F))
return UNSUPPORTED;
- return MBlazeRegisterInfo::getRegisterFromNumbering((insn>>16)&0x1F);
+ return getMBlazeRegisterFromNumbering((insn>>16)&0x1F);
}
static unsigned getRB(uint32_t insn) {
- if (!MBlazeRegisterInfo::getRegisterFromNumbering((insn>>11)&0x1F))
+ if (!getMBlazeRegisterFromNumbering((insn>>11)&0x1F))
return UNSUPPORTED;
- return MBlazeRegisterInfo::getRegisterFromNumbering((insn>>11)&0x1F);
+ return getMBlazeRegisterFromNumbering((insn>>11)&0x1F);
}
static int64_t getRS(uint32_t insn) {
- if (!MBlazeRegisterInfo::isSpecialRegister(insn&0x3FFF))
+ if (!isSpecialMBlazeRegister(insn&0x3FFF))
return UNSUPPORTED;
- return MBlazeRegisterInfo::getSpecialRegisterFromNumbering(insn&0x3FFF);
+ return getSpecialMBlazeRegisterFromNumbering(insn&0x3FFF);
}
static int64_t getIMM(uint32_t insn) {
Modified: llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/InstPrinter/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/InstPrinter/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/InstPrinter/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/InstPrinter/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -5,4 +5,4 @@
MBlazeInstPrinter.cpp
)
-add_dependencies(LLVMMBlazeAsmPrinter MBlazeCodeGenTable_gen)
+add_dependencies(LLVMMBlazeAsmPrinter MBlazeCommonTableGen)
Modified: llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlaze.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlaze.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlaze.h (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlaze.h Mon Jul 25 20:29:47 2011
@@ -15,6 +15,7 @@
#ifndef TARGET_MBLAZE_H
#define TARGET_MBLAZE_H
+#include "MCTargetDesc/MBlazeBaseInfo.h"
#include "MCTargetDesc/MBlazeMCTargetDesc.h"
#include "llvm/Target/TargetMachine.h"
@@ -22,17 +23,6 @@
class MBlazeTargetMachine;
class FunctionPass;
class MachineCodeEmitter;
- class MCCodeEmitter;
- class MCInstrInfo;
- class MCSubtargetInfo;
- class TargetAsmBackend;
- class formatted_raw_ostream;
-
- MCCodeEmitter *createMBlazeMCCodeEmitter(const MCInstrInfo &MCII,
- const MCSubtargetInfo &STI,
- MCContext &Ctx);
-
- TargetAsmBackend *createMBlazeAsmBackend(const Target &, const std::string &);
FunctionPass *createMBlazeISelDag(MBlazeTargetMachine &TM);
FunctionPass *createMBlazeDelaySlotFillerPass(MBlazeTargetMachine &TM);
Removed: llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeAsmBackend.cpp?rev=136039&view=auto
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeAsmBackend.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeAsmBackend.cpp (removed)
@@ -1,161 +0,0 @@
-//===-- MBlazeAsmBackend.cpp - MBlaze Assembler Backend -------------------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#include "llvm/MC/TargetAsmBackend.h"
-#include "MBlaze.h"
-#include "MBlazeELFWriterInfo.h"
-#include "llvm/ADT/Twine.h"
-#include "llvm/MC/MCAssembler.h"
-#include "llvm/MC/MCAsmLayout.h"
-#include "llvm/MC/MCELFObjectWriter.h"
-#include "llvm/MC/MCELFSymbolFlags.h"
-#include "llvm/MC/MCExpr.h"
-#include "llvm/MC/MCObjectWriter.h"
-#include "llvm/MC/MCSectionELF.h"
-#include "llvm/MC/MCSectionMachO.h"
-#include "llvm/MC/MCValue.h"
-#include "llvm/Support/ELF.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegistry.h"
-using namespace llvm;
-
-static unsigned getFixupKindSize(unsigned Kind) {
- switch (Kind) {
- default: assert(0 && "invalid fixup kind!");
- case FK_Data_1: return 1;
- case FK_PCRel_2:
- case FK_Data_2: return 2;
- case FK_PCRel_4:
- case FK_Data_4: return 4;
- case FK_Data_8: return 8;
- }
-}
-
-
-namespace {
-class MBlazeELFObjectWriter : public MCELFObjectTargetWriter {
-public:
- MBlazeELFObjectWriter(Triple::OSType OSType)
- : MCELFObjectTargetWriter(/*is64Bit*/ false, OSType, ELF::EM_MBLAZE,
- /*HasRelocationAddend*/ true) {}
-};
-
-class MBlazeAsmBackend : public TargetAsmBackend {
-public:
- MBlazeAsmBackend(const Target &T)
- : TargetAsmBackend() {
- }
-
- unsigned getNumFixupKinds() const {
- return 2;
- }
-
- bool MayNeedRelaxation(const MCInst &Inst) const;
-
- void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
-
- bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
-
- unsigned getPointerSize() const {
- return 4;
- }
-};
-
-static unsigned getRelaxedOpcode(unsigned Op) {
- switch (Op) {
- default: return Op;
- case MBlaze::ADDIK: return MBlaze::ADDIK32;
- case MBlaze::ORI: return MBlaze::ORI32;
- case MBlaze::BRLID: return MBlaze::BRLID32;
- }
-}
-
-bool MBlazeAsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
- if (getRelaxedOpcode(Inst.getOpcode()) == Inst.getOpcode())
- return false;
-
- bool hasExprOrImm = false;
- for (unsigned i = 0; i < Inst.getNumOperands(); ++i)
- hasExprOrImm |= Inst.getOperand(i).isExpr();
-
- return hasExprOrImm;
-}
-
-void MBlazeAsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
- Res = Inst;
- Res.setOpcode(getRelaxedOpcode(Inst.getOpcode()));
-}
-
-bool MBlazeAsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
- if ((Count % 4) != 0)
- return false;
-
- for (uint64_t i = 0; i < Count; i += 4)
- OW->Write32(0x00000000);
-
- return true;
-}
-} // end anonymous namespace
-
-namespace {
-class ELFMBlazeAsmBackend : public MBlazeAsmBackend {
-public:
- Triple::OSType OSType;
- ELFMBlazeAsmBackend(const Target &T, Triple::OSType _OSType)
- : MBlazeAsmBackend(T), OSType(_OSType) { }
-
- void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
- uint64_t Value) const;
-
- MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
- return createELFObjectWriter(new MBlazeELFObjectWriter(OSType), OS,
- /*IsLittleEndian*/ false);
- }
-};
-
-void ELFMBlazeAsmBackend::ApplyFixup(const MCFixup &Fixup, char *Data,
- unsigned DataSize, uint64_t Value) const {
- unsigned Size = getFixupKindSize(Fixup.getKind());
-
- assert(Fixup.getOffset() + Size <= DataSize &&
- "Invalid fixup offset!");
-
- char *data = Data + Fixup.getOffset();
- switch (Size) {
- default: llvm_unreachable("Cannot fixup unknown value.");
- case 1: llvm_unreachable("Cannot fixup 1 byte value.");
- case 8: llvm_unreachable("Cannot fixup 8 byte value.");
-
- case 4:
- *(data+7) = uint8_t(Value);
- *(data+6) = uint8_t(Value >> 8);
- *(data+3) = uint8_t(Value >> 16);
- *(data+2) = uint8_t(Value >> 24);
- break;
-
- case 2:
- *(data+3) = uint8_t(Value >> 0);
- *(data+2) = uint8_t(Value >> 8);
- }
-}
-} // end anonymous namespace
-
-TargetAsmBackend *llvm::createMBlazeAsmBackend(const Target &T,
- const std::string &TT) {
- Triple TheTriple(TT);
-
- if (TheTriple.isOSDarwin())
- assert(0 && "Mac not supported on MBlaze");
-
- if (TheTriple.isOSWindows())
- assert(0 && "Windows not supported on MBlaze");
-
- return new ELFMBlazeAsmBackend(T, TheTriple.getOS());
-}
Modified: llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeAsmPrinter.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeAsmPrinter.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeAsmPrinter.cpp Mon Jul 25 20:29:47 2011
@@ -136,19 +136,17 @@
const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
unsigned Reg = CSI[i].getReg();
- unsigned RegNum = MBlazeRegisterInfo::getRegisterNumbering(Reg);
+ unsigned RegNum = getMBlazeRegisterNumbering(Reg);
if (MBlaze::GPRRegisterClass->contains(Reg))
CPUBitmask |= (1 << RegNum);
}
// Return Address and Frame registers must also be set in CPUBitmask.
if (TFI->hasFP(*MF))
- CPUBitmask |= (1 << MBlazeRegisterInfo::
- getRegisterNumbering(RI.getFrameRegister(*MF)));
+ CPUBitmask |= (1 << getMBlazeRegisterNumbering(RI.getFrameRegister(*MF)));
if (MFI->adjustsStack())
- CPUBitmask |= (1 << MBlazeRegisterInfo::
- getRegisterNumbering(RI.getRARegister()));
+ CPUBitmask |= (1 << getMBlazeRegisterNumbering(RI.getRARegister()));
// Print CPUBitmask
OutStreamer.EmitRawText("\t.mask\t0x" + Twine::utohexstr(CPUBitmask));
@@ -318,18 +316,7 @@
return I == Pred->end() || !I->getDesc().isBarrier();
}
-static MCInstPrinter *createMBlazeMCInstPrinter(const Target &T,
- unsigned SyntaxVariant,
- const MCAsmInfo &MAI) {
- if (SyntaxVariant == 0)
- return new MBlazeInstPrinter(MAI);
- return 0;
-}
-
// Force static initialization.
extern "C" void LLVMInitializeMBlazeAsmPrinter() {
RegisterAsmPrinter<MBlazeAsmPrinter> X(TheMBlazeTarget);
- TargetRegistry::RegisterMCInstPrinter(TheMBlazeTarget,
- createMBlazeMCInstPrinter);
-
}
Modified: llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeISelLowering.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeISelLowering.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeISelLowering.cpp Mon Jul 25 20:29:47 2011
@@ -964,13 +964,13 @@
// The last register argument that must be saved is MBlaze::R10
TargetRegisterClass *RC = MBlaze::GPRRegisterClass;
- unsigned Begin = MBlazeRegisterInfo::getRegisterNumbering(MBlaze::R5);
- unsigned Start = MBlazeRegisterInfo::getRegisterNumbering(ArgRegEnd+1);
- unsigned End = MBlazeRegisterInfo::getRegisterNumbering(MBlaze::R10);
+ unsigned Begin = getMBlazeRegisterNumbering(MBlaze::R5);
+ unsigned Start = getMBlazeRegisterNumbering(ArgRegEnd+1);
+ unsigned End = getMBlazeRegisterNumbering(MBlaze::R10);
unsigned StackLoc = Start - Begin + 1;
for (; Start <= End; ++Start, ++StackLoc) {
- unsigned Reg = MBlazeRegisterInfo::getRegisterFromNumbering(Start);
+ unsigned Reg = getMBlazeRegisterFromNumbering(Start);
unsigned LiveReg = MF.addLiveIn(Reg, RC);
SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, LiveReg, MVT::i32);
Modified: llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeInstrInfo.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeInstrInfo.h (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeInstrInfo.h Mon Jul 25 20:29:47 2011
@@ -166,62 +166,6 @@
}
}
-/// MBlazeII - This namespace holds all of the target specific flags that
-/// instruction info tracks.
-///
-namespace MBlazeII {
- enum {
- // PseudoFrm - This represents an instruction that is a pseudo instruction
- // or one that has not been implemented yet. It is illegal to code generate
- // it, but tolerated for intermediate implementation stages.
- FPseudo = 0,
- FRRR,
- FRRI,
- FCRR,
- FCRI,
- FRCR,
- FRCI,
- FCCR,
- FCCI,
- FRRCI,
- FRRC,
- FRCX,
- FRCS,
- FCRCS,
- FCRCX,
- FCX,
- FCR,
- FRIR,
- FRRRR,
- FRI,
- FC,
- FormMask = 63
-
- //===------------------------------------------------------------------===//
- // MBlaze Specific MachineOperand flags.
- // MO_NO_FLAG,
-
- /// MO_GOT - Represents the offset into the global offset table at which
- /// the address the relocation entry symbol resides during execution.
- // MO_GOT,
-
- /// MO_GOT_CALL - Represents the offset into the global offset table at
- /// which the address of a call site relocation entry symbol resides
- /// during execution. This is different from the above since this flag
- /// can only be present in call instructions.
- // MO_GOT_CALL,
-
- /// MO_GPREL - Represents the offset from the current gp value to be used
- /// for the relocatable object file being produced.
- // MO_GPREL,
-
- /// MO_ABS_HILO - Represents the hi or low part of an absolute symbol
- /// address.
- // MO_ABS_HILO
-
- };
-}
-
class MBlazeInstrInfo : public MBlazeGenInstrInfo {
MBlazeTargetMachine &TM;
const MBlazeRegisterInfo RI;
Removed: llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp?rev=136039&view=auto
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp (removed)
@@ -1,222 +0,0 @@
-//===-- MBlazeMCCodeEmitter.cpp - Convert MBlaze code to machine code -----===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file implements the MBlazeMCCodeEmitter class.
-//
-//===----------------------------------------------------------------------===//
-
-#define DEBUG_TYPE "mccodeemitter"
-#include "MBlaze.h"
-#include "MBlazeInstrInfo.h"
-#include "llvm/MC/MCCodeEmitter.h"
-#include "llvm/MC/MCExpr.h"
-#include "llvm/MC/MCInst.h"
-#include "llvm/MC/MCSymbol.h"
-#include "llvm/MC/MCFixup.h"
-#include "llvm/ADT/Statistic.h"
-#include "llvm/Support/raw_ostream.h"
-using namespace llvm;
-
-STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
-
-namespace {
-class MBlazeMCCodeEmitter : public MCCodeEmitter {
- MBlazeMCCodeEmitter(const MBlazeMCCodeEmitter &); // DO NOT IMPLEMENT
- void operator=(const MBlazeMCCodeEmitter &); // DO NOT IMPLEMENT
- const MCInstrInfo &MCII;
-
-public:
- MBlazeMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
- MCContext &ctx)
- : MCII(mcii) {
- }
-
- ~MBlazeMCCodeEmitter() {}
-
- // getBinaryCodeForInstr - TableGen'erated function for getting the
- // binary encoding for an instruction.
- unsigned getBinaryCodeForInstr(const MCInst &MI) const;
-
- /// getMachineOpValue - Return binary encoding of operand. If the machine
- /// operand requires relocation, record the relocation and return zero.
- unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO) const;
- unsigned getMachineOpValue(const MCInst &MI, unsigned OpIdx) const {
- return getMachineOpValue(MI, MI.getOperand(OpIdx));
- }
-
- static unsigned GetMBlazeRegNum(const MCOperand &MO) {
- // FIXME: getMBlazeRegisterNumbering() is sufficient?
- assert(0 && "MBlazeMCCodeEmitter::GetMBlazeRegNum() not yet implemented.");
- return 0;
- }
-
- void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
- // The MicroBlaze uses a bit reversed format so we need to reverse the
- // order of the bits. Taken from:
- // http://graphics.stanford.edu/~seander/bithacks.html
- C = ((C * 0x80200802ULL) & 0x0884422110ULL) * 0x0101010101ULL >> 32;
-
- OS << (char)C;
- ++CurByte;
- }
-
- void EmitRawByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
- OS << (char)C;
- ++CurByte;
- }
-
- void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
- raw_ostream &OS) const {
- assert(Size <= 8 && "size too big in emit constant");
-
- for (unsigned i = 0; i != Size; ++i) {
- EmitByte(Val & 255, CurByte, OS);
- Val >>= 8;
- }
- }
-
- void EmitIMM(const MCOperand &imm, unsigned &CurByte, raw_ostream &OS) const;
- void EmitIMM(const MCInst &MI, unsigned &CurByte, raw_ostream &OS) const;
-
- void EmitImmediate(const MCInst &MI, unsigned opNo, bool pcrel,
- unsigned &CurByte, raw_ostream &OS,
- SmallVectorImpl<MCFixup> &Fixups) const;
-
- void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
- SmallVectorImpl<MCFixup> &Fixups) const;
-};
-
-} // end anonymous namespace
-
-
-MCCodeEmitter *llvm::createMBlazeMCCodeEmitter(const MCInstrInfo &MCII,
- const MCSubtargetInfo &STI,
- MCContext &Ctx) {
- return new MBlazeMCCodeEmitter(MCII, STI, Ctx);
-}
-
-/// getMachineOpValue - Return binary encoding of operand. If the machine
-/// operand requires relocation, record the relocation and return zero.
-unsigned MBlazeMCCodeEmitter::getMachineOpValue(const MCInst &MI,
- const MCOperand &MO) const {
- if (MO.isReg())
- return MBlazeRegisterInfo::getRegisterNumbering(MO.getReg());
- else if (MO.isImm())
- return static_cast<unsigned>(MO.getImm());
- else if (MO.isExpr())
- return 0; // The relocation has already been recorded at this point.
- else {
-#ifndef NDEBUG
- errs() << MO;
-#endif
- llvm_unreachable(0);
- }
- return 0;
-}
-
-void MBlazeMCCodeEmitter::
-EmitIMM(const MCOperand &imm, unsigned &CurByte, raw_ostream &OS) const {
- int32_t val = (int32_t)imm.getImm();
- if (val > 32767 || val < -32768) {
- EmitByte(0x0D, CurByte, OS);
- EmitByte(0x00, CurByte, OS);
- EmitRawByte((val >> 24) & 0xFF, CurByte, OS);
- EmitRawByte((val >> 16) & 0xFF, CurByte, OS);
- }
-}
-
-void MBlazeMCCodeEmitter::
-EmitIMM(const MCInst &MI, unsigned &CurByte,raw_ostream &OS) const {
- switch (MI.getOpcode()) {
- default: break;
-
- case MBlaze::ADDIK32:
- case MBlaze::ORI32:
- case MBlaze::BRLID32:
- EmitByte(0x0D, CurByte, OS);
- EmitByte(0x00, CurByte, OS);
- EmitRawByte(0, CurByte, OS);
- EmitRawByte(0, CurByte, OS);
- }
-}
-
-void MBlazeMCCodeEmitter::
-EmitImmediate(const MCInst &MI, unsigned opNo, bool pcrel, unsigned &CurByte,
- raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups) const {
- assert(MI.getNumOperands()>opNo && "Not enought operands for instruction");
-
- MCOperand oper = MI.getOperand(opNo);
-
- if (oper.isImm()) {
- EmitIMM(oper, CurByte, OS);
- } else if (oper.isExpr()) {
- MCFixupKind FixupKind;
- switch (MI.getOpcode()) {
- default:
- FixupKind = pcrel ? FK_PCRel_2 : FK_Data_2;
- Fixups.push_back(MCFixup::Create(0,oper.getExpr(),FixupKind));
- break;
- case MBlaze::ORI32:
- case MBlaze::ADDIK32:
- case MBlaze::BRLID32:
- FixupKind = pcrel ? FK_PCRel_4 : FK_Data_4;
- Fixups.push_back(MCFixup::Create(0,oper.getExpr(),FixupKind));
- break;
- }
- }
-}
-
-
-
-void MBlazeMCCodeEmitter::
-EncodeInstruction(const MCInst &MI, raw_ostream &OS,
- SmallVectorImpl<MCFixup> &Fixups) const {
- unsigned Opcode = MI.getOpcode();
- const MCInstrDesc &Desc = MCII.get(Opcode);
- uint64_t TSFlags = Desc.TSFlags;
- // Keep track of the current byte being emitted.
- unsigned CurByte = 0;
-
- // Emit an IMM instruction if the instruction we are encoding requires it
- EmitIMM(MI,CurByte,OS);
-
- switch ((TSFlags & MBlazeII::FormMask)) {
- default: break;
- case MBlazeII::FPseudo:
- // Pseudo instructions don't get encoded.
- return;
- case MBlazeII::FRRI:
- EmitImmediate(MI, 2, false, CurByte, OS, Fixups);
- break;
- case MBlazeII::FRIR:
- EmitImmediate(MI, 1, false, CurByte, OS, Fixups);
- break;
- case MBlazeII::FCRI:
- EmitImmediate(MI, 1, true, CurByte, OS, Fixups);
- break;
- case MBlazeII::FRCI:
- EmitImmediate(MI, 1, true, CurByte, OS, Fixups);
- case MBlazeII::FCCI:
- EmitImmediate(MI, 0, true, CurByte, OS, Fixups);
- break;
- }
-
- ++MCNumEmitted; // Keep track of the # of mi's emitted
- unsigned Value = getBinaryCodeForInstr(MI);
- EmitConstant(Value, 4, CurByte, OS);
-}
-
-// FIXME: These #defines shouldn't be necessary. Instead, tblgen should
-// be able to generate code emitter helpers for either variant, like it
-// does for the AsmWriter.
-#define MBlazeCodeEmitter MBlazeMCCodeEmitter
-#define MachineInstr MCInst
-#include "MBlazeGenCodeEmitter.inc"
-#undef MBlazeCodeEmitter
-#undef MachineInstr
Modified: llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeRegisterInfo.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeRegisterInfo.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeRegisterInfo.cpp Mon Jul 25 20:29:47 2011
@@ -45,163 +45,6 @@
MBlazeRegisterInfo(const MBlazeSubtarget &ST, const TargetInstrInfo &tii)
: MBlazeGenRegisterInfo(MBlaze::R15), Subtarget(ST), TII(tii) {}
-/// getRegisterNumbering - Given the enum value for some register, e.g.
-/// MBlaze::R0, return the number that it corresponds to (e.g. 0).
-unsigned MBlazeRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
- switch (RegEnum) {
- case MBlaze::R0 : return 0;
- case MBlaze::R1 : return 1;
- case MBlaze::R2 : return 2;
- case MBlaze::R3 : return 3;
- case MBlaze::R4 : return 4;
- case MBlaze::R5 : return 5;
- case MBlaze::R6 : return 6;
- case MBlaze::R7 : return 7;
- case MBlaze::R8 : return 8;
- case MBlaze::R9 : return 9;
- case MBlaze::R10 : return 10;
- case MBlaze::R11 : return 11;
- case MBlaze::R12 : return 12;
- case MBlaze::R13 : return 13;
- case MBlaze::R14 : return 14;
- case MBlaze::R15 : return 15;
- case MBlaze::R16 : return 16;
- case MBlaze::R17 : return 17;
- case MBlaze::R18 : return 18;
- case MBlaze::R19 : return 19;
- case MBlaze::R20 : return 20;
- case MBlaze::R21 : return 21;
- case MBlaze::R22 : return 22;
- case MBlaze::R23 : return 23;
- case MBlaze::R24 : return 24;
- case MBlaze::R25 : return 25;
- case MBlaze::R26 : return 26;
- case MBlaze::R27 : return 27;
- case MBlaze::R28 : return 28;
- case MBlaze::R29 : return 29;
- case MBlaze::R30 : return 30;
- case MBlaze::R31 : return 31;
- case MBlaze::RPC : return 0x0000;
- case MBlaze::RMSR : return 0x0001;
- case MBlaze::REAR : return 0x0003;
- case MBlaze::RESR : return 0x0005;
- case MBlaze::RFSR : return 0x0007;
- case MBlaze::RBTR : return 0x000B;
- case MBlaze::REDR : return 0x000D;
- case MBlaze::RPID : return 0x1000;
- case MBlaze::RZPR : return 0x1001;
- case MBlaze::RTLBX : return 0x1002;
- case MBlaze::RTLBLO : return 0x1003;
- case MBlaze::RTLBHI : return 0x1004;
- case MBlaze::RPVR0 : return 0x2000;
- case MBlaze::RPVR1 : return 0x2001;
- case MBlaze::RPVR2 : return 0x2002;
- case MBlaze::RPVR3 : return 0x2003;
- case MBlaze::RPVR4 : return 0x2004;
- case MBlaze::RPVR5 : return 0x2005;
- case MBlaze::RPVR6 : return 0x2006;
- case MBlaze::RPVR7 : return 0x2007;
- case MBlaze::RPVR8 : return 0x2008;
- case MBlaze::RPVR9 : return 0x2009;
- case MBlaze::RPVR10 : return 0x200A;
- case MBlaze::RPVR11 : return 0x200B;
- default: llvm_unreachable("Unknown register number!");
- }
- return 0; // Not reached
-}
-
-/// getRegisterFromNumbering - Given the enum value for some register, e.g.
-/// MBlaze::R0, return the number that it corresponds to (e.g. 0).
-unsigned MBlazeRegisterInfo::getRegisterFromNumbering(unsigned Reg) {
- switch (Reg) {
- case 0 : return MBlaze::R0;
- case 1 : return MBlaze::R1;
- case 2 : return MBlaze::R2;
- case 3 : return MBlaze::R3;
- case 4 : return MBlaze::R4;
- case 5 : return MBlaze::R5;
- case 6 : return MBlaze::R6;
- case 7 : return MBlaze::R7;
- case 8 : return MBlaze::R8;
- case 9 : return MBlaze::R9;
- case 10 : return MBlaze::R10;
- case 11 : return MBlaze::R11;
- case 12 : return MBlaze::R12;
- case 13 : return MBlaze::R13;
- case 14 : return MBlaze::R14;
- case 15 : return MBlaze::R15;
- case 16 : return MBlaze::R16;
- case 17 : return MBlaze::R17;
- case 18 : return MBlaze::R18;
- case 19 : return MBlaze::R19;
- case 20 : return MBlaze::R20;
- case 21 : return MBlaze::R21;
- case 22 : return MBlaze::R22;
- case 23 : return MBlaze::R23;
- case 24 : return MBlaze::R24;
- case 25 : return MBlaze::R25;
- case 26 : return MBlaze::R26;
- case 27 : return MBlaze::R27;
- case 28 : return MBlaze::R28;
- case 29 : return MBlaze::R29;
- case 30 : return MBlaze::R30;
- case 31 : return MBlaze::R31;
- default: llvm_unreachable("Unknown register number!");
- }
- return 0; // Not reached
-}
-
-unsigned MBlazeRegisterInfo::getSpecialRegisterFromNumbering(unsigned Reg) {
- switch (Reg) {
- case 0x0000 : return MBlaze::RPC;
- case 0x0001 : return MBlaze::RMSR;
- case 0x0003 : return MBlaze::REAR;
- case 0x0005 : return MBlaze::RESR;
- case 0x0007 : return MBlaze::RFSR;
- case 0x000B : return MBlaze::RBTR;
- case 0x000D : return MBlaze::REDR;
- case 0x1000 : return MBlaze::RPID;
- case 0x1001 : return MBlaze::RZPR;
- case 0x1002 : return MBlaze::RTLBX;
- case 0x1003 : return MBlaze::RTLBLO;
- case 0x1004 : return MBlaze::RTLBHI;
- case 0x2000 : return MBlaze::RPVR0;
- case 0x2001 : return MBlaze::RPVR1;
- case 0x2002 : return MBlaze::RPVR2;
- case 0x2003 : return MBlaze::RPVR3;
- case 0x2004 : return MBlaze::RPVR4;
- case 0x2005 : return MBlaze::RPVR5;
- case 0x2006 : return MBlaze::RPVR6;
- case 0x2007 : return MBlaze::RPVR7;
- case 0x2008 : return MBlaze::RPVR8;
- case 0x2009 : return MBlaze::RPVR9;
- case 0x200A : return MBlaze::RPVR10;
- case 0x200B : return MBlaze::RPVR11;
- default: llvm_unreachable("Unknown register number!");
- }
- return 0; // Not reached
-}
-
-bool MBlazeRegisterInfo::isRegister(unsigned Reg) {
- return Reg <= 31;
-}
-
-bool MBlazeRegisterInfo::isSpecialRegister(unsigned Reg) {
- switch (Reg) {
- case 0x0000 : case 0x0001 : case 0x0003 : case 0x0005 :
- case 0x0007 : case 0x000B : case 0x000D : case 0x1000 :
- case 0x1001 : case 0x1002 : case 0x1003 : case 0x1004 :
- case 0x2000 : case 0x2001 : case 0x2002 : case 0x2003 :
- case 0x2004 : case 0x2005 : case 0x2006 : case 0x2007 :
- case 0x2008 : case 0x2009 : case 0x200A : case 0x200B :
- return true;
-
- default:
- return false;
- }
- return false; // Not reached
-}
-
unsigned MBlazeRegisterInfo::getPICCallReg() {
return MBlaze::R20;
}
Modified: llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeRegisterInfo.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeRegisterInfo.h (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeRegisterInfo.h Mon Jul 25 20:29:47 2011
@@ -42,14 +42,6 @@
MBlazeRegisterInfo(const MBlazeSubtarget &Subtarget,
const TargetInstrInfo &tii);
- /// getRegisterNumbering - Given the enum value for some register, e.g.
- /// MBlaze::RA, return the number that it corresponds to (e.g. 31).
- static unsigned getRegisterNumbering(unsigned RegEnum);
- static unsigned getRegisterFromNumbering(unsigned RegEnum);
- static unsigned getSpecialRegisterFromNumbering(unsigned RegEnum);
- static bool isRegister(unsigned RegEnum);
- static bool isSpecialRegister(unsigned RegEnum);
-
/// Get PIC indirect call register
static unsigned getPICCallReg();
Modified: llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeTargetMachine.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeTargetMachine.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MBlazeTargetMachine.cpp Mon Jul 25 20:29:47 2011
@@ -20,44 +20,9 @@
#include "llvm/Target/TargetRegistry.h"
using namespace llvm;
-static MCStreamer *createMCStreamer(const Target &T, const std::string &TT,
- MCContext &Ctx, TargetAsmBackend &TAB,
- raw_ostream &_OS,
- MCCodeEmitter *_Emitter,
- bool RelaxAll,
- bool NoExecStack) {
- Triple TheTriple(TT);
-
- if (TheTriple.isOSDarwin()) {
- llvm_unreachable("MBlaze does not support Darwin MACH-O format");
- return NULL;
- }
-
- if (TheTriple.isOSWindows()) {
- llvm_unreachable("MBlaze does not support Windows COFF format");
- return NULL;
- }
-
- return createELFStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll, NoExecStack);
-}
-
-
extern "C" void LLVMInitializeMBlazeTarget() {
// Register the target.
RegisterTargetMachine<MBlazeTargetMachine> X(TheMBlazeTarget);
-
- // Register the MC code emitter
- TargetRegistry::RegisterCodeEmitter(TheMBlazeTarget,
- llvm::createMBlazeMCCodeEmitter);
-
- // Register the asm backend
- TargetRegistry::RegisterAsmBackend(TheMBlazeTarget,
- createMBlazeAsmBackend);
-
- // Register the object streamer
- TargetRegistry::RegisterObjectStreamer(TheMBlazeTarget,
- createMCStreamer);
-
}
// DataLayout --> Big-endian, 32-bit pointer/ABI/alignment
Modified: llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MCTargetDesc/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MCTargetDesc/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MCTargetDesc/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MCTargetDesc/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -1,4 +1,7 @@
add_llvm_library(LLVMMBlazeDesc
- MBlazeMCTargetDesc.cpp
+ MBlazeAsmBackend.cpp
MBlazeMCAsmInfo.cpp
+ MBlazeMCCodeEmitter.cpp
+ MBlazeMCTargetDesc.cpp
)
+add_dependencies(LLVMMBlazeDesc MBlazeCommonTableGen)
Modified: llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp Mon Jul 25 20:29:47 2011
@@ -13,10 +13,13 @@
#include "MBlazeMCTargetDesc.h"
#include "MBlazeMCAsmInfo.h"
+#include "InstPrinter/MBlazeInstPrinter.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Target/TargetRegistry.h"
+#include "llvm/Support/ErrorHandling.h"
#define GET_INSTRINFO_MC_DESC
#include "MBlazeGenInstrInfo.inc"
@@ -68,6 +71,35 @@
return X;
}
+static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
+ MCContext &Ctx, MCAsmBackend &MAB,
+ raw_ostream &_OS,
+ MCCodeEmitter *_Emitter,
+ bool RelaxAll,
+ bool NoExecStack) {
+ Triple TheTriple(TT);
+
+ if (TheTriple.isOSDarwin()) {
+ llvm_unreachable("MBlaze does not support Darwin MACH-O format");
+ return NULL;
+ }
+
+ if (TheTriple.isOSWindows()) {
+ llvm_unreachable("MBlaze does not support Windows COFF format");
+ return NULL;
+ }
+
+ return createELFStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll, NoExecStack);
+}
+
+static MCInstPrinter *createMBlazeMCInstPrinter(const Target &T,
+ unsigned SyntaxVariant,
+ const MCAsmInfo &MAI) {
+ if (SyntaxVariant == 0)
+ return new MBlazeInstPrinter(MAI);
+ return 0;
+}
+
// Force static initialization.
extern "C" void LLVMInitializeMBlazeTargetMC() {
// Register the MC asm info.
@@ -87,4 +119,20 @@
// Register the MC subtarget info.
TargetRegistry::RegisterMCSubtargetInfo(TheMBlazeTarget,
createMBlazeMCSubtargetInfo);
+
+ // Register the MC code emitter
+ TargetRegistry::RegisterMCCodeEmitter(TheMBlazeTarget,
+ llvm::createMBlazeMCCodeEmitter);
+
+ // Register the asm backend
+ TargetRegistry::RegisterMCAsmBackend(TheMBlazeTarget,
+ createMBlazeAsmBackend);
+
+ // Register the object streamer
+ TargetRegistry::RegisterMCObjectStreamer(TheMBlazeTarget,
+ createMCStreamer);
+
+ // Register the MCInstPrinter.
+ TargetRegistry::RegisterMCInstPrinter(TheMBlazeTarget,
+ createMBlazeMCInstPrinter);
}
Modified: llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.h (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.h Mon Jul 25 20:29:47 2011
@@ -15,12 +15,23 @@
#define MBLAZEMCTARGETDESC_H
namespace llvm {
+class MCAsmBackend;
+class MCContext;
+class MCCodeEmitter;
+class MCInstrInfo;
class MCSubtargetInfo;
class Target;
class StringRef;
+class formatted_raw_ostream;
extern Target TheMBlazeTarget;
+MCCodeEmitter *createMBlazeMCCodeEmitter(const MCInstrInfo &MCII,
+ const MCSubtargetInfo &STI,
+ MCContext &Ctx);
+
+MCAsmBackend *createMBlazeAsmBackend(const Target &T, StringRef TT);
+
} // End llvm namespace
// Defines symbolic names for MBlaze registers. This defines a mapping from
Modified: llvm/branches/exception-handling-rewrite/lib/Target/MSP430/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/MSP430/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/MSP430/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/MSP430/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -6,6 +6,7 @@
tablegen(MSP430GenDAGISel.inc -gen-dag-isel)
tablegen(MSP430GenCallingConv.inc -gen-callingconv)
tablegen(MSP430GenSubtargetInfo.inc -gen-subtarget)
+add_public_tablegen_target(MSP430CommonTableGen)
add_llvm_target(MSP430CodeGen
MSP430BranchSelector.cpp
Modified: llvm/branches/exception-handling-rewrite/lib/Target/MSP430/InstPrinter/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/MSP430/InstPrinter/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/MSP430/InstPrinter/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/MSP430/InstPrinter/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -3,4 +3,4 @@
add_llvm_library(LLVMMSP430AsmPrinter
MSP430InstPrinter.cpp
)
-add_dependencies(LLVMMSP430AsmPrinter MSP430CodeGenTable_gen)
+add_dependencies(LLVMMSP430AsmPrinter MSP430CommonTableGen)
Modified: llvm/branches/exception-handling-rewrite/lib/Target/MSP430/MCTargetDesc/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/MSP430/MCTargetDesc/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/MSP430/MCTargetDesc/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/MSP430/MCTargetDesc/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -2,3 +2,4 @@
MSP430MCTargetDesc.cpp
MSP430MCAsmInfo.cpp
)
+add_dependencies(LLVMMSP430Desc MSP430CommonTableGen)
Modified: llvm/branches/exception-handling-rewrite/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp Mon Jul 25 20:29:47 2011
@@ -13,6 +13,7 @@
#include "MSP430MCTargetDesc.h"
#include "MSP430MCAsmInfo.h"
+#include "InstPrinter/MSP430InstPrinter.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
@@ -55,6 +56,14 @@
return X;
}
+static MCInstPrinter *createMSP430MCInstPrinter(const Target &T,
+ unsigned SyntaxVariant,
+ const MCAsmInfo &MAI) {
+ if (SyntaxVariant == 0)
+ return new MSP430InstPrinter(MAI);
+ return 0;
+}
+
extern "C" void LLVMInitializeMSP430TargetMC() {
// Register the MC asm info.
RegisterMCAsmInfo<MSP430MCAsmInfo> X(TheMSP430Target);
@@ -73,4 +82,8 @@
// Register the MC subtarget info.
TargetRegistry::RegisterMCSubtargetInfo(TheMSP430Target,
createMSP430MCSubtargetInfo);
+
+ // Register the MCInstPrinter.
+ TargetRegistry::RegisterMCInstPrinter(TheMSP430Target,
+ createMSP430MCInstPrinter);
}
Modified: llvm/branches/exception-handling-rewrite/lib/Target/MSP430/MSP430AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/MSP430/MSP430AsmPrinter.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/MSP430/MSP430AsmPrinter.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/MSP430/MSP430AsmPrinter.cpp Mon Jul 25 20:29:47 2011
@@ -163,17 +163,7 @@
OutStreamer.EmitInstruction(TmpInst);
}
-static MCInstPrinter *createMSP430MCInstPrinter(const Target &T,
- unsigned SyntaxVariant,
- const MCAsmInfo &MAI) {
- if (SyntaxVariant == 0)
- return new MSP430InstPrinter(MAI);
- return 0;
-}
-
// Force static initialization.
extern "C" void LLVMInitializeMSP430AsmPrinter() {
RegisterAsmPrinter<MSP430AsmPrinter> X(TheMSP430Target);
- TargetRegistry::RegisterMCInstPrinter(TheMSP430Target,
- createMSP430MCInstPrinter);
}
Modified: llvm/branches/exception-handling-rewrite/lib/Target/Mips/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/Mips/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/Mips/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/Mips/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -6,6 +6,7 @@
tablegen(MipsGenDAGISel.inc -gen-dag-isel)
tablegen(MipsGenCallingConv.inc -gen-callingconv)
tablegen(MipsGenSubtargetInfo.inc -gen-subtarget)
+add_public_tablegen_target(MipsCommonTableGen)
add_llvm_target(MipsCodeGen
MipsAsmPrinter.cpp
Modified: llvm/branches/exception-handling-rewrite/lib/Target/Mips/InstPrinter/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/Mips/InstPrinter/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/Mips/InstPrinter/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/Mips/InstPrinter/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -3,4 +3,4 @@
add_llvm_library(LLVMMipsAsmPrinter
MipsInstPrinter.cpp
)
-add_dependencies(LLVMMipsAsmPrinter MipsCodeGenTable_gen)
+add_dependencies(LLVMMipsAsmPrinter MipsCommonTableGen)
Modified: llvm/branches/exception-handling-rewrite/lib/Target/Mips/MCTargetDesc/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/Mips/MCTargetDesc/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/Mips/MCTargetDesc/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/Mips/MCTargetDesc/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -2,3 +2,4 @@
MipsMCTargetDesc.cpp
MipsMCAsmInfo.cpp
)
+add_dependencies(LLVMMipsDesc MipsCommonTableGen)
Modified: llvm/branches/exception-handling-rewrite/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp Mon Jul 25 20:29:47 2011
@@ -13,6 +13,7 @@
#include "MipsMCTargetDesc.h"
#include "MipsMCAsmInfo.h"
+#include "InstPrinter/MipsInstPrinter.h"
#include "llvm/MC/MachineLocation.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
@@ -74,6 +75,12 @@
return X;
}
+static MCInstPrinter *createMipsMCInstPrinter(const Target &T,
+ unsigned SyntaxVariant,
+ const MCAsmInfo &MAI) {
+ return new MipsInstPrinter(MAI);
+}
+
extern "C" void LLVMInitializeMipsTargetMC() {
// Register the MC asm info.
RegisterMCAsmInfoFn X(TheMipsTarget, createMipsMCAsmInfo);
@@ -95,4 +102,10 @@
// Register the MC subtarget info.
TargetRegistry::RegisterMCSubtargetInfo(TheMipsTarget,
createMipsMCSubtargetInfo);
+
+ // Register the MCInstPrinter.
+ TargetRegistry::RegisterMCInstPrinter(TheMipsTarget,
+ createMipsMCInstPrinter);
+ TargetRegistry::RegisterMCInstPrinter(TheMipselTarget,
+ createMipsMCInstPrinter);
}
Modified: llvm/branches/exception-handling-rewrite/lib/Target/Mips/MipsAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/Mips/MipsAsmPrinter.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/Mips/MipsAsmPrinter.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/Mips/MipsAsmPrinter.cpp Mon Jul 25 20:29:47 2011
@@ -424,17 +424,7 @@
}
// Force static initialization.
-static MCInstPrinter *createMipsMCInstPrinter(const Target &T,
- unsigned SyntaxVariant,
- const MCAsmInfo &MAI) {
- return new MipsInstPrinter(MAI);
-}
-
extern "C" void LLVMInitializeMipsAsmPrinter() {
RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget);
RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget);
-
- TargetRegistry::RegisterMCInstPrinter(TheMipsTarget, createMipsMCInstPrinter);
- TargetRegistry::RegisterMCInstPrinter(TheMipselTarget,
- createMipsMCInstPrinter);
}
Modified: llvm/branches/exception-handling-rewrite/lib/Target/PTX/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/PTX/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/PTX/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/PTX/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -6,6 +6,7 @@
tablegen(PTXGenInstrInfo.inc -gen-instr-info)
tablegen(PTXGenRegisterInfo.inc -gen-register-info)
tablegen(PTXGenSubtargetInfo.inc -gen-subtarget)
+add_public_tablegen_target(PTXCommonTableGen)
add_llvm_target(PTXCodeGen
PTXAsmPrinter.cpp
Modified: llvm/branches/exception-handling-rewrite/lib/Target/PTX/MCTargetDesc/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/PTX/MCTargetDesc/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/PTX/MCTargetDesc/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/PTX/MCTargetDesc/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -2,3 +2,4 @@
PTXMCTargetDesc.cpp
PTXMCAsmInfo.cpp
)
+add_dependencies(LLVMPTXDesc PTXCommonTableGen)
Modified: llvm/branches/exception-handling-rewrite/lib/Target/PTX/PTXMCAsmStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/PTX/PTXMCAsmStreamer.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/PTX/PTXMCAsmStreamer.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/PTX/PTXMCAsmStreamer.cpp Mon Jul 25 20:29:47 2011
@@ -533,7 +533,7 @@
formatted_raw_ostream &OS,
bool isVerboseAsm, bool useLoc, bool useCFI,
MCInstPrinter *IP,
- MCCodeEmitter *CE, TargetAsmBackend *TAB,
+ MCCodeEmitter *CE, MCAsmBackend *MAB,
bool ShowInst) {
return new PTXMCAsmStreamer(Context, OS, isVerboseAsm, useLoc,
IP, CE, ShowInst);
Modified: llvm/branches/exception-handling-rewrite/lib/Target/PTX/PTXTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/PTX/PTXTargetMachine.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/PTX/PTXTargetMachine.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/PTX/PTXTargetMachine.cpp Mon Jul 25 20:29:47 2011
@@ -25,7 +25,7 @@
bool useCFI,
MCInstPrinter *InstPrint,
MCCodeEmitter *CE,
- TargetAsmBackend *TAB,
+ MCAsmBackend *MAB,
bool ShowInst);
}
Modified: llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -8,9 +8,9 @@
tablegen(PPCGenDAGISel.inc -gen-dag-isel)
tablegen(PPCGenCallingConv.inc -gen-callingconv)
tablegen(PPCGenSubtargetInfo.inc -gen-subtarget)
+add_public_tablegen_target(PowerPCCommonTableGen)
add_llvm_target(PowerPCCodeGen
- PPCAsmBackend.cpp
PPCAsmPrinter.cpp
PPCBranchSelector.cpp
PPCCodeEmitter.cpp
@@ -20,9 +20,7 @@
PPCISelLowering.cpp
PPCFrameLowering.cpp
PPCJITInfo.cpp
- PPCMCCodeEmitter.cpp
PPCMCInstLower.cpp
- PPCPredicates.cpp
PPCRegisterInfo.cpp
PPCSubtarget.cpp
PPCTargetMachine.cpp
Modified: llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/InstPrinter/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/InstPrinter/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/InstPrinter/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/InstPrinter/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -3,4 +3,4 @@
add_llvm_library(LLVMPowerPCAsmPrinter
PPCInstPrinter.cpp
)
-add_dependencies(LLVMPowerPCAsmPrinter PowerPCCodeGenTable_gen)
+add_dependencies(LLVMPowerPCAsmPrinter PowerPCCommonTableGen)
Modified: llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp Mon Jul 25 20:29:47 2011
@@ -13,7 +13,8 @@
#define DEBUG_TYPE "asm-printer"
#include "PPCInstPrinter.h"
-#include "PPCPredicates.h"
+#include "MCTargetDesc/PPCBaseInfo.h"
+#include "MCTargetDesc/PPCPredicates.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/Support/raw_ostream.h"
Modified: llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -1,4 +1,8 @@
add_llvm_library(LLVMPowerPCDesc
+ PPCAsmBackend.cpp
PPCMCTargetDesc.cpp
PPCMCAsmInfo.cpp
+ PPCMCCodeEmitter.cpp
+ PPCPredicates.cpp
)
+add_dependencies(LLVMPowerPCDesc PowerPCCommonTableGen)
Modified: llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp Mon Jul 25 20:29:47 2011
@@ -13,9 +13,11 @@
#include "PPCMCTargetDesc.h"
#include "PPCMCAsmInfo.h"
+#include "InstPrinter/PPCInstPrinter.h"
#include "llvm/MC/MachineLocation.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Target/TargetRegistry.h"
@@ -87,6 +89,25 @@
return X;
}
+// This is duplicated code. Refactor this.
+static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
+ MCContext &Ctx, MCAsmBackend &MAB,
+ raw_ostream &OS,
+ MCCodeEmitter *Emitter,
+ bool RelaxAll,
+ bool NoExecStack) {
+ if (Triple(TT).isOSDarwin())
+ return createMachOStreamer(Ctx, MAB, OS, Emitter, RelaxAll);
+
+ return NULL;
+}
+
+static MCInstPrinter *createPPCMCInstPrinter(const Target &T,
+ unsigned SyntaxVariant,
+ const MCAsmInfo &MAI) {
+ return new PPCInstPrinter(MAI, SyntaxVariant);
+}
+
extern "C" void LLVMInitializePowerPCTargetMC() {
// Register the MC asm info.
RegisterMCAsmInfoFn C(ThePPC32Target, createPPCMCAsmInfo);
@@ -109,4 +130,20 @@
createPPCMCSubtargetInfo);
TargetRegistry::RegisterMCSubtargetInfo(ThePPC64Target,
createPPCMCSubtargetInfo);
+
+ // Register the MC Code Emitter
+ TargetRegistry::RegisterMCCodeEmitter(ThePPC32Target, createPPCMCCodeEmitter);
+ TargetRegistry::RegisterMCCodeEmitter(ThePPC64Target, createPPCMCCodeEmitter);
+
+ // Register the asm backend.
+ TargetRegistry::RegisterMCAsmBackend(ThePPC32Target, createPPCAsmBackend);
+ TargetRegistry::RegisterMCAsmBackend(ThePPC64Target, createPPCAsmBackend);
+
+ // Register the object streamer.
+ TargetRegistry::RegisterMCObjectStreamer(ThePPC32Target, createMCStreamer);
+ TargetRegistry::RegisterMCObjectStreamer(ThePPC64Target, createMCStreamer);
+
+ // Register the MCInstPrinter.
+ TargetRegistry::RegisterMCInstPrinter(ThePPC32Target, createPPCMCInstPrinter);
+ TargetRegistry::RegisterMCInstPrinter(ThePPC64Target, createPPCMCInstPrinter);
}
Modified: llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h Mon Jul 25 20:29:47 2011
@@ -15,6 +15,10 @@
#define PPCMCTARGETDESC_H
namespace llvm {
+class MCAsmBackend;
+class MCCodeEmitter;
+class MCContext;
+class MCInstrInfo;
class MCSubtargetInfo;
class Target;
class StringRef;
@@ -22,6 +26,12 @@
extern Target ThePPC32Target;
extern Target ThePPC64Target;
+MCCodeEmitter *createPPCMCCodeEmitter(const MCInstrInfo &MCII,
+ const MCSubtargetInfo &STI,
+ MCContext &Ctx);
+
+MCAsmBackend *createPPCAsmBackend(const Target &T, StringRef TT);
+
} // End llvm namespace
// Defines symbolic names for PowerPC registers. This defines a mapping from
Modified: llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPC.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPC.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPC.h (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPC.h Mon Jul 25 20:29:47 2011
@@ -15,6 +15,7 @@
#ifndef LLVM_TARGET_POWERPC_H
#define LLVM_TARGET_POWERPC_H
+#include "MCTargetDesc/PPCBaseInfo.h"
#include "MCTargetDesc/PPCMCTargetDesc.h"
#include <string>
@@ -30,22 +31,12 @@
class MachineInstr;
class AsmPrinter;
class MCInst;
- class MCCodeEmitter;
- class MCContext;
- class MCInstrInfo;
- class MCSubtargetInfo;
class TargetMachine;
- class TargetAsmBackend;
FunctionPass *createPPCBranchSelectionPass();
FunctionPass *createPPCISelDag(PPCTargetMachine &TM);
FunctionPass *createPPCJITCodeEmitterPass(PPCTargetMachine &TM,
JITCodeEmitter &MCE);
- MCCodeEmitter *createPPCMCCodeEmitter(const MCInstrInfo &MCII,
- const MCSubtargetInfo &STI,
- MCContext &Ctx);
- TargetAsmBackend *createPPCAsmBackend(const Target &, const std::string &);
-
void LowerPPCMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
AsmPrinter &AP, bool isDarwin);
Removed: llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCAsmBackend.cpp?rev=136039&view=auto
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCAsmBackend.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCAsmBackend.cpp (removed)
@@ -1,123 +0,0 @@
-//===-- PPCAsmBackend.cpp - PPC Assembler Backend -------------------------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#include "llvm/MC/TargetAsmBackend.h"
-#include "PPC.h"
-#include "PPCFixupKinds.h"
-#include "llvm/MC/MCMachObjectWriter.h"
-#include "llvm/MC/MCSectionMachO.h"
-#include "llvm/MC/MCObjectWriter.h"
-#include "llvm/MC/MCValue.h"
-#include "llvm/Object/MachOFormat.h"
-#include "llvm/Target/TargetRegistry.h"
-using namespace llvm;
-
-namespace {
-class PPCMachObjectWriter : public MCMachObjectTargetWriter {
-public:
- PPCMachObjectWriter(bool Is64Bit, uint32_t CPUType,
- uint32_t CPUSubtype)
- : MCMachObjectTargetWriter(Is64Bit, CPUType, CPUSubtype) {}
-
- void RecordRelocation(MachObjectWriter *Writer,
- const MCAssembler &Asm, const MCAsmLayout &Layout,
- const MCFragment *Fragment, const MCFixup &Fixup,
- MCValue Target, uint64_t &FixedValue) {}
-};
-
-class PPCAsmBackend : public TargetAsmBackend {
-const Target &TheTarget;
-public:
- PPCAsmBackend(const Target &T) : TargetAsmBackend(), TheTarget(T) {}
-
- unsigned getNumFixupKinds() const { return PPC::NumTargetFixupKinds; }
-
- const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
- const static MCFixupKindInfo Infos[PPC::NumTargetFixupKinds] = {
- // name offset bits flags
- { "fixup_ppc_br24", 6, 24, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_ppc_brcond14", 16, 14, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_ppc_lo16", 16, 16, 0 },
- { "fixup_ppc_ha16", 16, 16, 0 },
- { "fixup_ppc_lo14", 16, 14, 0 }
- };
-
- if (Kind < FirstTargetFixupKind)
- return TargetAsmBackend::getFixupKindInfo(Kind);
-
- assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
- "Invalid kind!");
- return Infos[Kind - FirstTargetFixupKind];
- }
-
- bool MayNeedRelaxation(const MCInst &Inst) const {
- // FIXME.
- return false;
- }
-
- void RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
- // FIXME.
- assert(0 && "RelaxInstruction() unimplemented");
- }
-
- bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
- // FIXME: Zero fill for now. That's not right, but at least will get the
- // section size right.
- for (uint64_t i = 0; i != Count; ++i)
- OW->Write8(0);
- return true;
- }
-
- unsigned getPointerSize() const {
- StringRef Name = TheTarget.getName();
- if (Name == "ppc64") return 8;
- assert(Name == "ppc32" && "Unknown target name!");
- return 4;
- }
-};
-} // end anonymous namespace
-
-
-// FIXME: This should be in a separate file.
-namespace {
- class DarwinPPCAsmBackend : public PPCAsmBackend {
- public:
- DarwinPPCAsmBackend(const Target &T) : PPCAsmBackend(T) { }
-
- void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
- uint64_t Value) const {
- assert(0 && "UNIMP");
- }
-
- MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
- bool is64 = getPointerSize() == 8;
- return createMachObjectWriter(new PPCMachObjectWriter(
- /*Is64Bit=*/is64,
- (is64 ? object::mach::CTM_PowerPC64 :
- object::mach::CTM_PowerPC),
- object::mach::CSPPC_ALL),
- OS, /*IsLittleEndian=*/false);
- }
-
- virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
- return false;
- }
- };
-} // end anonymous namespace
-
-
-
-
-TargetAsmBackend *llvm::createPPCAsmBackend(const Target &T,
- const std::string &TT) {
- if (Triple(TT).isOSDarwin())
- return new DarwinPPCAsmBackend(T);
-
- return 0;
-}
Modified: llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCAsmPrinter.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCAsmPrinter.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCAsmPrinter.cpp Mon Jul 25 20:29:47 2011
@@ -18,9 +18,9 @@
#define DEBUG_TYPE "asmprinter"
#include "PPC.h"
-#include "PPCPredicates.h"
#include "PPCTargetMachine.h"
#include "PPCSubtarget.h"
+#include "MCTargetDesc/PPCPredicates.h"
#include "llvm/Analysis/DebugInfo.h"
#include "llvm/Constants.h"
#include "llvm/DerivedTypes.h"
@@ -679,18 +679,8 @@
return new PPCLinuxAsmPrinter(tm, Streamer);
}
-static MCInstPrinter *createPPCMCInstPrinter(const Target &T,
- unsigned SyntaxVariant,
- const MCAsmInfo &MAI) {
- return new PPCInstPrinter(MAI, SyntaxVariant);
-}
-
-
// Force static initialization.
extern "C" void LLVMInitializePowerPCAsmPrinter() {
TargetRegistry::RegisterAsmPrinter(ThePPC32Target, createPPCAsmPrinterPass);
TargetRegistry::RegisterAsmPrinter(ThePPC64Target, createPPCAsmPrinterPass);
-
- TargetRegistry::RegisterMCInstPrinter(ThePPC32Target, createPPCMCInstPrinter);
- TargetRegistry::RegisterMCInstPrinter(ThePPC64Target, createPPCMCInstPrinter);
}
Modified: llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCBranchSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCBranchSelector.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCBranchSelector.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCBranchSelector.cpp Mon Jul 25 20:29:47 2011
@@ -19,7 +19,7 @@
#include "PPC.h"
#include "PPCInstrBuilder.h"
#include "PPCInstrInfo.h"
-#include "PPCPredicates.h"
+#include "MCTargetDesc/PPCPredicates.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/ADT/Statistic.h"
Modified: llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCCodeEmitter.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCCodeEmitter.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCCodeEmitter.cpp Mon Jul 25 20:29:47 2011
@@ -140,7 +140,7 @@
const MachineOperand &MO = MI.getOperand(OpNo);
assert((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MFOCRF) &&
(MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
- return 0x80 >> PPCRegisterInfo::getRegisterNumbering(MO.getReg());
+ return 0x80 >> getPPCRegisterNumbering(MO.getReg());
}
MachineRelocation PPCCodeEmitter::GetRelocation(const MachineOperand &MO,
@@ -250,7 +250,7 @@
// The GPR operand should come through here though.
assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF) ||
MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
- return PPCRegisterInfo::getRegisterNumbering(MO.getReg());
+ return getPPCRegisterNumbering(MO.getReg());
}
assert(MO.isImm() &&
Removed: llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCFixupKinds.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCFixupKinds.h?rev=136039&view=auto
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCFixupKinds.h (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCFixupKinds.h (removed)
@@ -1,45 +0,0 @@
-//===-- PPCFixupKinds.h - PPC Specific Fixup Entries ------------*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_PPC_PPCFIXUPKINDS_H
-#define LLVM_PPC_PPCFIXUPKINDS_H
-
-#include "llvm/MC/MCFixup.h"
-
-namespace llvm {
-namespace PPC {
-enum Fixups {
- // fixup_ppc_br24 - 24-bit PC relative relocation for direct branches like 'b'
- // and 'bl'.
- fixup_ppc_br24 = FirstTargetFixupKind,
-
- /// fixup_ppc_brcond14 - 14-bit PC relative relocation for conditional
- /// branches.
- fixup_ppc_brcond14,
-
- /// fixup_ppc_lo16 - A 16-bit fixup corresponding to lo16(_foo) for instrs
- /// like 'li'.
- fixup_ppc_lo16,
-
- /// fixup_ppc_ha16 - A 16-bit fixup corresponding to ha16(_foo) for instrs
- /// like 'lis'.
- fixup_ppc_ha16,
-
- /// fixup_ppc_lo14 - A 14-bit fixup corresponding to lo16(_foo) for instrs
- /// like 'std'.
- fixup_ppc_lo14,
-
- // Marker
- LastTargetFixupKind,
- NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
-};
-}
-}
-
-#endif
Modified: llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCFrameLowering.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCFrameLowering.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCFrameLowering.cpp Mon Jul 25 20:29:47 2011
@@ -109,14 +109,14 @@
for (MachineRegisterInfo::livein_iterator
I = MF->getRegInfo().livein_begin(),
E = MF->getRegInfo().livein_end(); I != E; ++I) {
- unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first);
+ unsigned RegNo = getPPCRegisterNumbering(I->first);
if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
}
for (MachineRegisterInfo::liveout_iterator
I = MF->getRegInfo().liveout_begin(),
E = MF->getRegInfo().liveout_end(); I != E; ++I) {
- unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I);
+ unsigned RegNo = getPPCRegisterNumbering(*I);
if (VRRegNo[RegNo] == *I) // If this really is a vector reg.
UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
}
@@ -878,7 +878,7 @@
FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
}
- LowerBound -= (31 - PPCRegisterInfo::getRegisterNumbering(MinFPR) + 1) * 8;
+ LowerBound -= (31 - getPPCRegisterNumbering(MinFPR) + 1) * 8;
}
// Check whether the frame pointer register is allocated. If so, make sure it
@@ -912,8 +912,8 @@
}
unsigned MinReg =
- std::min<unsigned>(PPCRegisterInfo::getRegisterNumbering(MinGPR),
- PPCRegisterInfo::getRegisterNumbering(MinG8R));
+ std::min<unsigned>(getPPCRegisterNumbering(MinGPR),
+ getPPCRegisterNumbering(MinG8R));
if (Subtarget.isPPC64()) {
LowerBound -= (31 - MinReg + 1) * 8;
Modified: llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Mon Jul 25 20:29:47 2011
@@ -14,8 +14,8 @@
#define DEBUG_TYPE "ppc-codegen"
#include "PPC.h"
-#include "PPCPredicates.h"
#include "PPCTargetMachine.h"
+#include "MCTargetDesc/PPCPredicates.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionAnalysis.h"
Modified: llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCISelLowering.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCISelLowering.cpp Mon Jul 25 20:29:47 2011
@@ -14,8 +14,8 @@
#include "PPCISelLowering.h"
#include "PPCMachineFunctionInfo.h"
#include "PPCPerfectShuffle.h"
-#include "PPCPredicates.h"
#include "PPCTargetMachine.h"
+#include "MCTargetDesc/PPCPredicates.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/VectorExtras.h"
#include "llvm/CodeGen/CallingConvLower.h"
Modified: llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCInstrInfo.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCInstrInfo.cpp Mon Jul 25 20:29:47 2011
@@ -15,9 +15,9 @@
#include "PPC.h"
#include "PPCInstrBuilder.h"
#include "PPCMachineFunctionInfo.h"
-#include "PPCPredicates.h"
#include "PPCTargetMachine.h"
#include "PPCHazardRecognizers.h"
+#include "MCTargetDesc/PPCPredicates.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
@@ -402,7 +402,7 @@
// If the saved register wasn't CR0, shift the bits left so that they are
// in CR0's slot.
if (SrcReg != PPC::CR0) {
- unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
+ unsigned ShiftBits = getPPCRegisterNumbering(SrcReg)*4;
// rlwinm scratch, scratch, ShiftBits, 0, 31.
NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
.addReg(ScratchReg).addImm(ShiftBits)
@@ -537,7 +537,7 @@
// If the reloaded register isn't CR0, shift the bits right so that they are
// in the right CR's slot.
if (DestReg != PPC::CR0) {
- unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
+ unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4;
// rlwinm r11, r11, 32-ShiftBits, 0, 31.
NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
.addReg(ScratchReg).addImm(32-ShiftBits).addImm(0)
Removed: llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCMCCodeEmitter.cpp?rev=136039&view=auto
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCMCCodeEmitter.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCMCCodeEmitter.cpp (removed)
@@ -1,194 +0,0 @@
-//===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file implements the PPCMCCodeEmitter class.
-//
-//===----------------------------------------------------------------------===//
-
-#define DEBUG_TYPE "mccodeemitter"
-#include "PPC.h"
-#include "PPCRegisterInfo.h"
-#include "PPCFixupKinds.h"
-#include "llvm/MC/MCCodeEmitter.h"
-#include "llvm/MC/MCInst.h"
-#include "llvm/ADT/Statistic.h"
-#include "llvm/Support/raw_ostream.h"
-#include "llvm/Support/ErrorHandling.h"
-using namespace llvm;
-
-STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
-
-namespace {
-class PPCMCCodeEmitter : public MCCodeEmitter {
- PPCMCCodeEmitter(const PPCMCCodeEmitter &); // DO NOT IMPLEMENT
- void operator=(const PPCMCCodeEmitter &); // DO NOT IMPLEMENT
-
-public:
- PPCMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
- MCContext &ctx) {
- }
-
- ~PPCMCCodeEmitter() {}
-
- unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
- SmallVectorImpl<MCFixup> &Fixups) const;
- unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo,
- SmallVectorImpl<MCFixup> &Fixups) const;
- unsigned getHA16Encoding(const MCInst &MI, unsigned OpNo,
- SmallVectorImpl<MCFixup> &Fixups) const;
- unsigned getLO16Encoding(const MCInst &MI, unsigned OpNo,
- SmallVectorImpl<MCFixup> &Fixups) const;
- unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,
- SmallVectorImpl<MCFixup> &Fixups) const;
- unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
- SmallVectorImpl<MCFixup> &Fixups) const;
- unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
- SmallVectorImpl<MCFixup> &Fixups) const;
-
- /// getMachineOpValue - Return binary encoding of operand. If the machine
- /// operand requires relocation, record the relocation and return zero.
- unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
- SmallVectorImpl<MCFixup> &Fixups) const;
-
- // getBinaryCodeForInstr - TableGen'erated function for getting the
- // binary encoding for an instruction.
- unsigned getBinaryCodeForInstr(const MCInst &MI,
- SmallVectorImpl<MCFixup> &Fixups) const;
- void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
- SmallVectorImpl<MCFixup> &Fixups) const {
- unsigned Bits = getBinaryCodeForInstr(MI, Fixups);
-
- // Output the constant in big endian byte order.
- for (unsigned i = 0; i != 4; ++i) {
- OS << (char)(Bits >> 24);
- Bits <<= 8;
- }
-
- ++MCNumEmitted; // Keep track of the # of mi's emitted.
- }
-
-};
-
-} // end anonymous namespace
-
-MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII,
- const MCSubtargetInfo &STI,
- MCContext &Ctx) {
- return new PPCMCCodeEmitter(MCII, STI, Ctx);
-}
-
-unsigned PPCMCCodeEmitter::
-getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
- SmallVectorImpl<MCFixup> &Fixups) const {
- const MCOperand &MO = MI.getOperand(OpNo);
- if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
-
- // Add a fixup for the branch target.
- Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
- (MCFixupKind)PPC::fixup_ppc_br24));
- return 0;
-}
-
-unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
- SmallVectorImpl<MCFixup> &Fixups) const {
- const MCOperand &MO = MI.getOperand(OpNo);
- if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
-
- // Add a fixup for the branch target.
- Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
- (MCFixupKind)PPC::fixup_ppc_brcond14));
- return 0;
-}
-
-unsigned PPCMCCodeEmitter::getHA16Encoding(const MCInst &MI, unsigned OpNo,
- SmallVectorImpl<MCFixup> &Fixups) const {
- const MCOperand &MO = MI.getOperand(OpNo);
- if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
-
- // Add a fixup for the branch target.
- Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
- (MCFixupKind)PPC::fixup_ppc_ha16));
- return 0;
-}
-
-unsigned PPCMCCodeEmitter::getLO16Encoding(const MCInst &MI, unsigned OpNo,
- SmallVectorImpl<MCFixup> &Fixups) const {
- const MCOperand &MO = MI.getOperand(OpNo);
- if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
-
- // Add a fixup for the branch target.
- Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
- (MCFixupKind)PPC::fixup_ppc_lo16));
- return 0;
-}
-
-unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
- SmallVectorImpl<MCFixup> &Fixups) const {
- // Encode (imm, reg) as a memri, which has the low 16-bits as the
- // displacement and the next 5 bits as the register #.
- assert(MI.getOperand(OpNo+1).isReg());
- unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 16;
-
- const MCOperand &MO = MI.getOperand(OpNo);
- if (MO.isImm())
- return (getMachineOpValue(MI, MO, Fixups) & 0xFFFF) | RegBits;
-
- // Add a fixup for the displacement field.
- Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
- (MCFixupKind)PPC::fixup_ppc_lo16));
- return RegBits;
-}
-
-
-unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
- SmallVectorImpl<MCFixup> &Fixups) const {
- // Encode (imm, reg) as a memrix, which has the low 14-bits as the
- // displacement and the next 5 bits as the register #.
- assert(MI.getOperand(OpNo+1).isReg());
- unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 14;
-
- const MCOperand &MO = MI.getOperand(OpNo);
- if (MO.isImm())
- return (getMachineOpValue(MI, MO, Fixups) & 0x3FFF) | RegBits;
-
- // Add a fixup for the branch target.
- Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
- (MCFixupKind)PPC::fixup_ppc_lo14));
- return RegBits;
-}
-
-
-unsigned PPCMCCodeEmitter::
-get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
- SmallVectorImpl<MCFixup> &Fixups) const {
- const MCOperand &MO = MI.getOperand(OpNo);
- assert((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MFOCRF) &&
- (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
- return 0x80 >> PPCRegisterInfo::getRegisterNumbering(MO.getReg());
-}
-
-
-unsigned PPCMCCodeEmitter::
-getMachineOpValue(const MCInst &MI, const MCOperand &MO,
- SmallVectorImpl<MCFixup> &Fixups) const {
- if (MO.isReg()) {
- // MTCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
- // The GPR operand should come through here though.
- assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF) ||
- MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
- return PPCRegisterInfo::getRegisterNumbering(MO.getReg());
- }
-
- assert(MO.isImm() &&
- "Relocation required in an instruction that we cannot encode!");
- return MO.getImm();
-}
-
-
-#include "PPCGenMCCodeEmitter.inc"
Removed: llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCPredicates.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCPredicates.cpp?rev=136039&view=auto
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCPredicates.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCPredicates.cpp (removed)
@@ -1,31 +0,0 @@
-//===-- PPCPredicates.cpp - PPC Branch Predicate Information --------------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file implements the PowerPC branch predicates.
-//
-//===----------------------------------------------------------------------===//
-
-#include "PPCPredicates.h"
-#include "llvm/Support/ErrorHandling.h"
-#include <cassert>
-using namespace llvm;
-
-PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) {
- switch (Opcode) {
- default: llvm_unreachable("Unknown PPC branch opcode!");
- case PPC::PRED_EQ: return PPC::PRED_NE;
- case PPC::PRED_NE: return PPC::PRED_EQ;
- case PPC::PRED_LT: return PPC::PRED_GE;
- case PPC::PRED_GE: return PPC::PRED_LT;
- case PPC::PRED_GT: return PPC::PRED_LE;
- case PPC::PRED_LE: return PPC::PRED_GT;
- case PPC::PRED_NU: return PPC::PRED_UN;
- case PPC::PRED_UN: return PPC::PRED_NU;
- }
-}
Removed: llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCPredicates.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCPredicates.h?rev=136039&view=auto
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCPredicates.h (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCPredicates.h (removed)
@@ -1,39 +0,0 @@
-//===-- PPCPredicates.h - PPC Branch Predicate Information ------*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file describes the PowerPC branch predicates.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_TARGET_POWERPC_PPCPREDICATES_H
-#define LLVM_TARGET_POWERPC_PPCPREDICATES_H
-
-#include "PPC.h"
-
-namespace llvm {
-namespace PPC {
- /// Predicate - These are "(BI << 5) | BO" for various predicates.
- enum Predicate {
- PRED_ALWAYS = (0 << 5) | 20,
- PRED_LT = (0 << 5) | 12,
- PRED_LE = (1 << 5) | 4,
- PRED_EQ = (2 << 5) | 12,
- PRED_GE = (0 << 5) | 4,
- PRED_GT = (1 << 5) | 12,
- PRED_NE = (2 << 5) | 4,
- PRED_UN = (3 << 5) | 12,
- PRED_NU = (3 << 5) | 4
- };
-
- /// Invert the specified predicate. != -> ==, < -> >=.
- Predicate InvertPredicate(Predicate Opcode);
-}
-}
-
-#endif
Modified: llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCRegisterInfo.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCRegisterInfo.cpp Mon Jul 25 20:29:47 2011
@@ -67,49 +67,6 @@
(EnablePPC64RS && Subtarget.isPPC64()));
}
-/// getRegisterNumbering - Given the enum value for some register, e.g.
-/// PPC::F14, return the number that it corresponds to (e.g. 14).
-unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
- using namespace PPC;
- switch (RegEnum) {
- case 0: return 0;
- case R0 : case X0 : case F0 : case V0 : case CR0: case CR0LT: return 0;
- case R1 : case X1 : case F1 : case V1 : case CR1: case CR0GT: return 1;
- case R2 : case X2 : case F2 : case V2 : case CR2: case CR0EQ: return 2;
- case R3 : case X3 : case F3 : case V3 : case CR3: case CR0UN: return 3;
- case R4 : case X4 : case F4 : case V4 : case CR4: case CR1LT: return 4;
- case R5 : case X5 : case F5 : case V5 : case CR5: case CR1GT: return 5;
- case R6 : case X6 : case F6 : case V6 : case CR6: case CR1EQ: return 6;
- case R7 : case X7 : case F7 : case V7 : case CR7: case CR1UN: return 7;
- case R8 : case X8 : case F8 : case V8 : case CR2LT: return 8;
- case R9 : case X9 : case F9 : case V9 : case CR2GT: return 9;
- case R10: case X10: case F10: case V10: case CR2EQ: return 10;
- case R11: case X11: case F11: case V11: case CR2UN: return 11;
- case R12: case X12: case F12: case V12: case CR3LT: return 12;
- case R13: case X13: case F13: case V13: case CR3GT: return 13;
- case R14: case X14: case F14: case V14: case CR3EQ: return 14;
- case R15: case X15: case F15: case V15: case CR3UN: return 15;
- case R16: case X16: case F16: case V16: case CR4LT: return 16;
- case R17: case X17: case F17: case V17: case CR4GT: return 17;
- case R18: case X18: case F18: case V18: case CR4EQ: return 18;
- case R19: case X19: case F19: case V19: case CR4UN: return 19;
- case R20: case X20: case F20: case V20: case CR5LT: return 20;
- case R21: case X21: case F21: case V21: case CR5GT: return 21;
- case R22: case X22: case F22: case V22: case CR5EQ: return 22;
- case R23: case X23: case F23: case V23: case CR5UN: return 23;
- case R24: case X24: case F24: case V24: case CR6LT: return 24;
- case R25: case X25: case F25: case V25: case CR6GT: return 25;
- case R26: case X26: case F26: case V26: case CR6EQ: return 26;
- case R27: case X27: case F27: case V27: case CR6UN: return 27;
- case R28: case X28: case F28: case V28: case CR7LT: return 28;
- case R29: case X29: case F29: case V29: case CR7GT: return 29;
- case R30: case X30: case F30: case V30: case CR7EQ: return 30;
- case R31: case X31: case F31: case V31: case CR7UN: return 31;
- default:
- llvm_unreachable("Unhandled reg in PPCRegisterInfo::getRegisterNumbering!");
- }
-}
-
PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
const TargetInstrInfo &tii)
: PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR,
@@ -521,7 +478,7 @@
// rlwinm rA, rA, ShiftBits, 0, 31.
BuildMI(MBB, II, dl, TII.get(PPC::RLWINM), Reg)
.addReg(Reg, RegState::Kill)
- .addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4)
+ .addImm(getPPCRegisterNumbering(SrcReg) * 4)
.addImm(0)
.addImm(31);
Modified: llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCRegisterInfo.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCRegisterInfo.h (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCRegisterInfo.h Mon Jul 25 20:29:47 2011
@@ -33,10 +33,6 @@
public:
PPCRegisterInfo(const PPCSubtarget &SubTarget, const TargetInstrInfo &tii);
- /// getRegisterNumbering - Given the enum value for some register, e.g.
- /// PPC::F14, return the number that it corresponds to (e.g. 14).
- static unsigned getRegisterNumbering(unsigned RegEnum);
-
/// getPointerRegClass - Return the register class to use to hold pointers.
/// This is used for addressing modes.
virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const;
Modified: llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCTargetMachine.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/PowerPC/PPCTargetMachine.cpp Mon Jul 25 20:29:47 2011
@@ -20,36 +20,10 @@
#include "llvm/Support/FormattedStream.h"
using namespace llvm;
-// This is duplicated code. Refactor this.
-static MCStreamer *createMCStreamer(const Target &T, const std::string &TT,
- MCContext &Ctx, TargetAsmBackend &TAB,
- raw_ostream &OS,
- MCCodeEmitter *Emitter,
- bool RelaxAll,
- bool NoExecStack) {
- if (Triple(TT).isOSDarwin())
- return createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll);
-
- return NULL;
-}
-
extern "C" void LLVMInitializePowerPCTarget() {
// Register the targets
RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
-
- // Register the MC Code Emitter
- TargetRegistry::RegisterCodeEmitter(ThePPC32Target, createPPCMCCodeEmitter);
- TargetRegistry::RegisterCodeEmitter(ThePPC64Target, createPPCMCCodeEmitter);
-
-
- // Register the asm backend.
- TargetRegistry::RegisterAsmBackend(ThePPC32Target, createPPCAsmBackend);
- TargetRegistry::RegisterAsmBackend(ThePPC64Target, createPPCAsmBackend);
-
- // Register the object streamer.
- TargetRegistry::RegisterObjectStreamer(ThePPC32Target, createMCStreamer);
- TargetRegistry::RegisterObjectStreamer(ThePPC64Target, createMCStreamer);
}
PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
Modified: llvm/branches/exception-handling-rewrite/lib/Target/Sparc/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/Sparc/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/Sparc/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/Sparc/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -6,6 +6,7 @@
tablegen(SparcGenDAGISel.inc -gen-dag-isel)
tablegen(SparcGenSubtargetInfo.inc -gen-subtarget)
tablegen(SparcGenCallingConv.inc -gen-callingconv)
+add_public_tablegen_target(SparcCommonTableGen)
add_llvm_target(SparcCodeGen
DelaySlotFiller.cpp
Modified: llvm/branches/exception-handling-rewrite/lib/Target/Sparc/MCTargetDesc/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/Sparc/MCTargetDesc/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/Sparc/MCTargetDesc/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/Sparc/MCTargetDesc/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -2,3 +2,4 @@
SparcMCTargetDesc.cpp
SparcMCAsmInfo.cpp
)
+add_dependencies(LLVMSparcDesc SparcCommonTableGen)
Modified: llvm/branches/exception-handling-rewrite/lib/Target/SystemZ/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/SystemZ/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/SystemZ/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/SystemZ/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -6,6 +6,7 @@
tablegen(SystemZGenDAGISel.inc -gen-dag-isel)
tablegen(SystemZGenCallingConv.inc -gen-callingconv)
tablegen(SystemZGenSubtargetInfo.inc -gen-subtarget)
+add_public_tablegen_target(SystemZCommonTableGen)
add_llvm_target(SystemZCodeGen
SystemZAsmPrinter.cpp
Modified: llvm/branches/exception-handling-rewrite/lib/Target/SystemZ/MCTargetDesc/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/SystemZ/MCTargetDesc/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/SystemZ/MCTargetDesc/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/SystemZ/MCTargetDesc/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -2,6 +2,7 @@
SystemZMCTargetDesc.cpp
SystemZMCAsmInfo.cpp
)
+add_dependencies(LLVMSystemZDesc SystemZCommonTableGen)
# Hack: we need to include 'main' target directory to grab private headers
include_directories(${CMAKE_CURRENT_SOURCE_DIR}/.. ${CMAKE_CURRENT_BINARY_DIR}/..)
Modified: llvm/branches/exception-handling-rewrite/lib/Target/Target.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/Target.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/Target.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/Target.cpp Mon Jul 25 20:29:47 2011
@@ -17,6 +17,7 @@
#include "llvm/InitializePasses.h"
#include "llvm/PassManager.h"
#include "llvm/Target/TargetData.h"
+#include "llvm/Target/TargetLibraryInfo.h"
#include "llvm/LLVMContext.h"
#include <cstring>
@@ -39,6 +40,11 @@
unwrap(PM)->add(new TargetData(*unwrap(TD)));
}
+void LLVMAddTargetLibraryInfo(LLVMTargetLibraryInfoRef TLI,
+ LLVMPassManagerRef PM) {
+ unwrap(PM)->add(new TargetLibraryInfo(*unwrap(TLI)));
+}
+
char *LLVMCopyStringRepOfTargetData(LLVMTargetDataRef TD) {
std::string StringRep = unwrap(TD)->getStringRepresentation();
return strdup(StringRep.c_str());
Modified: llvm/branches/exception-handling-rewrite/lib/Target/X86/AsmParser/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/X86/AsmParser/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/X86/AsmParser/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/X86/AsmParser/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -4,4 +4,4 @@
X86AsmLexer.cpp
X86AsmParser.cpp
)
-add_dependencies(LLVMX86AsmParser X86CodeGenTable_gen)
+add_dependencies(LLVMX86AsmParser X86CommonTableGen)
Modified: llvm/branches/exception-handling-rewrite/lib/Target/X86/AsmParser/X86AsmLexer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/X86/AsmParser/X86AsmLexer.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/X86/AsmParser/X86AsmLexer.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/X86/AsmParser/X86AsmLexer.cpp Mon Jul 25 20:29:47 2011
@@ -7,20 +7,20 @@
//
//===----------------------------------------------------------------------===//
+#include "MCTargetDesc/X86BaseInfo.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCParser/MCAsmLexer.h"
#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
-#include "llvm/MC/TargetAsmLexer.h"
+#include "llvm/MC/MCTargetAsmLexer.h"
#include "llvm/Target/TargetRegistry.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringExtras.h"
-#include "X86.h"
using namespace llvm;
namespace {
-class X86AsmLexer : public TargetAsmLexer {
+class X86AsmLexer : public MCTargetAsmLexer {
const MCAsmInfo &AsmInfo;
bool tentativeIsValid;
@@ -60,8 +60,8 @@
}
}
public:
- X86AsmLexer(const Target &T, const MCAsmInfo &MAI)
- : TargetAsmLexer(T), AsmInfo(MAI), tentativeIsValid(false) {
+ X86AsmLexer(const Target &T, const MCRegisterInfo &MRI, const MCAsmInfo &MAI)
+ : MCTargetAsmLexer(T), AsmInfo(MAI), tentativeIsValid(false) {
}
};
@@ -160,6 +160,6 @@
}
extern "C" void LLVMInitializeX86AsmLexer() {
- RegisterAsmLexer<X86AsmLexer> X(TheX86_32Target);
- RegisterAsmLexer<X86AsmLexer> Y(TheX86_64Target);
+ RegisterMCAsmLexer<X86AsmLexer> X(TheX86_32Target);
+ RegisterMCAsmLexer<X86AsmLexer> Y(TheX86_64Target);
}
Modified: llvm/branches/exception-handling-rewrite/lib/Target/X86/AsmParser/X86AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/X86/AsmParser/X86AsmParser.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/X86/AsmParser/X86AsmParser.cpp Mon Jul 25 20:29:47 2011
@@ -7,9 +7,8 @@
//
//===----------------------------------------------------------------------===//
-#include "llvm/MC/TargetAsmParser.h"
-#include "X86.h"
-#include "X86Subtarget.h"
+#include "MCTargetDesc/X86BaseInfo.h"
+#include "llvm/MC/MCTargetAsmParser.h"
#include "llvm/Target/TargetRegistry.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCExpr.h"
@@ -32,7 +31,7 @@
namespace {
struct X86Operand;
-class X86ATTAsmParser : public TargetAsmParser {
+class X86ATTAsmParser : public MCTargetAsmParser {
MCSubtargetInfo &STI;
MCAsmParser &Parser;
@@ -75,7 +74,7 @@
public:
X86ATTAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
- : TargetAsmParser(), STI(sti), Parser(parser) {
+ : MCTargetAsmParser(), STI(sti), Parser(parser) {
// Initialize the set of available features.
setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
@@ -1130,8 +1129,8 @@
// Force static initialization.
extern "C" void LLVMInitializeX86AsmParser() {
- RegisterAsmParser<X86ATTAsmParser> X(TheX86_32Target);
- RegisterAsmParser<X86ATTAsmParser> Y(TheX86_64Target);
+ RegisterMCAsmParser<X86ATTAsmParser> X(TheX86_32Target);
+ RegisterMCAsmParser<X86ATTAsmParser> Y(TheX86_64Target);
LLVMInitializeX86AsmLexer();
}
Modified: llvm/branches/exception-handling-rewrite/lib/Target/X86/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/X86/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/X86/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/X86/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -11,10 +11,10 @@
tablegen(X86GenCallingConv.inc -gen-callingconv)
tablegen(X86GenSubtargetInfo.inc -gen-subtarget)
tablegen(X86GenEDInfo.inc -gen-enhanced-disassembly-info)
+add_public_tablegen_target(X86CommonTableGen)
set(sources
SSEDomainFix.cpp
- X86AsmBackend.cpp
X86AsmPrinter.cpp
X86COFFMachineModuleInfo.cpp
X86CodeEmitter.cpp
@@ -26,8 +26,6 @@
X86ISelLowering.cpp
X86InstrInfo.cpp
X86JITInfo.cpp
- X86MachObjectWriter.cpp
- X86MCCodeEmitter.cpp
X86MCInstLower.cpp
X86RegisterInfo.cpp
X86SelectionDAGInfo.cpp
Modified: llvm/branches/exception-handling-rewrite/lib/Target/X86/Disassembler/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/X86/Disassembler/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/X86/Disassembler/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/X86/Disassembler/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -11,4 +11,4 @@
PROPERTY COMPILE_FLAGS "/Od"
)
endif()
-add_dependencies(LLVMX86Disassembler X86CodeGenTable_gen)
+add_dependencies(LLVMX86Disassembler X86CommonTableGen)
Modified: llvm/branches/exception-handling-rewrite/lib/Target/X86/InstPrinter/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/X86/InstPrinter/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/X86/InstPrinter/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/X86/InstPrinter/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -5,4 +5,4 @@
X86IntelInstPrinter.cpp
X86InstComments.cpp
)
-add_dependencies(LLVMX86AsmPrinter X86CodeGenTable_gen)
+add_dependencies(LLVMX86AsmPrinter X86CommonTableGen)
Modified: llvm/branches/exception-handling-rewrite/lib/Target/X86/InstPrinter/X86InstComments.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/X86/InstPrinter/X86InstComments.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/X86/InstPrinter/X86InstComments.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/X86/InstPrinter/X86InstComments.cpp Mon Jul 25 20:29:47 2011
@@ -14,9 +14,9 @@
#include "X86InstComments.h"
#include "MCTargetDesc/X86MCTargetDesc.h"
+#include "Utils/X86ShuffleDecode.h"
#include "llvm/MC/MCInst.h"
#include "llvm/Support/raw_ostream.h"
-#include "../Utils/X86ShuffleDecode.h"
using namespace llvm;
//===----------------------------------------------------------------------===//
Modified: llvm/branches/exception-handling-rewrite/lib/Target/X86/MCTargetDesc/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/X86/MCTargetDesc/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/X86/MCTargetDesc/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/X86/MCTargetDesc/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -1,7 +1,11 @@
add_llvm_library(LLVMX86Desc
+ X86AsmBackend.cpp
X86MCTargetDesc.cpp
X86MCAsmInfo.cpp
+ X86MCCodeEmitter.cpp
+ X86MachObjectWriter.cpp
)
+add_dependencies(LLVMX86Desc X86CommonTableGen)
# Hack: we need to include 'main' target directory to grab private headers
include_directories(${CMAKE_CURRENT_SOURCE_DIR}/.. ${CMAKE_CURRENT_BINARY_DIR}/..)
Modified: llvm/branches/exception-handling-rewrite/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp Mon Jul 25 20:29:47 2011
@@ -13,9 +13,12 @@
#include "X86MCTargetDesc.h"
#include "X86MCAsmInfo.h"
+#include "InstPrinter/X86ATTInstPrinter.h"
+#include "InstPrinter/X86IntelInstPrinter.h"
#include "llvm/MC/MachineLocation.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Target/TargetRegistry.h"
#include "llvm/ADT/Triple.h"
@@ -363,6 +366,33 @@
return X;
}
+static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
+ MCContext &Ctx, MCAsmBackend &MAB,
+ raw_ostream &_OS,
+ MCCodeEmitter *_Emitter,
+ bool RelaxAll,
+ bool NoExecStack) {
+ Triple TheTriple(TT);
+
+ if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
+ return createMachOStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll);
+
+ if (TheTriple.isOSWindows())
+ return createWinCOFFStreamer(Ctx, MAB, *_Emitter, _OS, RelaxAll);
+
+ return createELFStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll, NoExecStack);
+}
+
+static MCInstPrinter *createX86MCInstPrinter(const Target &T,
+ unsigned SyntaxVariant,
+ const MCAsmInfo &MAI) {
+ if (SyntaxVariant == 0)
+ return new X86ATTInstPrinter(MAI);
+ if (SyntaxVariant == 1)
+ return new X86IntelInstPrinter(MAI);
+ return 0;
+}
+
// Force static initialization.
extern "C" void LLVMInitializeX86TargetMC() {
// Register the MC asm info.
@@ -386,4 +416,28 @@
X86_MC::createX86MCSubtargetInfo);
TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target,
X86_MC::createX86MCSubtargetInfo);
+
+ // Register the code emitter.
+ TargetRegistry::RegisterMCCodeEmitter(TheX86_32Target,
+ createX86MCCodeEmitter);
+ TargetRegistry::RegisterMCCodeEmitter(TheX86_64Target,
+ createX86MCCodeEmitter);
+
+ // Register the asm backend.
+ TargetRegistry::RegisterMCAsmBackend(TheX86_32Target,
+ createX86_32AsmBackend);
+ TargetRegistry::RegisterMCAsmBackend(TheX86_64Target,
+ createX86_64AsmBackend);
+
+ // Register the object streamer.
+ TargetRegistry::RegisterMCObjectStreamer(TheX86_32Target,
+ createMCStreamer);
+ TargetRegistry::RegisterMCObjectStreamer(TheX86_64Target,
+ createMCStreamer);
+
+ // Register the MCInstPrinter.
+ TargetRegistry::RegisterMCInstPrinter(TheX86_32Target,
+ createX86MCInstPrinter);
+ TargetRegistry::RegisterMCInstPrinter(TheX86_64Target,
+ createX86MCInstPrinter);
}
Modified: llvm/branches/exception-handling-rewrite/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h Mon Jul 25 20:29:47 2011
@@ -14,13 +14,20 @@
#ifndef X86MCTARGETDESC_H
#define X86MCTARGETDESC_H
+#include "llvm/Support/DataTypes.h"
#include <string>
namespace llvm {
+class MCAsmBackend;
+class MCCodeEmitter;
+class MCContext;
+class MCInstrInfo;
+class MCObjectWriter;
class MCRegisterInfo;
class MCSubtargetInfo;
class Target;
class StringRef;
+class raw_ostream;
extern Target TheX86_32Target, TheX86_64Target;
@@ -63,6 +70,19 @@
StringRef FS);
}
+MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII,
+ const MCSubtargetInfo &STI,
+ MCContext &Ctx);
+
+MCAsmBackend *createX86_32AsmBackend(const Target &T, StringRef TT);
+MCAsmBackend *createX86_64AsmBackend(const Target &T, StringRef TT);
+
+/// createX86MachObjectWriter - Construct an X86 Mach-O object writer.
+MCObjectWriter *createX86MachObjectWriter(raw_ostream &OS,
+ bool Is64Bit,
+ uint32_t CPUType,
+ uint32_t CPUSubtype);
+
} // End llvm namespace
Modified: llvm/branches/exception-handling-rewrite/lib/Target/X86/README.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/X86/README.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/X86/README.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/X86/README.txt Mon Jul 25 20:29:47 2011
@@ -2066,3 +2066,51 @@
//===---------------------------------------------------------------------===//
+unsigned log2(unsigned x) {
+ return x > 1 ? 32-__builtin_clz(x-1) : 0;
+}
+
+generates (x86_64):
+ xorl %eax, %eax
+ cmpl $2, %edi
+ jb LBB0_2
+## BB#1:
+ decl %edi
+ movl $63, %eax
+ bsrl %edi, %ecx
+ cmovel %eax, %ecx
+ xorl $31, %ecx
+ movl $32, %eax
+ subl %ecx, %eax
+LBB0_2:
+ ret
+
+The cmov and the early test are redundant:
+ xorl %eax, %eax
+ cmpl $2, %edi
+ jb LBB0_2
+## BB#1:
+ decl %edi
+ bsrl %edi, %ecx
+ xorl $31, %ecx
+ movl $32, %eax
+ subl %ecx, %eax
+LBB0_2:
+ ret
+
+If we want to get really fancy we could use some two's complement magic:
+ xorl %eax, %eax
+ cmpl $2, %edi
+ jb LBB0_2
+## BB#1:
+ decl %edi
+ bsrl %edi, %ecx
+ xorl $-32, %ecx
+ leal 33(%ecx), %eax
+LBB0_2:
+ ret
+
+This is only useful on targets that can't encode the first operand of a sub
+directly. The rule is C1 - (X^C2) -> (C1+1) + (X^~C2).
+
+//===---------------------------------------------------------------------===//
Modified: llvm/branches/exception-handling-rewrite/lib/Target/X86/X86.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/X86/X86.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/X86/X86.h (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/X86/X86.h Mon Jul 25 20:29:47 2011
@@ -15,6 +15,7 @@
#ifndef TARGET_X86_H
#define TARGET_X86_H
+#include "MCTargetDesc/X86BaseInfo.h"
#include "MCTargetDesc/X86MCTargetDesc.h"
#include "llvm/Support/DataTypes.h"
#include "llvm/Target/TargetMachine.h"
@@ -24,16 +25,8 @@
class FunctionPass;
class JITCodeEmitter;
class MachineCodeEmitter;
-class MCCodeEmitter;
-class MCContext;
-class MCInstrInfo;
-class MCObjectWriter;
-class MCSubtargetInfo;
class Target;
-class TargetAsmBackend;
class X86TargetMachine;
-class formatted_raw_ostream;
-class raw_ostream;
/// createX86ISelDag - This pass converts a legalized DAG into a
/// X86-specific DAG, ready for instruction scheduling.
@@ -60,13 +53,6 @@
FunctionPass *createX86JITCodeEmitterPass(X86TargetMachine &TM,
JITCodeEmitter &JCE);
-MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII,
- const MCSubtargetInfo &STI,
- MCContext &Ctx);
-
-TargetAsmBackend *createX86_32AsmBackend(const Target &, const std::string &);
-TargetAsmBackend *createX86_64AsmBackend(const Target &, const std::string &);
-
/// createX86EmitCodeToMemory - Returns a pass that converts a register
/// allocated function into raw machine code in a dynamically
/// allocated chunk of memory.
@@ -79,13 +65,6 @@
///
FunctionPass *createX86MaxStackAlignmentHeuristicPass();
-
-/// createX86MachObjectWriter - Construct an X86 Mach-O object writer.
-MCObjectWriter *createX86MachObjectWriter(raw_ostream &OS,
- bool Is64Bit,
- uint32_t CPUType,
- uint32_t CPUSubtype);
-
} // End llvm namespace
#endif
Removed: llvm/branches/exception-handling-rewrite/lib/Target/X86/X86AsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/X86/X86AsmBackend.cpp?rev=136039&view=auto
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/X86/X86AsmBackend.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/X86/X86AsmBackend.cpp (removed)
@@ -1,452 +0,0 @@
-//===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#include "llvm/MC/TargetAsmBackend.h"
-#include "X86.h"
-#include "X86FixupKinds.h"
-#include "llvm/ADT/Twine.h"
-#include "llvm/MC/MCAssembler.h"
-#include "llvm/MC/MCELFObjectWriter.h"
-#include "llvm/MC/MCExpr.h"
-#include "llvm/MC/MCFixupKindInfo.h"
-#include "llvm/MC/MCMachObjectWriter.h"
-#include "llvm/MC/MCObjectWriter.h"
-#include "llvm/MC/MCSectionCOFF.h"
-#include "llvm/MC/MCSectionELF.h"
-#include "llvm/MC/MCSectionMachO.h"
-#include "llvm/Object/MachOFormat.h"
-#include "llvm/Support/CommandLine.h"
-#include "llvm/Support/ELF.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegistry.h"
-using namespace llvm;
-
-// Option to allow disabling arithmetic relaxation to workaround PR9807, which
-// is useful when running bitwise comparison experiments on Darwin. We should be
-// able to remove this once PR9807 is resolved.
-static cl::opt<bool>
-MCDisableArithRelaxation("mc-x86-disable-arith-relaxation",
- cl::desc("Disable relaxation of arithmetic instruction for X86"));
-
-static unsigned getFixupKindLog2Size(unsigned Kind) {
- switch (Kind) {
- default: assert(0 && "invalid fixup kind!");
- case FK_PCRel_1:
- case FK_Data_1: return 0;
- case FK_PCRel_2:
- case FK_Data_2: return 1;
- case FK_PCRel_4:
- case X86::reloc_riprel_4byte:
- case X86::reloc_riprel_4byte_movq_load:
- case X86::reloc_signed_4byte:
- case X86::reloc_global_offset_table:
- case FK_Data_4: return 2;
- case FK_PCRel_8:
- case FK_Data_8: return 3;
- }
-}
-
-namespace {
-
-class X86ELFObjectWriter : public MCELFObjectTargetWriter {
-public:
- X86ELFObjectWriter(bool is64Bit, Triple::OSType OSType, uint16_t EMachine,
- bool HasRelocationAddend)
- : MCELFObjectTargetWriter(is64Bit, OSType, EMachine, HasRelocationAddend) {}
-};
-
-class X86AsmBackend : public TargetAsmBackend {
-public:
- X86AsmBackend(const Target &T)
- : TargetAsmBackend() {}
-
- unsigned getNumFixupKinds() const {
- return X86::NumTargetFixupKinds;
- }
-
- const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
- const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {
- { "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
- { "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel},
- { "reloc_signed_4byte", 0, 4 * 8, 0},
- { "reloc_global_offset_table", 0, 4 * 8, 0}
- };
-
- if (Kind < FirstTargetFixupKind)
- return TargetAsmBackend::getFixupKindInfo(Kind);
-
- assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
- "Invalid kind!");
- return Infos[Kind - FirstTargetFixupKind];
- }
-
- void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
- uint64_t Value) const {
- unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind());
-
- assert(Fixup.getOffset() + Size <= DataSize &&
- "Invalid fixup offset!");
- for (unsigned i = 0; i != Size; ++i)
- Data[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8));
- }
-
- bool MayNeedRelaxation(const MCInst &Inst) const;
-
- void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
-
- bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
-};
-} // end anonymous namespace
-
-static unsigned getRelaxedOpcodeBranch(unsigned Op) {
- switch (Op) {
- default:
- return Op;
-
- case X86::JAE_1: return X86::JAE_4;
- case X86::JA_1: return X86::JA_4;
- case X86::JBE_1: return X86::JBE_4;
- case X86::JB_1: return X86::JB_4;
- case X86::JE_1: return X86::JE_4;
- case X86::JGE_1: return X86::JGE_4;
- case X86::JG_1: return X86::JG_4;
- case X86::JLE_1: return X86::JLE_4;
- case X86::JL_1: return X86::JL_4;
- case X86::JMP_1: return X86::JMP_4;
- case X86::JNE_1: return X86::JNE_4;
- case X86::JNO_1: return X86::JNO_4;
- case X86::JNP_1: return X86::JNP_4;
- case X86::JNS_1: return X86::JNS_4;
- case X86::JO_1: return X86::JO_4;
- case X86::JP_1: return X86::JP_4;
- case X86::JS_1: return X86::JS_4;
- }
-}
-
-static unsigned getRelaxedOpcodeArith(unsigned Op) {
- switch (Op) {
- default:
- return Op;
-
- // IMUL
- case X86::IMUL16rri8: return X86::IMUL16rri;
- case X86::IMUL16rmi8: return X86::IMUL16rmi;
- case X86::IMUL32rri8: return X86::IMUL32rri;
- case X86::IMUL32rmi8: return X86::IMUL32rmi;
- case X86::IMUL64rri8: return X86::IMUL64rri32;
- case X86::IMUL64rmi8: return X86::IMUL64rmi32;
-
- // AND
- case X86::AND16ri8: return X86::AND16ri;
- case X86::AND16mi8: return X86::AND16mi;
- case X86::AND32ri8: return X86::AND32ri;
- case X86::AND32mi8: return X86::AND32mi;
- case X86::AND64ri8: return X86::AND64ri32;
- case X86::AND64mi8: return X86::AND64mi32;
-
- // OR
- case X86::OR16ri8: return X86::OR16ri;
- case X86::OR16mi8: return X86::OR16mi;
- case X86::OR32ri8: return X86::OR32ri;
- case X86::OR32mi8: return X86::OR32mi;
- case X86::OR64ri8: return X86::OR64ri32;
- case X86::OR64mi8: return X86::OR64mi32;
-
- // XOR
- case X86::XOR16ri8: return X86::XOR16ri;
- case X86::XOR16mi8: return X86::XOR16mi;
- case X86::XOR32ri8: return X86::XOR32ri;
- case X86::XOR32mi8: return X86::XOR32mi;
- case X86::XOR64ri8: return X86::XOR64ri32;
- case X86::XOR64mi8: return X86::XOR64mi32;
-
- // ADD
- case X86::ADD16ri8: return X86::ADD16ri;
- case X86::ADD16mi8: return X86::ADD16mi;
- case X86::ADD32ri8: return X86::ADD32ri;
- case X86::ADD32mi8: return X86::ADD32mi;
- case X86::ADD64ri8: return X86::ADD64ri32;
- case X86::ADD64mi8: return X86::ADD64mi32;
-
- // SUB
- case X86::SUB16ri8: return X86::SUB16ri;
- case X86::SUB16mi8: return X86::SUB16mi;
- case X86::SUB32ri8: return X86::SUB32ri;
- case X86::SUB32mi8: return X86::SUB32mi;
- case X86::SUB64ri8: return X86::SUB64ri32;
- case X86::SUB64mi8: return X86::SUB64mi32;
-
- // CMP
- case X86::CMP16ri8: return X86::CMP16ri;
- case X86::CMP16mi8: return X86::CMP16mi;
- case X86::CMP32ri8: return X86::CMP32ri;
- case X86::CMP32mi8: return X86::CMP32mi;
- case X86::CMP64ri8: return X86::CMP64ri32;
- case X86::CMP64mi8: return X86::CMP64mi32;
-
- // PUSH
- case X86::PUSHi8: return X86::PUSHi32;
- case X86::PUSHi16: return X86::PUSHi32;
- case X86::PUSH64i8: return X86::PUSH64i32;
- case X86::PUSH64i16: return X86::PUSH64i32;
- }
-}
-
-static unsigned getRelaxedOpcode(unsigned Op) {
- unsigned R = getRelaxedOpcodeArith(Op);
- if (R != Op)
- return R;
- return getRelaxedOpcodeBranch(Op);
-}
-
-bool X86AsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
- // Branches can always be relaxed.
- if (getRelaxedOpcodeBranch(Inst.getOpcode()) != Inst.getOpcode())
- return true;
-
- if (MCDisableArithRelaxation)
- return false;
-
- // Check if this instruction is ever relaxable.
- if (getRelaxedOpcodeArith(Inst.getOpcode()) == Inst.getOpcode())
- return false;
-
-
- // Check if it has an expression and is not RIP relative.
- bool hasExp = false;
- bool hasRIP = false;
- for (unsigned i = 0; i < Inst.getNumOperands(); ++i) {
- const MCOperand &Op = Inst.getOperand(i);
- if (Op.isExpr())
- hasExp = true;
-
- if (Op.isReg() && Op.getReg() == X86::RIP)
- hasRIP = true;
- }
-
- // FIXME: Why exactly do we need the !hasRIP? Is it just a limitation on
- // how we do relaxations?
- return hasExp && !hasRIP;
-}
-
-// FIXME: Can tblgen help at all here to verify there aren't other instructions
-// we can relax?
-void X86AsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
- // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
- unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
-
- if (RelaxedOp == Inst.getOpcode()) {
- SmallString<256> Tmp;
- raw_svector_ostream OS(Tmp);
- Inst.dump_pretty(OS);
- OS << "\n";
- report_fatal_error("unexpected instruction to relax: " + OS.str());
- }
-
- Res = Inst;
- Res.setOpcode(RelaxedOp);
-}
-
-/// WriteNopData - Write optimal nops to the output file for the \arg Count
-/// bytes. This returns the number of bytes written. It may return 0 if
-/// the \arg Count is more than the maximum optimal nops.
-bool X86AsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
- static const uint8_t Nops[10][10] = {
- // nop
- {0x90},
- // xchg %ax,%ax
- {0x66, 0x90},
- // nopl (%[re]ax)
- {0x0f, 0x1f, 0x00},
- // nopl 0(%[re]ax)
- {0x0f, 0x1f, 0x40, 0x00},
- // nopl 0(%[re]ax,%[re]ax,1)
- {0x0f, 0x1f, 0x44, 0x00, 0x00},
- // nopw 0(%[re]ax,%[re]ax,1)
- {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
- // nopl 0L(%[re]ax)
- {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
- // nopl 0L(%[re]ax,%[re]ax,1)
- {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
- // nopw 0L(%[re]ax,%[re]ax,1)
- {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
- // nopw %cs:0L(%[re]ax,%[re]ax,1)
- {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
- };
-
- // Write an optimal sequence for the first 15 bytes.
- const uint64_t OptimalCount = (Count < 16) ? Count : 15;
- const uint64_t Prefixes = OptimalCount <= 10 ? 0 : OptimalCount - 10;
- for (uint64_t i = 0, e = Prefixes; i != e; i++)
- OW->Write8(0x66);
- const uint64_t Rest = OptimalCount - Prefixes;
- for (uint64_t i = 0, e = Rest; i != e; i++)
- OW->Write8(Nops[Rest - 1][i]);
-
- // Finish with single byte nops.
- for (uint64_t i = OptimalCount, e = Count; i != e; ++i)
- OW->Write8(0x90);
-
- return true;
-}
-
-/* *** */
-
-namespace {
-class ELFX86AsmBackend : public X86AsmBackend {
-public:
- Triple::OSType OSType;
- ELFX86AsmBackend(const Target &T, Triple::OSType _OSType)
- : X86AsmBackend(T), OSType(_OSType) {
- HasReliableSymbolDifference = true;
- }
-
- virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
- const MCSectionELF &ES = static_cast<const MCSectionELF&>(Section);
- return ES.getFlags() & ELF::SHF_MERGE;
- }
-};
-
-class ELFX86_32AsmBackend : public ELFX86AsmBackend {
-public:
- ELFX86_32AsmBackend(const Target &T, Triple::OSType OSType)
- : ELFX86AsmBackend(T, OSType) {}
-
- MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
- return createELFObjectWriter(createELFObjectTargetWriter(),
- OS, /*IsLittleEndian*/ true);
- }
-
- MCELFObjectTargetWriter *createELFObjectTargetWriter() const {
- return new X86ELFObjectWriter(false, OSType, ELF::EM_386, false);
- }
-};
-
-class ELFX86_64AsmBackend : public ELFX86AsmBackend {
-public:
- ELFX86_64AsmBackend(const Target &T, Triple::OSType OSType)
- : ELFX86AsmBackend(T, OSType) {}
-
- MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
- return createELFObjectWriter(createELFObjectTargetWriter(),
- OS, /*IsLittleEndian*/ true);
- }
-
- MCELFObjectTargetWriter *createELFObjectTargetWriter() const {
- return new X86ELFObjectWriter(true, OSType, ELF::EM_X86_64, true);
- }
-};
-
-class WindowsX86AsmBackend : public X86AsmBackend {
- bool Is64Bit;
-
-public:
- WindowsX86AsmBackend(const Target &T, bool is64Bit)
- : X86AsmBackend(T)
- , Is64Bit(is64Bit) {
- }
-
- MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
- return createWinCOFFObjectWriter(OS, Is64Bit);
- }
-};
-
-class DarwinX86AsmBackend : public X86AsmBackend {
-public:
- DarwinX86AsmBackend(const Target &T)
- : X86AsmBackend(T) { }
-};
-
-class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
-public:
- DarwinX86_32AsmBackend(const Target &T)
- : DarwinX86AsmBackend(T) {}
-
- MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
- return createX86MachObjectWriter(OS, /*Is64Bit=*/false,
- object::mach::CTM_i386,
- object::mach::CSX86_ALL);
- }
-};
-
-class DarwinX86_64AsmBackend : public DarwinX86AsmBackend {
-public:
- DarwinX86_64AsmBackend(const Target &T)
- : DarwinX86AsmBackend(T) {
- HasReliableSymbolDifference = true;
- }
-
- MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
- return createX86MachObjectWriter(OS, /*Is64Bit=*/true,
- object::mach::CTM_x86_64,
- object::mach::CSX86_ALL);
- }
-
- virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
- // Temporary labels in the string literals sections require symbols. The
- // issue is that the x86_64 relocation format does not allow symbol +
- // offset, and so the linker does not have enough information to resolve the
- // access to the appropriate atom unless an external relocation is used. For
- // non-cstring sections, we expect the compiler to use a non-temporary label
- // for anything that could have an addend pointing outside the symbol.
- //
- // See <rdar://problem/4765733>.
- const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
- return SMO.getType() == MCSectionMachO::S_CSTRING_LITERALS;
- }
-
- virtual bool isSectionAtomizable(const MCSection &Section) const {
- const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
- // Fixed sized data sections are uniqued, they cannot be diced into atoms.
- switch (SMO.getType()) {
- default:
- return true;
-
- case MCSectionMachO::S_4BYTE_LITERALS:
- case MCSectionMachO::S_8BYTE_LITERALS:
- case MCSectionMachO::S_16BYTE_LITERALS:
- case MCSectionMachO::S_LITERAL_POINTERS:
- case MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS:
- case MCSectionMachO::S_LAZY_SYMBOL_POINTERS:
- case MCSectionMachO::S_MOD_INIT_FUNC_POINTERS:
- case MCSectionMachO::S_MOD_TERM_FUNC_POINTERS:
- case MCSectionMachO::S_INTERPOSING:
- return false;
- }
- }
-};
-
-} // end anonymous namespace
-
-TargetAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
- const std::string &TT) {
- Triple TheTriple(TT);
-
- if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
- return new DarwinX86_32AsmBackend(T);
-
- if (TheTriple.isOSWindows())
- return new WindowsX86AsmBackend(T, false);
-
- return new ELFX86_32AsmBackend(T, TheTriple.getOS());
-}
-
-TargetAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
- const std::string &TT) {
- Triple TheTriple(TT);
-
- if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
- return new DarwinX86_64AsmBackend(T);
-
- if (TheTriple.isOSWindows())
- return new WindowsX86AsmBackend(T, true);
-
- return new ELFX86_64AsmBackend(T, TheTriple.getOS());
-}
Modified: llvm/branches/exception-handling-rewrite/lib/Target/X86/X86AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/X86/X86AsmPrinter.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/X86/X86AsmPrinter.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/X86/X86AsmPrinter.cpp Mon Jul 25 20:29:47 2011
@@ -708,21 +708,8 @@
// Target Registry Stuff
//===----------------------------------------------------------------------===//
-static MCInstPrinter *createX86MCInstPrinter(const Target &T,
- unsigned SyntaxVariant,
- const MCAsmInfo &MAI) {
- if (SyntaxVariant == 0)
- return new X86ATTInstPrinter(MAI);
- if (SyntaxVariant == 1)
- return new X86IntelInstPrinter(MAI);
- return 0;
-}
-
// Force static initialization.
extern "C" void LLVMInitializeX86AsmPrinter() {
RegisterAsmPrinter<X86AsmPrinter> X(TheX86_32Target);
RegisterAsmPrinter<X86AsmPrinter> Y(TheX86_64Target);
-
- TargetRegistry::RegisterMCInstPrinter(TheX86_32Target,createX86MCInstPrinter);
- TargetRegistry::RegisterMCInstPrinter(TheX86_64Target,createX86MCInstPrinter);
}
Modified: llvm/branches/exception-handling-rewrite/lib/Target/X86/X86CodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/X86/X86CodeEmitter.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/X86/X86CodeEmitter.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/X86/X86CodeEmitter.cpp Mon Jul 25 20:29:47 2011
@@ -167,7 +167,7 @@
const MachineOperand& MO = MI.getOperand(i);
if (MO.isReg()) {
unsigned Reg = MO.getReg();
- if (X86InstrInfo::isX86_64NonExtLowByteReg(Reg))
+ if (X86II::isX86_64NonExtLowByteReg(Reg))
REX |= 0x40;
}
}
Removed: llvm/branches/exception-handling-rewrite/lib/Target/X86/X86FixupKinds.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/X86/X86FixupKinds.h?rev=136039&view=auto
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/X86/X86FixupKinds.h (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/X86/X86FixupKinds.h (removed)
@@ -1,33 +0,0 @@
-//===-- X86/X86FixupKinds.h - X86 Specific Fixup Entries --------*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_X86_X86FIXUPKINDS_H
-#define LLVM_X86_X86FIXUPKINDS_H
-
-#include "llvm/MC/MCFixup.h"
-
-namespace llvm {
-namespace X86 {
-enum Fixups {
- reloc_riprel_4byte = FirstTargetFixupKind, // 32-bit rip-relative
- reloc_riprel_4byte_movq_load, // 32-bit rip-relative in movq
- reloc_signed_4byte, // 32-bit signed. Unlike FK_Data_4
- // this will be sign extended at
- // runtime.
- reloc_global_offset_table, // 32-bit, relative to the start
- // of the instruction. Used only
- // for _GLOBAL_OFFSET_TABLE_.
- // Marker
- LastTargetFixupKind,
- NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
-};
-}
-}
-
-#endif
Modified: llvm/branches/exception-handling-rewrite/lib/Target/X86/X86FrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/X86/X86FrameLowering.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/X86/X86FrameLowering.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/X86/X86FrameLowering.cpp Mon Jul 25 20:29:47 2011
@@ -34,6 +34,13 @@
// FIXME: completely move here.
extern cl::opt<bool> ForceStackAlign;
+// FIXME: Remove once linker support is available. The feature exists only on
+// Darwin at the moment.
+static cl::opt<bool>
+GenerateCompactUnwind("gen-compact-unwind",
+ cl::desc("Generate compact unwind encoding"),
+ cl::Hidden);
+
bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
return !MF.getFrameInfo()->hasVarSizedObjects();
}
@@ -283,8 +290,8 @@
}
void X86FrameLowering::emitCalleeSavedFrameMoves(MachineFunction &MF,
- MCSymbol *Label,
- unsigned FramePtr) const {
+ MCSymbol *Label,
+ unsigned FramePtr) const {
MachineFrameInfo *MFI = MF.getFrameInfo();
MachineModuleInfo &MMI = MF.getMMI();
@@ -346,6 +353,245 @@
}
}
+/// getCompactUnwindRegNum - Get the compact unwind number for a given
+/// register. The number corresponds to the enum lists in
+/// compact_unwind_encoding.h.
+static int getCompactUnwindRegNum(const unsigned *CURegs, unsigned Reg) {
+ int Idx = 1;
+ for (; *CURegs; ++CURegs, ++Idx)
+ if (*CURegs == Reg)
+ return Idx;
+
+ return -1;
+}
+
+/// encodeCompactUnwindRegistersWithoutFrame - Create the permutation encoding
+/// used with frameless stacks. It is passed the number of registers to be saved
+/// and an array of the registers saved.
+static uint32_t encodeCompactUnwindRegistersWithoutFrame(unsigned SavedRegs[6],
+ unsigned RegCount,
+ bool Is64Bit) {
+ // The saved registers are numbered from 1 to 6. In order to encode the order
+ // in which they were saved, we re-number them according to their place in the
+ // register order. The re-numbering is relative to the last re-numbered
+ // register. E.g., if we have registers {6, 2, 4, 5} saved in that order:
+ //
+ // Orig Re-Num
+ // ---- ------
+ // 6 6
+ // 2 2
+ // 4 3
+ // 5 3
+ //
+ static const unsigned CU32BitRegs[] = {
+ X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
+ };
+ static const unsigned CU64BitRegs[] = {
+ X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
+ };
+ const unsigned *CURegs = (Is64Bit ? CU64BitRegs : CU32BitRegs);
+
+ uint32_t RenumRegs[6];
+ for (unsigned i = 6 - RegCount; i < 6; ++i) {
+ int CUReg = getCompactUnwindRegNum(CURegs, SavedRegs[i]);
+ if (CUReg == -1) return ~0U;
+ SavedRegs[i] = CUReg;
+
+ unsigned Countless = 0;
+ for (unsigned j = 6 - RegCount; j < i; ++j)
+ if (SavedRegs[j] < SavedRegs[i])
+ ++Countless;
+
+ RenumRegs[i] = SavedRegs[i] - Countless - 1;
+ }
+
+ // Take the renumbered values and encode them into a 10-bit number.
+ uint32_t permutationEncoding = 0;
+ switch (RegCount) {
+ case 6:
+ permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1]
+ + 6 * RenumRegs[2] + 2 * RenumRegs[3]
+ + RenumRegs[4];
+ break;
+ case 5:
+ permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2]
+ + 6 * RenumRegs[3] + 2 * RenumRegs[4]
+ + RenumRegs[5];
+ break;
+ case 4:
+ permutationEncoding |= 60 * RenumRegs[2] + 12 * RenumRegs[3]
+ + 3 * RenumRegs[4] + RenumRegs[5];
+ break;
+ case 3:
+ permutationEncoding |= 20 * RenumRegs[3] + 4 * RenumRegs[4]
+ + RenumRegs[5];
+ break;
+ case 2:
+ permutationEncoding |= 5 * RenumRegs[4] + RenumRegs[5];
+ break;
+ case 1:
+ permutationEncoding |= RenumRegs[5];
+ break;
+ }
+
+ assert((permutationEncoding & 0x3FF) == permutationEncoding &&
+ "Invalid compact register encoding!");
+ return permutationEncoding;
+}
+
+/// encodeCompactUnwindRegistersWithFrame - Return the registers encoded for a
+/// compact encoding with a frame pointer.
+static uint32_t encodeCompactUnwindRegistersWithFrame(unsigned SavedRegs[6],
+ bool Is64Bit) {
+ static const unsigned CU32BitRegs[] = {
+ X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
+ };
+ static const unsigned CU64BitRegs[] = {
+ X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
+ };
+ const unsigned *CURegs = (Is64Bit ? CU64BitRegs : CU32BitRegs);
+
+ // Encode the registers in the order they were saved, 3-bits per register. The
+ // registers are numbered from 1 to 6.
+ uint32_t RegEnc = 0;
+ for (int I = 5; I >= 0; --I) {
+ unsigned Reg = SavedRegs[I];
+ if (Reg == 0) break;
+ int CURegNum = getCompactUnwindRegNum(CURegs, Reg);
+ if (CURegNum == -1)
+ return ~0U;
+ RegEnc |= (CURegNum & 0x7) << (5 - I);
+ }
+
+ assert((RegEnc & 0x7FFF) == RegEnc && "Invalid compact register encoding!");
+ return RegEnc;
+}
+
+uint32_t X86FrameLowering::getCompactUnwindEncoding(MachineFunction &MF) const {
+ const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
+ unsigned FramePtr = RegInfo->getFrameRegister(MF);
+ unsigned StackPtr = RegInfo->getStackRegister();
+
+ X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
+ int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
+
+ bool Is64Bit = STI.is64Bit();
+ bool HasFP = hasFP(MF);
+
+ unsigned SavedRegs[6] = { 0, 0, 0, 0, 0, 0 };
+ int SavedRegIdx = 6;
+
+ unsigned OffsetSize = (Is64Bit ? 8 : 4);
+
+ unsigned PushInstr = (Is64Bit ? X86::PUSH64r : X86::PUSH32r);
+ unsigned PushInstrSize = 1;
+ unsigned MoveInstr = (Is64Bit ? X86::MOV64rr : X86::MOV32rr);
+ unsigned MoveInstrSize = (Is64Bit ? 3 : 2);
+ unsigned SubtractInstr = getSUBriOpcode(Is64Bit, -TailCallReturnAddrDelta);
+ unsigned SubtractInstrIdx = (Is64Bit ? 3 : 2);
+
+ unsigned InstrOffset = 0;
+ unsigned CFAOffset = 0;
+ unsigned StackAdjust = 0;
+
+ MachineBasicBlock &MBB = MF.front(); // Prologue is in entry BB.
+ bool ExpectEnd = false;
+ for (MachineBasicBlock::iterator
+ MBBI = MBB.begin(), MBBE = MBB.end(); MBBI != MBBE; ++MBBI) {
+ MachineInstr &MI = *MBBI;
+ unsigned Opc = MI.getOpcode();
+ if (Opc == X86::PROLOG_LABEL) continue;
+ if (!MI.getFlag(MachineInstr::FrameSetup)) break;
+
+ // We don't exect any more prolog instructions.
+ if (ExpectEnd) return 0;
+
+ if (Opc == PushInstr) {
+ // If there are too many saved registers, we cannot use compact encoding.
+ if (--SavedRegIdx < 0) return 0;
+
+ SavedRegs[SavedRegIdx] = MI.getOperand(0).getReg();
+ CFAOffset += OffsetSize;
+ InstrOffset += PushInstrSize;
+ } else if (Opc == MoveInstr) {
+ unsigned SrcReg = MI.getOperand(1).getReg();
+ unsigned DstReg = MI.getOperand(0).getReg();
+
+ if (DstReg != FramePtr || SrcReg != StackPtr)
+ return 0;
+
+ CFAOffset = 0;
+ memset(SavedRegs, 0, sizeof(SavedRegs));
+ InstrOffset += MoveInstrSize;
+ } else if (Opc == SubtractInstr) {
+ if (StackAdjust)
+ // We all ready have a stack pointer adjustment.
+ return 0;
+
+ if (!MI.getOperand(0).isReg() ||
+ MI.getOperand(0).getReg() != MI.getOperand(1).getReg() ||
+ MI.getOperand(0).getReg() != StackPtr || !MI.getOperand(2).isImm())
+ // We need this to be a stack adjustment pointer. Something like:
+ //
+ // %RSP<def> = SUB64ri8 %RSP, 48
+ return 0;
+
+ StackAdjust = MI.getOperand(2).getImm() / 4;
+ SubtractInstrIdx += InstrOffset;
+ ExpectEnd = true;
+ }
+ }
+
+ // Encode that we are using EBP/RBP as the frame pointer.
+ uint32_t CompactUnwindEncoding = 0;
+ CFAOffset /= 4;
+ if (HasFP) {
+ if ((CFAOffset & 0xFF) != CFAOffset)
+ // Offset was too big for compact encoding.
+ return 0;
+
+ // Get the encoding of the saved registers when we have a frame pointer.
+ uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame(SavedRegs, Is64Bit);
+ if (RegEnc == ~0U)
+ return 0;
+
+ CompactUnwindEncoding |= 0x01000000;
+ CompactUnwindEncoding |= (CFAOffset & 0xFF) << 16;
+ CompactUnwindEncoding |= RegEnc & 0x7FFF;
+ } else {
+ unsigned FullOffset = CFAOffset + StackAdjust;
+ if ((FullOffset & 0xFF) == FullOffset) {
+ // Frameless stack.
+ CompactUnwindEncoding |= 0x02000000;
+ CompactUnwindEncoding |= (FullOffset & 0xFF) << 16;
+ } else {
+ if ((CFAOffset & 0x7) != CFAOffset)
+ // The extra stack adjustments are too big for us to handle.
+ return 0;
+
+ // Frameless stack with an offset too large for us to encode compactly.
+ CompactUnwindEncoding |= 0x03000000;
+
+ // Encode the offset to the nnnnnn value in the 'subl $nnnnnn, ESP'
+ // instruction.
+ CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16;
+
+ // Encode any extra stack stack changes (done via push instructions).
+ CompactUnwindEncoding |= (CFAOffset & 0x7) << 13;
+ }
+
+ // Get the encoding of the saved registers when we don't have a frame
+ // pointer.
+ uint32_t RegEnc = encodeCompactUnwindRegistersWithoutFrame(SavedRegs,
+ 6 - SavedRegIdx,
+ Is64Bit);
+ if (RegEnc == ~0U) return 0;
+ CompactUnwindEncoding |= RegEnc & 0x3FF;
+ }
+
+ return CompactUnwindEncoding;
+}
+
/// emitPrologue - Push callee-saved registers onto the stack, which
/// automatically adjust the stack pointer. Adjust the stack pointer to allocate
/// space for local variables. Also emit labels used by the exception handler to
@@ -478,7 +724,7 @@
Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
}
- // Update EBP with the new base value...
+ // Update EBP with the new base value.
BuildMI(MBB, MBBI, DL,
TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
.addReg(StackPtr)
@@ -534,8 +780,7 @@
BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(Label);
// Define the current CFA rule to use the provided offset.
- unsigned Ptr = StackSize ?
- MachineLocation::VirtualFP : StackPtr;
+ unsigned Ptr = StackSize ? MachineLocation::VirtualFP : StackPtr;
MachineLocation SPDst(Ptr);
MachineLocation SPSrc(Ptr, StackOffset);
Moves.push_back(MachineMove(Label, SPDst, SPSrc));
@@ -657,6 +902,11 @@
if (PushedRegs)
emitCalleeSavedFrameMoves(MF, Label, HasFP ? FramePtr : StackPtr);
}
+
+ // Darwin 10.7 and greater has support for compact unwind encoding.
+ if (GenerateCompactUnwind &&
+ STI.isTargetDarwin() && !STI.getTargetTriple().isMacOSXVersionLT(10, 6))
+ MMI.setCompactUnwindEncoding(getCompactUnwindEncoding(MF));
}
void X86FrameLowering::emitEpilogue(MachineFunction &MF,
Modified: llvm/branches/exception-handling-rewrite/lib/Target/X86/X86FrameLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/X86/X86FrameLowering.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/X86/X86FrameLowering.h (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/X86/X86FrameLowering.h Mon Jul 25 20:29:47 2011
@@ -58,6 +58,7 @@
bool hasReservedCallFrame(const MachineFunction &MF) const;
int getFrameIndexOffset(const MachineFunction &MF, int FI) const;
+ uint32_t getCompactUnwindEncoding(MachineFunction &MF) const;
};
} // End llvm namespace
Modified: llvm/branches/exception-handling-rewrite/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/X86/X86ISelLowering.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/X86/X86ISelLowering.cpp Mon Jul 25 20:29:47 2011
@@ -983,6 +983,7 @@
setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
+ setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
}
@@ -3075,27 +3076,16 @@
if (i == e)
return false;
- // Determine if it's ok to perform a palignr with only the LHS, since we
- // don't have access to the actual shuffle elements to see if RHS is undef.
- bool Unary = Mask[i] < (int)e;
- bool NeedsUnary = false;
+ // Make sure we're shifting in the right direction.
+ if (Mask[i] <= i)
+ return false;
int s = Mask[i] - i;
// Check the rest of the elements to see if they are consecutive.
for (++i; i != e; ++i) {
int m = Mask[i];
- if (m < 0)
- continue;
-
- Unary = Unary && (m < (int)e);
- NeedsUnary = NeedsUnary || (m < s);
-
- if (NeedsUnary && !Unary)
- return false;
- if (Unary && m != ((s+i) & (e-1)))
- return false;
- if (!Unary && m != (s+i))
+ if (m >= 0 && m != s+i)
return false;
}
return true;
@@ -3631,6 +3621,7 @@
if (Val >= 0)
break;
}
+ assert(Val - i > 0 && "PALIGNR imm should be positive");
return (Val - i) * EltSize;
}
@@ -3840,21 +3831,25 @@
}
/// getOnesVector - Returns a vector of specified type with all bits set.
-/// Always build ones vectors as <4 x i32> or <8 x i32> bitcasted to
-/// their original type, ensuring they get CSE'd.
+/// Always build ones vectors as <4 x i32>. For 256-bit types, use two
+/// <4 x i32> inserted in a <8 x i32> appropriately. Then bitcast to their
+/// original type, ensuring they get CSE'd.
static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
assert(VT.isVector() && "Expected a vector type");
assert((VT.is128BitVector() || VT.is256BitVector())
&& "Expected a 128-bit or 256-bit vector type");
SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
+ SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
+ Cst, Cst, Cst, Cst);
- SDValue Vec;
if (VT.is256BitVector()) {
- SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
- Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
- } else
- Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
+ SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32),
+ Vec, DAG.getConstant(0, MVT::i32), DAG, dl);
+ Vec = Insert128BitVector(InsV, Vec,
+ DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl);
+ }
+
return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
}
@@ -3964,6 +3959,34 @@
return DAG.getNode(ISD::BITCAST, dl, VT, V);
}
+/// PromoteVectorToScalarSplat - Since there's no native support for
+/// scalar_to_vector for 256-bit AVX, a 128-bit scalar_to_vector +
+/// INSERT_SUBVECTOR is generated. Recognize this idiom and do the
+/// shuffle before the insertion, this yields less instructions in the end.
+static SDValue PromoteVectorToScalarSplat(ShuffleVectorSDNode *SV,
+ SelectionDAG &DAG) {
+ EVT SrcVT = SV->getValueType(0);
+ SDValue V1 = SV->getOperand(0);
+ DebugLoc dl = SV->getDebugLoc();
+ int NumElems = SrcVT.getVectorNumElements();
+
+ assert(SrcVT.is256BitVector() && "unknown howto handle vector type");
+
+ SmallVector<int, 4> Mask;
+ for (int i = 0; i < NumElems/2; ++i)
+ Mask.push_back(SV->getMaskElt(i));
+
+ EVT SVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(),
+ NumElems/2);
+ SDValue SV1 = DAG.getVectorShuffle(SVT, dl, V1.getOperand(1),
+ DAG.getUNDEF(SVT), &Mask[0]);
+ SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), SV1,
+ DAG.getConstant(0, MVT::i32), DAG, dl);
+
+ return Insert128BitVector(InsV, SV1,
+ DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
+}
+
/// PromoteSplat - Promote a splat of v4i32, v8i16 or v16i8 to v4f32 and
/// v8i32, v16i16 or v32i8 to v8f32.
static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
@@ -5751,7 +5774,17 @@
if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
return Op;
- // Handle splats by matching through known masks
+ // Since there's no native support for scalar_to_vector for 256-bit AVX, a
+ // 128-bit scalar_to_vector + INSERT_SUBVECTOR is generated. Recognize this
+ // idiom and do the shuffle before the insertion, this yields less
+ // instructions in the end.
+ if (VT.is256BitVector() &&
+ V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
+ V1.getOperand(0).getOpcode() == ISD::UNDEF &&
+ V1.getOperand(1).getOpcode() == ISD::SCALAR_TO_VECTOR)
+ return PromoteVectorToScalarSplat(SVOp, DAG);
+
+ // Handle splats by matching through known shuffle masks
if ((VT.is128BitVector() && NumElem <= 4) ||
(VT.is256BitVector() && NumElem <= 8))
return SDValue();
@@ -6334,9 +6367,26 @@
SDValue
X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
+ LLVMContext *Context = DAG.getContext();
DebugLoc dl = Op.getDebugLoc();
EVT OpVT = Op.getValueType();
+ // If this is a 256-bit vector result, first insert into a 128-bit
+ // vector and then insert into the 256-bit vector.
+ if (OpVT.getSizeInBits() > 128) {
+ // Insert into a 128-bit vector.
+ EVT VT128 = EVT::getVectorVT(*Context,
+ OpVT.getVectorElementType(),
+ OpVT.getVectorNumElements() / 2);
+
+ Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
+
+ // Insert the 128-bit vector.
+ return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op,
+ DAG.getConstant(0, MVT::i32),
+ DAG, dl);
+ }
+
if (Op.getValueType() == MVT::v1i64 &&
Op.getOperand(0).getValueType() == MVT::i64)
return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
@@ -11977,6 +12027,35 @@
return SDValue();
}
+/// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
+/// so it can be folded inside ANDNP.
+static bool CanFoldXORWithAllOnes(const SDNode *N) {
+ EVT VT = N->getValueType(0);
+
+ // Match direct AllOnes for 128 and 256-bit vectors
+ if (ISD::isBuildVectorAllOnes(N))
+ return true;
+
+ // Look through a bit convert.
+ if (N->getOpcode() == ISD::BITCAST)
+ N = N->getOperand(0).getNode();
+
+ // Sometimes the operand may come from a insert_subvector building a 256-bit
+ // allones vector
+ SDValue V1 = N->getOperand(0);
+ SDValue V2 = N->getOperand(1);
+
+ if (VT.getSizeInBits() == 256 &&
+ N->getOpcode() == ISD::INSERT_SUBVECTOR &&
+ V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
+ V1.getOperand(0).getOpcode() == ISD::UNDEF &&
+ ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
+ ISD::isBuildVectorAllOnes(V2.getNode()))
+ return true;
+
+ return false;
+}
+
static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI,
const X86Subtarget *Subtarget) {
@@ -12001,12 +12080,14 @@
// Check LHS for vnot
if (N0.getOpcode() == ISD::XOR &&
- ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
+ //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
+ CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
// Check RHS for vnot
if (N1.getOpcode() == ISD::XOR &&
- ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
+ //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
+ CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
return SDValue();
Modified: llvm/branches/exception-handling-rewrite/lib/Target/X86/X86InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/X86/X86InstrFormats.td?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/X86/X86InstrFormats.td (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/X86/X86InstrFormats.td Mon Jul 25 20:29:47 2011
@@ -501,6 +501,9 @@
class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern>
: PDI<o, F, outs, ins, asm, pattern>, REX_W;
+class VRPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
+ list<dag> pattern>
+ : VPDI<o, F, outs, ins, asm, pattern>, VEX_W;
// MMX Instruction templates
//
Modified: llvm/branches/exception-handling-rewrite/lib/Target/X86/X86InstrFragmentsSIMD.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/X86/X86InstrFragmentsSIMD.td (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/X86/X86InstrFragmentsSIMD.td Mon Jul 25 20:29:47 2011
@@ -467,3 +467,4 @@
node:$index), [{
return X86::isVINSERTF128Index(N);
}], INSERT_get_vinsertf128_imm>;
+
Modified: llvm/branches/exception-handling-rewrite/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/X86/X86InstrInfo.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/X86/X86InstrInfo.cpp Mon Jul 25 20:29:47 2011
@@ -2450,6 +2450,7 @@
case X86::AVX_SET0PS:
case X86::AVX_SET0PD:
case X86::AVX_SET0PI:
+ case X86::AVX_SETALLONES:
Alignment = 16;
break;
case X86::FsFLD0SD:
@@ -2494,6 +2495,7 @@
case X86::AVX_SET0PI:
case X86::AVX_SET0PSY:
case X86::AVX_SET0PDY:
+ case X86::AVX_SETALLONES:
case X86::FsFLD0SD:
case X86::FsFLD0SS:
case X86::VFsFLD0SD:
@@ -2531,9 +2533,10 @@
Ty = VectorType::get(Type::getFloatTy(MF.getFunction()->getContext()), 8);
else
Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
- const Constant *C = LoadMI->getOpcode() == X86::V_SETALLONES ?
- Constant::getAllOnesValue(Ty) :
- Constant::getNullValue(Ty);
+
+ bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX_SETALLONES);
+ const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
+ Constant::getNullValue(Ty);
unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
// Create operands to load from the constant pool entry.
@@ -3013,31 +3016,6 @@
RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
}
-
-/// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher)
-/// register? e.g. r8, xmm8, xmm13, etc.
-bool X86InstrInfo::isX86_64ExtendedReg(unsigned RegNo) {
- switch (RegNo) {
- default: break;
- case X86::R8: case X86::R9: case X86::R10: case X86::R11:
- case X86::R12: case X86::R13: case X86::R14: case X86::R15:
- case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
- case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
- case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
- case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
- case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
- case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
- case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
- case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
- case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
- case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
- case X86::CR8: case X86::CR9: case X86::CR10: case X86::CR11:
- case X86::CR12: case X86::CR13: case X86::CR14: case X86::CR15:
- return true;
- }
- return false;
-}
-
/// getGlobalBaseReg - Return a virtual register initialized with the
/// the global base register value. Output instructions required to
/// initialize the register in the function entry block, if necessary.
Modified: llvm/branches/exception-handling-rewrite/lib/Target/X86/X86InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/X86/X86InstrInfo.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/X86/X86InstrInfo.h (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/X86/X86InstrInfo.h Mon Jul 25 20:29:47 2011
@@ -27,24 +27,6 @@
class X86TargetMachine;
namespace X86 {
- // Enums for memory operand decoding. Each memory operand is represented with
- // a 5 operand sequence in the form:
- // [BaseReg, ScaleAmt, IndexReg, Disp, Segment]
- // These enums help decode this.
- enum {
- AddrBaseReg = 0,
- AddrScaleAmt = 1,
- AddrIndexReg = 2,
- AddrDisp = 3,
-
- /// AddrSegmentReg - The operand # of the segment in the memory operand.
- AddrSegmentReg = 4,
-
- /// AddrNumOperands - Total number of operands in a memory reference.
- AddrNumOperands = 5
- };
-
-
// X86 specific condition code. These correspond to X86_*_COND in
// X86InstrInfo.td. They must be kept in synch.
enum CondCode {
@@ -82,133 +64,8 @@
/// GetOppositeBranchCondition - Return the inverse of the specified cond,
/// e.g. turning COND_E to COND_NE.
CondCode GetOppositeBranchCondition(X86::CondCode CC);
+} // end namespace X86;
-}
-
-/// X86II - This namespace holds all of the target specific flags that
-/// instruction info tracks.
-///
-namespace X86II {
- /// Target Operand Flag enum.
- enum TOF {
- //===------------------------------------------------------------------===//
- // X86 Specific MachineOperand flags.
-
- MO_NO_FLAG,
-
- /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a
- /// relocation of:
- /// SYMBOL_LABEL + [. - PICBASELABEL]
- MO_GOT_ABSOLUTE_ADDRESS,
-
- /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the
- /// immediate should get the value of the symbol minus the PIC base label:
- /// SYMBOL_LABEL - PICBASELABEL
- MO_PIC_BASE_OFFSET,
-
- /// MO_GOT - On a symbol operand this indicates that the immediate is the
- /// offset to the GOT entry for the symbol name from the base of the GOT.
- ///
- /// See the X86-64 ELF ABI supplement for more details.
- /// SYMBOL_LABEL @GOT
- MO_GOT,
-
- /// MO_GOTOFF - On a symbol operand this indicates that the immediate is
- /// the offset to the location of the symbol name from the base of the GOT.
- ///
- /// See the X86-64 ELF ABI supplement for more details.
- /// SYMBOL_LABEL @GOTOFF
- MO_GOTOFF,
-
- /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is
- /// offset to the GOT entry for the symbol name from the current code
- /// location.
- ///
- /// See the X86-64 ELF ABI supplement for more details.
- /// SYMBOL_LABEL @GOTPCREL
- MO_GOTPCREL,
-
- /// MO_PLT - On a symbol operand this indicates that the immediate is
- /// offset to the PLT entry of symbol name from the current code location.
- ///
- /// See the X86-64 ELF ABI supplement for more details.
- /// SYMBOL_LABEL @PLT
- MO_PLT,
-
- /// MO_TLSGD - On a symbol operand this indicates that the immediate is
- /// some TLS offset.
- ///
- /// See 'ELF Handling for Thread-Local Storage' for more details.
- /// SYMBOL_LABEL @TLSGD
- MO_TLSGD,
-
- /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is
- /// some TLS offset.
- ///
- /// See 'ELF Handling for Thread-Local Storage' for more details.
- /// SYMBOL_LABEL @GOTTPOFF
- MO_GOTTPOFF,
-
- /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is
- /// some TLS offset.
- ///
- /// See 'ELF Handling for Thread-Local Storage' for more details.
- /// SYMBOL_LABEL @INDNTPOFF
- MO_INDNTPOFF,
-
- /// MO_TPOFF - On a symbol operand this indicates that the immediate is
- /// some TLS offset.
- ///
- /// See 'ELF Handling for Thread-Local Storage' for more details.
- /// SYMBOL_LABEL @TPOFF
- MO_TPOFF,
-
- /// MO_NTPOFF - On a symbol operand this indicates that the immediate is
- /// some TLS offset.
- ///
- /// See 'ELF Handling for Thread-Local Storage' for more details.
- /// SYMBOL_LABEL @NTPOFF
- MO_NTPOFF,
-
- /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the
- /// reference is actually to the "__imp_FOO" symbol. This is used for
- /// dllimport linkage on windows.
- MO_DLLIMPORT,
-
- /// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the
- /// reference is actually to the "FOO$stub" symbol. This is used for calls
- /// and jumps to external functions on Tiger and earlier.
- MO_DARWIN_STUB,
-
- /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the
- /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a
- /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
- MO_DARWIN_NONLAZY,
-
- /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates
- /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is
- /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
- MO_DARWIN_NONLAZY_PIC_BASE,
-
- /// MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this
- /// indicates that the reference is actually to "FOO$non_lazy_ptr -PICBASE",
- /// which is a PIC-base-relative reference to a hidden dyld lazy pointer
- /// stub.
- MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE,
-
- /// MO_TLVP - On a symbol operand this indicates that the immediate is
- /// some TLS offset.
- ///
- /// This is the TLS offset for the Darwin TLS mechanism.
- MO_TLVP,
-
- /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate
- /// is some TLS offset from the picbase.
- ///
- /// This is the 32-bit TLS offset for Darwin TLS in PIC mode.
- MO_TLVP_PIC_BASE
- };
-}
/// isGlobalStubReference - Return true if the specified TargetFlag operand is
/// a reference to a stub for a global, not the global itself.
@@ -243,353 +100,6 @@
}
}
-/// X86II - This namespace holds all of the target specific flags that
-/// instruction info tracks.
-///
-namespace X86II {
- enum {
- //===------------------------------------------------------------------===//
- // Instruction encodings. These are the standard/most common forms for X86
- // instructions.
- //
-
- // PseudoFrm - This represents an instruction that is a pseudo instruction
- // or one that has not been implemented yet. It is illegal to code generate
- // it, but tolerated for intermediate implementation stages.
- Pseudo = 0,
-
- /// Raw - This form is for instructions that don't have any operands, so
- /// they are just a fixed opcode value, like 'leave'.
- RawFrm = 1,
-
- /// AddRegFrm - This form is used for instructions like 'push r32' that have
- /// their one register operand added to their opcode.
- AddRegFrm = 2,
-
- /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
- /// to specify a destination, which in this case is a register.
- ///
- MRMDestReg = 3,
-
- /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
- /// to specify a destination, which in this case is memory.
- ///
- MRMDestMem = 4,
-
- /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
- /// to specify a source, which in this case is a register.
- ///
- MRMSrcReg = 5,
-
- /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
- /// to specify a source, which in this case is memory.
- ///
- MRMSrcMem = 6,
-
- /// MRM[0-7][rm] - These forms are used to represent instructions that use
- /// a Mod/RM byte, and use the middle field to hold extended opcode
- /// information. In the intel manual these are represented as /0, /1, ...
- ///
-
- // First, instructions that operate on a register r/m operand...
- MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3
- MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7
-
- // Next, instructions that operate on a memory r/m operand...
- MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3
- MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7
-
- // MRMInitReg - This form is used for instructions whose source and
- // destinations are the same register.
- MRMInitReg = 32,
-
- //// MRM_C1 - A mod/rm byte of exactly 0xC1.
- MRM_C1 = 33,
- MRM_C2 = 34,
- MRM_C3 = 35,
- MRM_C4 = 36,
- MRM_C8 = 37,
- MRM_C9 = 38,
- MRM_E8 = 39,
- MRM_F0 = 40,
- MRM_F8 = 41,
- MRM_F9 = 42,
- MRM_D0 = 45,
- MRM_D1 = 46,
-
- /// RawFrmImm8 - This is used for the ENTER instruction, which has two
- /// immediates, the first of which is a 16-bit immediate (specified by
- /// the imm encoding) and the second is a 8-bit fixed value.
- RawFrmImm8 = 43,
-
- /// RawFrmImm16 - This is used for CALL FAR instructions, which have two
- /// immediates, the first of which is a 16 or 32-bit immediate (specified by
- /// the imm encoding) and the second is a 16-bit fixed value. In the AMD
- /// manual, this operand is described as pntr16:32 and pntr16:16
- RawFrmImm16 = 44,
-
- FormMask = 63,
-
- //===------------------------------------------------------------------===//
- // Actual flags...
-
- // OpSize - Set if this instruction requires an operand size prefix (0x66),
- // which most often indicates that the instruction operates on 16 bit data
- // instead of 32 bit data.
- OpSize = 1 << 6,
-
- // AsSize - Set if this instruction requires an operand size prefix (0x67),
- // which most often indicates that the instruction address 16 bit address
- // instead of 32 bit address (or 32 bit address in 64 bit mode).
- AdSize = 1 << 7,
-
- //===------------------------------------------------------------------===//
- // Op0Mask - There are several prefix bytes that are used to form two byte
- // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is
- // used to obtain the setting of this field. If no bits in this field is
- // set, there is no prefix byte for obtaining a multibyte opcode.
- //
- Op0Shift = 8,
- Op0Mask = 0x1F << Op0Shift,
-
- // TB - TwoByte - Set if this instruction has a two byte opcode, which
- // starts with a 0x0F byte before the real opcode.
- TB = 1 << Op0Shift,
-
- // REP - The 0xF3 prefix byte indicating repetition of the following
- // instruction.
- REP = 2 << Op0Shift,
-
- // D8-DF - These escape opcodes are used by the floating point unit. These
- // values must remain sequential.
- D8 = 3 << Op0Shift, D9 = 4 << Op0Shift,
- DA = 5 << Op0Shift, DB = 6 << Op0Shift,
- DC = 7 << Op0Shift, DD = 8 << Op0Shift,
- DE = 9 << Op0Shift, DF = 10 << Op0Shift,
-
- // XS, XD - These prefix codes are for single and double precision scalar
- // floating point operations performed in the SSE registers.
- XD = 11 << Op0Shift, XS = 12 << Op0Shift,
-
- // T8, TA, A6, A7 - Prefix after the 0x0F prefix.
- T8 = 13 << Op0Shift, TA = 14 << Op0Shift,
- A6 = 15 << Op0Shift, A7 = 16 << Op0Shift,
-
- // TF - Prefix before and after 0x0F
- TF = 17 << Op0Shift,
-
- //===------------------------------------------------------------------===//
- // REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
- // They are used to specify GPRs and SSE registers, 64-bit operand size,
- // etc. We only cares about REX.W and REX.R bits and only the former is
- // statically determined.
- //
- REXShift = Op0Shift + 5,
- REX_W = 1 << REXShift,
-
- //===------------------------------------------------------------------===//
- // This three-bit field describes the size of an immediate operand. Zero is
- // unused so that we can tell if we forgot to set a value.
- ImmShift = REXShift + 1,
- ImmMask = 7 << ImmShift,
- Imm8 = 1 << ImmShift,
- Imm8PCRel = 2 << ImmShift,
- Imm16 = 3 << ImmShift,
- Imm16PCRel = 4 << ImmShift,
- Imm32 = 5 << ImmShift,
- Imm32PCRel = 6 << ImmShift,
- Imm64 = 7 << ImmShift,
-
- //===------------------------------------------------------------------===//
- // FP Instruction Classification... Zero is non-fp instruction.
-
- // FPTypeMask - Mask for all of the FP types...
- FPTypeShift = ImmShift + 3,
- FPTypeMask = 7 << FPTypeShift,
-
- // NotFP - The default, set for instructions that do not use FP registers.
- NotFP = 0 << FPTypeShift,
-
- // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
- ZeroArgFP = 1 << FPTypeShift,
-
- // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
- OneArgFP = 2 << FPTypeShift,
-
- // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
- // result back to ST(0). For example, fcos, fsqrt, etc.
- //
- OneArgFPRW = 3 << FPTypeShift,
-
- // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
- // explicit argument, storing the result to either ST(0) or the implicit
- // argument. For example: fadd, fsub, fmul, etc...
- TwoArgFP = 4 << FPTypeShift,
-
- // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
- // explicit argument, but have no destination. Example: fucom, fucomi, ...
- CompareFP = 5 << FPTypeShift,
-
- // CondMovFP - "2 operand" floating point conditional move instructions.
- CondMovFP = 6 << FPTypeShift,
-
- // SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
- SpecialFP = 7 << FPTypeShift,
-
- // Lock prefix
- LOCKShift = FPTypeShift + 3,
- LOCK = 1 << LOCKShift,
-
- // Segment override prefixes. Currently we just need ability to address
- // stuff in gs and fs segments.
- SegOvrShift = LOCKShift + 1,
- SegOvrMask = 3 << SegOvrShift,
- FS = 1 << SegOvrShift,
- GS = 2 << SegOvrShift,
-
- // Execution domain for SSE instructions in bits 23, 24.
- // 0 in bits 23-24 means normal, non-SSE instruction.
- SSEDomainShift = SegOvrShift + 2,
-
- OpcodeShift = SSEDomainShift + 2,
-
- //===------------------------------------------------------------------===//
- /// VEX - The opcode prefix used by AVX instructions
- VEXShift = OpcodeShift + 8,
- VEX = 1U << 0,
-
- /// VEX_W - Has a opcode specific functionality, but is used in the same
- /// way as REX_W is for regular SSE instructions.
- VEX_W = 1U << 1,
-
- /// VEX_4V - Used to specify an additional AVX/SSE register. Several 2
- /// address instructions in SSE are represented as 3 address ones in AVX
- /// and the additional register is encoded in VEX_VVVV prefix.
- VEX_4V = 1U << 2,
-
- /// VEX_I8IMM - Specifies that the last register used in a AVX instruction,
- /// must be encoded in the i8 immediate field. This usually happens in
- /// instructions with 4 operands.
- VEX_I8IMM = 1U << 3,
-
- /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current
- /// instruction uses 256-bit wide registers. This is usually auto detected
- /// if a VR256 register is used, but some AVX instructions also have this
- /// field marked when using a f256 memory references.
- VEX_L = 1U << 4,
-
- /// Has3DNow0F0FOpcode - This flag indicates that the instruction uses the
- /// wacky 0x0F 0x0F prefix for 3DNow! instructions. The manual documents
- /// this as having a 0x0F prefix with a 0x0F opcode, and each instruction
- /// storing a classifier in the imm8 field. To simplify our implementation,
- /// we handle this by storeing the classifier in the opcode field and using
- /// this flag to indicate that the encoder should do the wacky 3DNow! thing.
- Has3DNow0F0FOpcode = 1U << 5
- };
-
- // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
- // specified machine instruction.
- //
- static inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) {
- return TSFlags >> X86II::OpcodeShift;
- }
-
- static inline bool hasImm(uint64_t TSFlags) {
- return (TSFlags & X86II::ImmMask) != 0;
- }
-
- /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field
- /// of the specified instruction.
- static inline unsigned getSizeOfImm(uint64_t TSFlags) {
- switch (TSFlags & X86II::ImmMask) {
- default: assert(0 && "Unknown immediate size");
- case X86II::Imm8:
- case X86II::Imm8PCRel: return 1;
- case X86II::Imm16:
- case X86II::Imm16PCRel: return 2;
- case X86II::Imm32:
- case X86II::Imm32PCRel: return 4;
- case X86II::Imm64: return 8;
- }
- }
-
- /// isImmPCRel - Return true if the immediate of the specified instruction's
- /// TSFlags indicates that it is pc relative.
- static inline unsigned isImmPCRel(uint64_t TSFlags) {
- switch (TSFlags & X86II::ImmMask) {
- default: assert(0 && "Unknown immediate size");
- case X86II::Imm8PCRel:
- case X86II::Imm16PCRel:
- case X86II::Imm32PCRel:
- return true;
- case X86II::Imm8:
- case X86II::Imm16:
- case X86II::Imm32:
- case X86II::Imm64:
- return false;
- }
- }
-
- /// getMemoryOperandNo - The function returns the MCInst operand # for the
- /// first field of the memory operand. If the instruction doesn't have a
- /// memory operand, this returns -1.
- ///
- /// Note that this ignores tied operands. If there is a tied register which
- /// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only
- /// counted as one operand.
- ///
- static inline int getMemoryOperandNo(uint64_t TSFlags) {
- switch (TSFlags & X86II::FormMask) {
- case X86II::MRMInitReg: assert(0 && "FIXME: Remove this form");
- default: assert(0 && "Unknown FormMask value in getMemoryOperandNo!");
- case X86II::Pseudo:
- case X86II::RawFrm:
- case X86II::AddRegFrm:
- case X86II::MRMDestReg:
- case X86II::MRMSrcReg:
- case X86II::RawFrmImm8:
- case X86II::RawFrmImm16:
- return -1;
- case X86II::MRMDestMem:
- return 0;
- case X86II::MRMSrcMem: {
- bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
- unsigned FirstMemOp = 1;
- if (HasVEX_4V)
- ++FirstMemOp;// Skip the register source (which is encoded in VEX_VVVV).
-
- // FIXME: Maybe lea should have its own form? This is a horrible hack.
- //if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
- // Opcode == X86::LEA16r || Opcode == X86::LEA32r)
- return FirstMemOp;
- }
- case X86II::MRM0r: case X86II::MRM1r:
- case X86II::MRM2r: case X86II::MRM3r:
- case X86II::MRM4r: case X86II::MRM5r:
- case X86II::MRM6r: case X86II::MRM7r:
- return -1;
- case X86II::MRM0m: case X86II::MRM1m:
- case X86II::MRM2m: case X86II::MRM3m:
- case X86II::MRM4m: case X86II::MRM5m:
- case X86II::MRM6m: case X86II::MRM7m:
- return 0;
- case X86II::MRM_C1:
- case X86II::MRM_C2:
- case X86II::MRM_C3:
- case X86II::MRM_C4:
- case X86II::MRM_C8:
- case X86II::MRM_C9:
- case X86II::MRM_E8:
- case X86II::MRM_F0:
- case X86II::MRM_F8:
- case X86II::MRM_F9:
- case X86II::MRM_D0:
- case X86II::MRM_D1:
- return -1;
- }
- }
-}
-
inline static bool isScale(const MachineOperand &MO) {
return MO.isImm() &&
(MO.getImm() == 1 || MO.getImm() == 2 ||
@@ -829,20 +339,11 @@
/// instruction that defines the specified register class.
bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
- static bool isX86_64NonExtLowByteReg(unsigned reg) {
- return (reg == X86::SPL || reg == X86::BPL ||
- reg == X86::SIL || reg == X86::DIL);
- }
-
static bool isX86_64ExtendedReg(const MachineOperand &MO) {
if (!MO.isReg()) return false;
- return isX86_64ExtendedReg(MO.getReg());
+ return X86II::isX86_64ExtendedReg(MO.getReg());
}
- /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or
- /// higher) register? e.g. r8, xmm8, xmm13, etc.
- static bool isX86_64ExtendedReg(unsigned RegNo);
-
/// getGlobalBaseReg - Return a virtual register initialized with the
/// the global base register value. Output instructions required to
/// initialize the register in the function entry block, if necessary.
Modified: llvm/branches/exception-handling-rewrite/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/X86/X86InstrSSE.td?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/X86/X86InstrSSE.td Mon Jul 25 20:29:47 2011
@@ -2858,6 +2858,14 @@
[(set VR128:$dst,
(v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
VEX;
+def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
+ "mov{d|q}\t{$src, $dst|$dst, $src}",
+ [(set VR128:$dst,
+ (v2i64 (scalar_to_vector GR64:$src)))]>, VEX;
+def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
+ "mov{d|q}\t{$src, $dst|$dst, $src}",
+ [(set FR64:$dst, (bitconvert GR64:$src))]>, VEX;
+
def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
"movd\t{$src, $dst|$dst, $src}",
[(set VR128:$dst,
@@ -3135,11 +3143,17 @@
// Alias instructions that map zero vector to pxor / xorp* for sse.
// We set canFoldAsLoad because this can be converted to a constant-pool
// load of an all-ones value if folding it would be beneficial.
+// FIXME: Change encoding to pseudo! This is blocked right now by the x86
+// JIT implementation, it does not expand the instructions below like
+// X86MCInstLower does.
let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
- // FIXME: Change encoding to pseudo.
def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
[(set VR128:$dst, (v4i32 immAllOnesV))]>;
+let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
+ isCodeGenOnly = 1, ExeDomain = SSEPackedInt, Predicates = [HasAVX] in
+ def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
+ [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
//===---------------------------------------------------------------------===//
// SSE3 - Conversion Instructions
@@ -3631,9 +3645,8 @@
def : Pat<(fextend (loadf32 addr:$src)),
(CVTSS2SDrm addr:$src)>;
-
-
-// bit_convert
+// Bitcasts between 128-bit vector types. Return the original type since
+// no instruction is needed for the conversion
let Predicates = [HasXMMInt] in {
def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
@@ -3667,24 +3680,39 @@
def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
}
+// Bitcasts between 256-bit vector types. Return the original type since
+// no instruction is needed for the conversion
let Predicates = [HasAVX] in {
def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
+ def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
+ def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
+ def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
- def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
+ def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
+ def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
+ def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
+ def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
+ def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
+ def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
+ def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
+ def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
+ def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
+ def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
+ def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
}
// Move scalar to XMM zero-extended
@@ -5358,6 +5386,20 @@
(VINSERTF128rr VR256:$src1, VR128:$src2,
(INSERT_get_vinsertf128_imm VR256:$ins))>;
+// Special COPY patterns
+def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
+ (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
+def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)),
+ (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
+def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)),
+ (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
+def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)),
+ (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
+def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)),
+ (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
+def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)),
+ (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
+
//===----------------------------------------------------------------------===//
// VEXTRACTF128 - Extract packed floating-point values
//
Removed: llvm/branches/exception-handling-rewrite/lib/Target/X86/X86MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/X86/X86MCCodeEmitter.cpp?rev=136039&view=auto
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/X86/X86MCCodeEmitter.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/X86/X86MCCodeEmitter.cpp (removed)
@@ -1,1046 +0,0 @@
-//===-- X86/X86MCCodeEmitter.cpp - Convert X86 code to machine code -------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file implements the X86MCCodeEmitter class.
-//
-//===----------------------------------------------------------------------===//
-
-#define DEBUG_TYPE "mccodeemitter"
-#include "X86.h"
-#include "X86InstrInfo.h"
-#include "X86FixupKinds.h"
-#include "llvm/MC/MCCodeEmitter.h"
-#include "llvm/MC/MCExpr.h"
-#include "llvm/MC/MCInst.h"
-#include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/MC/MCSymbol.h"
-#include "llvm/Support/raw_ostream.h"
-
-using namespace llvm;
-
-namespace {
-class X86MCCodeEmitter : public MCCodeEmitter {
- X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
- void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
- const MCInstrInfo &MCII;
- const MCSubtargetInfo &STI;
- MCContext &Ctx;
-public:
- X86MCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
- MCContext &ctx)
- : MCII(mcii), STI(sti), Ctx(ctx) {
- }
-
- ~X86MCCodeEmitter() {}
-
- bool is64BitMode() const {
- // FIXME: Can tablegen auto-generate this?
- return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
- }
-
- static unsigned GetX86RegNum(const MCOperand &MO) {
- return X86_MC::getX86RegNum(MO.getReg());
- }
-
- // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range
- // 0-7 and the difference between the 2 groups is given by the REX prefix.
- // In the VEX prefix, registers are seen sequencially from 0-15 and encoded
- // in 1's complement form, example:
- //
- // ModRM field => XMM9 => 1
- // VEX.VVVV => XMM9 => ~9
- //
- // See table 4-35 of Intel AVX Programming Reference for details.
- static unsigned char getVEXRegisterEncoding(const MCInst &MI,
- unsigned OpNum) {
- unsigned SrcReg = MI.getOperand(OpNum).getReg();
- unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
- if ((SrcReg >= X86::XMM8 && SrcReg <= X86::XMM15) ||
- (SrcReg >= X86::YMM8 && SrcReg <= X86::YMM15))
- SrcRegNum += 8;
-
- // The registers represented through VEX_VVVV should
- // be encoded in 1's complement form.
- return (~SrcRegNum) & 0xf;
- }
-
- void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
- OS << (char)C;
- ++CurByte;
- }
-
- void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
- raw_ostream &OS) const {
- // Output the constant in little endian byte order.
- for (unsigned i = 0; i != Size; ++i) {
- EmitByte(Val & 255, CurByte, OS);
- Val >>= 8;
- }
- }
-
- void EmitImmediate(const MCOperand &Disp,
- unsigned ImmSize, MCFixupKind FixupKind,
- unsigned &CurByte, raw_ostream &OS,
- SmallVectorImpl<MCFixup> &Fixups,
- int ImmOffset = 0) const;
-
- inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
- unsigned RM) {
- assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
- return RM | (RegOpcode << 3) | (Mod << 6);
- }
-
- void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
- unsigned &CurByte, raw_ostream &OS) const {
- EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
- }
-
- void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
- unsigned &CurByte, raw_ostream &OS) const {
- // SIB byte is in the same format as the ModRMByte.
- EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
- }
-
-
- void EmitMemModRMByte(const MCInst &MI, unsigned Op,
- unsigned RegOpcodeField,
- uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS,
- SmallVectorImpl<MCFixup> &Fixups) const;
-
- void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
- SmallVectorImpl<MCFixup> &Fixups) const;
-
- void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
- const MCInst &MI, const MCInstrDesc &Desc,
- raw_ostream &OS) const;
-
- void EmitSegmentOverridePrefix(uint64_t TSFlags, unsigned &CurByte,
- int MemOperand, const MCInst &MI,
- raw_ostream &OS) const;
-
- void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
- const MCInst &MI, const MCInstrDesc &Desc,
- raw_ostream &OS) const;
-};
-
-} // end anonymous namespace
-
-
-MCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII,
- const MCSubtargetInfo &STI,
- MCContext &Ctx) {
- return new X86MCCodeEmitter(MCII, STI, Ctx);
-}
-
-/// isDisp8 - Return true if this signed displacement fits in a 8-bit
-/// sign-extended field.
-static bool isDisp8(int Value) {
- return Value == (signed char)Value;
-}
-
-/// getImmFixupKind - Return the appropriate fixup kind to use for an immediate
-/// in an instruction with the specified TSFlags.
-static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
- unsigned Size = X86II::getSizeOfImm(TSFlags);
- bool isPCRel = X86II::isImmPCRel(TSFlags);
-
- return MCFixup::getKindForSize(Size, isPCRel);
-}
-
-/// Is32BitMemOperand - Return true if the specified instruction with a memory
-/// operand should emit the 0x67 prefix byte in 64-bit mode due to a 32-bit
-/// memory operand. Op specifies the operand # of the memoperand.
-static bool Is32BitMemOperand(const MCInst &MI, unsigned Op) {
- const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
- const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
-
- if ((BaseReg.getReg() != 0 && X86::GR32RegClass.contains(BaseReg.getReg())) ||
- (IndexReg.getReg() != 0 && X86::GR32RegClass.contains(IndexReg.getReg())))
- return true;
- return false;
-}
-
-/// StartsWithGlobalOffsetTable - Return true for the simple cases where this
-/// expression starts with _GLOBAL_OFFSET_TABLE_. This is a needed to support
-/// PIC on ELF i386 as that symbol is magic. We check only simple case that
-/// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start
-/// of a binary expression.
-static bool StartsWithGlobalOffsetTable(const MCExpr *Expr) {
- if (Expr->getKind() == MCExpr::Binary) {
- const MCBinaryExpr *BE = static_cast<const MCBinaryExpr *>(Expr);
- Expr = BE->getLHS();
- }
-
- if (Expr->getKind() != MCExpr::SymbolRef)
- return false;
-
- const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
- const MCSymbol &S = Ref->getSymbol();
- return S.getName() == "_GLOBAL_OFFSET_TABLE_";
-}
-
-void X86MCCodeEmitter::
-EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind,
- unsigned &CurByte, raw_ostream &OS,
- SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const {
- const MCExpr *Expr = NULL;
- if (DispOp.isImm()) {
- // If this is a simple integer displacement that doesn't require a relocation,
- // emit it now.
- if (FixupKind != FK_PCRel_1 &&
- FixupKind != FK_PCRel_2 &&
- FixupKind != FK_PCRel_4) {
- EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS);
- return;
- }
- Expr = MCConstantExpr::Create(DispOp.getImm(), Ctx);
- } else {
- Expr = DispOp.getExpr();
- }
-
- // If we have an immoffset, add it to the expression.
- if ((FixupKind == FK_Data_4 ||
- FixupKind == MCFixupKind(X86::reloc_signed_4byte)) &&
- StartsWithGlobalOffsetTable(Expr)) {
- assert(ImmOffset == 0);
-
- FixupKind = MCFixupKind(X86::reloc_global_offset_table);
- ImmOffset = CurByte;
- }
-
- // If the fixup is pc-relative, we need to bias the value to be relative to
- // the start of the field, not the end of the field.
- if (FixupKind == FK_PCRel_4 ||
- FixupKind == MCFixupKind(X86::reloc_riprel_4byte) ||
- FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load))
- ImmOffset -= 4;
- if (FixupKind == FK_PCRel_2)
- ImmOffset -= 2;
- if (FixupKind == FK_PCRel_1)
- ImmOffset -= 1;
-
- if (ImmOffset)
- Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(ImmOffset, Ctx),
- Ctx);
-
- // Emit a symbolic constant as a fixup and 4 zeros.
- Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind));
- EmitConstant(0, Size, CurByte, OS);
-}
-
-void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
- unsigned RegOpcodeField,
- uint64_t TSFlags, unsigned &CurByte,
- raw_ostream &OS,
- SmallVectorImpl<MCFixup> &Fixups) const{
- const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp);
- const MCOperand &Base = MI.getOperand(Op+X86::AddrBaseReg);
- const MCOperand &Scale = MI.getOperand(Op+X86::AddrScaleAmt);
- const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
- unsigned BaseReg = Base.getReg();
-
- // Handle %rip relative addressing.
- if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
- assert(is64BitMode() && "Rip-relative addressing requires 64-bit mode");
- assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
- EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
-
- unsigned FixupKind = X86::reloc_riprel_4byte;
-
- // movq loads are handled with a special relocation form which allows the
- // linker to eliminate some loads for GOT references which end up in the
- // same linkage unit.
- if (MI.getOpcode() == X86::MOV64rm)
- FixupKind = X86::reloc_riprel_4byte_movq_load;
-
- // rip-relative addressing is actually relative to the *next* instruction.
- // Since an immediate can follow the mod/rm byte for an instruction, this
- // means that we need to bias the immediate field of the instruction with
- // the size of the immediate field. If we have this case, add it into the
- // expression to emit.
- int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0;
-
- EmitImmediate(Disp, 4, MCFixupKind(FixupKind),
- CurByte, OS, Fixups, -ImmSize);
- return;
- }
-
- unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
-
- // Determine whether a SIB byte is needed.
- // If no BaseReg, issue a RIP relative instruction only if the MCE can
- // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
- // 2-7) and absolute references.
-
- if (// The SIB byte must be used if there is an index register.
- IndexReg.getReg() == 0 &&
- // The SIB byte must be used if the base is ESP/RSP/R12, all of which
- // encode to an R/M value of 4, which indicates that a SIB byte is
- // present.
- BaseRegNo != N86::ESP &&
- // If there is no base register and we're in 64-bit mode, we need a SIB
- // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
- (!is64BitMode() || BaseReg != 0)) {
-
- if (BaseReg == 0) { // [disp32] in X86-32 mode
- EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
- EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
- return;
- }
-
- // If the base is not EBP/ESP and there is no displacement, use simple
- // indirect register encoding, this handles addresses like [EAX]. The
- // encoding for [EBP] with no displacement means [disp32] so we handle it
- // by emitting a displacement of 0 below.
- if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
- EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
- return;
- }
-
- // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
- if (Disp.isImm() && isDisp8(Disp.getImm())) {
- EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
- EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
- return;
- }
-
- // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
- EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
- EmitImmediate(Disp, 4, MCFixupKind(X86::reloc_signed_4byte), CurByte, OS,
- Fixups);
- return;
- }
-
- // We need a SIB byte, so start by outputting the ModR/M byte first
- assert(IndexReg.getReg() != X86::ESP &&
- IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
-
- bool ForceDisp32 = false;
- bool ForceDisp8 = false;
- if (BaseReg == 0) {
- // If there is no base register, we emit the special case SIB byte with
- // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
- EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
- ForceDisp32 = true;
- } else if (!Disp.isImm()) {
- // Emit the normal disp32 encoding.
- EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
- ForceDisp32 = true;
- } else if (Disp.getImm() == 0 &&
- // Base reg can't be anything that ends up with '5' as the base
- // reg, it is the magic [*] nomenclature that indicates no base.
- BaseRegNo != N86::EBP) {
- // Emit no displacement ModR/M byte
- EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
- } else if (isDisp8(Disp.getImm())) {
- // Emit the disp8 encoding.
- EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
- ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
- } else {
- // Emit the normal disp32 encoding.
- EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
- }
-
- // Calculate what the SS field value should be...
- static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
- unsigned SS = SSTable[Scale.getImm()];
-
- if (BaseReg == 0) {
- // Handle the SIB byte for the case where there is no base, see Intel
- // Manual 2A, table 2-7. The displacement has already been output.
- unsigned IndexRegNo;
- if (IndexReg.getReg())
- IndexRegNo = GetX86RegNum(IndexReg);
- else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
- IndexRegNo = 4;
- EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
- } else {
- unsigned IndexRegNo;
- if (IndexReg.getReg())
- IndexRegNo = GetX86RegNum(IndexReg);
- else
- IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
- EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
- }
-
- // Do we need to output a displacement?
- if (ForceDisp8)
- EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
- else if (ForceDisp32 || Disp.getImm() != 0)
- EmitImmediate(Disp, 4, MCFixupKind(X86::reloc_signed_4byte), CurByte, OS,
- Fixups);
-}
-
-/// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
-/// called VEX.
-void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
- int MemOperand, const MCInst &MI,
- const MCInstrDesc &Desc,
- raw_ostream &OS) const {
- bool HasVEX_4V = false;
- if ((TSFlags >> X86II::VEXShift) & X86II::VEX_4V)
- HasVEX_4V = true;
-
- // VEX_R: opcode externsion equivalent to REX.R in
- // 1's complement (inverted) form
- //
- // 1: Same as REX_R=0 (must be 1 in 32-bit mode)
- // 0: Same as REX_R=1 (64 bit mode only)
- //
- unsigned char VEX_R = 0x1;
-
- // VEX_X: equivalent to REX.X, only used when a
- // register is used for index in SIB Byte.
- //
- // 1: Same as REX.X=0 (must be 1 in 32-bit mode)
- // 0: Same as REX.X=1 (64-bit mode only)
- unsigned char VEX_X = 0x1;
-
- // VEX_B:
- //
- // 1: Same as REX_B=0 (ignored in 32-bit mode)
- // 0: Same as REX_B=1 (64 bit mode only)
- //
- unsigned char VEX_B = 0x1;
-
- // VEX_W: opcode specific (use like REX.W, or used for
- // opcode extension, or ignored, depending on the opcode byte)
- unsigned char VEX_W = 0;
-
- // VEX_5M (VEX m-mmmmm field):
- //
- // 0b00000: Reserved for future use
- // 0b00001: implied 0F leading opcode
- // 0b00010: implied 0F 38 leading opcode bytes
- // 0b00011: implied 0F 3A leading opcode bytes
- // 0b00100-0b11111: Reserved for future use
- //
- unsigned char VEX_5M = 0x1;
-
- // VEX_4V (VEX vvvv field): a register specifier
- // (in 1's complement form) or 1111 if unused.
- unsigned char VEX_4V = 0xf;
-
- // VEX_L (Vector Length):
- //
- // 0: scalar or 128-bit vector
- // 1: 256-bit vector
- //
- unsigned char VEX_L = 0;
-
- // VEX_PP: opcode extension providing equivalent
- // functionality of a SIMD prefix
- //
- // 0b00: None
- // 0b01: 66
- // 0b10: F3
- // 0b11: F2
- //
- unsigned char VEX_PP = 0;
-
- // Encode the operand size opcode prefix as needed.
- if (TSFlags & X86II::OpSize)
- VEX_PP = 0x01;
-
- if ((TSFlags >> X86II::VEXShift) & X86II::VEX_W)
- VEX_W = 1;
-
- if ((TSFlags >> X86II::VEXShift) & X86II::VEX_L)
- VEX_L = 1;
-
- switch (TSFlags & X86II::Op0Mask) {
- default: assert(0 && "Invalid prefix!");
- case X86II::T8: // 0F 38
- VEX_5M = 0x2;
- break;
- case X86II::TA: // 0F 3A
- VEX_5M = 0x3;
- break;
- case X86II::TF: // F2 0F 38
- VEX_PP = 0x3;
- VEX_5M = 0x2;
- break;
- case X86II::XS: // F3 0F
- VEX_PP = 0x2;
- break;
- case X86II::XD: // F2 0F
- VEX_PP = 0x3;
- break;
- case X86II::A6: // Bypass: Not used by VEX
- case X86II::A7: // Bypass: Not used by VEX
- case X86II::TB: // Bypass: Not used by VEX
- case 0:
- break; // No prefix!
- }
-
- // Set the vector length to 256-bit if YMM0-YMM15 is used
- for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
- if (!MI.getOperand(i).isReg())
- continue;
- unsigned SrcReg = MI.getOperand(i).getReg();
- if (SrcReg >= X86::YMM0 && SrcReg <= X86::YMM15)
- VEX_L = 1;
- }
-
- unsigned NumOps = MI.getNumOperands();
- unsigned CurOp = 0;
- bool IsDestMem = false;
-
- switch (TSFlags & X86II::FormMask) {
- case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
- case X86II::MRMDestMem:
- IsDestMem = true;
- // The important info for the VEX prefix is never beyond the address
- // registers. Don't check beyond that.
- NumOps = CurOp = X86::AddrNumOperands;
- case X86II::MRM0m: case X86II::MRM1m:
- case X86II::MRM2m: case X86II::MRM3m:
- case X86II::MRM4m: case X86II::MRM5m:
- case X86II::MRM6m: case X86II::MRM7m:
- case X86II::MRMSrcMem:
- case X86II::MRMSrcReg:
- if (MI.getNumOperands() > CurOp && MI.getOperand(CurOp).isReg() &&
- X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
- VEX_R = 0x0;
- CurOp++;
-
- if (HasVEX_4V) {
- VEX_4V = getVEXRegisterEncoding(MI, IsDestMem ? CurOp-1 : CurOp);
- CurOp++;
- }
-
- // To only check operands before the memory address ones, start
- // the search from the beginning
- if (IsDestMem)
- CurOp = 0;
-
- // If the last register should be encoded in the immediate field
- // do not use any bit from VEX prefix to this register, ignore it
- if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM)
- NumOps--;
-
- for (; CurOp != NumOps; ++CurOp) {
- const MCOperand &MO = MI.getOperand(CurOp);
- if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
- VEX_B = 0x0;
- if (!VEX_B && MO.isReg() &&
- ((TSFlags & X86II::FormMask) == X86II::MRMSrcMem) &&
- X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
- VEX_X = 0x0;
- }
- break;
- default: // MRMDestReg, MRM0r-MRM7r, RawFrm
- if (!MI.getNumOperands())
- break;
-
- if (MI.getOperand(CurOp).isReg() &&
- X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
- VEX_B = 0;
-
- if (HasVEX_4V)
- VEX_4V = getVEXRegisterEncoding(MI, CurOp);
-
- CurOp++;
- for (; CurOp != NumOps; ++CurOp) {
- const MCOperand &MO = MI.getOperand(CurOp);
- if (MO.isReg() && !HasVEX_4V &&
- X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
- VEX_R = 0x0;
- }
- break;
- }
-
- // Emit segment override opcode prefix as needed.
- EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS);
-
- // VEX opcode prefix can have 2 or 3 bytes
- //
- // 3 bytes:
- // +-----+ +--------------+ +-------------------+
- // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
- // +-----+ +--------------+ +-------------------+
- // 2 bytes:
- // +-----+ +-------------------+
- // | C5h | | R | vvvv | L | pp |
- // +-----+ +-------------------+
- //
- unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
-
- if (VEX_B && VEX_X && !VEX_W && (VEX_5M == 1)) { // 2 byte VEX prefix
- EmitByte(0xC5, CurByte, OS);
- EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
- return;
- }
-
- // 3 byte VEX prefix
- EmitByte(0xC4, CurByte, OS);
- EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS);
- EmitByte(LastByte | (VEX_W << 7), CurByte, OS);
-}
-
-/// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
-/// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
-/// size, and 3) use of X86-64 extended registers.
-static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
- const MCInstrDesc &Desc) {
- unsigned REX = 0;
- if (TSFlags & X86II::REX_W)
- REX |= 1 << 3; // set REX.W
-
- if (MI.getNumOperands() == 0) return REX;
-
- unsigned NumOps = MI.getNumOperands();
- // FIXME: MCInst should explicitize the two-addrness.
- bool isTwoAddr = NumOps > 1 &&
- Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1;
-
- // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
- unsigned i = isTwoAddr ? 1 : 0;
- for (; i != NumOps; ++i) {
- const MCOperand &MO = MI.getOperand(i);
- if (!MO.isReg()) continue;
- unsigned Reg = MO.getReg();
- if (!X86InstrInfo::isX86_64NonExtLowByteReg(Reg)) continue;
- // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
- // that returns non-zero.
- REX |= 0x40; // REX fixed encoding prefix
- break;
- }
-
- switch (TSFlags & X86II::FormMask) {
- case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
- case X86II::MRMSrcReg:
- if (MI.getOperand(0).isReg() &&
- X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
- REX |= 1 << 2; // set REX.R
- i = isTwoAddr ? 2 : 1;
- for (; i != NumOps; ++i) {
- const MCOperand &MO = MI.getOperand(i);
- if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
- REX |= 1 << 0; // set REX.B
- }
- break;
- case X86II::MRMSrcMem: {
- if (MI.getOperand(0).isReg() &&
- X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
- REX |= 1 << 2; // set REX.R
- unsigned Bit = 0;
- i = isTwoAddr ? 2 : 1;
- for (; i != NumOps; ++i) {
- const MCOperand &MO = MI.getOperand(i);
- if (MO.isReg()) {
- if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
- REX |= 1 << Bit; // set REX.B (Bit=0) and REX.X (Bit=1)
- Bit++;
- }
- }
- break;
- }
- case X86II::MRM0m: case X86II::MRM1m:
- case X86II::MRM2m: case X86II::MRM3m:
- case X86II::MRM4m: case X86II::MRM5m:
- case X86II::MRM6m: case X86II::MRM7m:
- case X86II::MRMDestMem: {
- unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands);
- i = isTwoAddr ? 1 : 0;
- if (NumOps > e && MI.getOperand(e).isReg() &&
- X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
- REX |= 1 << 2; // set REX.R
- unsigned Bit = 0;
- for (; i != e; ++i) {
- const MCOperand &MO = MI.getOperand(i);
- if (MO.isReg()) {
- if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
- REX |= 1 << Bit; // REX.B (Bit=0) and REX.X (Bit=1)
- Bit++;
- }
- }
- break;
- }
- default:
- if (MI.getOperand(0).isReg() &&
- X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
- REX |= 1 << 0; // set REX.B
- i = isTwoAddr ? 2 : 1;
- for (unsigned e = NumOps; i != e; ++i) {
- const MCOperand &MO = MI.getOperand(i);
- if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
- REX |= 1 << 2; // set REX.R
- }
- break;
- }
- return REX;
-}
-
-/// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed
-void X86MCCodeEmitter::EmitSegmentOverridePrefix(uint64_t TSFlags,
- unsigned &CurByte, int MemOperand,
- const MCInst &MI,
- raw_ostream &OS) const {
- switch (TSFlags & X86II::SegOvrMask) {
- default: assert(0 && "Invalid segment!");
- case 0:
- // No segment override, check for explicit one on memory operand.
- if (MemOperand != -1) { // If the instruction has a memory operand.
- switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) {
- default: assert(0 && "Unknown segment register!");
- case 0: break;
- case X86::CS: EmitByte(0x2E, CurByte, OS); break;
- case X86::SS: EmitByte(0x36, CurByte, OS); break;
- case X86::DS: EmitByte(0x3E, CurByte, OS); break;
- case X86::ES: EmitByte(0x26, CurByte, OS); break;
- case X86::FS: EmitByte(0x64, CurByte, OS); break;
- case X86::GS: EmitByte(0x65, CurByte, OS); break;
- }
- }
- break;
- case X86II::FS:
- EmitByte(0x64, CurByte, OS);
- break;
- case X86II::GS:
- EmitByte(0x65, CurByte, OS);
- break;
- }
-}
-
-/// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode.
-///
-/// MemOperand is the operand # of the start of a memory operand if present. If
-/// Not present, it is -1.
-void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
- int MemOperand, const MCInst &MI,
- const MCInstrDesc &Desc,
- raw_ostream &OS) const {
-
- // Emit the lock opcode prefix as needed.
- if (TSFlags & X86II::LOCK)
- EmitByte(0xF0, CurByte, OS);
-
- // Emit segment override opcode prefix as needed.
- EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS);
-
- // Emit the repeat opcode prefix as needed.
- if ((TSFlags & X86II::Op0Mask) == X86II::REP)
- EmitByte(0xF3, CurByte, OS);
-
- // Emit the address size opcode prefix as needed.
- if ((TSFlags & X86II::AdSize) ||
- (MemOperand != -1 && is64BitMode() && Is32BitMemOperand(MI, MemOperand)))
- EmitByte(0x67, CurByte, OS);
-
- // Emit the operand size opcode prefix as needed.
- if (TSFlags & X86II::OpSize)
- EmitByte(0x66, CurByte, OS);
-
- bool Need0FPrefix = false;
- switch (TSFlags & X86II::Op0Mask) {
- default: assert(0 && "Invalid prefix!");
- case 0: break; // No prefix!
- case X86II::REP: break; // already handled.
- case X86II::TB: // Two-byte opcode prefix
- case X86II::T8: // 0F 38
- case X86II::TA: // 0F 3A
- case X86II::A6: // 0F A6
- case X86II::A7: // 0F A7
- Need0FPrefix = true;
- break;
- case X86II::TF: // F2 0F 38
- EmitByte(0xF2, CurByte, OS);
- Need0FPrefix = true;
- break;
- case X86II::XS: // F3 0F
- EmitByte(0xF3, CurByte, OS);
- Need0FPrefix = true;
- break;
- case X86II::XD: // F2 0F
- EmitByte(0xF2, CurByte, OS);
- Need0FPrefix = true;
- break;
- case X86II::D8: EmitByte(0xD8, CurByte, OS); break;
- case X86II::D9: EmitByte(0xD9, CurByte, OS); break;
- case X86II::DA: EmitByte(0xDA, CurByte, OS); break;
- case X86II::DB: EmitByte(0xDB, CurByte, OS); break;
- case X86II::DC: EmitByte(0xDC, CurByte, OS); break;
- case X86II::DD: EmitByte(0xDD, CurByte, OS); break;
- case X86II::DE: EmitByte(0xDE, CurByte, OS); break;
- case X86II::DF: EmitByte(0xDF, CurByte, OS); break;
- }
-
- // Handle REX prefix.
- // FIXME: Can this come before F2 etc to simplify emission?
- if (is64BitMode()) {
- if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
- EmitByte(0x40 | REX, CurByte, OS);
- }
-
- // 0x0F escape code must be emitted just before the opcode.
- if (Need0FPrefix)
- EmitByte(0x0F, CurByte, OS);
-
- // FIXME: Pull this up into previous switch if REX can be moved earlier.
- switch (TSFlags & X86II::Op0Mask) {
- case X86II::TF: // F2 0F 38
- case X86II::T8: // 0F 38
- EmitByte(0x38, CurByte, OS);
- break;
- case X86II::TA: // 0F 3A
- EmitByte(0x3A, CurByte, OS);
- break;
- case X86II::A6: // 0F A6
- EmitByte(0xA6, CurByte, OS);
- break;
- case X86II::A7: // 0F A7
- EmitByte(0xA7, CurByte, OS);
- break;
- }
-}
-
-void X86MCCodeEmitter::
-EncodeInstruction(const MCInst &MI, raw_ostream &OS,
- SmallVectorImpl<MCFixup> &Fixups) const {
- unsigned Opcode = MI.getOpcode();
- const MCInstrDesc &Desc = MCII.get(Opcode);
- uint64_t TSFlags = Desc.TSFlags;
-
- // Pseudo instructions don't get encoded.
- if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
- return;
-
- // If this is a two-address instruction, skip one of the register operands.
- // FIXME: This should be handled during MCInst lowering.
- unsigned NumOps = Desc.getNumOperands();
- unsigned CurOp = 0;
- if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1)
- ++CurOp;
- else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, MCOI::TIED_TO)== 0)
- // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
- --NumOps;
-
- // Keep track of the current byte being emitted.
- unsigned CurByte = 0;
-
- // Is this instruction encoded using the AVX VEX prefix?
- bool HasVEXPrefix = false;
-
- // It uses the VEX.VVVV field?
- bool HasVEX_4V = false;
-
- if ((TSFlags >> X86II::VEXShift) & X86II::VEX)
- HasVEXPrefix = true;
- if ((TSFlags >> X86II::VEXShift) & X86II::VEX_4V)
- HasVEX_4V = true;
-
-
- // Determine where the memory operand starts, if present.
- int MemoryOperand = X86II::getMemoryOperandNo(TSFlags);
- if (MemoryOperand != -1) MemoryOperand += CurOp;
-
- if (!HasVEXPrefix)
- EmitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
- else
- EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
-
-
- unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
-
- if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode)
- BaseOpcode = 0x0F; // Weird 3DNow! encoding.
-
- unsigned SrcRegNum = 0;
- switch (TSFlags & X86II::FormMask) {
- case X86II::MRMInitReg:
- assert(0 && "FIXME: Remove this form when the JIT moves to MCCodeEmitter!");
- default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
- assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
- case X86II::Pseudo:
- assert(0 && "Pseudo instruction shouldn't be emitted");
- case X86II::RawFrm:
- EmitByte(BaseOpcode, CurByte, OS);
- break;
-
- case X86II::RawFrmImm8:
- EmitByte(BaseOpcode, CurByte, OS);
- EmitImmediate(MI.getOperand(CurOp++),
- X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
- CurByte, OS, Fixups);
- EmitImmediate(MI.getOperand(CurOp++), 1, FK_Data_1, CurByte, OS, Fixups);
- break;
- case X86II::RawFrmImm16:
- EmitByte(BaseOpcode, CurByte, OS);
- EmitImmediate(MI.getOperand(CurOp++),
- X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
- CurByte, OS, Fixups);
- EmitImmediate(MI.getOperand(CurOp++), 2, FK_Data_2, CurByte, OS, Fixups);
- break;
-
- case X86II::AddRegFrm:
- EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
- break;
-
- case X86II::MRMDestReg:
- EmitByte(BaseOpcode, CurByte, OS);
- EmitRegModRMByte(MI.getOperand(CurOp),
- GetX86RegNum(MI.getOperand(CurOp+1)), CurByte, OS);
- CurOp += 2;
- break;
-
- case X86II::MRMDestMem:
- EmitByte(BaseOpcode, CurByte, OS);
- SrcRegNum = CurOp + X86::AddrNumOperands;
-
- if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
- SrcRegNum++;
-
- EmitMemModRMByte(MI, CurOp,
- GetX86RegNum(MI.getOperand(SrcRegNum)),
- TSFlags, CurByte, OS, Fixups);
- CurOp = SrcRegNum + 1;
- break;
-
- case X86II::MRMSrcReg:
- EmitByte(BaseOpcode, CurByte, OS);
- SrcRegNum = CurOp + 1;
-
- if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
- SrcRegNum++;
-
- EmitRegModRMByte(MI.getOperand(SrcRegNum),
- GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
- CurOp = SrcRegNum + 1;
- break;
-
- case X86II::MRMSrcMem: {
- int AddrOperands = X86::AddrNumOperands;
- unsigned FirstMemOp = CurOp+1;
- if (HasVEX_4V) {
- ++AddrOperands;
- ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
- }
-
- EmitByte(BaseOpcode, CurByte, OS);
-
- EmitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
- TSFlags, CurByte, OS, Fixups);
- CurOp += AddrOperands + 1;
- break;
- }
-
- case X86II::MRM0r: case X86II::MRM1r:
- case X86II::MRM2r: case X86II::MRM3r:
- case X86II::MRM4r: case X86II::MRM5r:
- case X86II::MRM6r: case X86II::MRM7r:
- if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
- CurOp++;
- EmitByte(BaseOpcode, CurByte, OS);
- EmitRegModRMByte(MI.getOperand(CurOp++),
- (TSFlags & X86II::FormMask)-X86II::MRM0r,
- CurByte, OS);
- break;
- case X86II::MRM0m: case X86II::MRM1m:
- case X86II::MRM2m: case X86II::MRM3m:
- case X86II::MRM4m: case X86II::MRM5m:
- case X86II::MRM6m: case X86II::MRM7m:
- EmitByte(BaseOpcode, CurByte, OS);
- EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m,
- TSFlags, CurByte, OS, Fixups);
- CurOp += X86::AddrNumOperands;
- break;
- case X86II::MRM_C1:
- EmitByte(BaseOpcode, CurByte, OS);
- EmitByte(0xC1, CurByte, OS);
- break;
- case X86II::MRM_C2:
- EmitByte(BaseOpcode, CurByte, OS);
- EmitByte(0xC2, CurByte, OS);
- break;
- case X86II::MRM_C3:
- EmitByte(BaseOpcode, CurByte, OS);
- EmitByte(0xC3, CurByte, OS);
- break;
- case X86II::MRM_C4:
- EmitByte(BaseOpcode, CurByte, OS);
- EmitByte(0xC4, CurByte, OS);
- break;
- case X86II::MRM_C8:
- EmitByte(BaseOpcode, CurByte, OS);
- EmitByte(0xC8, CurByte, OS);
- break;
- case X86II::MRM_C9:
- EmitByte(BaseOpcode, CurByte, OS);
- EmitByte(0xC9, CurByte, OS);
- break;
- case X86II::MRM_E8:
- EmitByte(BaseOpcode, CurByte, OS);
- EmitByte(0xE8, CurByte, OS);
- break;
- case X86II::MRM_F0:
- EmitByte(BaseOpcode, CurByte, OS);
- EmitByte(0xF0, CurByte, OS);
- break;
- case X86II::MRM_F8:
- EmitByte(BaseOpcode, CurByte, OS);
- EmitByte(0xF8, CurByte, OS);
- break;
- case X86II::MRM_F9:
- EmitByte(BaseOpcode, CurByte, OS);
- EmitByte(0xF9, CurByte, OS);
- break;
- case X86II::MRM_D0:
- EmitByte(BaseOpcode, CurByte, OS);
- EmitByte(0xD0, CurByte, OS);
- break;
- case X86II::MRM_D1:
- EmitByte(BaseOpcode, CurByte, OS);
- EmitByte(0xD1, CurByte, OS);
- break;
- }
-
- // If there is a remaining operand, it must be a trailing immediate. Emit it
- // according to the right size for the instruction.
- if (CurOp != NumOps) {
- // The last source register of a 4 operand instruction in AVX is encoded
- // in bits[7:4] of a immediate byte, and bits[3:0] are ignored.
- if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) {
- const MCOperand &MO = MI.getOperand(CurOp++);
- bool IsExtReg =
- X86InstrInfo::isX86_64ExtendedReg(MO.getReg());
- unsigned RegNum = (IsExtReg ? (1 << 7) : 0);
- RegNum |= GetX86RegNum(MO) << 4;
- EmitImmediate(MCOperand::CreateImm(RegNum), 1, FK_Data_1, CurByte, OS,
- Fixups);
- } else {
- unsigned FixupKind;
- // FIXME: Is there a better way to know that we need a signed relocation?
- if (MI.getOpcode() == X86::ADD64ri32 ||
- MI.getOpcode() == X86::MOV64ri32 ||
- MI.getOpcode() == X86::MOV64mi32 ||
- MI.getOpcode() == X86::PUSH64i32)
- FixupKind = X86::reloc_signed_4byte;
- else
- FixupKind = getImmFixupKind(TSFlags);
- EmitImmediate(MI.getOperand(CurOp++),
- X86II::getSizeOfImm(TSFlags), MCFixupKind(FixupKind),
- CurByte, OS, Fixups);
- }
- }
-
- if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode)
- EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS);
-
-
-#ifndef NDEBUG
- // FIXME: Verify.
- if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
- errs() << "Cannot encode all operands of: ";
- MI.dump();
- errs() << '\n';
- abort();
- }
-#endif
-}
Modified: llvm/branches/exception-handling-rewrite/lib/Target/X86/X86MCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/X86/X86MCInstLower.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/X86/X86MCInstLower.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/X86/X86MCInstLower.cpp Mon Jul 25 20:29:47 2011
@@ -381,6 +381,7 @@
case X86::AVX_SET0PD: LowerUnaryToTwoAddr(OutMI, X86::VXORPDrr); break;
case X86::AVX_SET0PDY: LowerUnaryToTwoAddr(OutMI, X86::VXORPDYrr); break;
case X86::AVX_SET0PI: LowerUnaryToTwoAddr(OutMI, X86::VPXORrr); break;
+ case X86::AVX_SETALLONES: LowerUnaryToTwoAddr(OutMI, X86::VPCMPEQDrr); break;
case X86::MOV16r0:
LowerSubReg32_Op0(OutMI, X86::MOV32r0); // MOV16r0 -> MOV32r0
Removed: llvm/branches/exception-handling-rewrite/lib/Target/X86/X86MachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/X86/X86MachObjectWriter.cpp?rev=136039&view=auto
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/X86/X86MachObjectWriter.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/X86/X86MachObjectWriter.cpp (removed)
@@ -1,554 +0,0 @@
-//===-- X86MachObjectWriter.cpp - X86 Mach-O Writer -----------------------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#include "X86.h"
-#include "X86FixupKinds.h"
-#include "llvm/ADT/Twine.h"
-#include "llvm/MC/MCAssembler.h"
-#include "llvm/MC/MCAsmLayout.h"
-#include "llvm/MC/MCMachObjectWriter.h"
-#include "llvm/MC/MCSectionMachO.h"
-#include "llvm/MC/MCValue.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Object/MachOFormat.h"
-
-using namespace llvm;
-using namespace llvm::object;
-
-namespace {
-class X86MachObjectWriter : public MCMachObjectTargetWriter {
- void RecordScatteredRelocation(MachObjectWriter *Writer,
- const MCAssembler &Asm,
- const MCAsmLayout &Layout,
- const MCFragment *Fragment,
- const MCFixup &Fixup,
- MCValue Target,
- unsigned Log2Size,
- uint64_t &FixedValue);
- void RecordTLVPRelocation(MachObjectWriter *Writer,
- const MCAssembler &Asm,
- const MCAsmLayout &Layout,
- const MCFragment *Fragment,
- const MCFixup &Fixup,
- MCValue Target,
- uint64_t &FixedValue);
-
- void RecordX86Relocation(MachObjectWriter *Writer,
- const MCAssembler &Asm,
- const MCAsmLayout &Layout,
- const MCFragment *Fragment,
- const MCFixup &Fixup,
- MCValue Target,
- uint64_t &FixedValue);
- void RecordX86_64Relocation(MachObjectWriter *Writer,
- const MCAssembler &Asm,
- const MCAsmLayout &Layout,
- const MCFragment *Fragment,
- const MCFixup &Fixup,
- MCValue Target,
- uint64_t &FixedValue);
-public:
- X86MachObjectWriter(bool Is64Bit, uint32_t CPUType,
- uint32_t CPUSubtype)
- : MCMachObjectTargetWriter(Is64Bit, CPUType, CPUSubtype,
- /*UseAggressiveSymbolFolding=*/Is64Bit) {}
-
- void RecordRelocation(MachObjectWriter *Writer,
- const MCAssembler &Asm, const MCAsmLayout &Layout,
- const MCFragment *Fragment, const MCFixup &Fixup,
- MCValue Target, uint64_t &FixedValue) {
- if (Writer->is64Bit())
- RecordX86_64Relocation(Writer, Asm, Layout, Fragment, Fixup, Target,
- FixedValue);
- else
- RecordX86Relocation(Writer, Asm, Layout, Fragment, Fixup, Target,
- FixedValue);
- }
-};
-}
-
-static bool isFixupKindRIPRel(unsigned Kind) {
- return Kind == X86::reloc_riprel_4byte ||
- Kind == X86::reloc_riprel_4byte_movq_load;
-}
-
-static unsigned getFixupKindLog2Size(unsigned Kind) {
- switch (Kind) {
- default:
- llvm_unreachable("invalid fixup kind!");
- case FK_PCRel_1:
- case FK_Data_1: return 0;
- case FK_PCRel_2:
- case FK_Data_2: return 1;
- case FK_PCRel_4:
- // FIXME: Remove these!!!
- case X86::reloc_riprel_4byte:
- case X86::reloc_riprel_4byte_movq_load:
- case X86::reloc_signed_4byte:
- case FK_Data_4: return 2;
- case FK_Data_8: return 3;
- }
-}
-
-void X86MachObjectWriter::RecordX86_64Relocation(MachObjectWriter *Writer,
- const MCAssembler &Asm,
- const MCAsmLayout &Layout,
- const MCFragment *Fragment,
- const MCFixup &Fixup,
- MCValue Target,
- uint64_t &FixedValue) {
- unsigned IsPCRel = Writer->isFixupKindPCRel(Asm, Fixup.getKind());
- unsigned IsRIPRel = isFixupKindRIPRel(Fixup.getKind());
- unsigned Log2Size = getFixupKindLog2Size(Fixup.getKind());
-
- // See <reloc.h>.
- uint32_t FixupOffset =
- Layout.getFragmentOffset(Fragment) + Fixup.getOffset();
- uint32_t FixupAddress =
- Writer->getFragmentAddress(Fragment, Layout) + Fixup.getOffset();
- int64_t Value = 0;
- unsigned Index = 0;
- unsigned IsExtern = 0;
- unsigned Type = 0;
-
- Value = Target.getConstant();
-
- if (IsPCRel) {
- // Compensate for the relocation offset, Darwin x86_64 relocations only have
- // the addend and appear to have attempted to define it to be the actual
- // expression addend without the PCrel bias. However, instructions with data
- // following the relocation are not accommodated for (see comment below
- // regarding SIGNED{1,2,4}), so it isn't exactly that either.
- Value += 1LL << Log2Size;
- }
-
- if (Target.isAbsolute()) { // constant
- // SymbolNum of 0 indicates the absolute section.
- Type = macho::RIT_X86_64_Unsigned;
- Index = 0;
-
- // FIXME: I believe this is broken, I don't think the linker can understand
- // it. I think it would require a local relocation, but I'm not sure if that
- // would work either. The official way to get an absolute PCrel relocation
- // is to use an absolute symbol (which we don't support yet).
- if (IsPCRel) {
- IsExtern = 1;
- Type = macho::RIT_X86_64_Branch;
- }
- } else if (Target.getSymB()) { // A - B + constant
- const MCSymbol *A = &Target.getSymA()->getSymbol();
- MCSymbolData &A_SD = Asm.getSymbolData(*A);
- const MCSymbolData *A_Base = Asm.getAtom(&A_SD);
-
- const MCSymbol *B = &Target.getSymB()->getSymbol();
- MCSymbolData &B_SD = Asm.getSymbolData(*B);
- const MCSymbolData *B_Base = Asm.getAtom(&B_SD);
-
- // Neither symbol can be modified.
- if (Target.getSymA()->getKind() != MCSymbolRefExpr::VK_None ||
- Target.getSymB()->getKind() != MCSymbolRefExpr::VK_None)
- report_fatal_error("unsupported relocation of modified symbol");
-
- // We don't support PCrel relocations of differences. Darwin 'as' doesn't
- // implement most of these correctly.
- if (IsPCRel)
- report_fatal_error("unsupported pc-relative relocation of difference");
-
- // The support for the situation where one or both of the symbols would
- // require a local relocation is handled just like if the symbols were
- // external. This is certainly used in the case of debug sections where the
- // section has only temporary symbols and thus the symbols don't have base
- // symbols. This is encoded using the section ordinal and non-extern
- // relocation entries.
-
- // Darwin 'as' doesn't emit correct relocations for this (it ends up with a
- // single SIGNED relocation); reject it for now. Except the case where both
- // symbols don't have a base, equal but both NULL.
- if (A_Base == B_Base && A_Base)
- report_fatal_error("unsupported relocation with identical base");
-
- Value += Writer->getSymbolAddress(&A_SD, Layout) -
- (A_Base == NULL ? 0 : Writer->getSymbolAddress(A_Base, Layout));
- Value -= Writer->getSymbolAddress(&B_SD, Layout) -
- (B_Base == NULL ? 0 : Writer->getSymbolAddress(B_Base, Layout));
-
- if (A_Base) {
- Index = A_Base->getIndex();
- IsExtern = 1;
- }
- else {
- Index = A_SD.getFragment()->getParent()->getOrdinal() + 1;
- IsExtern = 0;
- }
- Type = macho::RIT_X86_64_Unsigned;
-
- macho::RelocationEntry MRE;
- MRE.Word0 = FixupOffset;
- MRE.Word1 = ((Index << 0) |
- (IsPCRel << 24) |
- (Log2Size << 25) |
- (IsExtern << 27) |
- (Type << 28));
- Writer->addRelocation(Fragment->getParent(), MRE);
-
- if (B_Base) {
- Index = B_Base->getIndex();
- IsExtern = 1;
- }
- else {
- Index = B_SD.getFragment()->getParent()->getOrdinal() + 1;
- IsExtern = 0;
- }
- Type = macho::RIT_X86_64_Subtractor;
- } else {
- const MCSymbol *Symbol = &Target.getSymA()->getSymbol();
- MCSymbolData &SD = Asm.getSymbolData(*Symbol);
- const MCSymbolData *Base = Asm.getAtom(&SD);
-
- // Relocations inside debug sections always use local relocations when
- // possible. This seems to be done because the debugger doesn't fully
- // understand x86_64 relocation entries, and expects to find values that
- // have already been fixed up.
- if (Symbol->isInSection()) {
- const MCSectionMachO &Section = static_cast<const MCSectionMachO&>(
- Fragment->getParent()->getSection());
- if (Section.hasAttribute(MCSectionMachO::S_ATTR_DEBUG))
- Base = 0;
- }
-
- // x86_64 almost always uses external relocations, except when there is no
- // symbol to use as a base address (a local symbol with no preceding
- // non-local symbol).
- if (Base) {
- Index = Base->getIndex();
- IsExtern = 1;
-
- // Add the local offset, if needed.
- if (Base != &SD)
- Value += Layout.getSymbolOffset(&SD) - Layout.getSymbolOffset(Base);
- } else if (Symbol->isInSection() && !Symbol->isVariable()) {
- // The index is the section ordinal (1-based).
- Index = SD.getFragment()->getParent()->getOrdinal() + 1;
- IsExtern = 0;
- Value += Writer->getSymbolAddress(&SD, Layout);
-
- if (IsPCRel)
- Value -= FixupAddress + (1 << Log2Size);
- } else if (Symbol->isVariable()) {
- const MCExpr *Value = Symbol->getVariableValue();
- int64_t Res;
- bool isAbs = Value->EvaluateAsAbsolute(Res, Layout,
- Writer->getSectionAddressMap());
- if (isAbs) {
- FixedValue = Res;
- return;
- } else {
- report_fatal_error("unsupported relocation of variable '" +
- Symbol->getName() + "'");
- }
- } else {
- report_fatal_error("unsupported relocation of undefined symbol '" +
- Symbol->getName() + "'");
- }
-
- MCSymbolRefExpr::VariantKind Modifier = Target.getSymA()->getKind();
- if (IsPCRel) {
- if (IsRIPRel) {
- if (Modifier == MCSymbolRefExpr::VK_GOTPCREL) {
- // x86_64 distinguishes movq foo at GOTPCREL so that the linker can
- // rewrite the movq to an leaq at link time if the symbol ends up in
- // the same linkage unit.
- if (unsigned(Fixup.getKind()) == X86::reloc_riprel_4byte_movq_load)
- Type = macho::RIT_X86_64_GOTLoad;
- else
- Type = macho::RIT_X86_64_GOT;
- } else if (Modifier == MCSymbolRefExpr::VK_TLVP) {
- Type = macho::RIT_X86_64_TLV;
- } else if (Modifier != MCSymbolRefExpr::VK_None) {
- report_fatal_error("unsupported symbol modifier in relocation");
- } else {
- Type = macho::RIT_X86_64_Signed;
-
- // The Darwin x86_64 relocation format has a problem where it cannot
- // encode an address (L<foo> + <constant>) which is outside the atom
- // containing L<foo>. Generally, this shouldn't occur but it does
- // happen when we have a RIPrel instruction with data following the
- // relocation entry (e.g., movb $012, L0(%rip)). Even with the PCrel
- // adjustment Darwin x86_64 uses, the offset is still negative and the
- // linker has no way to recognize this.
- //
- // To work around this, Darwin uses several special relocation types
- // to indicate the offsets. However, the specification or
- // implementation of these seems to also be incomplete; they should
- // adjust the addend as well based on the actual encoded instruction
- // (the additional bias), but instead appear to just look at the final
- // offset.
- switch (-(Target.getConstant() + (1LL << Log2Size))) {
- case 1: Type = macho::RIT_X86_64_Signed1; break;
- case 2: Type = macho::RIT_X86_64_Signed2; break;
- case 4: Type = macho::RIT_X86_64_Signed4; break;
- }
- }
- } else {
- if (Modifier != MCSymbolRefExpr::VK_None)
- report_fatal_error("unsupported symbol modifier in branch "
- "relocation");
-
- Type = macho::RIT_X86_64_Branch;
- }
- } else {
- if (Modifier == MCSymbolRefExpr::VK_GOT) {
- Type = macho::RIT_X86_64_GOT;
- } else if (Modifier == MCSymbolRefExpr::VK_GOTPCREL) {
- // GOTPCREL is allowed as a modifier on non-PCrel instructions, in which
- // case all we do is set the PCrel bit in the relocation entry; this is
- // used with exception handling, for example. The source is required to
- // include any necessary offset directly.
- Type = macho::RIT_X86_64_GOT;
- IsPCRel = 1;
- } else if (Modifier == MCSymbolRefExpr::VK_TLVP) {
- report_fatal_error("TLVP symbol modifier should have been rip-rel");
- } else if (Modifier != MCSymbolRefExpr::VK_None)
- report_fatal_error("unsupported symbol modifier in relocation");
- else
- Type = macho::RIT_X86_64_Unsigned;
- }
- }
-
- // x86_64 always writes custom values into the fixups.
- FixedValue = Value;
-
- // struct relocation_info (8 bytes)
- macho::RelocationEntry MRE;
- MRE.Word0 = FixupOffset;
- MRE.Word1 = ((Index << 0) |
- (IsPCRel << 24) |
- (Log2Size << 25) |
- (IsExtern << 27) |
- (Type << 28));
- Writer->addRelocation(Fragment->getParent(), MRE);
-}
-
-void X86MachObjectWriter::RecordScatteredRelocation(MachObjectWriter *Writer,
- const MCAssembler &Asm,
- const MCAsmLayout &Layout,
- const MCFragment *Fragment,
- const MCFixup &Fixup,
- MCValue Target,
- unsigned Log2Size,
- uint64_t &FixedValue) {
- uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
- unsigned IsPCRel = Writer->isFixupKindPCRel(Asm, Fixup.getKind());
- unsigned Type = macho::RIT_Vanilla;
-
- // See <reloc.h>.
- const MCSymbol *A = &Target.getSymA()->getSymbol();
- MCSymbolData *A_SD = &Asm.getSymbolData(*A);
-
- if (!A_SD->getFragment())
- report_fatal_error("symbol '" + A->getName() +
- "' can not be undefined in a subtraction expression");
-
- uint32_t Value = Writer->getSymbolAddress(A_SD, Layout);
- uint64_t SecAddr = Writer->getSectionAddress(A_SD->getFragment()->getParent());
- FixedValue += SecAddr;
- uint32_t Value2 = 0;
-
- if (const MCSymbolRefExpr *B = Target.getSymB()) {
- MCSymbolData *B_SD = &Asm.getSymbolData(B->getSymbol());
-
- if (!B_SD->getFragment())
- report_fatal_error("symbol '" + B->getSymbol().getName() +
- "' can not be undefined in a subtraction expression");
-
- // Select the appropriate difference relocation type.
- //
- // Note that there is no longer any semantic difference between these two
- // relocation types from the linkers point of view, this is done solely for
- // pedantic compatibility with 'as'.
- Type = A_SD->isExternal() ? (unsigned)macho::RIT_Difference :
- (unsigned)macho::RIT_Generic_LocalDifference;
- Value2 = Writer->getSymbolAddress(B_SD, Layout);
- FixedValue -= Writer->getSectionAddress(B_SD->getFragment()->getParent());
- }
-
- // Relocations are written out in reverse order, so the PAIR comes first.
- if (Type == macho::RIT_Difference ||
- Type == macho::RIT_Generic_LocalDifference) {
- macho::RelocationEntry MRE;
- MRE.Word0 = ((0 << 0) |
- (macho::RIT_Pair << 24) |
- (Log2Size << 28) |
- (IsPCRel << 30) |
- macho::RF_Scattered);
- MRE.Word1 = Value2;
- Writer->addRelocation(Fragment->getParent(), MRE);
- }
-
- macho::RelocationEntry MRE;
- MRE.Word0 = ((FixupOffset << 0) |
- (Type << 24) |
- (Log2Size << 28) |
- (IsPCRel << 30) |
- macho::RF_Scattered);
- MRE.Word1 = Value;
- Writer->addRelocation(Fragment->getParent(), MRE);
-}
-
-void X86MachObjectWriter::RecordTLVPRelocation(MachObjectWriter *Writer,
- const MCAssembler &Asm,
- const MCAsmLayout &Layout,
- const MCFragment *Fragment,
- const MCFixup &Fixup,
- MCValue Target,
- uint64_t &FixedValue) {
- assert(Target.getSymA()->getKind() == MCSymbolRefExpr::VK_TLVP &&
- !is64Bit() &&
- "Should only be called with a 32-bit TLVP relocation!");
-
- unsigned Log2Size = getFixupKindLog2Size(Fixup.getKind());
- uint32_t Value = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
- unsigned IsPCRel = 0;
-
- // Get the symbol data.
- MCSymbolData *SD_A = &Asm.getSymbolData(Target.getSymA()->getSymbol());
- unsigned Index = SD_A->getIndex();
-
- // We're only going to have a second symbol in pic mode and it'll be a
- // subtraction from the picbase. For 32-bit pic the addend is the difference
- // between the picbase and the next address. For 32-bit static the addend is
- // zero.
- if (Target.getSymB()) {
- // If this is a subtraction then we're pcrel.
- uint32_t FixupAddress =
- Writer->getFragmentAddress(Fragment, Layout) + Fixup.getOffset();
- MCSymbolData *SD_B = &Asm.getSymbolData(Target.getSymB()->getSymbol());
- IsPCRel = 1;
- FixedValue = (FixupAddress - Writer->getSymbolAddress(SD_B, Layout) +
- Target.getConstant());
- FixedValue += 1ULL << Log2Size;
- } else {
- FixedValue = 0;
- }
-
- // struct relocation_info (8 bytes)
- macho::RelocationEntry MRE;
- MRE.Word0 = Value;
- MRE.Word1 = ((Index << 0) |
- (IsPCRel << 24) |
- (Log2Size << 25) |
- (1 << 27) | // Extern
- (macho::RIT_Generic_TLV << 28)); // Type
- Writer->addRelocation(Fragment->getParent(), MRE);
-}
-
-void X86MachObjectWriter::RecordX86Relocation(MachObjectWriter *Writer,
- const MCAssembler &Asm,
- const MCAsmLayout &Layout,
- const MCFragment *Fragment,
- const MCFixup &Fixup,
- MCValue Target,
- uint64_t &FixedValue) {
- unsigned IsPCRel = Writer->isFixupKindPCRel(Asm, Fixup.getKind());
- unsigned Log2Size = getFixupKindLog2Size(Fixup.getKind());
-
- // If this is a 32-bit TLVP reloc it's handled a bit differently.
- if (Target.getSymA() &&
- Target.getSymA()->getKind() == MCSymbolRefExpr::VK_TLVP) {
- RecordTLVPRelocation(Writer, Asm, Layout, Fragment, Fixup, Target,
- FixedValue);
- return;
- }
-
- // If this is a difference or a defined symbol plus an offset, then we need a
- // scattered relocation entry. Differences always require scattered
- // relocations.
- if (Target.getSymB())
- return RecordScatteredRelocation(Writer, Asm, Layout, Fragment, Fixup,
- Target, Log2Size, FixedValue);
-
- // Get the symbol data, if any.
- MCSymbolData *SD = 0;
- if (Target.getSymA())
- SD = &Asm.getSymbolData(Target.getSymA()->getSymbol());
-
- // If this is an internal relocation with an offset, it also needs a scattered
- // relocation entry.
- uint32_t Offset = Target.getConstant();
- if (IsPCRel)
- Offset += 1 << Log2Size;
- if (Offset && SD && !Writer->doesSymbolRequireExternRelocation(SD))
- return RecordScatteredRelocation(Writer, Asm, Layout, Fragment, Fixup,
- Target, Log2Size, FixedValue);
-
- // See <reloc.h>.
- uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
- unsigned Index = 0;
- unsigned IsExtern = 0;
- unsigned Type = 0;
-
- if (Target.isAbsolute()) { // constant
- // SymbolNum of 0 indicates the absolute section.
- //
- // FIXME: Currently, these are never generated (see code below). I cannot
- // find a case where they are actually emitted.
- Type = macho::RIT_Vanilla;
- } else {
- // Resolve constant variables.
- if (SD->getSymbol().isVariable()) {
- int64_t Res;
- if (SD->getSymbol().getVariableValue()->EvaluateAsAbsolute(
- Res, Layout, Writer->getSectionAddressMap())) {
- FixedValue = Res;
- return;
- }
- }
-
- // Check whether we need an external or internal relocation.
- if (Writer->doesSymbolRequireExternRelocation(SD)) {
- IsExtern = 1;
- Index = SD->getIndex();
- // For external relocations, make sure to offset the fixup value to
- // compensate for the addend of the symbol address, if it was
- // undefined. This occurs with weak definitions, for example.
- if (!SD->Symbol->isUndefined())
- FixedValue -= Layout.getSymbolOffset(SD);
- } else {
- // The index is the section ordinal (1-based).
- const MCSectionData &SymSD = Asm.getSectionData(
- SD->getSymbol().getSection());
- Index = SymSD.getOrdinal() + 1;
- FixedValue += Writer->getSectionAddress(&SymSD);
- }
- if (IsPCRel)
- FixedValue -= Writer->getSectionAddress(Fragment->getParent());
-
- Type = macho::RIT_Vanilla;
- }
-
- // struct relocation_info (8 bytes)
- macho::RelocationEntry MRE;
- MRE.Word0 = FixupOffset;
- MRE.Word1 = ((Index << 0) |
- (IsPCRel << 24) |
- (Log2Size << 25) |
- (IsExtern << 27) |
- (Type << 28));
- Writer->addRelocation(Fragment->getParent(), MRE);
-}
-
-MCObjectWriter *llvm::createX86MachObjectWriter(raw_ostream &OS,
- bool Is64Bit,
- uint32_t CPUType,
- uint32_t CPUSubtype) {
- return createMachObjectWriter(new X86MachObjectWriter(Is64Bit,
- CPUType,
- CPUSubtype),
- OS, /*IsLittleEndian=*/true);
-}
Modified: llvm/branches/exception-handling-rewrite/lib/Target/X86/X86TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/X86/X86TargetMachine.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/X86/X86TargetMachine.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/X86/X86TargetMachine.cpp Mon Jul 25 20:29:47 2011
@@ -16,52 +16,15 @@
#include "llvm/PassManager.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/Passes.h"
-#include "llvm/MC/MCCodeEmitter.h"
-#include "llvm/MC/MCStreamer.h"
#include "llvm/Support/FormattedStream.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetRegistry.h"
using namespace llvm;
-static MCStreamer *createMCStreamer(const Target &T, const std::string &TT,
- MCContext &Ctx, TargetAsmBackend &TAB,
- raw_ostream &_OS,
- MCCodeEmitter *_Emitter,
- bool RelaxAll,
- bool NoExecStack) {
- Triple TheTriple(TT);
-
- if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
- return createMachOStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll);
-
- if (TheTriple.isOSWindows())
- return createWinCOFFStreamer(Ctx, TAB, *_Emitter, _OS, RelaxAll);
-
- return createELFStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll, NoExecStack);
-}
-
extern "C" void LLVMInitializeX86Target() {
// Register the target.
RegisterTargetMachine<X86_32TargetMachine> X(TheX86_32Target);
RegisterTargetMachine<X86_64TargetMachine> Y(TheX86_64Target);
-
- // Register the code emitter.
- TargetRegistry::RegisterCodeEmitter(TheX86_32Target,
- createX86MCCodeEmitter);
- TargetRegistry::RegisterCodeEmitter(TheX86_64Target,
- createX86MCCodeEmitter);
-
- // Register the asm backend.
- TargetRegistry::RegisterAsmBackend(TheX86_32Target,
- createX86_32AsmBackend);
- TargetRegistry::RegisterAsmBackend(TheX86_64Target,
- createX86_64AsmBackend);
-
- // Register the object streamer.
- TargetRegistry::RegisterObjectStreamer(TheX86_32Target,
- createMCStreamer);
- TargetRegistry::RegisterObjectStreamer(TheX86_64Target,
- createMCStreamer);
}
Modified: llvm/branches/exception-handling-rewrite/lib/Target/XCore/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/XCore/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/XCore/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/XCore/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -6,6 +6,7 @@
tablegen(XCoreGenDAGISel.inc -gen-dag-isel)
tablegen(XCoreGenCallingConv.inc -gen-callingconv)
tablegen(XCoreGenSubtargetInfo.inc -gen-subtarget)
+add_public_tablegen_target(XCoreCommonTableGen)
add_llvm_target(XCoreCodeGen
XCoreAsmPrinter.cpp
Modified: llvm/branches/exception-handling-rewrite/lib/Target/XCore/MCTargetDesc/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Target/XCore/MCTargetDesc/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Target/XCore/MCTargetDesc/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/lib/Target/XCore/MCTargetDesc/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -2,6 +2,7 @@
XCoreMCTargetDesc.cpp
XCoreMCAsmInfo.cpp
)
+add_dependencies(LLVMXCoreDesc XCoreCommonTableGen)
# Hack: we need to include 'main' target directory to grab private headers
include_directories(${CMAKE_CURRENT_SOURCE_DIR}/.. ${CMAKE_CURRENT_BINARY_DIR}/..)
Modified: llvm/branches/exception-handling-rewrite/lib/Transforms/IPO/ArgumentPromotion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Transforms/IPO/ArgumentPromotion.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Transforms/IPO/ArgumentPromotion.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Transforms/IPO/ArgumentPromotion.cpp Mon Jul 25 20:29:47 2011
@@ -576,9 +576,7 @@
for (ScalarizeTable::iterator SI = ArgIndices.begin(),
E = ArgIndices.end(); SI != E; ++SI) {
// not allowed to dereference ->begin() if size() is 0
- Params.push_back(GetElementPtrInst::getIndexedType(I->getType(),
- SI->begin(),
- SI->end()));
+ Params.push_back(GetElementPtrInst::getIndexedType(I->getType(), *SI));
assert(Params.back());
}
@@ -668,7 +666,7 @@
ConstantInt::get(Type::getInt32Ty(F->getContext()), 0), 0 };
for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
Idxs[1] = ConstantInt::get(Type::getInt32Ty(F->getContext()), i);
- Value *Idx = GetElementPtrInst::Create(*AI, Idxs, Idxs+2,
+ Value *Idx = GetElementPtrInst::Create(*AI, Idxs,
(*AI)->getName()+"."+utostr(i),
Call);
// TODO: Tell AA about the new values?
@@ -699,8 +697,7 @@
ElTy = cast<CompositeType>(ElTy)->getTypeAtIndex(*II);
}
// And create a GEP to extract those indices.
- V = GetElementPtrInst::Create(V, Ops.begin(), Ops.end(),
- V->getName()+".idx", Call);
+ V = GetElementPtrInst::Create(V, Ops, V->getName()+".idx", Call);
Ops.clear();
AA.copyValue(OrigLoad->getOperand(0), V);
}
@@ -801,7 +798,7 @@
for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
Idxs[1] = ConstantInt::get(Type::getInt32Ty(F->getContext()), i);
Value *Idx =
- GetElementPtrInst::Create(TheAlloca, Idxs, Idxs+2,
+ GetElementPtrInst::Create(TheAlloca, Idxs,
TheAlloca->getName()+"."+Twine(i),
InsertPt);
I2->setName(I->getName()+"."+Twine(i));
Modified: llvm/branches/exception-handling-rewrite/lib/Transforms/IPO/GlobalOpt.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Transforms/IPO/GlobalOpt.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Transforms/IPO/GlobalOpt.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Transforms/IPO/GlobalOpt.cpp Mon Jul 25 20:29:47 2011
@@ -603,7 +603,7 @@
Idxs.push_back(NullInt);
for (unsigned i = 3, e = GEPI->getNumOperands(); i != e; ++i)
Idxs.push_back(GEPI->getOperand(i));
- NewPtr = GetElementPtrInst::Create(NewPtr, Idxs.begin(), Idxs.end(),
+ NewPtr = GetElementPtrInst::Create(NewPtr, Idxs,
GEPI->getName()+"."+Twine(Val),GEPI);
}
}
@@ -1243,8 +1243,7 @@
GEPIdx.push_back(GEPI->getOperand(1));
GEPIdx.append(GEPI->op_begin()+3, GEPI->op_end());
- Value *NGEPI = GetElementPtrInst::Create(NewPtr,
- GEPIdx.begin(), GEPIdx.end(),
+ Value *NGEPI = GetElementPtrInst::Create(NewPtr, GEPIdx,
GEPI->getName(), GEPI);
GEPI->replaceAllUsesWith(NGEPI);
GEPI->eraseFromParent();
Modified: llvm/branches/exception-handling-rewrite/lib/Transforms/InstCombine/InstCombineCasts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Transforms/InstCombine/InstCombineCasts.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Transforms/InstCombine/InstCombineCasts.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Transforms/InstCombine/InstCombineCasts.cpp Mon Jul 25 20:29:47 2011
@@ -1693,7 +1693,7 @@
// If we found a path from the src to dest, create the getelementptr now.
if (SrcElTy == DstElTy) {
SmallVector<Value*, 8> Idxs(NumZeros+1, ZeroUInt);
- return GetElementPtrInst::CreateInBounds(Src, Idxs.begin(), Idxs.end());
+ return GetElementPtrInst::CreateInBounds(Src, Idxs);
}
}
Modified: llvm/branches/exception-handling-rewrite/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp Mon Jul 25 20:29:47 2011
@@ -58,8 +58,7 @@
Idx[0] = NullIdx;
Idx[1] = NullIdx;
Instruction *GEP =
- GetElementPtrInst::CreateInBounds(New, Idx, Idx + 2,
- New->getName()+".sub");
+ GetElementPtrInst::CreateInBounds(New, Idx, New->getName()+".sub");
InsertNewInstBefore(GEP, *It);
// Now make everything use the getelementptr instead of the original
Modified: llvm/branches/exception-handling-rewrite/lib/Transforms/InstCombine/InstCombinePHI.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Transforms/InstCombine/InstCombinePHI.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Transforms/InstCombine/InstCombinePHI.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Transforms/InstCombine/InstCombinePHI.cpp Mon Jul 25 20:29:47 2011
@@ -229,8 +229,7 @@
Value *Base = FixedOperands[0];
GetElementPtrInst *NewGEP =
- GetElementPtrInst::Create(Base, FixedOperands.begin()+1,
- FixedOperands.end());
+ GetElementPtrInst::Create(Base, makeArrayRef(FixedOperands).slice(1));
if (AllInBounds) NewGEP->setIsInBounds();
NewGEP->setDebugLoc(FirstInst->getDebugLoc());
return NewGEP;
Modified: llvm/branches/exception-handling-rewrite/lib/Transforms/InstCombine/InstructionCombining.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Transforms/InstCombine/InstructionCombining.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Transforms/InstCombine/InstructionCombining.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Transforms/InstCombine/InstructionCombining.cpp Mon Jul 25 20:29:47 2011
@@ -851,10 +851,9 @@
if (!Indices.empty())
return (GEP.isInBounds() && Src->isInBounds()) ?
- GetElementPtrInst::CreateInBounds(Src->getOperand(0), Indices.begin(),
- Indices.end(), GEP.getName()) :
- GetElementPtrInst::Create(Src->getOperand(0), Indices.begin(),
- Indices.end(), GEP.getName());
+ GetElementPtrInst::CreateInBounds(Src->getOperand(0), Indices,
+ GEP.getName()) :
+ GetElementPtrInst::Create(Src->getOperand(0), Indices, GEP.getName());
}
// Handle gep(bitcast x) and gep(gep x, 0, 0, 0).
@@ -883,8 +882,7 @@
// -> GEP i8* X, ...
SmallVector<Value*, 8> Idx(GEP.idx_begin()+1, GEP.idx_end());
GetElementPtrInst *Res =
- GetElementPtrInst::Create(StrippedPtr, Idx.begin(),
- Idx.end(), GEP.getName());
+ GetElementPtrInst::Create(StrippedPtr, Idx, GEP.getName());
Res->setIsInBounds(GEP.isInBounds());
return Res;
}
Modified: llvm/branches/exception-handling-rewrite/lib/Transforms/Instrumentation/PathProfiling.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Transforms/Instrumentation/PathProfiling.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Transforms/Instrumentation/PathProfiling.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Transforms/Instrumentation/PathProfiling.cpp Mon Jul 25 20:29:47 2011
@@ -1029,8 +1029,7 @@
gepIndices[1] = incValue;
GetElementPtrInst* pcPointer =
- GetElementPtrInst::Create(dag->getCounterArray(),
- gepIndices.begin(), gepIndices.end(),
+ GetElementPtrInst::Create(dag->getCounterArray(), gepIndices,
"counterInc", insertPoint);
// Load from the array - call it oldPC
Modified: llvm/branches/exception-handling-rewrite/lib/Transforms/Scalar/SCCP.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Transforms/Scalar/SCCP.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Transforms/Scalar/SCCP.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Transforms/Scalar/SCCP.cpp Mon Jul 25 20:29:47 2011
@@ -156,7 +156,7 @@
///
class SCCPSolver : public InstVisitor<SCCPSolver> {
const TargetData *TD;
- SmallPtrSet<BasicBlock*, 8> BBExecutable;// The BBs that are executable.
+ SmallPtrSet<BasicBlock*, 8> BBExecutable; // The BBs that are executable.
DenseMap<Value*, LatticeVal> ValueState; // The state each value is in.
/// StructValueState - This maintains ValueState for values that have
Modified: llvm/branches/exception-handling-rewrite/lib/Transforms/Scalar/Scalar.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Transforms/Scalar/Scalar.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Transforms/Scalar/Scalar.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Transforms/Scalar/Scalar.cpp Mon Jul 25 20:29:47 2011
@@ -187,3 +187,7 @@
void LLVMAddBasicAliasAnalysisPass(LLVMPassManagerRef PM) {
unwrap(PM)->add(createBasicAliasAnalysisPass());
}
+
+void LLVMAddLowerExpectIntrinsicPass(LLVMPassManagerRef PM) {
+ unwrap(PM)->add(createLowerExpectIntrinsicPass());
+}
Modified: llvm/branches/exception-handling-rewrite/lib/Transforms/Scalar/ScalarReplAggregates.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Transforms/Scalar/ScalarReplAggregates.cpp Mon Jul 25 20:29:47 2011
@@ -145,6 +145,9 @@
SmallVector<AllocaInst*, 32> &NewElts);
void RewriteGEP(GetElementPtrInst *GEPI, AllocaInst *AI, uint64_t Offset,
SmallVector<AllocaInst*, 32> &NewElts);
+ void RewriteLifetimeIntrinsic(IntrinsicInst *II, AllocaInst *AI,
+ uint64_t Offset,
+ SmallVector<AllocaInst*, 32> &NewElts);
void RewriteMemIntrinUserOfAlloca(MemIntrinsic *MI, Instruction *Inst,
AllocaInst *AI,
SmallVector<AllocaInst*, 32> &NewElts);
@@ -508,7 +511,8 @@
}
if (BitCastInst *BCI = dyn_cast<BitCastInst>(User)) {
- IsNotTrivial = true; // Can't be mem2reg'd.
+ if (!onlyUsedByLifetimeMarkers(BCI))
+ IsNotTrivial = true; // Can't be mem2reg'd.
if (!CanConvertToScalar(BCI, Offset))
return false;
continue;
@@ -566,6 +570,14 @@
continue;
}
+ // If this is a lifetime intrinsic, we can handle it.
+ if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(User)) {
+ if (II->getIntrinsicID() == Intrinsic::lifetime_start ||
+ II->getIntrinsicID() == Intrinsic::lifetime_end) {
+ continue;
+ }
+ }
+
// Otherwise, we cannot handle this!
return false;
}
@@ -709,6 +721,16 @@
continue;
}
+ if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(User)) {
+ if (II->getIntrinsicID() == Intrinsic::lifetime_start ||
+ II->getIntrinsicID() == Intrinsic::lifetime_end) {
+ // There's no need to preserve these, as the resulting alloca will be
+ // converted to a register anyways.
+ II->eraseFromParent();
+ continue;
+ }
+ }
+
llvm_unreachable("Unsupported operation!");
}
}
@@ -1349,6 +1371,13 @@
continue;
}
+ if (BitCastInst *BCI = dyn_cast<BitCastInst>(U)) {
+ if (onlyUsedByLifetimeMarkers(BCI)) {
+ InstsToRewrite.insert(BCI);
+ continue;
+ }
+ }
+
return false;
}
@@ -1360,6 +1389,18 @@
// If we have instructions that need to be rewritten for this to be promotable
// take care of it now.
for (unsigned i = 0, e = InstsToRewrite.size(); i != e; ++i) {
+ if (BitCastInst *BCI = dyn_cast<BitCastInst>(InstsToRewrite[i])) {
+ // This could only be a bitcast used by nothing but lifetime intrinsics.
+ for (BitCastInst::use_iterator I = BCI->use_begin(), E = BCI->use_end();
+ I != E;) {
+ Use &U = I.getUse();
+ ++I;
+ cast<Instruction>(U.getUser())->eraseFromParent();
+ }
+ BCI->eraseFromParent();
+ continue;
+ }
+
if (SelectInst *SI = dyn_cast<SelectInst>(InstsToRewrite[i])) {
// Selects in InstsToRewrite only have load uses. Rewrite each as two
// loads with a new select.
@@ -1692,6 +1733,10 @@
isSafeMemAccess(Offset, TD->getTypeAllocSize(SIType),
SIType, true, Info, SI, true /*AllowWholeAccess*/);
Info.hasALoadOrStore = true;
+ } else if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(User)) {
+ if (II->getIntrinsicID() != Intrinsic::lifetime_start &&
+ II->getIntrinsicID() != Intrinsic::lifetime_end)
+ return MarkUnsafe(Info, User);
} else if (isa<PHINode>(User) || isa<SelectInst>(User)) {
isSafePHISelectUseForScalarRepl(User, Offset, Info);
} else {
@@ -1929,6 +1974,14 @@
// address operand will be updated, so nothing else needs to be done.
continue;
}
+
+ if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(User)) {
+ if (II->getIntrinsicID() == Intrinsic::lifetime_start ||
+ II->getIntrinsicID() == Intrinsic::lifetime_end) {
+ RewriteLifetimeIntrinsic(II, AI, Offset, NewElts);
+ }
+ continue;
+ }
if (LoadInst *LI = dyn_cast<LoadInst>(User)) {
Type *LIType = LI->getType();
@@ -2086,8 +2139,7 @@
}
Instruction *Val = NewElts[Idx];
if (NewArgs.size() > 1) {
- Val = GetElementPtrInst::CreateInBounds(Val, NewArgs.begin(),
- NewArgs.end(), "", GEPI);
+ Val = GetElementPtrInst::CreateInBounds(Val, NewArgs, "", GEPI);
Val->takeName(GEPI);
}
if (Val->getType() != GEPI->getType())
@@ -2096,6 +2148,62 @@
DeadInsts.push_back(GEPI);
}
+/// RewriteLifetimeIntrinsic - II is a lifetime.start/lifetime.end. Rewrite it
+/// to mark the lifetime of the scalarized memory.
+void SROA::RewriteLifetimeIntrinsic(IntrinsicInst *II, AllocaInst *AI,
+ uint64_t Offset,
+ SmallVector<AllocaInst*, 32> &NewElts) {
+ ConstantInt *OldSize = cast<ConstantInt>(II->getArgOperand(0));
+ // Put matching lifetime markers on everything from Offset up to
+ // Offset+OldSize.
+ Type *AIType = AI->getAllocatedType();
+ uint64_t NewOffset = Offset;
+ Type *IdxTy;
+ uint64_t Idx = FindElementAndOffset(AIType, NewOffset, IdxTy);
+
+ IRBuilder<> Builder(II);
+ uint64_t Size = OldSize->getLimitedValue();
+
+ if (NewOffset) {
+ // Splice the first element and index 'NewOffset' bytes in. SROA will
+ // split the alloca again later.
+ Value *V = Builder.CreateBitCast(NewElts[Idx], Builder.getInt8PtrTy());
+ V = Builder.CreateGEP(V, Builder.getInt64(NewOffset));
+
+ IdxTy = NewElts[Idx]->getAllocatedType();
+ uint64_t EltSize = TD->getTypeAllocSize(IdxTy) - NewOffset;
+ if (EltSize > Size) {
+ EltSize = Size;
+ Size = 0;
+ } else {
+ Size -= EltSize;
+ }
+ if (II->getIntrinsicID() == Intrinsic::lifetime_start)
+ Builder.CreateLifetimeStart(V, Builder.getInt64(EltSize));
+ else
+ Builder.CreateLifetimeEnd(V, Builder.getInt64(EltSize));
+ ++Idx;
+ }
+
+ for (; Idx != NewElts.size() && Size; ++Idx) {
+ IdxTy = NewElts[Idx]->getAllocatedType();
+ uint64_t EltSize = TD->getTypeAllocSize(IdxTy);
+ if (EltSize > Size) {
+ EltSize = Size;
+ Size = 0;
+ } else {
+ Size -= EltSize;
+ }
+ if (II->getIntrinsicID() == Intrinsic::lifetime_start)
+ Builder.CreateLifetimeStart(NewElts[Idx],
+ Builder.getInt64(EltSize));
+ else
+ Builder.CreateLifetimeEnd(NewElts[Idx],
+ Builder.getInt64(EltSize));
+ }
+ DeadInsts.push_back(II);
+}
+
/// RewriteMemIntrinUserOfAlloca - MI is a memcpy/memset/memmove from or to AI.
/// Rewrite it to copy or set the elements of the scalarized memory.
void SROA::RewriteMemIntrinUserOfAlloca(MemIntrinsic *MI, Instruction *Inst,
@@ -2163,7 +2271,7 @@
if (OtherPtr) {
Value *Idx[2] = { Zero,
ConstantInt::get(Type::getInt32Ty(MI->getContext()), i) };
- OtherElt = GetElementPtrInst::CreateInBounds(OtherPtr, Idx, Idx + 2,
+ OtherElt = GetElementPtrInst::CreateInBounds(OtherPtr, Idx,
OtherPtr->getName()+"."+Twine(i),
MI);
uint64_t EltOffset;
Modified: llvm/branches/exception-handling-rewrite/lib/Transforms/Utils/CodeExtractor.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Transforms/Utils/CodeExtractor.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Transforms/Utils/CodeExtractor.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Transforms/Utils/CodeExtractor.cpp Mon Jul 25 20:29:47 2011
@@ -317,8 +317,7 @@
Idx[1] = ConstantInt::get(Type::getInt32Ty(header->getContext()), i);
TerminatorInst *TI = newFunction->begin()->getTerminator();
GetElementPtrInst *GEP =
- GetElementPtrInst::Create(AI, Idx, Idx+2,
- "gep_" + inputs[i]->getName(), TI);
+ GetElementPtrInst::Create(AI, Idx, "gep_" + inputs[i]->getName(), TI);
RewriteVal = new LoadInst(GEP, "loadgep_" + inputs[i]->getName(), TI);
} else
RewriteVal = AI++;
@@ -420,7 +419,7 @@
Idx[0] = Constant::getNullValue(Type::getInt32Ty(Context));
Idx[1] = ConstantInt::get(Type::getInt32Ty(Context), i);
GetElementPtrInst *GEP =
- GetElementPtrInst::Create(Struct, Idx, Idx + 2,
+ GetElementPtrInst::Create(Struct, Idx,
"gep_" + StructValues[i]->getName());
codeReplacer->getInstList().push_back(GEP);
StoreInst *SI = new StoreInst(StructValues[i], GEP);
@@ -446,7 +445,7 @@
Idx[0] = Constant::getNullValue(Type::getInt32Ty(Context));
Idx[1] = ConstantInt::get(Type::getInt32Ty(Context), FirstOut + i);
GetElementPtrInst *GEP
- = GetElementPtrInst::Create(Struct, Idx, Idx + 2,
+ = GetElementPtrInst::Create(Struct, Idx,
"gep_reload_" + outputs[i]->getName());
codeReplacer->getInstList().push_back(GEP);
Output = GEP;
@@ -561,7 +560,7 @@
Idx[1] = ConstantInt::get(Type::getInt32Ty(Context),
FirstOut+out);
GetElementPtrInst *GEP =
- GetElementPtrInst::Create(OAI, Idx, Idx + 2,
+ GetElementPtrInst::Create(OAI, Idx,
"gep_" + outputs[out]->getName(),
NTRet);
new StoreInst(outputs[out], GEP, NTRet);
Modified: llvm/branches/exception-handling-rewrite/lib/Transforms/Utils/LoopUnroll.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Transforms/Utils/LoopUnroll.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Transforms/Utils/LoopUnroll.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Transforms/Utils/LoopUnroll.cpp Mon Jul 25 20:29:47 2011
@@ -106,6 +106,18 @@
/// branch instruction. However, if the trip count (and multiple) are not known,
/// loop unrolling will mostly produce more code that is no faster.
///
+/// TripCount is generally defined as the number of times the loop header
+/// executes. UnrollLoop relaxes the definition to permit early exits: here
+/// TripCount is the iteration on which control exits LatchBlock if no early
+/// exits were taken. Note that UnrollLoop assumes that the loop counter test
+/// terminates LatchBlock in order to remove unnecesssary instances of the
+/// test. In other words, control may exit the loop prior to TripCount
+/// iterations via an early branch, but control may not exit the loop from the
+/// LatchBlock's terminator prior to TripCount iterations.
+///
+/// Similarly, TripMultiple divides the number of times that the LatchBlock may
+/// execute without exiting the loop.
+///
/// The LoopInfo Analysis that is passed will be kept consistent.
///
/// If a LoopPassManager is passed in, and the loop is fully removed, it will be
Modified: llvm/branches/exception-handling-rewrite/lib/Transforms/Utils/LowerInvoke.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/Transforms/Utils/LowerInvoke.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/Transforms/Utils/LowerInvoke.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/Transforms/Utils/LowerInvoke.cpp Mon Jul 25 20:29:47 2011
@@ -455,8 +455,7 @@
Value *Idx[] = { Constant::getNullValue(Type::getInt32Ty(F.getContext())),
ConstantInt::get(Type::getInt32Ty(F.getContext()), 1) };
- OldJmpBufPtr = GetElementPtrInst::Create(JmpBuf, &Idx[0], &Idx[2],
- "OldBuf",
+ OldJmpBufPtr = GetElementPtrInst::Create(JmpBuf, Idx, "OldBuf",
EntryBB->getTerminator());
// Copy the JBListHead to the alloca.
@@ -502,8 +501,7 @@
"setjmp.cont");
Idx[1] = ConstantInt::get(Type::getInt32Ty(F.getContext()), 0);
- Value *JmpBufPtr = GetElementPtrInst::Create(JmpBuf, &Idx[0], &Idx[2],
- "TheJmpBuf",
+ Value *JmpBufPtr = GetElementPtrInst::Create(JmpBuf, Idx, "TheJmpBuf",
EntryBB->getTerminator());
JmpBufPtr = new BitCastInst(JmpBufPtr,
Type::getInt8PtrTy(F.getContext()),
@@ -557,8 +555,7 @@
// Get a pointer to the jmpbuf and longjmp.
Value *Idx[] = { Constant::getNullValue(Type::getInt32Ty(F.getContext())),
ConstantInt::get(Type::getInt32Ty(F.getContext()), 0) };
- Idx[0] = GetElementPtrInst::Create(BufPtr, &Idx[0], &Idx[2], "JmpBuf",
- UnwindBlock);
+ Idx[0] = GetElementPtrInst::Create(BufPtr, Idx, "JmpBuf", UnwindBlock);
Idx[0] = new BitCastInst(Idx[0],
Type::getInt8PtrTy(F.getContext()),
"tmp", UnwindBlock);
Modified: llvm/branches/exception-handling-rewrite/lib/VMCore/AsmWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/VMCore/AsmWriter.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/VMCore/AsmWriter.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/VMCore/AsmWriter.cpp Mon Jul 25 20:29:47 2011
@@ -1098,6 +1098,7 @@
void writeOperand(const Value *Op, bool PrintType);
void writeParamOperand(const Value *Operand, Attributes Attrs);
+ void writeAtomic(AtomicOrdering Ordering, SynchronizationScope SynchScope);
void writeAllMDNodes();
@@ -1128,6 +1129,28 @@
WriteAsOperandInternal(Out, Operand, &TypePrinter, &Machine, TheModule);
}
+void AssemblyWriter::writeAtomic(AtomicOrdering Ordering,
+ SynchronizationScope SynchScope) {
+ if (Ordering == NotAtomic)
+ return;
+
+ switch (SynchScope) {
+ default: Out << " <bad scope " << int(SynchScope) << ">"; break;
+ case SingleThread: Out << " singlethread"; break;
+ case CrossThread: break;
+ }
+
+ switch (Ordering) {
+ default: Out << " <bad ordering " << int(Ordering) << ">"; break;
+ case Unordered: Out << " unordered"; break;
+ case Monotonic: Out << " monotonic"; break;
+ case Acquire: Out << " acquire"; break;
+ case Release: Out << " release"; break;
+ case AcquireRelease: Out << " acq_rel"; break;
+ case SequentiallyConsistent: Out << " seq_cst"; break;
+ }
+}
+
void AssemblyWriter::writeParamOperand(const Value *Operand,
Attributes Attrs) {
if (Operand == 0) {
@@ -1910,6 +1933,8 @@
Out << ", align " << cast<LoadInst>(I).getAlignment();
} else if (isa<StoreInst>(I) && cast<StoreInst>(I).getAlignment()) {
Out << ", align " << cast<StoreInst>(I).getAlignment();
+ } else if (const FenceInst *FI = dyn_cast<FenceInst>(&I)) {
+ writeAtomic(FI->getOrdering(), FI->getSynchScope());
}
// Print Metadata info.
Modified: llvm/branches/exception-handling-rewrite/lib/VMCore/ConstantFold.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/VMCore/ConstantFold.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/VMCore/ConstantFold.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/VMCore/ConstantFold.cpp Mon Jul 25 20:29:47 2011
@@ -2173,7 +2173,7 @@
if (isa<UndefValue>(C)) {
PointerType *Ptr = cast<PointerType>(C->getType());
- Type *Ty = GetElementPtrInst::getIndexedType(Ptr, Idxs.begin(), Idxs.end());
+ Type *Ty = GetElementPtrInst::getIndexedType(Ptr, Idxs);
assert(Ty != 0 && "Invalid indices for GEP!");
return UndefValue::get(PointerType::get(Ty, Ptr->getAddressSpace()));
}
@@ -2187,8 +2187,7 @@
}
if (isNull) {
PointerType *Ptr = cast<PointerType>(C->getType());
- Type *Ty = GetElementPtrInst::getIndexedType(Ptr, Idxs.begin(),
- Idxs.end());
+ Type *Ty = GetElementPtrInst::getIndexedType(Ptr, Idxs);
assert(Ty != 0 && "Invalid indices for GEP!");
return ConstantPointerNull::get(PointerType::get(Ty,
Ptr->getAddressSpace()));
Modified: llvm/branches/exception-handling-rewrite/lib/VMCore/Constants.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/VMCore/Constants.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/VMCore/Constants.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/VMCore/Constants.cpp Mon Jul 25 20:29:47 2011
@@ -573,21 +573,16 @@
//===----------------------------------------------------------------------===//
-ConstantArray::ConstantArray(ArrayType *T,
- const std::vector<Constant*> &V)
+ConstantArray::ConstantArray(ArrayType *T, ArrayRef<Constant *> V)
: Constant(T, ConstantArrayVal,
OperandTraits<ConstantArray>::op_end(this) - V.size(),
V.size()) {
assert(V.size() == T->getNumElements() &&
"Invalid initializer vector for constant array");
- Use *OL = OperandList;
- for (std::vector<Constant*>::const_iterator I = V.begin(), E = V.end();
- I != E; ++I, ++OL) {
- Constant *C = *I;
- assert(C->getType() == T->getElementType() &&
+ for (unsigned i = 0, e = V.size(); i != e; ++i)
+ assert(V[i]->getType() == T->getElementType() &&
"Initializer for array element doesn't match array element type!");
- *OL = C;
- }
+ std::copy(V.begin(), V.end(), op_begin());
}
Constant *ConstantArray::get(ArrayType *Ty, ArrayRef<Constant*> V) {
@@ -653,21 +648,16 @@
}
-ConstantStruct::ConstantStruct(StructType *T,
- const std::vector<Constant*> &V)
+ConstantStruct::ConstantStruct(StructType *T, ArrayRef<Constant *> V)
: Constant(T, ConstantStructVal,
OperandTraits<ConstantStruct>::op_end(this) - V.size(),
V.size()) {
assert((T->isOpaque() || V.size() == T->getNumElements()) &&
"Invalid initializer vector for constant structure");
- Use *OL = OperandList;
- for (std::vector<Constant*>::const_iterator I = V.begin(), E = V.end();
- I != E; ++I, ++OL) {
- Constant *C = *I;
- assert((T->isOpaque() || C->getType() == T->getElementType(I-V.begin())) &&
+ for (unsigned i = 0, e = V.size(); i != e; ++i)
+ assert((T->isOpaque() || V[i]->getType() == T->getElementType(i)) &&
"Initializer for struct element doesn't match struct element type!");
- *OL = C;
- }
+ std::copy(V.begin(), V.end(), op_begin());
}
// ConstantStruct accessors.
@@ -692,19 +682,14 @@
return get(T, Values);
}
-ConstantVector::ConstantVector(VectorType *T,
- const std::vector<Constant*> &V)
+ConstantVector::ConstantVector(VectorType *T, ArrayRef<Constant *> V)
: Constant(T, ConstantVectorVal,
OperandTraits<ConstantVector>::op_end(this) - V.size(),
V.size()) {
- Use *OL = OperandList;
- for (std::vector<Constant*>::const_iterator I = V.begin(), E = V.end();
- I != E; ++I, ++OL) {
- Constant *C = *I;
- assert(C->getType() == T->getElementType() &&
+ for (size_t i = 0, e = V.size(); i != e; i++)
+ assert(V[i]->getType() == T->getElementType() &&
"Initializer for vector element doesn't match vector element type!");
- *OL = C;
- }
+ std::copy(V.begin(), V.end(), op_begin());
}
// ConstantVector accessors.
@@ -1598,8 +1583,7 @@
return FC; // Fold a few common cases.
// Get the result type of the getelementptr!
- Type *Ty =
- GetElementPtrInst::getIndexedType(C->getType(), Idxs.begin(), Idxs.end());
+ Type *Ty = GetElementPtrInst::getIndexedType(C->getType(), Idxs);
assert(Ty && "GEP indices invalid!");
unsigned AS = cast<PointerType>(C->getType())->getAddressSpace();
Type *ReqTy = Ty->getPointerTo(AS);
Modified: llvm/branches/exception-handling-rewrite/lib/VMCore/Instruction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/VMCore/Instruction.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/VMCore/Instruction.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/VMCore/Instruction.cpp Mon Jul 25 20:29:47 2011
@@ -128,6 +128,7 @@
case Alloca: return "alloca";
case Load: return "load";
case Store: return "store";
+ case Fence: return "fence";
case GetElementPtr: return "getelementptr";
// Convert instructions...
Modified: llvm/branches/exception-handling-rewrite/lib/VMCore/Instructions.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/VMCore/Instructions.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/VMCore/Instructions.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/VMCore/Instructions.cpp Mon Jul 25 20:29:47 2011
@@ -1085,31 +1085,34 @@
}
//===----------------------------------------------------------------------===//
-// GetElementPtrInst Implementation
+// FenceInst Implementation
//===----------------------------------------------------------------------===//
-static unsigned retrieveAddrSpace(const Value *Val) {
- return cast<PointerType>(Val->getType())->getAddressSpace();
-}
-
-void GetElementPtrInst::init(Value *Ptr, Value* const *Idx, unsigned NumIdx,
- const Twine &Name) {
- assert(NumOperands == 1+NumIdx && "NumOperands not initialized?");
- Use *OL = OperandList;
- OL[0] = Ptr;
-
- for (unsigned i = 0; i != NumIdx; ++i)
- OL[i+1] = Idx[i];
-
- setName(Name);
+FenceInst::FenceInst(LLVMContext &C, AtomicOrdering Ordering,
+ SynchronizationScope SynchScope,
+ Instruction *InsertBefore)
+ : Instruction(Type::getVoidTy(C), Fence, 0, 0, InsertBefore) {
+ setOrdering(Ordering);
+ setSynchScope(SynchScope);
+}
+
+FenceInst::FenceInst(LLVMContext &C, AtomicOrdering Ordering,
+ SynchronizationScope SynchScope,
+ BasicBlock *InsertAtEnd)
+ : Instruction(Type::getVoidTy(C), Fence, 0, 0, InsertAtEnd) {
+ setOrdering(Ordering);
+ setSynchScope(SynchScope);
}
-void GetElementPtrInst::init(Value *Ptr, Value *Idx, const Twine &Name) {
- assert(NumOperands == 2 && "NumOperands not initialized?");
- Use *OL = OperandList;
- OL[0] = Ptr;
- OL[1] = Idx;
+//===----------------------------------------------------------------------===//
+// GetElementPtrInst Implementation
+//===----------------------------------------------------------------------===//
+void GetElementPtrInst::init(Value *Ptr, ArrayRef<Value *> IdxList,
+ const Twine &Name) {
+ assert(NumOperands == 1 + IdxList.size() && "NumOperands not initialized?");
+ OperandList[0] = Ptr;
+ std::copy(IdxList.begin(), IdxList.end(), op_begin() + 1);
setName(Name);
}
@@ -1118,34 +1121,10 @@
OperandTraits<GetElementPtrInst>::op_end(this)
- GEPI.getNumOperands(),
GEPI.getNumOperands()) {
- Use *OL = OperandList;
- Use *GEPIOL = GEPI.OperandList;
- for (unsigned i = 0, E = NumOperands; i != E; ++i)
- OL[i] = GEPIOL[i];
+ std::copy(GEPI.op_begin(), GEPI.op_end(), op_begin());
SubclassOptionalData = GEPI.SubclassOptionalData;
}
-GetElementPtrInst::GetElementPtrInst(Value *Ptr, Value *Idx,
- const Twine &Name, Instruction *InBe)
- : Instruction(PointerType::get(
- checkGEPType(getIndexedType(Ptr->getType(),Idx)), retrieveAddrSpace(Ptr)),
- GetElementPtr,
- OperandTraits<GetElementPtrInst>::op_end(this) - 2,
- 2, InBe) {
- init(Ptr, Idx, Name);
-}
-
-GetElementPtrInst::GetElementPtrInst(Value *Ptr, Value *Idx,
- const Twine &Name, BasicBlock *IAE)
- : Instruction(PointerType::get(
- checkGEPType(getIndexedType(Ptr->getType(),Idx)),
- retrieveAddrSpace(Ptr)),
- GetElementPtr,
- OperandTraits<GetElementPtrInst>::op_end(this) - 2,
- 2, IAE) {
- init(Ptr, Idx, Name);
-}
-
/// getIndexedType - Returns the type of the element that would be accessed with
/// a gep instruction with the specified parameters.
///
@@ -1156,14 +1135,13 @@
/// pointer type.
///
template <typename IndexTy>
-static Type *getIndexedTypeInternal(Type *Ptr, IndexTy const *Idxs,
- unsigned NumIdx) {
+static Type *getIndexedTypeInternal(Type *Ptr, ArrayRef<IndexTy> IdxList) {
PointerType *PTy = dyn_cast<PointerType>(Ptr);
if (!PTy) return 0; // Type isn't a pointer type!
Type *Agg = PTy->getElementType();
// Handle the special case of the empty set index set, which is always valid.
- if (NumIdx == 0)
+ if (IdxList.empty())
return Agg;
// If there is at least one index, the top level type must be sized, otherwise
@@ -1172,44 +1150,29 @@
return 0;
unsigned CurIdx = 1;
- for (; CurIdx != NumIdx; ++CurIdx) {
+ for (; CurIdx != IdxList.size(); ++CurIdx) {
CompositeType *CT = dyn_cast<CompositeType>(Agg);
if (!CT || CT->isPointerTy()) return 0;
- IndexTy Index = Idxs[CurIdx];
+ IndexTy Index = IdxList[CurIdx];
if (!CT->indexValid(Index)) return 0;
Agg = CT->getTypeAtIndex(Index);
}
- return CurIdx == NumIdx ? Agg : 0;
+ return CurIdx == IdxList.size() ? Agg : 0;
}
-Type *GetElementPtrInst::getIndexedType(Type *Ptr, Value* const *Idxs,
- unsigned NumIdx) {
- return getIndexedTypeInternal(Ptr, Idxs, NumIdx);
+Type *GetElementPtrInst::getIndexedType(Type *Ptr, ArrayRef<Value *> IdxList) {
+ return getIndexedTypeInternal(Ptr, IdxList);
}
Type *GetElementPtrInst::getIndexedType(Type *Ptr,
- Constant* const *Idxs,
- unsigned NumIdx) {
- return getIndexedTypeInternal(Ptr, Idxs, NumIdx);
+ ArrayRef<Constant *> IdxList) {
+ return getIndexedTypeInternal(Ptr, IdxList);
}
-Type *GetElementPtrInst::getIndexedType(Type *Ptr,
- uint64_t const *Idxs,
- unsigned NumIdx) {
- return getIndexedTypeInternal(Ptr, Idxs, NumIdx);
+Type *GetElementPtrInst::getIndexedType(Type *Ptr, ArrayRef<uint64_t> IdxList) {
+ return getIndexedTypeInternal(Ptr, IdxList);
}
-Type *GetElementPtrInst::getIndexedType(Type *Ptr, Value *Idx) {
- PointerType *PTy = dyn_cast<PointerType>(Ptr);
- if (!PTy) return 0; // Type isn't a pointer type!
-
- // Check the pointer index.
- if (!PTy->indexValid(Idx)) return 0;
-
- return PTy->getElementType();
-}
-
-
/// hasAllZeroIndices - Return true if all of the indices of this GEP are
/// zeros. If so, the result pointer and the first operand have the same
/// value, just potentially different types.
@@ -3164,6 +3127,10 @@
isVolatile(), getAlignment());
}
+FenceInst *FenceInst::clone_impl() const {
+ return new FenceInst(getContext(), getOrdering(), getSynchScope());
+}
+
TruncInst *TruncInst::clone_impl() const {
return new TruncInst(getOperand(0), getType());
}
Modified: llvm/branches/exception-handling-rewrite/lib/VMCore/Verifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/lib/VMCore/Verifier.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/lib/VMCore/Verifier.cpp (original)
+++ llvm/branches/exception-handling-rewrite/lib/VMCore/Verifier.cpp Mon Jul 25 20:29:47 2011
@@ -278,6 +278,7 @@
void visitUserOp1(Instruction &I);
void visitUserOp2(Instruction &I) { visitUserOp1(I); }
void visitIntrinsicFunctionCall(Intrinsic::ID ID, CallInst &CI);
+ void visitFenceInst(FenceInst &FI);
void visitAllocaInst(AllocaInst &AI);
void visitExtractValueInst(ExtractValueInst &EVI);
void visitInsertValueInst(InsertValueInst &IVI);
@@ -1276,8 +1277,7 @@
void Verifier::visitGetElementPtrInst(GetElementPtrInst &GEP) {
SmallVector<Value*, 16> Idxs(GEP.idx_begin(), GEP.idx_end());
Type *ElTy =
- GetElementPtrInst::getIndexedType(GEP.getOperand(0)->getType(),
- Idxs.begin(), Idxs.end());
+ GetElementPtrInst::getIndexedType(GEP.getOperand(0)->getType(), Idxs);
Assert1(ElTy, "Invalid indices for GEP pointer type!", &GEP);
Assert2(GEP.getType()->isPointerTy() &&
cast<PointerType>(GEP.getType())->getElementType() == ElTy,
@@ -1316,6 +1316,15 @@
visitInstruction(AI);
}
+void Verifier::visitFenceInst(FenceInst &FI) {
+ const AtomicOrdering Ordering = FI.getOrdering();
+ Assert1(Ordering == Acquire || Ordering == Release ||
+ Ordering == AcquireRelease || Ordering == SequentiallyConsistent,
+ "fence instructions may only have "
+ " acquire, release, acq_rel, or seq_cst ordering.", &FI);
+ visitInstruction(FI);
+}
+
void Verifier::visitExtractValueInst(ExtractValueInst &EVI) {
Assert1(ExtractValueInst::getIndexedType(EVI.getAggregateOperand()->getType(),
EVI.getIndices()) ==
Modified: llvm/branches/exception-handling-rewrite/test/CodeGen/X86/avx-256-splat.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/test/CodeGen/X86/avx-256-splat.ll?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/test/CodeGen/X86/avx-256-splat.ll (original)
+++ llvm/branches/exception-handling-rewrite/test/CodeGen/X86/avx-256-splat.ll Mon Jul 25 20:29:47 2011
@@ -5,7 +5,6 @@
; CHECK: vextractf128 $0
; CHECK-NEXT: punpcklbw
; CHECK-NEXT: punpckhbw
-; CHECK-NEXT: vinsertf128 $0
; CHECK-NEXT: vinsertf128 $1
; CHECK-NEXT: vpermilps $85
define <32 x i8> @funcA(<32 x i8> %a) nounwind uwtable readnone ssp {
@@ -16,7 +15,6 @@
; CHECK: vextractf128 $0
; CHECK-NEXT: punpckhwd
-; CHECK-NEXT: vinsertf128 $0
; CHECK-NEXT: vinsertf128 $1
; CHECK-NEXT: vpermilps $85
define <16 x i16> @funcB(<16 x i16> %a) nounwind uwtable readnone ssp {
@@ -25,3 +23,25 @@
ret <16 x i16> %shuffle
}
+; CHECK: vmovd
+; CHECK-NEXT: movlhps
+; CHECK-NEXT: vinsertf128 $1
+define <4 x i64> @funcC(i64 %q) nounwind uwtable readnone ssp {
+entry:
+ %vecinit.i = insertelement <4 x i64> undef, i64 %q, i32 0
+ %vecinit2.i = insertelement <4 x i64> %vecinit.i, i64 %q, i32 1
+ %vecinit4.i = insertelement <4 x i64> %vecinit2.i, i64 %q, i32 2
+ %vecinit6.i = insertelement <4 x i64> %vecinit4.i, i64 %q, i32 3
+ ret <4 x i64> %vecinit6.i
+}
+
+; CHECK: vshufpd
+; CHECK-NEXT: vinsertf128 $1
+define <4 x double> @funcD(double %q) nounwind uwtable readnone ssp {
+entry:
+ %vecinit.i = insertelement <4 x double> undef, double %q, i32 0
+ %vecinit2.i = insertelement <4 x double> %vecinit.i, double %q, i32 1
+ %vecinit4.i = insertelement <4 x double> %vecinit2.i, double %q, i32 2
+ %vecinit6.i = insertelement <4 x double> %vecinit4.i, double %q, i32 3
+ ret <4 x double> %vecinit6.i
+}
Modified: llvm/branches/exception-handling-rewrite/test/CodeGen/X86/avx-256.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/test/CodeGen/X86/avx-256.ll?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/test/CodeGen/X86/avx-256.ll (original)
+++ llvm/branches/exception-handling-rewrite/test/CodeGen/X86/avx-256.ll Mon Jul 25 20:29:47 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86 -mcpu=corei7 -mattr=avx | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
@x = common global <8 x float> zeroinitializer, align 32
@y = common global <4 x double> zeroinitializer, align 32
@@ -13,3 +13,14 @@
ret void
}
+; CHECK: vpcmpeqd
+; CHECK: vinsertf128 $1
+define void @ones([0 x float]* nocapture %RET, [0 x float]* nocapture %aFOO) nounwind {
+allocas:
+ %ptr2vec615 = bitcast [0 x float]* %RET to <8 x float>*
+ store <8 x float> <float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float
+0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float
+0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000>, <8 x
+float>* %ptr2vec615, align 32
+ ret void
+}
Modified: llvm/branches/exception-handling-rewrite/test/CodeGen/X86/extractelement-load.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/test/CodeGen/X86/extractelement-load.ll?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/test/CodeGen/X86/extractelement-load.ll (original)
+++ llvm/branches/exception-handling-rewrite/test/CodeGen/X86/extractelement-load.ll Mon Jul 25 20:29:47 2011
@@ -1,9 +1,25 @@
-; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=yonah | not grep movd
-; RUN: llc < %s -march=x86-64 -mattr=+sse2 -mcpu=core2 | not grep movd
+; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=yonah | FileCheck %s
+; RUN: llc < %s -march=x86-64 -mattr=+sse2 -mcpu=core2 | FileCheck %s
define i32 @t(<2 x i64>* %val) nounwind {
+; CHECK: t:
+; CHECK-NOT: movd
+; CHECK: movl 8(
+; CHECK-NEXT: ret
%tmp2 = load <2 x i64>* %val, align 16 ; <<2 x i64>> [#uses=1]
%tmp3 = bitcast <2 x i64> %tmp2 to <4 x i32> ; <<4 x i32>> [#uses=1]
%tmp4 = extractelement <4 x i32> %tmp3, i32 2 ; <i32> [#uses=1]
ret i32 %tmp4
}
+
+; Case where extractelement of load ends up as undef.
+; (Making sure this doesn't crash.)
+define i32 @t2(<8 x i32>* %xp) {
+; CHECK: t2:
+; CHECK: ret
+ %x = load <8 x i32>* %xp
+ %Shuff68 = shufflevector <8 x i32> %x, <8 x i32> undef, <8 x i32> <i32
+undef, i32 7, i32 9, i32 undef, i32 13, i32 15, i32 1, i32 3>
+ %y = extractelement <8 x i32> %Shuff68, i32 0
+ ret i32 %y
+}
Modified: llvm/branches/exception-handling-rewrite/test/CodeGen/X86/palignr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/test/CodeGen/X86/palignr.ll?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/test/CodeGen/X86/palignr.ll (original)
+++ llvm/branches/exception-handling-rewrite/test/CodeGen/X86/palignr.ll Mon Jul 25 20:29:47 2011
@@ -1,7 +1,8 @@
-; RUN: llc < %s -march=x86 -mcpu=core2 | FileCheck %s
+; RUN: llc < %s -march=x86 -mcpu=core2 -mattr=+ssse3 | FileCheck %s
; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck --check-prefix=YONAH %s
define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind {
+; CHECK: test1:
; CHECK: pshufd
; CHECK-YONAH: pshufd
%C = shufflevector <4 x i32> %A, <4 x i32> undef, <4 x i32> < i32 1, i32 2, i32 3, i32 0 >
@@ -9,6 +10,7 @@
}
define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) nounwind {
+; CHECK: test2:
; CHECK: palignr
; CHECK-YONAH: shufps
%C = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> < i32 1, i32 2, i32 3, i32 4 >
@@ -16,43 +18,56 @@
}
define <4 x i32> @test3(<4 x i32> %A, <4 x i32> %B) nounwind {
+; CHECK: test3:
; CHECK: palignr
%C = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> < i32 1, i32 2, i32 undef, i32 4 >
ret <4 x i32> %C
}
define <4 x i32> @test4(<4 x i32> %A, <4 x i32> %B) nounwind {
+; CHECK: test4:
; CHECK: palignr
%C = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> < i32 6, i32 7, i32 undef, i32 1 >
ret <4 x i32> %C
}
define <4 x float> @test5(<4 x float> %A, <4 x float> %B) nounwind {
+; CHECK: test5:
; CHECK: palignr
%C = shufflevector <4 x float> %A, <4 x float> %B, <4 x i32> < i32 6, i32 7, i32 undef, i32 1 >
ret <4 x float> %C
}
define <8 x i16> @test6(<8 x i16> %A, <8 x i16> %B) nounwind {
+; CHECK: test6:
; CHECK: palignr
%C = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 3, i32 4, i32 undef, i32 6, i32 7, i32 8, i32 9, i32 10 >
ret <8 x i16> %C
}
define <8 x i16> @test7(<8 x i16> %A, <8 x i16> %B) nounwind {
+; CHECK: test7:
; CHECK: palignr
%C = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 undef, i32 6, i32 undef, i32 8, i32 9, i32 10, i32 11, i32 12 >
ret <8 x i16> %C
}
-define <8 x i16> @test8(<8 x i16> %A, <8 x i16> %B) nounwind {
-; CHECK: palignr
- %C = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 undef, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0 >
- ret <8 x i16> %C
-}
-
-define <16 x i8> @test9(<16 x i8> %A, <16 x i8> %B) nounwind {
+define <16 x i8> @test8(<16 x i8> %A, <16 x i8> %B) nounwind {
+; CHECK: test8:
; CHECK: palignr
%C = shufflevector <16 x i8> %A, <16 x i8> %B, <16 x i32> < i32 5, i32 6, i32 7, i32 undef, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20 >
ret <16 x i8> %C
}
+
+; Check that we don't do unary (circular on single operand) palignr incorrectly.
+; (It is possible, but before this testcase was committed, it was being done
+; incorrectly. In particular, one of the operands of the palignr node
+; was an UNDEF.)
+define <8 x i16> @test9(<8 x i16> %A, <8 x i16> %B) nounwind {
+; CHECK: test9:
+; CHECK-NOT: palignr
+; CHECK: pshufb
+ %C = shufflevector <8 x i16> %B, <8 x i16> %A, <8 x i32> < i32 undef, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0 >
+ ret <8 x i16> %C
+}
+
Modified: llvm/branches/exception-handling-rewrite/test/MC/ARM/basic-arm-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/test/MC/ARM/basic-arm-instructions.s?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/test/MC/ARM/basic-arm-instructions.s (original)
+++ llvm/branches/exception-handling-rewrite/test/MC/ARM/basic-arm-instructions.s Mon Jul 25 20:29:47 2011
@@ -1614,6 +1614,57 @@
@------------------------------------------------------------------------------
@ FIXME: SRS
@------------------------------------------------------------------------------
+
+
+ at ------------------------------------------------------------------------------
+@ SSAT
+ at ------------------------------------------------------------------------------
+ ssat r8, #1, r10
+ ssat r8, #1, r10, lsl #0
+ ssat r8, #1, r10, lsl #31
+ ssat r8, #1, r10, asr #32
+ ssat r8, #1, r10, asr #1
+
+@ CHECK: ssat r8, #1, r10 @ encoding: [0x1a,0x80,0xa0,0xe6]
+@ CHECK: ssat r8, #1, r10 @ encoding: [0x1a,0x80,0xa0,0xe6]
+@ CHECK: ssat r8, #1, r10, lsl #31 @ encoding: [0x9a,0x8f,0xa0,0xe6]
+@ CHECK: ssat r8, #1, r10, asr #32 @ encoding: [0x5a,0x80,0xa0,0xe6]
+@ CHECK: ssat r8, #1, r10, asr #1 @ encoding: [0xda,0x80,0xa0,0xe6]
+
+
+ at ------------------------------------------------------------------------------
+@ SSAT16
+ at ------------------------------------------------------------------------------
+ ssat16 r2, #1, r7
+ ssat16 r3, #16, r5
+
+@ CHECK: ssat16 r2, #1, r7 @ encoding: [0x37,0x2f,0xa0,0xe6]
+@ CHECK: ssat16 r3, #16, r5 @ encoding: [0x35,0x3f,0xaf,0xe6]
+
+
+ at ------------------------------------------------------------------------------
+@ SSAX
+ at ------------------------------------------------------------------------------
+ ssax r2, r3, r4
+ ssaxlt r2, r3, r4
+
+@ CHECK: ssax r2, r3, r4 @ encoding: [0x54,0x2f,0x13,0xe6]
+@ CHECK: ssaxlt r2, r3, r4 @ encoding: [0x54,0x2f,0x13,0xb6]
+
+ at ------------------------------------------------------------------------------
+@ SSUB16/SSUB8
+ at ------------------------------------------------------------------------------
+ ssub16 r1, r0, r6
+ ssub16ne r5, r3, r2
+ ssub8 r9, r2, r4
+ ssub8eq r5, r1, r2
+
+@ CHECK: ssub16 r1, r0, r6 @ encoding: [0x76,0x1f,0x10,0xe6]
+@ CHECK: ssub16ne r5, r3, r2 @ encoding: [0x72,0x5f,0x13,0x16]
+@ CHECK: ssub8 r9, r2, r4 @ encoding: [0xf4,0x9f,0x12,0xe6]
+@ CHECK: ssub8eq r5, r1, r2 @ encoding: [0xf2,0x5f,0x11,0x06]
+
+
@------------------------------------------------------------------------------
@ STM*
@------------------------------------------------------------------------------
Modified: llvm/branches/exception-handling-rewrite/test/MC/ARM/diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/test/MC/ARM/diagnostics.s?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/test/MC/ARM/diagnostics.s (original)
+++ llvm/branches/exception-handling-rewrite/test/MC/ARM/diagnostics.s Mon Jul 25 20:29:47 2011
@@ -160,3 +160,54 @@
@ CHECK: error: 'be' or 'le' operand expected
@ CHECK: setend 1
@ CHECK: ^
+
+
+ @ Out of range immediates and bad shift types for SSAT
+ ssat r8, #0, r10, lsl #8
+ ssat r8, #33, r10, lsl #8
+ ssat r8, #1, r10, lsl #-1
+ ssat r8, #1, r10, lsl #32
+ ssat r8, #1, r10, asr #0
+ ssat r8, #1, r10, asr #33
+ ssat r8, #1, r10, lsr #5
+ ssat r8, #1, r10, lsl fred
+ ssat r8, #1, r10, lsl #fred
+
+@ CHECK: error: invalid operand for instruction
+@ CHECK: ssat r8, #0, r10, lsl #8
+@ CHECK: ^
+@ CHECK: error: invalid operand for instruction
+@ CHECK: ssat r8, #33, r10, lsl #8
+@ CHECK: ^
+@ CHECK: error: 'lsr' shift amount must be in range [0,31]
+@ CHECK: ssat r8, #1, r10, lsl #-1
+@ CHECK: ^
+@ CHECK: error: 'lsr' shift amount must be in range [0,31]
+@ CHECK: ssat r8, #1, r10, lsl #32
+@ CHECK: ^
+@ CHECK: error: 'asr' shift amount must be in range [1,32]
+@ CHECK: ssat r8, #1, r10, asr #0
+@ CHECK: ^
+@ CHECK: error: 'asr' shift amount must be in range [1,32]
+@ CHECK: ssat r8, #1, r10, asr #33
+@ CHECK: ^
+@ CHECK: error: shift operator 'asr' or 'lsl' expected
+@ CHECK: ssat r8, #1, r10, lsr #5
+@ CHECK: ^
+@ CHECK: error: '#' expected
+@ CHECK: ssat r8, #1, r10, lsl fred
+@ CHECK: ^
+@ CHECK: error: shift amount must be an immediate
+@ CHECK: ssat r8, #1, r10, lsl #fred
+@ CHECK: ^
+
+ @ Out of range immediates for SSAT16
+ ssat16 r2, #0, r7
+ ssat16 r3, #17, r5
+
+@ CHECK: error: invalid operand for instruction
+@ CHECK: ssat16 r2, #0, r7
+@ CHECK: ^
+@ CHECK: error: invalid operand for instruction
+@ CHECK: ssat16 r3, #17, r5
+@ CHECK: ^
Modified: llvm/branches/exception-handling-rewrite/test/MC/AsmParser/labels.s
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/test/MC/AsmParser/labels.s?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/test/MC/AsmParser/labels.s (original)
+++ llvm/branches/exception-handling-rewrite/test/MC/AsmParser/labels.s Mon Jul 25 20:29:47 2011
@@ -35,9 +35,6 @@
// CHECK: .globl "a 3"
.globl "a 3"
-// CHECK: .weak "a 4"
- .weak "a 4"
-
// CHECK: .desc "a 5",1
.desc "a 5", 1
Modified: llvm/branches/exception-handling-rewrite/tools/llvm-mc/llvm-mc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/tools/llvm-mc/llvm-mc.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/tools/llvm-mc/llvm-mc.cpp (original)
+++ llvm/branches/exception-handling-rewrite/tools/llvm-mc/llvm-mc.cpp Mon Jul 25 20:29:47 2011
@@ -14,6 +14,7 @@
#include "llvm/MC/MCParser/AsmLexer.h"
#include "llvm/MC/MCParser/MCAsmLexer.h"
+#include "llvm/MC/MCAsmBackend.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCCodeEmitter.h"
#include "llvm/MC/MCInstPrinter.h"
@@ -23,10 +24,8 @@
#include "llvm/MC/MCSectionMachO.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetAsmParser.h"
#include "llvm/MC/SubtargetFeature.h"
-#include "llvm/MC/TargetAsmBackend.h"
-#include "llvm/MC/TargetAsmParser.h"
-#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetRegistry.h"
#include "llvm/Target/TargetSelect.h"
#include "llvm/ADT/OwningPtr.h"
@@ -369,24 +368,24 @@
MCInstPrinter *IP =
TheTarget->createMCInstPrinter(OutputAsmVariant, *MAI);
MCCodeEmitter *CE = 0;
- TargetAsmBackend *TAB = 0;
+ MCAsmBackend *MAB = 0;
if (ShowEncoding) {
- CE = TheTarget->createCodeEmitter(*MCII, *STI, Ctx);
- TAB = TheTarget->createAsmBackend(TripleName);
+ CE = TheTarget->createMCCodeEmitter(*MCII, *STI, Ctx);
+ MAB = TheTarget->createMCAsmBackend(TripleName);
}
Str.reset(TheTarget->createAsmStreamer(Ctx, FOS, /*asmverbose*/true,
/*useLoc*/ true,
- /*useCFI*/ true, IP, CE, TAB,
+ /*useCFI*/ true, IP, CE, MAB,
ShowInst));
} else if (FileType == OFT_Null) {
Str.reset(createNullStreamer(Ctx));
} else {
assert(FileType == OFT_ObjectFile && "Invalid file type!");
- MCCodeEmitter *CE = TheTarget->createCodeEmitter(*MCII, *STI, Ctx);
- TargetAsmBackend *TAB = TheTarget->createAsmBackend(TripleName);
- Str.reset(TheTarget->createObjectStreamer(TripleName, Ctx, *TAB,
- FOS, CE, RelaxAll,
- NoExecStack));
+ MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, *STI, Ctx);
+ MCAsmBackend *MAB = TheTarget->createMCAsmBackend(TripleName);
+ Str.reset(TheTarget->createMCObjectStreamer(TripleName, Ctx, *MAB,
+ FOS, CE, RelaxAll,
+ NoExecStack));
}
if (EnableLogging) {
@@ -395,7 +394,7 @@
OwningPtr<MCAsmParser> Parser(createMCAsmParser(*TheTarget, SrcMgr, Ctx,
*Str.get(), *MAI));
- OwningPtr<TargetAsmParser> TAP(TheTarget->createAsmParser(*STI, *Parser));
+ OwningPtr<MCTargetAsmParser> TAP(TheTarget->createMCAsmParser(*STI, *Parser));
if (!TAP) {
errs() << ProgName
<< ": error: this target does not support assembly parsing.\n";
@@ -452,17 +451,10 @@
// Initialize targets and assembly printers/parsers.
llvm::InitializeAllTargetInfos();
- // FIXME: We shouldn't need to initialize the Target(Machine)s.
- llvm::InitializeAllTargets();
llvm::InitializeAllTargetMCs();
- llvm::InitializeAllAsmPrinters();
llvm::InitializeAllAsmParsers();
llvm::InitializeAllDisassemblers();
- // Register the target printer for --version.
- // FIXME: Remove when we stop initializing the Target(Machine)s above.
- cl::AddExtraVersionPrinter(TargetRegistry::printRegisteredTargetsForVersion);
-
cl::ParseCommandLineOptions(argc, argv, "llvm machine code playground\n");
TripleName = Triple::normalize(TripleName);
Modified: llvm/branches/exception-handling-rewrite/tools/llvm-objdump/MCFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/tools/llvm-objdump/MCFunction.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/tools/llvm-objdump/MCFunction.cpp (original)
+++ llvm/branches/exception-handling-rewrite/tools/llvm-objdump/MCFunction.cpp Mon Jul 25 20:29:47 2011
@@ -54,6 +54,8 @@
}
}
Splits.insert(Index+Size);
+ } else if (Desc.isReturn()) {
+ Splits.insert(Index+Size);
}
Instructions.push_back(MCDecodedInst(Index, Size, Inst));
Modified: llvm/branches/exception-handling-rewrite/tools/llvm-objdump/MCFunction.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/tools/llvm-objdump/MCFunction.h?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/tools/llvm-objdump/MCFunction.h (original)
+++ llvm/branches/exception-handling-rewrite/tools/llvm-objdump/MCFunction.h Mon Jul 25 20:29:47 2011
@@ -48,6 +48,8 @@
succ_iterator succ_begin() const { return Succs.begin(); }
succ_iterator succ_end() const { return Succs.end(); }
+ bool contains(MCBasicBlock *BB) const { return Succs.count(BB); }
+
void addInst(const MCDecodedInst &Inst) { Insts.push_back(Inst); }
void addSucc(MCBasicBlock *BB) { Succs.insert(BB); }
};
Modified: llvm/branches/exception-handling-rewrite/tools/llvm-objdump/llvm-objdump.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/tools/llvm-objdump/llvm-objdump.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/tools/llvm-objdump/llvm-objdump.cpp (original)
+++ llvm/branches/exception-handling-rewrite/tools/llvm-objdump/llvm-objdump.cpp Mon Jul 25 20:29:47 2011
@@ -27,6 +27,7 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/Format.h"
+#include "llvm/Support/GraphWriter.h"
#include "llvm/Support/Host.h"
#include "llvm/Support/ManagedStatic.h"
#include "llvm/Support/MemoryBuffer.h"
@@ -280,12 +281,28 @@
Out << "digraph " << f.getName() << " {\n";
Out << "graph [ rankdir = \"LR\" ];\n";
for (MCFunction::iterator i = f.begin(), e = f.end(); i != e; ++i) {
+ bool hasPreds = false;
+ // Only print blocks that have predecessors.
+ // FIXME: Slow.
+ for (MCFunction::iterator pi = f.begin(), pe = f.end(); pi != pe;
+ ++pi)
+ if (pi->second.contains(&i->second)) {
+ hasPreds = true;
+ break;
+ }
+
+ if (!hasPreds && i != f.begin())
+ continue;
+
Out << '"' << (uintptr_t)&i->second << "\" [ label=\"<a>";
// Print instructions.
for (unsigned ii = 0, ie = i->second.getInsts().size(); ii != ie;
++ii) {
- IP->printInst(&i->second.getInsts()[ii].Inst, Out);
- Out << '|';
+ // Escape special chars and print the instruction in mnemonic form.
+ std::string Str;
+ raw_string_ostream OS(Str);
+ IP->printInst(&i->second.getInsts()[ii].Inst, OS);
+ Out << DOT::EscapeString(OS.str()) << '|';
}
Out << "<o>\" shape=\"record\" ];\n";
@@ -308,17 +325,10 @@
// Initialize targets and assembly printers/parsers.
llvm::InitializeAllTargetInfos();
- // FIXME: We shouldn't need to initialize the Target(Machine)s.
- llvm::InitializeAllTargets();
llvm::InitializeAllTargetMCs();
- llvm::InitializeAllAsmPrinters();
llvm::InitializeAllAsmParsers();
llvm::InitializeAllDisassemblers();
- // Register the target printer for --version.
- // FIXME: Remove when we stop initializing the Target(Machine)s above.
- cl::AddExtraVersionPrinter(TargetRegistry::printRegisteredTargetsForVersion);
-
cl::ParseCommandLineOptions(argc, argv, "llvm object file dumper\n");
TripleName = Triple::normalize(TripleName);
Modified: llvm/branches/exception-handling-rewrite/tools/llvmc/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/tools/llvmc/CMakeLists.txt?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/tools/llvmc/CMakeLists.txt (original)
+++ llvm/branches/exception-handling-rewrite/tools/llvmc/CMakeLists.txt Mon Jul 25 20:29:47 2011
@@ -1,4 +1,8 @@
-# add_subdirectory(src)
+add_subdirectory(src)
# TODO: support plugins and user-configured builds.
# See ./doc/LLVMC-Reference.rst "Customizing LLVMC: the compilation graph"
+
+if( LLVM_INCLUDE_EXAMPLES )
+ add_subdirectory(examples)
+endif()
Modified: llvm/branches/exception-handling-rewrite/tools/llvmc/examples/mcc16/Hooks.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/tools/llvmc/examples/mcc16/Hooks.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/tools/llvmc/examples/mcc16/Hooks.cpp (original)
+++ llvm/branches/exception-handling-rewrite/tools/llvmc/examples/mcc16/Hooks.cpp Mon Jul 25 20:29:47 2011
@@ -3,9 +3,10 @@
#include "llvm/Support/raw_ostream.h"
#include <string>
+#include <locale>
namespace llvmc {
- extern char *ProgramName;
+ extern const char *ProgramName;
namespace autogenerated {
extern llvm::cl::opt<std::string> Parameter_p;
@@ -31,6 +32,7 @@
// It is __partname format in lower case.
std::string
GetLowerCasePartDefine(void) {
+ std::locale loc;
std::string Partname;
if (autogenerated::Parameter_p.empty()) {
Partname = "16f1xxx";
@@ -40,7 +42,7 @@
std::string LowerCase;
for (unsigned i = 0; i < Partname.size(); i++) {
- LowerCase.push_back(std::tolower(Partname[i]));
+ LowerCase.push_back(std::tolower(Partname[i], loc));
}
return "__" + LowerCase;
@@ -48,6 +50,7 @@
std::string
GetUpperCasePartDefine(void) {
+ std::locale loc;
std::string Partname;
if (autogenerated::Parameter_p.empty()) {
Partname = "16f1xxx";
@@ -57,7 +60,7 @@
std::string UpperCase;
for (unsigned i = 0; i < Partname.size(); i++) {
- UpperCase.push_back(std::toupper(Partname[i]));
+ UpperCase.push_back(std::toupper(Partname[i], loc));
}
return "__" + UpperCase;
Modified: llvm/branches/exception-handling-rewrite/tools/lto/LTOCodeGenerator.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/tools/lto/LTOCodeGenerator.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/tools/lto/LTOCodeGenerator.cpp (original)
+++ llvm/branches/exception-handling-rewrite/tools/lto/LTOCodeGenerator.cpp Mon Jul 25 20:29:47 2011
@@ -263,7 +263,7 @@
break;
}
- // construct LTModule, hand over ownership of module and target
+ // construct LTOModule, hand over ownership of module and target
SubtargetFeatures Features;
Features.getDefaultSubtargetFeatures(llvm::Triple(Triple));
std::string FeatureStr = Features.getString();
Modified: llvm/branches/exception-handling-rewrite/tools/lto/LTOModule.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/tools/lto/LTOModule.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/tools/lto/LTOModule.cpp (original)
+++ llvm/branches/exception-handling-rewrite/tools/lto/LTOModule.cpp Mon Jul 25 20:29:47 2011
@@ -38,7 +38,7 @@
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/MC/SubtargetFeature.h"
-#include "llvm/MC/TargetAsmParser.h"
+#include "llvm/MC/MCTargetAsmParser.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetRegistry.h"
@@ -626,8 +626,8 @@
createMCSubtargetInfo(_target->getTargetTriple(),
_target->getTargetCPU(),
_target->getTargetFeatureString()));
- OwningPtr<TargetAsmParser>
- TAP(_target->getTarget().createAsmParser(*STI, *Parser.get()));
+ OwningPtr<MCTargetAsmParser>
+ TAP(_target->getTarget().createMCAsmParser(*STI, *Parser.get()));
Parser->setTargetParser(*TAP);
int Res = Parser->Run(false);
if (Res)
Modified: llvm/branches/exception-handling-rewrite/unittests/Transforms/Utils/Cloning.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/unittests/Transforms/Utils/Cloning.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/unittests/Transforms/Utils/Cloning.cpp (original)
+++ llvm/branches/exception-handling-rewrite/unittests/Transforms/Utils/Cloning.cpp Mon Jul 25 20:29:47 2011
@@ -124,7 +124,7 @@
Constant *Z = Constant::getNullValue(Type::getInt32Ty(context));
std::vector<Value *> ops;
ops.push_back(Z);
- GetElementPtrInst *GEP = GetElementPtrInst::Create(V, ops.begin(), ops.end());
+ GetElementPtrInst *GEP = GetElementPtrInst::Create(V, ops);
EXPECT_FALSE(this->clone(GEP)->isInBounds());
GEP->setIsInBounds();
Modified: llvm/branches/exception-handling-rewrite/utils/TableGen/AsmMatcherEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/utils/TableGen/AsmMatcherEmitter.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/utils/TableGen/AsmMatcherEmitter.cpp (original)
+++ llvm/branches/exception-handling-rewrite/utils/TableGen/AsmMatcherEmitter.cpp Mon Jul 25 20:29:47 2011
@@ -2172,7 +2172,7 @@
OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
OS << "#undef GET_ASSEMBLER_HEADER\n";
OS << " // This should be included into the middle of the declaration of\n";
- OS << " // your subclasses implementation of TargetAsmParser.\n";
+ OS << " // your subclasses implementation of MCTargetAsmParser.\n";
OS << " unsigned ComputeAvailableFeatures(uint64_t FeatureBits) const;\n";
OS << " enum MatchResultTy {\n";
OS << " Match_ConversionFail,\n";
Modified: llvm/branches/exception-handling-rewrite/utils/TableGen/EDEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/exception-handling-rewrite/utils/TableGen/EDEmitter.cpp?rev=136040&r1=136039&r2=136040&view=diff
==============================================================================
--- llvm/branches/exception-handling-rewrite/utils/TableGen/EDEmitter.cpp (original)
+++ llvm/branches/exception-handling-rewrite/utils/TableGen/EDEmitter.cpp Mon Jul 25 20:29:47 2011
@@ -587,6 +587,7 @@
IMM("neg_zero");
IMM("imm0_31");
IMM("imm0_31_m1");
+ IMM("imm1_16");
IMM("imm1_32");
IMM("nModImm");
IMM("imm0_7");
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