[llvm-branch-commits] [llvm-branch] r134804 - in /llvm/branches/type-system-rewrite: ./ docs/ include/llvm/ include/llvm/CodeGen/ include/llvm/MC/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/AsmPrinter/ lib/CodeGen/SelectionDAG/ lib/MC/ lib/MC/MCDisassembler/ lib/Support/ lib/Target/ARM/ lib/Target/ARM/AsmParser/ lib/Target/ARM/MCTargetDesc/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CBackend/ lib/Target/CellSPU/ lib/Target/CppBackend/ lib/Target/MBlaze/ lib/Target/MBlaze/AsmParser/ lib/Target/MSP430/ lib/Target/Mips...
Chris Lattner
sabre at nondot.org
Sat Jul 9 00:04:43 PDT 2011
Author: lattner
Date: Sat Jul 9 02:04:43 2011
New Revision: 134804
URL: http://llvm.org/viewvc/llvm-project?rev=134804&view=rev
Log:
Merging r134727 through r134803 from mainline into the branch
Added:
llvm/branches/type-system-rewrite/test/CodeGen/X86/allrem-moddi3.ll
- copied unchanged from r134803, llvm/trunk/test/CodeGen/X86/allrem-moddi3.ll
llvm/branches/type-system-rewrite/test/CodeGen/X86/fma.ll
- copied unchanged from r134803, llvm/trunk/test/CodeGen/X86/fma.ll
llvm/branches/type-system-rewrite/test/CodeGen/X86/reghinting.ll
- copied unchanged from r134803, llvm/trunk/test/CodeGen/X86/reghinting.ll
llvm/branches/type-system-rewrite/test/MC/ARM/mode-switch.s
- copied unchanged from r134803, llvm/trunk/test/MC/ARM/mode-switch.s
Modified:
llvm/branches/type-system-rewrite/ (props changed)
llvm/branches/type-system-rewrite/docs/LangRef.html
llvm/branches/type-system-rewrite/include/llvm/CodeGen/ISDOpcodes.h
llvm/branches/type-system-rewrite/include/llvm/CodeGen/MachineRegisterInfo.h
llvm/branches/type-system-rewrite/include/llvm/CodeGen/RuntimeLibcalls.h
llvm/branches/type-system-rewrite/include/llvm/Intrinsics.td
llvm/branches/type-system-rewrite/include/llvm/MC/MCSubtargetInfo.h
llvm/branches/type-system-rewrite/include/llvm/MC/SubtargetFeature.h
llvm/branches/type-system-rewrite/include/llvm/Target/TargetRegistry.h
llvm/branches/type-system-rewrite/include/llvm/Target/TargetSelect.h
llvm/branches/type-system-rewrite/include/llvm/Target/TargetSelectionDAG.td
llvm/branches/type-system-rewrite/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
llvm/branches/type-system-rewrite/lib/CodeGen/InlineSpiller.cpp
llvm/branches/type-system-rewrite/lib/CodeGen/LiveIntervalUnion.cpp
llvm/branches/type-system-rewrite/lib/CodeGen/LiveIntervalUnion.h
llvm/branches/type-system-rewrite/lib/CodeGen/RegAllocGreedy.cpp
llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/LegalizeTypes.h
llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/branches/type-system-rewrite/lib/CodeGen/VirtRegMap.h
llvm/branches/type-system-rewrite/lib/MC/MCAsmStreamer.cpp
llvm/branches/type-system-rewrite/lib/MC/MCDisassembler/EDDisassembler.cpp
llvm/branches/type-system-rewrite/lib/MC/MCSubtargetInfo.cpp
llvm/branches/type-system-rewrite/lib/MC/SubtargetFeature.cpp
llvm/branches/type-system-rewrite/lib/Support/Host.cpp
llvm/branches/type-system-rewrite/lib/Target/ARM/ARMAsmPrinter.cpp
llvm/branches/type-system-rewrite/lib/Target/ARM/ARMConstantIslandPass.cpp
llvm/branches/type-system-rewrite/lib/Target/ARM/ARMISelLowering.cpp
llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrInfo.td
llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrThumb.td
llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrThumb2.td
llvm/branches/type-system-rewrite/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/branches/type-system-rewrite/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
llvm/branches/type-system-rewrite/lib/Target/ARM/Thumb1FrameLowering.cpp
llvm/branches/type-system-rewrite/lib/Target/Alpha/AlphaISelLowering.cpp
llvm/branches/type-system-rewrite/lib/Target/Alpha/AlphaSubtarget.cpp
llvm/branches/type-system-rewrite/lib/Target/Blackfin/BlackfinSubtarget.cpp
llvm/branches/type-system-rewrite/lib/Target/CBackend/CBackend.cpp
llvm/branches/type-system-rewrite/lib/Target/CellSPU/SPUISelLowering.cpp
llvm/branches/type-system-rewrite/lib/Target/CellSPU/SPUSubtarget.cpp
llvm/branches/type-system-rewrite/lib/Target/CppBackend/CPPBackend.cpp
llvm/branches/type-system-rewrite/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp
llvm/branches/type-system-rewrite/lib/Target/MBlaze/MBlazeISelLowering.cpp
llvm/branches/type-system-rewrite/lib/Target/MBlaze/MBlazeSubtarget.cpp
llvm/branches/type-system-rewrite/lib/Target/MSP430/MSP430Subtarget.cpp
llvm/branches/type-system-rewrite/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp
llvm/branches/type-system-rewrite/lib/Target/Mips/MipsISelLowering.cpp
llvm/branches/type-system-rewrite/lib/Target/Mips/MipsSubtarget.cpp
llvm/branches/type-system-rewrite/lib/Target/PTX/PTXSubtarget.cpp
llvm/branches/type-system-rewrite/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/branches/type-system-rewrite/lib/Target/PowerPC/PPCSubtarget.cpp
llvm/branches/type-system-rewrite/lib/Target/Sparc/SparcISelLowering.cpp
llvm/branches/type-system-rewrite/lib/Target/Sparc/SparcSubtarget.cpp
llvm/branches/type-system-rewrite/lib/Target/SystemZ/SystemZISelLowering.cpp
llvm/branches/type-system-rewrite/lib/Target/SystemZ/SystemZSubtarget.cpp
llvm/branches/type-system-rewrite/lib/Target/X86/AsmParser/X86AsmParser.cpp
llvm/branches/type-system-rewrite/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
llvm/branches/type-system-rewrite/lib/Target/X86/X86ISelLowering.cpp
llvm/branches/type-system-rewrite/lib/Target/X86/X86Subtarget.cpp
llvm/branches/type-system-rewrite/lib/Target/X86/X86Subtarget.h
llvm/branches/type-system-rewrite/lib/Target/X86/X86TargetMachine.cpp
llvm/branches/type-system-rewrite/lib/Target/XCore/XCoreSubtarget.cpp
llvm/branches/type-system-rewrite/lib/Transforms/InstCombine/InstCombineCasts.cpp
llvm/branches/type-system-rewrite/lib/Transforms/Scalar/GVN.cpp
llvm/branches/type-system-rewrite/test/CodeGen/ARM/lsr-unfolded-offset.ll
llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/machine-licm.ll
llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/thumb2-bcc.ll
llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/thumb2-branch.ll
llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/thumb2-ifcvt1.ll
llvm/branches/type-system-rewrite/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll
llvm/branches/type-system-rewrite/test/CodeGen/X86/2010-07-11-FPStackLoneUse.ll
llvm/branches/type-system-rewrite/test/CodeGen/X86/2011-04-13-SchedCmpJmp.ll
llvm/branches/type-system-rewrite/test/CodeGen/X86/divide-by-constant.ll
llvm/branches/type-system-rewrite/test/CodeGen/X86/lsr-reuse-trunc.ll
llvm/branches/type-system-rewrite/test/CodeGen/X86/peep-test-3.ll
llvm/branches/type-system-rewrite/test/CodeGen/X86/sse1.ll
llvm/branches/type-system-rewrite/test/CodeGen/X86/sse3.ll
llvm/branches/type-system-rewrite/test/Transforms/GVN/2011-07-07-MatchIntrinsicExtract.ll
llvm/branches/type-system-rewrite/tools/llc/llc.cpp
llvm/branches/type-system-rewrite/tools/llvm-mc/llvm-mc.cpp
llvm/branches/type-system-rewrite/tools/lto/LTOModule.cpp
Propchange: llvm/branches/type-system-rewrite/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Sat Jul 9 02:04:43 2011
@@ -1,2 +1,2 @@
/llvm/branches/Apple/Pertwee:110850,110961
-/llvm/trunk:133420-134362,134364-134683,134685-134725
+/llvm/trunk:133420-134362,134364-134683,134685-134725,134727-134803
Modified: llvm/branches/type-system-rewrite/docs/LangRef.html
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/docs/LangRef.html?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/docs/LangRef.html (original)
+++ llvm/branches/type-system-rewrite/docs/LangRef.html Sat Jul 9 02:04:43 2011
@@ -239,6 +239,7 @@
<li><a href="#int_pow">'<tt>llvm.pow.*</tt>' Intrinsic</a></li>
<li><a href="#int_exp">'<tt>llvm.exp.*</tt>' Intrinsic</a></li>
<li><a href="#int_log">'<tt>llvm.log.*</tt>' Intrinsic</a></li>
+ <li><a href="#int_fma">'<tt>llvm.fma.*</tt>' Intrinsic</a></li>
</ol>
</li>
<li><a href="#int_manip">Bit Manipulation Intrinsics</a>
@@ -6497,6 +6498,37 @@
<p>This function returns the same values as the libm <tt>log</tt> functions
would, and handles error conditions in the same way.</p>
+<h4>
+ <a name="int_fma">'<tt>llvm.fma.*</tt>' Intrinsic</a>
+</h4>
+
+<div>
+
+<h5>Syntax:</h5>
+<p>This is an overloaded intrinsic. You can use <tt>llvm.fma</tt> on any
+ floating point or vector of floating point type. Not all targets support all
+ types however.</p>
+
+<pre>
+ declare float @llvm.fma.f32(float %a, float %b, float %c)
+ declare double @llvm.fma.f64(double %a, double %b, double %c)
+ declare x86_fp80 @llvm.fma.f80(x86_fp80 %a, x86_fp80 %b, x86_fp80 %c)
+ declare fp128 @llvm.fma.f128(fp128 %a, fp128 %b, fp128 %c)
+ declare ppc_fp128 @llvm.fma.ppcf128(ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c)
+</pre>
+
+<h5>Overview:</h5>
+<p>The '<tt>llvm.fma.*</tt>' intrinsics perform the fused multiply-add
+ operation.</p>
+
+<h5>Arguments:</h5>
+<p>The argument and return value are floating point numbers of the same
+ type.</p>
+
+<h5>Semantics:</h5>
+<p>This function returns the same values as the libm <tt>fma</tt> functions
+ would.</p>
+
</div>
<!-- ======================================================================= -->
Modified: llvm/branches/type-system-rewrite/include/llvm/CodeGen/ISDOpcodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/include/llvm/CodeGen/ISDOpcodes.h?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/include/llvm/CodeGen/ISDOpcodes.h (original)
+++ llvm/branches/type-system-rewrite/include/llvm/CodeGen/ISDOpcodes.h Sat Jul 9 02:04:43 2011
@@ -232,7 +232,7 @@
SMULO, UMULO,
// Simple binary floating point operators.
- FADD, FSUB, FMUL, FDIV, FREM,
+ FADD, FSUB, FMUL, FMA, FDIV, FREM,
// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This
// DAG node does not require that X and Y have the same type, just that they
Modified: llvm/branches/type-system-rewrite/include/llvm/CodeGen/MachineRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/include/llvm/CodeGen/MachineRegisterInfo.h?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/include/llvm/CodeGen/MachineRegisterInfo.h (original)
+++ llvm/branches/type-system-rewrite/include/llvm/CodeGen/MachineRegisterInfo.h Sat Jul 9 02:04:43 2011
@@ -225,6 +225,14 @@
return RegAllocHints[Reg];
}
+ /// getSimpleHint - Return the preferred register allocation hint, or 0 if a
+ /// standard simple hint (Type == 0) is not set.
+ unsigned getSimpleHint(unsigned Reg) const {
+ std::pair<unsigned, unsigned> Hint = getRegAllocationHint(Reg);
+ return Hint.first ? 0 : Hint.second;
+ }
+
+
//===--------------------------------------------------------------------===//
// Physical Register Use Info
//===--------------------------------------------------------------------===//
Modified: llvm/branches/type-system-rewrite/include/llvm/CodeGen/RuntimeLibcalls.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/include/llvm/CodeGen/RuntimeLibcalls.h?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/include/llvm/CodeGen/RuntimeLibcalls.h (original)
+++ llvm/branches/type-system-rewrite/include/llvm/CodeGen/RuntimeLibcalls.h Sat Jul 9 02:04:43 2011
@@ -103,6 +103,10 @@
REM_F64,
REM_F80,
REM_PPCF128,
+ FMA_F32,
+ FMA_F64,
+ FMA_F80,
+ FMA_PPCF128,
POWI_F32,
POWI_F64,
POWI_F80,
Modified: llvm/branches/type-system-rewrite/include/llvm/Intrinsics.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/include/llvm/Intrinsics.td?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/include/llvm/Intrinsics.td (original)
+++ llvm/branches/type-system-rewrite/include/llvm/Intrinsics.td Sat Jul 9 02:04:43 2011
@@ -255,6 +255,12 @@
def int_exp2 : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
}
+let Properties = [IntrNoMem] in {
+ def int_fma : Intrinsic<[llvm_anyfloat_ty],
+ [LLVMMatchType<0>, LLVMMatchType<0>,
+ LLVMMatchType<0>]>;
+}
+
// NOTE: these are internal interfaces.
def int_setjmp : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty]>;
def int_longjmp : Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty]>;
Modified: llvm/branches/type-system-rewrite/include/llvm/MC/MCSubtargetInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/include/llvm/MC/MCSubtargetInfo.h?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/include/llvm/MC/MCSubtargetInfo.h (original)
+++ llvm/branches/type-system-rewrite/include/llvm/MC/MCSubtargetInfo.h Sat Jul 9 02:04:43 2011
@@ -34,7 +34,8 @@
const unsigned *ForwardingPathes; // Forwarding pathes
unsigned NumFeatures; // Number of processor features
unsigned NumProcs; // Number of processors
- uint64_t FeatureBits; // Feature bits for current CPU
+
+ uint64_t FeatureBits; // Feature bits for current CPU + FS
public:
void InitMCSubtargetInfo(StringRef CPU, StringRef FS,
@@ -54,6 +55,14 @@
/// feature string), recompute and return feature bits.
uint64_t ReInitMCSubtargetInfo(StringRef CPU, StringRef FS);
+ /// ToggleFeature - Toggle a feature and returns the re-computed feature
+ /// bits. This version does not change the implied bits.
+ uint64_t ToggleFeature(uint64_t FB);
+
+ /// ToggleFeature - Toggle a feature and returns the re-computed feature
+ /// bits. This version will also change all implied bits.
+ uint64_t ToggleFeature(StringRef FS);
+
/// getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
///
InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const;
Modified: llvm/branches/type-system-rewrite/include/llvm/MC/SubtargetFeature.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/include/llvm/MC/SubtargetFeature.h?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/include/llvm/MC/SubtargetFeature.h (original)
+++ llvm/branches/type-system-rewrite/include/llvm/MC/SubtargetFeature.h Sat Jul 9 02:04:43 2011
@@ -82,6 +82,12 @@
/// Adding Features.
void AddFeature(const StringRef String, bool IsEnabled = true);
+ /// ToggleFeature - Toggle a feature and returns the newly updated feature
+ /// bits.
+ uint64_t ToggleFeature(uint64_t Bits, const StringRef String,
+ const SubtargetFeatureKV *FeatureTable,
+ size_t FeatureTableSize);
+
/// Get feature bits of a CPU.
uint64_t getFeatureBits(const StringRef CPU,
const SubtargetFeatureKV *CPUTable,
Modified: llvm/branches/type-system-rewrite/include/llvm/Target/TargetRegistry.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/include/llvm/Target/TargetRegistry.h?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/include/llvm/Target/TargetRegistry.h (original)
+++ llvm/branches/type-system-rewrite/include/llvm/Target/TargetRegistry.h Sat Jul 9 02:04:43 2011
@@ -36,6 +36,7 @@
class MCInstrInfo;
class MCRegisterInfo;
class MCStreamer;
+ class MCSubtargetInfo;
class TargetAsmBackend;
class TargetAsmLexer;
class TargetAsmParser;
@@ -69,6 +70,9 @@
StringRef TT);
typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void);
typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(void);
+ typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(StringRef TT,
+ StringRef CPU,
+ StringRef Features);
typedef TargetMachine *(*TargetMachineCtorTy)(const Target &T,
const std::string &TT,
const std::string &CPU,
@@ -79,8 +83,7 @@
const std::string &TT);
typedef TargetAsmLexer *(*AsmLexerCtorTy)(const Target &T,
const MCAsmInfo &MAI);
- typedef TargetAsmParser *(*AsmParserCtorTy)(StringRef TT,
- StringRef CPU, StringRef Features,
+ typedef TargetAsmParser *(*AsmParserCtorTy)(MCSubtargetInfo &STI,
MCAsmParser &P);
typedef MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T);
typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const Target &T,
@@ -137,6 +140,10 @@
/// if registered.
MCRegInfoCtorFnTy MCRegInfoCtorFn;
+ /// MCSubtargetInfoCtorFn - Constructor function for this target's
+ /// MCSubtargetInfo, if registered.
+ MCSubtargetInfoCtorFnTy MCSubtargetInfoCtorFn;
+
/// TargetMachineCtorFn - Construction function for this target's
/// TargetMachine, if registered.
TargetMachineCtorTy TargetMachineCtorFn;
@@ -262,6 +269,22 @@
return MCRegInfoCtorFn();
}
+ /// createMCSubtargetInfo - Create a MCSubtargetInfo implementation.
+ ///
+ /// \arg Triple - This argument is used to determine the target machine
+ /// feature set; it should always be provided. Generally this should be
+ /// either the target triple from the module, or the target triple of the
+ /// host if that does not exist.
+ /// \arg CPU - This specifies the name of the target CPU.
+ /// \arg Features - This specifies the string representation of the
+ /// additional target features.
+ MCSubtargetInfo *createMCSubtargetInfo(StringRef Triple, StringRef CPU,
+ StringRef Features) const {
+ if (!MCSubtargetInfoCtorFn)
+ return 0;
+ return MCSubtargetInfoCtorFn(Triple, CPU, Features);
+ }
+
/// createTargetMachine - Create a target specific machine implementation
/// for the specified \arg Triple.
///
@@ -299,12 +322,11 @@
///
/// \arg Parser - The target independent parser implementation to use for
/// parsing and lexing.
- TargetAsmParser *createAsmParser(StringRef Triple, StringRef CPU,
- StringRef Features,
+ TargetAsmParser *createAsmParser(MCSubtargetInfo &STI,
MCAsmParser &Parser) const {
if (!AsmParserCtorFn)
return 0;
- return AsmParserCtorFn(Triple, CPU, Features, Parser);
+ return AsmParserCtorFn(STI, Parser);
}
/// createAsmPrinter - Create a target specific assembly printer pass. This
@@ -506,6 +528,22 @@
T.MCRegInfoCtorFn = Fn;
}
+ /// RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for
+ /// the given target.
+ ///
+ /// Clients are responsible for ensuring that registration doesn't occur
+ /// while another thread is attempting to access the registry. Typically
+ /// this is done by initializing all targets at program startup.
+ ///
+ /// @param T - The target being registered.
+ /// @param Fn - A function to construct a MCSubtargetInfo for the target.
+ static void RegisterMCSubtargetInfo(Target &T,
+ Target::MCSubtargetInfoCtorFnTy Fn) {
+ // Ignore duplicate registration.
+ if (!T.MCSubtargetInfoCtorFn)
+ T.MCSubtargetInfoCtorFn = Fn;
+ }
+
/// RegisterTargetMachine - Register a TargetMachine implementation for the
/// given target.
///
@@ -782,6 +820,40 @@
}
};
+ /// RegisterMCSubtargetInfo - Helper template for registering a target
+ /// subtarget info implementation. This invokes the static "Create" method
+ /// on the class to actually do the construction. Usage:
+ ///
+ /// extern "C" void LLVMInitializeFooTarget() {
+ /// extern Target TheFooTarget;
+ /// RegisterMCSubtargetInfo<FooMCSubtargetInfo> X(TheFooTarget);
+ /// }
+ template<class MCSubtargetInfoImpl>
+ struct RegisterMCSubtargetInfo {
+ RegisterMCSubtargetInfo(Target &T) {
+ TargetRegistry::RegisterMCSubtargetInfo(T, &Allocator);
+ }
+ private:
+ static MCSubtargetInfo *Allocator(StringRef TT, StringRef CPU,
+ StringRef FS) {
+ return new MCSubtargetInfoImpl();
+ }
+ };
+
+ /// RegisterMCSubtargetInfoFn - Helper template for registering a target
+ /// subtarget info implementation. This invokes the specified function to
+ /// do the construction. Usage:
+ ///
+ /// extern "C" void LLVMInitializeFooTarget() {
+ /// extern Target TheFooTarget;
+ /// RegisterMCSubtargetInfoFn X(TheFooTarget, TheFunction);
+ /// }
+ struct RegisterMCSubtargetInfoFn {
+ RegisterMCSubtargetInfoFn(Target &T, Target::MCSubtargetInfoCtorFnTy Fn) {
+ TargetRegistry::RegisterMCSubtargetInfo(T, Fn);
+ }
+ };
+
/// RegisterTargetMachine - Helper template for registering a target machine
/// implementation, for use in the target machine initialization
/// function. Usage:
@@ -859,9 +931,8 @@
}
private:
- static TargetAsmParser *Allocator(StringRef TT, StringRef CPU,
- StringRef FS, MCAsmParser &P) {
- return new AsmParserImpl(TT, CPU, FS, P);
+ static TargetAsmParser *Allocator(MCSubtargetInfo &STI, MCAsmParser &P) {
+ return new AsmParserImpl(STI, P);
}
};
Modified: llvm/branches/type-system-rewrite/include/llvm/Target/TargetSelect.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/include/llvm/Target/TargetSelect.h?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/include/llvm/Target/TargetSelect.h (original)
+++ llvm/branches/type-system-rewrite/include/llvm/Target/TargetSelect.h Sat Jul 9 02:04:43 2011
@@ -26,6 +26,10 @@
#define LLVM_TARGET(TargetName) void LLVMInitialize##TargetName##Target();
#include "llvm/Config/Targets.def"
+#define LLVM_TARGET(TargetName) \
+ void LLVMInitialize##TargetName##MCSubtargetInfo();
+#include "llvm/Config/Targets.def"
+
// Declare all of the available assembly printer initialization functions.
#define LLVM_ASM_PRINTER(TargetName) void LLVMInitialize##TargetName##AsmPrinter();
#include "llvm/Config/AsmPrinters.def"
@@ -35,7 +39,8 @@
#include "llvm/Config/AsmParsers.def"
// Declare all of the available disassembler initialization functions.
-#define LLVM_DISASSEMBLER(TargetName) void LLVMInitialize##TargetName##Disassembler();
+#define LLVM_DISASSEMBLER(TargetName) \
+ void LLVMInitialize##TargetName##Disassembler();
#include "llvm/Config/Disassemblers.def"
}
@@ -63,6 +68,16 @@
#include "llvm/Config/Targets.def"
}
+ /// InitializeAllMCSubtargetInfos - The main program should call this function
+ /// if it wants access to all available subtarget infos for targets that LLVM
+ /// is configured to support, to make them available via the TargetRegistry.
+ ///
+ /// It is legal for a client to make multiple calls to this function.
+ inline void InitializeAllMCSubtargetInfos() {
+#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##MCSubtargetInfo();
+#include "llvm/Config/Targets.def"
+ }
+
/// InitializeAllAsmPrinters - The main program should call this function if
/// it wants all asm printers that LLVM is configured to support, to make them
/// available via the TargetRegistry.
Modified: llvm/branches/type-system-rewrite/include/llvm/Target/TargetSelectionDAG.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/include/llvm/Target/TargetSelectionDAG.td?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/include/llvm/Target/TargetSelectionDAG.td (original)
+++ llvm/branches/type-system-rewrite/include/llvm/Target/TargetSelectionDAG.td Sat Jul 9 02:04:43 2011
@@ -353,6 +353,7 @@
def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
+def fma : SDNode<"ISD::FMA" , SDTFPTernaryOp>;
def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>;
def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
Modified: llvm/branches/type-system-rewrite/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp Sat Jul 9 02:04:43 2011
@@ -21,6 +21,7 @@
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCStreamer.h"
+#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/Target/TargetAsmParser.h"
#include "llvm/Target/TargetMachine.h"
@@ -112,11 +113,15 @@
OutContext, OutStreamer,
*MAI));
- OwningPtr<TargetAsmParser>
- TAP(TM.getTarget().createAsmParser(TM.getTargetTriple(),
- TM.getTargetCPU(),
- TM.getTargetFeatureString(),
- *Parser));
+ // FIXME: It would be nice if we can avoid createing a new instance of
+ // MCSubtargetInfo here given TargetSubtargetInfo is available. However,
+ // we have to watch out for asm directives which can change subtarget
+ // state. e.g. .code 16, .code 32.
+ OwningPtr<MCSubtargetInfo>
+ STI(TM.getTarget().createMCSubtargetInfo(TM.getTargetTriple(),
+ TM.getTargetCPU(),
+ TM.getTargetFeatureString()));
+ OwningPtr<TargetAsmParser> TAP(TM.getTarget().createAsmParser(*STI, *Parser));
if (!TAP)
report_fatal_error("Inline asm not supported by this streamer because"
" we don't have an asm parser for this target\n");
Modified: llvm/branches/type-system-rewrite/lib/CodeGen/InlineSpiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/CodeGen/InlineSpiller.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/CodeGen/InlineSpiller.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/CodeGen/InlineSpiller.cpp Sat Jul 9 02:04:43 2011
@@ -303,7 +303,8 @@
// Best spill candidate seen so far. This must dominate UseVNI.
SibValueInfo SVI(UseReg, UseVNI);
MachineBasicBlock *UseMBB = LIS.getMBBFromIndex(UseVNI->def);
- unsigned SpillDepth = Loops.getLoopDepth(UseMBB);
+ MachineBasicBlock *SpillMBB = UseMBB;
+ unsigned SpillDepth = Loops.getLoopDepth(SpillMBB);
bool SeenOrigPHI = false; // Original PHI met.
do {
@@ -316,7 +317,30 @@
// Is this value a better spill candidate?
if (!isRegToSpill(Reg)) {
MachineBasicBlock *MBB = LIS.getMBBFromIndex(VNI->def);
- if (MBB != UseMBB && MDT.dominates(MBB, UseMBB)) {
+ if (MBB == SpillMBB) {
+ // This is an alternative def earlier in the same MBB.
+ // Hoist the spill as far as possible in SpillMBB. This can ease
+ // register pressure:
+ //
+ // x = def
+ // y = use x
+ // s = copy x
+ //
+ // Hoisting the spill of s to immediately after the def removes the
+ // interference between x and y:
+ //
+ // x = def
+ // spill x
+ // y = use x<kill>
+ //
+ if (VNI->def < SVI.SpillVNI->def) {
+ DEBUG(dbgs() << " hoist in BB#" << MBB->getNumber() << ": "
+ << PrintReg(Reg) << ':' << VNI->id << '@' << VNI->def
+ << '\n');
+ SVI.SpillReg = Reg;
+ SVI.SpillVNI = VNI;
+ }
+ } else if (MBB != UseMBB && MDT.dominates(MBB, UseMBB)) {
// This is a valid spill location dominating UseVNI.
// Prefer to spill at a smaller loop depth.
unsigned Depth = Loops.getLoopDepth(MBB);
@@ -325,6 +349,7 @@
<< ':' << VNI->id << '@' << VNI->def << '\n');
SVI.SpillReg = Reg;
SVI.SpillVNI = VNI;
+ SpillMBB = MBB;
SpillDepth = Depth;
}
}
Modified: llvm/branches/type-system-rewrite/lib/CodeGen/LiveIntervalUnion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/CodeGen/LiveIntervalUnion.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/CodeGen/LiveIntervalUnion.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/CodeGen/LiveIntervalUnion.cpp Sat Jul 9 02:04:43 2011
@@ -244,7 +244,7 @@
//
// For comments on how to speed it up, see Query::findIntersection().
unsigned LiveIntervalUnion::Query::
-collectInterferingVRegs(unsigned MaxInterferingRegs, float MaxWeight) {
+collectInterferingVRegs(unsigned MaxInterferingRegs) {
InterferenceResult IR = firstInterference();
LiveInterval::iterator VirtRegEnd = VirtReg->end();
LiveInterval *RecentInterferingVReg = NULL;
@@ -287,10 +287,6 @@
RecentInterferingVReg = IR.LiveUnionI.value();
++IR.LiveUnionI;
- // Stop collecting when the max weight is exceeded.
- if (RecentInterferingVReg->weight >= MaxWeight)
- return InterferingVRegs.size();
-
continue;
}
// VirtRegI may have advanced far beyond LiveUnionI,
Modified: llvm/branches/type-system-rewrite/lib/CodeGen/LiveIntervalUnion.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/CodeGen/LiveIntervalUnion.h?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/CodeGen/LiveIntervalUnion.h (original)
+++ llvm/branches/type-system-rewrite/lib/CodeGen/LiveIntervalUnion.h Sat Jul 9 02:04:43 2011
@@ -229,8 +229,7 @@
// Count the virtual registers in this union that interfere with this
// query's live virtual register, up to maxInterferingRegs.
- unsigned collectInterferingVRegs(unsigned MaxInterferingRegs = UINT_MAX,
- float MaxWeight = HUGE_VALF);
+ unsigned collectInterferingVRegs(unsigned MaxInterferingRegs = UINT_MAX);
// Was this virtual register visited during collectInterferingVRegs?
bool isSeenInterference(LiveInterval *VReg) const;
Modified: llvm/branches/type-system-rewrite/lib/CodeGen/RegAllocGreedy.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/CodeGen/RegAllocGreedy.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/CodeGen/RegAllocGreedy.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/CodeGen/RegAllocGreedy.cpp Sat Jul 9 02:04:43 2011
@@ -133,6 +133,20 @@
}
}
+ /// Cost of evicting interference.
+ struct EvictionCost {
+ unsigned BrokenHints; ///< Total number of broken hints.
+ float MaxWeight; ///< Maximum spill weight evicted.
+
+ EvictionCost(unsigned B = 0) : BrokenHints(B), MaxWeight(0) {}
+
+ bool operator<(const EvictionCost &O) const {
+ if (BrokenHints != O.BrokenHints)
+ return BrokenHints < O.BrokenHints;
+ return MaxWeight < O.MaxWeight;
+ }
+ };
+
// splitting state.
std::auto_ptr<SplitAnalysis> SA;
std::auto_ptr<SplitEditor> SE;
@@ -197,8 +211,10 @@
void splitAroundRegion(LiveInterval&, GlobalSplitCandidate&,
SmallVectorImpl<LiveInterval*>&);
void calcGapWeights(unsigned, SmallVectorImpl<float>&);
- bool canEvict(LiveInterval &A, LiveInterval &B);
- bool canEvictInterference(LiveInterval&, unsigned, float&);
+ bool shouldEvict(LiveInterval &A, bool, LiveInterval &B, bool);
+ bool canEvictInterference(LiveInterval&, unsigned, bool, EvictionCost&);
+ void evictInterference(LiveInterval&, unsigned,
+ SmallVectorImpl<LiveInterval*>&);
unsigned tryAssign(LiveInterval&, AllocationOrder&,
SmallVectorImpl<LiveInterval*>&);
@@ -382,7 +398,21 @@
if (!PhysReg || Order.isHint(PhysReg))
return PhysReg;
- // PhysReg is available. Try to evict interference from a cheaper alternative.
+ // PhysReg is available, but there may be a better choice.
+
+ // If we missed a simple hint, try to cheaply evict interference from the
+ // preferred register.
+ if (unsigned Hint = MRI->getSimpleHint(VirtReg.reg))
+ if (Order.isHint(Hint)) {
+ DEBUG(dbgs() << "missed hint " << PrintReg(Hint, TRI) << '\n');
+ EvictionCost MaxCost(1);
+ if (canEvictInterference(VirtReg, Hint, true, MaxCost)) {
+ evictInterference(VirtReg, Hint, NewVRegs);
+ return Hint;
+ }
+ }
+
+ // Try to evict interference from a cheaper alternative.
unsigned Cost = TRI->getCostPerUse(PhysReg);
// Most registers have 0 additional cost.
@@ -400,23 +430,42 @@
// Interference eviction
//===----------------------------------------------------------------------===//
-/// canEvict - determine if A can evict the assigned live range B. The eviction
-/// policy defined by this function together with the allocation order defined
-/// by enqueue() decides which registers ultimately end up being split and
-/// spilled.
+/// shouldEvict - determine if A should evict the assigned live range B. The
+/// eviction policy defined by this function together with the allocation order
+/// defined by enqueue() decides which registers ultimately end up being split
+/// and spilled.
///
/// Cascade numbers are used to prevent infinite loops if this function is a
/// cyclic relation.
-bool RAGreedy::canEvict(LiveInterval &A, LiveInterval &B) {
+///
+/// @param A The live range to be assigned.
+/// @param IsHint True when A is about to be assigned to its preferred
+/// register.
+/// @param B The live range to be evicted.
+/// @param BreaksHint True when B is already assigned to its preferred register.
+bool RAGreedy::shouldEvict(LiveInterval &A, bool IsHint,
+ LiveInterval &B, bool BreaksHint) {
+ bool CanSplit = getStage(B) <= RS_Second;
+
+ // Be fairly aggressive about following hints as long as the evictee can be
+ // split.
+ if (CanSplit && IsHint && !BreaksHint)
+ return true;
+
return A.weight > B.weight;
}
-/// canEvict - Return true if all interferences between VirtReg and PhysReg can
-/// be evicted.
-/// Return false if any interference is heavier than MaxWeight.
-/// On return, set MaxWeight to the maximal spill weight of an interference.
+/// canEvictInterference - Return true if all interferences between VirtReg and
+/// PhysReg can be evicted. When OnlyCheap is set, don't do anything
+///
+/// @param VirtReg Live range that is about to be assigned.
+/// @param PhysReg Desired register for assignment.
+/// @prarm IsHint True when PhysReg is VirtReg's preferred register.
+/// @param MaxCost Only look for cheaper candidates and update with new cost
+/// when returning true.
+/// @returns True when interference can be evicted cheaper than MaxCost.
bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg,
- float &MaxWeight) {
+ bool IsHint, EvictionCost &MaxCost) {
// Find VirtReg's cascade number. This will be unassigned if VirtReg was never
// involved in an eviction before. If a cascade number was assigned, deny
// evicting anything with the same or a newer cascade number. This prevents
@@ -428,11 +477,11 @@
if (!Cascade)
Cascade = NextCascade;
- float Weight = 0;
+ EvictionCost Cost;
for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) {
LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
// If there is 10 or more interferences, chances are one is heavier.
- if (Q.collectInterferingVRegs(10, MaxWeight) >= 10)
+ if (Q.collectInterferingVRegs(10) >= 10)
return false;
// Check if any interfering live range is heavier than MaxWeight.
@@ -440,19 +489,69 @@
LiveInterval *Intf = Q.interferingVRegs()[i - 1];
if (TargetRegisterInfo::isPhysicalRegister(Intf->reg))
return false;
- if (Cascade <= ExtraRegInfo[Intf->reg].Cascade)
+ // Never evict spill products. They cannot split or spill.
+ if (getStage(*Intf) == RS_Spill)
return false;
- if (Intf->weight >= MaxWeight)
+ // Once a live range becomes small enough, it is urgent that we find a
+ // register for it. This is indicated by an infinite spill weight. These
+ // urgent live ranges get to evict almost anything.
+ bool Urgent = !VirtReg.isSpillable() && Intf->isSpillable();
+ // Only evict older cascades or live ranges without a cascade.
+ unsigned IntfCascade = ExtraRegInfo[Intf->reg].Cascade;
+ if (Cascade <= IntfCascade) {
+ if (!Urgent)
+ return false;
+ // We permit breaking cascades for urgent evictions. It should be the
+ // last resort, though, so make it really expensive.
+ Cost.BrokenHints += 10;
+ }
+ // Would this break a satisfied hint?
+ bool BreaksHint = VRM->hasPreferredPhys(Intf->reg);
+ // Update eviction cost.
+ Cost.BrokenHints += BreaksHint;
+ Cost.MaxWeight = std::max(Cost.MaxWeight, Intf->weight);
+ // Abort if this would be too expensive.
+ if (!(Cost < MaxCost))
return false;
- if (!canEvict(VirtReg, *Intf))
+ // Finally, apply the eviction policy for non-urgent evictions.
+ if (!Urgent && !shouldEvict(VirtReg, IsHint, *Intf, BreaksHint))
return false;
- Weight = std::max(Weight, Intf->weight);
}
}
- MaxWeight = Weight;
+ MaxCost = Cost;
return true;
}
+/// evictInterference - Evict any interferring registers that prevent VirtReg
+/// from being assigned to Physreg. This assumes that canEvictInterference
+/// returned true.
+void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg,
+ SmallVectorImpl<LiveInterval*> &NewVRegs) {
+ // Make sure that VirtReg has a cascade number, and assign that cascade
+ // number to every evicted register. These live ranges than then only be
+ // evicted by a newer cascade, preventing infinite loops.
+ unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;
+ if (!Cascade)
+ Cascade = ExtraRegInfo[VirtReg.reg].Cascade = NextCascade++;
+
+ DEBUG(dbgs() << "evicting " << PrintReg(PhysReg, TRI)
+ << " interference: Cascade " << Cascade << '\n');
+ for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) {
+ LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
+ assert(Q.seenAllInterferences() && "Didn't check all interfererences.");
+ for (unsigned i = 0, e = Q.interferingVRegs().size(); i != e; ++i) {
+ LiveInterval *Intf = Q.interferingVRegs()[i];
+ unassign(*Intf, VRM->getPhys(Intf->reg));
+ assert((ExtraRegInfo[Intf->reg].Cascade < Cascade ||
+ VirtReg.isSpillable() < Intf->isSpillable()) &&
+ "Cannot decrease cascade number, illegal eviction");
+ ExtraRegInfo[Intf->reg].Cascade = Cascade;
+ ++NumEvicted;
+ NewVRegs.push_back(Intf);
+ }
+ }
+}
+
/// tryEvict - Try to evict all interferences for a physreg.
/// @param VirtReg Currently unassigned virtual register.
/// @param Order Physregs to try.
@@ -463,31 +562,37 @@
unsigned CostPerUseLimit) {
NamedRegionTimer T("Evict", TimerGroupName, TimePassesIsEnabled);
- // Keep track of the lightest single interference seen so far.
- float BestWeight = HUGE_VALF;
+ // Keep track of the cheapest interference seen so far.
+ EvictionCost BestCost(~0u);
unsigned BestPhys = 0;
+ // When we are just looking for a reduced cost per use, don't break any
+ // hints, and only evict smaller spill weights.
+ if (CostPerUseLimit < ~0u) {
+ BestCost.BrokenHints = 0;
+ BestCost.MaxWeight = VirtReg.weight;
+ }
+
Order.rewind();
while (unsigned PhysReg = Order.next()) {
if (TRI->getCostPerUse(PhysReg) >= CostPerUseLimit)
continue;
- // The first use of a register in a function has cost 1.
- if (CostPerUseLimit == 1 && !MRI->isPhysRegUsed(PhysReg))
- continue;
-
- float Weight = BestWeight;
- if (!canEvictInterference(VirtReg, PhysReg, Weight))
- continue;
+ // The first use of a callee-saved register in a function has cost 1.
+ // Don't start using a CSR when the CostPerUseLimit is low.
+ if (CostPerUseLimit == 1)
+ if (unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg))
+ if (!MRI->isPhysRegUsed(CSR)) {
+ DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " would clobber CSR "
+ << PrintReg(CSR, TRI) << '\n');
+ continue;
+ }
- // This is an eviction candidate.
- DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " interference = "
- << Weight << '\n');
- if (BestPhys && Weight >= BestWeight)
+ if (!canEvictInterference(VirtReg, PhysReg, false, BestCost))
continue;
// Best so far.
BestPhys = PhysReg;
- BestWeight = Weight;
+
// Stop if the hint can be used.
if (Order.isHint(PhysReg))
break;
@@ -496,29 +601,7 @@
if (!BestPhys)
return 0;
- // We will evict interference. Make sure that VirtReg has a cascade number,
- // and assign that cascade number to every evicted register. These live
- // ranges than then only be evicted by a newer cascade, preventing infinite
- // loops.
- unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;
- if (!Cascade)
- Cascade = ExtraRegInfo[VirtReg.reg].Cascade = NextCascade++;
-
- DEBUG(dbgs() << "evicting " << PrintReg(BestPhys, TRI)
- << " interference: Cascade " << Cascade << '\n');
- for (const unsigned *AliasI = TRI->getOverlaps(BestPhys); *AliasI; ++AliasI) {
- LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
- assert(Q.seenAllInterferences() && "Didn't check all interfererences.");
- for (unsigned i = 0, e = Q.interferingVRegs().size(); i != e; ++i) {
- LiveInterval *Intf = Q.interferingVRegs()[i];
- unassign(*Intf, VRM->getPhys(Intf->reg));
- assert(ExtraRegInfo[Intf->reg].Cascade < Cascade &&
- "Cannot decrease cascade number, illegal eviction");
- ExtraRegInfo[Intf->reg].Cascade = Cascade;
- ++NumEvicted;
- NewVRegs.push_back(Intf);
- }
- }
+ evictInterference(VirtReg, BestPhys, NewVRegs);
return BestPhys;
}
@@ -1552,7 +1635,7 @@
// If we couldn't allocate a register from spilling, there is probably some
// invalid inline assembly. The base class wil report it.
- if (Stage >= RS_Spill)
+ if (Stage >= RS_Spill || !VirtReg.isSpillable())
return ~0u;
// Try splitting VirtReg or interferences.
Modified: llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Jul 9 02:04:43 2011
@@ -3351,6 +3351,10 @@
Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
RTLIB::REM_F80, RTLIB::REM_PPCF128));
break;
+ case ISD::FMA:
+ Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
+ RTLIB::FMA_F80, RTLIB::FMA_PPCF128));
+ break;
case ISD::FP16_TO_FP32:
Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
break;
Modified: llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp Sat Jul 9 02:04:43 2011
@@ -74,6 +74,7 @@
case ISD::FLOG: R = SoftenFloatRes_FLOG(N); break;
case ISD::FLOG2: R = SoftenFloatRes_FLOG2(N); break;
case ISD::FLOG10: R = SoftenFloatRes_FLOG10(N); break;
+ case ISD::FMA: R = SoftenFloatRes_FMA(N); break;
case ISD::FMUL: R = SoftenFloatRes_FMUL(N); break;
case ISD::FNEARBYINT: R = SoftenFloatRes_FNEARBYINT(N); break;
case ISD::FNEG: R = SoftenFloatRes_FNEG(N); break;
@@ -294,6 +295,19 @@
NVT, &Op, 1, false, N->getDebugLoc());
}
+SDValue DAGTypeLegalizer::SoftenFloatRes_FMA(SDNode *N) {
+ EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
+ SDValue Ops[3] = { GetSoftenedFloat(N->getOperand(0)),
+ GetSoftenedFloat(N->getOperand(1)),
+ GetSoftenedFloat(N->getOperand(2)) };
+ return MakeLibCall(GetFPLibCall(N->getValueType(0),
+ RTLIB::FMA_F32,
+ RTLIB::FMA_F64,
+ RTLIB::FMA_F80,
+ RTLIB::FMA_PPCF128),
+ NVT, Ops, 3, false, N->getDebugLoc());
+}
+
SDValue DAGTypeLegalizer::SoftenFloatRes_FMUL(SDNode *N) {
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
@@ -837,6 +851,7 @@
case ISD::FLOG: ExpandFloatRes_FLOG(N, Lo, Hi); break;
case ISD::FLOG2: ExpandFloatRes_FLOG2(N, Lo, Hi); break;
case ISD::FLOG10: ExpandFloatRes_FLOG10(N, Lo, Hi); break;
+ case ISD::FMA: ExpandFloatRes_FMA(N, Lo, Hi); break;
case ISD::FMUL: ExpandFloatRes_FMUL(N, Lo, Hi); break;
case ISD::FNEARBYINT: ExpandFloatRes_FNEARBYINT(N, Lo, Hi); break;
case ISD::FNEG: ExpandFloatRes_FNEG(N, Lo, Hi); break;
@@ -989,6 +1004,19 @@
GetPairElements(Call, Lo, Hi);
}
+void DAGTypeLegalizer::ExpandFloatRes_FMA(SDNode *N, SDValue &Lo,
+ SDValue &Hi) {
+ SDValue Ops[3] = { N->getOperand(0), N->getOperand(1), N->getOperand(2) };
+ SDValue Call = MakeLibCall(GetFPLibCall(N->getValueType(0),
+ RTLIB::FMA_F32,
+ RTLIB::FMA_F64,
+ RTLIB::FMA_F80,
+ RTLIB::FMA_PPCF128),
+ N->getValueType(0), Ops, 3, false,
+ N->getDebugLoc());
+ GetPairElements(Call, Lo, Hi);
+}
+
void DAGTypeLegalizer::ExpandFloatRes_FMUL(SDNode *N, SDValue &Lo,
SDValue &Hi) {
SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
Modified: llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/LegalizeTypes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original)
+++ llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/LegalizeTypes.h Sat Jul 9 02:04:43 2011
@@ -378,6 +378,7 @@
SDValue SoftenFloatRes_FLOG(SDNode *N);
SDValue SoftenFloatRes_FLOG2(SDNode *N);
SDValue SoftenFloatRes_FLOG10(SDNode *N);
+ SDValue SoftenFloatRes_FMA(SDNode *N);
SDValue SoftenFloatRes_FMUL(SDNode *N);
SDValue SoftenFloatRes_FNEARBYINT(SDNode *N);
SDValue SoftenFloatRes_FNEG(SDNode *N);
@@ -442,6 +443,7 @@
void ExpandFloatRes_FLOG (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandFloatRes_FLOG2 (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandFloatRes_FLOG10 (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandFloatRes_FMA (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandFloatRes_FMUL (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandFloatRes_FNEARBYINT(SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandFloatRes_FNEG (SDNode *N, SDValue &Lo, SDValue &Hi);
Modified: llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Sat Jul 9 02:04:43 2011
@@ -5878,6 +5878,7 @@
case ISD::FSUB: return "fsub";
case ISD::FMUL: return "fmul";
case ISD::FDIV: return "fdiv";
+ case ISD::FMA: return "fma";
case ISD::FREM: return "frem";
case ISD::FCOPYSIGN: return "fcopysign";
case ISD::FGETSIGN: return "fgetsign";
Modified: llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Sat Jul 9 02:04:43 2011
@@ -4651,6 +4651,13 @@
case Intrinsic::pow:
visitPow(I);
return 0;
+ case Intrinsic::fma:
+ setValue(&I, DAG.getNode(ISD::FMA, dl,
+ getValue(I.getArgOperand(0)).getValueType(),
+ getValue(I.getArgOperand(0)),
+ getValue(I.getArgOperand(1)),
+ getValue(I.getArgOperand(2))));
+ return 0;
case Intrinsic::convert_to_fp16:
setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl,
MVT::i16, getValue(I.getArgOperand(0))));
Modified: llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/TargetLowering.cpp Sat Jul 9 02:04:43 2011
@@ -139,6 +139,10 @@
Names[RTLIB::REM_F64] = "fmod";
Names[RTLIB::REM_F80] = "fmodl";
Names[RTLIB::REM_PPCF128] = "fmodl";
+ Names[RTLIB::FMA_F32] = "fmaf";
+ Names[RTLIB::FMA_F64] = "fma";
+ Names[RTLIB::FMA_F80] = "fmal";
+ Names[RTLIB::FMA_PPCF128] = "fmal";
Names[RTLIB::POWI_F32] = "__powisf2";
Names[RTLIB::POWI_F64] = "__powidf2";
Names[RTLIB::POWI_F80] = "__powixf2";
Modified: llvm/branches/type-system-rewrite/lib/CodeGen/VirtRegMap.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/CodeGen/VirtRegMap.h?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/CodeGen/VirtRegMap.h (original)
+++ llvm/branches/type-system-rewrite/lib/CodeGen/VirtRegMap.h Sat Jul 9 02:04:43 2011
@@ -208,6 +208,11 @@
/// @brief returns the register allocation preference.
unsigned getRegAllocPref(unsigned virtReg);
+ /// @brief returns true if VirtReg is assigned to its preferred physreg.
+ bool hasPreferredPhys(unsigned VirtReg) {
+ return getPhys(VirtReg) == getRegAllocPref(VirtReg);
+ }
+
/// @brief records virtReg is a split live interval from SReg.
void setIsSplitFromReg(unsigned virtReg, unsigned SReg) {
Virt2SplitMap[virtReg] = SReg;
Modified: llvm/branches/type-system-rewrite/lib/MC/MCAsmStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/MC/MCAsmStreamer.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/MC/MCAsmStreamer.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/MC/MCAsmStreamer.cpp Sat Jul 9 02:04:43 2011
@@ -1088,7 +1088,7 @@
}
}
- // FIXME: Node the fixup comments for Thumb2 are completely bogus since the
+ // FIXME: Note the fixup comments for Thumb2 are completely bogus since the
// high order halfword of a 32-bit Thumb2 instruction is emitted first.
OS << "encoding: [";
for (unsigned i = 0, e = Code.size(); i != e; ++i) {
Modified: llvm/branches/type-system-rewrite/lib/MC/MCDisassembler/EDDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/MC/MCDisassembler/EDDisassembler.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/MC/MCDisassembler/EDDisassembler.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/MC/MCDisassembler/EDDisassembler.cpp Sat Jul 9 02:04:43 2011
@@ -23,6 +23,7 @@
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstPrinter.h"
#include "llvm/MC/MCStreamer.h"
+#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCParser/AsmLexer.h"
#include "llvm/MC/MCParser/MCAsmParser.h"
#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
@@ -373,7 +374,8 @@
*AsmInfo));
StringRef triple = tripleFromArch(Key.Arch);
- OwningPtr<TargetAsmParser> TargetParser(Tgt->createAsmParser(triple, "", "",
+ OwningPtr<MCSubtargetInfo> STI(Tgt->createMCSubtargetInfo(triple, "", ""));
+ OwningPtr<TargetAsmParser> TargetParser(Tgt->createAsmParser(*STI,
*genericParser));
AsmToken OpcodeToken = genericParser->Lex();
Modified: llvm/branches/type-system-rewrite/lib/MC/MCSubtargetInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/MC/MCSubtargetInfo.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/MC/MCSubtargetInfo.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/MC/MCSubtargetInfo.cpp Sat Jul 9 02:04:43 2011
@@ -48,6 +48,23 @@
return FeatureBits;
}
+/// ToggleFeature - Toggle a feature and returns the re-computed feature
+/// bits. This version does not change the implied bits.
+uint64_t MCSubtargetInfo::ToggleFeature(uint64_t FB) {
+ FeatureBits ^= FB;
+ return FeatureBits;
+}
+
+/// ToggleFeature - Toggle a feature and returns the re-computed feature
+/// bits. This version will also change all implied bits.
+uint64_t MCSubtargetInfo::ToggleFeature(StringRef FS) {
+ SubtargetFeatures Features;
+ FeatureBits = Features.ToggleFeature(FeatureBits, FS,
+ ProcFeatures, NumFeatures);
+ return FeatureBits;
+}
+
+
InstrItineraryData
MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
assert(ProcItins && "Instruction itineraries information not available!");
Modified: llvm/branches/type-system-rewrite/lib/MC/SubtargetFeature.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/MC/SubtargetFeature.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/MC/SubtargetFeature.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/MC/SubtargetFeature.cpp Sat Jul 9 02:04:43 2011
@@ -224,6 +224,38 @@
}
}
+/// ToggleFeature - Toggle a feature and returns the newly updated feature
+/// bits.
+uint64_t
+SubtargetFeatures::ToggleFeature(uint64_t Bits, const StringRef Feature,
+ const SubtargetFeatureKV *FeatureTable,
+ size_t FeatureTableSize) {
+ // Find feature in table.
+ const SubtargetFeatureKV *FeatureEntry =
+ Find(StripFlag(Feature), FeatureTable, FeatureTableSize);
+ // If there is a match
+ if (FeatureEntry) {
+ if ((Bits & FeatureEntry->Value) == FeatureEntry->Value) {
+ Bits &= ~FeatureEntry->Value;
+
+ // For each feature that implies this, clear it.
+ ClearImpliedBits(Bits, FeatureEntry, FeatureTable, FeatureTableSize);
+ } else {
+ Bits |= FeatureEntry->Value;
+
+ // For each feature that this implies, set it.
+ SetImpliedBits(Bits, FeatureEntry, FeatureTable, FeatureTableSize);
+ }
+ } else {
+ errs() << "'" << Feature
+ << "' is not a recognized feature for this target"
+ << " (ignoring feature)\n";
+ }
+
+ return Bits;
+}
+
+
/// getFeatureBits - Get feature bits a CPU.
///
uint64_t SubtargetFeatures::getFeatureBits(const StringRef CPU,
Modified: llvm/branches/type-system-rewrite/lib/Support/Host.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Support/Host.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Support/Host.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Support/Host.cpp Sat Jul 9 02:04:43 2011
@@ -214,7 +214,12 @@
// As found in a Summer 2010 model iMac.
case 37: // Intel Core i7, laptop version.
return "corei7";
- case 42: // SandyBridge
+
+ // SandyBridge:
+ case 42: // Intel Core i7 processor. All processors are manufactured
+ // using the 32 nm process.
+ case 44: // Intel Core i7 processor and Intel Xeon processor. All
+ // processors are manufactured using the 32 nm process.
case 45:
return "corei7-avx";
Modified: llvm/branches/type-system-rewrite/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/ARM/ARMAsmPrinter.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/ARM/ARMAsmPrinter.cpp Sat Jul 9 02:04:43 2011
@@ -1799,32 +1799,6 @@
}
return;
}
- // Tail jump branches are really just branch instructions with additional
- // code-gen attributes. Convert them to the canonical form here.
- case ARM::tTAILJMPd:
- case ARM::tTAILJMPdND: {
- MCInst TmpInst, TmpInst2;
- LowerARMMachineInstrToMCInst(MI, TmpInst2, *this);
- // The Darwin toolchain doesn't support tail call relocations of 16-bit
- // branches.
- TmpInst.setOpcode(Opc == ARM::tTAILJMPd ? ARM::t2B : ARM::tB);
- TmpInst.addOperand(TmpInst2.getOperand(0));
- OutStreamer.AddComment("TAILCALL");
- OutStreamer.EmitInstruction(TmpInst);
- return;
- }
- case ARM::tTAILJMPrND:
- case ARM::tTAILJMPr: {
- MCInst TmpInst;
- TmpInst.setOpcode(ARM::tBX);
- TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
- // Predicate.
- TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
- TmpInst.addOperand(MCOperand::CreateReg(0));
- OutStreamer.AddComment("TAILCALL");
- OutStreamer.EmitInstruction(TmpInst);
- return;
- }
}
MCInst TmpInst;
Modified: llvm/branches/type-system-rewrite/lib/Target/ARM/ARMConstantIslandPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/ARM/ARMConstantIslandPass.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/ARM/ARMConstantIslandPass.cpp Sat Jul 9 02:04:43 2011
@@ -1538,7 +1538,10 @@
if (MI->getOpcode() == ARM::tPOP_RET &&
MI->getOperand(2).getReg() == ARM::PC &&
MI->getNumExplicitOperands() == 3) {
- BuildMI(MI->getParent(), MI->getDebugLoc(), TII->get(ARM::tBX_RET));
+ // Create the new insn and copy the predicate from the old.
+ BuildMI(MI->getParent(), MI->getDebugLoc(), TII->get(ARM::tBX_RET))
+ .addOperand(MI->getOperand(0))
+ .addOperand(MI->getOperand(1));
MI->eraseFromParent();
MadeChange = true;
}
Modified: llvm/branches/type-system-rewrite/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/ARM/ARMISelLowering.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/ARM/ARMISelLowering.cpp Sat Jul 9 02:04:43 2011
@@ -708,6 +708,9 @@
setOperationAction(ISD::FPOW, MVT::f64, Expand);
setOperationAction(ISD::FPOW, MVT::f32, Expand);
+ setOperationAction(ISD::FMA, MVT::f64, Expand);
+ setOperationAction(ISD::FMA, MVT::f32, Expand);
+
// Various VFP goodness
if (!UseSoftFloat && !Subtarget->isThumb1Only()) {
// int <-> fp are custom expanded into bit_convert + ARMISD ops.
@@ -1637,7 +1640,11 @@
return false;
// FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
- // emitEpilogue is not ready for them.
+ // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
+ // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
+ // support in the assembler and linker to be used. This would need to be
+ // fixed to fully support tail calls in Thumb1.
+ //
// Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
// LR. This means if we need to reload LR, it takes an extra instructions,
// which outweighs the value of the tail call; but here we don't know yet
Modified: llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrInfo.td?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrInfo.td Sat Jul 9 02:04:43 2011
@@ -1527,7 +1527,6 @@
// Tail calls.
-// FIXME: The Thumb versions of these should live in ARMInstrThumb.td
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
// Darwin versions.
let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
@@ -1543,18 +1542,11 @@
(Bcc br_target:$dst, (ops 14, zero_reg))>,
Requires<[IsARM, IsDarwin]>;
- def tTAILJMPd: tPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
- Size4Bytes, IIC_Br,
- []>, Requires<[IsThumb, IsDarwin]>;
-
def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
Size4Bytes, IIC_Br, [],
(BX GPR:$dst)>,
Requires<[IsARM, IsDarwin]>;
- def tTAILJMPr : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
- Size4Bytes, IIC_Br,
- []>, Requires<[IsThumb, IsDarwin]>;
}
// Non-Darwin versions (the difference is R9).
@@ -1571,17 +1563,10 @@
(Bcc br_target:$dst, (ops 14, zero_reg))>,
Requires<[IsARM, IsNotDarwin]>;
- def tTAILJMPdND : tPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
- Size4Bytes, IIC_Br,
- []>, Requires<[IsThumb, IsNotDarwin]>;
-
def TAILJMPrND : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
Size4Bytes, IIC_Br, [],
(BX GPR:$dst)>,
Requires<[IsARM, IsNotDarwin]>;
- def tTAILJMPrND : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
- Size4Bytes, IIC_Br,
- []>, Requires<[IsThumb, IsNotDarwin]>;
}
}
Modified: llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrThumb.td?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrThumb.td Sat Jul 9 02:04:43 2011
@@ -361,27 +361,6 @@
// Control Flow Instructions.
//
-let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
- def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr",
- [(ARMretflag)]>,
- T1Special<{1,1,0,?}> {
- // A6.2.3 & A8.6.25
- let Inst{6-3} = 0b1110; // Rm = lr
- let Inst{2-0} = 0b000;
- }
-
- // Alternative return instruction used by vararg functions.
- def tBX_RET_vararg : TI<(outs), (ins tGPR:$Rm),
- IIC_Br, "bx\t$Rm",
- []>,
- T1Special<{1,1,0,?}> {
- // A6.2.3 & A8.6.25
- bits<4> Rm;
- let Inst{6-3} = Rm;
- let Inst{2-0} = 0b000;
- }
-}
-
// Indirect branches
let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
@@ -391,18 +370,16 @@
let Inst{6-3} = Rm;
let Inst{2-0} = 0b000;
}
+}
- def tBRIND : TI<(outs), (ins GPR:$Rm),
- IIC_Br,
- "mov\tpc, $Rm",
- [(brind GPR:$Rm)]>,
- T1Special<{1,0,?,?}> {
- // A8.6.97
- bits<4> Rm;
- let Inst{7} = 1; // <Rd> = Inst{7:2-0} = pc
- let Inst{6-3} = Rm;
- let Inst{2-0} = 0b111;
- }
+let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
+ def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), Size2Bytes, IIC_Br,
+ [(ARMretflag)], (tBX LR, pred:$p)>;
+
+ // Alternative return instruction used by vararg functions.
+ def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),
+ Size2Bytes, IIC_Br, [],
+ (tBX GPR:$Rm, pred:$p)>;
}
// All calls clobber the non-callee saved registers. SP is marked as a use to
@@ -571,6 +548,33 @@
}
}
+// Tail calls
+let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
+ // Darwin versions.
+ let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
+ Uses = [SP] in {
+ // tTAILJMPd: Darwin version uses a Thumb2 branch (no Thumb1 tail calls
+ // on Darwin), so it's in ARMInstrThumb2.td.
+ def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
+ Size4Bytes, IIC_Br, [],
+ (tBX GPR:$dst, (ops 14, zero_reg))>,
+ Requires<[IsThumb, IsDarwin]>;
+ }
+ // Non-Darwin versions (the difference is R9).
+ let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
+ Uses = [SP] in {
+ def tTAILJMPdND : tPseudoExpand<(outs), (ins t_brtarget:$dst, variable_ops),
+ Size4Bytes, IIC_Br, [],
+ (tB t_brtarget:$dst)>,
+ Requires<[IsThumb, IsNotDarwin]>;
+ def tTAILJMPrND : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
+ Size4Bytes, IIC_Br, [],
+ (tBX GPR:$dst, (ops 14, zero_reg))>,
+ Requires<[IsThumb, IsNotDarwin]>;
+ }
+}
+
+
// A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
// A8.6.16 B: Encoding T1
// If Inst{11-8} == 0b1111 then SEE SVC
@@ -1480,3 +1484,9 @@
Size2Bytes, IIC_iPop_Br, [],
(tPOP pred:$p, reglist:$regs)>;
+// Indirect branch using "mov pc, $Rm"
+let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
+ def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p),
+ Size2Bytes, IIC_Br, [(brind GPR:$Rm)],
+ (tMOVr PC, GPR:$Rm, pred:$p)>;
+}
Modified: llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrThumb2.td?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrThumb2.td Sat Jul 9 02:04:43 2011
@@ -3062,6 +3062,17 @@
let Inst{10-0} = target{11-1};
}
+// Tail calls. The Darwin version of thumb tail calls uses a t2 branch, so
+// it goes here.
+let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
+ // Darwin version.
+ let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
+ Uses = [SP] in
+ def tTAILJMPd: tPseudoExpand<(outs), (ins uncondbrtarget:$dst, variable_ops),
+ Size4Bytes, IIC_Br, [],
+ (t2B uncondbrtarget:$dst)>,
+ Requires<[IsThumb2, IsDarwin]>;
+}
// IT block
let Defs = [ITSTATE] in
Modified: llvm/branches/type-system-rewrite/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Sat Jul 9 02:04:43 2011
@@ -25,6 +25,7 @@
#include "llvm/Target/TargetAsmParser.h"
#include "llvm/Support/SourceMgr.h"
#include "llvm/Support/raw_ostream.h"
+#include "llvm/ADT/OwningPtr.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/StringSwitch.h"
@@ -40,8 +41,8 @@
class ARMOperand;
class ARMAsmParser : public TargetAsmParser {
+ MCSubtargetInfo &STI;
MCAsmParser &Parser;
- const MCSubtargetInfo *STI;
MCAsmParser &getParser() const { return Parser; }
MCAsmLexer &getLexer() const { return Parser.getLexer(); }
@@ -86,11 +87,14 @@
bool isThumb() const {
// FIXME: Can tablegen auto-generate this?
- return (STI->getFeatureBits() & ARM::ModeThumb) != 0;
+ return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
}
-
bool isThumbOne() const {
- return isThumb() && (STI->getFeatureBits() & ARM::FeatureThumb2) == 0;
+ return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
+ }
+ void SwitchMode() {
+ unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
+ setAvailableFeatures(FB);
}
/// @name Auto-generated Match Functions
@@ -127,13 +131,12 @@
const SmallVectorImpl<MCParsedAsmOperand*> &);
public:
- ARMAsmParser(StringRef TT, StringRef CPU, StringRef FS, MCAsmParser &_Parser)
- : TargetAsmParser(), Parser(_Parser) {
- STI = ARM_MC::createARMMCSubtargetInfo(TT, CPU, FS);
-
+ ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
+ : TargetAsmParser(), STI(_STI), Parser(_Parser) {
MCAsmParserExtension::Initialize(_Parser);
+
// Initialize the set of available features.
- setAvailableFeatures(ComputeAvailableFeatures(STI->getFeatureBits()));
+ setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
}
virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
@@ -2028,7 +2031,7 @@
// that updates the condition codes if it ends in 's'. So see if the
// mnemonic ends in 's' and if so try removing the 's' and adding a CCOut
// operand with a value of CPSR.
- else if(MatchResult == Match_MnemonicFail) {
+ else if (MatchResult == Match_MnemonicFail) {
// Get the instruction mnemonic, which is the first token.
StringRef Mnemonic = ((ARMOperand*)Operands[0])->getToken();
if (Mnemonic.substr(Mnemonic.size()-1) == "s") {
@@ -2214,20 +2217,15 @@
return Error(Parser.getTok().getLoc(), "unexpected token in directive");
Parser.Lex();
- // FIXME: We need to be able switch subtargets at this point so that
- // MatchInstructionImpl() will work when it gets the AvailableFeatures which
- // includes Feature_IsThumb or not to match the right instructions. This is
- // blocked on the FIXME in llvm-mc.cpp when creating the TargetMachine.
- if (Val == 16){
- assert(isThumb() &&
- "switching between arm/thumb not yet suppported via .code 16)");
+ if (Val == 16) {
+ if (!isThumb())
+ SwitchMode();
getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
- }
- else{
- assert(!isThumb() &&
- "switching between thumb/arm not yet suppported via .code 32)");
+ } else {
+ if (isThumb())
+ SwitchMode();
getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
- }
+ }
return false;
}
Modified: llvm/branches/type-system-rewrite/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Sat Jul 9 02:04:43 2011
@@ -112,17 +112,18 @@
// Force static initialization.
extern "C" void LLVMInitializeARMMCInstrInfo() {
- RegisterMCInstrInfo<MCInstrInfo> X(TheARMTarget);
- RegisterMCInstrInfo<MCInstrInfo> Y(TheThumbTarget);
-
TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo);
TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo);
}
extern "C" void LLVMInitializeARMMCRegInfo() {
- RegisterMCRegInfo<MCRegisterInfo> X(TheARMTarget);
- RegisterMCRegInfo<MCRegisterInfo> Y(TheThumbTarget);
-
TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo);
TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo);
}
+
+extern "C" void LLVMInitializeARMMCSubtargetInfo() {
+ TargetRegistry::RegisterMCSubtargetInfo(TheARMTarget,
+ ARM_MC::createARMMCSubtargetInfo);
+ TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget,
+ ARM_MC::createARMMCSubtargetInfo);
+}
Modified: llvm/branches/type-system-rewrite/lib/Target/ARM/Thumb1FrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/ARM/Thumb1FrameLowering.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/ARM/Thumb1FrameLowering.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/ARM/Thumb1FrameLowering.cpp Sat Jul 9 02:04:43 2011
@@ -273,8 +273,8 @@
emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, VARegSaveSize);
- BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg))
- .addReg(ARM::R3, RegState::Kill);
+ AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg))
+ .addReg(ARM::R3, RegState::Kill));
// erase the old tBX_RET instruction
MBB.erase(MBBI);
}
Modified: llvm/branches/type-system-rewrite/lib/Target/Alpha/AlphaISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/Alpha/AlphaISelLowering.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/Alpha/AlphaISelLowering.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/Alpha/AlphaISelLowering.cpp Sat Jul 9 02:04:43 2011
@@ -122,6 +122,9 @@
setOperationAction(ISD::FPOW , MVT::f32, Expand);
setOperationAction(ISD::FPOW , MVT::f64, Expand);
+ setOperationAction(ISD::FMA, MVT::f64, Expand);
+ setOperationAction(ISD::FMA, MVT::f32, Expand);
+
setOperationAction(ISD::SETCC, MVT::f32, Promote);
setOperationAction(ISD::BITCAST, MVT::f32, Promote);
Modified: llvm/branches/type-system-rewrite/lib/Target/Alpha/AlphaSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/Alpha/AlphaSubtarget.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/Alpha/AlphaSubtarget.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/Alpha/AlphaSubtarget.cpp Sat Jul 9 02:04:43 2011
@@ -13,6 +13,7 @@
#include "AlphaSubtarget.h"
#include "Alpha.h"
+#include "llvm/Target/TargetRegistry.h"
#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
@@ -35,3 +36,15 @@
// Initialize scheduling itinerary for the specified CPU.
InstrItins = getInstrItineraryForCPU(CPUName);
}
+
+MCSubtargetInfo *createAlphaMCSubtargetInfo(StringRef TT, StringRef CPU,
+ StringRef FS) {
+ MCSubtargetInfo *X = new MCSubtargetInfo();
+ InitAlphaMCSubtargetInfo(X, CPU, FS);
+ return X;
+}
+
+extern "C" void LLVMInitializeAlphaMCSubtargetInfo() {
+ TargetRegistry::RegisterMCSubtargetInfo(TheAlphaTarget,
+ createAlphaMCSubtargetInfo);
+}
Modified: llvm/branches/type-system-rewrite/lib/Target/Blackfin/BlackfinSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/Blackfin/BlackfinSubtarget.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/Blackfin/BlackfinSubtarget.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/Blackfin/BlackfinSubtarget.cpp Sat Jul 9 02:04:43 2011
@@ -12,6 +12,8 @@
//===----------------------------------------------------------------------===//
#include "BlackfinSubtarget.h"
+#include "Blackfin.h"
+#include "llvm/Target/TargetRegistry.h"
#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
@@ -42,3 +44,15 @@
// Parse features string.
ParseSubtargetFeatures(CPUName, FS);
}
+
+MCSubtargetInfo *createBlackfinMCSubtargetInfo(StringRef TT, StringRef CPU,
+ StringRef FS) {
+ MCSubtargetInfo *X = new MCSubtargetInfo();
+ InitBlackfinMCSubtargetInfo(X, CPU, FS);
+ return X;
+}
+
+extern "C" void LLVMInitializeBlackfinMCSubtargetInfo() {
+ TargetRegistry::RegisterMCSubtargetInfo(TheBlackfinTarget,
+ createBlackfinMCSubtargetInfo);
+}
Modified: llvm/branches/type-system-rewrite/lib/Target/CBackend/CBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/CBackend/CBackend.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/CBackend/CBackend.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/CBackend/CBackend.cpp Sat Jul 9 02:04:43 2011
@@ -36,6 +36,7 @@
#include "llvm/Transforms/Scalar.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetRegistry.h"
@@ -60,6 +61,10 @@
RegisterTargetMachine<CTargetMachine> X(TheCBackendTarget);
}
+extern "C" void LLVMInitializeCBackendMCSubtargetInfo() {
+ RegisterMCSubtargetInfo<MCSubtargetInfo> X(TheCBackendTarget);
+}
+
namespace {
class CBEMCAsmInfo : public MCAsmInfo {
public:
Modified: llvm/branches/type-system-rewrite/lib/Target/CellSPU/SPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/CellSPU/SPUISelLowering.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/CellSPU/SPUISelLowering.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/CellSPU/SPUISelLowering.cpp Sat Jul 9 02:04:43 2011
@@ -221,6 +221,9 @@
setOperationAction(ISD::FSQRT, MVT::f64, Expand);
setOperationAction(ISD::FSQRT, MVT::f32, Expand);
+ setOperationAction(ISD::FMA, MVT::f64, Expand);
+ setOperationAction(ISD::FMA, MVT::f32, Expand);
+
setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
Modified: llvm/branches/type-system-rewrite/lib/Target/CellSPU/SPUSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/CellSPU/SPUSubtarget.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/CellSPU/SPUSubtarget.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/CellSPU/SPUSubtarget.cpp Sat Jul 9 02:04:43 2011
@@ -14,6 +14,7 @@
#include "SPUSubtarget.h"
#include "SPU.h"
#include "SPURegisterInfo.h"
+#include "llvm/Target/TargetRegistry.h"
#include "llvm/ADT/SmallVector.h"
#define GET_SUBTARGETINFO_ENUM
@@ -65,3 +66,15 @@
CriticalPathRCs.push_back(&SPU::VECREGRegClass);
return OptLevel >= CodeGenOpt::Default;
}
+
+MCSubtargetInfo *createSPUMCSubtargetInfo(StringRef TT, StringRef CPU,
+ StringRef FS) {
+ MCSubtargetInfo *X = new MCSubtargetInfo();
+ InitSPUMCSubtargetInfo(X, CPU, FS);
+ return X;
+}
+
+extern "C" void LLVMInitializeCellSPUMCSubtargetInfo() {
+ TargetRegistry::RegisterMCSubtargetInfo(TheCellSPUTarget,
+ createSPUMCSubtargetInfo);
+}
Modified: llvm/branches/type-system-rewrite/lib/Target/CppBackend/CPPBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/CppBackend/CPPBackend.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/CppBackend/CPPBackend.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/CppBackend/CPPBackend.cpp Sat Jul 9 02:04:43 2011
@@ -22,6 +22,7 @@
#include "llvm/Module.h"
#include "llvm/Pass.h"
#include "llvm/PassManager.h"
+#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
@@ -74,6 +75,10 @@
RegisterTargetMachine<CPPTargetMachine> X(TheCppBackendTarget);
}
+extern "C" void LLVMInitializeCppBackendMCSubtargetInfo() {
+ RegisterMCSubtargetInfo<MCSubtargetInfo> X(TheCppBackendTarget);
+}
+
namespace {
typedef std::vector<const Type*> TypeList;
typedef std::map<const Type*,std::string> TypeMap;
Modified: llvm/branches/type-system-rewrite/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp Sat Jul 9 02:04:43 2011
@@ -63,8 +63,7 @@
public:
- MBlazeAsmParser(StringRef TT, StringRef CPU, StringRef FS,
- MCAsmParser &_Parser)
+ MBlazeAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
: TargetAsmParser(), Parser(_Parser) {}
virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
Modified: llvm/branches/type-system-rewrite/lib/Target/MBlaze/MBlazeISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/MBlaze/MBlazeISelLowering.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/MBlaze/MBlazeISelLowering.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/MBlaze/MBlazeISelLowering.cpp Sat Jul 9 02:04:43 2011
@@ -69,6 +69,7 @@
// Floating point operations which are not supported
setOperationAction(ISD::FREM, MVT::f32, Expand);
+ setOperationAction(ISD::FMA, MVT::f32, Expand);
setOperationAction(ISD::UINT_TO_FP, MVT::i8, Expand);
setOperationAction(ISD::UINT_TO_FP, MVT::i16, Expand);
setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
Modified: llvm/branches/type-system-rewrite/lib/Target/MBlaze/MBlazeSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/MBlaze/MBlazeSubtarget.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/MBlaze/MBlazeSubtarget.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/MBlaze/MBlazeSubtarget.cpp Sat Jul 9 02:04:43 2011
@@ -15,6 +15,7 @@
#include "MBlaze.h"
#include "MBlazeRegisterInfo.h"
#include "llvm/Support/CommandLine.h"
+#include "llvm/Target/TargetRegistry.h"
#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
@@ -62,3 +63,15 @@
CriticalPathRCs.push_back(&MBlaze::GPRRegClass);
return HasItin && OptLevel >= CodeGenOpt::Default;
}
+
+MCSubtargetInfo *createMBlazeMCSubtargetInfo(StringRef TT, StringRef CPU,
+ StringRef FS) {
+ MCSubtargetInfo *X = new MCSubtargetInfo();
+ InitMBlazeMCSubtargetInfo(X, CPU, FS);
+ return X;
+}
+
+extern "C" void LLVMInitializeMBlazeMCSubtargetInfo() {
+ TargetRegistry::RegisterMCSubtargetInfo(TheMBlazeTarget,
+ createMBlazeMCSubtargetInfo);
+}
Modified: llvm/branches/type-system-rewrite/lib/Target/MSP430/MSP430Subtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/MSP430/MSP430Subtarget.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/MSP430/MSP430Subtarget.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/MSP430/MSP430Subtarget.cpp Sat Jul 9 02:04:43 2011
@@ -13,6 +13,7 @@
#include "MSP430Subtarget.h"
#include "MSP430.h"
+#include "llvm/Target/TargetRegistry.h"
#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
@@ -31,3 +32,15 @@
// Parse features string.
ParseSubtargetFeatures(CPUName, FS);
}
+
+MCSubtargetInfo *createMSP430MCSubtargetInfo(StringRef TT, StringRef CPU,
+ StringRef FS) {
+ MCSubtargetInfo *X = new MCSubtargetInfo();
+ InitMSP430MCSubtargetInfo(X, CPU, FS);
+ return X;
+}
+
+extern "C" void LLVMInitializeMSP430MCSubtargetInfo() {
+ TargetRegistry::RegisterMCSubtargetInfo(TheMSP430Target,
+ createMSP430MCSubtargetInfo);
+}
Modified: llvm/branches/type-system-rewrite/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp Sat Jul 9 02:04:43 2011
@@ -15,6 +15,7 @@
#include "MipsInstPrinter.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
+#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/ADT/StringExtras.h"
using namespace llvm;
@@ -57,6 +58,7 @@
case FCOND_NGT:
case FCOND_GT: return "ngt";
}
+ llvm_unreachable("Impossible condition code!");
}
StringRef MipsInstPrinter::getOpcodeName(unsigned Opcode) const {
Modified: llvm/branches/type-system-rewrite/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/Mips/MipsISelLowering.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/Mips/MipsISelLowering.cpp Sat Jul 9 02:04:43 2011
@@ -146,6 +146,8 @@
setOperationAction(ISD::FLOG2, MVT::f32, Expand);
setOperationAction(ISD::FLOG10, MVT::f32, Expand);
setOperationAction(ISD::FEXP, MVT::f32, Expand);
+ setOperationAction(ISD::FMA, MVT::f32, Expand);
+ setOperationAction(ISD::FMA, MVT::f64, Expand);
setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
Modified: llvm/branches/type-system-rewrite/lib/Target/Mips/MipsSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/Mips/MipsSubtarget.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/Mips/MipsSubtarget.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/Mips/MipsSubtarget.cpp Sat Jul 9 02:04:43 2011
@@ -13,6 +13,7 @@
#include "MipsSubtarget.h"
#include "Mips.h"
+#include "llvm/Target/TargetRegistry.h"
#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
@@ -61,3 +62,15 @@
HasCondMov = true;
}
}
+
+MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU,
+ StringRef FS) {
+ MCSubtargetInfo *X = new MCSubtargetInfo();
+ InitMipsMCSubtargetInfo(X, CPU, FS);
+ return X;
+}
+
+extern "C" void LLVMInitializeMipsMCSubtargetInfo() {
+ TargetRegistry::RegisterMCSubtargetInfo(TheMipsTarget,
+ createMipsMCSubtargetInfo);
+}
Modified: llvm/branches/type-system-rewrite/lib/Target/PTX/PTXSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/PTX/PTXSubtarget.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/PTX/PTXSubtarget.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/PTX/PTXSubtarget.cpp Sat Jul 9 02:04:43 2011
@@ -12,7 +12,9 @@
//===----------------------------------------------------------------------===//
#include "PTXSubtarget.h"
+#include "PTX.h"
#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Target/TargetRegistry.h"
#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
@@ -64,3 +66,18 @@
case PTX_VERSION_2_3: return "2.3";
}
}
+
+
+MCSubtargetInfo *createPTXMCSubtargetInfo(StringRef TT, StringRef CPU,
+ StringRef FS) {
+ MCSubtargetInfo *X = new MCSubtargetInfo();
+ InitPTXMCSubtargetInfo(X, CPU, FS);
+ return X;
+}
+
+extern "C" void LLVMInitializePTXMCSubtargetInfo() {
+ TargetRegistry::RegisterMCSubtargetInfo(ThePTX32Target,
+ createPTXMCSubtargetInfo);
+ TargetRegistry::RegisterMCSubtargetInfo(ThePTX64Target,
+ createPTXMCSubtargetInfo);
+}
Modified: llvm/branches/type-system-rewrite/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/PowerPC/PPCISelLowering.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/PowerPC/PPCISelLowering.cpp Sat Jul 9 02:04:43 2011
@@ -125,10 +125,12 @@
setOperationAction(ISD::FCOS , MVT::f64, Expand);
setOperationAction(ISD::FREM , MVT::f64, Expand);
setOperationAction(ISD::FPOW , MVT::f64, Expand);
+ setOperationAction(ISD::FMA , MVT::f64, Expand);
setOperationAction(ISD::FSIN , MVT::f32, Expand);
setOperationAction(ISD::FCOS , MVT::f32, Expand);
setOperationAction(ISD::FREM , MVT::f32, Expand);
setOperationAction(ISD::FPOW , MVT::f32, Expand);
+ setOperationAction(ISD::FMA , MVT::f32, Expand);
setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
Modified: llvm/branches/type-system-rewrite/lib/Target/PowerPC/PPCSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/PowerPC/PPCSubtarget.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/PowerPC/PPCSubtarget.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/PowerPC/PPCSubtarget.cpp Sat Jul 9 02:04:43 2011
@@ -15,6 +15,7 @@
#include "PPC.h"
#include "llvm/GlobalValue.h"
#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetRegistry.h"
#include <cstdlib>
#define GET_SUBTARGETINFO_ENUM
@@ -140,3 +141,17 @@
return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
GV->hasCommonLinkage() || isDecl;
}
+
+MCSubtargetInfo *createPPCMCSubtargetInfo(StringRef TT, StringRef CPU,
+ StringRef FS) {
+ MCSubtargetInfo *X = new MCSubtargetInfo();
+ InitPPCMCSubtargetInfo(X, CPU, FS);
+ return X;
+}
+
+extern "C" void LLVMInitializePowerPCMCSubtargetInfo() {
+ TargetRegistry::RegisterMCSubtargetInfo(ThePPC32Target,
+ createPPCMCSubtargetInfo);
+ TargetRegistry::RegisterMCSubtargetInfo(ThePPC64Target,
+ createPPCMCSubtargetInfo);
+}
Modified: llvm/branches/type-system-rewrite/lib/Target/Sparc/SparcISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/Sparc/SparcISelLowering.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/Sparc/SparcISelLowering.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/Sparc/SparcISelLowering.cpp Sat Jul 9 02:04:43 2011
@@ -754,9 +754,11 @@
setOperationAction(ISD::FSIN , MVT::f64, Expand);
setOperationAction(ISD::FCOS , MVT::f64, Expand);
setOperationAction(ISD::FREM , MVT::f64, Expand);
+ setOperationAction(ISD::FMA , MVT::f64, Expand);
setOperationAction(ISD::FSIN , MVT::f32, Expand);
setOperationAction(ISD::FCOS , MVT::f32, Expand);
setOperationAction(ISD::FREM , MVT::f32, Expand);
+ setOperationAction(ISD::FMA , MVT::f32, Expand);
setOperationAction(ISD::CTPOP, MVT::i32, Expand);
setOperationAction(ISD::CTTZ , MVT::i32, Expand);
setOperationAction(ISD::CTLZ , MVT::i32, Expand);
Modified: llvm/branches/type-system-rewrite/lib/Target/Sparc/SparcSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/Sparc/SparcSubtarget.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/Sparc/SparcSubtarget.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/Sparc/SparcSubtarget.cpp Sat Jul 9 02:04:43 2011
@@ -12,6 +12,8 @@
//===----------------------------------------------------------------------===//
#include "SparcSubtarget.h"
+#include "Sparc.h"
+#include "llvm/Target/TargetRegistry.h"
#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
@@ -42,3 +44,15 @@
// Parse features string.
ParseSubtargetFeatures(CPUName, FS);
}
+
+MCSubtargetInfo *createSparcMCSubtargetInfo(StringRef TT, StringRef CPU,
+ StringRef FS) {
+ MCSubtargetInfo *X = new MCSubtargetInfo();
+ InitSparcMCSubtargetInfo(X, CPU, FS);
+ return X;
+}
+
+extern "C" void LLVMInitializeSparcMCSubtargetInfo() {
+ TargetRegistry::RegisterMCSubtargetInfo(TheSparcTarget,
+ createSparcMCSubtargetInfo);
+}
Modified: llvm/branches/type-system-rewrite/lib/Target/SystemZ/SystemZISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/SystemZ/SystemZISelLowering.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/SystemZ/SystemZISelLowering.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/SystemZ/SystemZISelLowering.cpp Sat Jul 9 02:04:43 2011
@@ -142,6 +142,8 @@
setOperationAction(ISD::FCOS, MVT::f64, Expand);
setOperationAction(ISD::FREM, MVT::f32, Expand);
setOperationAction(ISD::FREM, MVT::f64, Expand);
+ setOperationAction(ISD::FMA, MVT::f32, Expand);
+ setOperationAction(ISD::FMA, MVT::f64, Expand);
// We have only 64-bit bitconverts
setOperationAction(ISD::BITCAST, MVT::f32, Expand);
Modified: llvm/branches/type-system-rewrite/lib/Target/SystemZ/SystemZSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/SystemZ/SystemZSubtarget.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/SystemZ/SystemZSubtarget.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/SystemZ/SystemZSubtarget.cpp Sat Jul 9 02:04:43 2011
@@ -15,6 +15,7 @@
#include "SystemZ.h"
#include "llvm/GlobalValue.h"
#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetRegistry.h"
#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
@@ -53,3 +54,15 @@
return false;
}
+
+MCSubtargetInfo *createSystemZMCSubtargetInfo(StringRef TT, StringRef CPU,
+ StringRef FS) {
+ MCSubtargetInfo *X = new MCSubtargetInfo();
+ InitSystemZMCSubtargetInfo(X, CPU, FS);
+ return X;
+}
+
+extern "C" void LLVMInitializeSystemZMCSubtargetInfo() {
+ TargetRegistry::RegisterMCSubtargetInfo(TheSystemZTarget,
+ createSystemZMCSubtargetInfo);
+}
Modified: llvm/branches/type-system-rewrite/lib/Target/X86/AsmParser/X86AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/X86/AsmParser/X86AsmParser.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/X86/AsmParser/X86AsmParser.cpp Sat Jul 9 02:04:43 2011
@@ -19,6 +19,7 @@
#include "llvm/MC/MCParser/MCAsmLexer.h"
#include "llvm/MC/MCParser/MCAsmParser.h"
#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
+#include "llvm/ADT/OwningPtr.h"
#include "llvm/ADT/SmallString.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringExtras.h"
@@ -36,8 +37,8 @@
struct X86Operand;
class X86ATTAsmParser : public TargetAsmParser {
+ MCSubtargetInfo &STI;
MCAsmParser &Parser;
- const MCSubtargetInfo *STI;
private:
MCAsmParser &getParser() const { return Parser; }
@@ -65,7 +66,7 @@
bool is64Bit() {
// FIXME: Can tablegen auto-generate this?
- return (STI->getFeatureBits() & X86::Mode64Bit) != 0;
+ return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
}
/// @name Auto-generated Matcher Functions
@@ -77,13 +78,11 @@
/// }
public:
- X86ATTAsmParser(StringRef TT, StringRef CPU, StringRef FS,
- MCAsmParser &parser)
- : TargetAsmParser(), Parser(parser) {
- STI = X86_MC::createX86MCSubtargetInfo(TT, CPU, FS);
+ X86ATTAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
+ : TargetAsmParser(), STI(sti), Parser(parser) {
// Initialize the set of available features.
- setAvailableFeatures(ComputeAvailableFeatures(STI->getFeatureBits()));
+ setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
}
virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
Modified: llvm/branches/type-system-rewrite/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp Sat Jul 9 02:04:43 2011
@@ -107,28 +107,6 @@
}
}
-static bool hasX86_64() {
- // FIXME: Code duplication. See X86Subtarget::AutoDetectSubtargetFeatures.
- unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
- union {
- unsigned u[3];
- char c[12];
- } text;
-
- if (X86_MC::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1))
- return false;
-
- bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
- bool IsAMD = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
- if (IsIntel || IsAMD) {
- X86_MC::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
- if ((EDX >> 29) & 0x1)
- return true;
- }
-
- return false;
-}
-
MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {
std::string ArchFS = X86_MC::ParseX86Triple(TT);
@@ -140,12 +118,13 @@
}
std::string CPUName = CPU;
- if (CPUName.empty())
+ if (CPUName.empty()) {
+#if defined (__x86_64__) || defined(__i386__)
CPUName = sys::getHostCPUName();
-
- if (ArchFS.empty() && CPUName.empty() && hasX86_64())
- // Auto-detect if host is 64-bit capable, it's the default if true.
- ArchFS = "+64bit-mode";
+#else
+ CPUName = "generic";
+#endif
+ }
MCSubtargetInfo *X = new MCSubtargetInfo();
InitX86MCSubtargetInfo(X, CPUName, ArchFS);
@@ -166,17 +145,19 @@
// Force static initialization.
extern "C" void LLVMInitializeX86MCInstrInfo() {
- RegisterMCInstrInfo<MCInstrInfo> X(TheX86_32Target);
- RegisterMCInstrInfo<MCInstrInfo> Y(TheX86_64Target);
-
TargetRegistry::RegisterMCInstrInfo(TheX86_32Target, createX86MCInstrInfo);
TargetRegistry::RegisterMCInstrInfo(TheX86_64Target, createX86MCInstrInfo);
}
extern "C" void LLVMInitializeX86MCRegInfo() {
- RegisterMCRegInfo<MCRegisterInfo> X(TheX86_32Target);
- RegisterMCRegInfo<MCRegisterInfo> Y(TheX86_64Target);
-
TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo);
TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo);
}
+
+
+extern "C" void LLVMInitializeX86MCSubtargetInfo() {
+ TargetRegistry::RegisterMCSubtargetInfo(TheX86_32Target,
+ X86_MC::createX86MCSubtargetInfo);
+ TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target,
+ X86_MC::createX86MCSubtargetInfo);
+}
Modified: llvm/branches/type-system-rewrite/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/X86/X86ISelLowering.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/X86/X86ISelLowering.cpp Sat Jul 9 02:04:43 2011
@@ -235,10 +235,16 @@
// Setup Windows compiler runtime calls.
setLibcallName(RTLIB::SDIV_I64, "_alldiv");
setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
+ setLibcallName(RTLIB::SREM_I64, "_allrem");
+ setLibcallName(RTLIB::UREM_I64, "_aullrem");
+ setLibcallName(RTLIB::MUL_I64, "_allmul");
setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2");
setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2");
setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
+ setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
+ setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
+ setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C);
setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C);
}
@@ -646,6 +652,10 @@
addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
}
+ // We don't support FMA.
+ setOperationAction(ISD::FMA, MVT::f64, Expand);
+ setOperationAction(ISD::FMA, MVT::f32, Expand);
+
// Long double always uses X87.
if (!UseSoftFloat) {
addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
@@ -670,6 +680,8 @@
setOperationAction(ISD::FSIN , MVT::f80 , Expand);
setOperationAction(ISD::FCOS , MVT::f80 , Expand);
}
+
+ setOperationAction(ISD::FMA, MVT::f80, Expand);
}
// Always use a library call for pow.
Modified: llvm/branches/type-system-rewrite/lib/Target/X86/X86Subtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/X86/X86Subtarget.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/X86/X86Subtarget.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/X86/X86Subtarget.cpp Sat Jul 9 02:04:43 2011
@@ -225,7 +225,7 @@
X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
const std::string &FS,
- unsigned StackAlignOverride)
+ unsigned StackAlignOverride, bool is64Bit)
: X86GenSubtargetInfo(TT, CPU, FS)
, PICStyle(PICStyles::None)
, X86SSELevel(NoMMXSSE)
@@ -246,50 +246,45 @@
// FIXME: this is a known good value for Yonah. How about others?
, MaxInlineSizeThreshold(128)
, TargetTriple(TT)
- , In64BitMode(false) {
- // Insert the architecture feature derived from the target triple into the
- // feature string. This is important for setting features that are implied
- // based on the architecture version.
- std::string ArchFS = X86_MC::ParseX86Triple(TT);
- if (!FS.empty()) {
- if (!ArchFS.empty())
- ArchFS = ArchFS + "," + FS;
- else
- ArchFS = FS;
- }
-
- std::string CPUName = CPU;
- if (CPUName.empty())
- CPUName = sys::getHostCPUName();
-
+ , In64BitMode(is64Bit) {
// Determine default and user specified characteristics
- if (!CPUName.empty() || !ArchFS.empty()) {
+ if (!FS.empty() || !CPU.empty()) {
+ std::string CPUName = CPU;
+ if (CPUName.empty()) {
+#if defined (__x86_64__) || defined(__i386__)
+ CPUName = sys::getHostCPUName();
+#else
+ CPUName = "generic";
+#endif
+ }
+
+ // Make sure 64-bit features are available in 64-bit mode. (But make sure
+ // SSE2 can be turned off explicitly.)
+ std::string FullFS = FS;
+ if (In64BitMode) {
+ if (!FullFS.empty())
+ FullFS = "+64bit,+sse2," + FullFS;
+ else
+ FullFS = "+64bit,+sse2";
+ }
+
// If feature string is not empty, parse features string.
- ParseSubtargetFeatures(CPUName, ArchFS);
- // All X86-64 CPUs also have SSE2, however user might request no SSE via
- // -mattr, so don't force SSELevel here.
+ ParseSubtargetFeatures(CPUName, FullFS);
+
if (HasAVX)
X86SSELevel = NoMMXSSE;
} else {
// Otherwise, use CPUID to auto-detect feature set.
AutoDetectSubtargetFeatures();
- // If CPU is 64-bit capable, default to 64-bit mode if not specified.
- In64BitMode = HasX86_64;
-
- // Make sure SSE2 is enabled; it is available on all X86-64 CPUs.
- if (In64BitMode && !HasAVX && X86SSELevel < SSE2)
- X86SSELevel = SSE2;
- }
-
- // If requesting codegen for X86-64, make sure that 64-bit features
- // are enabled.
- // FIXME: Remove this feature since it's not actually being used.
- if (In64BitMode) {
- HasX86_64 = true;
-
- // All 64-bit cpus have cmov support.
- HasCMov = true;
+ // Make sure 64-bit features are available in 64-bit mode.
+ if (In64BitMode) {
+ HasX86_64 = true;
+ HasCMov = true;
+
+ if (!HasAVX && X86SSELevel < SSE2)
+ X86SSELevel = SSE2;
+ }
}
DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
Modified: llvm/branches/type-system-rewrite/lib/Target/X86/X86Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/X86/X86Subtarget.h?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/X86/X86Subtarget.h (original)
+++ llvm/branches/type-system-rewrite/lib/Target/X86/X86Subtarget.h Sat Jul 9 02:04:43 2011
@@ -122,7 +122,7 @@
///
X86Subtarget(const std::string &TT, const std::string &CPU,
const std::string &FS,
- unsigned StackAlignOverride);
+ unsigned StackAlignOverride, bool is64Bit);
/// getStackAlignment - Returns the minimum alignment known to hold of the
/// stack frame on entry to the function and which must be maintained by every
Modified: llvm/branches/type-system-rewrite/lib/Target/X86/X86TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/X86/X86TargetMachine.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/X86/X86TargetMachine.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/X86/X86TargetMachine.cpp Sat Jul 9 02:04:43 2011
@@ -120,7 +120,7 @@
const std::string &CPU,
const std::string &FS, bool is64Bit)
: LLVMTargetMachine(T, TT, CPU, FS),
- Subtarget(TT, CPU, FS, StackAlignmentOverride),
+ Subtarget(TT, CPU, FS, StackAlignmentOverride, is64Bit),
FrameLowering(*this, Subtarget),
ELFWriterInfo(is64Bit, true) {
DefRelocModel = getRelocationModel();
Modified: llvm/branches/type-system-rewrite/lib/Target/XCore/XCoreSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/XCore/XCoreSubtarget.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/XCore/XCoreSubtarget.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/XCore/XCoreSubtarget.cpp Sat Jul 9 02:04:43 2011
@@ -13,6 +13,7 @@
#include "XCoreSubtarget.h"
#include "XCore.h"
+#include "llvm/Target/TargetRegistry.h"
#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
@@ -27,3 +28,16 @@
: XCoreGenSubtargetInfo(TT, CPU, FS)
{
}
+
+
+MCSubtargetInfo *createXCoreMCSubtargetInfo(StringRef TT, StringRef CPU,
+ StringRef FS) {
+ MCSubtargetInfo *X = new MCSubtargetInfo();
+ InitXCoreMCSubtargetInfo(X, CPU, FS);
+ return X;
+}
+
+extern "C" void LLVMInitializeXCoreMCSubtargetInfo() {
+ TargetRegistry::RegisterMCSubtargetInfo(TheXCoreTarget,
+ createXCoreMCSubtargetInfo);
+}
Modified: llvm/branches/type-system-rewrite/lib/Transforms/InstCombine/InstCombineCasts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Transforms/InstCombine/InstCombineCasts.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Transforms/InstCombine/InstCombineCasts.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Transforms/InstCombine/InstCombineCasts.cpp Sat Jul 9 02:04:43 2011
@@ -30,6 +30,14 @@
}
if (BinaryOperator *I = dyn_cast<BinaryOperator>(Val)) {
+ // Cannot look past anything that might overflow.
+ OverflowingBinaryOperator *OBI = dyn_cast<OverflowingBinaryOperator>(Val);
+ if (OBI && !OBI->hasNoUnsignedWrap()) {
+ Scale = 1;
+ Offset = 0;
+ return Val;
+ }
+
if (ConstantInt *RHS = dyn_cast<ConstantInt>(I->getOperand(1))) {
if (I->getOpcode() == Instruction::Shl) {
// This is a value scaled by '1 << the shift amt'.
@@ -71,11 +79,6 @@
// This requires TargetData to get the alloca alignment and size information.
if (!TD) return 0;
- // Insist that the amount-to-allocate not overflow.
- OverflowingBinaryOperator *OBI =
- dyn_cast<OverflowingBinaryOperator>(AI.getOperand(0));
- if (OBI && !(OBI->hasNoSignedWrap() || OBI->hasNoUnsignedWrap())) return 0;
-
const PointerType *PTy = cast<PointerType>(CI.getType());
BuilderTy AllocaBuilder(*Builder);
Modified: llvm/branches/type-system-rewrite/lib/Transforms/Scalar/GVN.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Transforms/Scalar/GVN.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Transforms/Scalar/GVN.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Transforms/Scalar/GVN.cpp Sat Jul 9 02:04:43 2011
@@ -173,12 +173,15 @@
// is we'll synthesize a semantically equivalent expression instead on
// an extract value expression.
switch (I->getIntrinsicID()) {
+ case Intrinsic::sadd_with_overflow:
case Intrinsic::uadd_with_overflow:
e.opcode = Instruction::Add;
break;
+ case Intrinsic::ssub_with_overflow:
case Intrinsic::usub_with_overflow:
e.opcode = Instruction::Sub;
break;
+ case Intrinsic::smul_with_overflow:
case Intrinsic::umul_with_overflow:
e.opcode = Instruction::Mul;
break;
Modified: llvm/branches/type-system-rewrite/test/CodeGen/ARM/lsr-unfolded-offset.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/ARM/lsr-unfolded-offset.ll?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/ARM/lsr-unfolded-offset.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/ARM/lsr-unfolded-offset.ll Sat Jul 9 02:04:43 2011
@@ -4,12 +4,13 @@
; register pressure and therefore spilling. There is more room for improvement
; here.
-; CHECK: sub sp, #{{32|24}}
+; CHECK: sub sp, #{{32|28|24}}
-; CHECK: ldr r{{.*}}, [sp, #4]
-; CHECK-NEXT: ldr r{{.*}}, [sp, #16]
-; CHECK-NEXT: ldr r{{.*}}, [sp, #12]
-; CHECK-NEXT: adds
+; CHECK: %for.inc
+; CHECK: ldr{{(.w)?}} r{{.*}}, [sp, #
+; CHECK: ldr{{(.w)?}} r{{.*}}, [sp, #
+; CHECK: ldr{{(.w)?}} r{{.*}}, [sp, #
+; CHECK: add
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32"
target triple = "thumbv7-apple-macosx10.7.0"
Modified: llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/machine-licm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/machine-licm.ll?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/machine-licm.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/machine-licm.ll Sat Jul 9 02:04:43 2011
@@ -8,26 +8,25 @@
define void @t1(i32* nocapture %vals, i32 %c) nounwind {
entry:
; CHECK: t1:
-; CHECK: cbz
+; CHECK: bxeq lr
+
%0 = icmp eq i32 %c, 0 ; <i1> [#uses=1]
br i1 %0, label %return, label %bb.nph
bb.nph: ; preds = %entry
-; CHECK: BB#1
; CHECK: movw r[[R2:[0-9]+]], :lower16:L_GV$non_lazy_ptr
; CHECK: movt r[[R2]], :upper16:L_GV$non_lazy_ptr
; CHECK: ldr{{(.w)?}} r[[R2b:[0-9]+]], [r[[R2]]
; CHECK: ldr{{.*}}, [r[[R2b]]
-; CHECK: LBB0_2
+; CHECK: LBB0_
; CHECK-NOT: LCPI0_0:
-; PIC: BB#1
; PIC: movw r[[R2:[0-9]+]], :lower16:(L_GV$non_lazy_ptr-(LPC0_0+4))
; PIC: movt r[[R2]], :upper16:(L_GV$non_lazy_ptr-(LPC0_0+4))
; PIC: add r[[R2]], pc
; PIC: ldr{{(.w)?}} r[[R2b:[0-9]+]], [r[[R2]]
; PIC: ldr{{.*}}, [r[[R2b]]
-; PIC: LBB0_2
+; PIC: LBB0_
; PIC-NOT: LCPI0_0:
; PIC: .section
%.pre = load i32* @GV, align 4 ; <i32> [#uses=1]
Modified: llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/thumb2-bcc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/thumb2-bcc.ll?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/thumb2-bcc.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/thumb2-bcc.ll Sat Jul 9 02:04:43 2011
@@ -1,5 +1,7 @@
-; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
-; RUN: llc < %s -march=thumb -mattr=+thumb2 | not grep it
+; RUN: llc < %s -ifcvt-limit=0 -march=thumb -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -ifcvt-limit=0 -march=thumb -mattr=+thumb2 | not grep it
+; If-conversion defeats the purpose of this test, which is to check CBZ
+; generation, so turn it off.
define i32 @t1(i32 %a, i32 %b, i32 %c) {
; CHECK: t1:
Modified: llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/thumb2-branch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/thumb2-branch.ll?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/thumb2-branch.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/thumb2-branch.ll Sat Jul 9 02:04:43 2011
@@ -1,4 +1,6 @@
-; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+thumb2 | FileCheck %s
+; RUN: llc < %s -ifcvt-limit=0 -mtriple=thumbv7-apple-darwin -mattr=+thumb2 | FileCheck %s
+; If-conversion defeats the purpose of this test, which is to check conditional
+; branch generation, so turn it off.
define i32 @f1(i32 %a, i32 %b, i32* %v) {
entry:
Modified: llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/thumb2-ifcvt1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/thumb2-ifcvt1.ll?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/thumb2-ifcvt1.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/thumb2-ifcvt1.ll Sat Jul 9 02:04:43 2011
@@ -2,8 +2,10 @@
define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; CHECK: t1:
-; CHECK: it ne
+; CHECK: ittt ne
; CHECK: cmpne
+; CHECK: addne
+; CHECK: bxne lr
switch i32 %c, label %cond_next [
i32 1, label %cond_true
i32 7, label %cond_true
Modified: llvm/branches/type-system-rewrite/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll Sat Jul 9 02:04:43 2011
@@ -22,8 +22,11 @@
define void @t2() nounwind ssp {
entry:
; CHECK: t2:
-; CHECK: movl %eax, %ecx
-; CHECK: %ecx = foo (%ecx, %eax)
+; CHECK: movl
+; CHECK: [[D2:%e.x]] = foo
+; CHECK: ([[D2]],
+; CHECK-NOT: [[D2]]
+; CHECK: )
%b = alloca i32 ; <i32*> [#uses=2]
%a = alloca i32 ; <i32*> [#uses=1]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
Modified: llvm/branches/type-system-rewrite/test/CodeGen/X86/2010-07-11-FPStackLoneUse.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/X86/2010-07-11-FPStackLoneUse.ll?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/X86/2010-07-11-FPStackLoneUse.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/X86/2010-07-11-FPStackLoneUse.ll Sat Jul 9 02:04:43 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mcpu=i486
+; RUN: llc < %s -mcpu=core2
; PR7375
;
; This function contains a block (while.cond) with a lonely RFP use that is
Modified: llvm/branches/type-system-rewrite/test/CodeGen/X86/2011-04-13-SchedCmpJmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/X86/2011-04-13-SchedCmpJmp.ll?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/X86/2011-04-13-SchedCmpJmp.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/X86/2011-04-13-SchedCmpJmp.ll Sat Jul 9 02:04:43 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=yonah | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core2 | FileCheck %s
; Reduced from JavaScriptCore
%"class.JSC::CodeLocationCall" = type { [8 x i8] }
Modified: llvm/branches/type-system-rewrite/test/CodeGen/X86/divide-by-constant.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/X86/divide-by-constant.ll?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/X86/divide-by-constant.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/X86/divide-by-constant.ll Sat Jul 9 02:04:43 2011
@@ -40,7 +40,7 @@
%div = sdiv i16 %x, 33 ; <i32> [#uses=1]
ret i16 %div
; CHECK: test4:
-; CHECK: imull $1986, %eax, %eax
+; CHECK: imull $1986, %eax, %
}
define i32 @test5(i32 %A) nounwind {
Modified: llvm/branches/type-system-rewrite/test/CodeGen/X86/lsr-reuse-trunc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/X86/lsr-reuse-trunc.ll?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/X86/lsr-reuse-trunc.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/X86/lsr-reuse-trunc.ll Sat Jul 9 02:04:43 2011
@@ -5,8 +5,9 @@
; stick with indexing here.
; CHECK: movaps (%{{rsi|rdx}},%rax,4), [[X3:%xmm[0-9]+]]
-; CHECK: movaps
-; CHECK: [[X3]], (%{{rdi|rcx}},%rax,4)
+; CHECK: cvtdq2ps
+; CHECK: orps {{%xmm[0-9]+}}, [[X4:%xmm[0-9]+]]
+; CHECK: movaps [[X4]], (%{{rdi|rcx}},%rax,4)
; CHECK: addq $4, %rax
; CHECK: cmpl %eax, (%{{rdx|r8}})
; CHECK-NEXT: jg
Modified: llvm/branches/type-system-rewrite/test/CodeGen/X86/peep-test-3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/X86/peep-test-3.ll?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/X86/peep-test-3.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/X86/peep-test-3.ll Sat Jul 9 02:04:43 2011
@@ -9,7 +9,7 @@
%0 = ptrtoint float* %A to i32 ; <i32> [#uses=1]
%1 = and i32 %0, 3 ; <i32> [#uses=1]
%2 = xor i32 %IA, 1 ; <i32> [#uses=1]
-; CHECK: orl %ecx, %edx
+; CHECK: orl %e
; CHECK-NEXT: je
%3 = or i32 %2, %1 ; <i32> [#uses=1]
%4 = icmp eq i32 %3, 0 ; <i1> [#uses=1]
Modified: llvm/branches/type-system-rewrite/test/CodeGen/X86/sse1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/X86/sse1.ll?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/X86/sse1.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/X86/sse1.ll Sat Jul 9 02:04:43 2011
@@ -1,6 +1,6 @@
; Tests for SSE1 and below, without SSE2+.
; RUN: llc < %s -march=x86 -mcpu=pentium3 -O3 | FileCheck %s
-; RUN: llc < %s -march=x86-64 -mcpu=pentium3 -O3 | FileCheck %s
+; RUN: llc < %s -march=x86-64 -mattr=-sse2,+sse -O3 | FileCheck %s
define <8 x i16> @test1(<8 x i32> %a) nounwind {
; CHECK: test1
Modified: llvm/branches/type-system-rewrite/test/CodeGen/X86/sse3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/X86/sse3.ll?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/X86/sse3.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/X86/sse3.ll Sat Jul 9 02:04:43 2011
@@ -1,6 +1,6 @@
-; These are tests for SSE3 codegen. Yonah has SSE3 and earlier but not SSSE3+.
+; These are tests for SSE3 codegen.
-; RUN: llc < %s -march=x86-64 -mcpu=yonah -mtriple=i686-apple-darwin9 -O3 \
+; RUN: llc < %s -march=x86-64 -mcpu=nocona -mtriple=i686-apple-darwin9 -O3 \
; RUN: | FileCheck %s --check-prefix=X64
; Test for v8xi16 lowering where we extract the first element of the vector and
@@ -169,10 +169,10 @@
; X64: t10:
; X64: pextrw $4, [[X0:%xmm[0-9]+]], %eax
; X64: unpcklpd [[X1:%xmm[0-9]+]]
-; X64: pshuflw $8, [[X1]], [[X1]]
-; X64: pinsrw $2, %eax, [[X1]]
+; X64: pshuflw $8, [[X1]], [[X2:%xmm[0-9]+]]
+; X64: pinsrw $2, %eax, [[X2]]
; X64: pextrw $6, [[X0]], %eax
-; X64: pinsrw $3, %eax, [[X1]]
+; X64: pinsrw $3, %eax, [[X2]]
}
Modified: llvm/branches/type-system-rewrite/test/Transforms/GVN/2011-07-07-MatchIntrinsicExtract.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/Transforms/GVN/2011-07-07-MatchIntrinsicExtract.ll?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/Transforms/GVN/2011-07-07-MatchIntrinsicExtract.ll (original)
+++ llvm/branches/type-system-rewrite/test/Transforms/GVN/2011-07-07-MatchIntrinsicExtract.ll Sat Jul 9 02:04:43 2011
@@ -39,9 +39,47 @@
; CHECK-NOT: mul1
; CHECK: ret
+define i64 @test4(i64 %a, i64 %b) nounwind ssp {
+entry:
+ %sadd = tail call %0 @llvm.sadd.with.overflow.i64(i64 %a, i64 %b)
+ %sadd.0 = extractvalue %0 %sadd, 0
+ %add1 = add i64 %a, %b
+ ret i64 %add1
+}
+
+; CHECK: @test4
+; CHECK-NOT: add1
+; CHECK: ret
+
+define i64 @test5(i64 %a, i64 %b) nounwind ssp {
+entry:
+ %ssub = tail call %0 @llvm.ssub.with.overflow.i64(i64 %a, i64 %b)
+ %ssub.0 = extractvalue %0 %ssub, 0
+ %sub1 = sub i64 %a, %b
+ ret i64 %sub1
+}
+
+; CHECK: @test5
+; CHECK-NOT: sub1
+; CHECK: ret
+
+define i64 @test6(i64 %a, i64 %b) nounwind ssp {
+entry:
+ %smul = tail call %0 @llvm.smul.with.overflow.i64(i64 %a, i64 %b)
+ %smul.0 = extractvalue %0 %smul, 0
+ %mul1 = mul i64 %a, %b
+ ret i64 %mul1
+}
+
+; CHECK: @test6
+; CHECK-NOT: mul1
+; CHECK: ret
declare void @exit(i32) noreturn
declare %0 @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone
declare %0 @llvm.usub.with.overflow.i64(i64, i64) nounwind readnone
declare %0 @llvm.umul.with.overflow.i64(i64, i64) nounwind readnone
+declare %0 @llvm.sadd.with.overflow.i64(i64, i64) nounwind readnone
+declare %0 @llvm.ssub.with.overflow.i64(i64, i64) nounwind readnone
+declare %0 @llvm.smul.with.overflow.i64(i64, i64) nounwind readnone
Modified: llvm/branches/type-system-rewrite/tools/llc/llc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/tools/llc/llc.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/tools/llc/llc.cpp (original)
+++ llvm/branches/type-system-rewrite/tools/llc/llc.cpp Sat Jul 9 02:04:43 2011
@@ -201,6 +201,7 @@
// Initialize targets first, so that --version shows registered targets.
InitializeAllTargets();
+ InitializeAllMCSubtargetInfos();
InitializeAllAsmPrinters();
InitializeAllAsmParsers();
Modified: llvm/branches/type-system-rewrite/tools/llvm-mc/llvm-mc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/tools/llvm-mc/llvm-mc.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/tools/llvm-mc/llvm-mc.cpp (original)
+++ llvm/branches/type-system-rewrite/tools/llvm-mc/llvm-mc.cpp Sat Jul 9 02:04:43 2011
@@ -19,6 +19,7 @@
#include "llvm/MC/MCInstPrinter.h"
#include "llvm/MC/MCSectionMachO.h"
#include "llvm/MC/MCStreamer.h"
+#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/SubtargetFeature.h"
#include "llvm/Target/TargetAsmBackend.h"
#include "llvm/Target/TargetAsmParser.h"
@@ -340,6 +341,9 @@
TM->getTargetLowering()->getObjFileLowering();
const_cast<TargetLoweringObjectFile&>(TLOF).Initialize(Ctx, *TM);
+ OwningPtr<MCSubtargetInfo>
+ STI(TheTarget->createMCSubtargetInfo(TripleName, MCPU, FeaturesStr));
+
// FIXME: There is a bit of code duplication with addPassesToEmitFile.
if (FileType == OFT_AssemblyFile) {
MCInstPrinter *IP =
@@ -371,8 +375,7 @@
OwningPtr<MCAsmParser> Parser(createMCAsmParser(*TheTarget, SrcMgr, Ctx,
*Str.get(), *MAI));
- OwningPtr<TargetAsmParser>
- TAP(TheTarget->createAsmParser(TripleName, MCPU, FeaturesStr, *Parser));
+ OwningPtr<TargetAsmParser> TAP(TheTarget->createAsmParser(*STI, *Parser));
if (!TAP) {
errs() << ProgName
<< ": error: this target does not support assembly parsing.\n";
@@ -448,6 +451,7 @@
llvm::InitializeAllTargetInfos();
// FIXME: We shouldn't need to initialize the Target(Machine)s.
llvm::InitializeAllTargets();
+ llvm::InitializeAllMCSubtargetInfos();
llvm::InitializeAllAsmPrinters();
llvm::InitializeAllAsmParsers();
llvm::InitializeAllDisassemblers();
Modified: llvm/branches/type-system-rewrite/tools/lto/LTOModule.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/tools/lto/LTOModule.cpp?rev=134804&r1=134803&r2=134804&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/tools/lto/LTOModule.cpp (original)
+++ llvm/branches/type-system-rewrite/tools/lto/LTOModule.cpp Sat Jul 9 02:04:43 2011
@@ -35,6 +35,7 @@
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCParser/MCAsmParser.h"
#include "llvm/MC/MCStreamer.h"
+#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/MC/SubtargetFeature.h"
#include "llvm/Target/TargetAsmParser.h"
@@ -618,11 +619,12 @@
OwningPtr<MCAsmParser> Parser(createMCAsmParser(_target->getTarget(), SrcMgr,
Context, *Streamer,
*_target->getMCAsmInfo()));
+ OwningPtr<MCSubtargetInfo> STI(_target->getTarget().
+ createMCSubtargetInfo(_target->getTargetTriple(),
+ _target->getTargetCPU(),
+ _target->getTargetFeatureString()));
OwningPtr<TargetAsmParser>
- TAP(_target->getTarget().createAsmParser(_target->getTargetTriple(),
- _target->getTargetCPU(),
- _target->getTargetFeatureString(),
- *Parser.get()));
+ TAP(_target->getTarget().createAsmParser(*STI, *Parser.get()));
Parser->setTargetParser(*TAP);
int Res = Parser->Run(false);
if (Res)
More information about the llvm-branch-commits
mailing list