[llvm-branch-commits] [llvm-branch] r134726 - in /llvm/branches/type-system-rewrite: ./ cmake/modules/ include/llvm/Target/ lib/CodeGen/AsmPrinter/ lib/CodeGen/SelectionDAG/ lib/MC/MCParser/ lib/Target/ARM/ lib/Target/ARM/AsmParser/ lib/Target/MBlaze/AsmParser/ lib/Target/X86/AsmParser/ lib/Transforms/Utils/ test/CodeGen/ARM/ test/CodeGen/X86/ utils/TableGen/
Chris Lattner
sabre at nondot.org
Fri Jul 8 13:11:56 PDT 2011
Author: lattner
Date: Fri Jul 8 15:11:55 2011
New Revision: 134726
URL: http://llvm.org/viewvc/llvm-project?rev=134726&view=rev
Log:
Merging r134685 through r134725 from mainline into the branch.
Added:
llvm/branches/type-system-rewrite/test/CodeGen/X86/sdiv-exact.ll
- copied unchanged from r134725, llvm/trunk/test/CodeGen/X86/sdiv-exact.ll
llvm/branches/type-system-rewrite/utils/TableGen/PseudoLoweringEmitter.cpp
- copied unchanged from r134725, llvm/trunk/utils/TableGen/PseudoLoweringEmitter.cpp
llvm/branches/type-system-rewrite/utils/TableGen/PseudoLoweringEmitter.h
- copied unchanged from r134725, llvm/trunk/utils/TableGen/PseudoLoweringEmitter.h
Modified:
llvm/branches/type-system-rewrite/ (props changed)
llvm/branches/type-system-rewrite/Makefile.rules
llvm/branches/type-system-rewrite/cmake/modules/LLVMLibDeps.cmake
llvm/branches/type-system-rewrite/include/llvm/Target/Target.td
llvm/branches/type-system-rewrite/include/llvm/Target/TargetAsmParser.h
llvm/branches/type-system-rewrite/include/llvm/Target/TargetLowering.h
llvm/branches/type-system-rewrite/include/llvm/Target/TargetRegistry.h
llvm/branches/type-system-rewrite/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
llvm/branches/type-system-rewrite/lib/CodeGen/AsmPrinter/DwarfDebug.h
llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/branches/type-system-rewrite/lib/MC/MCParser/TargetAsmParser.cpp
llvm/branches/type-system-rewrite/lib/Target/ARM/ARMAsmPrinter.cpp
llvm/branches/type-system-rewrite/lib/Target/ARM/ARMAsmPrinter.h
llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrFormats.td
llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrInfo.td
llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrThumb.td
llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrThumb2.td
llvm/branches/type-system-rewrite/lib/Target/ARM/ARMMCInstLower.cpp
llvm/branches/type-system-rewrite/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/branches/type-system-rewrite/lib/Target/ARM/CMakeLists.txt
llvm/branches/type-system-rewrite/lib/Target/ARM/Makefile
llvm/branches/type-system-rewrite/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp
llvm/branches/type-system-rewrite/lib/Target/X86/AsmParser/X86AsmParser.cpp
llvm/branches/type-system-rewrite/lib/Transforms/Utils/CloneFunction.cpp
llvm/branches/type-system-rewrite/lib/Transforms/Utils/InlineFunction.cpp
llvm/branches/type-system-rewrite/test/CodeGen/ARM/call-tc.ll
llvm/branches/type-system-rewrite/utils/TableGen/AsmMatcherEmitter.cpp
llvm/branches/type-system-rewrite/utils/TableGen/CMakeLists.txt
llvm/branches/type-system-rewrite/utils/TableGen/TableGen.cpp
Propchange: llvm/branches/type-system-rewrite/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Fri Jul 8 15:11:55 2011
@@ -1,2 +1,2 @@
/llvm/branches/Apple/Pertwee:110850,110961
-/llvm/trunk:133420-134362,134364-134683
+/llvm/trunk:133420-134362,134364-134683,134685-134725
Modified: llvm/branches/type-system-rewrite/Makefile.rules
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/Makefile.rules?rev=134726&r1=134725&r2=134726&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/Makefile.rules (original)
+++ llvm/branches/type-system-rewrite/Makefile.rules Fri Jul 8 15:11:55 2011
@@ -1750,6 +1750,11 @@
$(Echo) "Building $(<F) MC code emitter with tblgen"
$(Verb) $(TableGen) -gen-emitter -mc-emitter -o $(call SYSPATH, $@) $<
+$(TARGET:%=$(ObjDir)/%GenMCPseudoLowering.inc.tmp): \
+$(ObjDir)/%GenMCPseudoLowering.inc.tmp: %.td $(ObjDir)/.dir
+ $(Echo) "Building $(<F) MC Pseudo instruction expander with tblgen"
+ $(Verb) $(TableGen) -gen-pseudo-lowering -o $(call SYSPATH, $@) $<
+
$(TARGET:%=$(ObjDir)/%GenCodeEmitter.inc.tmp): \
$(ObjDir)/%GenCodeEmitter.inc.tmp: %.td $(ObjDir)/.dir
$(Echo) "Building $(<F) code emitter with tblgen"
Modified: llvm/branches/type-system-rewrite/cmake/modules/LLVMLibDeps.cmake
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/cmake/modules/LLVMLibDeps.cmake?rev=134726&r1=134725&r2=134726&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/cmake/modules/LLVMLibDeps.cmake (original)
+++ llvm/branches/type-system-rewrite/cmake/modules/LLVMLibDeps.cmake Fri Jul 8 15:11:55 2011
@@ -1,4 +1,4 @@
-set(MSVC_LIB_DEPS_LLVMARMAsmParser LLVMARMCodeGen LLVMARMInfo LLVMMC LLVMMCParser LLVMSupport LLVMTarget)
+set(MSVC_LIB_DEPS_LLVMARMAsmParser LLVMARMCodeGen LLVMARMDesc LLVMARMInfo LLVMMC LLVMMCParser LLVMSupport LLVMTarget)
set(MSVC_LIB_DEPS_LLVMARMAsmPrinter LLVMMC LLVMSupport)
set(MSVC_LIB_DEPS_LLVMARMCodeGen LLVMARMAsmPrinter LLVMARMDesc LLVMARMInfo LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget)
set(MSVC_LIB_DEPS_LLVMARMDesc LLVMARMInfo LLVMMC)
@@ -40,7 +40,8 @@
set(MSVC_LIB_DEPS_LLVMMSP430AsmPrinter LLVMMC LLVMSupport)
set(MSVC_LIB_DEPS_LLVMMSP430CodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMMSP430AsmPrinter LLVMMSP430Info LLVMSelectionDAG LLVMSupport LLVMTarget)
set(MSVC_LIB_DEPS_LLVMMSP430Info LLVMMC LLVMSupport)
-set(MSVC_LIB_DEPS_LLVMMipsCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMMipsInfo LLVMSelectionDAG LLVMSupport LLVMTarget)
+set(MSVC_LIB_DEPS_LLVMMipsAsmPrinter LLVMMC LLVMSupport)
+set(MSVC_LIB_DEPS_LLVMMipsCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMMipsAsmPrinter LLVMMipsInfo LLVMSelectionDAG LLVMSupport LLVMTarget)
set(MSVC_LIB_DEPS_LLVMMipsInfo LLVMMC LLVMSupport)
set(MSVC_LIB_DEPS_LLVMObject LLVMSupport)
set(MSVC_LIB_DEPS_LLVMPTXCodeGen LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMPTXInfo LLVMSelectionDAG LLVMSupport LLVMTarget)
@@ -58,10 +59,10 @@
set(MSVC_LIB_DEPS_LLVMSystemZInfo LLVMMC LLVMSupport)
set(MSVC_LIB_DEPS_LLVMTarget LLVMCore LLVMMC LLVMSupport)
set(MSVC_LIB_DEPS_LLVMTransformUtils LLVMAnalysis LLVMCore LLVMSupport LLVMTarget LLVMipa)
-set(MSVC_LIB_DEPS_LLVMX86AsmParser LLVMMC LLVMMCParser LLVMSupport LLVMTarget LLVMX86Info)
+set(MSVC_LIB_DEPS_LLVMX86AsmParser LLVMMC LLVMMCParser LLVMSupport LLVMTarget LLVMX86Desc LLVMX86Info)
set(MSVC_LIB_DEPS_LLVMX86AsmPrinter LLVMMC LLVMSupport LLVMX86Utils)
set(MSVC_LIB_DEPS_LLVMX86CodeGen LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget LLVMX86AsmPrinter LLVMX86Desc LLVMX86Info LLVMX86Utils)
-set(MSVC_LIB_DEPS_LLVMX86Desc LLVMMC LLVMX86Info)
+set(MSVC_LIB_DEPS_LLVMX86Desc LLVMMC LLVMSupport LLVMX86Info)
set(MSVC_LIB_DEPS_LLVMX86Disassembler LLVMMC LLVMSupport LLVMX86Info)
set(MSVC_LIB_DEPS_LLVMX86Info LLVMMC LLVMSupport)
set(MSVC_LIB_DEPS_LLVMX86Utils LLVMCore LLVMSupport)
Modified: llvm/branches/type-system-rewrite/include/llvm/Target/Target.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/include/llvm/Target/Target.td?rev=134726&r1=134725&r2=134726&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/include/llvm/Target/Target.td (original)
+++ llvm/branches/type-system-rewrite/include/llvm/Target/Target.td Fri Jul 8 15:11:55 2011
@@ -373,6 +373,14 @@
///@}
}
+/// PseudoInstExpansion - Expansion information for a pseudo-instruction.
+/// Which instruction it expands to and how the operands map from the
+/// pseudo.
+class PseudoInstExpansion<dag Result> {
+ dag ResultInst = Result; // The instruction to generate.
+ bit isPseudo = 1;
+}
+
/// Predicates - These are extra conditionals which are turned into instruction
/// selector matching code. Currently each predicate is just a string.
class Predicate<string cond> {
Modified: llvm/branches/type-system-rewrite/include/llvm/Target/TargetAsmParser.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/include/llvm/Target/TargetAsmParser.h?rev=134726&r1=134725&r2=134726&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/include/llvm/Target/TargetAsmParser.h (original)
+++ llvm/branches/type-system-rewrite/include/llvm/Target/TargetAsmParser.h Fri Jul 8 15:11:55 2011
@@ -15,7 +15,6 @@
namespace llvm {
class MCStreamer;
class StringRef;
-class Target;
class SMLoc;
class AsmToken;
class MCParsedAsmOperand;
@@ -26,23 +25,19 @@
TargetAsmParser(const TargetAsmParser &); // DO NOT IMPLEMENT
void operator=(const TargetAsmParser &); // DO NOT IMPLEMENT
protected: // Can only create subclasses.
- TargetAsmParser(const Target &);
+ TargetAsmParser();
- /// The Target that this machine was created for.
- const Target &TheTarget;
-
- /// The current set of available features.
+ /// AvailableFeatures - The current set of available features.
unsigned AvailableFeatures;
public:
virtual ~TargetAsmParser();
- const Target &getTarget() const { return TheTarget; }
-
unsigned getAvailableFeatures() const { return AvailableFeatures; }
void setAvailableFeatures(unsigned Value) { AvailableFeatures = Value; }
- virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) = 0;
+ virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+ SMLoc &EndLoc) = 0;
/// ParseInstruction - Parse one assembly instruction.
///
Modified: llvm/branches/type-system-rewrite/include/llvm/Target/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/include/llvm/Target/TargetLowering.h?rev=134726&r1=134725&r2=134726&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/include/llvm/Target/TargetLowering.h (original)
+++ llvm/branches/type-system-rewrite/include/llvm/Target/TargetLowering.h Fri Jul 8 15:11:55 2011
@@ -1540,6 +1540,8 @@
//===--------------------------------------------------------------------===//
// Div utility functions
//
+ SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl,
+ SelectionDAG &DAG) const;
SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG,
std::vector<SDNode*>* Created) const;
SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG,
Modified: llvm/branches/type-system-rewrite/include/llvm/Target/TargetRegistry.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/include/llvm/Target/TargetRegistry.h?rev=134726&r1=134725&r2=134726&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/include/llvm/Target/TargetRegistry.h (original)
+++ llvm/branches/type-system-rewrite/include/llvm/Target/TargetRegistry.h Fri Jul 8 15:11:55 2011
@@ -79,7 +79,7 @@
const std::string &TT);
typedef TargetAsmLexer *(*AsmLexerCtorTy)(const Target &T,
const MCAsmInfo &MAI);
- typedef TargetAsmParser *(*AsmParserCtorTy)(const Target &T, StringRef TT,
+ typedef TargetAsmParser *(*AsmParserCtorTy)(StringRef TT,
StringRef CPU, StringRef Features,
MCAsmParser &P);
typedef MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T);
@@ -300,10 +300,11 @@
/// \arg Parser - The target independent parser implementation to use for
/// parsing and lexing.
TargetAsmParser *createAsmParser(StringRef Triple, StringRef CPU,
- StringRef Features, MCAsmParser &Parser) const {
+ StringRef Features,
+ MCAsmParser &Parser) const {
if (!AsmParserCtorFn)
return 0;
- return AsmParserCtorFn(*this, Triple, CPU, Features, Parser);
+ return AsmParserCtorFn(Triple, CPU, Features, Parser);
}
/// createAsmPrinter - Create a target specific assembly printer pass. This
@@ -858,10 +859,9 @@
}
private:
- static TargetAsmParser *Allocator(const Target &T, StringRef TT,
- StringRef CPU, StringRef FS,
- MCAsmParser &P) {
- return new AsmParserImpl(T, TT, CPU, FS, P);
+ static TargetAsmParser *Allocator(StringRef TT, StringRef CPU,
+ StringRef FS, MCAsmParser &P) {
+ return new AsmParserImpl(TT, CPU, FS, P);
}
};
Modified: llvm/branches/type-system-rewrite/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=134726&r1=134725&r2=134726&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Fri Jul 8 15:11:55 2011
@@ -1355,6 +1355,34 @@
MI->getOperand(1).isImm() && MI->getOperand(1).getImm() == 0;
}
+/// getDebugLocEntry - Get .debug_loc entry for the instraction range starting
+/// at MI.
+static DotDebugLocEntry getDebugLocEntry(AsmPrinter *Asm,
+ const MCSymbol *FLabel,
+ const MCSymbol *SLabel,
+ const MachineInstr *MI) {
+ const MDNode *Var = MI->getOperand(MI->getNumOperands() - 1).getMetadata();
+
+ if (MI->getNumOperands() != 3) {
+ MachineLocation MLoc = Asm->getDebugValueLocation(MI);
+ return DotDebugLocEntry(FLabel, SLabel, MLoc, Var);
+ }
+ if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm()) {
+ MachineLocation MLoc;
+ MLoc.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
+ return DotDebugLocEntry(FLabel, SLabel, MLoc, Var);
+ }
+ if (MI->getOperand(0).isImm())
+ return DotDebugLocEntry(FLabel, SLabel, MI->getOperand(0).getImm());
+ if (MI->getOperand(0).isFPImm())
+ return DotDebugLocEntry(FLabel, SLabel, MI->getOperand(0).getFPImm());
+ if (MI->getOperand(0).isCImm())
+ return DotDebugLocEntry(FLabel, SLabel, MI->getOperand(0).getCImm());
+
+ assert (0 && "Unexpected 3 operand DBG_VALUE instruction!");
+ return DotDebugLocEntry();
+}
+
/// collectVariableInfo - Populate DbgScope entries with variables' info.
void
DwarfDebug::collectVariableInfo(const MachineFunction *MF,
@@ -1441,25 +1469,7 @@
}
// The value is valid until the next DBG_VALUE or clobber.
- MachineLocation MLoc;
- if (Begin->getNumOperands() == 3) {
- if (Begin->getOperand(0).isReg() && Begin->getOperand(1).isImm()) {
- MLoc.set(Begin->getOperand(0).getReg(),
- Begin->getOperand(1).getImm());
- DotDebugLocEntries.
- push_back(DotDebugLocEntry(FLabel, SLabel, MLoc, Var));
- }
- // FIXME: Handle isFPImm also.
- else if (Begin->getOperand(0).isImm()) {
- DotDebugLocEntries.
- push_back(DotDebugLocEntry(FLabel, SLabel,
- Begin->getOperand(0).getImm()));
- }
- } else {
- MLoc = Asm->getDebugValueLocation(Begin);
- DotDebugLocEntries.
- push_back(DotDebugLocEntry(FLabel, SLabel, MLoc, Var));
- }
+ DotDebugLocEntries.push_back(getDebugLocEntry(Asm, FLabel, SLabel, Begin));
}
DotDebugLocEntries.push_back(DotDebugLocEntry());
}
@@ -2608,56 +2618,61 @@
MCSymbol *end = Asm->OutStreamer.getContext().CreateTempSymbol();
Asm->EmitLabelDifference(end, begin, 2);
Asm->OutStreamer.EmitLabel(begin);
- if (Entry.isConstant()) {
+ if (Entry.isInt()) {
DIBasicType BTy(DV.getType());
if (BTy.Verify() &&
(BTy.getEncoding() == dwarf::DW_ATE_signed
|| BTy.getEncoding() == dwarf::DW_ATE_signed_char)) {
Asm->OutStreamer.AddComment("DW_OP_consts");
Asm->EmitInt8(dwarf::DW_OP_consts);
- Asm->EmitSLEB128(Entry.getConstant());
+ Asm->EmitSLEB128(Entry.getInt());
} else {
Asm->OutStreamer.AddComment("DW_OP_constu");
Asm->EmitInt8(dwarf::DW_OP_constu);
- Asm->EmitULEB128(Entry.getConstant());
+ Asm->EmitULEB128(Entry.getInt());
}
- } else if (DV.hasComplexAddress()) {
- unsigned N = DV.getNumAddrElements();
- unsigned i = 0;
- if (N >= 2 && DV.getAddrElement(0) == DIBuilder::OpPlus) {
- if (Entry.Loc.getOffset()) {
- i = 2;
- Asm->EmitDwarfRegOp(Entry.Loc);
- Asm->OutStreamer.AddComment("DW_OP_deref");
- Asm->EmitInt8(dwarf::DW_OP_deref);
- Asm->OutStreamer.AddComment("DW_OP_plus_uconst");
- Asm->EmitInt8(dwarf::DW_OP_plus_uconst);
- Asm->EmitSLEB128(DV.getAddrElement(1));
+ } else if (Entry.isLocation()) {
+ if (!DV.hasComplexAddress())
+ // Regular entry.
+ Asm->EmitDwarfRegOp(Entry.Loc);
+ else {
+ // Complex address entry.
+ unsigned N = DV.getNumAddrElements();
+ unsigned i = 0;
+ if (N >= 2 && DV.getAddrElement(0) == DIBuilder::OpPlus) {
+ if (Entry.Loc.getOffset()) {
+ i = 2;
+ Asm->EmitDwarfRegOp(Entry.Loc);
+ Asm->OutStreamer.AddComment("DW_OP_deref");
+ Asm->EmitInt8(dwarf::DW_OP_deref);
+ Asm->OutStreamer.AddComment("DW_OP_plus_uconst");
+ Asm->EmitInt8(dwarf::DW_OP_plus_uconst);
+ Asm->EmitSLEB128(DV.getAddrElement(1));
+ } else {
+ // If first address element is OpPlus then emit
+ // DW_OP_breg + Offset instead of DW_OP_reg + Offset.
+ MachineLocation Loc(Entry.Loc.getReg(), DV.getAddrElement(1));
+ Asm->EmitDwarfRegOp(Loc);
+ i = 2;
+ }
} else {
- // If first address element is OpPlus then emit
- // DW_OP_breg + Offset instead of DW_OP_reg + Offset.
- MachineLocation Loc(Entry.Loc.getReg(), DV.getAddrElement(1));
- Asm->EmitDwarfRegOp(Loc);
- i = 2;
+ Asm->EmitDwarfRegOp(Entry.Loc);
+ }
+
+ // Emit remaining complex address elements.
+ for (; i < N; ++i) {
+ uint64_t Element = DV.getAddrElement(i);
+ if (Element == DIBuilder::OpPlus) {
+ Asm->EmitInt8(dwarf::DW_OP_plus_uconst);
+ Asm->EmitULEB128(DV.getAddrElement(++i));
+ } else if (Element == DIBuilder::OpDeref)
+ Asm->EmitInt8(dwarf::DW_OP_deref);
+ else llvm_unreachable("unknown Opcode found in complex address");
}
- } else {
- Asm->EmitDwarfRegOp(Entry.Loc);
- }
-
- // Emit remaining complex address elements.
- for (; i < N; ++i) {
- uint64_t Element = DV.getAddrElement(i);
- if (Element == DIBuilder::OpPlus) {
- Asm->EmitInt8(dwarf::DW_OP_plus_uconst);
- Asm->EmitULEB128(DV.getAddrElement(++i));
- } else if (Element == DIBuilder::OpDeref)
- Asm->EmitInt8(dwarf::DW_OP_deref);
- else llvm_unreachable("unknown Opcode found in complex address");
}
- } else {
- // Regular entry.
- Asm->EmitDwarfRegOp(Entry.Loc);
}
+ // else ... ignore constant fp. There is not any good way to
+ // to represent them here in dwarf.
Asm->OutStreamer.EmitLabel(end);
}
}
Modified: llvm/branches/type-system-rewrite/lib/CodeGen/AsmPrinter/DwarfDebug.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=134726&r1=134725&r2=134726&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/CodeGen/AsmPrinter/DwarfDebug.h (original)
+++ llvm/branches/type-system-rewrite/lib/CodeGen/AsmPrinter/DwarfDebug.h Fri Jul 8 15:11:55 2011
@@ -69,17 +69,35 @@
const MDNode *Variable;
bool Merged;
bool Constant;
- int64_t iConstant;
+ enum EntryType {
+ E_Location,
+ E_Integer,
+ E_ConstantFP,
+ E_ConstantInt
+ };
+ enum EntryType EntryKind;
+
+ union {
+ int64_t Int;
+ const ConstantFP *CFP;
+ const ConstantInt *CIP;
+ } Constants;
DotDebugLocEntry()
: Begin(0), End(0), Variable(0), Merged(false),
- Constant(false), iConstant(0) {}
+ Constant(false) { Constants.Int = 0;}
DotDebugLocEntry(const MCSymbol *B, const MCSymbol *E, MachineLocation &L,
const MDNode *V)
: Begin(B), End(E), Loc(L), Variable(V), Merged(false),
- Constant(false), iConstant(0) {}
+ Constant(false) { Constants.Int = 0; EntryKind = E_Location; }
DotDebugLocEntry(const MCSymbol *B, const MCSymbol *E, int64_t i)
: Begin(B), End(E), Variable(0), Merged(false),
- Constant(true), iConstant(i) {}
+ Constant(true) { Constants.Int = i; EntryKind = E_Integer; }
+ DotDebugLocEntry(const MCSymbol *B, const MCSymbol *E, const ConstantFP *FPtr)
+ : Begin(B), End(E), Variable(0), Merged(false),
+ Constant(true) { Constants.CFP = FPtr; EntryKind = E_ConstantFP; }
+ DotDebugLocEntry(const MCSymbol *B, const MCSymbol *E, const ConstantInt *IPtr)
+ : Begin(B), End(E), Variable(0), Merged(false),
+ Constant(true) { Constants.CIP = IPtr; EntryKind = E_ConstantInt; }
/// Empty entries are also used as a trigger to emit temp label. Such
/// labels are referenced is used to find debug_loc offset for a given DIE.
@@ -91,8 +109,13 @@
Next->Begin = Begin;
Merged = true;
}
- bool isConstant() { return Constant; }
- int64_t getConstant() { return iConstant; }
+ bool isLocation() const { return EntryKind == E_Location; }
+ bool isInt() const { return EntryKind == E_Integer; }
+ bool isConstantFP() const { return EntryKind == E_ConstantFP; }
+ bool isConstantInt() const { return EntryKind == E_ConstantInt; }
+ int64_t getInt() { return Constants.Int; }
+ const ConstantFP *getConstantFP() { return Constants.CFP; }
+ const ConstantInt *getConstantInt() { return Constants.CIP; }
} DotDebugLocEntry;
//===----------------------------------------------------------------------===//
Modified: llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=134726&r1=134725&r2=134726&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Fri Jul 8 15:11:55 2011
@@ -2501,6 +2501,22 @@
Op1.getValueType(), Op1, Op2));
}
+void SelectionDAGBuilder::visitSDiv(const User &I) {
+ SDValue Op1 = getValue(I.getOperand(0));
+ SDValue Op2 = getValue(I.getOperand(1));
+
+ // Turn exact SDivs into multiplications.
+ // FIXME: This should be in DAGCombiner, but it doesn't have access to the
+ // exact bit.
+ if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
+ !isa<ConstantSDNode>(Op1) &&
+ isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
+ setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG));
+ else
+ setValue(&I, DAG.getNode(ISD::SDIV, getCurDebugLoc(), Op1.getValueType(),
+ Op1, Op2));
+}
+
void SelectionDAGBuilder::visitICmp(const User &I) {
ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
Modified: llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h?rev=134726&r1=134725&r2=134726&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h (original)
+++ llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h Fri Jul 8 15:11:55 2011
@@ -467,7 +467,7 @@
void visitSRem(const User &I) { visitBinary(I, ISD::SREM); }
void visitFRem(const User &I) { visitBinary(I, ISD::FREM); }
void visitUDiv(const User &I) { visitBinary(I, ISD::UDIV); }
- void visitSDiv(const User &I) { visitBinary(I, ISD::SDIV); }
+ void visitSDiv(const User &I);
void visitFDiv(const User &I) { visitBinary(I, ISD::FDIV); }
void visitAnd (const User &I) { visitBinary(I, ISD::AND); }
void visitOr (const User &I) { visitBinary(I, ISD::OR); }
Modified: llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=134726&r1=134725&r2=134726&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/TargetLowering.cpp Fri Jul 8 15:11:55 2011
@@ -3211,6 +3211,32 @@
return true;
}
+/// BuildExactDiv - Given an exact SDIV by a constant, create a multiplication
+/// with the multiplicative inverse of the constant.
+SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl,
+ SelectionDAG &DAG) const {
+ ConstantSDNode *C = cast<ConstantSDNode>(Op2);
+ APInt d = C->getAPIntValue();
+ assert(d != 0 && "Division by zero!");
+
+ // Shift the value upfront if it is even, so the LSB is one.
+ unsigned ShAmt = d.countTrailingZeros();
+ if (ShAmt) {
+ // TODO: For UDIV use SRL instead of SRA.
+ SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType()));
+ Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt);
+ d = d.ashr(ShAmt);
+ }
+
+ // Calculate the multiplicative inverse, using Newton's method.
+ APInt t, xn = d;
+ while ((t = d*xn) != 1)
+ xn *= APInt(d.getBitWidth(), 2) - t;
+
+ Op2 = DAG.getConstant(xn, Op1.getValueType());
+ return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
+}
+
/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
/// return a DAG expression to select that will generate the same value by
/// multiplying by a magic number. See:
Modified: llvm/branches/type-system-rewrite/lib/MC/MCParser/TargetAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/MC/MCParser/TargetAsmParser.cpp?rev=134726&r1=134725&r2=134726&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/MC/MCParser/TargetAsmParser.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/MC/MCParser/TargetAsmParser.cpp Fri Jul 8 15:11:55 2011
@@ -10,8 +10,8 @@
#include "llvm/Target/TargetAsmParser.h"
using namespace llvm;
-TargetAsmParser::TargetAsmParser(const Target &T)
- : TheTarget(T), AvailableFeatures(0)
+TargetAsmParser::TargetAsmParser()
+ : AvailableFeatures(0)
{
}
Modified: llvm/branches/type-system-rewrite/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/ARM/ARMAsmPrinter.cpp?rev=134726&r1=134725&r2=134726&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/ARM/ARMAsmPrinter.cpp Fri Jul 8 15:11:55 2011
@@ -1069,48 +1069,18 @@
extern cl::opt<bool> EnableARMEHABI;
+// Simple pseudo-instructions have their lowering (with expansion to real
+// instructions) auto-generated.
+#include "ARMGenMCPseudoLowering.inc"
+
void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
- unsigned Opc = MI->getOpcode();
- switch (Opc) {
- default: break;
- case ARM::B: {
- // B is just a Bcc with an 'always' predicate.
- MCInst TmpInst;
- LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
- TmpInst.setOpcode(ARM::Bcc);
- // Add predicate operands.
- TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
- TmpInst.addOperand(MCOperand::CreateReg(0));
- OutStreamer.EmitInstruction(TmpInst);
- return;
- }
- case ARM::LDMIA_RET: {
- // LDMIA_RET is just a normal LDMIA_UPD instruction that targets PC and as
- // such has additional code-gen properties and scheduling information.
- // To emit it, we just construct as normal and set the opcode to LDMIA_UPD.
- MCInst TmpInst;
- LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
- TmpInst.setOpcode(ARM::LDMIA_UPD);
- OutStreamer.EmitInstruction(TmpInst);
- return;
- }
- case ARM::t2LDMIA_RET: {
- // As above for LDMIA_RET. Map to the tPOP instruction.
- MCInst TmpInst;
- LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
- TmpInst.setOpcode(ARM::t2LDMIA_UPD);
- OutStreamer.EmitInstruction(TmpInst);
+ // Do any auto-generated pseudo lowerings.
+ if (emitPseudoExpansionLowering(OutStreamer, MI))
return;
- }
- case ARM::tPOP_RET: {
- // As above for LDMIA_RET. Map to the tPOP instruction.
- MCInst TmpInst;
- LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
- TmpInst.setOpcode(ARM::tPOP);
- OutStreamer.EmitInstruction(TmpInst);
- return;
- }
+ // Check for manual lowerings.
+ unsigned Opc = MI->getOpcode();
+ switch (Opc) {
case ARM::t2MOVi32imm: assert(0 && "Should be lowered by thumb2it pass");
case ARM::DBG_VALUE: {
if (isVerbose() && OutStreamer.hasRawTextSupport()) {
@@ -1121,14 +1091,6 @@
}
return;
}
- case ARM::tBfar: {
- MCInst TmpInst;
- TmpInst.setOpcode(ARM::tBL);
- TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(
- MI->getOperand(0).getMBB()->getSymbol(), OutContext)));
- OutStreamer.EmitInstruction(TmpInst);
- return;
- }
case ARM::LEApcrel:
case ARM::tLEApcrel:
case ARM::t2LEApcrel: {
@@ -1159,39 +1121,8 @@
OutStreamer.EmitInstruction(TmpInst);
return;
}
- case ARM::MOVPCRX: {
- MCInst TmpInst;
- TmpInst.setOpcode(ARM::MOVr);
- TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
- TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
- // Add predicate operands.
- TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
- TmpInst.addOperand(MCOperand::CreateReg(0));
- // Add 's' bit operand (always reg0 for this)
- TmpInst.addOperand(MCOperand::CreateReg(0));
- OutStreamer.EmitInstruction(TmpInst);
- return;
- }
// Darwin call instructions are just normal call instructions with different
// clobber semantics (they clobber R9).
- case ARM::BLr9:
- case ARM::BLr9_pred:
- case ARM::BLXr9:
- case ARM::BLXr9_pred: {
- unsigned newOpc;
- switch (Opc) {
- default: assert(0);
- case ARM::BLr9: newOpc = ARM::BL; break;
- case ARM::BLr9_pred: newOpc = ARM::BL_pred; break;
- case ARM::BLXr9: newOpc = ARM::BLX; break;
- case ARM::BLXr9_pred: newOpc = ARM::BLX_pred; break;
- }
- MCInst TmpInst;
- LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
- TmpInst.setOpcode(newOpc);
- OutStreamer.EmitInstruction(TmpInst);
- return;
- }
case ARM::BXr9_CALL:
case ARM::BX_CALL: {
{
@@ -1870,20 +1801,6 @@
}
// Tail jump branches are really just branch instructions with additional
// code-gen attributes. Convert them to the canonical form here.
- case ARM::TAILJMPd:
- case ARM::TAILJMPdND: {
- MCInst TmpInst, TmpInst2;
- // Lower the instruction as-is to get the operands properly converted.
- LowerARMMachineInstrToMCInst(MI, TmpInst2, *this);
- TmpInst.setOpcode(ARM::Bcc);
- TmpInst.addOperand(TmpInst2.getOperand(0));
- // Add predicate operands.
- TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
- TmpInst.addOperand(MCOperand::CreateReg(0));
- OutStreamer.AddComment("TAILCALL");
- OutStreamer.EmitInstruction(TmpInst);
- return;
- }
case ARM::tTAILJMPd:
case ARM::tTAILJMPdND: {
MCInst TmpInst, TmpInst2;
@@ -1896,14 +1813,10 @@
OutStreamer.EmitInstruction(TmpInst);
return;
}
- case ARM::TAILJMPrND:
case ARM::tTAILJMPrND:
- case ARM::TAILJMPr:
case ARM::tTAILJMPr: {
- unsigned newOpc = (Opc == ARM::TAILJMPr || Opc == ARM::TAILJMPrND)
- ? ARM::BX : ARM::tBX;
MCInst TmpInst;
- TmpInst.setOpcode(newOpc);
+ TmpInst.setOpcode(ARM::tBX);
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
// Predicate.
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
@@ -1912,31 +1825,6 @@
OutStreamer.EmitInstruction(TmpInst);
return;
}
-
- // These are the pseudos created to comply with stricter operand restrictions
- // on ARMv5. Lower them now to "normal" instructions, since all the
- // restrictions are already satisfied.
- case ARM::MULv5:
- EmitPatchedInstruction(MI, ARM::MUL);
- return;
- case ARM::MLAv5:
- EmitPatchedInstruction(MI, ARM::MLA);
- return;
- case ARM::SMULLv5:
- EmitPatchedInstruction(MI, ARM::SMULL);
- return;
- case ARM::UMULLv5:
- EmitPatchedInstruction(MI, ARM::UMULL);
- return;
- case ARM::SMLALv5:
- EmitPatchedInstruction(MI, ARM::SMLAL);
- return;
- case ARM::UMLALv5:
- EmitPatchedInstruction(MI, ARM::UMLAL);
- return;
- case ARM::UMAALv5:
- EmitPatchedInstruction(MI, ARM::UMAAL);
- return;
}
MCInst TmpInst;
Modified: llvm/branches/type-system-rewrite/lib/Target/ARM/ARMAsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/ARM/ARMAsmPrinter.h?rev=134726&r1=134725&r2=134726&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/ARM/ARMAsmPrinter.h (original)
+++ llvm/branches/type-system-rewrite/lib/Target/ARM/ARMAsmPrinter.h Fri Jul 8 15:11:55 2011
@@ -21,6 +21,8 @@
namespace llvm {
+class MCOperand;
+
namespace ARM {
enum DW_ISA {
DW_ISA_ARM_thumb = 1,
@@ -72,6 +74,9 @@
void EmitStartOfAsmFile(Module &M);
void EmitEndOfAsmFile(Module &M);
+ // lowerOperand - Convert a MachineOperand into the equivalent MCOperand.
+ bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp);
+
private:
// Helpers for EmitStartOfAsmFile() and EmitEndOfAsmFile()
void emitAttributes();
@@ -84,6 +89,10 @@
void EmitUnwindingInstruction(const MachineInstr *MI);
+ // emitPseudoExpansionLowering - tblgen'erated.
+ bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
+ const MachineInstr *MI);
+
public:
void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
@@ -100,6 +109,7 @@
llvm::ARM::DW_ISA_ARM_thumb : llvm::ARM::DW_ISA_ARM_arm;
}
+ MCOperand GetSymbolRef(const MachineOperand &MO, const MCSymbol *Symbol);
MCSymbol *GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
const MachineBasicBlock *MBB) const;
MCSymbol *GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const;
@@ -107,7 +117,7 @@
MCSymbol *GetARMSJLJEHLabel(void) const;
MCSymbol *GetARMGVSymbol(const GlobalValue *GV);
-
+
/// EmitMachineConstantPoolValue - Print a machine constantpool value to
/// the .s file.
virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV);
Modified: llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrFormats.td?rev=134726&r1=134725&r2=134726&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrFormats.td Fri Jul 8 15:11:55 2011
@@ -314,6 +314,25 @@
let SZ = sz;
list<Predicate> Predicates = [IsThumb2];
}
+
+class ARMPseudoExpand<dag oops, dag iops, SizeFlagVal sz,
+ InstrItinClass itin, list<dag> pattern,
+ dag Result>
+ : ARMPseudoInst<oops, iops, sz, itin, pattern>,
+ PseudoInstExpansion<Result>;
+
+class tPseudoExpand<dag oops, dag iops, SizeFlagVal sz,
+ InstrItinClass itin, list<dag> pattern,
+ dag Result>
+ : tPseudoInst<oops, iops, sz, itin, pattern>,
+ PseudoInstExpansion<Result>;
+
+class t2PseudoExpand<dag oops, dag iops, SizeFlagVal sz,
+ InstrItinClass itin, list<dag> pattern,
+ dag Result>
+ : t2PseudoInst<oops, iops, sz, itin, pattern>,
+ PseudoInstExpansion<Result>;
+
// Almost all ARM instructions are predicable.
class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
IndexMode im, Format f, InstrItinClass itin,
Modified: llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrInfo.td?rev=134726&r1=134725&r2=134726&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrInfo.td Fri Jul 8 15:11:55 2011
@@ -1363,14 +1363,6 @@
let Inst{27-4} = 0b000100101111111111110001;
let Inst{3-0} = dst;
}
-
- // ARMV4 only
- // FIXME: We would really like to define this as a vanilla ARMPat like:
- // ARMPat<(brind GPR:$dst), (MOVr PC, GPR:$dst)>
- // With that, however, we can't set isBranch, isTerminator, etc..
- def MOVPCRX : ARMPseudoInst<(outs), (ins GPR:$dst),
- Size4Bytes, IIC_Br, [(brind GPR:$dst)]>,
- Requires<[IsARM, NoV4T]>;
}
// All calls clobber the non-callee saved registers. SP is marked as
@@ -1437,24 +1429,29 @@
// moved above / below calls.
Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
Uses = [R7, SP] in {
- def BLr9 : ARMPseudoInst<(outs), (ins bltarget:$func, variable_ops),
+ def BLr9 : ARMPseudoExpand<(outs), (ins bl_target:$func, variable_ops),
Size4Bytes, IIC_Br,
- [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]>;
+ [(ARMcall tglobaladdr:$func)], (BL bl_target:$func)>,
+ Requires<[IsARM, IsDarwin]>;
- def BLr9_pred : ARMPseudoInst<(outs),
- (ins bltarget:$func, pred:$p, variable_ops),
+ def BLr9_pred : ARMPseudoExpand<(outs),
+ (ins bl_target:$func, pred:$p, variable_ops),
Size4Bytes, IIC_Br,
- [(ARMcall_pred tglobaladdr:$func)]>,
+ [(ARMcall_pred tglobaladdr:$func)],
+ (BL_pred bl_target:$func, pred:$p)>,
Requires<[IsARM, IsDarwin]>;
// ARMv5T and above
- def BLXr9 : ARMPseudoInst<(outs), (ins GPR:$func, variable_ops),
+ def BLXr9 : ARMPseudoExpand<(outs), (ins GPR:$func, variable_ops),
Size4Bytes, IIC_Br,
- [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]>;
+ [(ARMcall GPR:$func)],
+ (BLX GPR:$func)>,
+ Requires<[IsARM, HasV5T, IsDarwin]>;
- def BLXr9_pred: ARMPseudoInst<(outs), (ins GPR:$func, pred:$p, variable_ops),
- Size4Bytes, IIC_Br,
- [(ARMcall_pred GPR:$func)]>,
+ def BLXr9_pred: ARMPseudoExpand<(outs), (ins GPR:$func, pred:$p,variable_ops),
+ Size4Bytes, IIC_Br,
+ [(ARMcall_pred GPR:$func)],
+ (BLX_pred GPR:$func, pred:$p)>,
Requires<[IsARM, HasV5T, IsDarwin]>;
// ARMv4T
@@ -1469,6 +1466,65 @@
Requires<[IsARM, NoV4T, IsDarwin]>;
}
+let isBranch = 1, isTerminator = 1 in {
+ // FIXME: should be able to write a pattern for ARMBrcond, but can't use
+ // a two-value operand where a dag node expects two operands. :(
+ def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
+ IIC_Br, "b", "\t$target",
+ [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
+ bits<24> target;
+ let Inst{23-0} = target;
+ }
+
+ let isBarrier = 1 in {
+ // B is "predicable" since it's just a Bcc with an 'always' condition.
+ let isPredicable = 1 in
+ // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
+ // should be sufficient.
+ // FIXME: Is B really a Barrier? That doesn't seem right.
+ def B : ARMPseudoExpand<(outs), (ins br_target:$target), Size4Bytes, IIC_Br,
+ [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>;
+
+ let isNotDuplicable = 1, isIndirectBranch = 1 in {
+ def BR_JTr : ARMPseudoInst<(outs),
+ (ins GPR:$target, i32imm:$jt, i32imm:$id),
+ SizeSpecial, IIC_Br,
+ [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
+ // FIXME: This shouldn't use the generic "addrmode2," but rather be split
+ // into i12 and rs suffixed versions.
+ def BR_JTm : ARMPseudoInst<(outs),
+ (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
+ SizeSpecial, IIC_Br,
+ [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
+ imm:$id)]>;
+ def BR_JTadd : ARMPseudoInst<(outs),
+ (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
+ SizeSpecial, IIC_Br,
+ [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
+ imm:$id)]>;
+ } // isNotDuplicable = 1, isIndirectBranch = 1
+ } // isBarrier = 1
+
+}
+
+// BLX (immediate) -- for disassembly only
+def BLXi : AXI<(outs), (ins br_target:$target), BrMiscFrm, NoItinerary,
+ "blx\t$target", [/* pattern left blank */]>,
+ Requires<[IsARM, HasV5T]> {
+ let Inst{31-25} = 0b1111101;
+ bits<25> target;
+ let Inst{23-0} = target{24-1};
+ let Inst{24} = target{0};
+}
+
+// Branch and Exchange Jazelle -- for disassembly only
+def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
+ [/* For disassembly only; pattern left blank */]> {
+ let Inst{23-20} = 0b0010;
+ //let Inst{19-8} = 0xfff;
+ let Inst{7-4} = 0b0010;
+}
+
// Tail calls.
// FIXME: The Thumb versions of these should live in ARMInstrThumb.td
@@ -1482,17 +1538,19 @@
def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
IIC_Br, []>, Requires<[IsDarwin]>;
- def TAILJMPd : ARMPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
- Size4Bytes, IIC_Br,
- []>, Requires<[IsARM, IsDarwin]>;
+ def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst, variable_ops),
+ Size4Bytes, IIC_Br, [],
+ (Bcc br_target:$dst, (ops 14, zero_reg))>,
+ Requires<[IsARM, IsDarwin]>;
def tTAILJMPd: tPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
Size4Bytes, IIC_Br,
[]>, Requires<[IsThumb, IsDarwin]>;
- def TAILJMPr : ARMPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
- Size4Bytes, IIC_Br,
- []>, Requires<[IsARM, IsDarwin]>;
+ def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
+ Size4Bytes, IIC_Br, [],
+ (BX GPR:$dst)>,
+ Requires<[IsARM, IsDarwin]>;
def tTAILJMPr : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
Size4Bytes, IIC_Br,
@@ -1508,79 +1566,28 @@
def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
IIC_Br, []>, Requires<[IsNotDarwin]>;
- def TAILJMPdND : ARMPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
- Size4Bytes, IIC_Br,
- []>, Requires<[IsARM, IsNotDarwin]>;
+ def TAILJMPdND : ARMPseudoExpand<(outs), (ins brtarget:$dst, variable_ops),
+ Size4Bytes, IIC_Br, [],
+ (Bcc br_target:$dst, (ops 14, zero_reg))>,
+ Requires<[IsARM, IsNotDarwin]>;
def tTAILJMPdND : tPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
Size4Bytes, IIC_Br,
[]>, Requires<[IsThumb, IsNotDarwin]>;
- def TAILJMPrND : ARMPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
- Size4Bytes, IIC_Br,
- []>, Requires<[IsARM, IsNotDarwin]>;
+ def TAILJMPrND : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
+ Size4Bytes, IIC_Br, [],
+ (BX GPR:$dst)>,
+ Requires<[IsARM, IsNotDarwin]>;
def tTAILJMPrND : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
Size4Bytes, IIC_Br,
[]>, Requires<[IsThumb, IsNotDarwin]>;
}
}
-let isBranch = 1, isTerminator = 1 in {
- // B is "predicable" since it's just a Bcc with an 'always' condition.
- let isBarrier = 1 in {
- let isPredicable = 1 in
- // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
- // should be sufficient.
- def B : ARMPseudoInst<(outs), (ins brtarget:$target), Size4Bytes, IIC_Br,
- [(br bb:$target)]>;
-
- let isNotDuplicable = 1, isIndirectBranch = 1 in {
- def BR_JTr : ARMPseudoInst<(outs),
- (ins GPR:$target, i32imm:$jt, i32imm:$id),
- SizeSpecial, IIC_Br,
- [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
- // FIXME: This shouldn't use the generic "addrmode2," but rather be split
- // into i12 and rs suffixed versions.
- def BR_JTm : ARMPseudoInst<(outs),
- (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
- SizeSpecial, IIC_Br,
- [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
- imm:$id)]>;
- def BR_JTadd : ARMPseudoInst<(outs),
- (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
- SizeSpecial, IIC_Br,
- [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
- imm:$id)]>;
- } // isNotDuplicable = 1, isIndirectBranch = 1
- } // isBarrier = 1
- // FIXME: should be able to write a pattern for ARMBrcond, but can't use
- // a two-value operand where a dag node expects two operands. :(
- def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
- IIC_Br, "b", "\t$target",
- [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
- bits<24> target;
- let Inst{23-0} = target;
- }
-}
-// BLX (immediate) -- for disassembly only
-def BLXi : AXI<(outs), (ins br_target:$target), BrMiscFrm, NoItinerary,
- "blx\t$target", [/* pattern left blank */]>,
- Requires<[IsARM, HasV5T]> {
- let Inst{31-25} = 0b1111101;
- bits<25> target;
- let Inst{23-0} = target{24-1};
- let Inst{24} = target{0};
-}
-// Branch and Exchange Jazelle -- for disassembly only
-def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
- [/* For disassembly only; pattern left blank */]> {
- let Inst{23-20} = 0b0010;
- //let Inst{19-8} = 0xfff;
- let Inst{7-4} = 0b0010;
-}
// Secure Monitor Call is a system instruction -- for disassembly only
def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
@@ -2030,9 +2037,10 @@
// FIXME: Should pc be an implicit operand like PICADD, etc?
let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
-def LDMIA_RET : ARMPseudoInst<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
- reglist:$regs, variable_ops),
- Size4Bytes, IIC_iLoad_mBr, []>,
+def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
+ reglist:$regs, variable_ops),
+ Size4Bytes, IIC_iLoad_mBr, [],
+ (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
RegConstraint<"$Rn = $wb">;
//===----------------------------------------------------------------------===//
@@ -2690,28 +2698,26 @@
let Inst{3-0} = Rn;
}
+// FIXME: The v5 pseudos are only necessary for the additional Constraint
+// property. Remove them when it's possible to add those properties
+// on an individual MachineInstr, not just an instuction description.
let isCommutable = 1 in {
-let Constraints = "@earlyclobber $Rd" in
-def MULv5: ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
- pred:$p, cc_out:$s),
- Size4Bytes, IIC_iMUL32,
- [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
- Requires<[IsARM, NoV6]>;
-
def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
[(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
Requires<[IsARM, HasV6]> {
let Inst{15-12} = 0b0000;
}
-}
let Constraints = "@earlyclobber $Rd" in
-def MLAv5: ARMPseudoInst<(outs GPR:$Rd),
- (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
- Size4Bytes, IIC_iMAC32,
- [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
+def MULv5: ARMPseudoExpand<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
+ pred:$p, cc_out:$s),
+ Size4Bytes, IIC_iMUL32,
+ [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))],
+ (MUL GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
Requires<[IsARM, NoV6]>;
+}
+
def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
[(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
@@ -2720,6 +2726,14 @@
let Inst{15-12} = Ra;
}
+let Constraints = "@earlyclobber $Rd" in
+def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
+ (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
+ Size4Bytes, IIC_iMAC32,
+ [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
+ (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
+ Requires<[IsARM, NoV6]>;
+
def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
[(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
@@ -2735,49 +2749,34 @@
}
// Extra precision multiplies with low / high results
-
let neverHasSideEffects = 1 in {
let isCommutable = 1 in {
-let Constraints = "@earlyclobber $RdLo, at earlyclobber $RdHi" in {
-def SMULLv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
- (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
- Size4Bytes, IIC_iMUL64, []>,
- Requires<[IsARM, NoV6]>;
-
-def UMULLv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
- (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
- Size4Bytes, IIC_iMUL64, []>,
- Requires<[IsARM, NoV6]>;
-}
-
def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
- (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
+ (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
"smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
Requires<[IsARM, HasV6]>;
def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
- (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
+ (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
"umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
Requires<[IsARM, HasV6]>;
-}
-// Multiply + accumulate
let Constraints = "@earlyclobber $RdLo, at earlyclobber $RdHi" in {
-def SMLALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
+def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
(ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
- Size4Bytes, IIC_iMAC64, []>,
+ Size4Bytes, IIC_iMUL64, [],
+ (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
Requires<[IsARM, NoV6]>;
-def UMLALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
- (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
- Size4Bytes, IIC_iMAC64, []>,
- Requires<[IsARM, NoV6]>;
-def UMAALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
+
+def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
(ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
- Size4Bytes, IIC_iMAC64, []>,
+ Size4Bytes, IIC_iMUL64, [],
+ (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
Requires<[IsARM, NoV6]>;
-
+}
}
+// Multiply + accumulate
def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
(ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
"smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
@@ -2800,6 +2799,25 @@
let Inst{11-8} = Rm;
let Inst{3-0} = Rn;
}
+
+let Constraints = "@earlyclobber $RdLo, at earlyclobber $RdHi" in {
+def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
+ (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
+ Size4Bytes, IIC_iMAC64, [],
+ (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
+ Requires<[IsARM, NoV6]>;
+def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
+ (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
+ Size4Bytes, IIC_iMAC64, [],
+ (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
+ Requires<[IsARM, NoV6]>;
+def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
+ (ins GPR:$Rn, GPR:$Rm, pred:$p),
+ Size4Bytes, IIC_iMAC64, [],
+ (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
+ Requires<[IsARM, NoV6]>;
+}
+
} // neverHasSideEffects
// Most significant word multiply
@@ -3838,6 +3856,13 @@
// Non-Instruction Patterns
//
+// ARMv4 indirect branch using (MOVr PC, dst)
+let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
+ def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
+ Size4Bytes, IIC_Br, [(brind GPR:$dst)],
+ (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
+ Requires<[IsARM, NoV4T]>;
+
// Large immediate handling.
// 32-bit immediate using two piece so_imms or movw + movt.
Modified: llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrThumb.td?rev=134726&r1=134725&r2=134726&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrThumb.td Fri Jul 8 15:11:55 2011
@@ -405,12 +405,6 @@
}
}
-// FIXME: remove when we have a way to marking a MI with these properties.
-let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
- hasExtraDefRegAllocReq = 1 in
-def tPOP_RET : tPseudoInst<(outs), (ins pred:$p, reglist:$regs, variable_ops),
- Size2Bytes, IIC_iPop_Br, []>;
-
// All calls clobber the non-callee saved registers. SP is marked as a use to
// prevent stack-pointer assignments that appear immediately before calls from
// potentially appearing dead.
@@ -528,8 +522,8 @@
// Just a pseudo for a tBL instruction. Needed to let regalloc know about
// the clobber of LR.
let Defs = [LR] in
- def tBfar : tPseudoInst<(outs), (ins t_bltarget:$target),
- Size4Bytes, IIC_Br, []>;
+ def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target),
+ Size4Bytes, IIC_Br, [], (tBL t_bltarget:$target)>;
def tBR_JTr : tPseudoInst<(outs),
(ins tGPR:$target, i32imm:$jt, i32imm:$id),
@@ -1477,3 +1471,12 @@
[(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
imm:$cp))]>,
Requires<[IsThumb, IsThumb1Only]>;
+
+// Pseudo-instruction for merged POP and return.
+// FIXME: remove when we have a way to marking a MI with these properties.
+let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
+ hasExtraDefRegAllocReq = 1 in
+def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
+ Size2Bytes, IIC_iPop_Br, [],
+ (tPOP pred:$p, reglist:$regs)>;
+
Modified: llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrThumb2.td?rev=134726&r1=134725&r2=134726&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrThumb2.td Fri Jul 8 15:11:55 2011
@@ -2978,9 +2978,10 @@
// FIXME: Should pc be an implicit operand like PICADD, etc?
let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
-def t2LDMIA_RET: t2PseudoInst<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
+def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
reglist:$regs, variable_ops),
- Size4Bytes, IIC_iLoad_mBr, []>,
+ Size4Bytes, IIC_iLoad_mBr, [],
+ (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
RegConstraint<"$Rn = $wb">;
let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
Modified: llvm/branches/type-system-rewrite/lib/Target/ARM/ARMMCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/ARM/ARMMCInstLower.cpp?rev=134726&r1=134725&r2=134726&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/ARM/ARMMCInstLower.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/ARM/ARMMCInstLower.cpp Fri Jul 8 15:11:55 2011
@@ -23,43 +23,94 @@
using namespace llvm;
-static MCOperand GetSymbolRef(const MachineOperand &MO, const MCSymbol *Symbol,
- ARMAsmPrinter &Printer) {
- MCContext &Ctx = Printer.OutContext;
+MCOperand ARMAsmPrinter::GetSymbolRef(const MachineOperand &MO,
+ const MCSymbol *Symbol) {
const MCExpr *Expr;
switch (MO.getTargetFlags()) {
default: {
- Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None, Ctx);
+ Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None,
+ OutContext);
switch (MO.getTargetFlags()) {
default:
assert(0 && "Unknown target flag on symbol operand");
case 0:
break;
case ARMII::MO_LO16:
- Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None, Ctx);
- Expr = ARMMCExpr::CreateLower16(Expr, Ctx);
+ Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None,
+ OutContext);
+ Expr = ARMMCExpr::CreateLower16(Expr, OutContext);
break;
case ARMII::MO_HI16:
- Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None, Ctx);
- Expr = ARMMCExpr::CreateUpper16(Expr, Ctx);
+ Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None,
+ OutContext);
+ Expr = ARMMCExpr::CreateUpper16(Expr, OutContext);
break;
}
break;
}
case ARMII::MO_PLT:
- Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_ARM_PLT, Ctx);
+ Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_ARM_PLT,
+ OutContext);
break;
}
if (!MO.isJTI() && MO.getOffset())
Expr = MCBinaryExpr::CreateAdd(Expr,
- MCConstantExpr::Create(MO.getOffset(), Ctx),
- Ctx);
+ MCConstantExpr::Create(MO.getOffset(),
+ OutContext),
+ OutContext);
return MCOperand::CreateExpr(Expr);
}
+bool ARMAsmPrinter::lowerOperand(const MachineOperand &MO,
+ MCOperand &MCOp) {
+ switch (MO.getType()) {
+ default:
+ assert(0 && "unknown operand type");
+ return false;
+ case MachineOperand::MO_Register:
+ // Ignore all non-CPSR implicit register operands.
+ if (MO.isImplicit() && MO.getReg() != ARM::CPSR)
+ return false;
+ assert(!MO.getSubReg() && "Subregs should be eliminated!");
+ MCOp = MCOperand::CreateReg(MO.getReg());
+ break;
+ case MachineOperand::MO_Immediate:
+ MCOp = MCOperand::CreateImm(MO.getImm());
+ break;
+ case MachineOperand::MO_MachineBasicBlock:
+ MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
+ MO.getMBB()->getSymbol(), OutContext));
+ break;
+ case MachineOperand::MO_GlobalAddress:
+ MCOp = GetSymbolRef(MO, Mang->getSymbol(MO.getGlobal()));
+ break;
+ case MachineOperand::MO_ExternalSymbol:
+ MCOp = GetSymbolRef(MO,
+ GetExternalSymbolSymbol(MO.getSymbolName()));
+ break;
+ case MachineOperand::MO_JumpTableIndex:
+ MCOp = GetSymbolRef(MO, GetJTISymbol(MO.getIndex()));
+ break;
+ case MachineOperand::MO_ConstantPoolIndex:
+ MCOp = GetSymbolRef(MO, GetCPISymbol(MO.getIndex()));
+ break;
+ case MachineOperand::MO_BlockAddress:
+ MCOp = GetSymbolRef(MO, GetBlockAddressSymbol(MO.getBlockAddress()));
+ break;
+ case MachineOperand::MO_FPImmediate: {
+ APFloat Val = MO.getFPImm()->getValueAPF();
+ bool ignored;
+ Val.convert(APFloat::IEEEdouble, APFloat::rmTowardZero, &ignored);
+ MCOp = MCOperand::CreateFPImm(Val.convertToDouble());
+ break;
+ }
+ }
+ return true;
+}
+
void llvm::LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
ARMAsmPrinter &AP) {
OutMI.setOpcode(MI->getOpcode());
@@ -68,48 +119,7 @@
const MachineOperand &MO = MI->getOperand(i);
MCOperand MCOp;
- switch (MO.getType()) {
- default:
- MI->dump();
- assert(0 && "unknown operand type");
- case MachineOperand::MO_Register:
- // Ignore all non-CPSR implicit register operands.
- if (MO.isImplicit() && MO.getReg() != ARM::CPSR) continue;
- assert(!MO.getSubReg() && "Subregs should be eliminated!");
- MCOp = MCOperand::CreateReg(MO.getReg());
- break;
- case MachineOperand::MO_Immediate:
- MCOp = MCOperand::CreateImm(MO.getImm());
- break;
- case MachineOperand::MO_MachineBasicBlock:
- MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
- MO.getMBB()->getSymbol(), AP.OutContext));
- break;
- case MachineOperand::MO_GlobalAddress:
- MCOp = GetSymbolRef(MO, AP.Mang->getSymbol(MO.getGlobal()), AP);
- break;
- case MachineOperand::MO_ExternalSymbol:
- MCOp = GetSymbolRef(MO,
- AP.GetExternalSymbolSymbol(MO.getSymbolName()), AP);
- break;
- case MachineOperand::MO_JumpTableIndex:
- MCOp = GetSymbolRef(MO, AP.GetJTISymbol(MO.getIndex()), AP);
- break;
- case MachineOperand::MO_ConstantPoolIndex:
- MCOp = GetSymbolRef(MO, AP.GetCPISymbol(MO.getIndex()), AP);
- break;
- case MachineOperand::MO_BlockAddress:
- MCOp = GetSymbolRef(MO,AP.GetBlockAddressSymbol(MO.getBlockAddress()),AP);
- break;
- case MachineOperand::MO_FPImmediate: {
- APFloat Val = MO.getFPImm()->getValueAPF();
- bool ignored;
- Val.convert(APFloat::IEEEdouble, APFloat::rmTowardZero, &ignored);
- MCOp = MCOperand::CreateFPImm(Val.convertToDouble());
- break;
- }
- }
-
- OutMI.addOperand(MCOp);
+ if (AP.lowerOperand(MO, MCOp))
+ OutMI.addOperand(MCOp);
}
}
Modified: llvm/branches/type-system-rewrite/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=134726&r1=134725&r2=134726&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Jul 8 15:11:55 2011
@@ -41,7 +41,7 @@
class ARMAsmParser : public TargetAsmParser {
MCAsmParser &Parser;
- MCSubtargetInfo *STI;
+ const MCSubtargetInfo *STI;
MCAsmParser &getParser() const { return Parser; }
MCAsmLexer &getLexer() const { return Parser.getLexer(); }
@@ -127,9 +127,8 @@
const SmallVectorImpl<MCParsedAsmOperand*> &);
public:
- ARMAsmParser(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
- MCAsmParser &_Parser)
- : TargetAsmParser(T), Parser(_Parser) {
+ ARMAsmParser(StringRef TT, StringRef CPU, StringRef FS, MCAsmParser &_Parser)
+ : TargetAsmParser(), Parser(_Parser) {
STI = ARM_MC::createARMMCSubtargetInfo(TT, CPU, FS);
MCAsmParserExtension::Initialize(_Parser);
Modified: llvm/branches/type-system-rewrite/lib/Target/ARM/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/ARM/CMakeLists.txt?rev=134726&r1=134725&r2=134726&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/ARM/CMakeLists.txt (original)
+++ llvm/branches/type-system-rewrite/lib/Target/ARM/CMakeLists.txt Fri Jul 8 15:11:55 2011
@@ -4,6 +4,7 @@
tablegen(ARMGenInstrInfo.inc -gen-instr-info)
tablegen(ARMGenCodeEmitter.inc -gen-emitter)
tablegen(ARMGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
+tablegen(ARMGenMCPseudoLowering.inc -gen-pseudo-lowering)
tablegen(ARMGenAsmWriter.inc -gen-asm-writer)
tablegen(ARMGenAsmMatcher.inc -gen-asm-matcher)
tablegen(ARMGenDAGISel.inc -gen-dag-isel)
Modified: llvm/branches/type-system-rewrite/lib/Target/ARM/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/ARM/Makefile?rev=134726&r1=134725&r2=134726&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/ARM/Makefile (original)
+++ llvm/branches/type-system-rewrite/lib/Target/ARM/Makefile Fri Jul 8 15:11:55 2011
@@ -17,7 +17,8 @@
ARMGenDAGISel.inc ARMGenSubtargetInfo.inc \
ARMGenCodeEmitter.inc ARMGenCallingConv.inc \
ARMGenDecoderTables.inc ARMGenEDInfo.inc \
- ARMGenFastISel.inc ARMGenMCCodeEmitter.inc
+ ARMGenFastISel.inc ARMGenMCCodeEmitter.inc \
+ ARMGenMCPseudoLowering.inc
DIRS = InstPrinter AsmParser Disassembler TargetInfo MCTargetDesc
Modified: llvm/branches/type-system-rewrite/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp?rev=134726&r1=134725&r2=134726&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp Fri Jul 8 15:11:55 2011
@@ -63,9 +63,9 @@
public:
- MBlazeAsmParser(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
+ MBlazeAsmParser(StringRef TT, StringRef CPU, StringRef FS,
MCAsmParser &_Parser)
- : TargetAsmParser(T), Parser(_Parser) {}
+ : TargetAsmParser(), Parser(_Parser) {}
virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands);
Modified: llvm/branches/type-system-rewrite/lib/Target/X86/AsmParser/X86AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=134726&r1=134725&r2=134726&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/X86/AsmParser/X86AsmParser.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/X86/AsmParser/X86AsmParser.cpp Fri Jul 8 15:11:55 2011
@@ -37,7 +37,7 @@
class X86ATTAsmParser : public TargetAsmParser {
MCAsmParser &Parser;
- MCSubtargetInfo *STI;
+ const MCSubtargetInfo *STI;
private:
MCAsmParser &getParser() const { return Parser; }
@@ -77,9 +77,9 @@
/// }
public:
- X86ATTAsmParser(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
+ X86ATTAsmParser(StringRef TT, StringRef CPU, StringRef FS,
MCAsmParser &parser)
- : TargetAsmParser(T), Parser(parser) {
+ : TargetAsmParser(), Parser(parser) {
STI = X86_MC::createX86MCSubtargetInfo(TT, CPU, FS);
// Initialize the set of available features.
Modified: llvm/branches/type-system-rewrite/lib/Transforms/Utils/CloneFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Transforms/Utils/CloneFunction.cpp?rev=134726&r1=134725&r2=134726&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Transforms/Utils/CloneFunction.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Transforms/Utils/CloneFunction.cpp Fri Jul 8 15:11:55 2011
@@ -342,18 +342,6 @@
Ops.size(), TD);
}
-static DebugLoc
-UpdateInlinedAtInfo(const DebugLoc &InsnDL, const DebugLoc &TheCallDL,
- LLVMContext &Ctx) {
- DebugLoc NewLoc = TheCallDL;
- if (MDNode *IA = InsnDL.getInlinedAt(Ctx))
- NewLoc = UpdateInlinedAtInfo(DebugLoc::getFromDILocation(IA), TheCallDL,
- Ctx);
-
- return DebugLoc::get(InsnDL.getLine(), InsnDL.getCol(),
- InsnDL.getScope(Ctx), NewLoc.getAsMDNode(Ctx));
-}
-
/// CloneAndPruneFunctionInto - This works exactly like CloneFunctionInto,
/// except that it does some simple constant prop and DCE on the fly. The
/// effect of this is to copy significantly less code in cases where (for
@@ -418,50 +406,14 @@
if (PHINode *PN = dyn_cast<PHINode>(I)) {
// Skip over all PHI nodes, remembering them for later.
BasicBlock::const_iterator OldI = BI->begin();
- for (; (PN = dyn_cast<PHINode>(I)); ++I, ++OldI) {
- if (I->hasMetadata()) {
- if (!TheCallDL.isUnknown()) {
- DebugLoc IDL = I->getDebugLoc();
- if (!IDL.isUnknown()) {
- DebugLoc NewDL = UpdateInlinedAtInfo(IDL, TheCallDL,
- I->getContext());
- I->setDebugLoc(NewDL);
- }
- } else {
- // The cloned instruction has dbg info but the call instruction
- // does not have dbg info. Remove dbg info from cloned instruction.
- I->setDebugLoc(DebugLoc());
- }
- }
+ for (; (PN = dyn_cast<PHINode>(I)); ++I, ++OldI)
PHIToResolve.push_back(cast<PHINode>(OldI));
- }
}
- // FIXME:
- // FIXME:
- // FIXME: Unclone all this metadata stuff.
- // FIXME:
- // FIXME:
-
// Otherwise, remap the rest of the instructions normally.
- for (; I != NewBB->end(); ++I) {
- if (I->hasMetadata()) {
- if (!TheCallDL.isUnknown()) {
- DebugLoc IDL = I->getDebugLoc();
- if (!IDL.isUnknown()) {
- DebugLoc NewDL = UpdateInlinedAtInfo(IDL, TheCallDL,
- I->getContext());
- I->setDebugLoc(NewDL);
- }
- } else {
- // The cloned instruction has dbg info but the call instruction
- // does not have dbg info. Remove dbg info from cloned instruction.
- I->setDebugLoc(DebugLoc());
- }
- }
+ for (; I != NewBB->end(); ++I)
RemapInstruction(I, VMap,
ModuleLevelChanges ? RF_None : RF_NoModuleLevelChanges);
- }
}
// Defer PHI resolution until rest of function is resolved, PHI resolution
Modified: llvm/branches/type-system-rewrite/lib/Transforms/Utils/InlineFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Transforms/Utils/InlineFunction.cpp?rev=134726&r1=134725&r2=134726&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Transforms/Utils/InlineFunction.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Transforms/Utils/InlineFunction.cpp Fri Jul 8 15:11:55 2011
@@ -744,6 +744,41 @@
return false;
}
+/// updateInlinedAtInfo - Helper function used by fixupLineNumbers to recursively
+/// update InlinedAtEntry of a DebugLoc.
+static DebugLoc updateInlinedAtInfo(const DebugLoc &DL,
+ const DebugLoc &InlinedAtDL,
+ LLVMContext &Ctx) {
+ if (MDNode *IA = DL.getInlinedAt(Ctx)) {
+ DebugLoc NewInlinedAtDL
+ = updateInlinedAtInfo(DebugLoc::getFromDILocation(IA), InlinedAtDL, Ctx);
+ return DebugLoc::get(DL.getLine(), DL.getCol(), DL.getScope(Ctx),
+ NewInlinedAtDL.getAsMDNode(Ctx));
+ }
+
+ return DebugLoc::get(DL.getLine(), DL.getCol(), DL.getScope(Ctx),
+ InlinedAtDL.getAsMDNode(Ctx));
+}
+
+
+/// fixupLineNumbers - Update inlined instructions' line numbers to
+/// to encode location where these instructions are inlined.
+static void fixupLineNumbers(Function *Fn, Function::iterator FI,
+ Instruction *TheCall) {
+ DebugLoc TheCallDL = TheCall->getDebugLoc();
+ if (TheCallDL.isUnknown())
+ return;
+
+ for (; FI != Fn->end(); ++FI) {
+ for (BasicBlock::iterator BI = FI->begin(), BE = FI->end();
+ BI != BE; ++BI) {
+ DebugLoc DL = BI->getDebugLoc();
+ if (!DL.isUnknown())
+ BI->setDebugLoc(updateInlinedAtInfo(DL, TheCallDL, BI->getContext()));
+ }
+ }
+}
+
// InlineFunction - This function inlines the called function into the basic
// block of the caller. This returns false if it is not possible to inline this
// call. The program is still in a well defined state if this occurs though.
@@ -846,6 +881,9 @@
// Update the callgraph if requested.
if (IFI.CG)
UpdateCallGraphAfterInlining(CS, FirstNewBlock, VMap, IFI);
+
+ // Update inlined instructions' line number information.
+ fixupLineNumbers(Caller, FirstNewBlock, TheCall);
}
// If there are any alloca instructions in the block that used to be the entry
Modified: llvm/branches/type-system-rewrite/test/CodeGen/ARM/call-tc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/ARM/call-tc.ll?rev=134726&r1=134725&r2=134726&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/ARM/call-tc.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/ARM/call-tc.ll Fri Jul 8 15:11:55 2011
@@ -15,11 +15,11 @@
define void @t2() {
; CHECKV6: t2:
-; CHECKV6: bx r0 @ TAILCALL
+; CHECKV6: bx r0
; CHECKT2D: t2:
; CHECKT2D: ldr
; CHECKT2D-NEXT: ldr
-; CHECKT2D-NEXT: bx r0 @ TAILCALL
+; CHECKT2D-NEXT: bx r0
%tmp = load i32 ()** @t ; <i32 ()*> [#uses=1]
%tmp.upgrd.2 = tail call i32 %tmp( ) ; <i32> [#uses=0]
ret void
@@ -27,11 +27,11 @@
define void @t3() {
; CHECKV6: t3:
-; CHECKV6: b _t2 @ TAILCALL
+; CHECKV6: b _t2
; CHECKELF: t3:
-; CHECKELF: b t2(PLT) @ TAILCALL
+; CHECKELF: b t2(PLT)
; CHECKT2D: t3:
-; CHECKT2D: b.w _t2 @ TAILCALL
+; CHECKT2D: b.w _t2
tail call void @t2( ) ; <i32> [#uses=0]
ret void
@@ -41,9 +41,9 @@
define double @t4(double %a) nounwind readonly ssp {
entry:
; CHECKV6: t4:
-; CHECKV6: b _sin @ TAILCALL
+; CHECKV6: b _sin
; CHECKELF: t4:
-; CHECKELF: b sin(PLT) @ TAILCALL
+; CHECKELF: b sin(PLT)
%0 = tail call double @sin(double %a) nounwind readonly ; <double> [#uses=1]
ret double %0
}
@@ -51,9 +51,9 @@
define float @t5(float %a) nounwind readonly ssp {
entry:
; CHECKV6: t5:
-; CHECKV6: b _sinf @ TAILCALL
+; CHECKV6: b _sinf
; CHECKELF: t5:
-; CHECKELF: b sinf(PLT) @ TAILCALL
+; CHECKELF: b sinf(PLT)
%0 = tail call float @sinf(float %a) nounwind readonly ; <float> [#uses=1]
ret float %0
}
@@ -65,9 +65,9 @@
define i32 @t6(i32 %a, i32 %b) nounwind readnone {
entry:
; CHECKV6: t6:
-; CHECKV6: b ___divsi3 @ TAILCALL
+; CHECKV6: b ___divsi3
; CHECKELF: t6:
-; CHECKELF: b __aeabi_idiv(PLT) @ TAILCALL
+; CHECKELF: b __aeabi_idiv(PLT)
%0 = sdiv i32 %a, %b
ret i32 %0
}
Modified: llvm/branches/type-system-rewrite/utils/TableGen/AsmMatcherEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/utils/TableGen/AsmMatcherEmitter.cpp?rev=134726&r1=134725&r2=134726&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/utils/TableGen/AsmMatcherEmitter.cpp (original)
+++ llvm/branches/type-system-rewrite/utils/TableGen/AsmMatcherEmitter.cpp Fri Jul 8 15:11:55 2011
@@ -1153,7 +1153,7 @@
assert(FeatureNo < 32 && "Too many subtarget features!");
}
- StringRef CommentDelimiter = AsmParser->getValueAsString("CommentDelimiter");
+ std::string CommentDelimiter = AsmParser->getValueAsString("CommentDelimiter");
// Parse the instructions; we need to do this first so that we can gather the
// singleton register classes.
@@ -1825,7 +1825,8 @@
SubtargetFeatureInfo &SFI = *it->second;
OS << " if (";
- StringRef Conds = SFI.TheDef->getValueAsString("AssemblerCondString");
+ std::string CondStorage = SFI.TheDef->getValueAsString("AssemblerCondString");
+ StringRef Conds = CondStorage;
std::pair<StringRef,StringRef> Comma = Conds.split(',');
bool First = true;
do {
Modified: llvm/branches/type-system-rewrite/utils/TableGen/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/utils/TableGen/CMakeLists.txt?rev=134726&r1=134725&r2=134726&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/utils/TableGen/CMakeLists.txt (original)
+++ llvm/branches/type-system-rewrite/utils/TableGen/CMakeLists.txt Fri Jul 8 15:11:55 2011
@@ -34,6 +34,7 @@
LLVMCConfigurationEmitter.cpp
NeonEmitter.cpp
OptParserEmitter.cpp
+ PseudoLoweringEmitter.cpp
Record.cpp
RegisterInfoEmitter.cpp
SetTheory.cpp
Modified: llvm/branches/type-system-rewrite/utils/TableGen/TableGen.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/utils/TableGen/TableGen.cpp?rev=134726&r1=134725&r2=134726&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/utils/TableGen/TableGen.cpp (original)
+++ llvm/branches/type-system-rewrite/utils/TableGen/TableGen.cpp Fri Jul 8 15:11:55 2011
@@ -33,6 +33,7 @@
#include "LLVMCConfigurationEmitter.h"
#include "NeonEmitter.h"
#include "OptParserEmitter.h"
+#include "PseudoLoweringEmitter.h"
#include "Record.h"
#include "RegisterInfoEmitter.h"
#include "ARMDecoderEmitter.h"
@@ -59,6 +60,7 @@
GenAsmMatcher,
GenARMDecoder,
GenDisassembler,
+ GenPseudoLowering,
GenCallingConv,
GenClangAttrClasses,
GenClangAttrImpl,
@@ -106,6 +108,8 @@
"Generate decoders for ARM/Thumb"),
clEnumValN(GenDisassembler, "gen-disassembler",
"Generate disassembler"),
+ clEnumValN(GenPseudoLowering, "gen-pseudo-lowering",
+ "Generate pseudo instruction lowering"),
clEnumValN(GenAsmMatcher, "gen-asm-matcher",
"Generate assembly instruction matcher"),
clEnumValN(GenDAGISel, "gen-dag-isel",
@@ -314,6 +318,9 @@
case GenDisassembler:
DisassemblerEmitter(Records).run(Out.os());
break;
+ case GenPseudoLowering:
+ PseudoLoweringEmitter(Records).run(Out.os());
+ break;
case GenOptParserDefs:
OptParserEmitter(Records, true).run(Out.os());
break;
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