[llvm-branch-commits] [llvm-branch] r134684 - in /llvm/branches/type-system-rewrite: ./ cmake/modules/ docs/ include/llvm/ include/llvm/ADT/ include/llvm/CodeGen/ include/llvm/MC/ include/llvm/Object/ include/llvm/Support/ include/llvm/Target/ include/llvm/Transforms/ include/llvm/Transforms/Utils/ lib/Analysis/ lib/Bitcode/Reader/ lib/CodeGen/ lib/CodeGen/AsmPrinter/ lib/CodeGen/SelectionDAG/ lib/MC/ lib/MC/MCDisassembler/ lib/Object/ lib/Support/ lib/Support/Unix/ lib/Target/ lib/Target/ARM/ lib/Target/ARM/AsmParser/ lib/Ta...
Chris Lattner
sabre at nondot.org
Thu Jul 7 21:45:16 PDT 2011
Author: lattner
Date: Thu Jul 7 23:45:15 2011
New Revision: 134684
URL: http://llvm.org/viewvc/llvm-project?rev=134684&view=rev
Log:
Merging r134364 through r134683 from mainline to the branch.
Added:
llvm/branches/type-system-rewrite/docs/BranchWeightMetadata.html
- copied unchanged from r134683, llvm/trunk/docs/BranchWeightMetadata.html
llvm/branches/type-system-rewrite/lib/Target/ARM/MCTargetDesc/
- copied from r134683, llvm/trunk/lib/Target/ARM/MCTargetDesc/
llvm/branches/type-system-rewrite/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
- copied unchanged from r134683, llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
llvm/branches/type-system-rewrite/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
- copied unchanged from r134683, llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
llvm/branches/type-system-rewrite/lib/Target/ARM/MCTargetDesc/CMakeLists.txt
- copied unchanged from r134683, llvm/trunk/lib/Target/ARM/MCTargetDesc/CMakeLists.txt
llvm/branches/type-system-rewrite/lib/Target/ARM/MCTargetDesc/Makefile
- copied unchanged from r134683, llvm/trunk/lib/Target/ARM/MCTargetDesc/Makefile
llvm/branches/type-system-rewrite/lib/Target/Mips/InstPrinter/
- copied from r134683, llvm/trunk/lib/Target/Mips/InstPrinter/
llvm/branches/type-system-rewrite/lib/Target/Mips/InstPrinter/CMakeLists.txt
- copied unchanged from r134683, llvm/trunk/lib/Target/Mips/InstPrinter/CMakeLists.txt
llvm/branches/type-system-rewrite/lib/Target/Mips/InstPrinter/Makefile
- copied unchanged from r134683, llvm/trunk/lib/Target/Mips/InstPrinter/Makefile
llvm/branches/type-system-rewrite/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp
- copied unchanged from r134683, llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp
llvm/branches/type-system-rewrite/lib/Target/Mips/InstPrinter/MipsInstPrinter.h
- copied unchanged from r134683, llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.h
llvm/branches/type-system-rewrite/lib/Target/Mips/MipsAsmPrinter.h
- copied unchanged from r134683, llvm/trunk/lib/Target/Mips/MipsAsmPrinter.h
llvm/branches/type-system-rewrite/lib/Target/Mips/MipsMCInstLower.cpp
- copied unchanged from r134683, llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp
llvm/branches/type-system-rewrite/lib/Target/Mips/MipsMCInstLower.h
- copied unchanged from r134683, llvm/trunk/lib/Target/Mips/MipsMCInstLower.h
llvm/branches/type-system-rewrite/lib/Target/Mips/MipsMCSymbolRefExpr.cpp
- copied unchanged from r134683, llvm/trunk/lib/Target/Mips/MipsMCSymbolRefExpr.cpp
llvm/branches/type-system-rewrite/lib/Target/Mips/MipsMCSymbolRefExpr.h
- copied unchanged from r134683, llvm/trunk/lib/Target/Mips/MipsMCSymbolRefExpr.h
llvm/branches/type-system-rewrite/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
- copied unchanged from r134683, llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
llvm/branches/type-system-rewrite/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
- copied unchanged from r134683, llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
llvm/branches/type-system-rewrite/lib/Transforms/Utils/LowerExpectIntrinsic.cpp
- copied unchanged from r134683, llvm/trunk/lib/Transforms/Utils/LowerExpectIntrinsic.cpp
llvm/branches/type-system-rewrite/test/CodeGen/Generic/2011-07-07-ScheduleDAGCrash.ll
- copied unchanged from r134683, llvm/trunk/test/CodeGen/Generic/2011-07-07-ScheduleDAGCrash.ll
llvm/branches/type-system-rewrite/test/CodeGen/Generic/builtin-expect.ll
- copied unchanged from r134683, llvm/trunk/test/CodeGen/Generic/builtin-expect.ll
llvm/branches/type-system-rewrite/test/CodeGen/X86/membarrier.ll
- copied unchanged from r134683, llvm/trunk/test/CodeGen/X86/membarrier.ll
llvm/branches/type-system-rewrite/test/Transforms/GVN/2011-07-07-MatchIntrinsicExtract.ll
- copied unchanged from r134683, llvm/trunk/test/Transforms/GVN/2011-07-07-MatchIntrinsicExtract.ll
llvm/branches/type-system-rewrite/test/Transforms/LICM/2011-07-06-Alignment.ll
- copied unchanged from r134683, llvm/trunk/test/Transforms/LICM/2011-07-06-Alignment.ll
llvm/branches/type-system-rewrite/test/Transforms/LowerExpectIntrinsic/
- copied from r134683, llvm/trunk/test/Transforms/LowerExpectIntrinsic/
llvm/branches/type-system-rewrite/test/Transforms/LowerExpectIntrinsic/basic.ll
- copied unchanged from r134683, llvm/trunk/test/Transforms/LowerExpectIntrinsic/basic.ll
llvm/branches/type-system-rewrite/test/Transforms/LowerExpectIntrinsic/dg.exp
- copied unchanged from r134683, llvm/trunk/test/Transforms/LowerExpectIntrinsic/dg.exp
Removed:
llvm/branches/type-system-rewrite/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp
llvm/branches/type-system-rewrite/lib/Target/X86/MCTargetDesc/X86TargetDesc.h
llvm/branches/type-system-rewrite/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll
Modified:
llvm/branches/type-system-rewrite/ (props changed)
llvm/branches/type-system-rewrite/cmake/modules/LLVMLibDeps.cmake
llvm/branches/type-system-rewrite/docs/index.html
llvm/branches/type-system-rewrite/include/llvm/ADT/ImmutableList.h
llvm/branches/type-system-rewrite/include/llvm/ADT/SmallVector.h
llvm/branches/type-system-rewrite/include/llvm/CodeGen/SelectionDAGNodes.h
llvm/branches/type-system-rewrite/include/llvm/InitializePasses.h
llvm/branches/type-system-rewrite/include/llvm/Intrinsics.td
llvm/branches/type-system-rewrite/include/llvm/LLVMContext.h
llvm/branches/type-system-rewrite/include/llvm/LinkAllPasses.h
llvm/branches/type-system-rewrite/include/llvm/MC/MCAsmInfo.h
llvm/branches/type-system-rewrite/include/llvm/MC/MCSubtargetInfo.h
llvm/branches/type-system-rewrite/include/llvm/Object/ObjectFile.h
llvm/branches/type-system-rewrite/include/llvm/Support/CFG.h
llvm/branches/type-system-rewrite/include/llvm/Support/PassManagerBuilder.h
llvm/branches/type-system-rewrite/include/llvm/Target/Target.td
llvm/branches/type-system-rewrite/include/llvm/Target/TargetAsmInfo.h
llvm/branches/type-system-rewrite/include/llvm/Target/TargetFrameLowering.h
llvm/branches/type-system-rewrite/include/llvm/Target/TargetMachine.h
llvm/branches/type-system-rewrite/include/llvm/Target/TargetRegisterInfo.h
llvm/branches/type-system-rewrite/include/llvm/Target/TargetRegistry.h
llvm/branches/type-system-rewrite/include/llvm/Transforms/Scalar.h
llvm/branches/type-system-rewrite/include/llvm/Transforms/Utils/SSAUpdater.h
llvm/branches/type-system-rewrite/lib/Analysis/ScalarEvolutionExpander.cpp
llvm/branches/type-system-rewrite/lib/Bitcode/Reader/BitcodeReader.h
llvm/branches/type-system-rewrite/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
llvm/branches/type-system-rewrite/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
llvm/branches/type-system-rewrite/lib/CodeGen/BranchFolding.cpp
llvm/branches/type-system-rewrite/lib/CodeGen/BranchFolding.h
llvm/branches/type-system-rewrite/lib/CodeGen/InlineSpiller.cpp
llvm/branches/type-system-rewrite/lib/CodeGen/IntrinsicLowering.cpp
llvm/branches/type-system-rewrite/lib/CodeGen/LLVMTargetMachine.cpp
llvm/branches/type-system-rewrite/lib/CodeGen/LiveDebugVariables.cpp
llvm/branches/type-system-rewrite/lib/CodeGen/LiveRangeEdit.cpp
llvm/branches/type-system-rewrite/lib/CodeGen/MachineInstr.cpp
llvm/branches/type-system-rewrite/lib/CodeGen/RegAllocGreedy.cpp
llvm/branches/type-system-rewrite/lib/CodeGen/RegisterCoalescer.cpp
llvm/branches/type-system-rewrite/lib/CodeGen/ScheduleDAGEmit.cpp
llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/branches/type-system-rewrite/lib/CodeGen/TailDuplication.cpp
llvm/branches/type-system-rewrite/lib/MC/MCAsmInfo.cpp
llvm/branches/type-system-rewrite/lib/MC/MCAsmStreamer.cpp
llvm/branches/type-system-rewrite/lib/MC/MCDisassembler/Disassembler.cpp
llvm/branches/type-system-rewrite/lib/MC/MCDisassembler/EDDisassembler.cpp
llvm/branches/type-system-rewrite/lib/MC/MCDisassembler/EDDisassembler.h
llvm/branches/type-system-rewrite/lib/MC/MCDwarf.cpp
llvm/branches/type-system-rewrite/lib/MC/MCSubtargetInfo.cpp
llvm/branches/type-system-rewrite/lib/MC/SubtargetFeature.cpp
llvm/branches/type-system-rewrite/lib/Object/COFFObjectFile.cpp
llvm/branches/type-system-rewrite/lib/Support/Triple.cpp
llvm/branches/type-system-rewrite/lib/Support/Unix/Path.inc
llvm/branches/type-system-rewrite/lib/Target/ARM/ARM.td
llvm/branches/type-system-rewrite/lib/Target/ARM/ARMAsmPrinter.cpp
llvm/branches/type-system-rewrite/lib/Target/ARM/ARMBaseInfo.h
llvm/branches/type-system-rewrite/lib/Target/ARM/ARMFrameLowering.cpp
llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrFormats.td
llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrInfo.td
llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrVFP.td
llvm/branches/type-system-rewrite/lib/Target/ARM/ARMSubtarget.cpp
llvm/branches/type-system-rewrite/lib/Target/ARM/ARMSubtarget.h
llvm/branches/type-system-rewrite/lib/Target/ARM/ARMTargetMachine.cpp
llvm/branches/type-system-rewrite/lib/Target/ARM/ARMTargetMachine.h
llvm/branches/type-system-rewrite/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/branches/type-system-rewrite/lib/Target/ARM/CMakeLists.txt
llvm/branches/type-system-rewrite/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
llvm/branches/type-system-rewrite/lib/Target/ARM/Makefile
llvm/branches/type-system-rewrite/lib/Target/Alpha/AlphaSubtarget.cpp
llvm/branches/type-system-rewrite/lib/Target/Alpha/AlphaSubtarget.h
llvm/branches/type-system-rewrite/lib/Target/Alpha/AlphaTargetMachine.cpp
llvm/branches/type-system-rewrite/lib/Target/Blackfin/BlackfinSubtarget.cpp
llvm/branches/type-system-rewrite/lib/Target/Blackfin/BlackfinSubtarget.h
llvm/branches/type-system-rewrite/lib/Target/Blackfin/BlackfinTargetMachine.cpp
llvm/branches/type-system-rewrite/lib/Target/CBackend/CTargetMachine.h
llvm/branches/type-system-rewrite/lib/Target/CellSPU/SPUSubtarget.cpp
llvm/branches/type-system-rewrite/lib/Target/CellSPU/SPUSubtarget.h
llvm/branches/type-system-rewrite/lib/Target/CellSPU/SPUTargetMachine.cpp
llvm/branches/type-system-rewrite/lib/Target/CppBackend/CPPTargetMachine.h
llvm/branches/type-system-rewrite/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp
llvm/branches/type-system-rewrite/lib/Target/MBlaze/InstPrinter/MBlazeInstPrinter.h
llvm/branches/type-system-rewrite/lib/Target/MBlaze/MBlazeAsmPrinter.cpp
llvm/branches/type-system-rewrite/lib/Target/MBlaze/MBlazeSubtarget.cpp
llvm/branches/type-system-rewrite/lib/Target/MBlaze/MBlazeSubtarget.h
llvm/branches/type-system-rewrite/lib/Target/MBlaze/MBlazeTargetMachine.cpp
llvm/branches/type-system-rewrite/lib/Target/MSP430/InstPrinter/MSP430InstPrinter.h
llvm/branches/type-system-rewrite/lib/Target/MSP430/MSP430AsmPrinter.cpp
llvm/branches/type-system-rewrite/lib/Target/MSP430/MSP430Subtarget.cpp
llvm/branches/type-system-rewrite/lib/Target/MSP430/MSP430Subtarget.h
llvm/branches/type-system-rewrite/lib/Target/MSP430/MSP430TargetMachine.cpp
llvm/branches/type-system-rewrite/lib/Target/Mips/CMakeLists.txt
llvm/branches/type-system-rewrite/lib/Target/Mips/Makefile
llvm/branches/type-system-rewrite/lib/Target/Mips/Mips.td
llvm/branches/type-system-rewrite/lib/Target/Mips/MipsAsmPrinter.cpp
llvm/branches/type-system-rewrite/lib/Target/Mips/MipsEmitGPRestore.cpp
llvm/branches/type-system-rewrite/lib/Target/Mips/MipsISelDAGToDAG.cpp
llvm/branches/type-system-rewrite/lib/Target/Mips/MipsISelLowering.cpp
llvm/branches/type-system-rewrite/lib/Target/Mips/MipsInstrInfo.cpp
llvm/branches/type-system-rewrite/lib/Target/Mips/MipsInstrInfo.h
llvm/branches/type-system-rewrite/lib/Target/Mips/MipsInstrInfo.td
llvm/branches/type-system-rewrite/lib/Target/Mips/MipsMCAsmInfo.cpp
llvm/branches/type-system-rewrite/lib/Target/Mips/MipsRegisterInfo.cpp
llvm/branches/type-system-rewrite/lib/Target/Mips/MipsSubtarget.cpp
llvm/branches/type-system-rewrite/lib/Target/Mips/MipsSubtarget.h
llvm/branches/type-system-rewrite/lib/Target/Mips/MipsTargetMachine.cpp
llvm/branches/type-system-rewrite/lib/Target/PTX/PTXSubtarget.cpp
llvm/branches/type-system-rewrite/lib/Target/PTX/PTXSubtarget.h
llvm/branches/type-system-rewrite/lib/Target/PTX/PTXTargetMachine.cpp
llvm/branches/type-system-rewrite/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h
llvm/branches/type-system-rewrite/lib/Target/PowerPC/PPCAsmPrinter.cpp
llvm/branches/type-system-rewrite/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/branches/type-system-rewrite/lib/Target/PowerPC/PPCSubtarget.cpp
llvm/branches/type-system-rewrite/lib/Target/PowerPC/PPCSubtarget.h
llvm/branches/type-system-rewrite/lib/Target/PowerPC/PPCTargetMachine.cpp
llvm/branches/type-system-rewrite/lib/Target/Sparc/SparcSubtarget.cpp
llvm/branches/type-system-rewrite/lib/Target/Sparc/SparcSubtarget.h
llvm/branches/type-system-rewrite/lib/Target/Sparc/SparcTargetMachine.cpp
llvm/branches/type-system-rewrite/lib/Target/SystemZ/SystemZSubtarget.cpp
llvm/branches/type-system-rewrite/lib/Target/SystemZ/SystemZSubtarget.h
llvm/branches/type-system-rewrite/lib/Target/SystemZ/SystemZTargetMachine.cpp
llvm/branches/type-system-rewrite/lib/Target/TargetAsmInfo.cpp
llvm/branches/type-system-rewrite/lib/Target/TargetMachine.cpp
llvm/branches/type-system-rewrite/lib/Target/X86/AsmParser/X86AsmParser.cpp
llvm/branches/type-system-rewrite/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
llvm/branches/type-system-rewrite/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h
llvm/branches/type-system-rewrite/lib/Target/X86/InstPrinter/X86InstComments.cpp
llvm/branches/type-system-rewrite/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp
llvm/branches/type-system-rewrite/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h
llvm/branches/type-system-rewrite/lib/Target/X86/MCTargetDesc/CMakeLists.txt
llvm/branches/type-system-rewrite/lib/Target/X86/X86.h
llvm/branches/type-system-rewrite/lib/Target/X86/X86.td
llvm/branches/type-system-rewrite/lib/Target/X86/X86AsmPrinter.cpp
llvm/branches/type-system-rewrite/lib/Target/X86/X86FrameLowering.cpp
llvm/branches/type-system-rewrite/lib/Target/X86/X86FrameLowering.h
llvm/branches/type-system-rewrite/lib/Target/X86/X86ISelLowering.cpp
llvm/branches/type-system-rewrite/lib/Target/X86/X86InstrFormats.td
llvm/branches/type-system-rewrite/lib/Target/X86/X86InstrInfo.td
llvm/branches/type-system-rewrite/lib/Target/X86/X86InstrSSE.td
llvm/branches/type-system-rewrite/lib/Target/X86/X86MCAsmInfo.cpp
llvm/branches/type-system-rewrite/lib/Target/X86/X86RegisterInfo.cpp
llvm/branches/type-system-rewrite/lib/Target/X86/X86RegisterInfo.h
llvm/branches/type-system-rewrite/lib/Target/X86/X86Subtarget.cpp
llvm/branches/type-system-rewrite/lib/Target/X86/X86Subtarget.h
llvm/branches/type-system-rewrite/lib/Target/X86/X86TargetMachine.cpp
llvm/branches/type-system-rewrite/lib/Target/XCore/XCoreSubtarget.cpp
llvm/branches/type-system-rewrite/lib/Target/XCore/XCoreSubtarget.h
llvm/branches/type-system-rewrite/lib/Target/XCore/XCoreTargetMachine.cpp
llvm/branches/type-system-rewrite/lib/Transforms/InstCombine/InstCombineCompares.cpp
llvm/branches/type-system-rewrite/lib/Transforms/Scalar/GVN.cpp
llvm/branches/type-system-rewrite/lib/Transforms/Scalar/IndVarSimplify.cpp
llvm/branches/type-system-rewrite/lib/Transforms/Scalar/LICM.cpp
llvm/branches/type-system-rewrite/lib/Transforms/Scalar/Scalar.cpp
llvm/branches/type-system-rewrite/lib/Transforms/Scalar/ScalarReplAggregates.cpp
llvm/branches/type-system-rewrite/lib/Transforms/Utils/CMakeLists.txt
llvm/branches/type-system-rewrite/lib/Transforms/Utils/SSAUpdater.cpp
llvm/branches/type-system-rewrite/lib/VMCore/LLVMContext.cpp
llvm/branches/type-system-rewrite/test/CodeGen/ARM/2009-10-30.ll
llvm/branches/type-system-rewrite/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll
llvm/branches/type-system-rewrite/test/CodeGen/ARM/armv4.ll
llvm/branches/type-system-rewrite/test/CodeGen/ARM/bfx.ll
llvm/branches/type-system-rewrite/test/CodeGen/ARM/call.ll
llvm/branches/type-system-rewrite/test/CodeGen/ARM/globals.ll
llvm/branches/type-system-rewrite/test/CodeGen/ARM/hello.ll
llvm/branches/type-system-rewrite/test/CodeGen/ARM/iabs.ll
llvm/branches/type-system-rewrite/test/CodeGen/ARM/ifcvt1.ll
llvm/branches/type-system-rewrite/test/CodeGen/ARM/ifcvt2.ll
llvm/branches/type-system-rewrite/test/CodeGen/ARM/ifcvt3.ll
llvm/branches/type-system-rewrite/test/CodeGen/ARM/indirectbr.ll
llvm/branches/type-system-rewrite/test/CodeGen/ARM/ldr_frame.ll
llvm/branches/type-system-rewrite/test/CodeGen/ARM/phi.ll
llvm/branches/type-system-rewrite/test/CodeGen/ARM/prefetch.ll
llvm/branches/type-system-rewrite/test/CodeGen/ARM/truncstore-dag-combine.ll
llvm/branches/type-system-rewrite/test/CodeGen/Thumb/barrier.ll
llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll
llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/lsr-deficiency.ll
llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/machine-licm.ll
llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/thumb2-clz.ll
llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/thumb2-rev.ll
llvm/branches/type-system-rewrite/test/CodeGen/X86/2010-04-08-CoalescerBug.ll
llvm/branches/type-system-rewrite/test/CodeGen/X86/2010-06-25-CoalescerSubRegDefDead.ll
llvm/branches/type-system-rewrite/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll
llvm/branches/type-system-rewrite/test/CodeGen/X86/crash.ll
llvm/branches/type-system-rewrite/test/CodeGen/X86/inline-asm-q-regs.ll
llvm/branches/type-system-rewrite/test/CodeGen/X86/inline-asm.ll
llvm/branches/type-system-rewrite/test/CodeGen/X86/lsr-nonaffine.ll
llvm/branches/type-system-rewrite/test/CodeGen/X86/memcpy.ll
llvm/branches/type-system-rewrite/test/CodeGen/X86/tlv-1.ll
llvm/branches/type-system-rewrite/test/MC/ARM/prefetch.ll
llvm/branches/type-system-rewrite/test/MC/ELF/relocation.s
llvm/branches/type-system-rewrite/test/MC/X86/x86-64.s
llvm/branches/type-system-rewrite/test/Transforms/IndVarSimplify/no-iv-rewrite.ll
llvm/branches/type-system-rewrite/test/Transforms/IndVarSimplify/variable-stride-ivs-0.ll
llvm/branches/type-system-rewrite/test/Transforms/InstCombine/icmp.ll
llvm/branches/type-system-rewrite/tools/llvm-mc/Disassembler.cpp
llvm/branches/type-system-rewrite/tools/llvm-mc/Disassembler.h
llvm/branches/type-system-rewrite/tools/llvm-mc/llvm-mc.cpp
llvm/branches/type-system-rewrite/tools/llvm-objdump/llvm-objdump.cpp
llvm/branches/type-system-rewrite/tools/lto/LTOModule.cpp
llvm/branches/type-system-rewrite/unittests/ADT/SmallVectorTest.cpp
llvm/branches/type-system-rewrite/utils/TableGen/ARMDecoderEmitter.cpp
llvm/branches/type-system-rewrite/utils/TableGen/AsmMatcherEmitter.cpp
llvm/branches/type-system-rewrite/utils/TableGen/AsmWriterEmitter.cpp
llvm/branches/type-system-rewrite/utils/TableGen/CodeEmitterGen.cpp
llvm/branches/type-system-rewrite/utils/TableGen/CodeGenDAGPatterns.cpp
llvm/branches/type-system-rewrite/utils/TableGen/CodeGenInstruction.cpp
llvm/branches/type-system-rewrite/utils/TableGen/CodeGenInstruction.h
llvm/branches/type-system-rewrite/utils/TableGen/EDEmitter.cpp
llvm/branches/type-system-rewrite/utils/TableGen/FixedLenDecoderEmitter.cpp
llvm/branches/type-system-rewrite/utils/TableGen/SubtargetEmitter.cpp
llvm/branches/type-system-rewrite/utils/llvmbuild
Propchange: llvm/branches/type-system-rewrite/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Thu Jul 7 23:45:15 2011
@@ -1,2 +1,2 @@
/llvm/branches/Apple/Pertwee:110850,110961
-/llvm/trunk:133420-134362
+/llvm/trunk:133420-134362,134364-134683
Modified: llvm/branches/type-system-rewrite/cmake/modules/LLVMLibDeps.cmake
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/cmake/modules/LLVMLibDeps.cmake?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/cmake/modules/LLVMLibDeps.cmake (original)
+++ llvm/branches/type-system-rewrite/cmake/modules/LLVMLibDeps.cmake Thu Jul 7 23:45:15 2011
@@ -1,6 +1,7 @@
set(MSVC_LIB_DEPS_LLVMARMAsmParser LLVMARMCodeGen LLVMARMInfo LLVMMC LLVMMCParser LLVMSupport LLVMTarget)
set(MSVC_LIB_DEPS_LLVMARMAsmPrinter LLVMMC LLVMSupport)
-set(MSVC_LIB_DEPS_LLVMARMCodeGen LLVMARMAsmPrinter LLVMARMInfo LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget)
+set(MSVC_LIB_DEPS_LLVMARMCodeGen LLVMARMAsmPrinter LLVMARMDesc LLVMARMInfo LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget)
+set(MSVC_LIB_DEPS_LLVMARMDesc LLVMARMInfo LLVMMC)
set(MSVC_LIB_DEPS_LLVMARMDisassembler LLVMARMCodeGen LLVMARMInfo LLVMMC LLVMSupport)
set(MSVC_LIB_DEPS_LLVMARMInfo LLVMMC LLVMSupport)
set(MSVC_LIB_DEPS_LLVMAlphaCodeGen LLVMAlphaInfo LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget)
@@ -21,7 +22,7 @@
set(MSVC_LIB_DEPS_LLVMCore LLVMSupport)
set(MSVC_LIB_DEPS_LLVMCppBackend LLVMCore LLVMCppBackendInfo LLVMSupport LLVMTarget)
set(MSVC_LIB_DEPS_LLVMCppBackendInfo LLVMMC LLVMSupport)
-set(MSVC_LIB_DEPS_LLVMExecutionEngine LLVMCore LLVMSupport LLVMTarget)
+set(MSVC_LIB_DEPS_LLVMExecutionEngine LLVMCore LLVMMC LLVMSupport LLVMTarget)
set(MSVC_LIB_DEPS_LLVMInstCombine LLVMAnalysis LLVMCore LLVMSupport LLVMTarget LLVMTransformUtils)
set(MSVC_LIB_DEPS_LLVMInstrumentation LLVMAnalysis LLVMCore LLVMSupport LLVMTransformUtils)
set(MSVC_LIB_DEPS_LLVMInterpreter LLVMCodeGen LLVMCore LLVMExecutionEngine LLVMSupport LLVMTarget)
@@ -59,8 +60,8 @@
set(MSVC_LIB_DEPS_LLVMTransformUtils LLVMAnalysis LLVMCore LLVMSupport LLVMTarget LLVMipa)
set(MSVC_LIB_DEPS_LLVMX86AsmParser LLVMMC LLVMMCParser LLVMSupport LLVMTarget LLVMX86Info)
set(MSVC_LIB_DEPS_LLVMX86AsmPrinter LLVMMC LLVMSupport LLVMX86Utils)
-set(MSVC_LIB_DEPS_LLVMX86CodeGen LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget LLVMX86AsmPrinter LLVMX86Info LLVMX86Utils)
-set(MSVC_LIB_DEPS_LLVMX86Desc LLVMX86Info)
+set(MSVC_LIB_DEPS_LLVMX86CodeGen LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget LLVMX86AsmPrinter LLVMX86Desc LLVMX86Info LLVMX86Utils)
+set(MSVC_LIB_DEPS_LLVMX86Desc LLVMMC LLVMX86Info)
set(MSVC_LIB_DEPS_LLVMX86Disassembler LLVMMC LLVMSupport LLVMX86Info)
set(MSVC_LIB_DEPS_LLVMX86Info LLVMMC LLVMSupport)
set(MSVC_LIB_DEPS_LLVMX86Utils LLVMCore LLVMSupport)
Modified: llvm/branches/type-system-rewrite/docs/index.html
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/docs/index.html?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/docs/index.html (original)
+++ llvm/branches/type-system-rewrite/docs/index.html Thu Jul 7 23:45:15 2011
@@ -164,6 +164,7 @@
<li><a href="HowToReleaseLLVM.html">How To Release LLVM To The Public</a> - This
is a guide to preparing LLVM releases. Most developers can ignore it.</li>
+
<li><a href="http://llvm.org/doxygen/">Doxygen generated
documentation</a> (<a
href="http://llvm.org/doxygen/inherits.html">classes</a>)
@@ -239,6 +240,10 @@
<li><a href="DebuggingJITedCode.html">The GDB JIT interface</a> - How to debug
JITed code with GDB.</li>
+
+<li><a href="BranchWeightMetadata.html">Branch Weight Metadata</a> - Provides
+information about Branch Prediction Information.</li>
+
</ul>
Modified: llvm/branches/type-system-rewrite/include/llvm/ADT/ImmutableList.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/include/llvm/ADT/ImmutableList.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/include/llvm/ADT/ImmutableList.h (original)
+++ llvm/branches/type-system-rewrite/include/llvm/ADT/ImmutableList.h Thu Jul 7 23:45:15 2011
@@ -103,6 +103,14 @@
/// isEmpty - Returns true if the list is empty.
bool isEmpty() const { return !X; }
+ bool contains(const T& V) const {
+ for (iterator I = begin(), E = end(); I != E; ++I) {
+ if (*I == V)
+ return true;
+ }
+ return false;
+ }
+
/// isEqual - Returns true if two lists are equal. Because all lists created
/// from the same ImmutableListFactory are uniqued, this has O(1) complexity
/// because it the contents of the list do not need to be compared. Note
Modified: llvm/branches/type-system-rewrite/include/llvm/ADT/SmallVector.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/include/llvm/ADT/SmallVector.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/include/llvm/ADT/SmallVector.h (original)
+++ llvm/branches/type-system-rewrite/include/llvm/ADT/SmallVector.h Thu Jul 7 23:45:15 2011
@@ -410,7 +410,14 @@
this->setEnd(this->end()+1);
// Push everything else over.
std::copy_backward(I, this->end()-1, this->end());
- *I = Elt;
+
+ // If we just moved the element we're inserting, be sure to update
+ // the reference.
+ const T *EltPtr = &Elt;
+ if (I <= EltPtr && EltPtr < this->EndX)
+ ++EltPtr;
+
+ *I = *EltPtr;
return I;
}
size_t EltNo = I-this->begin();
Modified: llvm/branches/type-system-rewrite/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/include/llvm/CodeGen/SelectionDAGNodes.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/branches/type-system-rewrite/include/llvm/CodeGen/SelectionDAGNodes.h Thu Jul 7 23:45:15 2011
@@ -23,6 +23,7 @@
#include "llvm/ADT/FoldingSet.h"
#include "llvm/ADT/GraphTraits.h"
#include "llvm/ADT/ilist_node.h"
+#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/ISDOpcodes.h"
@@ -496,11 +497,29 @@
///
bool isOperandOf(SDNode *N) const;
- /// isPredecessorOf - Return true if this node is a predecessor of N. This
- /// node is either an operand of N or it can be reached by recursively
+ /// isPredecessorOf - Return true if this node is a predecessor of N.
+ /// NOTE: Implemented on top of hasPredecessor and every bit as
+ /// expensive. Use carefully.
+ bool isPredecessorOf(const SDNode *N) const { return N->hasPredecessor(this); }
+
+ /// hasPredecessor - Return true if N is a predecessor of this node.
+ /// N is either an operand of this node, or can be reached by recursively
+ /// traversing up the operands.
+ /// NOTE: This is an expensive method. Use it carefully.
+ bool hasPredecessor(const SDNode *N) const;
+
+ /// hasPredecesorHelper - Return true if N is a predecessor of this node.
+ /// N is either an operand of this node, or can be reached by recursively
/// traversing up the operands.
- /// NOTE: this is an expensive method. Use it carefully.
- bool isPredecessorOf(SDNode *N) const;
+ /// In this helper the Visited and worklist sets are held externally to
+ /// cache predecessors over multiple invocations. If you want to test for
+ /// multiple predecessors this method is preferable to multiple calls to
+ /// hasPredecessor. Be sure to clear Visited and Worklist if the DAG
+ /// changes.
+ /// NOTE: This is still very expensive. Use carefully.
+ bool hasPredecessorHelper(const SDNode *N,
+ SmallPtrSet<const SDNode *, 32> &Visited,
+ SmallVector<const SDNode *, 16> &Worklist) const;
/// getNumOperands - Return the number of values used by this operation.
///
Modified: llvm/branches/type-system-rewrite/include/llvm/InitializePasses.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/include/llvm/InitializePasses.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/include/llvm/InitializePasses.h (original)
+++ llvm/branches/type-system-rewrite/include/llvm/InitializePasses.h Thu Jul 7 23:45:15 2011
@@ -140,6 +140,7 @@
void initializeLoopUnswitchPass(PassRegistry&);
void initializeLoopIdiomRecognizePass(PassRegistry&);
void initializeLowerAtomicPass(PassRegistry&);
+void initializeLowerExpectIntrinsicPass(PassRegistry&);
void initializeLowerIntrinsicsPass(PassRegistry&);
void initializeLowerInvokePass(PassRegistry&);
void initializeLowerSetJmpPass(PassRegistry&);
Modified: llvm/branches/type-system-rewrite/include/llvm/Intrinsics.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/include/llvm/Intrinsics.td?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/include/llvm/Intrinsics.td (original)
+++ llvm/branches/type-system-rewrite/include/llvm/Intrinsics.td Thu Jul 7 23:45:15 2011
@@ -266,6 +266,11 @@
[IntrNoMem]>,
GCCBuiltin<"__builtin_object_size">;
+//===------------------------- Expect Intrinsics --------------------------===//
+//
+def int_expect : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
+ LLVMMatchType<0>], [IntrNoMem]>;
+
//===-------------------- Bit Manipulation Intrinsics ---------------------===//
//
Modified: llvm/branches/type-system-rewrite/include/llvm/LLVMContext.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/include/llvm/LLVMContext.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/include/llvm/LLVMContext.h (original)
+++ llvm/branches/type-system-rewrite/include/llvm/LLVMContext.h Thu Jul 7 23:45:15 2011
@@ -39,7 +39,8 @@
// compile-time performance optimization, not a correctness optimization.
enum {
MD_dbg = 0, // "dbg"
- MD_tbaa = 1 // "tbaa"
+ MD_tbaa = 1, // "tbaa"
+ MD_prof = 2 // "prof"
};
/// getMDKindID - Return a unique non-zero ID for the specified metadata kind.
Modified: llvm/branches/type-system-rewrite/include/llvm/LinkAllPasses.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/include/llvm/LinkAllPasses.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/include/llvm/LinkAllPasses.h (original)
+++ llvm/branches/type-system-rewrite/include/llvm/LinkAllPasses.h Thu Jul 7 23:45:15 2011
@@ -91,6 +91,7 @@
(void) llvm::createLoopUnswitchPass();
(void) llvm::createLoopIdiomPass();
(void) llvm::createLoopRotatePass();
+ (void) llvm::createLowerExpectIntrinsicPass();
(void) llvm::createLowerInvokePass();
(void) llvm::createLowerSetJmpPass();
(void) llvm::createLowerSwitchPass();
Modified: llvm/branches/type-system-rewrite/include/llvm/MC/MCAsmInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/include/llvm/MC/MCAsmInfo.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/include/llvm/MC/MCAsmInfo.h (original)
+++ llvm/branches/type-system-rewrite/include/llvm/MC/MCAsmInfo.h Thu Jul 7 23:45:15 2011
@@ -284,6 +284,10 @@
// use EmitLabelOffsetDifference.
bool DwarfUsesLabelOffsetForRanges;
+ /// DwarfRegNumForCFI - True if dwarf register numbers are printed
+ /// instead of symbolic register names in .cfi_* directives.
+ bool DwarfRegNumForCFI; // Defaults to false;
+
//===--- CBE Asm Translation Table -----------------------------------===//
const char *const *AsmTransCBE; // Defaults to empty
@@ -475,6 +479,9 @@
bool doesDwarfUsesLabelOffsetForRanges() const {
return DwarfUsesLabelOffsetForRanges;
}
+ bool useDwarfRegNumForCFI() const {
+ return DwarfRegNumForCFI;
+ }
const char *const *getAsmCBE() const {
return AsmTransCBE;
}
Modified: llvm/branches/type-system-rewrite/include/llvm/MC/MCSubtargetInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/include/llvm/MC/MCSubtargetInfo.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/include/llvm/MC/MCSubtargetInfo.h (original)
+++ llvm/branches/type-system-rewrite/include/llvm/MC/MCSubtargetInfo.h Thu Jul 7 23:45:15 2011
@@ -34,30 +34,29 @@
const unsigned *ForwardingPathes; // Forwarding pathes
unsigned NumFeatures; // Number of processor features
unsigned NumProcs; // Number of processors
-
+ uint64_t FeatureBits; // Feature bits for current CPU
+
public:
- void InitMCSubtargetInfo(const SubtargetFeatureKV *PF,
+ void InitMCSubtargetInfo(StringRef CPU, StringRef FS,
+ const SubtargetFeatureKV *PF,
const SubtargetFeatureKV *PD,
const SubtargetInfoKV *PI, const InstrStage *IS,
const unsigned *OC, const unsigned *FP,
- unsigned NF, unsigned NP) {
- ProcFeatures = PF;
- ProcDesc = PD;
- ProcItins = PI;
- Stages = IS;
- OperandCycles = OC;
- ForwardingPathes = FP;
- NumFeatures = NF;
- NumProcs = NP;
+ unsigned NF, unsigned NP);
+
+ /// getFeatureBits - Get the feature bits.
+ ///
+ uint64_t getFeatureBits() const {
+ return FeatureBits;
}
+ /// ReInitMCSubtargetInfo - Change CPU (and optionally supplemented with
+ /// feature string), recompute and return feature bits.
+ uint64_t ReInitMCSubtargetInfo(StringRef CPU, StringRef FS);
+
/// getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
///
InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const;
-
- /// getFeatureBits - Get the feature bits for a CPU (optionally supplemented
- /// with feature string).
- uint64_t getFeatureBits(StringRef CPU, StringRef FS) const;
};
} // End llvm namespace
Modified: llvm/branches/type-system-rewrite/include/llvm/Object/ObjectFile.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/include/llvm/Object/ObjectFile.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/include/llvm/Object/ObjectFile.h (original)
+++ llvm/branches/type-system-rewrite/include/llvm/Object/ObjectFile.h Thu Jul 7 23:45:15 2011
@@ -44,7 +44,10 @@
const ObjectFile *OwningObject;
public:
- RelocationRef() : OwningObject(NULL) { std::memset(&RelocationPimpl, 0, sizeof(RelocationPimpl)); }
+ RelocationRef() : OwningObject(NULL) {
+ std::memset(&RelocationPimpl, 0, sizeof(RelocationPimpl));
+ }
+
RelocationRef(DataRefImpl RelocationP, const ObjectFile *Owner);
bool operator==(const RelocationRef &Other) const;
@@ -59,7 +62,10 @@
const ObjectFile *OwningObject;
public:
- SymbolRef() : OwningObject(NULL) { std::memset(&SymbolPimpl, 0, sizeof(SymbolPimpl)); }
+ SymbolRef() : OwningObject(NULL) {
+ std::memset(&SymbolPimpl, 0, sizeof(SymbolPimpl));
+ }
+
SymbolRef(DataRefImpl SymbolP, const ObjectFile *Owner);
bool operator==(const SymbolRef &Other) const;
@@ -86,7 +92,10 @@
const ObjectFile *OwningObject;
public:
- SectionRef() : OwningObject(NULL) { std::memset(&SectionPimpl, 0, sizeof(SectionPimpl)); }
+ SectionRef() : OwningObject(NULL) {
+ std::memset(&SectionPimpl, 0, sizeof(SectionPimpl));
+ }
+
SectionRef(DataRefImpl SectionP, const ObjectFile *Owner);
bool operator==(const SectionRef &Other) const;
Modified: llvm/branches/type-system-rewrite/include/llvm/Support/CFG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/include/llvm/Support/CFG.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/include/llvm/Support/CFG.h (original)
+++ llvm/branches/type-system-rewrite/include/llvm/Support/CFG.h Thu Jul 7 23:45:15 2011
@@ -109,11 +109,18 @@
// TODO: This can be random access iterator, only operator[] missing.
explicit inline SuccIterator(Term_ T) : Term(T), idx(0) {// begin iterator
- assert(T && "getTerminator returned null!");
}
inline SuccIterator(Term_ T, bool) // end iterator
- : Term(T), idx(Term->getNumSuccessors()) {
- assert(T && "getTerminator returned null!");
+ : Term(T) {
+ if (Term)
+ idx = Term->getNumSuccessors();
+ else
+ // Term == NULL happens, if a basic block is not fully constructed and
+ // consequently getTerminator() returns NULL. In this case we construct a
+ // SuccIterator which describes a basic block that has zero successors.
+ // Defining SuccIterator for incomplete and malformed CFGs is especially
+ // useful for debugging.
+ idx = 0;
}
inline const Self &operator=(const Self &I) {
@@ -201,6 +208,7 @@
/// Get the source BB of this iterator.
inline BB_ *getSource() {
+ assert(Term && "Source not available, if basic block was malformed");
return Term->getParent();
}
};
Modified: llvm/branches/type-system-rewrite/include/llvm/Support/PassManagerBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/include/llvm/Support/PassManagerBuilder.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/include/llvm/Support/PassManagerBuilder.h (original)
+++ llvm/branches/type-system-rewrite/include/llvm/Support/PassManagerBuilder.h Thu Jul 7 23:45:15 2011
@@ -67,7 +67,12 @@
/// EP_LoopOptimizerEnd - This extension point allows adding loop passes to
/// the end of the loop optimizer.
- EP_LoopOptimizerEnd
+ EP_LoopOptimizerEnd,
+
+ /// EP_ScalarOptimizerLate - This extension point allows adding optimization
+ /// passes after most of the main optimizations, but before the last
+ /// cleanup-ish optimizations.
+ EP_ScalarOptimizerLate
};
/// The Optimization Level - Specify the basic optimization level.
@@ -147,6 +152,7 @@
FPM.add(createCFGSimplificationPass());
FPM.add(createScalarReplAggregatesPass());
FPM.add(createEarlyCSEPass());
+ FPM.add(createLowerExpectIntrinsicPass());
}
/// populateModulePassManager - This sets up the primary pass manager.
@@ -188,7 +194,6 @@
MPM.add(createArgumentPromotionPass()); // Scalarize uninlined fn args
// Start of function pass.
- MPM.add(createObjCARCExpandPass()); // Canonicalize ObjC ARC code.
// Break up aggregate allocas, using SSAUpdater.
MPM.add(createScalarReplAggregatesPass(-1, false));
MPM.add(createEarlyCSEPass()); // Catch trivial redundancies
@@ -224,7 +229,9 @@
MPM.add(createJumpThreadingPass()); // Thread jumps
MPM.add(createCorrelatedValuePropagationPass());
MPM.add(createDeadStoreEliminationPass()); // Delete dead stores
- MPM.add(createObjCARCOptPass()); // Objective-C ARC optimizations.
+
+ addExtensionsToPM(EP_ScalarOptimizerLate, MPM);
+
MPM.add(createAggressiveDCEPass()); // Delete dead instructions
MPM.add(createCFGSimplificationPass()); // Merge & remove BBs
MPM.add(createInstructionCombiningPass()); // Clean up after everything.
Modified: llvm/branches/type-system-rewrite/include/llvm/Target/Target.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/include/llvm/Target/Target.td?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/include/llvm/Target/Target.td (original)
+++ llvm/branches/type-system-rewrite/include/llvm/Target/Target.td Thu Jul 7 23:45:15 2011
@@ -324,6 +324,9 @@
bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
+ bit isPseudo = 0; // Is this instruction a pseudo-instruction?
+ // If so, won't have encoding information for
+ // the [MC]CodeEmitter stuff.
// Side effect flags - When set, the flags have these meanings:
//
@@ -338,6 +341,11 @@
// Is this instruction a "real" instruction (with a distinct machine
// encoding), or is it a pseudo instruction used for codegen modeling
// purposes.
+ // FIXME: For now this is distinct from isPseudo, above, as code-gen-only
+ // instructions can (and often do) still have encoding information
+ // associated with them. Once we've migrated all of them over to true
+ // pseudo-instructions that are lowered to real instructions prior to
+ // the printer/emitter, we can remove this attribute and just use isPseudo.
bit isCodeGenOnly = 0;
// Is this instruction a pseudo instruction for use by the assembler parser.
@@ -374,6 +382,15 @@
/// matcher, this is true. Targets should set this by inheriting their
/// feature from the AssemblerPredicate class in addition to Predicate.
bit AssemblerMatcherPredicate = 0;
+
+ /// AssemblerCondString - Name of the subtarget feature being tested used
+ /// as alternative condition string used for assembler matcher.
+ /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0".
+ /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0".
+ /// It can also list multiple features separated by ",".
+ /// e.g. "ModeThumb,FeatureThumb2" is translated to
+ /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".
+ string AssemblerCondString = "";
}
/// NoHonorSignDependentRounding - This predicate is true if support for
@@ -681,8 +698,9 @@
/// AssemblerPredicate - This is a Predicate that can be used when the assembler
/// matches instructions and aliases.
-class AssemblerPredicate {
+class AssemblerPredicate<string cond> {
bit AssemblerMatcherPredicate = 1;
+ string AssemblerCondString = cond;
}
Modified: llvm/branches/type-system-rewrite/include/llvm/Target/TargetAsmInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/include/llvm/Target/TargetAsmInfo.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/include/llvm/Target/TargetAsmInfo.h (original)
+++ llvm/branches/type-system-rewrite/include/llvm/Target/TargetAsmInfo.h Thu Jul 7 23:45:15 2011
@@ -20,6 +20,7 @@
#include "llvm/Target/TargetRegisterInfo.h"
namespace llvm {
+ template <typename T> class ArrayRef;
class MCSection;
class MCContext;
class MachineFunction;
@@ -30,8 +31,9 @@
unsigned PointerSize;
bool IsLittleEndian;
TargetFrameLowering::StackDirection StackDir;
- const TargetRegisterInfo *TRI;
std::vector<MachineMove> InitialFrameState;
+ const TargetRegisterInfo *TRI;
+ const TargetFrameLowering *TFI;
const TargetLoweringObjectFile *TLOF;
public:
@@ -83,6 +85,9 @@
return TLOF->isFunctionEHFrameSymbolPrivate();
}
+ int getCompactUnwindEncoding(ArrayRef<MCCFIInstruction> Instrs,
+ int DataAlignmentFactor, bool IsEH) const;
+
const unsigned *getCalleeSavedRegs(MachineFunction *MF = 0) const {
return TRI->getCalleeSavedRegs(MF);
}
@@ -106,10 +111,6 @@
int getSEHRegNum(unsigned RegNum) const {
return TRI->getSEHRegNum(RegNum);
}
-
- int getCompactUnwindRegNum(unsigned RegNum) const {
- return TRI->getCompactUnwindRegNum(RegNum);
- }
};
}
Modified: llvm/branches/type-system-rewrite/include/llvm/Target/TargetFrameLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/include/llvm/Target/TargetFrameLowering.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/include/llvm/Target/TargetFrameLowering.h (original)
+++ llvm/branches/type-system-rewrite/include/llvm/Target/TargetFrameLowering.h Thu Jul 7 23:45:15 2011
@@ -15,6 +15,8 @@
#define LLVM_TARGET_TARGETFRAMELOWERING_H
#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/MC/MCDwarf.h"
+#include "llvm/ADT/ArrayRef.h"
#include <utility>
#include <vector>
@@ -189,6 +191,14 @@
///
virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
}
+
+ /// getCompactUnwindEncoding - Get the compact unwind encoding for the
+ /// function. Return 0 if the compact unwind isn't available.
+ virtual uint32_t getCompactUnwindEncoding(ArrayRef<MCCFIInstruction> Instrs,
+ int DataAlignmentFactor,
+ bool IsEH) const {
+ return 0;
+ }
};
} // End llvm namespace
Modified: llvm/branches/type-system-rewrite/include/llvm/Target/TargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/include/llvm/Target/TargetMachine.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/include/llvm/Target/TargetMachine.h (original)
+++ llvm/branches/type-system-rewrite/include/llvm/Target/TargetMachine.h Thu Jul 7 23:45:15 2011
@@ -14,6 +14,7 @@
#ifndef LLVM_TARGET_TARGETMACHINE_H
#define LLVM_TARGET_TARGETMACHINE_H
+#include "llvm/ADT/StringRef.h"
#include <cassert>
#include <string>
@@ -91,7 +92,8 @@
TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT
void operator=(const TargetMachine &); // DO NOT IMPLEMENT
protected: // Can only create subclasses.
- TargetMachine(const Target &);
+ TargetMachine(const Target &T, StringRef TargetTriple,
+ StringRef CPU, StringRef FS);
/// getSubtargetImpl - virtual method implemented by subclasses that returns
/// a reference to that target's TargetSubtargetInfo-derived member variable.
@@ -100,6 +102,12 @@
/// TheTarget - The Target that this machine was created for.
const Target &TheTarget;
+ /// TargetTriple, TargetCPU, TargetFS - Triple string, CPU name, and target
+ /// feature strings the TargetMachine instance is created with.
+ std::string TargetTriple;
+ std::string TargetCPU;
+ std::string TargetFS;
+
/// AsmInfo - Contains target specific asm information.
///
const MCAsmInfo *AsmInfo;
@@ -115,6 +123,10 @@
const Target &getTarget() const { return TheTarget; }
+ const StringRef getTargetTriple() const { return TargetTriple; }
+ const StringRef getTargetCPU() const { return TargetCPU; }
+ const StringRef getTargetFeatureString() const { return TargetFS; }
+
// Interfaces to the major aspects of target machine information:
// -- Instruction opcode and operand information
// -- Pipelines and scheduling information
@@ -295,10 +307,9 @@
/// implemented with the LLVM target-independent code generator.
///
class LLVMTargetMachine : public TargetMachine {
- std::string TargetTriple;
-
protected: // Can only create subclasses.
- LLVMTargetMachine(const Target &T, const std::string &TargetTriple);
+ LLVMTargetMachine(const Target &T, StringRef TargetTriple,
+ StringRef CPU, StringRef FS);
private:
/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
@@ -311,9 +322,6 @@
virtual void setCodeModelForStatic();
public:
-
- const std::string &getTargetTriple() const { return TargetTriple; }
-
/// addPassesToEmitFile - Add passes to the specified pass manager to get the
/// specified file emitted. Typically this will involve several steps of code
/// generation. If OptLevel is None, the code generator should emit code as
Modified: llvm/branches/type-system-rewrite/include/llvm/Target/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/include/llvm/Target/TargetRegisterInfo.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/include/llvm/Target/TargetRegisterInfo.h (original)
+++ llvm/branches/type-system-rewrite/include/llvm/Target/TargetRegisterInfo.h Thu Jul 7 23:45:15 2011
@@ -723,7 +723,7 @@
/// getCompactUnwindRegNum - This function maps the register to the number for
/// compact unwind encoding. Return -1 if the register isn't valid.
- virtual int getCompactUnwindRegNum(unsigned) const {
+ virtual int getCompactUnwindRegNum(unsigned, bool) const {
return -1;
}
};
Modified: llvm/branches/type-system-rewrite/include/llvm/Target/TargetRegistry.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/include/llvm/Target/TargetRegistry.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/include/llvm/Target/TargetRegistry.h (original)
+++ llvm/branches/type-system-rewrite/include/llvm/Target/TargetRegistry.h Thu Jul 7 23:45:15 2011
@@ -35,7 +35,6 @@
class MCInstPrinter;
class MCInstrInfo;
class MCRegisterInfo;
- class MCSubtargetInfo;
class MCStreamer;
class TargetAsmBackend;
class TargetAsmLexer;
@@ -70,7 +69,6 @@
StringRef TT);
typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void);
typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(void);
- typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(void);
typedef TargetMachine *(*TargetMachineCtorTy)(const Target &T,
const std::string &TT,
const std::string &CPU,
@@ -81,11 +79,11 @@
const std::string &TT);
typedef TargetAsmLexer *(*AsmLexerCtorTy)(const Target &T,
const MCAsmInfo &MAI);
- typedef TargetAsmParser *(*AsmParserCtorTy)(const Target &T,MCAsmParser &P,
- TargetMachine &TM);
+ typedef TargetAsmParser *(*AsmParserCtorTy)(const Target &T, StringRef TT,
+ StringRef CPU, StringRef Features,
+ MCAsmParser &P);
typedef MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T);
typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const Target &T,
- TargetMachine &TM,
unsigned SyntaxVariant,
const MCAsmInfo &MAI);
typedef MCCodeEmitter *(*CodeEmitterCtorTy)(const Target &T,
@@ -139,10 +137,6 @@
/// if registered.
MCRegInfoCtorFnTy MCRegInfoCtorFn;
- /// MCSubtargetInfoCtorFn - Constructor function for this target's
- /// MCSubtargetInfo, if registered.
- MCSubtargetInfoCtorFnTy MCSubtargetInfoCtorFn;
-
/// TargetMachineCtorFn - Construction function for this target's
/// TargetMachine, if registered.
TargetMachineCtorTy TargetMachineCtorFn;
@@ -268,14 +262,6 @@
return MCRegInfoCtorFn();
}
- /// createMCSubtargetInfo - Create a MCSubtargetInfo implementation.
- ///
- MCSubtargetInfo *createMCSubtargetInfo() const {
- if (!MCSubtargetInfoCtorFn)
- return 0;
- return MCSubtargetInfoCtorFn();
- }
-
/// createTargetMachine - Create a target specific machine implementation
/// for the specified \arg Triple.
///
@@ -313,11 +299,11 @@
///
/// \arg Parser - The target independent parser implementation to use for
/// parsing and lexing.
- TargetAsmParser *createAsmParser(MCAsmParser &Parser,
- TargetMachine &TM) const {
+ TargetAsmParser *createAsmParser(StringRef Triple, StringRef CPU,
+ StringRef Features, MCAsmParser &Parser) const {
if (!AsmParserCtorFn)
return 0;
- return AsmParserCtorFn(*this, Parser, TM);
+ return AsmParserCtorFn(*this, Triple, CPU, Features, Parser);
}
/// createAsmPrinter - Create a target specific assembly printer pass. This
@@ -334,12 +320,11 @@
return MCDisassemblerCtorFn(*this);
}
- MCInstPrinter *createMCInstPrinter(TargetMachine &TM,
- unsigned SyntaxVariant,
+ MCInstPrinter *createMCInstPrinter(unsigned SyntaxVariant,
const MCAsmInfo &MAI) const {
if (!MCInstPrinterCtorFn)
return 0;
- return MCInstPrinterCtorFn(*this, TM, SyntaxVariant, MAI);
+ return MCInstPrinterCtorFn(*this, SyntaxVariant, MAI);
}
@@ -520,22 +505,6 @@
T.MCRegInfoCtorFn = Fn;
}
- /// RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for
- /// the given target.
- ///
- /// Clients are responsible for ensuring that registration doesn't occur
- /// while another thread is attempting to access the registry. Typically
- /// this is done by initializing all targets at program startup.
- ///
- /// @param T - The target being registered.
- /// @param Fn - A function to construct a MCSubtargetInfo for the target.
- static void RegisterMCSubtargetInfo(Target &T,
- Target::MCSubtargetInfoCtorFnTy Fn) {
- // Ignore duplicate registration.
- if (!T.MCSubtargetInfoCtorFn)
- T.MCSubtargetInfoCtorFn = Fn;
- }
-
/// RegisterTargetMachine - Register a TargetMachine implementation for the
/// given target.
///
@@ -812,39 +781,6 @@
}
};
- /// RegisterMCSubtargetInfo - Helper template for registering a target
- /// subtarget info implementation. This invokes the static "Create" method
- /// on the class to actually do the construction. Usage:
- ///
- /// extern "C" void LLVMInitializeFooTarget() {
- /// extern Target TheFooTarget;
- /// RegisterMCSubtargetInfo<FooMCSubtargetInfo> X(TheFooTarget);
- /// }
- template<class MCSubtargetInfoImpl>
- struct RegisterMCSubtargetInfo {
- RegisterMCSubtargetInfo(Target &T) {
- TargetRegistry::RegisterMCSubtargetInfo(T, &Allocator);
- }
- private:
- static MCSubtargetInfo *Allocator() {
- return new MCSubtargetInfoImpl();
- }
- };
-
- /// RegisterMCSubtargetInfoFn - Helper template for registering a target
- /// subtarget info implementation. This invokes the specified function to
- /// do the construction. Usage:
- ///
- /// extern "C" void LLVMInitializeFooTarget() {
- /// extern Target TheFooTarget;
- /// RegisterMCSubtargetInfoFn X(TheFooTarget, TheFunction);
- /// }
- struct RegisterMCSubtargetInfoFn {
- RegisterMCSubtargetInfoFn(Target &T, Target::MCSubtargetInfoCtorFnTy Fn) {
- TargetRegistry::RegisterMCSubtargetInfo(T, Fn);
- }
- };
-
/// RegisterTargetMachine - Helper template for registering a target machine
/// implementation, for use in the target machine initialization
/// function. Usage:
@@ -922,9 +858,10 @@
}
private:
- static TargetAsmParser *Allocator(const Target &T, MCAsmParser &P,
- TargetMachine &TM) {
- return new AsmParserImpl(T, P, TM);
+ static TargetAsmParser *Allocator(const Target &T, StringRef TT,
+ StringRef CPU, StringRef FS,
+ MCAsmParser &P) {
+ return new AsmParserImpl(T, TT, CPU, FS, P);
}
};
Modified: llvm/branches/type-system-rewrite/include/llvm/Transforms/Scalar.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/include/llvm/Transforms/Scalar.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/include/llvm/Transforms/Scalar.h (original)
+++ llvm/branches/type-system-rewrite/include/llvm/Transforms/Scalar.h Thu Jul 7 23:45:15 2011
@@ -361,6 +361,14 @@
FunctionPass *createInstructionSimplifierPass();
extern char &InstructionSimplifierID;
+
+//===----------------------------------------------------------------------===//
+//
+// LowerExpectIntriniscs - Removes llvm.expect intrinsics and creates
+// "block_weights" metadata.
+FunctionPass *createLowerExpectIntrinsicPass();
+
+
} // End llvm namespace
#endif
Modified: llvm/branches/type-system-rewrite/include/llvm/Transforms/Utils/SSAUpdater.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/include/llvm/Transforms/Utils/SSAUpdater.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/include/llvm/Transforms/Utils/SSAUpdater.h (original)
+++ llvm/branches/type-system-rewrite/include/llvm/Transforms/Utils/SSAUpdater.h Thu Jul 7 23:45:15 2011
@@ -122,12 +122,9 @@
class LoadAndStorePromoter {
protected:
SSAUpdater &SSA;
- DbgDeclareInst *DDI;
- DIBuilder *DIB;
public:
LoadAndStorePromoter(const SmallVectorImpl<Instruction*> &Insts,
- SSAUpdater &S, DbgDeclareInst *DDI, DIBuilder *DIB,
- StringRef Name = StringRef());
+ SSAUpdater &S, StringRef Name = StringRef());
virtual ~LoadAndStorePromoter() {}
/// run - This does the promotion. Insts is a list of loads and stores to
@@ -161,6 +158,10 @@
virtual void instructionDeleted(Instruction *I) const {
}
+ /// updateDebugInfo - This is called to update debug info associated with the
+ /// instruction.
+ virtual void updateDebugInfo(Instruction *I) const {
+ }
};
} // End llvm namespace
Modified: llvm/branches/type-system-rewrite/lib/Analysis/ScalarEvolutionExpander.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Analysis/ScalarEvolutionExpander.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Analysis/ScalarEvolutionExpander.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Analysis/ScalarEvolutionExpander.cpp Thu Jul 7 23:45:15 2011
@@ -955,7 +955,7 @@
// at IVIncInsertPos.
Instruction *InsertPos = L == IVIncInsertLoop ?
IVIncInsertPos : Pred->getTerminator();
- Builder.SetInsertPoint(InsertPos->getParent(), InsertPos);
+ Builder.SetInsertPoint(InsertPos);
Value *IncV;
// If the PHI is a pointer, use a GEP, otherwise use an add or sub.
if (isPointer) {
Modified: llvm/branches/type-system-rewrite/lib/Bitcode/Reader/BitcodeReader.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Bitcode/Reader/BitcodeReader.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Bitcode/Reader/BitcodeReader.h (original)
+++ llvm/branches/type-system-rewrite/lib/Bitcode/Reader/BitcodeReader.h Thu Jul 7 23:45:15 2011
@@ -44,9 +44,9 @@
/// number that holds the resolved value.
typedef std::vector<std::pair<Constant*, unsigned> > ResolveConstantsTy;
ResolveConstantsTy ResolveConstants;
- LLVMContext& Context;
+ LLVMContext &Context;
public:
- BitcodeReaderValueList(LLVMContext& C) : Context(C) {}
+ BitcodeReaderValueList(LLVMContext &C) : Context(C) {}
~BitcodeReaderValueList() {
assert(ResolveConstants.empty() && "Constants not resolved?");
}
@@ -213,10 +213,9 @@
Type *getTypeByID(unsigned ID);
Type *getTypeByIDOrNull(unsigned ID);
Value *getFnValueByID(unsigned ID, const Type *Ty) {
- if (Ty == Type::getMetadataTy(Context))
+ if (Ty && Ty->isMetadataTy())
return MDValueList.getValueFwdRef(ID);
- else
- return ValueList.getValueFwdRef(ID, Ty);
+ return ValueList.getValueFwdRef(ID, Ty);
}
BasicBlock *getBasicBlock(unsigned ID) const {
if (ID >= FunctionBBs.size()) return 0; // Invalid ID
Modified: llvm/branches/type-system-rewrite/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp Thu Jul 7 23:45:15 2011
@@ -111,7 +111,12 @@
OwningPtr<MCAsmParser> Parser(createMCAsmParser(TM.getTarget(), SrcMgr,
OutContext, OutStreamer,
*MAI));
- OwningPtr<TargetAsmParser> TAP(TM.getTarget().createAsmParser(*Parser, TM));
+
+ OwningPtr<TargetAsmParser>
+ TAP(TM.getTarget().createAsmParser(TM.getTargetTriple(),
+ TM.getTargetCPU(),
+ TM.getTargetFeatureString(),
+ *Parser));
if (!TAP)
report_fatal_error("Inline asm not supported by this streamer because"
" we don't have an asm parser for this target\n");
Modified: llvm/branches/type-system-rewrite/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Thu Jul 7 23:45:15 2011
@@ -1428,6 +1428,8 @@
SLabel = FunctionEndSym;
else {
const MachineInstr *End = HI[1];
+ DEBUG(dbgs() << "DotDebugLoc Pair:\n"
+ << "\t" << *Begin << "\t" << *End << "\n");
if (End->isDebugValue())
SLabel = getLabelBeforeInsn(End);
else {
@@ -1846,8 +1848,6 @@
assert(UserVariables.empty() && DbgValues.empty() && "Maps weren't cleaned");
- /// ProcessedArgs - Collection of arguments already processed.
- SmallPtrSet<const MDNode *, 8> ProcessedArgs;
const TargetRegisterInfo *TRI = Asm->TM.getRegisterInfo();
/// LiveUserVar - Map physreg numbers to the MDNode they contain.
std::vector<const MDNode*> LiveUserVar(TRI->getNumRegs());
@@ -1887,8 +1887,12 @@
if (Prev->isDebugValue()) {
// Coalesce identical entries at the end of History.
if (History.size() >= 2 &&
- Prev->isIdenticalTo(History[History.size() - 2]))
+ Prev->isIdenticalTo(History[History.size() - 2])) {
+ DEBUG(dbgs() << "Coalesce identical DBG_VALUE entries:\n"
+ << "\t" << *Prev
+ << "\t" << *History[History.size() - 2] << "\n");
History.pop_back();
+ }
// Terminate old register assignments that don't reach MI;
MachineFunction::const_iterator PrevMBB = Prev->getParent();
@@ -1898,9 +1902,12 @@
// its basic block.
MachineBasicBlock::const_iterator LastMI =
PrevMBB->getLastNonDebugInstr();
- if (LastMI == PrevMBB->end())
+ if (LastMI == PrevMBB->end()) {
// Drop DBG_VALUE for empty range.
+ DEBUG(dbgs() << "Drop DBG_VALUE for empty range:\n"
+ << "\t" << *Prev << "\n");
History.pop_back();
+ }
else {
// Terminate after LastMI.
History.push_back(LastMI);
Modified: llvm/branches/type-system-rewrite/lib/CodeGen/BranchFolding.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/CodeGen/BranchFolding.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/CodeGen/BranchFolding.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/CodeGen/BranchFolding.cpp Thu Jul 7 23:45:15 2011
@@ -366,11 +366,31 @@
return TailLen;
}
+void BranchFolder::MaintainLiveIns(MachineBasicBlock *CurMBB,
+ MachineBasicBlock *NewMBB) {
+ if (RS) {
+ RS->enterBasicBlock(CurMBB);
+ if (!CurMBB->empty())
+ RS->forward(prior(CurMBB->end()));
+ BitVector RegsLiveAtExit(TRI->getNumRegs());
+ RS->getRegsUsed(RegsLiveAtExit, false);
+ for (unsigned int i = 0, e = TRI->getNumRegs(); i != e; i++)
+ if (RegsLiveAtExit[i])
+ NewMBB->addLiveIn(i);
+ }
+}
+
/// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
/// after it, replacing it with an unconditional branch to NewDest.
void BranchFolder::ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst,
MachineBasicBlock *NewDest) {
+ MachineBasicBlock *CurMBB = OldInst->getParent();
+
TII->ReplaceTailWithBranchTo(OldInst, NewDest);
+
+ // For targets that use the register scavenger, we must maintain LiveIns.
+ MaintainLiveIns(CurMBB, NewDest);
+
++NumTailMerge;
}
@@ -399,16 +419,7 @@
NewMBB->splice(NewMBB->end(), &CurMBB, BBI1, CurMBB.end());
// For targets that use the register scavenger, we must maintain LiveIns.
- if (RS) {
- RS->enterBasicBlock(&CurMBB);
- if (!CurMBB.empty())
- RS->forward(prior(CurMBB.end()));
- BitVector RegsLiveAtExit(TRI->getNumRegs());
- RS->getRegsUsed(RegsLiveAtExit, false);
- for (unsigned int i = 0, e = TRI->getNumRegs(); i != e; i++)
- if (RegsLiveAtExit[i])
- NewMBB->addLiveIn(i);
- }
+ MaintainLiveIns(&CurMBB, NewMBB);
return NewMBB;
}
Modified: llvm/branches/type-system-rewrite/lib/CodeGen/BranchFolding.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/CodeGen/BranchFolding.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/CodeGen/BranchFolding.h (original)
+++ llvm/branches/type-system-rewrite/lib/CodeGen/BranchFolding.h Thu Jul 7 23:45:15 2011
@@ -95,6 +95,8 @@
bool TailMergeBlocks(MachineFunction &MF);
bool TryTailMergeBlocks(MachineBasicBlock* SuccBB,
MachineBasicBlock* PredBB);
+ void MaintainLiveIns(MachineBasicBlock *CurMBB,
+ MachineBasicBlock *NewMBB);
void ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst,
MachineBasicBlock *NewDest);
MachineBasicBlock *SplitMBBAt(MachineBasicBlock &CurMBB,
Modified: llvm/branches/type-system-rewrite/lib/CodeGen/InlineSpiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/CodeGen/InlineSpiller.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/CodeGen/InlineSpiller.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/CodeGen/InlineSpiller.cpp Thu Jul 7 23:45:15 2011
@@ -425,6 +425,7 @@
// Check possible sibling copies.
if (VNI->isPHIDef() || VNI->getCopy()) {
VNInfo *OrigVNI = OrigLI.getVNInfoAt(VNI->def);
+ assert(OrigVNI && "Def outside original live range");
if (OrigVNI->def != VNI->def)
DefMI = traceSiblingValue(Reg, VNI, OrigVNI);
}
Modified: llvm/branches/type-system-rewrite/lib/CodeGen/IntrinsicLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/CodeGen/IntrinsicLowering.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/CodeGen/IntrinsicLowering.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/CodeGen/IntrinsicLowering.cpp Thu Jul 7 23:45:15 2011
@@ -353,6 +353,13 @@
report_fatal_error("Code generator does not support intrinsic function '"+
Callee->getName()+"'!");
+ case Intrinsic::expect: {
+ // Just replace __builtin_expect(exp, c) with EXP.
+ Value *V = CI->getArgOperand(0);
+ CI->replaceAllUsesWith(V);
+ break;
+ }
+
// The setjmp/longjmp intrinsics should only exist in the code if it was
// never optimized (ie, right out of the CFE), or if it has been hacked on
// by the lowerinvoke pass. In both cases, the right thing to do is to
Modified: llvm/branches/type-system-rewrite/lib/CodeGen/LLVMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/CodeGen/LLVMTargetMachine.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/CodeGen/LLVMTargetMachine.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/CodeGen/LLVMTargetMachine.cpp Thu Jul 7 23:45:15 2011
@@ -98,10 +98,10 @@
EnableFastISelOption("fast-isel", cl::Hidden,
cl::desc("Enable the \"fast\" instruction selector"));
-LLVMTargetMachine::LLVMTargetMachine(const Target &T,
- const std::string &Triple)
- : TargetMachine(T), TargetTriple(Triple) {
- AsmInfo = T.createAsmInfo(TargetTriple);
+LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple,
+ StringRef CPU, StringRef FS)
+ : TargetMachine(T, Triple, CPU, FS) {
+ AsmInfo = T.createAsmInfo(Triple);
}
// Set the default code model for the JIT for a generic target.
@@ -136,14 +136,14 @@
default: return true;
case CGFT_AssemblyFile: {
MCInstPrinter *InstPrinter =
- getTarget().createMCInstPrinter(*this, MAI.getAssemblerDialect(), MAI);
+ getTarget().createMCInstPrinter(MAI.getAssemblerDialect(), MAI);
// Create a code emitter if asked to show the encoding.
MCCodeEmitter *MCE = 0;
TargetAsmBackend *TAB = 0;
if (ShowMCEncoding) {
MCE = getTarget().createCodeEmitter(*this, *Context);
- TAB = getTarget().createAsmBackend(TargetTriple);
+ TAB = getTarget().createAsmBackend(getTargetTriple());
}
MCStreamer *S = getTarget().createAsmStreamer(*Context, Out,
@@ -160,12 +160,12 @@
// Create the code emitter for the target if it exists. If not, .o file
// emission fails.
MCCodeEmitter *MCE = getTarget().createCodeEmitter(*this, *Context);
- TargetAsmBackend *TAB = getTarget().createAsmBackend(TargetTriple);
+ TargetAsmBackend *TAB = getTarget().createAsmBackend(getTargetTriple());
if (MCE == 0 || TAB == 0)
return true;
- AsmStreamer.reset(getTarget().createObjectStreamer(TargetTriple, *Context,
- *TAB, Out, MCE,
+ AsmStreamer.reset(getTarget().createObjectStreamer(getTargetTriple(),
+ *Context, *TAB, Out, MCE,
hasMCRelaxAll(),
hasMCNoExecStack()));
AsmStreamer.get()->InitSections();
@@ -241,12 +241,12 @@
// Create the code emitter for the target if it exists. If not, .o file
// emission fails.
MCCodeEmitter *MCE = getTarget().createCodeEmitter(*this, *Ctx);
- TargetAsmBackend *TAB = getTarget().createAsmBackend(TargetTriple);
+ TargetAsmBackend *TAB = getTarget().createAsmBackend(getTargetTriple());
if (MCE == 0 || TAB == 0)
return true;
OwningPtr<MCStreamer> AsmStreamer;
- AsmStreamer.reset(getTarget().createObjectStreamer(TargetTriple, *Ctx,
+ AsmStreamer.reset(getTarget().createObjectStreamer(getTargetTriple(), *Ctx,
*TAB, Out, MCE,
hasMCRelaxAll(),
hasMCNoExecStack()));
@@ -303,10 +303,6 @@
if (!DisableVerify)
PM.add(createVerifierPass());
- // Simplify ObjC ARC code. This is done late because it makes re-optimization
- // difficult.
- PM.add(createObjCARCContractPass());
-
// Run loop strength reduction before anything else.
if (OptLevel != CodeGenOpt::None && !DisableLSR) {
PM.add(createLoopStrengthReducePass(getTargetLowering()));
@@ -388,6 +384,12 @@
// Expand pseudo-instructions emitted by ISel.
PM.add(createExpandISelPseudosPass());
+ // Pre-ra tail duplication.
+ if (OptLevel != CodeGenOpt::None && !DisableEarlyTailDup) {
+ PM.add(createTailDuplicatePass(true));
+ printAndVerify(PM, "After Pre-RegAlloc TailDuplicate");
+ }
+
// Optimize PHIs before DCE: removing dead PHI cycles may make more
// instructions dead.
if (OptLevel != CodeGenOpt::None)
@@ -416,12 +418,6 @@
printAndVerify(PM, "After codegen peephole optimization pass");
}
- // Pre-ra tail duplication.
- if (OptLevel != CodeGenOpt::None && !DisableEarlyTailDup) {
- PM.add(createTailDuplicatePass(true));
- printAndVerify(PM, "After Pre-RegAlloc TailDuplicate");
- }
-
// Run pre-ra passes.
if (addPreRegAlloc(PM, OptLevel))
printAndVerify(PM, "After PreRegAlloc passes");
Modified: llvm/branches/type-system-rewrite/lib/CodeGen/LiveDebugVariables.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/CodeGen/LiveDebugVariables.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/CodeGen/LiveDebugVariables.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/CodeGen/LiveDebugVariables.cpp Thu Jul 7 23:45:15 2011
@@ -123,7 +123,7 @@
/// getNext - Return the next UserValue in the equivalence class.
UserValue *getNext() const { return next; }
- /// match - Does this UserValue match the aprameters?
+ /// match - Does this UserValue match the parameters?
bool match(const MDNode *Var, unsigned Offset) const {
return Var == variable && Offset == offset;
}
Modified: llvm/branches/type-system-rewrite/lib/CodeGen/LiveRangeEdit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/CodeGen/LiveRangeEdit.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/CodeGen/LiveRangeEdit.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/CodeGen/LiveRangeEdit.cpp Thu Jul 7 23:45:15 2011
@@ -298,10 +298,16 @@
if (NumComp <= 1)
continue;
++NumFracRanges;
+ bool IsOriginal = VRM.getOriginal(LI->reg) == LI->reg;
DEBUG(dbgs() << NumComp << " components: " << *LI << '\n');
SmallVector<LiveInterval*, 8> Dups(1, LI);
for (unsigned i = 1; i != NumComp; ++i) {
Dups.push_back(&createFrom(LI->reg, LIS, VRM));
+ // If LI is an original interval that hasn't been split yet, make the new
+ // intervals their own originals instead of referring to LI. The original
+ // interval must contain all the split products, and LI doesn't.
+ if (IsOriginal)
+ VRM.setIsSplitFromReg(Dups.back()->reg, 0);
if (delegate_)
delegate_->LRE_DidCloneVirtReg(Dups.back()->reg, LI->reg);
}
Modified: llvm/branches/type-system-rewrite/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/CodeGen/MachineInstr.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/CodeGen/MachineInstr.cpp Thu Jul 7 23:45:15 2011
@@ -802,6 +802,11 @@
return false;
}
}
+ // If DebugLoc does not match then two dbg.values are not identical.
+ if (isDebugValue())
+ if (!getDebugLoc().isUnknown() && !Other->getDebugLoc().isUnknown()
+ && getDebugLoc() != Other->getDebugLoc())
+ return false;
return true;
}
Modified: llvm/branches/type-system-rewrite/lib/CodeGen/RegAllocGreedy.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/CodeGen/RegAllocGreedy.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/CodeGen/RegAllocGreedy.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/CodeGen/RegAllocGreedy.cpp Thu Jul 7 23:45:15 2011
@@ -649,8 +649,6 @@
for (;;) {
ArrayRef<unsigned> NewBundles = SpillPlacer->getRecentPositive();
- if (NewBundles.empty())
- break;
// Find new through blocks in the periphery of PrefRegBundles.
for (int i = 0, e = NewBundles.size(); i != e; ++i) {
unsigned Bundle = NewBundles[i];
@@ -670,12 +668,12 @@
}
}
// Any new blocks to add?
- if (ActiveBlocks.size() > AddedTo) {
- ArrayRef<unsigned> Add(&ActiveBlocks[AddedTo],
- ActiveBlocks.size() - AddedTo);
- addThroughConstraints(Intf, Add);
- AddedTo = ActiveBlocks.size();
- }
+ if (ActiveBlocks.size() == AddedTo)
+ break;
+ addThroughConstraints(Intf,
+ ArrayRef<unsigned>(ActiveBlocks).slice(AddedTo));
+ AddedTo = ActiveBlocks.size();
+
// Perhaps iterating can enable more bundles?
SpillPlacer->iterate();
}
@@ -812,9 +810,9 @@
tie(Start, Stop) = Indexes->getMBBRange(BI.MBB);
Intf.moveToBlock(BI.MBB->getNumber());
DEBUG(dbgs() << "EB#" << Bundles->getBundle(BI.MBB->getNumber(), 0)
- << (RegIn ? " => " : " -- ")
+ << (BI.LiveIn ? (RegIn ? " => " : " -> ") : " ")
<< "BB#" << BI.MBB->getNumber()
- << (RegOut ? " => " : " -- ")
+ << (BI.LiveOut ? (RegOut ? " => " : " -> ") : " ")
<< " EB#" << Bundles->getBundle(BI.MBB->getNumber(), 1)
<< " [" << Start << ';'
<< SA->getLastSplitPoint(BI.MBB->getNumber()) << '-' << Stop
@@ -958,7 +956,8 @@
//
// ~ Interference after last use.
// |---o---o--o| Live-out on stack, late last use.
- // =========____ Copy to stack after LSP, overlap MainIntv.
+ // ============ Copy to stack after LSP, overlap MainIntv.
+ // \_____ Stack interval is live-out.
//
if (!RegOut && Intf.first() > BI.LastUse.getBoundaryIndex()) {
assert(RegIn && "Stack-in, stack-out should already be handled");
@@ -998,8 +997,8 @@
// The interference is overlapping somewhere we wanted to use MainIntv. That
// means we need to create a local interval that can be allocated a
// different register.
- DEBUG(dbgs() << ", creating local interval.\n");
unsigned LocalIntv = SE->openIntv();
+ DEBUG(dbgs() << ", creating local interval " << LocalIntv << ".\n");
// We may be creating copies directly between MainIntv and LocalIntv,
// bypassing the stack interval. When we do that, we should never use the
@@ -1062,7 +1061,7 @@
// |---o-- Live-in in MainIntv.
// ====--- Switch to LocalIntv before interference.
//
- SlotIndex Switch = SE->enterIntvBefore(Intf.first());
+ SlotIndex Switch = SE->enterIntvBefore(std::min(Pos, Intf.first()));
assert(Switch <= Intf.first() && "Expected to avoid interference");
SE->useIntv(Switch, Pos);
SE->selectIntv(MainIntv);
@@ -1080,7 +1079,7 @@
// | o-- Defined in block.
// --- Begin LocalIntv at first use.
//
- SlotIndex Switch = SE->enterIntvBefore(BI.FirstUse);
+ SlotIndex Switch = SE->enterIntvBefore(std::min(Pos, BI.FirstUse));
SE->useIntv(Switch, Pos);
}
}
Modified: llvm/branches/type-system-rewrite/lib/CodeGen/RegisterCoalescer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/CodeGen/RegisterCoalescer.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/CodeGen/RegisterCoalescer.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/CodeGen/RegisterCoalescer.cpp Thu Jul 7 23:45:15 2011
@@ -1214,12 +1214,6 @@
unsigned Dst = MI->getOperand(0).getReg();
unsigned Src = MI->getOperand(1).getReg();
- // FIXME: If "B = X" kills X, we have to move the kill back to its
- // previous use. For now we just avoid the optimization in that case.
- LiveInterval &SrcInt = li.getInterval(Src);
- if (SrcInt.killedAt(VNI->def))
- return false;
-
if (!TargetRegisterInfo::isVirtualRegister(Src) ||
!TargetRegisterInfo::isVirtualRegister(Dst))
return false;
@@ -1253,6 +1247,7 @@
// If the copies use two different value numbers of X, we cannot merge
// A and B.
+ LiveInterval &SrcInt = li.getInterval(Src);
if (SrcInt.getVNInfoAt(Other->def) != SrcInt.getVNInfoAt(VNI->def))
return false;
@@ -1476,6 +1471,7 @@
if (RHSValNoAssignments.empty())
RHSValNoAssignments.push_back(-1);
+ SmallVector<unsigned, 8> SourceRegisters;
for (SmallVector<MachineInstr*, 8>::iterator I = DupCopies.begin(),
E = DupCopies.end(); I != E; ++I) {
MachineInstr *MI = *I;
@@ -1489,11 +1485,19 @@
// X = X
// and mark the X as coalesced to keep the illusion.
unsigned Src = MI->getOperand(1).getReg();
+ SourceRegisters.push_back(Src);
MI->getOperand(0).substVirtReg(Src, 0, *tri_);
markAsJoined(MI);
}
+ // If B = X was the last use of X in a liverange, we have to shrink it now
+ // that B = X is gone.
+ for (SmallVector<unsigned, 8>::iterator I = SourceRegisters.begin(),
+ E = SourceRegisters.end(); I != E; ++I) {
+ li_->shrinkToUses(&li_->getInterval(*I));
+ }
+
// If we get here, we know that we can coalesce the live ranges. Ask the
// intervals to coalesce themselves now.
LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo,
Modified: llvm/branches/type-system-rewrite/lib/CodeGen/ScheduleDAGEmit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/CodeGen/ScheduleDAGEmit.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/CodeGen/ScheduleDAGEmit.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/CodeGen/ScheduleDAGEmit.cpp Thu Jul 7 23:45:15 2011
@@ -45,6 +45,7 @@
unsigned Reg = 0;
for (SUnit::const_succ_iterator II = SU->Succs.begin(),
EE = SU->Succs.end(); II != EE; ++II) {
+ if (II->isCtrl()) continue; // ignore chain preds
if (II->getReg()) {
Reg = II->getReg();
break;
Modified: llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Jul 7 23:45:15 2011
@@ -5929,12 +5929,17 @@
// Now check for #3 and #4.
bool RealUse = false;
+
+ // Caches for hasPredecessorHelper
+ SmallPtrSet<const SDNode *, 32> Visited;
+ SmallVector<const SDNode *, 16> Worklist;
+
for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
E = Ptr.getNode()->use_end(); I != E; ++I) {
SDNode *Use = *I;
if (Use == N)
continue;
- if (Use->isPredecessorOf(N))
+ if (N->hasPredecessorHelper(Use, Visited, Worklist))
return false;
if (!((Use->getOpcode() == ISD::LOAD &&
Modified: llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Jul 7 23:45:15 2011
@@ -3326,13 +3326,13 @@
const TargetLowering &TLI) {
assert((SrcAlign == 0 || SrcAlign >= DstAlign) &&
"Expecting memcpy / memset source to meet alignment requirement!");
- // If 'SrcAlign' is zero, that means the memory operation does not need load
- // the value, i.e. memset or memcpy from constant string. Otherwise, it's
- // the inferred alignment of the source. 'DstAlign', on the other hand, is the
- // specified alignment of the memory operation. If it is zero, that means
- // it's possible to change the alignment of the destination. 'MemcpyStrSrc'
- // indicates whether the memcpy source is constant so it does not need to be
- // loaded.
+ // If 'SrcAlign' is zero, that means the memory operation does not need to
+ // load the value, i.e. memset or memcpy from constant string. Otherwise,
+ // it's the inferred alignment of the source. 'DstAlign', on the other hand,
+ // is the specified alignment of the memory operation. If it is zero, that
+ // means it's possible to change the alignment of the destination.
+ // 'MemcpyStrSrc' indicates whether the memcpy source is constant so it does
+ // not need to be loaded.
EVT VT = TLI.getOptimalMemOpType(Size, DstAlign, SrcAlign,
NonScalarIntSafe, MemcpyStrSrc,
DAG.getMachineFunction());
@@ -5691,24 +5691,39 @@
return false;
}
-/// isPredecessorOf - Return true if this node is a predecessor of N. This node
-/// is either an operand of N or it can be reached by traversing up the operands.
-/// NOTE: this is an expensive method. Use it carefully.
-bool SDNode::isPredecessorOf(SDNode *N) const {
- SmallPtrSet<SDNode *, 32> Visited;
- SmallVector<SDNode *, 16> Worklist;
- Worklist.push_back(N);
-
- do {
- N = Worklist.pop_back_val();
- for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
- SDNode *Op = N->getOperand(i).getNode();
- if (Op == this)
- return true;
+/// hasPredecessor - Return true if N is a predecessor of this node.
+/// N is either an operand of this node, or can be reached by recursively
+/// traversing up the operands.
+/// NOTE: This is an expensive method. Use it carefully.
+bool SDNode::hasPredecessor(const SDNode *N) const {
+ SmallPtrSet<const SDNode *, 32> Visited;
+ SmallVector<const SDNode *, 16> Worklist;
+ return hasPredecessorHelper(N, Visited, Worklist);
+}
+
+bool SDNode::hasPredecessorHelper(const SDNode *N,
+ SmallPtrSet<const SDNode *, 32> &Visited,
+ SmallVector<const SDNode *, 16> &Worklist) const {
+ if (Visited.empty()) {
+ Worklist.push_back(this);
+ } else {
+ // Take a look in the visited set. If we've already encountered this node
+ // we needn't search further.
+ if (Visited.count(N))
+ return true;
+ }
+
+ // Haven't visited N yet. Continue the search.
+ while (!Worklist.empty()) {
+ const SDNode *M = Worklist.pop_back_val();
+ for (unsigned i = 0, e = M->getNumOperands(); i != e; ++i) {
+ SDNode *Op = M->getOperand(i).getNode();
if (Visited.insert(Op))
Worklist.push_back(Op);
+ if (Op == N)
+ return true;
}
- } while (!Worklist.empty());
+ }
return false;
}
Modified: llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Thu Jul 7 23:45:15 2011
@@ -4771,6 +4771,13 @@
case Intrinsic::flt_rounds:
setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
return 0;
+
+ case Intrinsic::expect: {
+ // Just replace __builtin_expect(exp, c) with EXP.
+ setValue(&I, getValue(I.getArgOperand(0)));
+ return 0;
+ }
+
case Intrinsic::trap: {
StringRef TrapFuncName = getTrapFunctionName();
if (TrapFuncName.empty()) {
Modified: llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/CodeGen/SelectionDAG/TargetLowering.cpp Thu Jul 7 23:45:15 2011
@@ -2623,7 +2623,6 @@
TargetLowering::ConstraintType
TargetLowering::getConstraintType(const std::string &Constraint) const {
- // FIXME: lots more standard ones to handle.
if (Constraint.size() == 1) {
switch (Constraint[0]) {
default: break;
Modified: llvm/branches/type-system-rewrite/lib/CodeGen/TailDuplication.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/CodeGen/TailDuplication.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/CodeGen/TailDuplication.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/CodeGen/TailDuplication.cpp Thu Jul 7 23:45:15 2011
@@ -102,9 +102,15 @@
SmallVector<MachineBasicBlock*, 8> &TDBBs,
const DenseSet<unsigned> &RegsUsedByPhi,
SmallVector<MachineInstr*, 16> &Copies);
- bool TailDuplicate(MachineBasicBlock *TailBB, MachineFunction &MF,
+ bool TailDuplicate(MachineBasicBlock *TailBB,
+ bool IsSimple,
+ MachineFunction &MF,
SmallVector<MachineBasicBlock*, 8> &TDBBs,
SmallVector<MachineInstr*, 16> &Copies);
+ bool TailDuplicateAndUpdate(MachineBasicBlock *MBB,
+ bool IsSimple,
+ MachineFunction &MF);
+
void RemoveDeadBlock(MachineBasicBlock *MBB);
};
@@ -175,6 +181,109 @@
}
}
+/// TailDuplicateAndUpdate - Tail duplicate the block and cleanup.
+bool
+TailDuplicatePass::TailDuplicateAndUpdate(MachineBasicBlock *MBB,
+ bool IsSimple,
+ MachineFunction &MF) {
+ // Save the successors list.
+ SmallSetVector<MachineBasicBlock*, 8> Succs(MBB->succ_begin(),
+ MBB->succ_end());
+
+ SmallVector<MachineBasicBlock*, 8> TDBBs;
+ SmallVector<MachineInstr*, 16> Copies;
+ if (!TailDuplicate(MBB, IsSimple, MF, TDBBs, Copies))
+ return false;
+
+ ++NumTails;
+
+ SmallVector<MachineInstr*, 8> NewPHIs;
+ MachineSSAUpdater SSAUpdate(MF, &NewPHIs);
+
+ // TailBB's immediate successors are now successors of those predecessors
+ // which duplicated TailBB. Add the predecessors as sources to the PHI
+ // instructions.
+ bool isDead = MBB->pred_empty() && !MBB->hasAddressTaken();
+ if (PreRegAlloc)
+ UpdateSuccessorsPHIs(MBB, isDead, TDBBs, Succs);
+
+ // If it is dead, remove it.
+ if (isDead) {
+ NumInstrDups -= MBB->size();
+ RemoveDeadBlock(MBB);
+ ++NumDeadBlocks;
+ }
+
+ // Update SSA form.
+ if (!SSAUpdateVRs.empty()) {
+ for (unsigned i = 0, e = SSAUpdateVRs.size(); i != e; ++i) {
+ unsigned VReg = SSAUpdateVRs[i];
+ SSAUpdate.Initialize(VReg);
+
+ // If the original definition is still around, add it as an available
+ // value.
+ MachineInstr *DefMI = MRI->getVRegDef(VReg);
+ MachineBasicBlock *DefBB = 0;
+ if (DefMI) {
+ DefBB = DefMI->getParent();
+ SSAUpdate.AddAvailableValue(DefBB, VReg);
+ }
+
+ // Add the new vregs as available values.
+ DenseMap<unsigned, AvailableValsTy>::iterator LI =
+ SSAUpdateVals.find(VReg);
+ for (unsigned j = 0, ee = LI->second.size(); j != ee; ++j) {
+ MachineBasicBlock *SrcBB = LI->second[j].first;
+ unsigned SrcReg = LI->second[j].second;
+ SSAUpdate.AddAvailableValue(SrcBB, SrcReg);
+ }
+
+ // Rewrite uses that are outside of the original def's block.
+ MachineRegisterInfo::use_iterator UI = MRI->use_begin(VReg);
+ while (UI != MRI->use_end()) {
+ MachineOperand &UseMO = UI.getOperand();
+ MachineInstr *UseMI = &*UI;
+ ++UI;
+ if (UseMI->isDebugValue()) {
+ // SSAUpdate can replace the use with an undef. That creates
+ // a debug instruction that is a kill.
+ // FIXME: Should it SSAUpdate job to delete debug instructions
+ // instead of replacing the use with undef?
+ UseMI->eraseFromParent();
+ continue;
+ }
+ if (UseMI->getParent() == DefBB && !UseMI->isPHI())
+ continue;
+ SSAUpdate.RewriteUse(UseMO);
+ }
+ }
+
+ SSAUpdateVRs.clear();
+ SSAUpdateVals.clear();
+ }
+
+ // Eliminate some of the copies inserted by tail duplication to maintain
+ // SSA form.
+ for (unsigned i = 0, e = Copies.size(); i != e; ++i) {
+ MachineInstr *Copy = Copies[i];
+ if (!Copy->isCopy())
+ continue;
+ unsigned Dst = Copy->getOperand(0).getReg();
+ unsigned Src = Copy->getOperand(1).getReg();
+ MachineRegisterInfo::use_iterator UI = MRI->use_begin(Src);
+ if (++UI == MRI->use_end()) {
+ // Copy is the only use. Do trivial copy propagation here.
+ MRI->replaceRegWith(Dst, Src);
+ Copy->eraseFromParent();
+ }
+ }
+
+ if (NewPHIs.size())
+ NumAddedPHIs += NewPHIs.size();
+
+ return true;
+}
+
/// TailDuplicateBlocks - Look for small blocks that are unconditionally
/// branched to and do not fall through. Tail-duplicate their instructions
/// into their predecessors to eliminate (dynamic) branches.
@@ -186,108 +295,22 @@
VerifyPHIs(MF, true);
}
- SmallVector<MachineInstr*, 8> NewPHIs;
- MachineSSAUpdater SSAUpdate(MF, &NewPHIs);
-
for (MachineFunction::iterator I = ++MF.begin(), E = MF.end(); I != E; ) {
MachineBasicBlock *MBB = I++;
if (NumTails == TailDupLimit)
break;
- // Save the successors list.
- SmallSetVector<MachineBasicBlock*, 8> Succs(MBB->succ_begin(),
- MBB->succ_end());
-
- SmallVector<MachineBasicBlock*, 8> TDBBs;
- SmallVector<MachineInstr*, 16> Copies;
- if (TailDuplicate(MBB, MF, TDBBs, Copies)) {
- ++NumTails;
-
- // TailBB's immediate successors are now successors of those predecessors
- // which duplicated TailBB. Add the predecessors as sources to the PHI
- // instructions.
- bool isDead = MBB->pred_empty() && !MBB->hasAddressTaken();
- if (PreRegAlloc)
- UpdateSuccessorsPHIs(MBB, isDead, TDBBs, Succs);
-
- // If it is dead, remove it.
- if (isDead) {
- NumInstrDups -= MBB->size();
- RemoveDeadBlock(MBB);
- ++NumDeadBlocks;
- }
-
- // Update SSA form.
- if (!SSAUpdateVRs.empty()) {
- for (unsigned i = 0, e = SSAUpdateVRs.size(); i != e; ++i) {
- unsigned VReg = SSAUpdateVRs[i];
- SSAUpdate.Initialize(VReg);
-
- // If the original definition is still around, add it as an available
- // value.
- MachineInstr *DefMI = MRI->getVRegDef(VReg);
- MachineBasicBlock *DefBB = 0;
- if (DefMI) {
- DefBB = DefMI->getParent();
- SSAUpdate.AddAvailableValue(DefBB, VReg);
- }
-
- // Add the new vregs as available values.
- DenseMap<unsigned, AvailableValsTy>::iterator LI =
- SSAUpdateVals.find(VReg);
- for (unsigned j = 0, ee = LI->second.size(); j != ee; ++j) {
- MachineBasicBlock *SrcBB = LI->second[j].first;
- unsigned SrcReg = LI->second[j].second;
- SSAUpdate.AddAvailableValue(SrcBB, SrcReg);
- }
-
- // Rewrite uses that are outside of the original def's block.
- MachineRegisterInfo::use_iterator UI = MRI->use_begin(VReg);
- while (UI != MRI->use_end()) {
- MachineOperand &UseMO = UI.getOperand();
- MachineInstr *UseMI = &*UI;
- ++UI;
- if (UseMI->isDebugValue()) {
- // SSAUpdate can replace the use with an undef. That creates
- // a debug instruction that is a kill.
- // FIXME: Should it SSAUpdate job to delete debug instructions
- // instead of replacing the use with undef?
- UseMI->eraseFromParent();
- continue;
- }
- if (UseMI->getParent() == DefBB && !UseMI->isPHI())
- continue;
- SSAUpdate.RewriteUse(UseMO);
- }
- }
-
- SSAUpdateVRs.clear();
- SSAUpdateVals.clear();
- }
+ bool IsSimple = isSimpleBB(MBB);
- // Eliminate some of the copies inserted by tail duplication to maintain
- // SSA form.
- for (unsigned i = 0, e = Copies.size(); i != e; ++i) {
- MachineInstr *Copy = Copies[i];
- if (!Copy->isCopy())
- continue;
- unsigned Dst = Copy->getOperand(0).getReg();
- unsigned Src = Copy->getOperand(1).getReg();
- MachineRegisterInfo::use_iterator UI = MRI->use_begin(Src);
- if (++UI == MRI->use_end()) {
- // Copy is the only use. Do trivial copy propagation here.
- MRI->replaceRegWith(Dst, Src);
- Copy->eraseFromParent();
- }
- }
+ if (!shouldTailDuplicate(MF, IsSimple, *MBB))
+ continue;
- if (PreRegAlloc && TailDupVerify)
- VerifyPHIs(MF, false);
- MadeChange = true;
- }
+ MadeChange |= TailDuplicateAndUpdate(MBB, IsSimple, MF);
}
- NumAddedPHIs += NewPHIs.size();
+
+ if (PreRegAlloc && TailDupVerify)
+ VerifyPHIs(MF, false);
return MadeChange;
}
@@ -527,14 +550,12 @@
// to allow undoing the effects of tail merging and other optimizations
// that rearrange the predecessors of the indirect branch.
- bool hasIndirectBR = false;
- if (PreRegAlloc && !TailBB.empty()) {
- const MCInstrDesc &MCID = TailBB.back().getDesc();
- if (MCID.isIndirectBranch()) {
- MaxDuplicateCount = 20;
- hasIndirectBR = true;
- }
- }
+ bool HasIndirectbr = false;
+ if (!TailBB.empty())
+ HasIndirectbr = TailBB.back().getDesc().isIndirectBranch();
+
+ if (HasIndirectbr && PreRegAlloc)
+ MaxDuplicateCount = 20;
// Check the instructions in the block to determine whether tail-duplication
// is invalid or unlikely to be profitable.
@@ -564,7 +585,7 @@
return false;
}
- if (hasIndirectBR)
+ if (HasIndirectbr && PreRegAlloc)
return true;
if (IsSimple)
@@ -706,14 +727,11 @@
/// TailDuplicate - If it is profitable, duplicate TailBB's contents in each
/// of its predecessors.
bool
-TailDuplicatePass::TailDuplicate(MachineBasicBlock *TailBB, MachineFunction &MF,
+TailDuplicatePass::TailDuplicate(MachineBasicBlock *TailBB,
+ bool IsSimple,
+ MachineFunction &MF,
SmallVector<MachineBasicBlock*, 8> &TDBBs,
SmallVector<MachineInstr*, 16> &Copies) {
- bool IsSimple = isSimpleBB(TailBB);
-
- if (!shouldTailDuplicate(MF, IsSimple, *TailBB))
- return false;
-
DEBUG(dbgs() << "\n*** Tail-duplicating BB#" << TailBB->getNumber() << '\n');
DenseSet<unsigned> UsedByPhi;
Modified: llvm/branches/type-system-rewrite/lib/MC/MCAsmInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/MC/MCAsmInfo.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/MC/MCAsmInfo.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/MC/MCAsmInfo.cpp Thu Jul 7 23:45:15 2011
@@ -78,6 +78,7 @@
DwarfRequiresRelocationForSectionOffset = true;
DwarfSectionOffsetDirective = 0;
DwarfUsesLabelOffsetForRanges = true;
+ DwarfRegNumForCFI = false;
HasMicrosoftFastStdCallMangling = false;
AsmTransCBE = 0;
Modified: llvm/branches/type-system-rewrite/lib/MC/MCAsmStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/MC/MCAsmStreamer.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/MC/MCAsmStreamer.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/MC/MCAsmStreamer.cpp Thu Jul 7 23:45:15 2011
@@ -825,7 +825,7 @@
}
void MCAsmStreamer::EmitRegisterName(int64_t Register) {
- if (InstPrinter) {
+ if (InstPrinter && !MAI.useDwarfRegNumForCFI()) {
const TargetAsmInfo &asmInfo = getContext().getTargetAsmInfo();
unsigned LLVMRegister = asmInfo.getLLVMRegNum(Register, true);
InstPrinter->printRegName(OS, LLVMRegister);
Modified: llvm/branches/type-system-rewrite/lib/MC/MCDisassembler/Disassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/MC/MCDisassembler/Disassembler.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/MC/MCDisassembler/Disassembler.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/MC/MCDisassembler/Disassembler.cpp Thu Jul 7 23:45:15 2011
@@ -79,7 +79,7 @@
// Set up the instruction printer.
int AsmPrinterVariant = MAI->getAssemblerDialect();
- MCInstPrinter *IP = TheTarget->createMCInstPrinter(*TM, AsmPrinterVariant,
+ MCInstPrinter *IP = TheTarget->createMCInstPrinter(AsmPrinterVariant,
*MAI);
assert(IP && "Unable to create instruction printer!");
Modified: llvm/branches/type-system-rewrite/lib/MC/MCDisassembler/EDDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/MC/MCDisassembler/EDDisassembler.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/MC/MCDisassembler/EDDisassembler.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/MC/MCDisassembler/EDDisassembler.cpp Thu Jul 7 23:45:15 2011
@@ -171,7 +171,7 @@
std::string featureString;
TargetMachine.reset(Tgt->createTargetMachine(tripleString, CPU,
featureString));
-
+
const TargetRegisterInfo *registerInfo = TargetMachine->getRegisterInfo();
if (!registerInfo)
@@ -183,7 +183,7 @@
if (!AsmInfo)
return;
-
+
Disassembler.reset(Tgt->createMCDisassembler());
if (!Disassembler)
@@ -193,8 +193,7 @@
InstString.reset(new std::string);
InstStream.reset(new raw_string_ostream(*InstString));
- InstPrinter.reset(Tgt->createMCInstPrinter(*TargetMachine, LLVMSyntaxVariant,
- *AsmInfo));
+ InstPrinter.reset(Tgt->createMCInstPrinter(LLVMSyntaxVariant, *AsmInfo));
if (!InstPrinter)
return;
@@ -372,8 +371,10 @@
OwningPtr<MCAsmParser> genericParser(createMCAsmParser(*Tgt, sourceMgr,
context, *streamer,
*AsmInfo));
- OwningPtr<TargetAsmParser> TargetParser(Tgt->createAsmParser(*genericParser,
- *TargetMachine));
+
+ StringRef triple = tripleFromArch(Key.Arch);
+ OwningPtr<TargetAsmParser> TargetParser(Tgt->createAsmParser(triple, "", "",
+ *genericParser));
AsmToken OpcodeToken = genericParser->Lex();
AsmToken NextToken = genericParser->Lex(); // consume next token, because specificParser expects us to
Modified: llvm/branches/type-system-rewrite/lib/MC/MCDisassembler/EDDisassembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/MC/MCDisassembler/EDDisassembler.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/MC/MCDisassembler/EDDisassembler.h (original)
+++ llvm/branches/type-system-rewrite/lib/MC/MCDisassembler/EDDisassembler.h Thu Jul 7 23:45:15 2011
@@ -41,6 +41,7 @@
class MCInst;
class MCParsedAsmOperand;
class MCStreamer;
+class MCSubtargetInfo;
template <typename T> class SmallVectorImpl;
class SourceMgr;
class Target;
Modified: llvm/branches/type-system-rewrite/lib/MC/MCDwarf.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/MC/MCDwarf.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/MC/MCDwarf.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/MC/MCDwarf.cpp Thu Jul 7 23:45:15 2011
@@ -7,22 +7,21 @@
//
//===----------------------------------------------------------------------===//
-#include "llvm/ADT/FoldingSet.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCDwarf.h"
-#include "llvm/MC/MCAssembler.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCObjectWriter.h"
-#include "llvm/ADT/SmallString.h"
-#include "llvm/ADT/Twine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetAsmBackend.h"
#include "llvm/Target/TargetAsmInfo.h"
+#include "llvm/ADT/FoldingSet.h"
+#include "llvm/ADT/SmallString.h"
+#include "llvm/ADT/StringExtras.h"
+#include "llvm/ADT/Twine.h"
using namespace llvm;
// Given a special op, return the address skip amount (in units of
@@ -500,7 +499,6 @@
bool UsingCFI;
bool IsEH;
const MCSymbol *SectionStart;
-
public:
FrameEmitterImpl(bool usingCFI, bool isEH, const MCSymbol *sectionStart) :
CFAOffset(0), CIENum(0), UsingCFI(usingCFI), IsEH(isEH),
@@ -715,6 +713,11 @@
// .quad __gxx_personality
// .quad except_tab1
+ uint32_t Encoding =
+ TAI.getCompactUnwindEncoding(Frame.Instructions,
+ getDataAlignmentFactor(Streamer), IsEH);
+ if (!Encoding) return false;
+
Streamer.SwitchSection(TAI.getCompactUnwindSection());
// Range Start
@@ -729,12 +732,10 @@
if (VerboseAsm) Streamer.AddComment("Range Length");
Streamer.EmitAbsValue(Range, 4);
- // FIXME:
// Compact Encoding
- const std::vector<MachineMove> &Moves = TAI.getInitialFrameState();
- uint32_t Encoding = 0;
Size = getSizeForEncoding(Streamer, dwarf::DW_EH_PE_udata4);
- if (VerboseAsm) Streamer.AddComment("Compact Unwind Encoding");
+ if (VerboseAsm) Streamer.AddComment(Twine("Compact Unwind Encoding: 0x") +
+ Twine(llvm::utohexstr(Encoding)));
Streamer.EmitIntValue(Encoding, Size);
// Personality Function
@@ -775,7 +776,7 @@
streamer.EmitLabel(sectionStart);
CIENum++;
- MCSymbol *sectionEnd = streamer.getContext().CreateTempSymbol();
+ MCSymbol *sectionEnd = context.CreateTempSymbol();
// Length
const MCExpr *Length = MakeStartMinusEndExpr(streamer, *sectionStart,
Modified: llvm/branches/type-system-rewrite/lib/MC/MCSubtargetInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/MC/MCSubtargetInfo.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/MC/MCSubtargetInfo.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/MC/MCSubtargetInfo.cpp Thu Jul 7 23:45:15 2011
@@ -16,6 +16,38 @@
using namespace llvm;
+void MCSubtargetInfo::InitMCSubtargetInfo(StringRef CPU, StringRef FS,
+ const SubtargetFeatureKV *PF,
+ const SubtargetFeatureKV *PD,
+ const SubtargetInfoKV *PI,
+ const InstrStage *IS,
+ const unsigned *OC,
+ const unsigned *FP,
+ unsigned NF, unsigned NP) {
+ ProcFeatures = PF;
+ ProcDesc = PD;
+ ProcItins = PI;
+ Stages = IS;
+ OperandCycles = OC;
+ ForwardingPathes = FP;
+ NumFeatures = NF;
+ NumProcs = NP;
+
+ SubtargetFeatures Features(FS);
+ FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs,
+ ProcFeatures, NumFeatures);
+}
+
+
+/// ReInitMCSubtargetInfo - Change CPU (and optionally supplemented with
+/// feature string) and recompute feature bits.
+uint64_t MCSubtargetInfo::ReInitMCSubtargetInfo(StringRef CPU, StringRef FS) {
+ SubtargetFeatures Features(FS);
+ FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs,
+ ProcFeatures, NumFeatures);
+ return FeatureBits;
+}
+
InstrItineraryData
MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
assert(ProcItins && "Instruction itineraries information not available!");
@@ -42,11 +74,3 @@
return InstrItineraryData(Stages, OperandCycles, ForwardingPathes,
(InstrItinerary *)Found->Value);
}
-
-/// getFeatureBits - Get the feature bits for a CPU (optionally supplemented
-/// with feature string).
-uint64_t MCSubtargetInfo::getFeatureBits(StringRef CPU, StringRef FS) const {
- SubtargetFeatures Features(FS);
- return Features.getFeatureBits(CPU, ProcDesc, NumProcs,
- ProcFeatures, NumFeatures);
-}
Modified: llvm/branches/type-system-rewrite/lib/MC/SubtargetFeature.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/MC/SubtargetFeature.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/MC/SubtargetFeature.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/MC/SubtargetFeature.cpp Thu Jul 7 23:45:15 2011
@@ -231,8 +231,9 @@
size_t CPUTableSize,
const SubtargetFeatureKV *FeatureTable,
size_t FeatureTableSize) {
- assert(CPUTable && "missing CPU table");
- assert(FeatureTable && "missing features table");
+ if (!FeatureTableSize || !CPUTableSize)
+ return 0;
+
#ifndef NDEBUG
for (size_t i = 1; i < CPUTableSize; i++) {
assert(strcmp(CPUTable[i - 1].Key, CPUTable[i].Key) < 0 &&
@@ -249,24 +250,27 @@
if (CPU == "help")
Help(CPUTable, CPUTableSize, FeatureTable, FeatureTableSize);
- // Find CPU entry
- const SubtargetFeatureKV *CPUEntry = Find(CPU, CPUTable, CPUTableSize);
- // If there is a match
- if (CPUEntry) {
- // Set base feature bits
- Bits = CPUEntry->Value;
-
- // Set the feature implied by this CPU feature, if any.
- for (size_t i = 0; i < FeatureTableSize; ++i) {
- const SubtargetFeatureKV &FE = FeatureTable[i];
- if (CPUEntry->Value & FE.Value)
- SetImpliedBits(Bits, &FE, FeatureTable, FeatureTableSize);
+ // Find CPU entry if CPU name is specified.
+ if (!CPU.empty()) {
+ const SubtargetFeatureKV *CPUEntry = Find(CPU, CPUTable, CPUTableSize);
+ // If there is a match
+ if (CPUEntry) {
+ // Set base feature bits
+ Bits = CPUEntry->Value;
+
+ // Set the feature implied by this CPU feature, if any.
+ for (size_t i = 0; i < FeatureTableSize; ++i) {
+ const SubtargetFeatureKV &FE = FeatureTable[i];
+ if (CPUEntry->Value & FE.Value)
+ SetImpliedBits(Bits, &FE, FeatureTable, FeatureTableSize);
+ }
+ } else {
+ errs() << "'" << CPU
+ << "' is not a recognized processor for this target"
+ << " (ignoring processor)\n";
}
- } else {
- errs() << "'" << CPU
- << "' is not a recognized processor for this target"
- << " (ignoring processor)\n";
}
+
// Iterate through each feature
for (size_t i = 0, E = Features.size(); i < E; i++) {
const StringRef Feature = Features[i];
Modified: llvm/branches/type-system-rewrite/lib/Object/COFFObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Object/COFFObjectFile.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Object/COFFObjectFile.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Object/COFFObjectFile.cpp Thu Jul 7 23:45:15 2011
@@ -117,7 +117,7 @@
error_code COFFObjectFile::getSymbolAddress(DataRefImpl Symb,
uint64_t &Result) const {
const coff_symbol *symb = toSymb(Symb);
- const coff_section *Section;
+ const coff_section *Section = NULL;
if (error_code ec = getSection(symb->SectionNumber, Section))
return ec;
char Type;
@@ -138,7 +138,7 @@
// in the same section as this symbol, and looking for either the next
// symbol, or the end of the section.
const coff_symbol *symb = toSymb(Symb);
- const coff_section *Section;
+ const coff_section *Section = NULL;
if (error_code ec = getSection(symb->SectionNumber, Section))
return ec;
char Type;
@@ -171,7 +171,7 @@
uint32_t Characteristics = 0;
if (symb->SectionNumber > 0) {
- const coff_section *Section;
+ const coff_section *Section = NULL;
if (error_code ec = getSection(symb->SectionNumber, Section))
return ec;
Characteristics = Section->Characteristics;
@@ -309,8 +309,7 @@
if (!checkSize(Data, ec, 0x3c + 8)) return;
HeaderStart += *reinterpret_cast<const ulittle32_t *>(base() + 0x3c);
// Check the PE header. ("PE\0\0")
- if (StringRef(reinterpret_cast<const char *>(base() + HeaderStart), 4)
- != "PE\0\0") {
+ if (std::memcmp(base() + HeaderStart, "PE\0\0", 4) != 0) {
ec = object_error::parse_failed;
return;
}
Modified: llvm/branches/type-system-rewrite/lib/Support/Triple.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Support/Triple.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Support/Triple.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Support/Triple.cpp Thu Jul 7 23:45:15 2011
@@ -282,7 +282,8 @@
return cellspu;
else if (ArchName == "msp430")
return msp430;
- else if (ArchName == "mips" || ArchName == "mipsallegrex")
+ else if (ArchName == "mips" || ArchName == "mipseb" ||
+ ArchName == "mipsallegrex")
return mips;
else if (ArchName == "mipsel" || ArchName == "mipsallegrexel" ||
ArchName == "psp")
@@ -351,6 +352,8 @@
return Haiku;
else if (OSName.startswith("minix"))
return Minix;
+ else if (OSName.startswith("rtems"))
+ return RTEMS;
else
return UnknownOS;
}
Modified: llvm/branches/type-system-rewrite/lib/Support/Unix/Path.inc
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Support/Unix/Path.inc?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Support/Unix/Path.inc (original)
+++ llvm/branches/type-system-rewrite/lib/Support/Unix/Path.inc Thu Jul 7 23:45:15 2011
@@ -842,6 +842,9 @@
// Save the name
path = FNBuffer;
+
+ // By default mkstemp sets the mode to 0600, so update mode bits now.
+ AddPermissionBits (*this, 0666);
#elif defined(HAVE_MKTEMP)
// If we don't have mkstemp, use the old and obsolete mktemp function.
if (mktemp(FNBuffer) == 0)
Modified: llvm/branches/type-system-rewrite/lib/Target/ARM/ARM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/ARM/ARM.td?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/ARM/ARM.td (original)
+++ llvm/branches/type-system-rewrite/lib/Target/ARM/ARM.td Thu Jul 7 23:45:15 2011
@@ -16,18 +16,26 @@
include "llvm/Target/Target.td"
+//===----------------------------------------------------------------------===//
+// ARM Subtarget state.
+//
+
+def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
+ "Thumb mode">;
//===----------------------------------------------------------------------===//
// ARM Subtarget features.
//
-def FeatureVFP2 : SubtargetFeature<"vfp2", "ARMFPUType", "VFPv2",
+def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
"Enable VFP2 instructions">;
-def FeatureVFP3 : SubtargetFeature<"vfp3", "ARMFPUType", "VFPv3",
- "Enable VFP3 instructions">;
-def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON",
- "Enable NEON instructions">;
-def FeatureThumb2 : SubtargetFeature<"thumb2", "ThumbMode", "Thumb2",
+def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
+ "Enable VFP3 instructions",
+ [FeatureVFP2]>;
+def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
+ "Enable NEON instructions",
+ [FeatureVFP3]>;
+def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
"Enable Thumb2 instructions">;
def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
"Does not support ARM mode execution">;
@@ -83,34 +91,24 @@
def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
"Supports Multiprocessing extension">;
-// ARM architectures.
-def ArchV4T : SubtargetFeature<"v4t", "ARMArchVersion", "V4T",
- "ARM v4T">;
-def ArchV5T : SubtargetFeature<"v5t", "ARMArchVersion", "V5T",
- "ARM v5T">;
-def ArchV5TE : SubtargetFeature<"v5te", "ARMArchVersion", "V5TE",
- "ARM v5TE, v5TEj, v5TExp">;
-def ArchV6 : SubtargetFeature<"v6", "ARMArchVersion", "V6",
- "ARM v6">;
-def ArchV6M : SubtargetFeature<"v6m", "ARMArchVersion", "V6M",
- "ARM v6m",
- [FeatureNoARM, FeatureDB]>;
-def ArchV6T2 : SubtargetFeature<"v6t2", "ARMArchVersion", "V6T2",
- "ARM v6t2",
- [FeatureThumb2, FeatureDSPThumb2]>;
-def ArchV7A : SubtargetFeature<"v7a", "ARMArchVersion", "V7A",
- "ARM v7A",
- [FeatureThumb2, FeatureNEON, FeatureDB,
- FeatureDSPThumb2]>;
-def ArchV7M : SubtargetFeature<"v7m", "ARMArchVersion", "V7M",
- "ARM v7M",
- [FeatureThumb2, FeatureNoARM, FeatureDB,
- FeatureHWDiv]>;
-def ArchV7EM : SubtargetFeature<"v7em", "ARMArchVersion", "V7EM",
- "ARM v7E-M",
- [FeatureThumb2, FeatureNoARM, FeatureDB,
- FeatureHWDiv, FeatureDSPThumb2,
- FeatureT2XtPk]>;
+// ARM ISAs.
+def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
+ "Support ARM v4T instructions">;
+def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true",
+ "Support ARM v5T instructions",
+ [HasV4TOps]>;
+def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true",
+ "Support ARM v5TE, v5TEj, and v5TExp instructions",
+ [HasV5TOps]>;
+def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
+ "Support ARM v6 instructions",
+ [HasV5TEOps]>;
+def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
+ "Support ARM v6t2 instructions",
+ [HasV6Ops, FeatureThumb2, FeatureDSPThumb2]>;
+def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
+ "Support ARM v7 instructions",
+ [HasV6T2Ops]>;
//===----------------------------------------------------------------------===//
// ARM Processors supported.
@@ -119,8 +117,6 @@
include "ARMSchedule.td"
// ARM processor families.
-def ProcOthers : SubtargetFeature<"others", "ARMProcFamily", "Others",
- "One of the other ARM processor families">;
def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
"Cortex-A8 ARM processors",
[FeatureSlowFPBrcc, FeatureNEONForFP,
@@ -145,64 +141,76 @@
def : ProcNoItin<"strongarm1110", []>;
// V4T Processors.
-def : ProcNoItin<"arm7tdmi", [ArchV4T]>;
-def : ProcNoItin<"arm7tdmi-s", [ArchV4T]>;
-def : ProcNoItin<"arm710t", [ArchV4T]>;
-def : ProcNoItin<"arm720t", [ArchV4T]>;
-def : ProcNoItin<"arm9", [ArchV4T]>;
-def : ProcNoItin<"arm9tdmi", [ArchV4T]>;
-def : ProcNoItin<"arm920", [ArchV4T]>;
-def : ProcNoItin<"arm920t", [ArchV4T]>;
-def : ProcNoItin<"arm922t", [ArchV4T]>;
-def : ProcNoItin<"arm940t", [ArchV4T]>;
-def : ProcNoItin<"ep9312", [ArchV4T]>;
+def : ProcNoItin<"arm7tdmi", [HasV4TOps]>;
+def : ProcNoItin<"arm7tdmi-s", [HasV4TOps]>;
+def : ProcNoItin<"arm710t", [HasV4TOps]>;
+def : ProcNoItin<"arm720t", [HasV4TOps]>;
+def : ProcNoItin<"arm9", [HasV4TOps]>;
+def : ProcNoItin<"arm9tdmi", [HasV4TOps]>;
+def : ProcNoItin<"arm920", [HasV4TOps]>;
+def : ProcNoItin<"arm920t", [HasV4TOps]>;
+def : ProcNoItin<"arm922t", [HasV4TOps]>;
+def : ProcNoItin<"arm940t", [HasV4TOps]>;
+def : ProcNoItin<"ep9312", [HasV4TOps]>;
// V5T Processors.
-def : ProcNoItin<"arm10tdmi", [ArchV5T]>;
-def : ProcNoItin<"arm1020t", [ArchV5T]>;
+def : ProcNoItin<"arm10tdmi", [HasV5TOps]>;
+def : ProcNoItin<"arm1020t", [HasV5TOps]>;
// V5TE Processors.
-def : ProcNoItin<"arm9e", [ArchV5TE]>;
-def : ProcNoItin<"arm926ej-s", [ArchV5TE]>;
-def : ProcNoItin<"arm946e-s", [ArchV5TE]>;
-def : ProcNoItin<"arm966e-s", [ArchV5TE]>;
-def : ProcNoItin<"arm968e-s", [ArchV5TE]>;
-def : ProcNoItin<"arm10e", [ArchV5TE]>;
-def : ProcNoItin<"arm1020e", [ArchV5TE]>;
-def : ProcNoItin<"arm1022e", [ArchV5TE]>;
-def : ProcNoItin<"xscale", [ArchV5TE]>;
-def : ProcNoItin<"iwmmxt", [ArchV5TE]>;
+def : ProcNoItin<"arm9e", [HasV5TEOps]>;
+def : ProcNoItin<"arm926ej-s", [HasV5TEOps]>;
+def : ProcNoItin<"arm946e-s", [HasV5TEOps]>;
+def : ProcNoItin<"arm966e-s", [HasV5TEOps]>;
+def : ProcNoItin<"arm968e-s", [HasV5TEOps]>;
+def : ProcNoItin<"arm10e", [HasV5TEOps]>;
+def : ProcNoItin<"arm1020e", [HasV5TEOps]>;
+def : ProcNoItin<"arm1022e", [HasV5TEOps]>;
+def : ProcNoItin<"xscale", [HasV5TEOps]>;
+def : ProcNoItin<"iwmmxt", [HasV5TEOps]>;
// V6 Processors.
-def : Processor<"arm1136j-s", ARMV6Itineraries, [ArchV6]>;
-def : Processor<"arm1136jf-s", ARMV6Itineraries, [ArchV6, FeatureVFP2,
+def : Processor<"arm1136j-s", ARMV6Itineraries, [HasV6Ops]>;
+def : Processor<"arm1136jf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
FeatureHasSlowFPVMLx]>;
-def : Processor<"arm1176jz-s", ARMV6Itineraries, [ArchV6]>;
-def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ArchV6, FeatureVFP2,
+def : Processor<"arm1176jz-s", ARMV6Itineraries, [HasV6Ops]>;
+def : Processor<"arm1176jzf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
FeatureHasSlowFPVMLx]>;
-def : Processor<"mpcorenovfp", ARMV6Itineraries, [ArchV6]>;
-def : Processor<"mpcore", ARMV6Itineraries, [ArchV6, FeatureVFP2,
+def : Processor<"mpcorenovfp", ARMV6Itineraries, [HasV6Ops]>;
+def : Processor<"mpcore", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
FeatureHasSlowFPVMLx]>;
// V6M Processors.
-def : Processor<"cortex-m0", ARMV6Itineraries, [ArchV6M]>;
+def : Processor<"cortex-m0", ARMV6Itineraries, [HasV6Ops, FeatureNoARM,
+ FeatureDB]>;
// V6T2 Processors.
-def : Processor<"arm1156t2-s", ARMV6Itineraries, [ArchV6T2]>;
-def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ArchV6T2, FeatureVFP2,
+def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops]>;
+def : Processor<"arm1156t2f-s", ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
FeatureHasSlowFPVMLx]>;
-// V7 Processors.
+// V7a Processors.
def : Processor<"cortex-a8", CortexA8Itineraries,
- [ArchV7A, ProcA8]>;
+ [ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
+ FeatureDSPThumb2]>;
def : Processor<"cortex-a9", CortexA9Itineraries,
- [ArchV7A, ProcA9]>;
+ [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
+ FeatureDSPThumb2]>;
def : Processor<"cortex-a9-mp", CortexA9Itineraries,
- [ArchV7A, ProcA9, FeatureMP]>;
+ [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
+ FeatureDSPThumb2, FeatureMP]>;
// V7M Processors.
-def : ProcNoItin<"cortex-m3", [ArchV7M]>;
-def : ProcNoItin<"cortex-m4", [ArchV7EM, FeatureVFP2, FeatureVFPOnlySP]>;
+def : ProcNoItin<"cortex-m3", [HasV7Ops,
+ FeatureThumb2, FeatureNoARM, FeatureDB,
+ FeatureHWDiv]>;
+
+// V7EM Processors.
+def : ProcNoItin<"cortex-m4", [HasV7Ops,
+ FeatureThumb2, FeatureNoARM, FeatureDB,
+ FeatureHWDiv, FeatureDSPThumb2,
+ FeatureT2XtPk, FeatureVFP2,
+ FeatureVFPOnlySP]>;
//===----------------------------------------------------------------------===//
// Register File Description
Modified: llvm/branches/type-system-rewrite/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/ARM/ARMAsmPrinter.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/ARM/ARMAsmPrinter.cpp Thu Jul 7 23:45:15 2011
@@ -654,7 +654,7 @@
}
/* TODO: ARMBuildAttrs::Allowed is not completely accurate,
- * since NEON can have 1 (allowed) or 2 (fused MAC operations) */
+ * since NEON can have 1 (allowed) or 2 (MAC operations) */
if (Subtarget->hasNEON()) {
AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
ARMBuildAttrs::Allowed);
@@ -1954,11 +1954,10 @@
//===----------------------------------------------------------------------===//
static MCInstPrinter *createARMMCInstPrinter(const Target &T,
- TargetMachine &TM,
unsigned SyntaxVariant,
const MCAsmInfo &MAI) {
if (SyntaxVariant == 0)
- return new ARMInstPrinter(TM, MAI);
+ return new ARMInstPrinter(MAI);
return 0;
}
Modified: llvm/branches/type-system-rewrite/lib/Target/ARM/ARMBaseInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/ARM/ARMBaseInfo.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/ARM/ARMBaseInfo.h (original)
+++ llvm/branches/type-system-rewrite/lib/Target/ARM/ARMBaseInfo.h Thu Jul 7 23:45:15 2011
@@ -17,22 +17,12 @@
#ifndef ARMBASEINFO_H
#define ARMBASEINFO_H
+#include "MCTargetDesc/ARMMCTargetDesc.h"
#include "llvm/Support/ErrorHandling.h"
// Note that the following auto-generated files only defined enum types, and
// so are safe to include here.
-// Defines symbolic names for ARM registers. This defines a mapping from
-// register name to register number.
-//
-#define GET_REGINFO_ENUM
-#include "ARMGenRegisterInfo.inc"
-
-// Defines symbolic names for the ARM instructions.
-//
-#define GET_INSTRINFO_ENUM
-#include "ARMGenInstrInfo.inc"
-
namespace llvm {
// Enums corresponding to ARM condition codes
Modified: llvm/branches/type-system-rewrite/lib/Target/ARM/ARMFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/ARM/ARMFrameLowering.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/ARM/ARMFrameLowering.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/ARM/ARMFrameLowering.cpp Thu Jul 7 23:45:15 2011
@@ -739,20 +739,52 @@
/// estimateStackSize - Estimate and return the size of the frame.
/// FIXME: Make generic?
static unsigned estimateStackSize(MachineFunction &MF) {
- const MachineFrameInfo *FFI = MF.getFrameInfo();
+ const MachineFrameInfo *MFI = MF.getFrameInfo();
+ const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
+ const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
+ unsigned MaxAlign = MFI->getMaxAlignment();
int Offset = 0;
- for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
- int FixedOff = -FFI->getObjectOffset(i);
+
+ // This code is very, very similar to PEI::calculateFrameObjectOffsets().
+ // It really should be refactored to share code. Until then, changes
+ // should keep in mind that there's tight coupling between the two.
+
+ for (int i = MFI->getObjectIndexBegin(); i != 0; ++i) {
+ int FixedOff = -MFI->getObjectOffset(i);
if (FixedOff > Offset) Offset = FixedOff;
}
- for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
- if (FFI->isDeadObjectIndex(i))
+ for (unsigned i = 0, e = MFI->getObjectIndexEnd(); i != e; ++i) {
+ if (MFI->isDeadObjectIndex(i))
continue;
- Offset += FFI->getObjectSize(i);
- unsigned Align = FFI->getObjectAlignment(i);
+ Offset += MFI->getObjectSize(i);
+ unsigned Align = MFI->getObjectAlignment(i);
// Adjust to alignment boundary
Offset = (Offset+Align-1)/Align*Align;
+
+ MaxAlign = std::max(Align, MaxAlign);
}
+
+ if (MFI->adjustsStack() && TFI->hasReservedCallFrame(MF))
+ Offset += MFI->getMaxCallFrameSize();
+
+ // Round up the size to a multiple of the alignment. If the function has
+ // any calls or alloca's, align to the target's StackAlignment value to
+ // ensure that the callee's frame or the alloca data is suitably aligned;
+ // otherwise, for leaf functions, align to the TransientStackAlignment
+ // value.
+ unsigned StackAlign;
+ if (MFI->adjustsStack() || MFI->hasVarSizedObjects() ||
+ (RegInfo->needsStackRealignment(MF) && MFI->getObjectIndexEnd() != 0))
+ StackAlign = TFI->getStackAlignment();
+ else
+ StackAlign = TFI->getTransientStackAlignment();
+
+ // If the frame pointer is eliminated, all frame offsets will be relative to
+ // SP not FP. Align to MaxAlign so this works.
+ StackAlign = std::max(StackAlign, MaxAlign);
+ unsigned AlignMask = StackAlign - 1;
+ Offset = (Offset + AlignMask) & ~uint64_t(AlignMask);
+
return (unsigned)Offset;
}
Modified: llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrFormats.td?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrFormats.td Thu Jul 7 23:45:15 2011
@@ -282,15 +282,13 @@
: InstTemplate<am, sz, im, f, d, cstr, itin>;
class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern>
- // FIXME: This really should derive from InstTemplate instead, as pseudos
- // don't need encoding information. TableGen doesn't like that
- // currently. Need to figure out why and fix it.
- : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain,
- "", itin> {
+ : InstTemplate<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo,
+ GenericDomain, "", itin> {
let OutOperandList = oops;
let InOperandList = iops;
let Pattern = pattern;
let isCodeGenOnly = 1;
+ let isPseudo = 1;
}
// PseudoInst that's ARM-mode only.
Modified: llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrInfo.td?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrInfo.td Thu Jul 7 23:45:15 2011
@@ -147,35 +147,48 @@
//===----------------------------------------------------------------------===//
// ARM Instruction Predicate Definitions.
//
-def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate;
+def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
+ AssemblerPredicate<"HasV4TOps">;
def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
-def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate;
-def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate;
+def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
+ AssemblerPredicate<"HasV5TEOps">;
+def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
+ AssemblerPredicate<"HasV6Ops">;
def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
-def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate;
+def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
+ AssemblerPredicate<"HasV6T2Ops">;
def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
-def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate;
+def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
+ AssemblerPredicate<"HasV7Ops">;
def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
-def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
-def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
-def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
-def HasFP16 : Predicate<"Subtarget->hasFP16()">, AssemblerPredicate;
-def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
+def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
+ AssemblerPredicate<"FeatureVFP2">;
+def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
+ AssemblerPredicate<"FeatureVFP3">;
+def HasNEON : Predicate<"Subtarget->hasNEON()">,
+ AssemblerPredicate<"FeatureNEON">;
+def HasFP16 : Predicate<"Subtarget->hasFP16()">,
+ AssemblerPredicate<"FeatureFP16">;
+def HasDivide : Predicate<"Subtarget->hasDivide()">,
+ AssemblerPredicate<"FeatureHWDiv">;
def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
- AssemblerPredicate;
+ AssemblerPredicate<"FeatureT2XtPk">;
def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
- AssemblerPredicate;
+ AssemblerPredicate<"FeatureDSPThumb2">;
def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
- AssemblerPredicate;
+ AssemblerPredicate<"FeatureDB">;
def HasMP : Predicate<"Subtarget->hasMPExtension()">,
- AssemblerPredicate;
+ AssemblerPredicate<"FeatureMP">;
def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
-def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate;
+def IsThumb : Predicate<"Subtarget->isThumb()">,
+ AssemblerPredicate<"ModeThumb">;
def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
-def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate;
-def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate;
+def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
+ AssemblerPredicate<"ModeThumb,FeatureThumb2">;
+def IsARM : Predicate<"!Subtarget->isThumb()">,
+ AssemblerPredicate<"!ModeThumb">;
def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
@@ -2698,10 +2711,7 @@
(ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
Size4Bytes, IIC_iMAC32,
[(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
- Requires<[IsARM, NoV6]> {
- bits<4> Ra;
- let Inst{15-12} = Ra;
-}
+ Requires<[IsARM, NoV6]>;
def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
[(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
Modified: llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrVFP.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrVFP.td?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrVFP.td (original)
+++ llvm/branches/type-system-rewrite/lib/Target/ARM/ARMInstrVFP.td Thu Jul 7 23:45:15 2011
@@ -873,7 +873,7 @@
} // End of 'let Constraints = "$a = $dst", isCodeGenOnly = 1 in'
//===----------------------------------------------------------------------===//
-// FP FMA Operations.
+// FP Multiply-Accumulate Operations.
//
def VMLAD : ADbI<0b11100, 0b00, 0, 0,
Modified: llvm/branches/type-system-rewrite/lib/Target/ARM/ARMSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/ARM/ARMSubtarget.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/ARM/ARMSubtarget.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/ARM/ARMSubtarget.cpp Thu Jul 7 23:45:15 2011
@@ -18,9 +18,10 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/ADT/SmallVector.h"
-#define GET_SUBTARGETINFO_CTOR
+#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
#define GET_SUBTARGETINFO_TARGET_DESC
+#define GET_SUBTARGETINFO_CTOR
#include "ARMGenSubtargetInfo.inc"
using namespace llvm;
@@ -37,17 +38,24 @@
cl::desc("Disallow all unaligned memory accesses"));
ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
- const std::string &FS, bool isT)
- : ARMGenSubtargetInfo()
- , ARMArchVersion(V4)
+ const std::string &FS)
+ : ARMGenSubtargetInfo(TT, CPU, FS)
, ARMProcFamily(Others)
- , ARMFPUType(None)
+ , HasV4TOps(false)
+ , HasV5TOps(false)
+ , HasV5TEOps(false)
+ , HasV6Ops(false)
+ , HasV6T2Ops(false)
+ , HasV7Ops(false)
+ , HasVFPv2(false)
+ , HasVFPv3(false)
+ , HasNEON(false)
, UseNEONForSinglePrecisionFP(false)
, SlowFPVMLx(false)
, HasVMLxForwarding(false)
, SlowFPBrcc(false)
- , IsThumb(isT)
- , ThumbMode(Thumb1)
+ , InThumbMode(false)
+ , HasThumb2(false)
, NoARM(false)
, PostRAScheduler(false)
, IsR9Reserved(ReserveR9)
@@ -68,78 +76,25 @@
, TargetTriple(TT)
, TargetABI(ARM_ABI_APCS) {
// Determine default and user specified characteristics
-
- // When no arch is specified either by CPU or by attributes, make the default
- // ARMv4T.
- const char *ARMArchFeature = "";
if (CPUString.empty())
CPUString = "generic";
- if (CPUString == "generic" && (FS.empty() || FS == "generic")) {
- ARMArchVersion = V4T;
- ARMArchFeature = "+v4t";
- }
-
- // Set the boolean corresponding to the current target triple, or the default
- // if one cannot be determined, to true.
- unsigned Len = TT.length();
- unsigned Idx = 0;
-
- if (Len >= 5 && TT.substr(0, 4) == "armv")
- Idx = 4;
- else if (Len >= 6 && TT.substr(0, 5) == "thumb") {
- IsThumb = true;
- if (Len >= 7 && TT[5] == 'v')
- Idx = 6;
- }
- if (Idx) {
- unsigned SubVer = TT[Idx];
- if (SubVer >= '7' && SubVer <= '9') {
- ARMArchVersion = V7A;
- ARMArchFeature = "+v7a";
- if (Len >= Idx+2 && TT[Idx+1] == 'm') {
- ARMArchVersion = V7M;
- ARMArchFeature = "+v7m";
- } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') {
- ARMArchVersion = V7EM;
- ARMArchFeature = "+v7em";
- }
- } else if (SubVer == '6') {
- ARMArchVersion = V6;
- ARMArchFeature = "+v6";
- if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2') {
- ARMArchVersion = V6T2;
- ARMArchFeature = "+v6t2";
- }
- } else if (SubVer == '5') {
- ARMArchVersion = V5T;
- ARMArchFeature = "+v5t";
- if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e') {
- ARMArchVersion = V5TE;
- ARMArchFeature = "+v5te";
- }
- } else if (SubVer == '4') {
- if (Len >= Idx+2 && TT[Idx+1] == 't') {
- ARMArchVersion = V4T;
- ARMArchFeature = "+v4t";
- } else {
- ARMArchVersion = V4;
- ARMArchFeature = "";
- }
- }
- }
-
- if (TT.find("eabi") != std::string::npos)
- TargetABI = ARM_ABI_AAPCS;
// Insert the architecture feature derived from the target triple into the
// feature string. This is important for setting features that are implied
// based on the architecture version.
- std::string FSWithArch = std::string(ARMArchFeature);
- if (FSWithArch.empty())
- FSWithArch = FS;
- else if (!FS.empty())
- FSWithArch = FSWithArch + "," + FS;
- ParseSubtargetFeatures(FSWithArch, CPUString);
+ std::string ArchFS = ARM_MC::ParseARMTriple(TT);
+ if (!FS.empty()) {
+ if (!ArchFS.empty())
+ ArchFS = ArchFS + "," + FS;
+ else
+ ArchFS = FS;
+ }
+ ParseSubtargetFeatures(CPUString, ArchFS);
+
+ // Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a
+ // ARM version or CPU and then remove this.
+ if (!HasV6T2Ops && hasThumb2())
+ HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true;
// Initialize scheduling itinerary for the specified CPU.
InstrItins = getInstrItineraryForCPU(CPUString);
@@ -147,11 +102,8 @@
// After parsing Itineraries, set ItinData.IssueWidth.
computeIssueWidth();
- // Thumb2 implies at least V6T2.
- if (ARMArchVersion >= V6T2)
- ThumbMode = Thumb2;
- else if (ThumbMode >= Thumb2)
- ARMArchVersion = V6T2;
+ if (TT.find("eabi") != std::string::npos)
+ TargetABI = ARM_ABI_AAPCS;
if (isAAPCS_ABI())
stackAlignment = 8;
@@ -159,7 +111,7 @@
if (!isTargetDarwin())
UseMovt = hasV6T2Ops();
else {
- IsR9Reserved = ReserveR9 | (ARMArchVersion < V6);
+ IsR9Reserved = ReserveR9 | !HasV6Ops;
UseMovt = DarwinUseMOVT && hasV6T2Ops();
}
Modified: llvm/branches/type-system-rewrite/lib/Target/ARM/ARMSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/ARM/ARMSubtarget.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/ARM/ARMSubtarget.h (original)
+++ llvm/branches/type-system-rewrite/lib/Target/ARM/ARMSubtarget.h Thu Jul 7 23:45:15 2011
@@ -14,6 +14,7 @@
#ifndef ARMSUBTARGET_H
#define ARMSUBTARGET_H
+#include "MCTargetDesc/ARMMCTargetDesc.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/ADT/Triple.h"
@@ -24,35 +25,31 @@
namespace llvm {
class GlobalValue;
+class StringRef;
class ARMSubtarget : public ARMGenSubtargetInfo {
protected:
- enum ARMArchEnum {
- V4, V4T, V5T, V5TE, V6, V6M, V6T2, V7A, V7M, V7EM
- };
-
enum ARMProcFamilyEnum {
Others, CortexA8, CortexA9
};
- enum ARMFPEnum {
- None, VFPv2, VFPv3, NEON
- };
-
- enum ThumbTypeEnum {
- Thumb1,
- Thumb2
- };
-
- /// ARMArchVersion - ARM architecture version: V4, V4T (base), V5T, V5TE,
- /// V6, V6T2, V7A, V7M, V7EM.
- ARMArchEnum ARMArchVersion;
-
/// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
ARMProcFamilyEnum ARMProcFamily;
- /// ARMFPUType - Floating Point Unit type.
- ARMFPEnum ARMFPUType;
+ /// HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6T2Ops, HasV7Ops -
+ /// Specify whether target support specific ARM ISA variants.
+ bool HasV4TOps;
+ bool HasV5TOps;
+ bool HasV5TEOps;
+ bool HasV6Ops;
+ bool HasV6T2Ops;
+ bool HasV7Ops;
+
+ /// HasVFPv2, HasVFPv3, HasNEON - Specify what floating point ISAs are
+ /// supported.
+ bool HasVFPv2;
+ bool HasVFPv3;
+ bool HasNEON;
/// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
/// specified. Use the method useNEONForSinglePrecisionFP() to
@@ -70,11 +67,11 @@
/// SlowFPBrcc - True if floating point compare + branch is slow.
bool SlowFPBrcc;
- /// IsThumb - True if we are in thumb mode, false if in ARM mode.
- bool IsThumb;
+ /// InThumbMode - True if compiling for Thumb, false for ARM.
+ bool InThumbMode;
- /// ThumbMode - Indicates supported Thumb version.
- ThumbTypeEnum ThumbMode;
+ /// HasThumb2 - True if Thumb2 instructions are supported.
+ bool HasThumb2;
/// NoARM - True if subtarget does not support ARM mode execution.
bool NoARM;
@@ -161,7 +158,7 @@
/// of the specified triple.
///
ARMSubtarget(const std::string &TT, const std::string &CPU,
- const std::string &FS, bool isThumb);
+ const std::string &FS);
/// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
/// that still makes it profitable to inline the call.
@@ -172,27 +169,28 @@
}
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
- void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
+ void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
void computeIssueWidth();
- bool hasV4TOps() const { return ARMArchVersion >= V4T; }
- bool hasV5TOps() const { return ARMArchVersion >= V5T; }
- bool hasV5TEOps() const { return ARMArchVersion >= V5TE; }
- bool hasV6Ops() const { return ARMArchVersion >= V6; }
- bool hasV6T2Ops() const { return ARMArchVersion >= V6T2; }
- bool hasV7Ops() const { return ARMArchVersion >= V7A; }
+ bool hasV4TOps() const { return HasV4TOps; }
+ bool hasV5TOps() const { return HasV5TOps; }
+ bool hasV5TEOps() const { return HasV5TEOps; }
+ bool hasV6Ops() const { return HasV6Ops; }
+ bool hasV6T2Ops() const { return HasV6T2Ops; }
+ bool hasV7Ops() const { return HasV7Ops; }
bool isCortexA8() const { return ARMProcFamily == CortexA8; }
bool isCortexA9() const { return ARMProcFamily == CortexA9; }
bool hasARMOps() const { return !NoARM; }
- bool hasVFP2() const { return ARMFPUType >= VFPv2; }
- bool hasVFP3() const { return ARMFPUType >= VFPv3; }
- bool hasNEON() const { return ARMFPUType >= NEON; }
+ bool hasVFP2() const { return HasVFPv2; }
+ bool hasVFP3() const { return HasVFPv3; }
+ bool hasNEON() const { return HasNEON; }
bool useNEONForSinglePrecisionFP() const {
return hasNEON() && UseNEONForSinglePrecisionFP; }
+
bool hasDivide() const { return HasHardwareDivide; }
bool hasT2ExtractPack() const { return HasT2ExtractPack; }
bool hasDataBarrier() const { return HasDataBarrier; }
@@ -216,10 +214,10 @@
bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
- bool isThumb() const { return IsThumb; }
- bool isThumb1Only() const { return IsThumb && (ThumbMode == Thumb1); }
- bool isThumb2() const { return IsThumb && (ThumbMode == Thumb2); }
- bool hasThumb2() const { return ThumbMode >= Thumb2; }
+ bool isThumb() const { return InThumbMode; }
+ bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
+ bool isThumb2() const { return InThumbMode && HasThumb2; }
+ bool hasThumb2() const { return HasThumb2; }
bool isR9Reserved() const { return IsR9Reserved; }
Modified: llvm/branches/type-system-rewrite/lib/Target/ARM/ARMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/ARM/ARMTargetMachine.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/ARM/ARMTargetMachine.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/ARM/ARMTargetMachine.cpp Thu Jul 7 23:45:15 2011
@@ -79,10 +79,9 @@
ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T,
const std::string &TT,
const std::string &CPU,
- const std::string &FS,
- bool isThumb)
- : LLVMTargetMachine(T, TT),
- Subtarget(TT, CPU, FS, isThumb),
+ const std::string &FS)
+ : LLVMTargetMachine(T, TT, CPU, FS),
+ Subtarget(TT, CPU, FS),
JITInfo(),
InstrItins(Subtarget.getInstrItineraryData()) {
DefRelocModel = getRelocationModel();
@@ -95,7 +94,7 @@
ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU,
const std::string &FS)
- : ARMBaseTargetMachine(T, TT, CPU, FS, false), InstrInfo(Subtarget),
+ : ARMBaseTargetMachine(T, TT, CPU, FS), InstrInfo(Subtarget),
DataLayout(Subtarget.isAPCS_ABI() ?
std::string("e-p:32:32-f64:32:64-i64:32:64-"
"v128:32:128-v64:32:64-n32") :
@@ -113,7 +112,7 @@
ThumbTargetMachine::ThumbTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU,
const std::string &FS)
- : ARMBaseTargetMachine(T, TT, CPU, FS, true),
+ : ARMBaseTargetMachine(T, TT, CPU, FS),
InstrInfo(Subtarget.hasThumb2()
? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
: ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
Modified: llvm/branches/type-system-rewrite/lib/Target/ARM/ARMTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/ARM/ARMTargetMachine.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/ARM/ARMTargetMachine.h (original)
+++ llvm/branches/type-system-rewrite/lib/Target/ARM/ARMTargetMachine.h Thu Jul 7 23:45:15 2011
@@ -41,8 +41,7 @@
public:
ARMBaseTargetMachine(const Target &T, const std::string &TT,
- const std::string &CPU, const std::string &FS,
- bool isThumb);
+ const std::string &CPU, const std::string &FS);
virtual ARMJITInfo *getJITInfo() { return &JITInfo; }
virtual const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; }
Modified: llvm/branches/type-system-rewrite/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Jul 7 23:45:15 2011
@@ -20,6 +20,7 @@
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Target/TargetRegistry.h"
#include "llvm/Target/TargetAsmParser.h"
#include "llvm/Support/SourceMgr.h"
@@ -28,6 +29,10 @@
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/ADT/Twine.h"
+
+#define GET_SUBTARGETINFO_ENUM
+#include "ARMGenSubtargetInfo.inc"
+
using namespace llvm;
namespace {
@@ -36,7 +41,7 @@
class ARMAsmParser : public TargetAsmParser {
MCAsmParser &Parser;
- TargetMachine &TM;
+ MCSubtargetInfo *STI;
MCAsmParser &getParser() const { return Parser; }
MCAsmLexer &getLexer() const { return Parser.getLexer(); }
@@ -79,6 +84,15 @@
void GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
bool &CanAcceptPredicationCode);
+ bool isThumb() const {
+ // FIXME: Can tablegen auto-generate this?
+ return (STI->getFeatureBits() & ARM::ModeThumb) != 0;
+ }
+
+ bool isThumbOne() const {
+ return isThumb() && (STI->getFeatureBits() & ARM::FeatureThumb2) == 0;
+ }
+
/// @name Auto-generated Match Functions
/// {
@@ -113,13 +127,15 @@
const SmallVectorImpl<MCParsedAsmOperand*> &);
public:
- ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
- : TargetAsmParser(T), Parser(_Parser), TM(_TM) {
- MCAsmParserExtension::Initialize(_Parser);
- // Initialize the set of available features.
- setAvailableFeatures(ComputeAvailableFeatures(
- &TM.getSubtarget<ARMSubtarget>()));
- }
+ ARMAsmParser(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
+ MCAsmParser &_Parser)
+ : TargetAsmParser(T), Parser(_Parser) {
+ STI = ARM_MC::createARMMCSubtargetInfo(TT, CPU, FS);
+
+ MCAsmParserExtension::Initialize(_Parser);
+ // Initialize the set of available features.
+ setAvailableFeatures(ComputeAvailableFeatures(STI->getFeatureBits()));
+ }
virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands);
@@ -1852,9 +1868,6 @@
void ARMAsmParser::
GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
bool &CanAcceptPredicationCode) {
- bool isThumbOne = TM.getSubtarget<ARMSubtarget>().isThumb1Only();
- bool isThumb = TM.getSubtarget<ARMSubtarget>().isThumb();
-
if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" ||
@@ -1863,7 +1876,7 @@
Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" ||
Mnemonic == "eor" || Mnemonic == "smlal" ||
- (Mnemonic == "mov" && !isThumbOne)) {
+ (Mnemonic == "mov" && !isThumbOne())) {
CanAcceptCarrySet = true;
} else {
CanAcceptCarrySet = false;
@@ -1880,7 +1893,7 @@
CanAcceptPredicationCode = true;
}
- if (isThumb)
+ if (isThumb())
if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
CanAcceptPredicationCode = false;
@@ -2207,12 +2220,12 @@
// includes Feature_IsThumb or not to match the right instructions. This is
// blocked on the FIXME in llvm-mc.cpp when creating the TargetMachine.
if (Val == 16){
- assert(TM.getSubtarget<ARMSubtarget>().isThumb() &&
+ assert(isThumb() &&
"switching between arm/thumb not yet suppported via .code 16)");
getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
}
else{
- assert(!TM.getSubtarget<ARMSubtarget>().isThumb() &&
+ assert(!isThumb() &&
"switching between thumb/arm not yet suppported via .code 32)");
getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
}
Modified: llvm/branches/type-system-rewrite/lib/Target/ARM/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/ARM/CMakeLists.txt?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/ARM/CMakeLists.txt (original)
+++ llvm/branches/type-system-rewrite/lib/Target/ARM/CMakeLists.txt Thu Jul 7 23:45:15 2011
@@ -65,3 +65,4 @@
add_subdirectory(AsmParser)
add_subdirectory(Disassembler)
add_subdirectory(InstPrinter)
+add_subdirectory(MCTargetDesc)
Modified: llvm/branches/type-system-rewrite/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/ARM/InstPrinter/ARMInstPrinter.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/ARM/InstPrinter/ARMInstPrinter.h (original)
+++ llvm/branches/type-system-rewrite/lib/Target/ARM/InstPrinter/ARMInstPrinter.h Thu Jul 7 23:45:15 2011
@@ -19,11 +19,10 @@
namespace llvm {
class MCOperand;
-class TargetMachine;
class ARMInstPrinter : public MCInstPrinter {
public:
- ARMInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI)
+ ARMInstPrinter(const MCAsmInfo &MAI)
: MCInstPrinter(MAI) {}
virtual void printInst(const MCInst *MI, raw_ostream &O);
Modified: llvm/branches/type-system-rewrite/lib/Target/ARM/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/ARM/Makefile?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/ARM/Makefile (original)
+++ llvm/branches/type-system-rewrite/lib/Target/ARM/Makefile Thu Jul 7 23:45:15 2011
@@ -19,6 +19,6 @@
ARMGenDecoderTables.inc ARMGenEDInfo.inc \
ARMGenFastISel.inc ARMGenMCCodeEmitter.inc
-DIRS = InstPrinter AsmParser Disassembler TargetInfo
+DIRS = InstPrinter AsmParser Disassembler TargetInfo MCTargetDesc
include $(LEVEL)/Makefile.common
Modified: llvm/branches/type-system-rewrite/lib/Target/Alpha/AlphaSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/Alpha/AlphaSubtarget.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/Alpha/AlphaSubtarget.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/Alpha/AlphaSubtarget.cpp Thu Jul 7 23:45:15 2011
@@ -14,22 +14,23 @@
#include "AlphaSubtarget.h"
#include "Alpha.h"
-#define GET_SUBTARGETINFO_CTOR
+#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
#define GET_SUBTARGETINFO_TARGET_DESC
+#define GET_SUBTARGETINFO_CTOR
#include "AlphaGenSubtargetInfo.inc"
using namespace llvm;
AlphaSubtarget::AlphaSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS)
- : AlphaGenSubtargetInfo(), HasCT(false) {
+ : AlphaGenSubtargetInfo(TT, CPU, FS), HasCT(false) {
std::string CPUName = CPU;
if (CPUName.empty())
CPUName = "generic";
// Parse features string.
- ParseSubtargetFeatures(FS, CPUName);
+ ParseSubtargetFeatures(CPUName, FS);
// Initialize scheduling itinerary for the specified CPU.
InstrItins = getInstrItineraryForCPU(CPUName);
Modified: llvm/branches/type-system-rewrite/lib/Target/Alpha/AlphaSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/Alpha/AlphaSubtarget.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/Alpha/AlphaSubtarget.h (original)
+++ llvm/branches/type-system-rewrite/lib/Target/Alpha/AlphaSubtarget.h Thu Jul 7 23:45:15 2011
@@ -22,6 +22,7 @@
#include "AlphaGenSubtargetInfo.inc"
namespace llvm {
+class StringRe;
class AlphaSubtarget : public AlphaGenSubtargetInfo {
protected:
@@ -39,7 +40,7 @@
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
- void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
+ void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
bool hasCT() const { return HasCT; }
};
Modified: llvm/branches/type-system-rewrite/lib/Target/Alpha/AlphaTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/Alpha/AlphaTargetMachine.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/Alpha/AlphaTargetMachine.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/Alpha/AlphaTargetMachine.cpp Thu Jul 7 23:45:15 2011
@@ -27,7 +27,7 @@
AlphaTargetMachine::AlphaTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU,
const std::string &FS)
- : LLVMTargetMachine(T, TT),
+ : LLVMTargetMachine(T, TT, CPU, FS),
DataLayout("e-f128:128:128-n64"),
FrameLowering(Subtarget),
Subtarget(TT, CPU, FS),
Modified: llvm/branches/type-system-rewrite/lib/Target/Blackfin/BlackfinSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/Blackfin/BlackfinSubtarget.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/Blackfin/BlackfinSubtarget.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/Blackfin/BlackfinSubtarget.cpp Thu Jul 7 23:45:15 2011
@@ -13,9 +13,10 @@
#include "BlackfinSubtarget.h"
-#define GET_SUBTARGETINFO_CTOR
+#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
#define GET_SUBTARGETINFO_TARGET_DESC
+#define GET_SUBTARGETINFO_CTOR
#include "BlackfinGenSubtargetInfo.inc"
using namespace llvm;
@@ -23,7 +24,7 @@
BlackfinSubtarget::BlackfinSubtarget(const std::string &TT,
const std::string &CPU,
const std::string &FS)
- : BlackfinGenSubtargetInfo(), sdram(false),
+ : BlackfinGenSubtargetInfo(TT, CPU, FS), sdram(false),
icplb(false),
wa_mi_shift(false),
wa_csync(false),
@@ -39,5 +40,5 @@
if (CPUName.empty())
CPUName = "generic";
// Parse features string.
- ParseSubtargetFeatures(FS, CPUName);
+ ParseSubtargetFeatures(CPUName, FS);
}
Modified: llvm/branches/type-system-rewrite/lib/Target/Blackfin/BlackfinSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/Blackfin/BlackfinSubtarget.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/Blackfin/BlackfinSubtarget.h (original)
+++ llvm/branches/type-system-rewrite/lib/Target/Blackfin/BlackfinSubtarget.h Thu Jul 7 23:45:15 2011
@@ -21,6 +21,7 @@
#include "BlackfinGenSubtargetInfo.inc"
namespace llvm {
+class StringRef;
class BlackfinSubtarget : public BlackfinGenSubtargetInfo {
bool sdram;
@@ -40,8 +41,7 @@
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
- void ParseSubtargetFeatures(const std::string &FS,
- const std::string &CPU);
+ void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
};
} // end namespace llvm
Modified: llvm/branches/type-system-rewrite/lib/Target/Blackfin/BlackfinTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/Blackfin/BlackfinTargetMachine.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/Blackfin/BlackfinTargetMachine.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/Blackfin/BlackfinTargetMachine.cpp Thu Jul 7 23:45:15 2011
@@ -28,7 +28,7 @@
const std::string &TT,
const std::string &CPU,
const std::string &FS)
- : LLVMTargetMachine(T, TT),
+ : LLVMTargetMachine(T, TT, CPU, FS),
DataLayout("e-p:32:32-i64:32-f64:32-n32"),
Subtarget(TT, CPU, FS),
TLInfo(*this),
Modified: llvm/branches/type-system-rewrite/lib/Target/CBackend/CTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/CBackend/CTargetMachine.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/CBackend/CTargetMachine.h (original)
+++ llvm/branches/type-system-rewrite/lib/Target/CBackend/CTargetMachine.h Thu Jul 7 23:45:15 2011
@@ -22,7 +22,7 @@
struct CTargetMachine : public TargetMachine {
CTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU, const std::string &FS)
- : TargetMachine(T) {}
+ : TargetMachine(T, TT, CPU, FS) {}
virtual bool addPassesToEmitFile(PassManagerBase &PM,
formatted_raw_ostream &Out,
Modified: llvm/branches/type-system-rewrite/lib/Target/CellSPU/SPUSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/CellSPU/SPUSubtarget.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/CellSPU/SPUSubtarget.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/CellSPU/SPUSubtarget.cpp Thu Jul 7 23:45:15 2011
@@ -13,19 +13,20 @@
#include "SPUSubtarget.h"
#include "SPU.h"
-#include "llvm/ADT/SmallVector.h"
#include "SPURegisterInfo.h"
+#include "llvm/ADT/SmallVector.h"
-#define GET_SUBTARGETINFO_CTOR
+#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
#define GET_SUBTARGETINFO_TARGET_DESC
+#define GET_SUBTARGETINFO_CTOR
#include "SPUGenSubtargetInfo.inc"
using namespace llvm;
SPUSubtarget::SPUSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS) :
- SPUGenSubtargetInfo(),
+ SPUGenSubtargetInfo(TT, CPU, FS),
StackAlignment(16),
ProcDirective(SPU::DEFAULT_PROC),
UseLargeMem(false)
@@ -35,7 +36,7 @@
std::string default_cpu("v0");
// Parse features string.
- ParseSubtargetFeatures(FS, default_cpu);
+ ParseSubtargetFeatures(default_cpu, FS);
// Initialize scheduling itinerary for the specified CPU.
InstrItins = getInstrItineraryForCPU(default_cpu);
Modified: llvm/branches/type-system-rewrite/lib/Target/CellSPU/SPUSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/CellSPU/SPUSubtarget.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/CellSPU/SPUSubtarget.h (original)
+++ llvm/branches/type-system-rewrite/lib/Target/CellSPU/SPUSubtarget.h Thu Jul 7 23:45:15 2011
@@ -23,6 +23,7 @@
namespace llvm {
class GlobalValue;
+ class StringRef;
namespace SPU {
enum {
@@ -57,7 +58,7 @@
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
- void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
+ void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
/// SetJITMode - This is called to inform the subtarget info that we are
/// producing code for the JIT.
Modified: llvm/branches/type-system-rewrite/lib/Target/CellSPU/SPUTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/CellSPU/SPUTargetMachine.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/CellSPU/SPUTargetMachine.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/CellSPU/SPUTargetMachine.cpp Thu Jul 7 23:45:15 2011
@@ -36,7 +36,7 @@
SPUTargetMachine::SPUTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU,const std::string &FS)
- : LLVMTargetMachine(T, TT),
+ : LLVMTargetMachine(T, TT, CPU, FS),
Subtarget(TT, CPU, FS),
DataLayout(Subtarget.getTargetDataString()),
InstrInfo(*this),
Modified: llvm/branches/type-system-rewrite/lib/Target/CppBackend/CPPTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/CppBackend/CPPTargetMachine.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/CppBackend/CPPTargetMachine.h (original)
+++ llvm/branches/type-system-rewrite/lib/Target/CppBackend/CPPTargetMachine.h Thu Jul 7 23:45:15 2011
@@ -24,7 +24,7 @@
struct CPPTargetMachine : public TargetMachine {
CPPTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU, const std::string &FS)
- : TargetMachine(T) {}
+ : TargetMachine(T, TT, CPU, FS) {}
virtual bool addPassesToEmitFile(PassManagerBase &PM,
formatted_raw_ostream &Out,
Modified: llvm/branches/type-system-rewrite/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp Thu Jul 7 23:45:15 2011
@@ -32,7 +32,6 @@
class MBlazeAsmParser : public TargetAsmParser {
MCAsmParser &Parser;
- TargetMachine &TM;
MCAsmParser &getParser() const { return Parser; }
MCAsmLexer &getLexer() const { return Parser.getLexer(); }
@@ -64,8 +63,9 @@
public:
- MBlazeAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
- : TargetAsmParser(T), Parser(_Parser), TM(_TM) {}
+ MBlazeAsmParser(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
+ MCAsmParser &_Parser)
+ : TargetAsmParser(T), Parser(_Parser) {}
virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands);
Modified: llvm/branches/type-system-rewrite/lib/Target/MBlaze/InstPrinter/MBlazeInstPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/MBlaze/InstPrinter/MBlazeInstPrinter.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/MBlaze/InstPrinter/MBlazeInstPrinter.h (original)
+++ llvm/branches/type-system-rewrite/lib/Target/MBlaze/InstPrinter/MBlazeInstPrinter.h Thu Jul 7 23:45:15 2011
@@ -18,11 +18,10 @@
namespace llvm {
class MCOperand;
- class TargetMachine;
class MBlazeInstPrinter : public MCInstPrinter {
public:
- MBlazeInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI)
+ MBlazeInstPrinter(const MCAsmInfo &MAI)
: MCInstPrinter(MAI) {}
virtual void printInst(const MCInst *MI, raw_ostream &O);
Modified: llvm/branches/type-system-rewrite/lib/Target/MBlaze/MBlazeAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/MBlaze/MBlazeAsmPrinter.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/MBlaze/MBlazeAsmPrinter.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/MBlaze/MBlazeAsmPrinter.cpp Thu Jul 7 23:45:15 2011
@@ -319,11 +319,10 @@
}
static MCInstPrinter *createMBlazeMCInstPrinter(const Target &T,
- TargetMachine &TM,
unsigned SyntaxVariant,
const MCAsmInfo &MAI) {
if (SyntaxVariant == 0)
- return new MBlazeInstPrinter(TM, MAI);
+ return new MBlazeInstPrinter(MAI);
return 0;
}
Modified: llvm/branches/type-system-rewrite/lib/Target/MBlaze/MBlazeSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/MBlaze/MBlazeSubtarget.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/MBlaze/MBlazeSubtarget.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/MBlaze/MBlazeSubtarget.cpp Thu Jul 7 23:45:15 2011
@@ -16,9 +16,10 @@
#include "MBlazeRegisterInfo.h"
#include "llvm/Support/CommandLine.h"
-#define GET_SUBTARGETINFO_CTOR
+#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
#define GET_SUBTARGETINFO_TARGET_DESC
+#define GET_SUBTARGETINFO_CTOR
#include "MBlazeGenSubtargetInfo.inc"
using namespace llvm;
@@ -26,7 +27,7 @@
MBlazeSubtarget::MBlazeSubtarget(const std::string &TT,
const std::string &CPU,
const std::string &FS):
- MBlazeGenSubtargetInfo(),
+ MBlazeGenSubtargetInfo(TT, CPU, FS),
HasBarrel(false), HasDiv(false), HasMul(false), HasPatCmp(false),
HasFPU(false), HasMul64(false), HasSqrt(false)
{
@@ -34,7 +35,7 @@
std::string CPUName = CPU;
if (CPUName.empty())
CPUName = "mblaze";
- ParseSubtargetFeatures(FS, CPUName);
+ ParseSubtargetFeatures(CPUName, FS);
// Only use instruction scheduling if the selected CPU has an instruction
// itinerary (the default CPU is the only one that doesn't).
@@ -61,4 +62,3 @@
CriticalPathRCs.push_back(&MBlaze::GPRRegClass);
return HasItin && OptLevel >= CodeGenOpt::Default;
}
-
Modified: llvm/branches/type-system-rewrite/lib/Target/MBlaze/MBlazeSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/MBlaze/MBlazeSubtarget.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/MBlaze/MBlazeSubtarget.h (original)
+++ llvm/branches/type-system-rewrite/lib/Target/MBlaze/MBlazeSubtarget.h Thu Jul 7 23:45:15 2011
@@ -22,6 +22,7 @@
#include "MBlazeGenSubtargetInfo.inc"
namespace llvm {
+class StringRef;
class MBlazeSubtarget : public MBlazeGenSubtargetInfo {
@@ -46,7 +47,7 @@
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
- void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
+ void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
/// Compute the number of maximum number of issues per cycle for the
/// MBlaze scheduling itineraries.
Modified: llvm/branches/type-system-rewrite/lib/Target/MBlaze/MBlazeTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/MBlaze/MBlazeTargetMachine.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/MBlaze/MBlazeTargetMachine.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/MBlaze/MBlazeTargetMachine.cpp Thu Jul 7 23:45:15 2011
@@ -81,7 +81,7 @@
MBlazeTargetMachine::
MBlazeTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU, const std::string &FS):
- LLVMTargetMachine(T, TT),
+ LLVMTargetMachine(T, TT, CPU, FS),
Subtarget(TT, CPU, FS),
DataLayout("E-p:32:32:32-i8:8:8-i16:16:16"),
InstrInfo(*this),
Modified: llvm/branches/type-system-rewrite/lib/Target/MSP430/InstPrinter/MSP430InstPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/MSP430/InstPrinter/MSP430InstPrinter.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/MSP430/InstPrinter/MSP430InstPrinter.h (original)
+++ llvm/branches/type-system-rewrite/lib/Target/MSP430/InstPrinter/MSP430InstPrinter.h Thu Jul 7 23:45:15 2011
@@ -18,11 +18,10 @@
namespace llvm {
class MCOperand;
- class TargetMachine;
class MSP430InstPrinter : public MCInstPrinter {
public:
- MSP430InstPrinter(TargetMachine &TM, const MCAsmInfo &MAI)
+ MSP430InstPrinter(const MCAsmInfo &MAI)
: MCInstPrinter(MAI) {}
virtual void printInst(const MCInst *MI, raw_ostream &O);
Modified: llvm/branches/type-system-rewrite/lib/Target/MSP430/MSP430AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/MSP430/MSP430AsmPrinter.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/MSP430/MSP430AsmPrinter.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/MSP430/MSP430AsmPrinter.cpp Thu Jul 7 23:45:15 2011
@@ -164,11 +164,10 @@
}
static MCInstPrinter *createMSP430MCInstPrinter(const Target &T,
- TargetMachine &TM,
unsigned SyntaxVariant,
const MCAsmInfo &MAI) {
if (SyntaxVariant == 0)
- return new MSP430InstPrinter(TM, MAI);
+ return new MSP430InstPrinter(MAI);
return 0;
}
Modified: llvm/branches/type-system-rewrite/lib/Target/MSP430/MSP430Subtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/MSP430/MSP430Subtarget.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/MSP430/MSP430Subtarget.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/MSP430/MSP430Subtarget.cpp Thu Jul 7 23:45:15 2011
@@ -14,18 +14,20 @@
#include "MSP430Subtarget.h"
#include "MSP430.h"
-#define GET_SUBTARGETINFO_CTOR
+#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
#define GET_SUBTARGETINFO_TARGET_DESC
+#define GET_SUBTARGETINFO_CTOR
#include "MSP430GenSubtargetInfo.inc"
using namespace llvm;
MSP430Subtarget::MSP430Subtarget(const std::string &TT,
- const std::string &CPUIgnored,
- const std::string &FS) {
- std::string CPU = "generic";
+ const std::string &CPU,
+ const std::string &FS) :
+ MSP430GenSubtargetInfo(TT, CPU, FS) {
+ std::string CPUName = "generic";
// Parse features string.
- ParseSubtargetFeatures(FS, CPU);
+ ParseSubtargetFeatures(CPUName, FS);
}
Modified: llvm/branches/type-system-rewrite/lib/Target/MSP430/MSP430Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/MSP430/MSP430Subtarget.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/MSP430/MSP430Subtarget.h (original)
+++ llvm/branches/type-system-rewrite/lib/Target/MSP430/MSP430Subtarget.h Thu Jul 7 23:45:15 2011
@@ -22,6 +22,7 @@
#include <string>
namespace llvm {
+class StringRef;
class MSP430Subtarget : public MSP430GenSubtargetInfo {
bool ExtendedInsts;
@@ -34,7 +35,7 @@
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
- void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
+ void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
};
} // End llvm namespace
Modified: llvm/branches/type-system-rewrite/lib/Target/MSP430/MSP430TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/MSP430/MSP430TargetMachine.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/MSP430/MSP430TargetMachine.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/MSP430/MSP430TargetMachine.cpp Thu Jul 7 23:45:15 2011
@@ -30,7 +30,7 @@
const std::string &TT,
const std::string &CPU,
const std::string &FS)
- : LLVMTargetMachine(T, TT),
+ : LLVMTargetMachine(T, TT, CPU, FS),
Subtarget(TT, CPU, FS),
// FIXME: Check TargetData string.
DataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"),
Modified: llvm/branches/type-system-rewrite/lib/Target/Mips/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/Mips/CMakeLists.txt?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/Mips/CMakeLists.txt (original)
+++ llvm/branches/type-system-rewrite/lib/Target/Mips/CMakeLists.txt Thu Jul 7 23:45:15 2011
@@ -17,6 +17,8 @@
MipsISelLowering.cpp
MipsFrameLowering.cpp
MipsMCAsmInfo.cpp
+ MipsMCInstLower.cpp
+ MipsMCSymbolRefExpr.cpp
MipsRegisterInfo.cpp
MipsSubtarget.cpp
MipsTargetMachine.cpp
@@ -24,4 +26,5 @@
MipsSelectionDAGInfo.cpp
)
+add_subdirectory(InstPrinter)
add_subdirectory(TargetInfo)
Modified: llvm/branches/type-system-rewrite/lib/Target/Mips/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/Mips/Makefile?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/Mips/Makefile (original)
+++ llvm/branches/type-system-rewrite/lib/Target/Mips/Makefile Thu Jul 7 23:45:15 2011
@@ -13,11 +13,11 @@
# Make sure that tblgen is run, first thing.
BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrInfo.inc \
- MipsGenAsmWriter.inc \
+ MipsGenAsmWriter.inc \
MipsGenDAGISel.inc MipsGenCallingConv.inc \
MipsGenSubtargetInfo.inc
-DIRS = TargetInfo
+DIRS = InstPrinter TargetInfo
include $(LEVEL)/Makefile.common
Modified: llvm/branches/type-system-rewrite/lib/Target/Mips/Mips.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/Mips/Mips.td?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/Mips/Mips.td (original)
+++ llvm/branches/type-system-rewrite/lib/Target/Mips/Mips.td Thu Jul 7 23:45:15 2011
@@ -88,6 +88,14 @@
FeatureVFPU, FeatureSEInReg, FeatureCondMov, FeatureMulDivAdd,
FeatureMinMax, FeatureSwap, FeatureBitCount]>;
+def MipsAsmWriter : AsmWriter {
+ string AsmWriterClassName = "InstPrinter";
+ bit isMCAsmWriter = 1;
+}
+
def Mips : Target {
let InstructionSet = MipsInstrInfo;
+
+ let AssemblyWriters = [MipsAsmWriter];
}
+
Modified: llvm/branches/type-system-rewrite/lib/Target/Mips/MipsAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/Mips/MipsAsmPrinter.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/Mips/MipsAsmPrinter.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/Mips/MipsAsmPrinter.cpp Thu Jul 7 23:45:15 2011
@@ -13,25 +13,25 @@
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "mips-asm-printer"
+#include "MipsAsmPrinter.h"
#include "Mips.h"
-#include "MipsSubtarget.h"
#include "MipsInstrInfo.h"
-#include "MipsTargetMachine.h"
#include "MipsMachineFunction.h"
+#include "MipsMCInstLower.h"
+#include "InstPrinter/MipsInstPrinter.h"
#include "llvm/BasicBlock.h"
#include "llvm/Instructions.h"
-#include "llvm/CodeGen/AsmPrinter.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCAsmInfo.h"
+#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/Target/Mangler.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetLoweringObjectFile.h"
-#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetRegistry.h"
#include "llvm/ADT/SmallString.h"
@@ -42,63 +42,20 @@
using namespace llvm;
-namespace {
- class MipsAsmPrinter : public AsmPrinter {
- const MipsSubtarget *Subtarget;
- public:
- explicit MipsAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
- : AsmPrinter(TM, Streamer) {
- Subtarget = &TM.getSubtarget<MipsSubtarget>();
- }
-
- virtual const char *getPassName() const {
- return "Mips Assembly Printer";
- }
-
- bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
- unsigned AsmVariant, const char *ExtraCode,
- raw_ostream &O);
- bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
- unsigned AsmVariant, const char *ExtraCode,
- raw_ostream &O);
- void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O);
- void printUnsignedImm(const MachineInstr *MI, int opNum, raw_ostream &O);
- void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
- const char *Modifier = 0);
- void printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
- const char *Modifier = 0);
- void printSavedRegsBitmask(raw_ostream &O);
- void printHex32(unsigned int Value, raw_ostream &O);
-
- const char *getCurrentABIString() const;
- void emitFrameDirective();
-
- void printInstruction(const MachineInstr *MI, raw_ostream &O); // autogen'd.
- void EmitInstruction(const MachineInstr *MI) {
- SmallString<128> Str;
- raw_svector_ostream OS(Str);
-
- if (MI->isDebugValue())
- PrintDebugValueComment(MI, OS);
+void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
+ SmallString<128> Str;
+ raw_svector_ostream OS(Str);
- printInstruction(MI, OS);
- OutStreamer.EmitRawText(OS.str());
- }
- virtual void EmitFunctionBodyStart();
- virtual void EmitFunctionBodyEnd();
- virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
- MBB) const;
- static const char *getRegisterName(unsigned RegNo);
-
- virtual void EmitFunctionEntryLabel();
- void EmitStartOfAsmFile(Module &M);
- virtual MachineLocation getDebugValueLocation(const MachineInstr *MI) const;
-
- void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
- };
-} // end of anonymous namespace
+ if (MI->isDebugValue()) {
+ PrintDebugValueComment(MI, OS);
+ return;
+ }
-#include "MipsGenAsmWriter.inc"
+ MipsMCInstLower MCInstLowering(Mang, *MF, *this);
+ MCInst TmpInst0;
+ MCInstLowering.Lower(MI, TmpInst0);
+ OutStreamer.EmitInstruction(TmpInst0);
+}
//===----------------------------------------------------------------------===//
//
@@ -214,9 +171,9 @@
unsigned stackSize = MF->getFrameInfo()->getStackSize();
OutStreamer.EmitRawText("\t.frame\t$" +
- Twine(LowercaseString(getRegisterName(stackReg))) +
- "," + Twine(stackSize) + ",$" +
- Twine(LowercaseString(getRegisterName(returnReg))));
+ Twine(LowercaseString(MipsInstPrinter::getRegisterName(stackReg))) +
+ "," + Twine(stackSize) + ",$" +
+ Twine(LowercaseString(MipsInstPrinter::getRegisterName(returnReg))));
}
/// Emit Set directives.
@@ -325,7 +282,7 @@
const MachineOperand &MO = MI->getOperand(OpNum);
assert(MO.isReg() && "unexpected inline asm memory operand");
- O << "0($" << MipsAsmPrinter::getRegisterName(MO.getReg()) << ")";
+ O << "0($" << MipsInstPrinter::getRegisterName(MO.getReg()) << ")";
return false;
}
@@ -351,7 +308,8 @@
switch (MO.getType()) {
case MachineOperand::MO_Register:
- O << '$' << LowercaseString(getRegisterName(MO.getReg()));
+ O << '$'
+ << LowercaseString(MipsInstPrinter::getRegisterName(MO.getReg()));
break;
case MachineOperand::MO_Immediate:
@@ -405,27 +363,27 @@
}
void MipsAsmPrinter::
-printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
- const char *Modifier) {
- // when using stack locations for not load/store instructions
- // print the same way as all normal 3 operand instructions.
- if (Modifier && !strcmp(Modifier, "stackloc")) {
- printOperand(MI, opNum+1, O);
- O << ", ";
- printOperand(MI, opNum, O);
- return;
- }
-
+printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {
// Load/Store memory operands -- imm($reg)
// If PIC target the target is loaded as the
// pattern lw $25,%call16($28)
- printOperand(MI, opNum, O);
- O << "(";
printOperand(MI, opNum+1, O);
+ O << "(";
+ printOperand(MI, opNum, O);
O << ")";
}
void MipsAsmPrinter::
+printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
+ // when using stack locations for not load/store instructions
+ // print the same way as all normal 3 operand instructions.
+ printOperand(MI, opNum, O);
+ O << ", ";
+ printOperand(MI, opNum+1, O);
+ return;
+}
+
+void MipsAsmPrinter::
printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
const char *Modifier) {
const MachineOperand& MO = MI->getOperand(opNum);
@@ -466,7 +424,17 @@
}
// Force static initialization.
+static MCInstPrinter *createMipsMCInstPrinter(const Target &T,
+ unsigned SyntaxVariant,
+ const MCAsmInfo &MAI) {
+ return new MipsInstPrinter(MAI);
+}
+
extern "C" void LLVMInitializeMipsAsmPrinter() {
RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget);
RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget);
+
+ TargetRegistry::RegisterMCInstPrinter(TheMipsTarget, createMipsMCInstPrinter);
+ TargetRegistry::RegisterMCInstPrinter(TheMipselTarget,
+ createMipsMCInstPrinter);
}
Modified: llvm/branches/type-system-rewrite/lib/Target/Mips/MipsEmitGPRestore.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/Mips/MipsEmitGPRestore.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/Mips/MipsEmitGPRestore.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/Mips/MipsEmitGPRestore.cpp Thu Jul 7 23:45:15 2011
@@ -64,8 +64,8 @@
// Insert lw.
++I;
DebugLoc dl = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
- BuildMI(MBB, I, dl, TII->get(Mips::LW), Mips::GP).addImm(0)
- .addFrameIndex(FI);
+ BuildMI(MBB, I, dl, TII->get(Mips::LW), Mips::GP).addFrameIndex(FI)
+ .addImm(0);
Changed = true;
}
@@ -77,8 +77,8 @@
DebugLoc dl = I->getDebugLoc();
// emit lw $gp, ($gp save slot on stack) after jalr
- BuildMI(MBB, ++I, dl, TII->get(Mips::LW), Mips::GP).addImm(0)
- .addFrameIndex(FI);
+ BuildMI(MBB, ++I, dl, TII->get(Mips::LW), Mips::GP).addFrameIndex(FI)
+ .addImm(0);
Changed = true;
}
}
Modified: llvm/branches/type-system-rewrite/lib/Target/Mips/MipsISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/Mips/MipsISelDAGToDAG.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/Mips/MipsISelDAGToDAG.cpp Thu Jul 7 23:45:15 2011
@@ -113,7 +113,7 @@
/// ComplexPattern used on MipsInstrInfo
/// Used on Mips Load/Store instructions
bool MipsDAGToDAGISel::
-SelectAddr(SDValue Addr, SDValue &Offset, SDValue &Base) {
+SelectAddr(SDValue Addr, SDValue &Base, SDValue &Offset) {
// if Address is FI, get the TargetFrameIndex.
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
@@ -200,7 +200,7 @@
SDValue N1 = N->getOperand(1);
SDValue Offset0, Offset1, Base;
- if (!SelectAddr(N1, Offset0, Base) ||
+ if (!SelectAddr(N1, Base, Offset0) ||
N1.getValueType() != MVT::i32)
return NULL;
@@ -230,14 +230,14 @@
// lwc $f0, X($3)
// lwc $f1, X+4($3)
SDNode *LD0 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
- MVT::Other, Offset0, Base, Chain);
+ MVT::Other, Base, Offset0, Chain);
SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
dl, NVT), 0);
SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::sub_fpeven, dl,
MVT::f64, Undef, SDValue(LD0, 0));
SDNode *LD1 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
- MVT::Other, Offset1, Base, SDValue(LD0, 1));
+ MVT::Other, Base, Offset1, SDValue(LD0, 1));
SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::sub_fpodd, dl,
MVT::f64, I0, SDValue(LD1, 0));
@@ -264,7 +264,7 @@
SDValue N2 = N->getOperand(2);
SDValue Offset0, Offset1, Base;
- if (!SelectAddr(N2, Offset0, Base) ||
+ if (!SelectAddr(N2, Base, Offset0) ||
N1.getValueType() != MVT::f64 ||
N2.getValueType() != MVT::i32)
return NULL;
@@ -294,12 +294,12 @@
// Generate:
// swc $f0, X($3)
// swc $f1, X+4($3)
- SDValue Ops0[] = { FPEven, Offset0, Base, Chain };
+ SDValue Ops0[] = { FPEven, Base, Offset0, Chain };
Chain = SDValue(CurDAG->getMachineNode(Mips::SWC1, dl,
MVT::Other, Ops0, 4), 0);
cast<MachineSDNode>(Chain.getNode())->setMemRefs(MemRefs0, MemRefs0 + 1);
- SDValue Ops1[] = { FPOdd, Offset1, Base, Chain };
+ SDValue Ops1[] = { FPOdd, Base, Offset1, Chain };
Chain = SDValue(CurDAG->getMachineNode(Mips::SWC1, dl,
MVT::Other, Ops1, 4), 0);
cast<MachineSDNode>(Chain.getNode())->setMemRefs(MemRefs0, MemRefs0 + 1);
Modified: llvm/branches/type-system-rewrite/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/Mips/MipsISelLowering.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/Mips/MipsISelLowering.cpp Thu Jul 7 23:45:15 2011
@@ -23,6 +23,7 @@
#include "llvm/GlobalVariable.h"
#include "llvm/Intrinsics.h"
#include "llvm/CallingConv.h"
+#include "InstPrinter/MipsInstPrinter.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
@@ -774,7 +775,7 @@
}
BuildMI(BB, dl, TII->get(Mips::SW))
- .addReg(Incr).addImm(0).addFrameIndex(fi);
+ .addReg(Incr).addFrameIndex(fi).addImm(0);
}
BB->addSuccessor(loopMBB);
@@ -785,7 +786,7 @@
// sc tmp1, 0(ptr)
// beq tmp1, $0, loopMBB
BB = loopMBB;
- BuildMI(BB, dl, TII->get(Mips::LL), Oldval).addImm(0).addReg(Ptr);
+ BuildMI(BB, dl, TII->get(Mips::LL), Oldval).addReg(Ptr).addImm(0);
BuildMI(BB, dl, TII->get(Mips::OR), Dest).addReg(Mips::ZERO).addReg(Oldval);
if (Nand) {
// and tmp2, oldval, incr
@@ -798,10 +799,10 @@
} else {
// lw tmp2, fi(sp) // load incr from stack
// or tmp1, $zero, tmp2
- BuildMI(BB, dl, TII->get(Mips::LW), Tmp2).addImm(0).addFrameIndex(fi);;
+ BuildMI(BB, dl, TII->get(Mips::LW), Tmp2).addFrameIndex(fi).addImm(0);
BuildMI(BB, dl, TII->get(Mips::OR), Tmp1).addReg(Mips::ZERO).addReg(Tmp2);
}
- BuildMI(BB, dl, TII->get(Mips::SC), Tmp1).addReg(Tmp1).addImm(0).addReg(Ptr);
+ BuildMI(BB, dl, TII->get(Mips::SC), Tmp1).addReg(Tmp1).addReg(Ptr).addImm(0);
BuildMI(BB, dl, TII->get(Mips::BEQ))
.addReg(Tmp1).addReg(Mips::ZERO).addMBB(loopMBB);
BB->addSuccessor(loopMBB);
@@ -910,7 +911,7 @@
}
BuildMI(BB, dl, TII->get(Mips::SW))
- .addReg(Incr2).addImm(0).addFrameIndex(fi);
+ .addReg(Incr2).addFrameIndex(fi).addImm(0);
}
BB->addSuccessor(loopMBB);
@@ -923,7 +924,7 @@
// sc tmp9,0(addr)
// beq tmp9,$0,loopMBB
BB = loopMBB;
- BuildMI(BB, dl, TII->get(Mips::LL), Oldval).addImm(0).addReg(Addr);
+ BuildMI(BB, dl, TII->get(Mips::LL), Oldval).addReg(Addr).addImm(0);
if (Nand) {
// and tmp6, oldval, incr2
// nor tmp7, $0, tmp6
@@ -938,13 +939,13 @@
} else {
// lw tmp6, fi(sp) // load incr2 from stack
// or tmp7, $zero, tmp6
- BuildMI(BB, dl, TII->get(Mips::LW), Tmp6).addImm(0).addFrameIndex(fi);;
+ BuildMI(BB, dl, TII->get(Mips::LW), Tmp6).addFrameIndex(fi).addImm(0);
BuildMI(BB, dl, TII->get(Mips::OR), Tmp7).addReg(Mips::ZERO).addReg(Tmp6);
}
BuildMI(BB, dl, TII->get(Mips::AND), Newval).addReg(Tmp7).addReg(Mask);
BuildMI(BB, dl, TII->get(Mips::AND), Tmp8).addReg(Oldval).addReg(Mask2);
BuildMI(BB, dl, TII->get(Mips::OR), Tmp9).addReg(Tmp8).addReg(Newval);
- BuildMI(BB, dl, TII->get(Mips::SC), Tmp9).addReg(Tmp9).addImm(0).addReg(Addr);
+ BuildMI(BB, dl, TII->get(Mips::SC), Tmp9).addReg(Tmp9).addReg(Addr).addImm(0);
BuildMI(BB, dl, TII->get(Mips::BEQ))
.addReg(Tmp9).addReg(Mips::ZERO).addMBB(loopMBB);
BB->addSuccessor(loopMBB);
@@ -1027,14 +1028,14 @@
// hoist "or" instruction out of the block loop2MBB.
BuildMI(BB, dl, TII->get(Mips::SW))
- .addReg(Newval).addImm(0).addFrameIndex(fi);
+ .addReg(Newval).addFrameIndex(fi).addImm(0);
BB->addSuccessor(loop1MBB);
// loop1MBB:
// ll dest, 0(ptr)
// bne dest, oldval, exitMBB
BB = loop1MBB;
- BuildMI(BB, dl, TII->get(Mips::LL), Dest).addImm(0).addReg(Ptr);
+ BuildMI(BB, dl, TII->get(Mips::LL), Dest).addReg(Ptr).addImm(0);
BuildMI(BB, dl, TII->get(Mips::BNE))
.addReg(Dest).addReg(Oldval).addMBB(exitMBB);
BB->addSuccessor(exitMBB);
@@ -1046,9 +1047,9 @@
// sc tmp1, 0(ptr)
// beq tmp1, $0, loop1MBB
BB = loop2MBB;
- BuildMI(BB, dl, TII->get(Mips::LW), Tmp2).addImm(0).addFrameIndex(fi);;
+ BuildMI(BB, dl, TII->get(Mips::LW), Tmp2).addFrameIndex(fi).addImm(0);
BuildMI(BB, dl, TII->get(Mips::OR), Tmp1).addReg(Mips::ZERO).addReg(Tmp2);
- BuildMI(BB, dl, TII->get(Mips::SC), Tmp1).addReg(Tmp1).addImm(0).addReg(Ptr);
+ BuildMI(BB, dl, TII->get(Mips::SC), Tmp1).addReg(Tmp1).addReg(Ptr).addImm(0);
BuildMI(BB, dl, TII->get(Mips::BEQ))
.addReg(Tmp1).addReg(Mips::ZERO).addMBB(loop1MBB);
BB->addSuccessor(loop1MBB);
@@ -1143,7 +1144,7 @@
// and oldval4,oldval3,mask
// bne oldval4,oldval2,exitMBB
BB = loop1MBB;
- BuildMI(BB, dl, TII->get(Mips::LL), Oldval3).addImm(0).addReg(Addr);
+ BuildMI(BB, dl, TII->get(Mips::LL), Oldval3).addReg(Addr).addImm(0);
BuildMI(BB, dl, TII->get(Mips::AND), Oldval4).addReg(Oldval3).addReg(Mask);
BuildMI(BB, dl, TII->get(Mips::BNE))
.addReg(Oldval4).addReg(Oldval2).addMBB(exitMBB);
@@ -1159,7 +1160,7 @@
BuildMI(BB, dl, TII->get(Mips::AND), Tmp6).addReg(Oldval3).addReg(Mask2);
BuildMI(BB, dl, TII->get(Mips::OR), Tmp7).addReg(Tmp6).addReg(Newval2);
BuildMI(BB, dl, TII->get(Mips::SC), Tmp7)
- .addReg(Tmp7).addImm(0).addReg(Addr);
+ .addReg(Tmp7).addReg(Addr).addImm(0);
BuildMI(BB, dl, TII->get(Mips::BEQ))
.addReg(Tmp7).addReg(Mips::ZERO).addMBB(loop1MBB);
BB->addSuccessor(loop1MBB);
Modified: llvm/branches/type-system-rewrite/lib/Target/Mips/MipsInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/Mips/MipsInstrInfo.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/Mips/MipsInstrInfo.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/Mips/MipsInstrInfo.cpp Thu Jul 7 23:45:15 2011
@@ -14,6 +14,7 @@
#include "MipsInstrInfo.h"
#include "MipsTargetMachine.h"
#include "MipsMachineFunction.h"
+#include "InstPrinter/MipsInstPrinter.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
@@ -29,6 +30,11 @@
: MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
+
+const MipsRegisterInfo &MipsInstrInfo::getRegisterInfo() const {
+ return RI;
+}
+
static bool isZeroImm(const MachineOperand &op) {
return op.isImm() && op.getImm() == 0;
}
@@ -43,10 +49,10 @@
{
if ((MI->getOpcode() == Mips::LW) || (MI->getOpcode() == Mips::LWC1) ||
(MI->getOpcode() == Mips::LDC1)) {
- if ((MI->getOperand(2).isFI()) && // is a stack slot
- (MI->getOperand(1).isImm()) && // the imm is zero
- (isZeroImm(MI->getOperand(1)))) {
- FrameIndex = MI->getOperand(2).getIndex();
+ if ((MI->getOperand(1).isFI()) && // is a stack slot
+ (MI->getOperand(2).isImm()) && // the imm is zero
+ (isZeroImm(MI->getOperand(2)))) {
+ FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg();
}
}
@@ -64,10 +70,10 @@
{
if ((MI->getOpcode() == Mips::SW) || (MI->getOpcode() == Mips::SWC1) ||
(MI->getOpcode() == Mips::SDC1)) {
- if ((MI->getOperand(2).isFI()) && // is a stack slot
- (MI->getOperand(1).isImm()) && // the imm is zero
- (isZeroImm(MI->getOperand(1)))) {
- FrameIndex = MI->getOperand(2).getIndex();
+ if ((MI->getOperand(1).isFI()) && // is a stack slot
+ (MI->getOperand(2).isImm()) && // the imm is zero
+ (isZeroImm(MI->getOperand(2)))) {
+ FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg();
}
}
@@ -164,25 +170,25 @@
if (RC == Mips::CPURegsRegisterClass)
BuildMI(MBB, I, DL, get(Mips::SW)).addReg(SrcReg, getKillRegState(isKill))
- .addImm(0).addFrameIndex(FI);
+ .addFrameIndex(FI).addImm(0);
else if (RC == Mips::FGR32RegisterClass)
BuildMI(MBB, I, DL, get(Mips::SWC1)).addReg(SrcReg, getKillRegState(isKill))
- .addImm(0).addFrameIndex(FI);
+ .addFrameIndex(FI).addImm(0);
else if (RC == Mips::AFGR64RegisterClass) {
if (!TM.getSubtarget<MipsSubtarget>().isMips1()) {
BuildMI(MBB, I, DL, get(Mips::SDC1))
.addReg(SrcReg, getKillRegState(isKill))
- .addImm(0).addFrameIndex(FI);
+ .addFrameIndex(FI).addImm(0);
} else {
const TargetRegisterInfo *TRI =
MBB.getParent()->getTarget().getRegisterInfo();
const unsigned *SubSet = TRI->getSubRegisters(SrcReg);
BuildMI(MBB, I, DL, get(Mips::SWC1))
.addReg(SubSet[0], getKillRegState(isKill))
- .addImm(0).addFrameIndex(FI);
+ .addFrameIndex(FI).addImm(0);
BuildMI(MBB, I, DL, get(Mips::SWC1))
.addReg(SubSet[1], getKillRegState(isKill))
- .addImm(4).addFrameIndex(FI);
+ .addFrameIndex(FI).addImm(4);
}
} else
llvm_unreachable("Register class not handled!");
@@ -198,20 +204,20 @@
if (I != MBB.end()) DL = I->getDebugLoc();
if (RC == Mips::CPURegsRegisterClass)
- BuildMI(MBB, I, DL, get(Mips::LW), DestReg).addImm(0).addFrameIndex(FI);
+ BuildMI(MBB, I, DL, get(Mips::LW), DestReg).addFrameIndex(FI).addImm(0);
else if (RC == Mips::FGR32RegisterClass)
- BuildMI(MBB, I, DL, get(Mips::LWC1), DestReg).addImm(0).addFrameIndex(FI);
+ BuildMI(MBB, I, DL, get(Mips::LWC1), DestReg).addFrameIndex(FI).addImm(0);
else if (RC == Mips::AFGR64RegisterClass) {
if (!TM.getSubtarget<MipsSubtarget>().isMips1()) {
- BuildMI(MBB, I, DL, get(Mips::LDC1), DestReg).addImm(0).addFrameIndex(FI);
+ BuildMI(MBB, I, DL, get(Mips::LDC1), DestReg).addFrameIndex(FI).addImm(0);
} else {
const TargetRegisterInfo *TRI =
MBB.getParent()->getTarget().getRegisterInfo();
const unsigned *SubSet = TRI->getSubRegisters(DestReg);
BuildMI(MBB, I, DL, get(Mips::LWC1), SubSet[0])
- .addImm(0).addFrameIndex(FI);
+ .addFrameIndex(FI).addImm(0);
BuildMI(MBB, I, DL, get(Mips::LWC1), SubSet[1])
- .addImm(4).addFrameIndex(FI);
+ .addFrameIndex(FI).addImm(4);
}
} else
llvm_unreachable("Register class not handled!");
Modified: llvm/branches/type-system-rewrite/lib/Target/Mips/MipsInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/Mips/MipsInstrInfo.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/Mips/MipsInstrInfo.h (original)
+++ llvm/branches/type-system-rewrite/lib/Target/Mips/MipsInstrInfo.h Thu Jul 7 23:45:15 2011
@@ -25,100 +25,9 @@
namespace llvm {
namespace Mips {
-
- // Mips Branch Codes
- enum FPBranchCode {
- BRANCH_F,
- BRANCH_T,
- BRANCH_FL,
- BRANCH_TL,
- BRANCH_INVALID
- };
-
- // Mips Condition Codes
- enum CondCode {
- // To be used with float branch True
- FCOND_F,
- FCOND_UN,
- FCOND_OEQ,
- FCOND_UEQ,
- FCOND_OLT,
- FCOND_ULT,
- FCOND_OLE,
- FCOND_ULE,
- FCOND_SF,
- FCOND_NGLE,
- FCOND_SEQ,
- FCOND_NGL,
- FCOND_LT,
- FCOND_NGE,
- FCOND_LE,
- FCOND_NGT,
-
- // To be used with float branch False
- // This conditions have the same mnemonic as the
- // above ones, but are used with a branch False;
- FCOND_T,
- FCOND_OR,
- FCOND_UNE,
- FCOND_ONE,
- FCOND_UGE,
- FCOND_OGE,
- FCOND_UGT,
- FCOND_OGT,
- FCOND_ST,
- FCOND_GLE,
- FCOND_SNE,
- FCOND_GL,
- FCOND_NLT,
- FCOND_GE,
- FCOND_NLE,
- FCOND_GT
- };
-
/// GetOppositeBranchOpc - Return the inverse of the specified
/// opcode, e.g. turning BEQ to BNE.
unsigned GetOppositeBranchOpc(unsigned Opc);
-
- /// MipsCCToString - Map each FP condition code to its string
- inline static const char *MipsFCCToString(Mips::CondCode CC)
- {
- switch (CC) {
- default: llvm_unreachable("Unknown condition code");
- case FCOND_F:
- case FCOND_T: return "f";
- case FCOND_UN:
- case FCOND_OR: return "un";
- case FCOND_OEQ:
- case FCOND_UNE: return "eq";
- case FCOND_UEQ:
- case FCOND_ONE: return "ueq";
- case FCOND_OLT:
- case FCOND_UGE: return "olt";
- case FCOND_ULT:
- case FCOND_OGE: return "ult";
- case FCOND_OLE:
- case FCOND_UGT: return "ole";
- case FCOND_ULE:
- case FCOND_OGT: return "ule";
- case FCOND_SF:
- case FCOND_ST: return "sf";
- case FCOND_NGLE:
- case FCOND_GLE: return "ngle";
- case FCOND_SEQ:
- case FCOND_SNE: return "seq";
- case FCOND_NGL:
- case FCOND_GL: return "ngl";
- case FCOND_LT:
- case FCOND_NLT: return "lt";
- case FCOND_NGE:
- case FCOND_GE: return "nge";
- case FCOND_LE:
- case FCOND_NLE: return "le";
- case FCOND_NGT:
- case FCOND_GT: return "ngt";
- }
- }
}
/// MipsII - This namespace holds all of the target specific flags that
@@ -177,7 +86,7 @@
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
///
- virtual const MipsRegisterInfo &getRegisterInfo() const { return RI; }
+ virtual const MipsRegisterInfo &getRegisterInfo() const;
/// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of
Modified: llvm/branches/type-system-rewrite/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/Mips/MipsInstrInfo.td?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/branches/type-system-rewrite/lib/Target/Mips/MipsInstrInfo.td Thu Jul 7 23:45:15 2011
@@ -134,7 +134,12 @@
// Address operand
def mem : Operand<i32> {
let PrintMethod = "printMemOperand";
- let MIOperandInfo = (ops simm16, CPURegs);
+ let MIOperandInfo = (ops CPURegs, simm16);
+}
+
+def mem_ea : Operand<i32> {
+ let PrintMethod = "printMemOperandEA";
+ let MIOperandInfo = (ops CPURegs, simm16);
}
// Transformation Function - get the lower 16 bits.
@@ -351,7 +356,7 @@
!strconcat(instr_asm, "\t$src"), [], IIHiLo>;
class EffectiveAddress<string instr_asm> :
- FI<0x09, (outs CPURegs:$dst), (ins mem:$addr),
+ FI<0x09, (outs CPURegs:$dst), (ins mem_ea:$addr),
instr_asm, [(set CPURegs:$dst, addr:$addr)], IIAlu>;
// Count Leading Ones/Zeros in Word
@@ -419,7 +424,7 @@
// are used, we have the same behavior, but get also a bunch of warnings
// from the assembler.
def CPLOAD : MipsPseudo<(outs), (ins CPURegs:$picreg), ".cpload\t$picreg", []>;
-def CPRESTORE : MipsPseudo<(outs), (ins i32imm:$loc), ".cprestore\t$loc\n", []>;
+def CPRESTORE : MipsPseudo<(outs), (ins i32imm:$loc), ".cprestore\t$loc", []>;
let usesCustomInserter = 1 in {
def ATOMIC_LOAD_ADD_I8 : MipsPseudo<
@@ -680,13 +685,13 @@
// instructions. The same not happens for stack address copies, so an
// add op with mem ComplexPattern is used and the stack address copy
// can be matched. It's similar to Sparc LEA_ADDRi
-def LEA_ADDiu : EffectiveAddress<"addiu\t$dst, ${addr:stackloc}">;
+def LEA_ADDiu : EffectiveAddress<"addiu\t$dst, $addr">;
// DynAlloc node points to dynamically allocated stack space.
// $sp is added to the list of implicitly used registers to prevent dead code
// elimination from removing instructions that modify $sp.
let Uses = [SP] in
-def DynAlloc : EffectiveAddress<"addiu\t$dst, ${addr:stackloc}">;
+def DynAlloc : EffectiveAddress<"addiu\t$dst, $addr">;
// MADD*/MSUB*
def MADD : MArithR<0, "madd", MipsMAdd, 1>;
Modified: llvm/branches/type-system-rewrite/lib/Target/Mips/MipsMCAsmInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/Mips/MipsMCAsmInfo.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/Mips/MipsMCAsmInfo.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/Mips/MipsMCAsmInfo.cpp Thu Jul 7 23:45:15 2011
@@ -28,4 +28,5 @@
SupportsDebugInformation = true;
ExceptionsType = ExceptionHandling::DwarfCFI;
HasLEB128 = true;
+ DwarfRegNumForCFI = true;
}
Modified: llvm/branches/type-system-rewrite/lib/Target/Mips/MipsRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/Mips/MipsRegisterInfo.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/Mips/MipsRegisterInfo.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/Mips/MipsRegisterInfo.cpp Thu Jul 7 23:45:15 2011
@@ -218,51 +218,31 @@
else
Offset = spOffset + stackSize;
- if (MI.isDebugValue()) {
- MI.getOperand(i).ChangeToRegister(FrameReg, false /*isDef*/);
- MI.getOperand(i+1).ChangeToImmediate(Offset);
- return;
- }
-
- Offset += MI.getOperand(i-1).getImm();
+ Offset += MI.getOperand(i+1).getImm();
DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
- unsigned NewReg = 0;
- int NewImm = 0;
- MachineBasicBlock &MBB = *MI.getParent();
- bool ATUsed;
-
- // Offset fits in the 16-bit field
- if (Offset < 0x8000 && Offset >= -0x8000) {
- NewReg = FrameReg;
- NewImm = Offset;
- ATUsed = false;
- }
- else {
- const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
+ // If MI is not a debug value, make sure Offset fits in the 16-bit immediate
+ // field.
+ if (!MI.isDebugValue() && (Offset >= 0x8000 || Offset < -0x8000)) {
+ MachineBasicBlock &MBB = *MI.getParent();
DebugLoc DL = II->getDebugLoc();
- int ImmLo = (short)(Offset & 0xffff);
int ImmHi = (((unsigned)Offset & 0xffff0000) >> 16) +
((Offset & 0x8000) != 0);
// FIXME: change this when mips goes MC".
- BuildMI(MBB, II, DL, TII->get(Mips::NOAT));
- BuildMI(MBB, II, DL, TII->get(Mips::LUi), Mips::AT).addImm(ImmHi);
- BuildMI(MBB, II, DL, TII->get(Mips::ADDu), Mips::AT).addReg(FrameReg)
- .addReg(Mips::AT);
- NewReg = Mips::AT;
- NewImm = ImmLo;
-
- ATUsed = true;
- }
+ BuildMI(MBB, II, DL, TII.get(Mips::NOAT));
+ BuildMI(MBB, II, DL, TII.get(Mips::LUi), Mips::AT).addImm(ImmHi);
+ BuildMI(MBB, II, DL, TII.get(Mips::ADDu), Mips::AT).addReg(FrameReg)
+ .addReg(Mips::AT);
+ FrameReg = Mips::AT;
+ Offset = (short)(Offset & 0xffff);
- // FIXME: change this when mips goes MC".
- if (ATUsed)
BuildMI(MBB, ++II, MI.getDebugLoc(), TII.get(Mips::ATMACRO));
+ }
- MI.getOperand(i).ChangeToRegister(NewReg, false);
- MI.getOperand(i-1).ChangeToImmediate(NewImm);
+ MI.getOperand(i).ChangeToRegister(FrameReg, false);
+ MI.getOperand(i+1).ChangeToImmediate(Offset);
}
unsigned MipsRegisterInfo::
Modified: llvm/branches/type-system-rewrite/lib/Target/Mips/MipsSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/Mips/MipsSubtarget.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/Mips/MipsSubtarget.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/Mips/MipsSubtarget.cpp Thu Jul 7 23:45:15 2011
@@ -14,16 +14,17 @@
#include "MipsSubtarget.h"
#include "Mips.h"
-#define GET_SUBTARGETINFO_CTOR
+#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
#define GET_SUBTARGETINFO_TARGET_DESC
+#define GET_SUBTARGETINFO_CTOR
#include "MipsGenSubtargetInfo.inc"
using namespace llvm;
MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS, bool little) :
- MipsGenSubtargetInfo(),
+ MipsGenSubtargetInfo(TT, CPU, FS),
MipsArchVersion(Mips1), MipsABI(O32), IsLittle(little), IsSingleFloat(false),
IsFP64bit(false), IsGP64bit(false), HasVFPU(false), IsLinux(true),
HasSEInReg(false), HasCondMov(false), HasMulDivAdd(false), HasMinMax(false),
@@ -35,7 +36,7 @@
MipsArchVersion = Mips1;
// Parse features string.
- ParseSubtargetFeatures(FS, CPUName);
+ ParseSubtargetFeatures(CPUName, FS);
// Initialize scheduling itinerary for the specified CPU.
InstrItins = getInstrItineraryForCPU(CPUName);
Modified: llvm/branches/type-system-rewrite/lib/Target/Mips/MipsSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/Mips/MipsSubtarget.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/Mips/MipsSubtarget.h (original)
+++ llvm/branches/type-system-rewrite/lib/Target/Mips/MipsSubtarget.h Thu Jul 7 23:45:15 2011
@@ -22,6 +22,7 @@
#include "MipsGenSubtargetInfo.inc"
namespace llvm {
+class StringRef;
class MipsSubtarget : public MipsGenSubtargetInfo {
@@ -99,7 +100,7 @@
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
- void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
+ void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
bool isMips1() const { return MipsArchVersion == Mips1; }
bool isMips32() const { return MipsArchVersion >= Mips32; }
Modified: llvm/branches/type-system-rewrite/lib/Target/Mips/MipsTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/Mips/MipsTargetMachine.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/Mips/MipsTargetMachine.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/Mips/MipsTargetMachine.cpp Thu Jul 7 23:45:15 2011
@@ -37,7 +37,7 @@
MipsTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU, const std::string &FS,
bool isLittle=false):
- LLVMTargetMachine(T, TT),
+ LLVMTargetMachine(T, TT, CPU, FS),
Subtarget(TT, CPU, FS, isLittle),
DataLayout(isLittle ?
std::string("e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") :
Modified: llvm/branches/type-system-rewrite/lib/Target/PTX/PTXSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/PTX/PTXSubtarget.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/PTX/PTXSubtarget.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/PTX/PTXSubtarget.cpp Thu Jul 7 23:45:15 2011
@@ -14,16 +14,17 @@
#include "PTXSubtarget.h"
#include "llvm/Support/ErrorHandling.h"
-#define GET_SUBTARGETINFO_CTOR
+#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
#define GET_SUBTARGETINFO_TARGET_DESC
+#define GET_SUBTARGETINFO_CTOR
#include "PTXGenSubtargetInfo.inc"
using namespace llvm;
PTXSubtarget::PTXSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS, bool is64Bit)
- : PTXGenSubtargetInfo(),
+ : PTXGenSubtargetInfo(TT, CPU, FS),
PTXTarget(PTX_COMPUTE_1_0),
PTXVersion(PTX_VERSION_2_0),
SupportsDouble(false),
@@ -32,7 +33,7 @@
std::string TARGET = CPU;
if (TARGET.empty())
TARGET = "generic";
- ParseSubtargetFeatures(FS, TARGET);
+ ParseSubtargetFeatures(TARGET, FS);
}
std::string PTXSubtarget::getTargetString() const {
Modified: llvm/branches/type-system-rewrite/lib/Target/PTX/PTXSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/PTX/PTXSubtarget.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/PTX/PTXSubtarget.h (original)
+++ llvm/branches/type-system-rewrite/lib/Target/PTX/PTXSubtarget.h Thu Jul 7 23:45:15 2011
@@ -20,6 +20,8 @@
#include "PTXGenSubtargetInfo.inc"
namespace llvm {
+class StringRef;
+
class PTXSubtarget : public PTXGenSubtargetInfo {
public:
@@ -112,8 +114,7 @@
(PTXTarget >= PTX_COMPUTE_2_0 && PTXTarget < PTX_LAST_COMPUTE);
}
- void ParseSubtargetFeatures(const std::string &FS,
- const std::string &CPU);
+ void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
}; // class PTXSubtarget
} // namespace llvm
Modified: llvm/branches/type-system-rewrite/lib/Target/PTX/PTXTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/PTX/PTXTargetMachine.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/PTX/PTXTargetMachine.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/PTX/PTXTargetMachine.cpp Thu Jul 7 23:45:15 2011
@@ -55,7 +55,7 @@
const std::string &CPU,
const std::string &FS,
bool is64Bit)
- : LLVMTargetMachine(T, TT),
+ : LLVMTargetMachine(T, TT, CPU, FS),
DataLayout(is64Bit ? DataLayout64 : DataLayout32),
Subtarget(TT, CPU, FS, is64Bit),
FrameLowering(Subtarget),
Modified: llvm/branches/type-system-rewrite/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h (original)
+++ llvm/branches/type-system-rewrite/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h Thu Jul 7 23:45:15 2011
@@ -19,14 +19,12 @@
namespace llvm {
class MCOperand;
-class TargetMachine;
class PPCInstPrinter : public MCInstPrinter {
// 0 -> AIX, 1 -> Darwin.
unsigned SyntaxVariant;
public:
- PPCInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI,
- unsigned syntaxVariant)
+ PPCInstPrinter(const MCAsmInfo &MAI, unsigned syntaxVariant)
: MCInstPrinter(MAI), SyntaxVariant(syntaxVariant) {}
bool isDarwinSyntax() const {
Modified: llvm/branches/type-system-rewrite/lib/Target/PowerPC/PPCAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/PowerPC/PPCAsmPrinter.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/PowerPC/PPCAsmPrinter.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/PowerPC/PPCAsmPrinter.cpp Thu Jul 7 23:45:15 2011
@@ -680,10 +680,9 @@
}
static MCInstPrinter *createPPCMCInstPrinter(const Target &T,
- TargetMachine &TM,
unsigned SyntaxVariant,
const MCAsmInfo &MAI) {
- return new PPCInstPrinter(TM, MAI, SyntaxVariant);
+ return new PPCInstPrinter(MAI, SyntaxVariant);
}
Modified: llvm/branches/type-system-rewrite/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/PowerPC/PPCISelLowering.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/PowerPC/PPCISelLowering.cpp Thu Jul 7 23:45:15 2011
@@ -1321,9 +1321,6 @@
SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
DAG.getConstant(8, MVT::i32), ISD::SETLT);
- SDValue Area = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, RegSaveArea,
- OverflowArea);
-
// adjustment constant gpr_index * 4/8
SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
VT.isInteger() ? GprIndex : FprIndex,
Modified: llvm/branches/type-system-rewrite/lib/Target/PowerPC/PPCSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/PowerPC/PPCSubtarget.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/PowerPC/PPCSubtarget.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/PowerPC/PPCSubtarget.cpp Thu Jul 7 23:45:15 2011
@@ -17,9 +17,10 @@
#include "llvm/Target/TargetMachine.h"
#include <cstdlib>
-#define GET_SUBTARGETINFO_CTOR
+#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
#define GET_SUBTARGETINFO_TARGET_DESC
+#define GET_SUBTARGETINFO_CTOR
#include "PPCGenSubtargetInfo.inc"
using namespace llvm;
@@ -64,7 +65,7 @@
PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS, bool is64Bit)
- : PPCGenSubtargetInfo()
+ : PPCGenSubtargetInfo(TT, CPU, FS)
, StackAlignment(16)
, DarwinDirective(PPC::DIR_NONE)
, IsGigaProcessor(false)
@@ -88,7 +89,7 @@
#endif
// Parse features string.
- ParseSubtargetFeatures(FS, CPUName);
+ ParseSubtargetFeatures(CPUName, FS);
// Initialize scheduling itinerary for the specified CPU.
InstrItins = getInstrItineraryForCPU(CPUName);
Modified: llvm/branches/type-system-rewrite/lib/Target/PowerPC/PPCSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/PowerPC/PPCSubtarget.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/PowerPC/PPCSubtarget.h (original)
+++ llvm/branches/type-system-rewrite/lib/Target/PowerPC/PPCSubtarget.h Thu Jul 7 23:45:15 2011
@@ -26,6 +26,7 @@
#undef PPC
namespace llvm {
+class StringRef;
namespace PPC {
// -m directive values.
@@ -80,8 +81,7 @@
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
- void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
-
+ void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
/// SetJITMode - This is called to inform the subtarget info that we are
/// producing code for the JIT.
@@ -106,7 +106,7 @@
// Note, the alignment values for f64 and i64 on ppc64 in Darwin
// documentation are wrong; these are correct (i.e. "what gcc does").
return isPPC64() ? "E-p:64:64-f64:64:64-i64:64:64-f128:64:128-n32:64"
- : "E-p:32:32-f64:32:64-i64:32:64-f128:64:128-n32";
+ : "E-p:32:32-f64:64:64-i64:64:64-f128:64:128-n32";
}
/// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
Modified: llvm/branches/type-system-rewrite/lib/Target/PowerPC/PPCTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/PowerPC/PPCTargetMachine.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/PowerPC/PPCTargetMachine.cpp Thu Jul 7 23:45:15 2011
@@ -69,7 +69,7 @@
PPCTargetMachine::PPCTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU,
const std::string &FS, bool is64Bit)
- : LLVMTargetMachine(T, TT),
+ : LLVMTargetMachine(T, TT, CPU, FS),
Subtarget(TT, CPU, FS, is64Bit),
DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
FrameLowering(Subtarget), JITInfo(*this, is64Bit),
Modified: llvm/branches/type-system-rewrite/lib/Target/Sparc/SparcSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/Sparc/SparcSubtarget.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/Sparc/SparcSubtarget.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/Sparc/SparcSubtarget.cpp Thu Jul 7 23:45:15 2011
@@ -13,16 +13,17 @@
#include "SparcSubtarget.h"
-#define GET_SUBTARGETINFO_CTOR
+#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
#define GET_SUBTARGETINFO_TARGET_DESC
+#define GET_SUBTARGETINFO_CTOR
#include "SparcGenSubtargetInfo.inc"
using namespace llvm;
SparcSubtarget::SparcSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS, bool is64Bit) :
- SparcGenSubtargetInfo(),
+ SparcGenSubtargetInfo(TT, CPU, FS),
IsV9(false),
V8DeprecatedInsts(false),
IsVIS(false),
@@ -39,5 +40,5 @@
IsV9 = CPUName == "v9";
// Parse features string.
- ParseSubtargetFeatures(FS, CPUName);
+ ParseSubtargetFeatures(CPUName, FS);
}
Modified: llvm/branches/type-system-rewrite/lib/Target/Sparc/SparcSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/Sparc/SparcSubtarget.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/Sparc/SparcSubtarget.h (original)
+++ llvm/branches/type-system-rewrite/lib/Target/Sparc/SparcSubtarget.h Thu Jul 7 23:45:15 2011
@@ -21,6 +21,7 @@
#include "SparcGenSubtargetInfo.inc"
namespace llvm {
+class StringRef;
class SparcSubtarget : public SparcGenSubtargetInfo {
bool IsV9;
@@ -38,7 +39,7 @@
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
- void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
+ void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
bool is64Bit() const { return Is64Bit; }
std::string getDataLayout() const {
Modified: llvm/branches/type-system-rewrite/lib/Target/Sparc/SparcTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/Sparc/SparcTargetMachine.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/Sparc/SparcTargetMachine.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/Sparc/SparcTargetMachine.cpp Thu Jul 7 23:45:15 2011
@@ -32,7 +32,7 @@
SparcTargetMachine::SparcTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU,
const std::string &FS, bool is64bit)
- : LLVMTargetMachine(T, TT),
+ : LLVMTargetMachine(T, TT, CPU, FS),
Subtarget(TT, CPU, FS, is64bit),
DataLayout(Subtarget.getDataLayout()),
TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget),
Modified: llvm/branches/type-system-rewrite/lib/Target/SystemZ/SystemZSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/SystemZ/SystemZSubtarget.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/SystemZ/SystemZSubtarget.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/SystemZ/SystemZSubtarget.cpp Thu Jul 7 23:45:15 2011
@@ -16,9 +16,10 @@
#include "llvm/GlobalValue.h"
#include "llvm/Target/TargetMachine.h"
-#define GET_SUBTARGETINFO_CTOR
+#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
#define GET_SUBTARGETINFO_TARGET_DESC
+#define GET_SUBTARGETINFO_CTOR
#include "SystemZGenSubtargetInfo.inc"
using namespace llvm;
@@ -26,13 +27,13 @@
SystemZSubtarget::SystemZSubtarget(const std::string &TT,
const std::string &CPU,
const std::string &FS):
- SystemZGenSubtargetInfo(), HasZ10Insts(false) {
+ SystemZGenSubtargetInfo(TT, CPU, FS), HasZ10Insts(false) {
std::string CPUName = CPU;
if (CPUName.empty())
CPUName = "z9";
// Parse features string.
- ParseSubtargetFeatures(FS, CPUName);
+ ParseSubtargetFeatures(CPUName, FS);
}
/// True if accessing the GV requires an extra load.
Modified: llvm/branches/type-system-rewrite/lib/Target/SystemZ/SystemZSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/SystemZ/SystemZSubtarget.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/SystemZ/SystemZSubtarget.h (original)
+++ llvm/branches/type-system-rewrite/lib/Target/SystemZ/SystemZSubtarget.h Thu Jul 7 23:45:15 2011
@@ -22,6 +22,7 @@
namespace llvm {
class GlobalValue;
+class StringRef;
class TargetMachine;
class SystemZSubtarget : public SystemZGenSubtargetInfo {
@@ -35,7 +36,7 @@
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
- void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
+ void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
bool isZ10() const { return HasZ10Insts; }
Modified: llvm/branches/type-system-rewrite/lib/Target/SystemZ/SystemZTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/SystemZ/SystemZTargetMachine.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/SystemZ/SystemZTargetMachine.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/SystemZ/SystemZTargetMachine.cpp Thu Jul 7 23:45:15 2011
@@ -26,7 +26,7 @@
const std::string &TT,
const std::string &CPU,
const std::string &FS)
- : LLVMTargetMachine(T, TT),
+ : LLVMTargetMachine(T, TT, CPU, FS),
Subtarget(TT, CPU, FS),
DataLayout("E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32"
"-f64:64:64-f128:128:128-a0:16:16-n32:64"),
Modified: llvm/branches/type-system-rewrite/lib/Target/TargetAsmInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/TargetAsmInfo.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/TargetAsmInfo.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/TargetAsmInfo.cpp Thu Jul 7 23:45:15 2011
@@ -20,8 +20,15 @@
const TargetData &TD = *TM.getTargetData();
IsLittleEndian = TD.isLittleEndian();
PointerSize = TD.getPointerSize();
- const TargetFrameLowering &TFI = *TM.getFrameLowering();
- StackDir = TFI.getStackGrowthDirection();
+
+ TFI = TM.getFrameLowering();
+ StackDir = TFI->getStackGrowthDirection();
TRI = TM.getRegisterInfo();
- TFI.getInitialFrameState(InitialFrameState);
+ TFI->getInitialFrameState(InitialFrameState);
+}
+
+int TargetAsmInfo::getCompactUnwindEncoding(ArrayRef<MCCFIInstruction> Instrs,
+ int DataAlignmentFactor,
+ bool IsEH) const {
+ return TFI->getCompactUnwindEncoding(Instrs, DataAlignmentFactor, IsEH);
}
Modified: llvm/branches/type-system-rewrite/lib/Target/TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/TargetMachine.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/TargetMachine.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/TargetMachine.cpp Thu Jul 7 23:45:15 2011
@@ -216,8 +216,9 @@
// TargetMachine Class
//
-TargetMachine::TargetMachine(const Target &T)
- : TheTarget(T), AsmInfo(0),
+TargetMachine::TargetMachine(const Target &T,
+ StringRef TT, StringRef CPU, StringRef FS)
+ : TheTarget(T), TargetTriple(TT), TargetCPU(CPU), TargetFS(FS), AsmInfo(0),
MCRelaxAll(false),
MCNoExecStack(false),
MCSaveTempLabels(false),
Modified: llvm/branches/type-system-rewrite/lib/Target/X86/AsmParser/X86AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/X86/AsmParser/X86AsmParser.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/X86/AsmParser/X86AsmParser.cpp Thu Jul 7 23:45:15 2011
@@ -15,6 +15,7 @@
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCParser/MCAsmLexer.h"
#include "llvm/MC/MCParser/MCAsmParser.h"
#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
@@ -25,6 +26,10 @@
#include "llvm/ADT/Twine.h"
#include "llvm/Support/SourceMgr.h"
#include "llvm/Support/raw_ostream.h"
+
+#define GET_SUBTARGETINFO_ENUM
+#include "X86GenSubtargetInfo.inc"
+
using namespace llvm;
namespace {
@@ -32,10 +37,7 @@
class X86ATTAsmParser : public TargetAsmParser {
MCAsmParser &Parser;
- TargetMachine &TM;
-
-protected:
- unsigned Is64Bit : 1;
+ MCSubtargetInfo *STI;
private:
MCAsmParser &getParser() const { return Parser; }
@@ -61,6 +63,11 @@
/// or %es:(%edi) in 32bit mode.
bool isDstOp(X86Operand &Op);
+ bool is64Bit() {
+ // FIXME: Can tablegen auto-generate this?
+ return (STI->getFeatureBits() & X86::Mode64Bit) != 0;
+ }
+
/// @name Auto-generated Matcher Functions
/// {
@@ -70,12 +77,13 @@
/// }
public:
- X86ATTAsmParser(const Target &T, MCAsmParser &parser, TargetMachine &TM)
- : TargetAsmParser(T), Parser(parser), TM(TM) {
+ X86ATTAsmParser(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
+ MCAsmParser &parser)
+ : TargetAsmParser(T), Parser(parser) {
+ STI = X86_MC::createX86MCSubtargetInfo(TT, CPU, FS);
// Initialize the set of available features.
- setAvailableFeatures(ComputeAvailableFeatures(
- &TM.getSubtarget<X86Subtarget>()));
+ setAvailableFeatures(ComputeAvailableFeatures(STI->getFeatureBits()));
}
virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
@@ -84,23 +92,6 @@
virtual bool ParseDirective(AsmToken DirectiveID);
};
-
-class X86_32ATTAsmParser : public X86ATTAsmParser {
-public:
- X86_32ATTAsmParser(const Target &T, MCAsmParser &Parser, TargetMachine &TM)
- : X86ATTAsmParser(T, Parser, TM) {
- Is64Bit = false;
- }
-};
-
-class X86_64ATTAsmParser : public X86ATTAsmParser {
-public:
- X86_64ATTAsmParser(const Target &T, MCAsmParser &Parser, TargetMachine &TM)
- : X86ATTAsmParser(T, Parser, TM) {
- Is64Bit = true;
- }
-};
-
} // end anonymous namespace
/// @name Auto-generated Match Functions
@@ -365,7 +356,7 @@
} // end anonymous namespace.
bool X86ATTAsmParser::isSrcOp(X86Operand &Op) {
- unsigned basereg = Is64Bit ? X86::RSI : X86::ESI;
+ unsigned basereg = is64Bit() ? X86::RSI : X86::ESI;
return (Op.isMem() &&
(Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::DS) &&
@@ -375,7 +366,7 @@
}
bool X86ATTAsmParser::isDstOp(X86Operand &Op) {
- unsigned basereg = Is64Bit ? X86::RDI : X86::EDI;
+ unsigned basereg = is64Bit() ? X86::RDI : X86::EDI;
return Op.isMem() && Op.Mem.SegReg == X86::ES &&
isa<MCConstantExpr>(Op.Mem.Disp) &&
@@ -406,7 +397,7 @@
// FIXME: This should be done using Requires<In32BitMode> and
// Requires<In64BitMode> so "eiz" usage in 64-bit instructions
// can be also checked.
- if (RegNo == X86::RIZ && !Is64Bit)
+ if (RegNo == X86::RIZ && !is64Bit())
return Error(Tok.getLoc(), "riz register in 64-bit mode only");
// Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
@@ -710,23 +701,6 @@
}
}
- // FIXME: Hack to recognize vpclmul<src1_quadword, src2_quadword>dq
- if (PatchedName.startswith("vpclmul")) {
- unsigned CLMULQuadWordSelect = StringSwitch<unsigned>(
- PatchedName.slice(7, PatchedName.size() - 2))
- .Case("lqlq", 0x00) // src1[63:0], src2[63:0]
- .Case("hqlq", 0x01) // src1[127:64], src2[63:0]
- .Case("lqhq", 0x10) // src1[63:0], src2[127:64]
- .Case("hqhq", 0x11) // src1[127:64], src2[127:64]
- .Default(~0U);
- if (CLMULQuadWordSelect != ~0U) {
- ExtraImmOp = MCConstantExpr::Create(CLMULQuadWordSelect,
- getParser().getContext());
- assert(PatchedName.endswith("dq") && "Unexpected mnemonic!");
- PatchedName = "vpclmulqdq";
- }
- }
-
Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
if (ExtraImmOp)
@@ -843,7 +817,7 @@
// Transform "movs[bwl] %ds:(%esi), %es:(%edi)" into "movs[bwl]"
if (Name.startswith("movs") && Operands.size() == 3 &&
(Name == "movsb" || Name == "movsw" || Name == "movsl" ||
- (Is64Bit && Name == "movsq"))) {
+ (is64Bit() && Name == "movsq"))) {
X86Operand &Op = *(X86Operand*)Operands.begin()[1];
X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
if (isSrcOp(Op) && isDstOp(Op2)) {
@@ -856,7 +830,7 @@
// Transform "lods[bwl] %ds:(%esi),{%al,%ax,%eax,%rax}" into "lods[bwl]"
if (Name.startswith("lods") && Operands.size() == 3 &&
(Name == "lods" || Name == "lodsb" || Name == "lodsw" ||
- Name == "lodsl" || (Is64Bit && Name == "lodsq"))) {
+ Name == "lodsl" || (is64Bit() && Name == "lodsq"))) {
X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]);
if (isSrcOp(*Op1) && Op2->isReg()) {
@@ -886,7 +860,7 @@
// Transform "stos[bwl] {%al,%ax,%eax,%rax},%es:(%edi)" into "stos[bwl]"
if (Name.startswith("stos") && Operands.size() == 3 &&
(Name == "stos" || Name == "stosb" || Name == "stosw" ||
- Name == "stosl" || (Is64Bit && Name == "stosq"))) {
+ Name == "stosl" || (is64Bit() && Name == "stosq"))) {
X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]);
if (isDstOp(*Op2) && Op1->isReg()) {
@@ -1161,8 +1135,8 @@
// Force static initialization.
extern "C" void LLVMInitializeX86AsmParser() {
- RegisterAsmParser<X86_32ATTAsmParser> X(TheX86_32Target);
- RegisterAsmParser<X86_64ATTAsmParser> Y(TheX86_64Target);
+ RegisterAsmParser<X86ATTAsmParser> X(TheX86_32Target);
+ RegisterAsmParser<X86ATTAsmParser> Y(TheX86_64Target);
LLVMInitializeX86AsmLexer();
}
Modified: llvm/branches/type-system-rewrite/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp Thu Jul 7 23:45:15 2011
@@ -15,8 +15,7 @@
#define DEBUG_TYPE "asm-printer"
#include "X86ATTInstPrinter.h"
#include "X86InstComments.h"
-#include "X86Subtarget.h"
-#include "MCTargetDesc/X86TargetDesc.h"
+#include "MCTargetDesc/X86MCTargetDesc.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCExpr.h"
@@ -31,11 +30,8 @@
#define PRINT_ALIAS_INSTR
#include "X86GenAsmWriter.inc"
-X86ATTInstPrinter::X86ATTInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI)
+X86ATTInstPrinter::X86ATTInstPrinter(const MCAsmInfo &MAI)
: MCInstPrinter(MAI) {
- // Initialize the set of available features.
- setAvailableFeatures(ComputeAvailableFeatures(
- &TM.getSubtarget<X86Subtarget>()));
}
void X86ATTInstPrinter::printRegName(raw_ostream &OS,
Modified: llvm/branches/type-system-rewrite/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h (original)
+++ llvm/branches/type-system-rewrite/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h Thu Jul 7 23:45:15 2011
@@ -19,19 +19,15 @@
namespace llvm {
class MCOperand;
-class X86Subtarget;
-class TargetMachine;
class X86ATTInstPrinter : public MCInstPrinter {
public:
- X86ATTInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI);
+ X86ATTInstPrinter(const MCAsmInfo &MAI);
virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
virtual void printInst(const MCInst *MI, raw_ostream &OS);
virtual StringRef getOpcodeName(unsigned Opcode) const;
- // Methods used to print the alias of an instruction.
- unsigned ComputeAvailableFeatures(const X86Subtarget *Subtarget) const;
// Autogenerated by tblgen, returns true if we successfully printed an
// alias.
bool printAliasInstr(const MCInst *MI, raw_ostream &OS);
Modified: llvm/branches/type-system-rewrite/lib/Target/X86/InstPrinter/X86InstComments.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/X86/InstPrinter/X86InstComments.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/X86/InstPrinter/X86InstComments.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/X86/InstPrinter/X86InstComments.cpp Thu Jul 7 23:45:15 2011
@@ -13,7 +13,7 @@
//===----------------------------------------------------------------------===//
#include "X86InstComments.h"
-#include "MCTargetDesc/X86TargetDesc.h"
+#include "MCTargetDesc/X86MCTargetDesc.h"
#include "llvm/MC/MCInst.h"
#include "llvm/Support/raw_ostream.h"
#include "../Utils/X86ShuffleDecode.h"
Modified: llvm/branches/type-system-rewrite/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp Thu Jul 7 23:45:15 2011
@@ -15,8 +15,7 @@
#define DEBUG_TYPE "asm-printer"
#include "X86IntelInstPrinter.h"
#include "X86InstComments.h"
-#include "X86Subtarget.h"
-#include "MCTargetDesc/X86TargetDesc.h"
+#include "MCTargetDesc/X86MCTargetDesc.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCExpr.h"
Modified: llvm/branches/type-system-rewrite/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h (original)
+++ llvm/branches/type-system-rewrite/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h Thu Jul 7 23:45:15 2011
@@ -20,11 +20,10 @@
namespace llvm {
class MCOperand;
-class TargetMachine;
class X86IntelInstPrinter : public MCInstPrinter {
public:
- X86IntelInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI)
+ X86IntelInstPrinter(const MCAsmInfo &MAI)
: MCInstPrinter(MAI) {}
virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
Modified: llvm/branches/type-system-rewrite/lib/Target/X86/MCTargetDesc/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/X86/MCTargetDesc/CMakeLists.txt?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/X86/MCTargetDesc/CMakeLists.txt (original)
+++ llvm/branches/type-system-rewrite/lib/Target/X86/MCTargetDesc/CMakeLists.txt Thu Jul 7 23:45:15 2011
@@ -1,2 +1,2 @@
-add_llvm_library(LLVMX86Desc X86TargetDesc.cpp)
+add_llvm_library(LLVMX86Desc X86MCTargetDesc.cpp)
Removed: llvm/branches/type-system-rewrite/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp?rev=134683&view=auto
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp (removed)
@@ -1,74 +0,0 @@
-//===-- X86TargetDesc.cpp - X86 Target Descriptions -------------*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file provides X86 specific target descriptions.
-//
-//===----------------------------------------------------------------------===//
-
-#include "X86TargetDesc.h"
-#include "llvm/MC/MCInstrInfo.h"
-#include "llvm/MC/MCRegisterInfo.h"
-#include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/Target/TargetRegistry.h"
-
-#define GET_REGINFO_MC_DESC
-#include "X86GenRegisterInfo.inc"
-
-#define GET_INSTRINFO_MC_DESC
-#include "X86GenInstrInfo.inc"
-
-#define GET_SUBTARGETINFO_MC_DESC
-#include "X86GenSubtargetInfo.inc"
-
-using namespace llvm;
-
-MCInstrInfo *createX86MCInstrInfo() {
- MCInstrInfo *X = new MCInstrInfo();
- InitX86MCInstrInfo(X);
- return X;
-}
-
-MCRegisterInfo *createX86MCRegisterInfo() {
- MCRegisterInfo *X = new MCRegisterInfo();
- InitX86MCRegisterInfo(X);
- return X;
-}
-
-MCSubtargetInfo *createX86MCSubtargetInfo() {
- MCSubtargetInfo *X = new MCSubtargetInfo();
- InitX86MCSubtargetInfo(X);
- return X;
-}
-
-// Force static initialization.
-extern "C" void LLVMInitializeX86MCInstrInfo() {
- RegisterMCInstrInfo<MCInstrInfo> X(TheX86_32Target);
- RegisterMCInstrInfo<MCInstrInfo> Y(TheX86_64Target);
-
- TargetRegistry::RegisterMCInstrInfo(TheX86_32Target, createX86MCInstrInfo);
- TargetRegistry::RegisterMCInstrInfo(TheX86_64Target, createX86MCInstrInfo);
-}
-
-extern "C" void LLVMInitializeX86MCRegInfo() {
- RegisterMCRegInfo<MCRegisterInfo> X(TheX86_32Target);
- RegisterMCRegInfo<MCRegisterInfo> Y(TheX86_64Target);
-
- TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo);
- TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo);
-}
-
-extern "C" void LLVMInitializeX86MCSubtargetInfo() {
- RegisterMCSubtargetInfo<MCSubtargetInfo> X(TheX86_32Target);
- RegisterMCSubtargetInfo<MCSubtargetInfo> Y(TheX86_64Target);
-
- TargetRegistry::RegisterMCSubtargetInfo(TheX86_32Target,
- createX86MCSubtargetInfo);
- TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target,
- createX86MCSubtargetInfo);
-}
Removed: llvm/branches/type-system-rewrite/lib/Target/X86/MCTargetDesc/X86TargetDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/X86/MCTargetDesc/X86TargetDesc.h?rev=134683&view=auto
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/X86/MCTargetDesc/X86TargetDesc.h (original)
+++ llvm/branches/type-system-rewrite/lib/Target/X86/MCTargetDesc/X86TargetDesc.h (removed)
@@ -1,34 +0,0 @@
-//===-- X86TargetDesc.h - X86 Target Descriptions ---------------*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file provides X86 specific target descriptions.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef X86TARGETDESC_H
-#define X86TARGETDESC_H
-
-namespace llvm {
-class Target;
-
-extern Target TheX86_32Target, TheX86_64Target;
-} // End llvm namespace
-
-// Defines symbolic names for X86 registers. This defines a mapping from
-// register name to register number.
-//
-#define GET_REGINFO_ENUM
-#include "X86GenRegisterInfo.inc"
-
-// Defines symbolic names for the X86 instructions.
-//
-#define GET_INSTRINFO_ENUM
-#include "X86GenInstrInfo.inc"
-
-#endif
Modified: llvm/branches/type-system-rewrite/lib/Target/X86/X86.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/X86/X86.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/X86/X86.h (original)
+++ llvm/branches/type-system-rewrite/lib/Target/X86/X86.h Thu Jul 7 23:45:15 2011
@@ -15,7 +15,7 @@
#ifndef TARGET_X86_H
#define TARGET_X86_H
-#include "MCTargetDesc/X86TargetDesc.h"
+#include "MCTargetDesc/X86MCTargetDesc.h"
#include "llvm/Support/DataTypes.h"
#include "llvm/Target/TargetMachine.h"
Modified: llvm/branches/type-system-rewrite/lib/Target/X86/X86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/X86/X86.td?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/X86/X86.td (original)
+++ llvm/branches/type-system-rewrite/lib/Target/X86/X86.td Thu Jul 7 23:45:15 2011
@@ -17,6 +17,13 @@
include "llvm/Target/Target.td"
//===----------------------------------------------------------------------===//
+// X86 Subtarget state.
+//
+
+def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
+ "64-bit mode (x86_64)">;
+
+//===----------------------------------------------------------------------===//
// X86 Subtarget features.
//===----------------------------------------------------------------------===//
Modified: llvm/branches/type-system-rewrite/lib/Target/X86/X86AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/X86/X86AsmPrinter.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/X86/X86AsmPrinter.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/X86/X86AsmPrinter.cpp Thu Jul 7 23:45:15 2011
@@ -709,13 +709,12 @@
//===----------------------------------------------------------------------===//
static MCInstPrinter *createX86MCInstPrinter(const Target &T,
- TargetMachine &TM,
unsigned SyntaxVariant,
const MCAsmInfo &MAI) {
if (SyntaxVariant == 0)
- return new X86ATTInstPrinter(TM, MAI);
+ return new X86ATTInstPrinter(MAI);
if (SyntaxVariant == 1)
- return new X86IntelInstPrinter(TM, MAI);
+ return new X86IntelInstPrinter(MAI);
return 0;
}
Modified: llvm/branches/type-system-rewrite/lib/Target/X86/X86FrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/X86/X86FrameLowering.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/X86/X86FrameLowering.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/X86/X86FrameLowering.cpp Thu Jul 7 23:45:15 2011
@@ -23,6 +23,7 @@
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/MC/MCAsmInfo.h"
+#include "llvm/MC/MCSymbol.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Support/CommandLine.h"
@@ -1029,3 +1030,100 @@
FrameIdx = 0;
}
}
+
+uint32_t X86FrameLowering::
+getCompactUnwindEncoding(ArrayRef<MCCFIInstruction> Instrs,
+ int DataAlignmentFactor, bool IsEH) const {
+ uint32_t Encoding = 0;
+ int CFAOffset = 0;
+ const TargetRegisterInfo *TRI = TM.getRegisterInfo();
+ SmallVector<unsigned, 8> SavedRegs;
+ int FramePointerReg = -1;
+
+ for (ArrayRef<MCCFIInstruction>::const_iterator
+ I = Instrs.begin(), E = Instrs.end(); I != E; ++I) {
+ const MCCFIInstruction &Inst = *I;
+ MCSymbol *Label = Inst.getLabel();
+
+ // Ignore invalid labels.
+ if (Label && !Label->isDefined()) continue;
+
+ unsigned Operation = Inst.getOperation();
+ if (Operation != MCCFIInstruction::Move &&
+ Operation != MCCFIInstruction::RelMove)
+ // FIXME: We can't handle this frame just yet.
+ return 0;
+
+ const MachineLocation &Dst = Inst.getDestination();
+ const MachineLocation &Src = Inst.getSource();
+ const bool IsRelative = (Operation == MCCFIInstruction::RelMove);
+
+ if (Dst.isReg() && Dst.getReg() == MachineLocation::VirtualFP) {
+ if (Src.getReg() == MachineLocation::VirtualFP) {
+ // DW_CFA_def_cfa_offset
+ if (IsRelative)
+ CFAOffset += Src.getOffset();
+ else
+ CFAOffset = -Src.getOffset();
+ } // else DW_CFA_def_cfa
+
+ continue;
+ }
+
+ if (Src.isReg() && Src.getReg() == MachineLocation::VirtualFP) {
+ // DW_CFA_def_cfa_register
+ FramePointerReg = Dst.getReg();
+ continue;
+ }
+
+ unsigned Reg = Src.getReg();
+ int Offset = Dst.getOffset();
+ if (IsRelative)
+ Offset -= CFAOffset;
+ Offset /= DataAlignmentFactor;
+
+ if (Offset < 0) {
+ // FIXME: Handle?
+ // DW_CFA_offset_extended_sf
+ return 0;
+ } else if (Reg < 64) {
+ // DW_CFA_offset + Reg
+ SavedRegs.push_back(Reg);
+ } else {
+ // FIXME: Handle?
+ // DW_CFA_offset_extended
+ return 0;
+ }
+ }
+
+ CFAOffset /= 4;
+
+ // Check if the offset is too big.
+ if ((CFAOffset & 0xFF) != CFAOffset)
+ return 0;
+
+ // Bail if there are too many registers to encode.
+ unsigned NumRegsToEncode = SavedRegs.size() - (FramePointerReg != -1 ? 1 : 0);
+ if (NumRegsToEncode > 5) return 0;
+
+ if (TRI->getLLVMRegNum(FramePointerReg, IsEH) != X86::EBP &&
+ TRI->getLLVMRegNum(FramePointerReg, IsEH) != X86::RBP)
+ // FIXME: Handle frameless version!
+ return 0;
+
+ Encoding |= 1 << 24;
+ Encoding |= (CFAOffset & 0xFF) << 16;
+
+ unsigned Idx = 0;
+ for (SmallVectorImpl<unsigned>::iterator
+ I = SavedRegs.begin(), E = SavedRegs.end(); I != E; ++I) {
+ if (*I == unsigned(FramePointerReg)) continue;
+
+ int CURegNum = TRI->getCompactUnwindRegNum(*I, IsEH);
+ if (CURegNum == -1) return 0;
+
+ Encoding |= (CURegNum & 0x7) << (Idx++ * 3);
+ }
+
+ return Encoding;
+}
Modified: llvm/branches/type-system-rewrite/lib/Target/X86/X86FrameLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/X86/X86FrameLowering.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/X86/X86FrameLowering.h (original)
+++ llvm/branches/type-system-rewrite/lib/Target/X86/X86FrameLowering.h Thu Jul 7 23:45:15 2011
@@ -15,6 +15,7 @@
#define X86_FRAMELOWERING_H
#include "X86Subtarget.h"
+#include "llvm/MC/MCDwarf.h"
#include "llvm/Target/TargetFrameLowering.h"
namespace llvm {
@@ -58,6 +59,9 @@
void getInitialFrameState(std::vector<MachineMove> &Moves) const;
int getFrameIndexOffset(const MachineFunction &MF, int FI) const;
+
+ uint32_t getCompactUnwindEncoding(ArrayRef<MCCFIInstruction> Instrs,
+ int DataAlignmentFactor, bool IsEH) const;
};
} // End llvm namespace
Modified: llvm/branches/type-system-rewrite/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/X86/X86ISelLowering.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/X86/X86ISelLowering.cpp Thu Jul 7 23:45:15 2011
@@ -9067,10 +9067,11 @@
SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
DebugLoc dl = Op.getDebugLoc();
- if (!Subtarget->hasSSE2()) {
+ // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
+ // There isn't any reason to disable it if the target processor supports it.
+ if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
SDValue Chain = Op.getOperand(0);
- SDValue Zero = DAG.getConstant(0,
- Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
+ SDValue Zero = DAG.getConstant(0, MVT::i32);
SDValue Ops[] = {
DAG.getRegister(X86::ESP, MVT::i32), // Base
DAG.getTargetConstant(1, MVT::i8), // Scale
@@ -12592,6 +12593,7 @@
case 'y':
case 'x':
case 'Y':
+ case 'l':
return C_RegisterClass;
case 'a':
case 'b':
@@ -12889,19 +12891,19 @@
// in the normal allocation?
case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
if (Subtarget->is64Bit()) {
- if (VT == MVT::i32)
+ if (VT == MVT::i32 || VT == MVT::f32)
return std::make_pair(0U, X86::GR32RegisterClass);
else if (VT == MVT::i16)
return std::make_pair(0U, X86::GR16RegisterClass);
else if (VT == MVT::i8)
return std::make_pair(0U, X86::GR8RegisterClass);
- else if (VT == MVT::i64)
+ else if (VT == MVT::i64 || VT == MVT::f64)
return std::make_pair(0U, X86::GR64RegisterClass);
break;
}
// 32-bit fallthrough
case 'Q': // Q_REGS
- if (VT == MVT::i32)
+ if (VT == MVT::i32 || VT == MVT::f32)
return std::make_pair(0U, X86::GR32_ABCDRegisterClass);
else if (VT == MVT::i16)
return std::make_pair(0U, X86::GR16_ABCDRegisterClass);
Modified: llvm/branches/type-system-rewrite/lib/Target/X86/X86InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/X86/X86InstrFormats.td?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/X86/X86InstrFormats.td (original)
+++ llvm/branches/type-system-rewrite/lib/Target/X86/X86InstrFormats.td Thu Jul 7 23:45:15 2011
@@ -460,6 +460,11 @@
class CLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag>pattern>
: Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
+ OpSize, Requires<[HasCLMUL]>;
+
+class AVXCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
+ list<dag>pattern>
+ : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
OpSize, VEX_4V, Requires<[HasAVX, HasCLMUL]>;
// FMA3 Instruction Templates
Modified: llvm/branches/type-system-rewrite/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/X86/X86InstrInfo.td?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/branches/type-system-rewrite/lib/Target/X86/X86InstrInfo.td Thu Jul 7 23:45:15 2011
@@ -438,8 +438,10 @@
def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
def FPStackf32 : Predicate<"!Subtarget->hasXMM()">;
def FPStackf64 : Predicate<"!Subtarget->hasXMMInt()">;
-def In32BitMode : Predicate<"!Subtarget->is64Bit()">, AssemblerPredicate;
-def In64BitMode : Predicate<"Subtarget->is64Bit()">, AssemblerPredicate;
+def In32BitMode : Predicate<"!Subtarget->is64Bit()">,
+ AssemblerPredicate<"!Mode64Bit">;
+def In64BitMode : Predicate<"Subtarget->is64Bit()">,
+ AssemblerPredicate<"Mode64Bit">;
def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
@@ -669,7 +671,7 @@
}
let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
-def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
+def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
"push{q}\t$imm", []>;
def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
"push{q}\t$imm", []>;
Modified: llvm/branches/type-system-rewrite/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/X86/X86InstrSSE.td?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/branches/type-system-rewrite/lib/Target/X86/X86InstrSSE.td Thu Jul 7 23:45:15 2011
@@ -5195,33 +5195,52 @@
// CLMUL Instructions
//===----------------------------------------------------------------------===//
-// Only the AVX version of CLMUL instructions are described here.
-
// Carry-less Multiplication instructions
-def VPCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
+let Constraints = "$src1 = $dst" in {
+def PCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
+ (ins VR128:$src1, VR128:$src2, i8imm:$src3),
+ "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
+ []>;
+
+def PCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
+ (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
+ "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
+ []>;
+}
+
+// AVX carry-less Multiplication instructions
+def VPCLMULQDQrr : AVXCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2, i8imm:$src3),
"vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
[]>;
-def VPCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
+def VPCLMULQDQrm : AVXCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
(ins VR128:$src1, i128mem:$src2, i8imm:$src3),
"vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
[]>;
-// Assembler Only
-multiclass avx_vpclmul<string asm> {
- def rr : I<0, Pseudo, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
- !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
- []>;
-
- def rm : I<0, Pseudo, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
- !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
- []>;
+
+multiclass pclmul_alias<string asm, int immop> {
+ def : InstAlias<!strconcat("pclmul", asm,
+ "dq {$src, $dst|$dst, $src}"),
+ (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
+
+ def : InstAlias<!strconcat("pclmul", asm,
+ "dq {$src, $dst|$dst, $src}"),
+ (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
+
+ def : InstAlias<!strconcat("vpclmul", asm,
+ "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
+ (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
+
+ def : InstAlias<!strconcat("vpclmul", asm,
+ "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
+ (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
}
-defm VPCLMULHQHQDQ : avx_vpclmul<"vpclmulhqhqdq">;
-defm VPCLMULHQLQDQ : avx_vpclmul<"vpclmulhqlqdq">;
-defm VPCLMULLQHQDQ : avx_vpclmul<"vpclmullqhqdq">;
-defm VPCLMULLQLQDQ : avx_vpclmul<"vpclmullqlqdq">;
+defm : pclmul_alias<"hqhq", 0x11>;
+defm : pclmul_alias<"hqlq", 0x01>;
+defm : pclmul_alias<"lqhq", 0x10>;
+defm : pclmul_alias<"lqlq", 0x00>;
//===----------------------------------------------------------------------===//
// AVX Instructions
Modified: llvm/branches/type-system-rewrite/lib/Target/X86/X86MCAsmInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/X86/X86MCAsmInfo.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/X86/X86MCAsmInfo.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/X86/X86MCAsmInfo.cpp Thu Jul 7 23:45:15 2011
@@ -45,13 +45,14 @@
"{flags}", "",
"{dirflag}", "",
"{fpsr}", "",
+ "{fpcr}", "",
"{cc}", "cc",
0,0};
X86MCAsmInfoDarwin::X86MCAsmInfoDarwin(const Triple &Triple) {
AsmTransCBE = x86_asm_table;
AssemblerDialect = AsmWriterFlavor;
-
+
bool is64Bit = Triple.getArch() == Triple::x86_64;
TextAlignFillValue = 0x90;
Modified: llvm/branches/type-system-rewrite/lib/Target/X86/X86RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/X86/X86RegisterInfo.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/X86/X86RegisterInfo.cpp Thu Jul 7 23:45:15 2011
@@ -107,8 +107,8 @@
/// getCompactUnwindRegNum - This function maps the register to the number for
/// compact unwind encoding. Return -1 if the register isn't valid.
-int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum) const {
- switch (RegNum) {
+int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum, bool isEH) const {
+ switch (getLLVMRegNum(RegNum, isEH)) {
case X86::EBX: case X86::RBX: return 1;
case X86::ECX: case X86::R12: return 2;
case X86::EDX: case X86::R13: return 3;
Modified: llvm/branches/type-system-rewrite/lib/Target/X86/X86RegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/X86/X86RegisterInfo.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/X86/X86RegisterInfo.h (original)
+++ llvm/branches/type-system-rewrite/lib/Target/X86/X86RegisterInfo.h Thu Jul 7 23:45:15 2011
@@ -83,7 +83,7 @@
/// getCompactUnwindRegNum - This function maps the register to the number for
/// compact unwind encoding. Return -1 if the register isn't valid.
- int getCompactUnwindRegNum(unsigned RegNum) const;
+ int getCompactUnwindRegNum(unsigned RegNum, bool isEH) const;
/// Code Generation virtual methods...
///
Modified: llvm/branches/type-system-rewrite/lib/Target/X86/X86Subtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/X86/X86Subtarget.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/X86/X86Subtarget.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/X86/X86Subtarget.cpp Thu Jul 7 23:45:15 2011
@@ -21,9 +21,10 @@
#include "llvm/Target/TargetMachine.h"
#include "llvm/ADT/SmallVector.h"
-#define GET_SUBTARGETINFO_CTOR
+#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
#define GET_SUBTARGETINFO_TARGET_DESC
+#define GET_SUBTARGETINFO_CTOR
#include "X86GenSubtargetInfo.inc"
using namespace llvm;
@@ -158,7 +159,7 @@
/// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
/// to immediate address.
bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const {
- if (Is64Bit)
+ if (In64BitMode)
return false;
return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
}
@@ -174,73 +175,6 @@
return 200;
}
-/// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
-/// specified arguments. If we can't run cpuid on the host, return true.
-static bool GetCpuIDAndInfo(unsigned value, unsigned *rEAX,
- unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
-#if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
- #if defined(__GNUC__)
- // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
- asm ("movq\t%%rbx, %%rsi\n\t"
- "cpuid\n\t"
- "xchgq\t%%rbx, %%rsi\n\t"
- : "=a" (*rEAX),
- "=S" (*rEBX),
- "=c" (*rECX),
- "=d" (*rEDX)
- : "a" (value));
- return false;
- #elif defined(_MSC_VER)
- int registers[4];
- __cpuid(registers, value);
- *rEAX = registers[0];
- *rEBX = registers[1];
- *rECX = registers[2];
- *rEDX = registers[3];
- return false;
- #endif
-#elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
- #if defined(__GNUC__)
- asm ("movl\t%%ebx, %%esi\n\t"
- "cpuid\n\t"
- "xchgl\t%%ebx, %%esi\n\t"
- : "=a" (*rEAX),
- "=S" (*rEBX),
- "=c" (*rECX),
- "=d" (*rEDX)
- : "a" (value));
- return false;
- #elif defined(_MSC_VER)
- __asm {
- mov eax,value
- cpuid
- mov esi,rEAX
- mov dword ptr [esi],eax
- mov esi,rEBX
- mov dword ptr [esi],ebx
- mov esi,rECX
- mov dword ptr [esi],ecx
- mov esi,rEDX
- mov dword ptr [esi],edx
- }
- return false;
- #endif
-#endif
- return true;
-}
-
-static void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model) {
- Family = (EAX >> 8) & 0xf; // Bits 8 - 11
- Model = (EAX >> 4) & 0xf; // Bits 4 - 7
- if (Family == 6 || Family == 0xf) {
- if (Family == 0xf)
- // Examine extended family ID if family ID is F.
- Family += (EAX >> 20) & 0xff; // Bits 20 - 27
- // Examine extended model ID if family ID is 6 or F.
- Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
- }
-}
-
void X86Subtarget::AutoDetectSubtargetFeatures() {
unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
union {
@@ -248,10 +182,10 @@
char c[12];
} text;
- if (GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1))
+ if (X86_MC::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1))
return;
- GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
+ X86_MC::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
if ((EDX >> 15) & 1) HasCMov = true;
if ((EDX >> 23) & 1) X86SSELevel = MMX;
@@ -276,13 +210,13 @@
// Determine if bit test memory instructions are slow.
unsigned Family = 0;
unsigned Model = 0;
- DetectFamilyModel(EAX, Family, Model);
+ X86_MC::DetectFamilyModel(EAX, Family, Model);
IsBTMemSlow = IsAMD || (Family == 6 && Model >= 13);
// If it's Nehalem, unaligned memory access is fast.
if (Family == 15 && Model == 26)
IsUAMemFast = true;
- GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
+ X86_MC::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
HasX86_64 = (EDX >> 29) & 0x1;
HasSSE4A = IsAMD && ((ECX >> 6) & 0x1);
HasFMA4 = IsAMD && ((ECX >> 16) & 0x1);
@@ -291,8 +225,8 @@
X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
const std::string &FS,
- bool is64Bit, unsigned StackAlignOverride)
- : X86GenSubtargetInfo()
+ unsigned StackAlignOverride)
+ : X86GenSubtargetInfo(TT, CPU, FS)
, PICStyle(PICStyles::None)
, X86SSELevel(NoMMXSSE)
, X863DNowLevel(NoThreeDNow)
@@ -312,15 +246,26 @@
// FIXME: this is a known good value for Yonah. How about others?
, MaxInlineSizeThreshold(128)
, TargetTriple(TT)
- , Is64Bit(is64Bit) {
+ , In64BitMode(false) {
+ // Insert the architecture feature derived from the target triple into the
+ // feature string. This is important for setting features that are implied
+ // based on the architecture version.
+ std::string ArchFS = X86_MC::ParseX86Triple(TT);
+ if (!FS.empty()) {
+ if (!ArchFS.empty())
+ ArchFS = ArchFS + "," + FS;
+ else
+ ArchFS = FS;
+ }
+
+ std::string CPUName = CPU;
+ if (CPUName.empty())
+ CPUName = sys::getHostCPUName();
// Determine default and user specified characteristics
- if (!CPU.empty() || !FS.empty()) {
+ if (!CPUName.empty() || !ArchFS.empty()) {
// If feature string is not empty, parse features string.
- std::string CPUName = CPU;
- if (CPUName.empty())
- CPUName = sys::getHostCPUName();
- ParseSubtargetFeatures(FS, CPUName);
+ ParseSubtargetFeatures(CPUName, ArchFS);
// All X86-64 CPUs also have SSE2, however user might request no SSE via
// -mattr, so don't force SSELevel here.
if (HasAVX)
@@ -328,14 +273,19 @@
} else {
// Otherwise, use CPUID to auto-detect feature set.
AutoDetectSubtargetFeatures();
+
+ // If CPU is 64-bit capable, default to 64-bit mode if not specified.
+ In64BitMode = HasX86_64;
+
// Make sure SSE2 is enabled; it is available on all X86-64 CPUs.
- if (Is64Bit && !HasAVX && X86SSELevel < SSE2)
+ if (In64BitMode && !HasAVX && X86SSELevel < SSE2)
X86SSELevel = SSE2;
}
// If requesting codegen for X86-64, make sure that 64-bit features
// are enabled.
- if (Is64Bit) {
+ // FIXME: Remove this feature since it's not actually being used.
+ if (In64BitMode) {
HasX86_64 = true;
// All 64-bit cpus have cmov support.
@@ -345,7 +295,7 @@
DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
<< ", 3DNowLevel " << X863DNowLevel
<< ", 64bit " << HasX86_64 << "\n");
- assert((!Is64Bit || HasX86_64) &&
+ assert((!In64BitMode || HasX86_64) &&
"64-bit code requested on a subtarget that doesn't support it!");
// Stack alignment is 16 bytes on Darwin, FreeBSD, Linux and Solaris (both
@@ -353,6 +303,6 @@
if (StackAlignOverride)
stackAlignment = StackAlignOverride;
else if (isTargetDarwin() || isTargetFreeBSD() || isTargetLinux() ||
- isTargetSolaris() || Is64Bit)
+ isTargetSolaris() || In64BitMode)
stackAlignment = 16;
}
Modified: llvm/branches/type-system-rewrite/lib/Target/X86/X86Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/X86/X86Subtarget.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/X86/X86Subtarget.h (original)
+++ llvm/branches/type-system-rewrite/lib/Target/X86/X86Subtarget.h Thu Jul 7 23:45:15 2011
@@ -24,6 +24,7 @@
namespace llvm {
class GlobalValue;
+class StringRef;
class TargetMachine;
/// PICStyles - The X86 backend supports a number of different styles of PIC.
@@ -111,9 +112,8 @@
Triple TargetTriple;
private:
- /// Is64Bit - True if the processor supports 64-bit instructions and
- /// pointer size is 64 bit.
- bool Is64Bit;
+ /// In64BitMode - True if compiling for 64-bit, false for 32-bit.
+ bool In64BitMode;
public:
@@ -121,7 +121,7 @@
/// of the specified triple.
///
X86Subtarget(const std::string &TT, const std::string &CPU,
- const std::string &FS, bool is64Bit,
+ const std::string &FS,
unsigned StackAlignOverride);
/// getStackAlignment - Returns the minimum alignment known to hold of the
@@ -135,13 +135,13 @@
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
- void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
+ void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
/// AutoDetectSubtargetFeatures - Auto-detect CPU features using CPUID
/// instruction.
void AutoDetectSubtargetFeatures();
- bool is64Bit() const { return Is64Bit; }
+ bool is64Bit() const { return In64BitMode; }
PICStyles::Style getPICStyle() const { return PICStyle; }
void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
@@ -199,7 +199,7 @@
}
bool isTargetWin64() const {
- return Is64Bit && (isTargetMingw() || isTargetWindows());
+ return In64BitMode && (isTargetMingw() || isTargetWindows());
}
bool isTargetEnvMacho() const {
@@ -207,7 +207,7 @@
}
bool isTargetWin32() const {
- return !Is64Bit && (isTargetMingw() || isTargetWindows());
+ return !In64BitMode && (isTargetMingw() || isTargetWindows());
}
bool isPICStyleSet() const { return PICStyle != PICStyles::None; }
Modified: llvm/branches/type-system-rewrite/lib/Target/X86/X86TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/X86/X86TargetMachine.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/X86/X86TargetMachine.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/X86/X86TargetMachine.cpp Thu Jul 7 23:45:15 2011
@@ -119,8 +119,8 @@
X86TargetMachine::X86TargetMachine(const Target &T, const std::string &TT,
const std::string &CPU,
const std::string &FS, bool is64Bit)
- : LLVMTargetMachine(T, TT),
- Subtarget(TT, CPU, FS, is64Bit, StackAlignmentOverride),
+ : LLVMTargetMachine(T, TT, CPU, FS),
+ Subtarget(TT, CPU, FS, StackAlignmentOverride),
FrameLowering(*this, Subtarget),
ELFWriterInfo(is64Bit, true) {
DefRelocModel = getRelocationModel();
Modified: llvm/branches/type-system-rewrite/lib/Target/XCore/XCoreSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/XCore/XCoreSubtarget.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/XCore/XCoreSubtarget.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/XCore/XCoreSubtarget.cpp Thu Jul 7 23:45:15 2011
@@ -14,15 +14,16 @@
#include "XCoreSubtarget.h"
#include "XCore.h"
-#define GET_SUBTARGETINFO_CTOR
+#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
#define GET_SUBTARGETINFO_TARGET_DESC
+#define GET_SUBTARGETINFO_CTOR
#include "XCoreGenSubtargetInfo.inc"
using namespace llvm;
XCoreSubtarget::XCoreSubtarget(const std::string &TT,
const std::string &CPU, const std::string &FS)
- : XCoreGenSubtargetInfo()
+ : XCoreGenSubtargetInfo(TT, CPU, FS)
{
}
Modified: llvm/branches/type-system-rewrite/lib/Target/XCore/XCoreSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/XCore/XCoreSubtarget.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/XCore/XCoreSubtarget.h (original)
+++ llvm/branches/type-system-rewrite/lib/Target/XCore/XCoreSubtarget.h Thu Jul 7 23:45:15 2011
@@ -22,6 +22,7 @@
#include "XCoreGenSubtargetInfo.inc"
namespace llvm {
+class StringRef;
class XCoreSubtarget : public XCoreGenSubtargetInfo {
@@ -34,7 +35,7 @@
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
- void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
+ void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
};
} // End llvm namespace
Modified: llvm/branches/type-system-rewrite/lib/Target/XCore/XCoreTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Target/XCore/XCoreTargetMachine.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Target/XCore/XCoreTargetMachine.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Target/XCore/XCoreTargetMachine.cpp Thu Jul 7 23:45:15 2011
@@ -23,7 +23,7 @@
XCoreTargetMachine::XCoreTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU,
const std::string &FS)
- : LLVMTargetMachine(T, TT),
+ : LLVMTargetMachine(T, TT, CPU, FS),
Subtarget(TT, CPU, FS),
DataLayout("e-p:32:32:32-a0:0:32-f32:32:32-f64:32:32-i1:8:32-i8:8:32-"
"i16:16:32-i32:32:32-i64:32:32-n32"),
Modified: llvm/branches/type-system-rewrite/lib/Transforms/InstCombine/InstCombineCompares.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Transforms/InstCombine/InstCombineCompares.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Transforms/InstCombine/InstCombineCompares.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Transforms/InstCombine/InstCombineCompares.cpp Thu Jul 7 23:45:15 2011
@@ -1454,7 +1454,11 @@
return new ICmpInst(isICMP_NE ? ICmpInst::ICMP_EQ :
ICmpInst::ICMP_NE, LHSI,
Constant::getNullValue(RHS->getType()));
-
+
+ // Don't perform the following transforms if the AND has multiple uses
+ if (!BO->hasOneUse())
+ break;
+
// Replace (and X, (1 << size(X)-1) != 0) with x s< 0
if (BOC->getValue().isSignBit()) {
Value *X = BO->getOperand(0);
Modified: llvm/branches/type-system-rewrite/lib/Transforms/Scalar/GVN.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Transforms/Scalar/GVN.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Transforms/Scalar/GVN.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Transforms/Scalar/GVN.cpp Thu Jul 7 23:45:15 2011
@@ -91,6 +91,7 @@
uint32_t nextValueNumber;
Expression create_expression(Instruction* I);
+ Expression create_extractvalue_expression(ExtractValueInst* EI);
uint32_t lookup_or_add_call(CallInst* C);
public:
ValueTable() : nextValueNumber(1) { }
@@ -141,7 +142,6 @@
// ValueTable Internal Functions
//===----------------------------------------------------------------------===//
-
Expression ValueTable::create_expression(Instruction *I) {
Expression e;
e.type = I->getType();
@@ -150,12 +150,8 @@
OI != OE; ++OI)
e.varargs.push_back(lookup_or_add(*OI));
- if (CmpInst *C = dyn_cast<CmpInst>(I))
+ if (CmpInst *C = dyn_cast<CmpInst>(I)) {
e.opcode = (C->getOpcode() << 8) | C->getPredicate();
- else if (ExtractValueInst *E = dyn_cast<ExtractValueInst>(I)) {
- for (ExtractValueInst::idx_iterator II = E->idx_begin(), IE = E->idx_end();
- II != IE; ++II)
- e.varargs.push_back(*II);
} else if (InsertValueInst *E = dyn_cast<InsertValueInst>(I)) {
for (InsertValueInst::idx_iterator II = E->idx_begin(), IE = E->idx_end();
II != IE; ++II)
@@ -165,6 +161,55 @@
return e;
}
+Expression ValueTable::create_extractvalue_expression(ExtractValueInst *EI) {
+ assert(EI != 0 && "Not an ExtractValueInst?");
+ Expression e;
+ e.type = EI->getType();
+ e.opcode = 0;
+
+ IntrinsicInst *I = dyn_cast<IntrinsicInst>(EI->getAggregateOperand());
+ if (I != 0 && EI->getNumIndices() == 1 && *EI->idx_begin() == 0 ) {
+ // EI might be an extract from one of our recognised intrinsics. If it
+ // is we'll synthesize a semantically equivalent expression instead on
+ // an extract value expression.
+ switch (I->getIntrinsicID()) {
+ case Intrinsic::uadd_with_overflow:
+ e.opcode = Instruction::Add;
+ break;
+ case Intrinsic::usub_with_overflow:
+ e.opcode = Instruction::Sub;
+ break;
+ case Intrinsic::umul_with_overflow:
+ e.opcode = Instruction::Mul;
+ break;
+ default:
+ break;
+ }
+
+ if (e.opcode != 0) {
+ // Intrinsic recognized. Grab its args to finish building the expression.
+ assert(I->getNumArgOperands() == 2 &&
+ "Expect two args for recognised intrinsics.");
+ e.varargs.push_back(lookup_or_add(I->getArgOperand(0)));
+ e.varargs.push_back(lookup_or_add(I->getArgOperand(1)));
+ return e;
+ }
+ }
+
+ // Not a recognised intrinsic. Fall back to producing an extract value
+ // expression.
+ e.opcode = EI->getOpcode();
+ for (Instruction::op_iterator OI = EI->op_begin(), OE = EI->op_end();
+ OI != OE; ++OI)
+ e.varargs.push_back(lookup_or_add(*OI));
+
+ for (ExtractValueInst::idx_iterator II = EI->idx_begin(), IE = EI->idx_end();
+ II != IE; ++II)
+ e.varargs.push_back(*II);
+
+ return e;
+}
+
//===----------------------------------------------------------------------===//
// ValueTable External Functions
//===----------------------------------------------------------------------===//
@@ -336,11 +381,13 @@
case Instruction::ExtractElement:
case Instruction::InsertElement:
case Instruction::ShuffleVector:
- case Instruction::ExtractValue:
case Instruction::InsertValue:
case Instruction::GetElementPtr:
exp = create_expression(I);
break;
+ case Instruction::ExtractValue:
+ exp = create_extractvalue_expression(cast<ExtractValueInst>(I));
+ break;
default:
valueNumbering[V] = nextValueNumber;
return nextValueNumber++;
Modified: llvm/branches/type-system-rewrite/lib/Transforms/Scalar/IndVarSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Transforms/Scalar/IndVarSimplify.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Transforms/Scalar/IndVarSimplify.cpp Thu Jul 7 23:45:15 2011
@@ -58,6 +58,7 @@
#include "llvm/Transforms/Utils/Local.h"
#include "llvm/Transforms/Utils/BasicBlockUtils.h"
#include "llvm/Target/TargetData.h"
+#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h"
@@ -72,6 +73,7 @@
STATISTIC(NumElimExt , "Number of IV sign/zero extends eliminated");
STATISTIC(NumElimRem , "Number of IV remainder operations eliminated");
STATISTIC(NumElimCmp , "Number of IV comparisons eliminated");
+STATISTIC(NumElimIV , "Number of congruent IVs eliminated");
static cl::opt<bool> DisableIVRewrite(
"disable-iv-rewrite", cl::Hidden,
@@ -79,12 +81,15 @@
namespace {
class IndVarSimplify : public LoopPass {
+ typedef DenseMap< const SCEV *, AssertingVH<PHINode> > ExprToIVMapTy;
+
IVUsers *IU;
LoopInfo *LI;
ScalarEvolution *SE;
DominatorTree *DT;
TargetData *TD;
+ ExprToIVMapTy ExprToIVMap;
SmallVector<WeakVH, 16> DeadInsts;
bool Changed;
public:
@@ -114,6 +119,11 @@
}
private:
+ virtual void releaseMemory() {
+ ExprToIVMap.clear();
+ DeadInsts.clear();
+ }
+
bool isValidRewrite(Value *FromVal, Value *ToVal);
void SimplifyIVUsers(SCEVExpander &Rewriter);
@@ -133,6 +143,8 @@
void RewriteLoopExitValues(Loop *L, SCEVExpander &Rewriter);
+ void SimplifyCongruentIVs(Loop *L);
+
void RewriteIVExpressions(Loop *L, SCEVExpander &Rewriter);
void SinkUnusedInvariants(Loop *L);
@@ -339,7 +351,7 @@
<< " RHS:\t" << *RHS << "\n");
ICmpInst *Cond = new ICmpInst(BI, Opcode, CmpIndVar, ExitCnt, "exitcond");
-
+ Cond->setDebugLoc(BI->getDebugLoc());
Value *OrigCond = BI->getCondition();
// It's tempting to use replaceAllUsesWith here to fully replace the old
// comparison, but that's not immediately safe, since users of the old
@@ -608,6 +620,8 @@
Instruction *NarrowDef,
Instruction *WideDef);
+ const SCEVAddRecExpr *GetWideRecurrence(Instruction *NarrowUse);
+
Instruction *WidenIVUse(Use &NarrowDefUse, Instruction *NarrowDef,
Instruction *WideDef);
@@ -704,6 +718,33 @@
return true;
}
+// GetWideRecurrence - Is this instruction potentially interesting from IVUsers'
+// perspective after widening it's type? In other words, can the extend be
+// safely hoisted out of the loop with SCEV reducing the value to a recurrence
+// on the same loop. If so, return the sign or zero extended
+// recurrence. Otherwise return NULL.
+const SCEVAddRecExpr *WidenIV::GetWideRecurrence(Instruction *NarrowUse) {
+ if (!SE->isSCEVable(NarrowUse->getType()))
+ return 0;
+
+ const SCEV *NarrowExpr = SE->getSCEV(NarrowUse);
+ if (SE->getTypeSizeInBits(NarrowExpr->getType())
+ >= SE->getTypeSizeInBits(WideType)) {
+ // NarrowUse implicitly widens its operand. e.g. a gep with a narrow
+ // index. So don't follow this use.
+ return 0;
+ }
+
+ const SCEV *WideExpr = IsSigned ?
+ SE->getSignExtendExpr(NarrowExpr, WideType) :
+ SE->getZeroExtendExpr(NarrowExpr, WideType);
+ const SCEVAddRecExpr *AddRec = dyn_cast<SCEVAddRecExpr>(WideExpr);
+ if (!AddRec || AddRec->getLoop() != L)
+ return 0;
+
+ return AddRec;
+}
+
/// WidenIVUse - Determine whether an individual user of the narrow IV can be
/// widened. If so, return the wide clone of the user.
Instruction *WidenIV::WidenIVUse(Use &NarrowDefUse, Instruction *NarrowDef,
@@ -753,24 +794,7 @@
}
// Does this user itself evaluate to a recurrence after widening?
- const SCEVAddRecExpr *WideAddRec = 0;
- if (SE->isSCEVable(NarrowUse->getType())) {
- const SCEV *NarrowExpr = SE->getSCEV(NarrowUse);
- if (SE->getTypeSizeInBits(NarrowExpr->getType())
- >= SE->getTypeSizeInBits(WideType)) {
- // NarrowUse implicitly widens its operand. e.g. a gep with a narrow
- // index. We have already extended the operand, so we're done.
- return 0;
- }
- const SCEV *WideExpr = IsSigned ?
- SE->getSignExtendExpr(NarrowExpr, WideType) :
- SE->getZeroExtendExpr(NarrowExpr, WideType);
-
- // Only widen past values that evaluate to a recurrence in the same loop.
- const SCEVAddRecExpr *AddRec = dyn_cast<SCEVAddRecExpr>(WideExpr);
- if (AddRec && AddRec->getLoop() == L)
- WideAddRec = AddRec;
- }
+ const SCEVAddRecExpr *WideAddRec = GetWideRecurrence(NarrowUse);
if (!WideAddRec) {
// This user does not evaluate to a recurence after widening, so don't
// follow it. Instead insert a Trunc to kill off the original use,
@@ -1117,7 +1141,7 @@
// Instructions processed by SimplifyIVUsers for CurrIV.
SmallPtrSet<Instruction*,16> Simplified;
- // Use-def pairs if IVUsers waiting to be processed for CurrIV.
+ // Use-def pairs if IV users waiting to be processed for CurrIV.
SmallVector<std::pair<Instruction*, Instruction*>, 8> SimpleIVUsers;
// Push users of the current LoopPhi. In rare cases, pushIVUsers may be
@@ -1163,6 +1187,45 @@
}
}
+/// SimplifyCongruentIVs - Check for congruent phis in this loop header and
+/// populate ExprToIVMap for use later.
+///
+void IndVarSimplify::SimplifyCongruentIVs(Loop *L) {
+ for (BasicBlock::iterator I = L->getHeader()->begin(); isa<PHINode>(I); ++I) {
+ PHINode *Phi = cast<PHINode>(I);
+ const SCEV *S = SE->getSCEV(Phi);
+ ExprToIVMapTy::const_iterator Pos;
+ bool Inserted;
+ tie(Pos, Inserted) = ExprToIVMap.insert(std::make_pair(S, Phi));
+ if (Inserted)
+ continue;
+ PHINode *OrigPhi = Pos->second;
+ // Replacing the congruent phi is sufficient because acyclic redundancy
+ // elimination, CSE/GVN, should handle the rest. However, once SCEV proves
+ // that a phi is congruent, it's almost certain to be the head of an IV
+ // user cycle that is isomorphic with the original phi. So it's worth
+ // eagerly cleaning up the common case of a single IV increment.
+ if (BasicBlock *LatchBlock = L->getLoopLatch()) {
+ Instruction *OrigInc =
+ cast<Instruction>(OrigPhi->getIncomingValueForBlock(LatchBlock));
+ Instruction *IsomorphicInc =
+ cast<Instruction>(Phi->getIncomingValueForBlock(LatchBlock));
+ if (OrigInc != IsomorphicInc &&
+ SE->getSCEV(OrigInc) == SE->getSCEV(IsomorphicInc) &&
+ HoistStep(OrigInc, IsomorphicInc, DT)) {
+ DEBUG(dbgs() << "INDVARS: Eliminated congruent iv.inc: "
+ << *IsomorphicInc << '\n');
+ IsomorphicInc->replaceAllUsesWith(OrigInc);
+ DeadInsts.push_back(IsomorphicInc);
+ }
+ }
+ DEBUG(dbgs() << "INDVARS: Eliminated congruent iv: " << *Phi << '\n');
+ ++NumElimIV;
+ Phi->replaceAllUsesWith(OrigPhi);
+ DeadInsts.push_back(Phi);
+ }
+}
+
bool IndVarSimplify::runOnLoop(Loop *L, LPPassManager &LPM) {
// If LoopSimplify form is not available, stay out of trouble. Some notes:
// - LSR currently only supports LoopSimplify-form loops. Indvars'
@@ -1182,6 +1245,7 @@
DT = &getAnalysis<DominatorTree>();
TD = getAnalysisIfAvailable<TargetData>();
+ ExprToIVMap.clear();
DeadInsts.clear();
Changed = false;
@@ -1218,6 +1282,11 @@
if (!DisableIVRewrite)
SimplifyIVUsers(Rewriter);
+ // Eliminate redundant IV cycles and populate ExprToIVMap.
+ // TODO: use ExprToIVMap to allow LFTR without canonical IVs
+ if (DisableIVRewrite)
+ SimplifyCongruentIVs(L);
+
// Compute the type of the largest recurrence expression, and decide whether
// a canonical induction variable should be inserted.
const Type *LargestType = 0;
@@ -1306,6 +1375,7 @@
// can be deleted in the loop below, causing the AssertingVH in the cache to
// trigger.
Rewriter.clear();
+ ExprToIVMap.clear();
// Now that we're done iterating through lists, clean up any instructions
// which are now dead.
Modified: llvm/branches/type-system-rewrite/lib/Transforms/Scalar/LICM.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Transforms/Scalar/LICM.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Transforms/Scalar/LICM.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Transforms/Scalar/LICM.cpp Thu Jul 7 23:45:15 2011
@@ -178,7 +178,7 @@
Pass *llvm::createLICMPass() { return new LICM(); }
/// Hoist expressions out of the specified loop. Note, alias info for inner
-/// loop is not preserved so it is not a good idea to run LICM multiple
+/// loop is not preserved so it is not a good idea to run LICM multiple
/// times on one loop.
///
bool LICM::runOnLoop(Loop *L, LPPassManager &LPM) {
@@ -199,13 +199,13 @@
// What if InnerLoop was modified by other passes ?
CurAST->add(*InnerAST);
-
+
// Once we've incorporated the inner loop's AST into ours, we don't need the
// subloop's anymore.
delete InnerAST;
LoopToAliasSetMap.erase(InnerL);
}
-
+
CurLoop = L;
// Get the preheader block to move instructions into...
@@ -245,7 +245,7 @@
I != E; ++I)
PromoteAliasSet(*I);
}
-
+
// Clear out loops state information for the next iteration
CurLoop = 0;
Preheader = 0;
@@ -283,7 +283,7 @@
for (BasicBlock::iterator II = BB->end(); II != BB->begin(); ) {
Instruction &I = *--II;
-
+
// If the instruction is dead, we would try to sink it because it isn't used
// in the loop, instead, just delete it.
if (isInstructionTriviallyDead(&I)) {
@@ -336,7 +336,7 @@
I.eraseFromParent();
continue;
}
-
+
// Try hoisting the instruction out to the preheader. We can only do this
// if all of the operands of the instruction are loop invariant and if it
// is safe to hoist the instruction.
@@ -364,7 +364,7 @@
// in the same alias set as something that ends up being modified.
if (AA->pointsToConstantMemory(LI->getOperand(0)))
return true;
-
+
// Don't hoist loads which have may-aliased stores in loop.
uint64_t Size = 0;
if (LI->getType()->isSized())
@@ -470,7 +470,7 @@
}
return;
}
-
+
if (ExitBlocks.empty()) {
// The instruction is actually dead if there ARE NO exit blocks.
CurAST->deleteValue(&I);
@@ -482,30 +482,30 @@
I.eraseFromParent();
return;
}
-
+
// Otherwise, if we have multiple exits, use the SSAUpdater to do all of the
// hard work of inserting PHI nodes as necessary.
SmallVector<PHINode*, 8> NewPHIs;
SSAUpdater SSA(&NewPHIs);
-
+
if (!I.use_empty())
SSA.Initialize(I.getType(), I.getName());
-
+
// Insert a copy of the instruction in each exit block of the loop that is
// dominated by the instruction. Each exit block is known to only be in the
// ExitBlocks list once.
BasicBlock *InstOrigBB = I.getParent();
unsigned NumInserted = 0;
-
+
for (unsigned i = 0, e = ExitBlocks.size(); i != e; ++i) {
BasicBlock *ExitBlock = ExitBlocks[i];
-
+
if (!DT->dominates(InstOrigBB, ExitBlock))
continue;
-
+
// Insert the code after the last PHI node.
BasicBlock::iterator InsertPt = ExitBlock->getFirstNonPHI();
-
+
// If this is the first exit block processed, just move the original
// instruction, otherwise clone the original instruction and insert
// the copy.
@@ -519,12 +519,12 @@
New->setName(I.getName()+".le");
ExitBlock->getInstList().insert(InsertPt, New);
}
-
+
// Now that we have inserted the instruction, inform SSAUpdater.
if (!I.use_empty())
SSA.AddAvailableValue(ExitBlock, New);
}
-
+
// If the instruction doesn't dominate any exit blocks, it must be dead.
if (NumInserted == 0) {
CurAST->deleteValue(&I);
@@ -533,7 +533,7 @@
I.eraseFromParent();
return;
}
-
+
// Next, rewrite uses of the instruction, inserting PHI nodes as needed.
for (Value::use_iterator UI = I.use_begin(), UE = I.use_end(); UI != UE; ) {
// Grab the use before incrementing the iterator.
@@ -542,12 +542,12 @@
++UI;
SSA.RewriteUseAfterInsertions(U);
}
-
+
// Update CurAST for NewPHIs if I had pointer type.
if (I.getType()->isPointerTy())
for (unsigned i = 0, e = NewPHIs.size(); i != e; ++i)
CurAST->copyValue(&I, NewPHIs[i]);
-
+
// Finally, remove the instruction from CurAST. It is no longer in the loop.
CurAST->deleteValue(&I);
}
@@ -606,15 +606,17 @@
SmallVectorImpl<BasicBlock*> &LoopExitBlocks;
AliasSetTracker &AST;
DebugLoc DL;
+ int Alignment;
public:
LoopPromoter(Value *SP,
const SmallVectorImpl<Instruction*> &Insts, SSAUpdater &S,
SmallPtrSet<Value*, 4> &PMA,
SmallVectorImpl<BasicBlock*> &LEB, AliasSetTracker &ast,
- DebugLoc dl)
- : LoadAndStorePromoter(Insts, S, 0, 0), SomePtr(SP),
- PointerMustAliases(PMA), LoopExitBlocks(LEB), AST(ast), DL(dl) {}
-
+ DebugLoc dl, int alignment)
+ : LoadAndStorePromoter(Insts, S), SomePtr(SP),
+ PointerMustAliases(PMA), LoopExitBlocks(LEB), AST(ast), DL(dl),
+ Alignment(alignment) {}
+
virtual bool isInstInList(Instruction *I,
const SmallVectorImpl<Instruction*> &) const {
Value *Ptr;
@@ -624,7 +626,7 @@
Ptr = cast<StoreInst>(I)->getPointerOperand();
return PointerMustAliases.count(Ptr);
}
-
+
virtual void doExtraRewritesBeforeFinalDeletion() const {
// Insert stores after in the loop exit blocks. Each exit block gets a
// store of the live-out values that feed them. Since we've already told
@@ -635,6 +637,7 @@
Value *LiveInValue = SSA.GetValueInMiddleOfBlock(ExitBlock);
Instruction *InsertPos = ExitBlock->getFirstNonPHI();
StoreInst *NewSI = new StoreInst(LiveInValue, SomePtr, InsertPos);
+ NewSI->setAlignment(Alignment);
NewSI->setDebugLoc(DL);
}
}
@@ -661,7 +664,7 @@
if (AS.isForwardingAliasSet() || !AS.isMod() || !AS.isMustAlias() ||
AS.isVolatile() || !CurLoop->isLoopInvariant(AS.begin()->getValue()))
return;
-
+
assert(!AS.empty() &&
"Must alias set should have at least one pointer element in it!");
Value *SomePtr = AS.begin()->getValue();
@@ -676,60 +679,78 @@
// tmp = *P; for () { if (c) tmp +=1; } *P = tmp;
//
// is not safe, because *P may only be valid to access if 'c' is true.
- //
+ //
// It is safe to promote P if all uses are direct load/stores and if at
// least one is guaranteed to be executed.
bool GuaranteedToExecute = false;
-
+
SmallVector<Instruction*, 64> LoopUses;
SmallPtrSet<Value*, 4> PointerMustAliases;
+ // We start with an alignment of one and try to find instructions that allow
+ // us to prove better alignment.
+ unsigned Alignment = 1;
+
// Check that all of the pointers in the alias set have the same type. We
// cannot (yet) promote a memory location that is loaded and stored in
// different sizes.
for (AliasSet::iterator ASI = AS.begin(), E = AS.end(); ASI != E; ++ASI) {
Value *ASIV = ASI->getValue();
PointerMustAliases.insert(ASIV);
-
+
// Check that all of the pointers in the alias set have the same type. We
// cannot (yet) promote a memory location that is loaded and stored in
// different sizes.
if (SomePtr->getType() != ASIV->getType())
return;
-
+
for (Value::use_iterator UI = ASIV->use_begin(), UE = ASIV->use_end();
UI != UE; ++UI) {
// Ignore instructions that are outside the loop.
Instruction *Use = dyn_cast<Instruction>(*UI);
if (!Use || !CurLoop->contains(Use))
continue;
-
+
// If there is an non-load/store instruction in the loop, we can't promote
// it.
- if (isa<LoadInst>(Use))
+ unsigned InstAlignment;
+ if (LoadInst *load = dyn_cast<LoadInst>(Use)) {
assert(!cast<LoadInst>(Use)->isVolatile() && "AST broken");
- else if (isa<StoreInst>(Use)) {
+ InstAlignment = load->getAlignment();
+ } else if (StoreInst *store = dyn_cast<StoreInst>(Use)) {
// Stores *of* the pointer are not interesting, only stores *to* the
// pointer.
if (Use->getOperand(1) != ASIV)
continue;
+ InstAlignment = store->getAlignment();
assert(!cast<StoreInst>(Use)->isVolatile() && "AST broken");
} else
return; // Not a load or store.
-
+
+ // If the alignment of this instruction allows us to specify a more
+ // restrictive (and performant) alignment and if we are sure this
+ // instruction will be executed, update the alignment.
+ // Larger is better, with the exception of 0 being the best alignment.
+ if ((InstAlignment > Alignment || InstAlignment == 0)
+ && (Alignment != 0))
+ if (isSafeToExecuteUnconditionally(*Use)) {
+ GuaranteedToExecute = true;
+ Alignment = InstAlignment;
+ }
+
if (!GuaranteedToExecute)
GuaranteedToExecute = isSafeToExecuteUnconditionally(*Use);
-
+
LoopUses.push_back(Use);
}
}
-
+
// If there isn't a guaranteed-to-execute instruction, we can't promote.
if (!GuaranteedToExecute)
return;
-
+
// Otherwise, this is safe to promote, lets do it!
- DEBUG(dbgs() << "LICM: Promoting value stored to in loop: " <<*SomePtr<<'\n');
+ DEBUG(dbgs() << "LICM: Promoting value stored to in loop: " <<*SomePtr<<'\n');
Changed = true;
++NumPromoted;
@@ -741,18 +762,19 @@
SmallVector<BasicBlock*, 8> ExitBlocks;
CurLoop->getUniqueExitBlocks(ExitBlocks);
-
+
// We use the SSAUpdater interface to insert phi nodes as required.
SmallVector<PHINode*, 16> NewPHIs;
SSAUpdater SSA(&NewPHIs);
LoopPromoter Promoter(SomePtr, LoopUses, SSA, PointerMustAliases, ExitBlocks,
- *CurAST, DL);
-
+ *CurAST, DL, Alignment);
+
// Set up the preheader to have a definition of the value. It is the live-out
// value from the preheader that uses in the loop will use.
LoadInst *PreheaderLoad =
new LoadInst(SomePtr, SomePtr->getName()+".promoted",
Preheader->getTerminator());
+ PreheaderLoad->setAlignment(Alignment);
PreheaderLoad->setDebugLoc(DL);
SSA.AddAvailableValue(Preheader, PreheaderLoad);
Modified: llvm/branches/type-system-rewrite/lib/Transforms/Scalar/Scalar.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Transforms/Scalar/Scalar.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Transforms/Scalar/Scalar.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Transforms/Scalar/Scalar.cpp Thu Jul 7 23:45:15 2011
@@ -48,6 +48,7 @@
initializeLoopUnswitchPass(Registry);
initializeLoopIdiomRecognizePass(Registry);
initializeLowerAtomicPass(Registry);
+ initializeLowerExpectIntrinsicPass(Registry);
initializeMemCpyOptPass(Registry);
initializeObjCARCAliasAnalysisPass(Registry);
initializeObjCARCExpandPass(Registry);
Modified: llvm/branches/type-system-rewrite/lib/Transforms/Scalar/ScalarReplAggregates.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Transforms/Scalar/ScalarReplAggregates.cpp Thu Jul 7 23:45:15 2011
@@ -30,6 +30,7 @@
#include "llvm/LLVMContext.h"
#include "llvm/Module.h"
#include "llvm/Pass.h"
+#include "llvm/Analysis/DebugInfo.h"
#include "llvm/Analysis/DIBuilder.h"
#include "llvm/Analysis/Dominators.h"
#include "llvm/Analysis/Loads.h"
@@ -1094,16 +1095,37 @@
namespace {
class AllocaPromoter : public LoadAndStorePromoter {
AllocaInst *AI;
+ DIBuilder *DIB;
+ SmallVector<DbgDeclareInst *, 4> DDIs;
+ SmallVector<DbgValueInst *, 4> DVIs;
public:
AllocaPromoter(const SmallVectorImpl<Instruction*> &Insts, SSAUpdater &S,
- DbgDeclareInst *DD, DIBuilder *&DB)
- : LoadAndStorePromoter(Insts, S, DD, DB), AI(0) {}
+ DIBuilder *DB)
+ : LoadAndStorePromoter(Insts, S), AI(0), DIB(DB) {}
void run(AllocaInst *AI, const SmallVectorImpl<Instruction*> &Insts) {
// Remember which alloca we're promoting (for isInstInList).
this->AI = AI;
+ if (MDNode *DebugNode = MDNode::getIfExists(AI->getContext(), AI))
+ for (Value::use_iterator UI = DebugNode->use_begin(),
+ E = DebugNode->use_end(); UI != E; ++UI)
+ if (DbgDeclareInst *DDI = dyn_cast<DbgDeclareInst>(*UI))
+ DDIs.push_back(DDI);
+ else if (DbgValueInst *DVI = dyn_cast<DbgValueInst>(*UI))
+ DVIs.push_back(DVI);
+
LoadAndStorePromoter::run(Insts);
AI->eraseFromParent();
+ for (SmallVector<DbgDeclareInst *, 4>::iterator I = DDIs.begin(),
+ E = DDIs.end(); I != E; ++I) {
+ DbgDeclareInst *DDI = *I;
+ DDI->eraseFromParent();
+ }
+ for (SmallVector<DbgValueInst *, 4>::iterator I = DVIs.begin(),
+ E = DVIs.end(); I != E; ++I) {
+ DbgValueInst *DVI = *I;
+ DVI->eraseFromParent();
+ }
}
virtual bool isInstInList(Instruction *I,
@@ -1112,6 +1134,45 @@
return LI->getOperand(0) == AI;
return cast<StoreInst>(I)->getPointerOperand() == AI;
}
+
+ virtual void updateDebugInfo(Instruction *Inst) const {
+ for (SmallVector<DbgDeclareInst *, 4>::const_iterator I = DDIs.begin(),
+ E = DDIs.end(); I != E; ++I) {
+ DbgDeclareInst *DDI = *I;
+ if (StoreInst *SI = dyn_cast<StoreInst>(Inst))
+ ConvertDebugDeclareToDebugValue(DDI, SI, *DIB);
+ else if (LoadInst *LI = dyn_cast<LoadInst>(Inst))
+ ConvertDebugDeclareToDebugValue(DDI, LI, *DIB);
+ }
+ for (SmallVector<DbgValueInst *, 4>::const_iterator I = DVIs.begin(),
+ E = DVIs.end(); I != E; ++I) {
+ DbgValueInst *DVI = *I;
+ if (StoreInst *SI = dyn_cast<StoreInst>(Inst)) {
+ Instruction *DbgVal = NULL;
+ // If an argument is zero extended then use argument directly. The ZExt
+ // may be zapped by an optimization pass in future.
+ Argument *ExtendedArg = NULL;
+ if (ZExtInst *ZExt = dyn_cast<ZExtInst>(SI->getOperand(0)))
+ ExtendedArg = dyn_cast<Argument>(ZExt->getOperand(0));
+ if (SExtInst *SExt = dyn_cast<SExtInst>(SI->getOperand(0)))
+ ExtendedArg = dyn_cast<Argument>(SExt->getOperand(0));
+ if (ExtendedArg)
+ DbgVal = DIB->insertDbgValueIntrinsic(ExtendedArg, 0,
+ DIVariable(DVI->getVariable()),
+ SI);
+ else
+ DbgVal = DIB->insertDbgValueIntrinsic(SI->getOperand(0), 0,
+ DIVariable(DVI->getVariable()),
+ SI);
+ DbgVal->setDebugLoc(DVI->getDebugLoc());
+ } else if (LoadInst *LI = dyn_cast<LoadInst>(Inst)) {
+ Instruction *DbgVal =
+ DIB->insertDbgValueIntrinsic(LI->getOperand(0), 0,
+ DIVariable(DVI->getVariable()), LI);
+ DbgVal->setDebugLoc(DVI->getDebugLoc());
+ }
+ }
+ }
};
} // end anon namespace
@@ -1381,10 +1442,9 @@
DT = &getAnalysis<DominatorTree>();
BasicBlock &BB = F.getEntryBlock(); // Get the entry node for the function
-
+ DIBuilder DIB(*F.getParent());
bool Changed = false;
SmallVector<Instruction*, 64> Insts;
- DIBuilder *DIB = 0;
while (1) {
Allocas.clear();
@@ -1408,11 +1468,7 @@
for (Value::use_iterator UI = AI->use_begin(), E = AI->use_end();
UI != E; ++UI)
Insts.push_back(cast<Instruction>(*UI));
-
- DbgDeclareInst *DDI = FindAllocaDbgDeclare(AI);
- if (DDI && !DIB)
- DIB = new DIBuilder(*AI->getParent()->getParent()->getParent());
- AllocaPromoter(Insts, SSA, DDI, DIB).run(AI, Insts);
+ AllocaPromoter(Insts, SSA, &DIB).run(AI, Insts);
Insts.clear();
}
}
@@ -1420,10 +1476,6 @@
Changed = true;
}
- // FIXME: Is there a better way to handle the lazy initialization of DIB
- // so that there doesn't need to be an explicit delete?
- delete DIB;
-
return Changed;
}
Modified: llvm/branches/type-system-rewrite/lib/Transforms/Utils/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Transforms/Utils/CMakeLists.txt?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Transforms/Utils/CMakeLists.txt (original)
+++ llvm/branches/type-system-rewrite/lib/Transforms/Utils/CMakeLists.txt Thu Jul 7 23:45:15 2011
@@ -14,6 +14,7 @@
Local.cpp
LoopSimplify.cpp
LoopUnroll.cpp
+ LowerExpectIntrinsic.cpp
LowerInvoke.cpp
LowerSwitch.cpp
Mem2Reg.cpp
Modified: llvm/branches/type-system-rewrite/lib/Transforms/Utils/SSAUpdater.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/Transforms/Utils/SSAUpdater.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/Transforms/Utils/SSAUpdater.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/Transforms/Utils/SSAUpdater.cpp Thu Jul 7 23:45:15 2011
@@ -16,7 +16,6 @@
#include "llvm/Instructions.h"
#include "llvm/IntrinsicInst.h"
#include "llvm/ADT/DenseMap.h"
-#include "llvm/Analysis/DIBuilder.h"
#include "llvm/Analysis/InstructionSimplify.h"
#include "llvm/Support/AlignOf.h"
#include "llvm/Support/Allocator.h"
@@ -358,8 +357,7 @@
LoadAndStorePromoter::
LoadAndStorePromoter(const SmallVectorImpl<Instruction*> &Insts,
- SSAUpdater &S, DbgDeclareInst *DD, DIBuilder *DB,
- StringRef BaseName) : SSA(S), DDI(DD), DIB(DB) {
+ SSAUpdater &S, StringRef BaseName) : SSA(S) {
if (Insts.empty()) return;
Value *SomeVal;
@@ -407,8 +405,7 @@
if (BlockUses.size() == 1) {
// If it is a store, it is a trivial def of the value in the block.
if (StoreInst *SI = dyn_cast<StoreInst>(User)) {
- if (DDI)
- ConvertDebugDeclareToDebugValue(DDI, SI, *DIB);
+ updateDebugInfo(SI);
SSA.AddAvailableValue(BB, SI->getOperand(0));
} else
// Otherwise it is a load, queue it to rewrite as a live-in load.
@@ -462,9 +459,7 @@
if (StoreInst *SI = dyn_cast<StoreInst>(II)) {
// If this is a store to an unrelated pointer, ignore it.
if (!isInstInList(SI, Insts)) continue;
-
- if (DDI)
- ConvertDebugDeclareToDebugValue(DDI, SI, *DIB);
+ updateDebugInfo(SI);
// Remember that this is the active value in the block.
StoredValue = SI->getOperand(0);
@@ -522,7 +517,4 @@
instructionDeleted(User);
User->eraseFromParent();
}
-
- if (DDI)
- DDI->eraseFromParent();
}
Modified: llvm/branches/type-system-rewrite/lib/VMCore/LLVMContext.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/lib/VMCore/LLVMContext.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/lib/VMCore/LLVMContext.cpp (original)
+++ llvm/branches/type-system-rewrite/lib/VMCore/LLVMContext.cpp Thu Jul 7 23:45:15 2011
@@ -39,6 +39,10 @@
// Create the 'tbaa' metadata kind.
unsigned TBAAID = getMDKindID("tbaa");
assert(TBAAID == MD_tbaa && "tbaa kind id drifted"); (void)TBAAID;
+
+ // Create the 'prof' metadata kind.
+ unsigned ProfID = getMDKindID("prof");
+ assert(ProfID == MD_prof && "prof kind id drifted"); (void)ProfID;
}
LLVMContext::~LLVMContext() { delete pImpl; }
Modified: llvm/branches/type-system-rewrite/test/CodeGen/ARM/2009-10-30.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/ARM/2009-10-30.ll?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/ARM/2009-10-30.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/ARM/2009-10-30.ll Thu Jul 7 23:45:15 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s
+; RUN: llc < %s -mtriple=armv6-linux-gnueabi | FileCheck %s
; This test checks that the address of the varg arguments is correctly
; computed when there are 5 or more regular arguments.
Modified: llvm/branches/type-system-rewrite/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll Thu Jul 7 23:45:15 2011
@@ -1,7 +1,7 @@
; RUN: llc %s -mtriple=arm-linux-gnueabi -filetype=obj -o - | \
; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=BASIC %s
; RUN: llc %s -mtriple=armv7-linux-gnueabi -march=arm -mcpu=cortex-a8 \
-; RUN: -mattr=-neon -mattr=+vfp2 \
+; RUN: -mattr=-neon,-vfp3,+vfp2 \
; RUN: -arm-reserve-r9 -filetype=obj -o - | \
; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=CORTEXA8 %s
Modified: llvm/branches/type-system-rewrite/test/CodeGen/ARM/armv4.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/ARM/armv4.ll?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/ARM/armv4.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/ARM/armv4.ll Thu Jul 7 23:45:15 2011
@@ -1,7 +1,7 @@
-; RUN: llc < %s -mtriple=arm-unknown-eabi | FileCheck %s -check-prefix=THUMB
-; RUN: llc < %s -mtriple=arm-unknown-eabi -mcpu=strongarm | FileCheck %s -check-prefix=ARM
-; RUN: llc < %s -mtriple=arm-unknown-eabi -mcpu=cortex-a8 | FileCheck %s -check-prefix=THUMB
-; RUN: llc < %s -mtriple=arm-unknown-eabi -mattr=+v6 | FileCheck %s -check-prefix=THUMB
+; RUN: llc < %s -mtriple=armv4t-unknown-eabi | FileCheck %s -check-prefix=THUMB
+; RUN: llc < %s -mtriple=armv4-unknown-eabi -mcpu=strongarm | FileCheck %s -check-prefix=ARM
+; RUN: llc < %s -mtriple=armv7-unknown-eabi -mcpu=cortex-a8 | FileCheck %s -check-prefix=THUMB
+; RUN: llc < %s -mtriple=armv6-unknown-eabi | FileCheck %s -check-prefix=THUMB
; RUN: llc < %s -mtriple=armv4-unknown-eabi | FileCheck %s -check-prefix=ARM
; RUN: llc < %s -mtriple=armv4t-unknown-eabi | FileCheck %s -check-prefix=THUMB
Modified: llvm/branches/type-system-rewrite/test/CodeGen/ARM/bfx.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/ARM/bfx.ll?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/ARM/bfx.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/ARM/bfx.ll Thu Jul 7 23:45:15 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm -mattr=+v7a | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+v7 | FileCheck %s
define i32 @sbfx1(i32 %a) {
; CHECK: sbfx1
Modified: llvm/branches/type-system-rewrite/test/CodeGen/ARM/call.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/ARM/call.ll?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/ARM/call.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/ARM/call.ll Thu Jul 7 23:45:15 2011
@@ -1,6 +1,6 @@
-; RUN: llc < %s -march=arm | FileCheck %s -check-prefix=CHECKV4
+; RUN: llc < %s -march=arm -mattr=+v4t | FileCheck %s -check-prefix=CHECKV4
; RUN: llc < %s -march=arm -mattr=+v5t | FileCheck %s -check-prefix=CHECKV5
-; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi\
+; RUN: llc < %s -mtriple=armv6-linux-gnueabi\
; RUN: -relocation-model=pic | FileCheck %s -check-prefix=CHECKELF
@t = weak global i32 ()* null ; <i32 ()**> [#uses=1]
Modified: llvm/branches/type-system-rewrite/test/CodeGen/ARM/globals.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/ARM/globals.ll?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/ARM/globals.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/ARM/globals.ll Thu Jul 7 23:45:15 2011
@@ -1,7 +1,7 @@
-; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=static | FileCheck %s -check-prefix=DarwinStatic
-; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=dynamic-no-pic | FileCheck %s -check-prefix=DarwinDynamic
-; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic | FileCheck %s -check-prefix=DarwinPIC
-; RUN: llc < %s -mtriple=arm-linux-gnueabi -relocation-model=pic | FileCheck %s -check-prefix=LinuxPIC
+; RUN: llc < %s -mtriple=armv6-apple-darwin -relocation-model=static | FileCheck %s -check-prefix=DarwinStatic
+; RUN: llc < %s -mtriple=armv6-apple-darwin -relocation-model=dynamic-no-pic | FileCheck %s -check-prefix=DarwinDynamic
+; RUN: llc < %s -mtriple=armv6-apple-darwin -relocation-model=pic | FileCheck %s -check-prefix=DarwinPIC
+; RUN: llc < %s -mtriple=armv6-linux-gnueabi -relocation-model=pic | FileCheck %s -check-prefix=LinuxPIC
@G = external global i32
Modified: llvm/branches/type-system-rewrite/test/CodeGen/ARM/hello.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/ARM/hello.ll?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/ARM/hello.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/ARM/hello.ll Thu Jul 7 23:45:15 2011
@@ -1,8 +1,8 @@
; RUN: llc < %s -march=arm
-; RUN: llc < %s -mtriple=arm-linux-gnueabi | grep mov | count 1
-; RUN: llc < %s -mtriple=arm-linux-gnu --disable-fp-elim | \
+; RUN: llc < %s -mtriple=armv6-linux-gnueabi | grep mov | count 1
+; RUN: llc < %s -mtriple=armv6-linux-gnu --disable-fp-elim | \
; RUN: grep mov | count 2
-; RUN: llc < %s -mtriple=arm-apple-darwin | grep mov | count 2
+; RUN: llc < %s -mtriple=armv6-apple-darwin | grep mov | count 2
@str = internal constant [12 x i8] c"Hello World\00"
Modified: llvm/branches/type-system-rewrite/test/CodeGen/ARM/iabs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/ARM/iabs.ll?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/ARM/iabs.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/ARM/iabs.ll Thu Jul 7 23:45:15 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+v4t | FileCheck %s
;; Integer absolute value, should produce something as good as: ARM:
;; add r3, r0, r0, asr #31
Modified: llvm/branches/type-system-rewrite/test/CodeGen/ARM/ifcvt1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/ARM/ifcvt1.ll?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/ARM/ifcvt1.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/ARM/ifcvt1.ll Thu Jul 7 23:45:15 2011
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=arm
-; RUN: llc < %s -march=arm | grep bx | count 1
+; RUN: llc < %s -march=arm -mattr=+v4t
+; RUN: llc < %s -march=arm -mattr=+v4t | grep bx | count 1
define i32 @t1(i32 %a, i32 %b) {
%tmp2 = icmp eq i32 %a, 0
Modified: llvm/branches/type-system-rewrite/test/CodeGen/ARM/ifcvt2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/ARM/ifcvt2.ll?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/ARM/ifcvt2.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/ARM/ifcvt2.ll Thu Jul 7 23:45:15 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+v4t | FileCheck %s
define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) {
; CHECK: t1:
Modified: llvm/branches/type-system-rewrite/test/CodeGen/ARM/ifcvt3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/ARM/ifcvt3.ll?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/ARM/ifcvt3.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/ARM/ifcvt3.ll Thu Jul 7 23:45:15 2011
@@ -1,6 +1,6 @@
-; RUN: llc < %s -march=arm
-; RUN: llc < %s -march=arm | grep cmpne | count 1
-; RUN: llc < %s -march=arm | grep bx | count 2
+; RUN: llc < %s -march=arm -mattr=+v4t
+; RUN: llc < %s -march=arm -mattr=+v4t | grep cmpne | count 1
+; RUN: llc < %s -march=arm -mattr=+v4t | grep bx | count 2
define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) {
switch i32 %c, label %cond_next [
Modified: llvm/branches/type-system-rewrite/test/CodeGen/ARM/indirectbr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/ARM/indirectbr.ll?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/ARM/indirectbr.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/ARM/indirectbr.ll Thu Jul 7 23:45:15 2011
@@ -1,5 +1,5 @@
-; RUN: llc < %s -relocation-model=pic -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=ARM
-; RUN: llc < %s -relocation-model=pic -mtriple=thumb-apple-darwin | FileCheck %s -check-prefix=THUMB
+; RUN: llc < %s -relocation-model=pic -mtriple=armv6-apple-darwin | FileCheck %s -check-prefix=ARM
+; RUN: llc < %s -relocation-model=pic -mtriple=thumbv6-apple-darwin | FileCheck %s -check-prefix=THUMB
; RUN: llc < %s -relocation-model=static -mtriple=thumbv7-apple-darwin | FileCheck %s -check-prefix=THUMB2
@nextaddr = global i8* null ; <i8**> [#uses=2]
Modified: llvm/branches/type-system-rewrite/test/CodeGen/ARM/ldr_frame.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/ARM/ldr_frame.ll?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/ARM/ldr_frame.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/ARM/ldr_frame.ll Thu Jul 7 23:45:15 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm | not grep mov
+; RUN: llc < %s -march=arm -mattr=+v4t | not grep mov
define i32 @f1() {
%buf = alloca [32 x i32], align 4
Modified: llvm/branches/type-system-rewrite/test/CodeGen/ARM/phi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/ARM/phi.ll?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/ARM/phi.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/ARM/phi.ll Thu Jul 7 23:45:15 2011
@@ -1,4 +1,4 @@
-; RUN: llc -march=arm < %s | FileCheck %s
+; RUN: llc -march=arm -mattr=+v4t < %s | FileCheck %s
; <rdar://problem/8686347>
define i32 @test1(i1 %a, i32* %b) {
@@ -20,4 +20,4 @@
%r = load i32* %gep
; CHECK-NEXT: bx lr
ret i32 %r
-}
\ No newline at end of file
+}
Modified: llvm/branches/type-system-rewrite/test/CodeGen/ARM/prefetch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/ARM/prefetch.ll?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/ARM/prefetch.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/ARM/prefetch.ll Thu Jul 7 23:45:15 2011
@@ -1,6 +1,6 @@
; RUN: llc < %s -march=thumb -mattr=-thumb2 | not grep pld
-; RUN: llc < %s -march=thumb -mattr=+v7a | FileCheck %s -check-prefix=THUMB2
-; RUN: llc < %s -march=arm -mattr=+v7a | FileCheck %s -check-prefix=ARM
+; RUN: llc < %s -march=thumb -mattr=+v7 | FileCheck %s -check-prefix=THUMB2
+; RUN: llc < %s -march=arm -mattr=+v7 | FileCheck %s -check-prefix=ARM
; RUN: llc < %s -march=arm -mcpu=cortex-a9-mp | FileCheck %s -check-prefix=ARM-MP
; rdar://8601536
Modified: llvm/branches/type-system-rewrite/test/CodeGen/ARM/truncstore-dag-combine.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/ARM/truncstore-dag-combine.ll?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/ARM/truncstore-dag-combine.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/ARM/truncstore-dag-combine.ll Thu Jul 7 23:45:15 2011
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=arm | not grep orr
-; RUN: llc < %s -march=arm | not grep mov
+; RUN: llc < %s -march=arm -mattr=+v4t | not grep orr
+; RUN: llc < %s -march=arm -mattr=+v4t | not grep mov
define void @bar(i8* %P, i16* %Q) {
entry:
Modified: llvm/branches/type-system-rewrite/test/CodeGen/Thumb/barrier.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/Thumb/barrier.ll?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/Thumb/barrier.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/Thumb/barrier.ll Thu Jul 7 23:45:15 2011
@@ -1,6 +1,6 @@
; RUN: llc < %s -mtriple=thumbv6-apple-darwin | FileCheck %s -check-prefix=V6
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=-db | FileCheck %s -check-prefix=V6
-; RUN: llc < %s -march=thumb -mattr=+v6m | FileCheck %s -check-prefix=V6M
+; RUN: llc < %s -march=thumb -mcpu=cortex-m0 | FileCheck %s -check-prefix=V6M
declare void @llvm.memory.barrier(i1 , i1 , i1 , i1 , i1)
Modified: llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll Thu Jul 7 23:45:15 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -O3 -relocation-model=pic -mattr=+thumb2 -mcpu=cortex-a8 | FileCheck %s
+; RUN: llc < %s -O3 -relocation-model=pic -mattr=+thumb2 -mcpu=cortex-a8 -disable-branch-fold | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32"
target triple = "thumbv7-apple-darwin10"
@@ -26,7 +26,7 @@
; CHECK: vldr.64 [[LDR:d.*]],
; CHECK: LPC0_0:
; CHECK: vadd.f64 [[ADD:d.*]], [[LDR]], [[LDR]]
-; CHECK: vmov.f64 [[LDR]]
+; CHECK-NOT: vmov.f64 [[ADD]]
%5 = fadd <2 x double> %3, %3 ; <<2 x double>> [#uses=2]
%6 = fadd <2 x double> %4, %4 ; <<2 x double>> [#uses=2]
%tmp7 = extractelement <2 x double> %5, i32 0 ; <double> [#uses=1]
Modified: llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/lsr-deficiency.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/lsr-deficiency.ll?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/lsr-deficiency.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/lsr-deficiency.ll Thu Jul 7 23:45:15 2011
@@ -13,16 +13,16 @@
define void @t() nounwind optsize {
; CHECK: t:
-; CHECK: mov.w r2, #1000
+; CHECK: mov{{.*}}, #1000
entry:
%.pre = load i32* @G, align 4 ; <i32> [#uses=1]
br label %bb
bb: ; preds = %bb, %entry
; CHECK: LBB0_1:
-; CHECK: cmp r2, #0
-; CHECK: sub{{(.w)?}} [[REGISTER:(r[0-9]+)|(lr)]], r2, #1
-; CHECK: mov r2, [[REGISTER]]
+; CHECK: cmp [[R2:r[0-9]+]], #0
+; CHECK: sub{{(.w)?}} [[REGISTER:(r[0-9]+)|(lr)]], [[R2]], #1
+; CHECK: mov [[R2]], [[REGISTER]]
%0 = phi i32 [ %.pre, %entry ], [ %3, %bb ] ; <i32> [#uses=1]
%indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=2]
Modified: llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/machine-licm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/machine-licm.ll?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/machine-licm.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/machine-licm.ll Thu Jul 7 23:45:15 2011
@@ -52,8 +52,8 @@
define void @t2(i8* %ptr1, i8* %ptr2) nounwind {
entry:
; CHECK: t2:
-; CHECK: mov.w r3, #1065353216
-; CHECK: vdup.32 q{{.*}}, r3
+; CHECK: mov.w [[R3:r[0-9]+]], #1065353216
+; CHECK: vdup.32 q{{.*}}, [[R3]]
br i1 undef, label %bb1, label %bb2
bb1:
Modified: llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/thumb2-clz.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/thumb2-clz.ll?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/thumb2-clz.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/thumb2-clz.ll Thu Jul 7 23:45:15 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7a | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7 | FileCheck %s
define i32 @f1(i32 %a) {
; CHECK: f1:
Modified: llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/thumb2-rev.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/thumb2-rev.ll?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/thumb2-rev.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/Thumb2/thumb2-rev.ll Thu Jul 7 23:45:15 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7a,+t2xtpk | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7,+t2xtpk | FileCheck %s
define i32 @f1(i32 %a) {
; CHECK: f1:
Removed: llvm/branches/type-system-rewrite/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll?rev=134683&view=auto
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll (removed)
@@ -1,121 +0,0 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -relocation-model=pic -disable-fp-elim -stats |& grep asm-printer | grep 77
-; rdar://6802189
-
-; Test if linearscan is unfavoring registers for allocation to allow more reuse
-; of reloads from stack slots.
-
- %struct.SHA_CTX = type { i32, i32, i32, i32, i32, i32, i32, [16 x i32], i32 }
-
-define fastcc void @sha1_block_data_order(%struct.SHA_CTX* nocapture %c, i8* %p, i64 %num) nounwind {
-entry:
- br label %bb
-
-bb: ; preds = %bb, %entry
- %asmtmp511 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 0) nounwind ; <i32> [#uses=3]
- %asmtmp513 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 0) nounwind ; <i32> [#uses=2]
- %asmtmp516 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 0) nounwind ; <i32> [#uses=1]
- %asmtmp517 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 0) nounwind ; <i32> [#uses=2]
- %0 = xor i32 0, %asmtmp513 ; <i32> [#uses=0]
- %1 = add i32 0, %asmtmp517 ; <i32> [#uses=1]
- %2 = add i32 %1, 0 ; <i32> [#uses=1]
- %3 = add i32 %2, 0 ; <i32> [#uses=1]
- %asmtmp519 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 0) nounwind ; <i32> [#uses=1]
- %4 = xor i32 0, %asmtmp511 ; <i32> [#uses=1]
- %asmtmp520 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 %4) nounwind ; <i32> [#uses=2]
- %5 = xor i32 0, %asmtmp516 ; <i32> [#uses=1]
- %6 = xor i32 %5, %asmtmp519 ; <i32> [#uses=1]
- %7 = add i32 %asmtmp513, -899497514 ; <i32> [#uses=1]
- %8 = add i32 %7, %asmtmp520 ; <i32> [#uses=1]
- %9 = add i32 %8, %6 ; <i32> [#uses=1]
- %10 = add i32 %9, 0 ; <i32> [#uses=1]
- %asmtmp523 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 0) nounwind ; <i32> [#uses=1]
- %asmtmp525 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %3) nounwind ; <i32> [#uses=2]
- %11 = xor i32 0, %asmtmp525 ; <i32> [#uses=1]
- %12 = add i32 0, %11 ; <i32> [#uses=1]
- %13 = add i32 %12, 0 ; <i32> [#uses=2]
- %asmtmp528 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %10) nounwind ; <i32> [#uses=1]
- %14 = xor i32 0, %asmtmp520 ; <i32> [#uses=1]
- %asmtmp529 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 %14) nounwind ; <i32> [#uses=1]
- %asmtmp530 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 5, i32 %13) nounwind ; <i32> [#uses=1]
- %15 = add i32 0, %asmtmp530 ; <i32> [#uses=1]
- %16 = xor i32 0, %asmtmp523 ; <i32> [#uses=1]
- %asmtmp532 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 %16) nounwind ; <i32> [#uses=2]
- %asmtmp533 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 5, i32 %15) nounwind ; <i32> [#uses=1]
- %17 = xor i32 %13, %asmtmp528 ; <i32> [#uses=1]
- %18 = xor i32 %17, 0 ; <i32> [#uses=1]
- %19 = add i32 %asmtmp525, -899497514 ; <i32> [#uses=1]
- %20 = add i32 %19, %asmtmp532 ; <i32> [#uses=1]
- %21 = add i32 %20, %18 ; <i32> [#uses=1]
- %22 = add i32 %21, %asmtmp533 ; <i32> [#uses=1]
- %23 = xor i32 0, %asmtmp511 ; <i32> [#uses=1]
- %24 = xor i32 %23, 0 ; <i32> [#uses=1]
- %asmtmp535 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 %24) nounwind ; <i32> [#uses=3]
- %25 = add i32 0, %asmtmp535 ; <i32> [#uses=1]
- %26 = add i32 %25, 0 ; <i32> [#uses=1]
- %27 = add i32 %26, 0 ; <i32> [#uses=1]
- %28 = xor i32 0, %asmtmp529 ; <i32> [#uses=0]
- %29 = xor i32 %22, 0 ; <i32> [#uses=1]
- %30 = xor i32 %29, 0 ; <i32> [#uses=1]
- %31 = add i32 0, %30 ; <i32> [#uses=1]
- %32 = add i32 %31, 0 ; <i32> [#uses=3]
- %asmtmp541 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 0) nounwind ; <i32> [#uses=2]
- %asmtmp542 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 5, i32 %32) nounwind ; <i32> [#uses=1]
- %33 = add i32 0, %asmtmp541 ; <i32> [#uses=1]
- %34 = add i32 %33, 0 ; <i32> [#uses=1]
- %35 = add i32 %34, %asmtmp542 ; <i32> [#uses=1]
- %asmtmp543 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %27) nounwind ; <i32> [#uses=2]
- %36 = xor i32 0, %asmtmp535 ; <i32> [#uses=0]
- %37 = xor i32 %32, 0 ; <i32> [#uses=1]
- %38 = xor i32 %37, %asmtmp543 ; <i32> [#uses=1]
- %39 = add i32 0, %38 ; <i32> [#uses=1]
- %40 = add i32 %39, 0 ; <i32> [#uses=2]
- %asmtmp546 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %32) nounwind ; <i32> [#uses=1]
- %asmtmp547 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 0) nounwind ; <i32> [#uses=2]
- %41 = add i32 0, -899497514 ; <i32> [#uses=1]
- %42 = add i32 %41, %asmtmp547 ; <i32> [#uses=1]
- %43 = add i32 %42, 0 ; <i32> [#uses=1]
- %44 = add i32 %43, 0 ; <i32> [#uses=3]
- %asmtmp549 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %35) nounwind ; <i32> [#uses=2]
- %45 = xor i32 0, %asmtmp541 ; <i32> [#uses=1]
- %asmtmp550 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 %45) nounwind ; <i32> [#uses=2]
- %asmtmp551 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 5, i32 %44) nounwind ; <i32> [#uses=1]
- %46 = xor i32 %40, %asmtmp546 ; <i32> [#uses=1]
- %47 = xor i32 %46, %asmtmp549 ; <i32> [#uses=1]
- %48 = add i32 %asmtmp543, -899497514 ; <i32> [#uses=1]
- %49 = add i32 %48, %asmtmp550 ; <i32> [#uses=1]
- %50 = add i32 %49, %47 ; <i32> [#uses=1]
- %51 = add i32 %50, %asmtmp551 ; <i32> [#uses=1]
- %asmtmp552 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %40) nounwind ; <i32> [#uses=2]
- %52 = xor i32 %44, %asmtmp549 ; <i32> [#uses=1]
- %53 = xor i32 %52, %asmtmp552 ; <i32> [#uses=1]
- %54 = add i32 0, %53 ; <i32> [#uses=1]
- %55 = add i32 %54, 0 ; <i32> [#uses=2]
- %asmtmp555 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %44) nounwind ; <i32> [#uses=2]
- %56 = xor i32 0, %asmtmp532 ; <i32> [#uses=1]
- %57 = xor i32 %56, %asmtmp547 ; <i32> [#uses=1]
- %asmtmp556 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 %57) nounwind ; <i32> [#uses=1]
- %58 = add i32 0, %asmtmp556 ; <i32> [#uses=1]
- %59 = add i32 %58, 0 ; <i32> [#uses=1]
- %60 = add i32 %59, 0 ; <i32> [#uses=1]
- %asmtmp558 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %51) nounwind ; <i32> [#uses=1]
- %61 = xor i32 %asmtmp517, %asmtmp511 ; <i32> [#uses=1]
- %62 = xor i32 %61, %asmtmp535 ; <i32> [#uses=1]
- %63 = xor i32 %62, %asmtmp550 ; <i32> [#uses=1]
- %asmtmp559 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 %63) nounwind ; <i32> [#uses=1]
- %64 = xor i32 %55, %asmtmp555 ; <i32> [#uses=1]
- %65 = xor i32 %64, %asmtmp558 ; <i32> [#uses=1]
- %asmtmp561 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %55) nounwind ; <i32> [#uses=1]
- %66 = add i32 %asmtmp552, -899497514 ; <i32> [#uses=1]
- %67 = add i32 %66, %65 ; <i32> [#uses=1]
- %68 = add i32 %67, %asmtmp559 ; <i32> [#uses=1]
- %69 = add i32 %68, 0 ; <i32> [#uses=1]
- %70 = add i32 %69, 0 ; <i32> [#uses=1]
- store i32 %70, i32* null, align 4
- %71 = add i32 0, %60 ; <i32> [#uses=1]
- store i32 %71, i32* null, align 4
- %72 = add i32 0, %asmtmp561 ; <i32> [#uses=1]
- store i32 %72, i32* null, align 4
- %73 = add i32 0, %asmtmp555 ; <i32> [#uses=1]
- store i32 %73, i32* null, align 4
- br label %bb
-}
Modified: llvm/branches/type-system-rewrite/test/CodeGen/X86/2010-04-08-CoalescerBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/X86/2010-04-08-CoalescerBug.ll?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/X86/2010-04-08-CoalescerBug.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/X86/2010-04-08-CoalescerBug.ll Thu Jul 7 23:45:15 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core2 | FileCheck %s
; rdar://7842028
; Do not delete partially dead copy instructions.
Modified: llvm/branches/type-system-rewrite/test/CodeGen/X86/2010-06-25-CoalescerSubRegDefDead.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/X86/2010-06-25-CoalescerSubRegDefDead.ll?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/X86/2010-06-25-CoalescerSubRegDefDead.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/X86/2010-06-25-CoalescerSubRegDefDead.ll Thu Jul 7 23:45:15 2011
@@ -1,4 +1,4 @@
-; RUN: llc -O1 -mtriple=x86_64-unknown-linux-gnu -relocation-model=pic -disable-fp-elim < %s | FileCheck %s
+; RUN: llc -O1 -mtriple=x86_64-unknown-linux-gnu -mcpu=core2 -relocation-model=pic -disable-fp-elim < %s | FileCheck %s
; <rdar://problem/8124405>
%struct.type = type { %struct.subtype*, i32, i8, i32, i8, i32, i32, i32, i32, i32, i8, i32, i32, i32, i32, i32, [256 x i32], i32, [257 x i32], [257 x i32], i32*, i16*, i8*, i32, i32, i32, i32, i32, [256 x i8], [16 x i8], [256 x i8], [4096 x i8], [16 x i32], [18002 x i8], [18002 x i8], [6 x [258 x i8]], [6 x [258 x i32]], [6 x [258 x i32]], [6 x [258 x i32]], [6 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32*, i32*, i32* }
Modified: llvm/branches/type-system-rewrite/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll Thu Jul 7 23:45:15 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -combiner-alias-analysis -march=x86-64 | FileCheck %s
+; RUN: llc < %s -combiner-alias-analysis -march=x86-64 -mcpu=core2 | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
target triple = "x86_64-apple-darwin10.4"
Modified: llvm/branches/type-system-rewrite/test/CodeGen/X86/crash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/X86/crash.ll?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/X86/crash.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/X86/crash.ll Thu Jul 7 23:45:15 2011
@@ -215,3 +215,104 @@
}
declare i64 @llvm.objectsize.i64(i8*, i1) nounwind readnone
+
+; PR10277
+; This test has dead code elimination caused by remat during spilling.
+; DCE causes a live interval to break into connected components.
+; One of the components is spilled.
+
+%t2 = type { i8 }
+%t9 = type { %t10 }
+%t10 = type { %t11 }
+%t11 = type { %t12 }
+%t12 = type { %t13*, %t13*, %t13* }
+%t13 = type { %t14*, %t15, %t15 }
+%t14 = type opaque
+%t15 = type { i8, i32, i32 }
+%t16 = type { %t17, i8* }
+%t17 = type { %t18 }
+%t18 = type { %t19 }
+%t19 = type { %t20*, %t20*, %t20* }
+%t20 = type { i32, i32 }
+%t21 = type { %t13* }
+
+define void @_ZNK4llvm17MipsFrameLowering12emitPrologueERNS_15MachineFunctionE() ssp align 2 {
+bb:
+ %tmp = load %t9** undef, align 4, !tbaa !0
+ %tmp2 = getelementptr inbounds %t9* %tmp, i32 0, i32 0
+ %tmp3 = getelementptr inbounds %t9* %tmp, i32 0, i32 0, i32 0, i32 0, i32 1
+ br label %bb4
+
+bb4: ; preds = %bb37, %bb
+ %tmp5 = phi i96 [ undef, %bb ], [ %tmp38, %bb37 ]
+ %tmp6 = phi i96 [ undef, %bb ], [ %tmp39, %bb37 ]
+ br i1 undef, label %bb34, label %bb7
+
+bb7: ; preds = %bb4
+ %tmp8 = load i32* undef, align 4
+ %tmp9 = and i96 %tmp6, 4294967040
+ %tmp10 = zext i32 %tmp8 to i96
+ %tmp11 = shl nuw nsw i96 %tmp10, 32
+ %tmp12 = or i96 %tmp9, %tmp11
+ %tmp13 = or i96 %tmp12, 1
+ %tmp14 = load i32* undef, align 4
+ %tmp15 = and i96 %tmp5, 4294967040
+ %tmp16 = zext i32 %tmp14 to i96
+ %tmp17 = shl nuw nsw i96 %tmp16, 32
+ %tmp18 = or i96 %tmp15, %tmp17
+ %tmp19 = or i96 %tmp18, 1
+ %tmp20 = load i8* undef, align 1
+ %tmp21 = and i8 %tmp20, 1
+ %tmp22 = icmp ne i8 %tmp21, 0
+ %tmp23 = select i1 %tmp22, i96 %tmp19, i96 %tmp13
+ %tmp24 = select i1 %tmp22, i96 %tmp13, i96 %tmp19
+ store i96 %tmp24, i96* undef, align 4
+ %tmp25 = load %t13** %tmp3, align 4
+ %tmp26 = icmp eq %t13* %tmp25, undef
+ br i1 %tmp26, label %bb28, label %bb27
+
+bb27: ; preds = %bb7
+ br label %bb29
+
+bb28: ; preds = %bb7
+ call void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%t10* %tmp2, %t21* byval align 4 undef, %t13* undef)
+ br label %bb29
+
+bb29: ; preds = %bb28, %bb27
+ store i96 %tmp23, i96* undef, align 4
+ %tmp30 = load %t13** %tmp3, align 4
+ br i1 false, label %bb33, label %bb31
+
+bb31: ; preds = %bb29
+ %tmp32 = getelementptr inbounds %t13* %tmp30, i32 1
+ store %t13* %tmp32, %t13** %tmp3, align 4
+ br label %bb37
+
+bb33: ; preds = %bb29
+ unreachable
+
+bb34: ; preds = %bb4
+ br i1 undef, label %bb36, label %bb35
+
+bb35: ; preds = %bb34
+ store %t13* null, %t13** %tmp3, align 4
+ br label %bb37
+
+bb36: ; preds = %bb34
+ call void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%t10* %tmp2, %t21* byval align 4 undef, %t13* undef)
+ br label %bb37
+
+bb37: ; preds = %bb36, %bb35, %bb31
+ %tmp38 = phi i96 [ %tmp23, %bb31 ], [ %tmp5, %bb35 ], [ %tmp5, %bb36 ]
+ %tmp39 = phi i96 [ %tmp24, %bb31 ], [ %tmp6, %bb35 ], [ %tmp6, %bb36 ]
+ %tmp40 = add i32 undef, 1
+ br label %bb4
+}
+
+declare %t14* @_ZN4llvm9MCContext16CreateTempSymbolEv(%t2*)
+
+declare void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%t10*, %t21* byval align 4, %t13*)
+
+declare void @llvm.lifetime.start(i64, i8* nocapture) nounwind
+
+declare void @llvm.lifetime.end(i64, i8* nocapture) nounwind
Modified: llvm/branches/type-system-rewrite/test/CodeGen/X86/inline-asm-q-regs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/X86/inline-asm-q-regs.ll?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/X86/inline-asm-q-regs.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/X86/inline-asm-q-regs.ll Thu Jul 7 23:45:15 2011
@@ -3,8 +3,20 @@
%0 = type { i64, i64, i64, i64, i64 } ; type %0
-define void @t() nounwind {
+define void @test1() nounwind {
entry:
%asmtmp = call %0 asm sideeffect "mov %cr0, $0 \0Amov %cr2, $1 \0Amov %cr3, $2 \0Amov %cr4, $3 \0Amov %cr8, $0 \0A", "=q,=q,=q,=q,=q,~{dirflag},~{fpsr},~{flags}"() nounwind ; <%0> [#uses=0]
ret void
}
+
+; PR9602
+define void @test2(float %tmp) nounwind {
+ call void asm sideeffect "$0", "q"(float %tmp) nounwind
+ call void asm sideeffect "$0", "Q"(float %tmp) nounwind
+ ret void
+}
+
+define void @test3(double %tmp) nounwind {
+ call void asm sideeffect "$0", "q"(double %tmp) nounwind
+ ret void
+}
Modified: llvm/branches/type-system-rewrite/test/CodeGen/X86/inline-asm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/X86/inline-asm.ll?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/X86/inline-asm.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/X86/inline-asm.ll Thu Jul 7 23:45:15 2011
@@ -23,3 +23,10 @@
tail call void asm sideeffect "bork $0", "J"(i32 37) nounwind
ret void
}
+
+; rdar://9738585
+define i32 @test5() nounwind {
+entry:
+ %0 = tail call i32 asm "test", "=l,~{dirflag},~{fpsr},~{flags}"() nounwind
+ ret i32 0
+}
Modified: llvm/branches/type-system-rewrite/test/CodeGen/X86/lsr-nonaffine.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/X86/lsr-nonaffine.ll?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/X86/lsr-nonaffine.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/X86/lsr-nonaffine.ll Thu Jul 7 23:45:15 2011
@@ -1,4 +1,4 @@
-; RUN: llc -asm-verbose=false -march=x86-64 -o - < %s | FileCheck %s
+; RUN: llc -asm-verbose=false -march=x86-64 -mtriple=x86_64-apple-darwin -o - < %s | FileCheck %s
; LSR should leave non-affine expressions alone because it currently
; doesn't know how to do anything with them, and when it tries, it
Modified: llvm/branches/type-system-rewrite/test/CodeGen/X86/memcpy.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/X86/memcpy.ll?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/X86/memcpy.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/X86/memcpy.ll Thu Jul 7 23:45:15 2011
@@ -1,5 +1,5 @@
-; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s -check-prefix=LINUX
-; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s -check-prefix=DARWIN
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=core2 | FileCheck %s -check-prefix=LINUX
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=DARWIN
declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind
Modified: llvm/branches/type-system-rewrite/test/CodeGen/X86/tlv-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/CodeGen/X86/tlv-1.ll?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/CodeGen/X86/tlv-1.ll (original)
+++ llvm/branches/type-system-rewrite/test/CodeGen/X86/tlv-1.ll Thu Jul 7 23:45:15 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple x86_64-apple-darwin | FileCheck %s
+; RUN: llc < %s -mtriple x86_64-apple-darwin -mcpu=core2 | FileCheck %s
%struct.A = type { [48 x i8], i32, i32, i32 }
Modified: llvm/branches/type-system-rewrite/test/MC/ARM/prefetch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/MC/ARM/prefetch.ll?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/MC/ARM/prefetch.ll (original)
+++ llvm/branches/type-system-rewrite/test/MC/ARM/prefetch.ll Thu Jul 7 23:45:15 2011
@@ -1,5 +1,5 @@
-; RUN: llc < %s -mtriple=armv7-apple-darwin -mattr=+v7a,+mp -show-mc-encoding | FileCheck %s -check-prefix=ARM
-; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+v7a -show-mc-encoding | FileCheck %s -check-prefix=T2
+; RUN: llc < %s -mtriple=armv7-apple-darwin -mattr=+v7,+mp -show-mc-encoding | FileCheck %s -check-prefix=ARM
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+v7 -show-mc-encoding | FileCheck %s -check-prefix=T2
; rdar://8924681
define void @t1(i8* %ptr) nounwind {
Modified: llvm/branches/type-system-rewrite/test/MC/ELF/relocation.s
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/MC/ELF/relocation.s?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/MC/ELF/relocation.s (original)
+++ llvm/branches/type-system-rewrite/test/MC/ELF/relocation.s Thu Jul 7 23:45:15 2011
@@ -92,23 +92,23 @@
// CHECK: # Relocation 0x0000000b
// CHECK-NEXT: (('r_offset', 0x0000004e)
// CHECK-NEXT: ('r_sym', 0x00000002)
-// CHECK-NEXT: ('r_type', 0x0000000b)
+// CHECK-NEXT: ('r_type', 0x0000000e)
// CHECK-NEXT: ('r_addend', 0x00000000)
// CHECK: # Relocation 0x0000000c
-// CHECK-NEXT: (('r_offset', 0x00000055)
+// CHECK-NEXT: (('r_offset', 0x00000052)
// CHECK-NEXT: ('r_sym', 0x00000006)
// CHECK-NEXT: ('r_type', 0x00000002)
// CHECK-NEXT: ('r_addend', 0xfffffffc)
// CHECK: # Relocation 0x0000000d
-// CHECK-NEXT: (('r_offset', 0x0000005c)
+// CHECK-NEXT: (('r_offset', 0x00000059)
// CHECK-NEXT: ('r_sym', 0x00000006)
// CHECK-NEXT: ('r_type', 0x00000002)
-// CHECK-NEXT: ('r_addend', 0x0000005c)
+// CHECK-NEXT: ('r_addend', 0x00000059)
// CHECK: # Relocation 0x0000000e
-// CHECK-NEXT: (('r_offset', 0x00000063)
+// CHECK-NEXT: (('r_offset', 0x00000060)
// CHECK-NEXT: ('r_sym', 0x00000002)
// CHECK-NEXT: ('r_type', 0x0000000b)
// CHECK-NEXT: ('r_addend', 0x00000000)
Modified: llvm/branches/type-system-rewrite/test/MC/X86/x86-64.s
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/MC/X86/x86-64.s?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/MC/X86/x86-64.s (original)
+++ llvm/branches/type-system-rewrite/test/MC/X86/x86-64.s Thu Jul 7 23:45:15 2011
@@ -219,6 +219,12 @@
// CHECK: pushq $1
push $1
+// rdar://9716860
+pushq $1
+// CHECK: encoding: [0x6a,0x01]
+pushq $1111111
+// CHECK: encoding: [0x68,0x47,0xf4,0x10,0x00]
+
// rdar://8017530
// CHECK: sldtw 4
sldt 4
@@ -1148,3 +1154,19 @@
// CHECK: movntiq
movntiq %rax, (%rdi)
movnti %rax, (%rdi)
+
+// CHECK: pclmulqdq $17, %xmm0, %xmm1
+// CHECK: encoding: [0x66,0x0f,0x3a,0x44,0xc8,0x11]
+pclmulhqhqdq %xmm0, %xmm1
+
+// CHECK: pclmulqdq $1, %xmm0, %xmm1
+// CHECK: encoding: [0x66,0x0f,0x3a,0x44,0xc8,0x01]
+pclmulqdq $1, %xmm0, %xmm1
+
+// CHECK: pclmulqdq $16, (%rdi), %xmm1
+// CHECK: encoding: [0x66,0x0f,0x3a,0x44,0x0f,0x10]
+pclmullqhqdq (%rdi), %xmm1
+
+// CHECK: pclmulqdq $0, (%rdi), %xmm1
+// CHECK: encoding: [0x66,0x0f,0x3a,0x44,0x0f,0x00]
+pclmulqdq $0, (%rdi), %xmm1
Modified: llvm/branches/type-system-rewrite/test/Transforms/IndVarSimplify/no-iv-rewrite.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/Transforms/IndVarSimplify/no-iv-rewrite.ll?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/Transforms/IndVarSimplify/no-iv-rewrite.ll (original)
+++ llvm/branches/type-system-rewrite/test/Transforms/IndVarSimplify/no-iv-rewrite.ll Thu Jul 7 23:45:15 2011
@@ -270,3 +270,53 @@
return:
ret i32 %i.0
}
+
+; Eliminate the congruent phis j, k, and l.
+; Eliminate the redundant IV increments k.next and l.next.
+; Two phis should remain, one starting at %init, and one at %init1.
+; Two increments should remain, one by %step and one by %step1.
+; CHECK: loop:
+; CHECK: phi i32
+; CHECK: phi i32
+; CHECK-NOT: phi
+; CHECK: add i32
+; CHECK: add i32
+; CHECK-NOT: add
+; CHECK: return:
+;
+; Five live-outs should remain.
+; CHECK: lcssa = phi
+; CHECK: lcssa = phi
+; CHECK: lcssa = phi
+; CHECK: lcssa = phi
+; CHECK: lcssa = phi
+; CHECK-NOT: phi
+; CHECK: ret
+define i32 @isomorphic(i32 %init, i32 %step, i32 %lim) nounwind {
+entry:
+ %step1 = add i32 %step, 1
+ %init1 = add i32 %init, %step1
+ %l.0 = sub i32 %init1, %step1
+ br label %loop
+
+loop:
+ %ii = phi i32 [ %init1, %entry ], [ %ii.next, %loop ]
+ %i = phi i32 [ %init, %entry ], [ %ii, %loop ]
+ %j = phi i32 [ %init, %entry ], [ %j.next, %loop ]
+ %k = phi i32 [ %init1, %entry ], [ %k.next, %loop ]
+ %l = phi i32 [ %l.0, %entry ], [ %l.next, %loop ]
+ %ii.next = add i32 %ii, %step1
+ %j.next = add i32 %j, %step1
+ %k.next = add i32 %k, %step1
+ %l.step = add i32 %l, %step
+ %l.next = add i32 %l.step, 1
+ %cmp = icmp ne i32 %ii.next, %lim
+ br i1 %cmp, label %loop, label %return
+
+return:
+ %sum1 = add i32 %i, %j.next
+ %sum2 = add i32 %sum1, %k.next
+ %sum3 = add i32 %sum1, %l.step
+ %sum4 = add i32 %sum1, %l.next
+ ret i32 %sum4
+}
Modified: llvm/branches/type-system-rewrite/test/Transforms/IndVarSimplify/variable-stride-ivs-0.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/Transforms/IndVarSimplify/variable-stride-ivs-0.ll?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/Transforms/IndVarSimplify/variable-stride-ivs-0.ll (original)
+++ llvm/branches/type-system-rewrite/test/Transforms/IndVarSimplify/variable-stride-ivs-0.ll Thu Jul 7 23:45:15 2011
@@ -1,9 +1,9 @@
-; RUN: opt < %s -indvars -instcombine -S | \
-; RUN: grep {store i32 0}
+; RUN: opt < %s -indvars -instcombine -S | FileCheck %s
+; RUN: opt < %s -indvars -disable-iv-rewrite -instcombine -S | FileCheck %s
+;
; Test that -indvars can reduce variable stride IVs. If it can reduce variable
-; stride iv's, it will make %iv. and %m.0.0 isomorphic to each other without
+; stride iv's, it will make %iv. and %m.0.0 isomorphic to each other without
; cycles, allowing the tmp.21 subtraction to be eliminated.
-; END.
define void @vnum_test8(i32* %data) {
entry:
@@ -20,6 +20,7 @@
%tmp.16 = getelementptr i32* %data, i32 %tmp.9 ; <i32*> [#uses=1]
br label %no_exit
+; CHECK: store i32 0
no_exit: ; preds = %no_exit, %no_exit.preheader
%iv.ui = phi i32 [ 0, %no_exit.preheader ], [ %iv..inc.ui, %no_exit ] ; <i32> [#uses=1]
%iv. = phi i32 [ %tmp.5, %no_exit.preheader ], [ %iv..inc, %no_exit ] ; <i32> [#uses=2]
Modified: llvm/branches/type-system-rewrite/test/Transforms/InstCombine/icmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/test/Transforms/InstCombine/icmp.ll?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/test/Transforms/InstCombine/icmp.ll (original)
+++ llvm/branches/type-system-rewrite/test/Transforms/InstCombine/icmp.ll Thu Jul 7 23:45:15 2011
@@ -547,3 +547,15 @@
%cmp = icmp eq i32 %sub, 123
ret i1 %cmp
}
+
+; PR10267 Don't make icmps more expensive when no other inst is subsumed.
+declare void @foo(i32)
+; CHECK: @test57
+; CHECK: %and = and i32 %a, -2
+; CHECK: %cmp = icmp ne i32 %and, 0
+define i1 @test57(i32 %a) {
+ %and = and i32 %a, -2
+ %cmp = icmp ne i32 %and, 0
+ call void @foo(i32 %and)
+ ret i1 %cmp
+}
Modified: llvm/branches/type-system-rewrite/tools/llvm-mc/Disassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/tools/llvm-mc/Disassembler.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/tools/llvm-mc/Disassembler.cpp (original)
+++ llvm/branches/type-system-rewrite/tools/llvm-mc/Disassembler.cpp Thu Jul 7 23:45:15 2011
@@ -127,7 +127,7 @@
return false;
}
-int Disassembler::disassemble(const Target &T, TargetMachine &TM,
+int Disassembler::disassemble(const Target &T,
const std::string &Triple,
MemoryBuffer &Buffer,
raw_ostream &Out) {
@@ -146,7 +146,7 @@
}
int AsmPrinterVariant = AsmInfo->getAssemblerDialect();
- OwningPtr<MCInstPrinter> IP(T.createMCInstPrinter(TM, AsmPrinterVariant,
+ OwningPtr<MCInstPrinter> IP(T.createMCInstPrinter(AsmPrinterVariant,
*AsmInfo));
if (!IP) {
errs() << "error: no instruction printer for target " << Triple << '\n';
Modified: llvm/branches/type-system-rewrite/tools/llvm-mc/Disassembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/tools/llvm-mc/Disassembler.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/tools/llvm-mc/Disassembler.h (original)
+++ llvm/branches/type-system-rewrite/tools/llvm-mc/Disassembler.h Thu Jul 7 23:45:15 2011
@@ -21,13 +21,11 @@
class MemoryBuffer;
class Target;
-class TargetMachine;
class raw_ostream;
class Disassembler {
public:
static int disassemble(const Target &target,
- TargetMachine &TM,
const std::string &tripleString,
MemoryBuffer &buffer,
raw_ostream &Out);
Modified: llvm/branches/type-system-rewrite/tools/llvm-mc/llvm-mc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/tools/llvm-mc/llvm-mc.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/tools/llvm-mc/llvm-mc.cpp (original)
+++ llvm/branches/type-system-rewrite/tools/llvm-mc/llvm-mc.cpp Thu Jul 7 23:45:15 2011
@@ -343,7 +343,7 @@
// FIXME: There is a bit of code duplication with addPassesToEmitFile.
if (FileType == OFT_AssemblyFile) {
MCInstPrinter *IP =
- TheTarget->createMCInstPrinter(*TM, OutputAsmVariant, *MAI);
+ TheTarget->createMCInstPrinter(OutputAsmVariant, *MAI);
MCCodeEmitter *CE = 0;
TargetAsmBackend *TAB = 0;
if (ShowEncoding) {
@@ -371,7 +371,8 @@
OwningPtr<MCAsmParser> Parser(createMCAsmParser(*TheTarget, SrcMgr, Ctx,
*Str.get(), *MAI));
- OwningPtr<TargetAsmParser> TAP(TheTarget->createAsmParser(*Parser, *TM));
+ OwningPtr<TargetAsmParser>
+ TAP(TheTarget->createAsmParser(TripleName, MCPU, FeaturesStr, *Parser));
if (!TAP) {
errs() << ProgName
<< ": error: this target does not support assembly parsing.\n";
@@ -426,7 +427,7 @@
return 1;
}
- Res = Disassembler::disassemble(*TheTarget, *TM, TripleName,
+ Res = Disassembler::disassemble(*TheTarget, TripleName,
*Buffer.take(), Out->os());
}
Modified: llvm/branches/type-system-rewrite/tools/llvm-objdump/llvm-objdump.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/tools/llvm-objdump/llvm-objdump.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/tools/llvm-objdump/llvm-objdump.cpp (original)
+++ llvm/branches/type-system-rewrite/tools/llvm-objdump/llvm-objdump.cpp Thu Jul 7 23:45:15 2011
@@ -14,12 +14,6 @@
//===----------------------------------------------------------------------===//
#include "llvm/Object/ObjectFile.h"
-// This config must be included before llvm-config.h.
-#include "llvm/Config/config.h"
-#include "../../lib/MC/MCDisassembler/EDDisassembler.h"
-#include "../../lib/MC/MCDisassembler/EDInst.h"
-#include "../../lib/MC/MCDisassembler/EDOperand.h"
-#include "../../lib/MC/MCDisassembler/EDToken.h"
#include "llvm/ADT/OwningPtr.h"
#include "llvm/ADT/Triple.h"
#include "llvm/MC/MCAsmInfo.h"
@@ -38,12 +32,9 @@
#include "llvm/Support/SourceMgr.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Support/system_error.h"
-#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegistry.h"
#include "llvm/Target/TargetSelect.h"
#include <algorithm>
-#include <cctype>
-#include <cerrno>
#include <cstring>
using namespace llvm;
using namespace object;
@@ -196,22 +187,9 @@
return;
}
- // FIXME: We shouldn't need to do this (and link in codegen).
- // When we split this out, we should do it in a way that makes
- // it straightforward to switch subtargets on the fly (.e.g,
- // the .cpu and .code16 directives).
- std::string FeaturesStr;
- std::string CPU;
- OwningPtr<TargetMachine> TM(TheTarget->createTargetMachine(TripleName, CPU,
- FeaturesStr));
- if (!TM) {
- errs() << "error: could not create target for triple " << TripleName << "\n";
- return;
- }
-
int AsmPrinterVariant = AsmInfo->getAssemblerDialect();
OwningPtr<MCInstPrinter> IP(TheTarget->createMCInstPrinter(
- *TM, AsmPrinterVariant, *AsmInfo));
+ AsmPrinterVariant, *AsmInfo));
if (!IP) {
errs() << "error: no instruction printer for target " << TripleName << '\n';
return;
Modified: llvm/branches/type-system-rewrite/tools/lto/LTOModule.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/tools/lto/LTOModule.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/tools/lto/LTOModule.cpp (original)
+++ llvm/branches/type-system-rewrite/tools/lto/LTOModule.cpp Thu Jul 7 23:45:15 2011
@@ -619,7 +619,10 @@
Context, *Streamer,
*_target->getMCAsmInfo()));
OwningPtr<TargetAsmParser>
- TAP(_target->getTarget().createAsmParser(*Parser.get(), *_target.get()));
+ TAP(_target->getTarget().createAsmParser(_target->getTargetTriple(),
+ _target->getTargetCPU(),
+ _target->getTargetFeatureString(),
+ *Parser.get()));
Parser->setTargetParser(*TAP);
int Res = Parser->Run(false);
if (Res)
Modified: llvm/branches/type-system-rewrite/unittests/ADT/SmallVectorTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/unittests/ADT/SmallVectorTest.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/unittests/ADT/SmallVectorTest.cpp (original)
+++ llvm/branches/type-system-rewrite/unittests/ADT/SmallVectorTest.cpp Thu Jul 7 23:45:15 2011
@@ -35,26 +35,26 @@
Constructable() : value(0) {
++numConstructorCalls;
}
-
+
Constructable(int val) : value(val) {
++numConstructorCalls;
}
-
+
Constructable(const Constructable & src) {
value = src.value;
++numConstructorCalls;
}
-
+
~Constructable() {
++numDestructorCalls;
}
-
+
Constructable & operator=(const Constructable & src) {
value = src.value;
++numAssignmentCalls;
return *this;
}
-
+
int getValue() const {
return abs(value);
}
@@ -64,7 +64,7 @@
numDestructorCalls = 0;
numAssignmentCalls = 0;
}
-
+
static int getNumConstructorCalls() {
return numConstructorCalls;
}
@@ -91,10 +91,10 @@
class SmallVectorTest : public testing::Test {
protected:
typedef SmallVector<Constructable, 4> VectorType;
-
+
VectorType theVector;
VectorType otherVector;
-
+
void SetUp() {
Constructable::reset();
}
@@ -111,7 +111,7 @@
// Assert that theVector contains the specified values, in order.
void assertValuesInOrder(VectorType & v, size_t size, ...) {
EXPECT_EQ(size, v.size());
-
+
va_list ap;
va_start(ap, size);
for (size_t i = 0; i < size; ++i) {
@@ -121,7 +121,7 @@
va_end(ap);
}
-
+
// Generate a sequence of values to initialize the vector.
void makeSequence(VectorType & v, int start, int end) {
for (int i = start; i <= end; ++i) {
@@ -155,18 +155,24 @@
theVector.push_back(Constructable(2));
assertValuesInOrder(theVector, 2u, 1, 2);
+ // Insert at beginning
+ theVector.insert(theVector.begin(), theVector[1]);
+ assertValuesInOrder(theVector, 3u, 2, 1, 2);
+
// Pop one element
theVector.pop_back();
- assertValuesInOrder(theVector, 1u, 1);
+ assertValuesInOrder(theVector, 2u, 2, 1);
- // Pop another element
+ // Pop remaining elements
+ theVector.pop_back();
theVector.pop_back();
assertEmpty(theVector);
-
+
// Check number of constructor calls. Should be 2 for each list element,
- // one for the argument to push_back, and one for the list element itself.
- EXPECT_EQ(4, Constructable::getNumConstructorCalls());
- EXPECT_EQ(4, Constructable::getNumDestructorCalls());
+ // one for the argument to push_back, one for the argument to insert,
+ // and one for the list element itself.
+ EXPECT_EQ(5, Constructable::getNumConstructorCalls());
+ EXPECT_EQ(5, Constructable::getNumDestructorCalls());
}
// Clear test.
@@ -198,7 +204,7 @@
SCOPED_TRACE("ResizeGrowTest");
theVector.resize(2);
-
+
// The extra constructor/destructor calls come from the temporary object used
// to initialize the contents of the resized array (via copy construction).
EXPECT_EQ(3, Constructable::getNumConstructorCalls());
@@ -226,10 +232,10 @@
for (int i = 0; i < 10; ++i) {
EXPECT_EQ(i+1, theVector[i].getValue());
}
-
+
// Now resize back to fixed size.
theVector.resize(1);
-
+
assertValuesInOrder(theVector, 1u, 1);
}
@@ -364,13 +370,13 @@
makeSequence(theVector, 1, 3);
makeSequence(otherVector, 1, 3);
-
+
EXPECT_TRUE(theVector == otherVector);
EXPECT_FALSE(theVector != otherVector);
otherVector.clear();
makeSequence(otherVector, 2, 4);
-
+
EXPECT_FALSE(theVector == otherVector);
EXPECT_TRUE(theVector != otherVector);
}
Modified: llvm/branches/type-system-rewrite/utils/TableGen/ARMDecoderEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/utils/TableGen/ARMDecoderEmitter.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/utils/TableGen/ARMDecoderEmitter.cpp (original)
+++ llvm/branches/type-system-rewrite/utils/TableGen/ARMDecoderEmitter.cpp Thu Jul 7 23:45:15 2011
@@ -421,6 +421,9 @@
protected:
// Populates the insn given the uid.
void insnWithID(insn_t &Insn, unsigned Opcode) const {
+ if (AllInstructions[Opcode]->isPseudo)
+ return;
+
BitsInit &Bits = getBitsField(*AllInstructions[Opcode]->TheDef, "Inst");
for (unsigned i = 0; i < BIT_WIDTH; ++i)
Modified: llvm/branches/type-system-rewrite/utils/TableGen/AsmMatcherEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/utils/TableGen/AsmMatcherEmitter.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/utils/TableGen/AsmMatcherEmitter.cpp (original)
+++ llvm/branches/type-system-rewrite/utils/TableGen/AsmMatcherEmitter.cpp Thu Jul 7 23:45:15 2011
@@ -1817,15 +1817,43 @@
Info.AsmParser->getValueAsString("AsmParserClassName");
OS << "unsigned " << Info.Target.getName() << ClassName << "::\n"
- << "ComputeAvailableFeatures(const " << Info.Target.getName()
- << "Subtarget *Subtarget) const {\n";
+ << "ComputeAvailableFeatures(uint64_t FB) const {\n";
OS << " unsigned Features = 0;\n";
for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
it = Info.SubtargetFeatures.begin(),
ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
SubtargetFeatureInfo &SFI = *it->second;
- OS << " if (" << SFI.TheDef->getValueAsString("CondString")
- << ")\n";
+
+ OS << " if (";
+ StringRef Conds = SFI.TheDef->getValueAsString("AssemblerCondString");
+ std::pair<StringRef,StringRef> Comma = Conds.split(',');
+ bool First = true;
+ do {
+ if (!First)
+ OS << " && ";
+
+ bool Neg = false;
+ StringRef Cond = Comma.first;
+ if (Cond[0] == '!') {
+ Neg = true;
+ Cond = Cond.substr(1);
+ }
+
+ OS << "((FB & " << Info.Target.getName() << "::" << Cond << ")";
+ if (Neg)
+ OS << " == 0";
+ else
+ OS << " != 0";
+ OS << ")";
+
+ if (Comma.second.empty())
+ break;
+
+ First = false;
+ Comma = Comma.second.split(',');
+ } while (true);
+
+ OS << ")\n";
OS << " Features |= " << SFI.getEnumName() << ";\n";
}
OS << " return Features;\n";
@@ -2140,8 +2168,7 @@
OS << "#undef GET_ASSEMBLER_HEADER\n";
OS << " // This should be included into the middle of the declaration of\n";
OS << " // your subclasses implementation of TargetAsmParser.\n";
- OS << " unsigned ComputeAvailableFeatures(const " <<
- Target.getName() << "Subtarget *Subtarget) const;\n";
+ OS << " unsigned ComputeAvailableFeatures(uint64_t FeatureBits) const;\n";
OS << " enum MatchResultTy {\n";
OS << " Match_ConversionFail,\n";
OS << " Match_InvalidOperand,\n";
Modified: llvm/branches/type-system-rewrite/utils/TableGen/AsmWriterEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/utils/TableGen/AsmWriterEmitter.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/utils/TableGen/AsmWriterEmitter.cpp (original)
+++ llvm/branches/type-system-rewrite/utils/TableGen/AsmWriterEmitter.cpp Thu Jul 7 23:45:15 2011
@@ -606,92 +606,29 @@
}
namespace {
-
-/// SubtargetFeatureInfo - Helper class for storing information on a subtarget
-/// feature which participates in instruction matching.
-struct SubtargetFeatureInfo {
- /// \brief The predicate record for this feature.
- const Record *TheDef;
-
- /// \brief An unique index assigned to represent this feature.
- unsigned Index;
-
- SubtargetFeatureInfo(const Record *D, unsigned Idx) : TheDef(D), Index(Idx) {}
-
- /// \brief The name of the enumerated constant identifying this feature.
- std::string getEnumName() const {
- return "Feature_" + TheDef->getName();
- }
-};
-
-struct AsmWriterInfo {
- /// Map of Predicate records to their subtarget information.
- std::map<const Record*, SubtargetFeatureInfo*> SubtargetFeatures;
-
- /// getSubtargetFeature - Lookup or create the subtarget feature info for the
- /// given operand.
- SubtargetFeatureInfo *getSubtargetFeature(const Record *Def) const {
- assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
- std::map<const Record*, SubtargetFeatureInfo*>::const_iterator I =
- SubtargetFeatures.find(Def);
- return I == SubtargetFeatures.end() ? 0 : I->second;
- }
-
- void addReqFeatures(const std::vector<Record*> &Features) {
- for (std::vector<Record*>::const_iterator
- I = Features.begin(), E = Features.end(); I != E; ++I) {
- const Record *Pred = *I;
-
- // Ignore predicates that are not intended for the assembler.
- if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
- continue;
-
- if (Pred->getName().empty())
- throw TGError(Pred->getLoc(), "Predicate has no name!");
-
- // Don't add the predicate again.
- if (getSubtargetFeature(Pred))
- continue;
-
- unsigned FeatureNo = SubtargetFeatures.size();
- SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo);
- assert(FeatureNo < 32 && "Too many subtarget features!");
- }
- }
-
- const SubtargetFeatureInfo *getFeatureInfo(const Record *R) {
- return SubtargetFeatures[R];
- }
-};
-
// IAPrinter - Holds information about an InstAlias. Two InstAliases match if
// they both have the same conditionals. In which case, we cannot print out the
// alias for that pattern.
class IAPrinter {
- AsmWriterInfo &AWI;
std::vector<std::string> Conds;
std::map<StringRef, unsigned> OpMap;
std::string Result;
std::string AsmString;
std::vector<Record*> ReqFeatures;
public:
- IAPrinter(AsmWriterInfo &Info, std::string R, std::string AS)
- : AWI(Info), Result(R), AsmString(AS) {}
+ IAPrinter(std::string R, std::string AS)
+ : Result(R), AsmString(AS) {}
void addCond(const std::string &C) { Conds.push_back(C); }
- void addReqFeatures(const std::vector<Record*> &Features) {
- AWI.addReqFeatures(Features);
- ReqFeatures = Features;
- }
void addOperand(StringRef Op, unsigned Idx) { OpMap[Op] = Idx; }
unsigned getOpIndex(StringRef Op) { return OpMap[Op]; }
bool isOpMapped(StringRef Op) { return OpMap.find(Op) != OpMap.end(); }
- bool print(raw_ostream &O) {
+ void print(raw_ostream &O) {
if (Conds.empty() && ReqFeatures.empty()) {
O.indent(6) << "return true;\n";
- return false;
+ return;
}
O << "if (";
@@ -706,27 +643,6 @@
O << *I;
}
- if (!ReqFeatures.empty()) {
- if (Conds.begin() != Conds.end()) {
- O << " &&\n";
- O.indent(8);
- } else {
- O << "if (";
- }
-
- std::string Req;
- raw_string_ostream ReqO(Req);
-
- for (std::vector<Record*>::iterator
- I = ReqFeatures.begin(), E = ReqFeatures.end(); I != E; ++I) {
- if (I != ReqFeatures.begin()) ReqO << " | ";
- ReqO << AWI.getFeatureInfo(*I)->getEnumName();
- }
-
- O << "(AvailableFeatures & (" << ReqO.str() << ")) == ("
- << ReqO.str() << ')';
- }
-
O << ") {\n";
O.indent(6) << "// " << Result << "\n";
O.indent(6) << "AsmString = \"" << AsmString << "\";\n";
@@ -738,7 +654,6 @@
O.indent(6) << "break;\n";
O.indent(4) << '}';
- return !ReqFeatures.empty();
}
bool operator==(const IAPrinter &RHS) {
@@ -770,53 +685,6 @@
} // end anonymous namespace
-/// EmitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
-/// definitions.
-static void EmitSubtargetFeatureFlagEnumeration(AsmWriterInfo &Info,
- raw_ostream &O) {
- O << "namespace {\n\n";
- O << "// Flags for subtarget features that participate in "
- << "alias instruction matching.\n";
- O << "enum SubtargetFeatureFlag {\n";
-
- for (std::map<const Record*, SubtargetFeatureInfo*>::const_iterator
- I = Info.SubtargetFeatures.begin(),
- E = Info.SubtargetFeatures.end(); I != E; ++I) {
- SubtargetFeatureInfo &SFI = *I->second;
- O << " " << SFI.getEnumName() << " = (1 << " << SFI.Index << "),\n";
- }
-
- O << " Feature_None = 0\n";
- O << "};\n\n";
- O << "} // end anonymous namespace\n\n";
-}
-
-/// EmitComputeAvailableFeatures - Emit the function to compute the list of
-/// available features given a subtarget.
-static void EmitComputeAvailableFeatures(AsmWriterInfo &Info,
- Record *AsmWriter,
- CodeGenTarget &Target,
- raw_ostream &O) {
- std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
-
- O << "unsigned " << Target.getName() << ClassName << "::\n"
- << "ComputeAvailableFeatures(const " << Target.getName()
- << "Subtarget *Subtarget) const {\n";
- O << " unsigned Features = 0;\n";
-
- for (std::map<const Record*, SubtargetFeatureInfo*>::const_iterator
- I = Info.SubtargetFeatures.begin(),
- E = Info.SubtargetFeatures.end(); I != E; ++I) {
- SubtargetFeatureInfo &SFI = *I->second;
- O << " if (" << SFI.TheDef->getValueAsString("CondString")
- << ")\n";
- O << " Features |= " << SFI.getEnumName() << ";\n";
- }
-
- O << " return Features;\n";
- O << "}\n\n";
-}
-
static void EmitGetMapOperandNumber(raw_ostream &O) {
O << "static unsigned getMapOperandNumber("
<< "const SmallVectorImpl<std::pair<StringRef, unsigned> > &OpMap,\n";
@@ -960,7 +828,6 @@
// A map of which conditions need to be met for each instruction operand
// before it can be matched to the mnemonic.
std::map<std::string, std::vector<IAPrinter*> > IAPrinterMap;
- AsmWriterInfo AWI;
for (std::map<std::string, std::vector<CodeGenInstAlias*> >::iterator
I = AliasMap.begin(), E = AliasMap.end(); I != E; ++I) {
@@ -977,9 +844,8 @@
if (NumResultOps < CountNumOperands(CGA->AsmString))
continue;
- IAPrinter *IAP = new IAPrinter(AWI, CGA->Result->getAsString(),
+ IAPrinter *IAP = new IAPrinter(CGA->Result->getAsString(),
CGA->AsmString);
- IAP->addReqFeatures(CGA->TheDef->getValueAsListOfDefs("Predicates"));
std::string Cond;
Cond = std::string("MI->getNumOperands() == ") + llvm::utostr(LastOpNo);
@@ -1049,9 +915,6 @@
}
}
- EmitSubtargetFeatureFlagEnumeration(AWI, O);
- EmitComputeAvailableFeatures(AWI, AsmWriter, Target, O);
-
std::string Header;
raw_string_ostream HeaderO(Header);
@@ -1061,7 +924,6 @@
std::string Cases;
raw_string_ostream CasesO(Cases);
- bool NeedAvailableFeatures = false;
for (std::map<std::string, std::vector<IAPrinter*> >::iterator
I = IAPrinterMap.begin(), E = IAPrinterMap.end(); I != E; ++I) {
@@ -1092,7 +954,7 @@
II = UniqueIAPs.begin(), IE = UniqueIAPs.end(); II != IE; ++II) {
IAPrinter *IAP = *II;
CasesO.indent(4);
- NeedAvailableFeatures |= IAP->print(CasesO);
+ IAP->print(CasesO);
CasesO << '\n';
}
@@ -1112,8 +974,6 @@
O << HeaderO.str();
O.indent(2) << "StringRef AsmString;\n";
O.indent(2) << "SmallVector<std::pair<StringRef, unsigned>, 4> OpMap;\n";
- if (NeedAvailableFeatures)
- O.indent(2) << "unsigned AvailableFeatures = getAvailableFeatures();\n\n";
O.indent(2) << "switch (MI->getOpcode()) {\n";
O.indent(2) << "default: return false;\n";
O << CasesO.str();
Modified: llvm/branches/type-system-rewrite/utils/TableGen/CodeEmitterGen.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/utils/TableGen/CodeEmitterGen.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/utils/TableGen/CodeEmitterGen.cpp (original)
+++ llvm/branches/type-system-rewrite/utils/TableGen/CodeEmitterGen.cpp Thu Jul 7 23:45:15 2011
@@ -34,7 +34,8 @@
for (std::vector<Record*>::iterator I = Insts.begin(), E = Insts.end();
I != E; ++I) {
Record *R = *I;
- if (R->getValueAsString("Namespace") == "TargetOpcode")
+ if (R->getValueAsString("Namespace") == "TargetOpcode" ||
+ R->getValueAsBit("isPseudo"))
continue;
BitsInit *BI = R->getValueAsBitsInit("Inst");
@@ -231,7 +232,8 @@
const CodeGenInstruction *CGI = *IN;
Record *R = CGI->TheDef;
- if (R->getValueAsString("Namespace") == "TargetOpcode") {
+ if (R->getValueAsString("Namespace") == "TargetOpcode" ||
+ R->getValueAsBit("isPseudo")) {
o << " 0U,\n";
continue;
}
@@ -255,7 +257,8 @@
for (std::vector<Record*>::iterator IC = Insts.begin(), EC = Insts.end();
IC != EC; ++IC) {
Record *R = *IC;
- if (R->getValueAsString("Namespace") == "TargetOpcode")
+ if (R->getValueAsString("Namespace") == "TargetOpcode" ||
+ R->getValueAsBit("isPseudo"))
continue;
const std::string &InstName = R->getValueAsString("Namespace") + "::"
+ R->getName();
Modified: llvm/branches/type-system-rewrite/utils/TableGen/CodeGenDAGPatterns.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/utils/TableGen/CodeGenDAGPatterns.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/utils/TableGen/CodeGenDAGPatterns.cpp (original)
+++ llvm/branches/type-system-rewrite/utils/TableGen/CodeGenDAGPatterns.cpp Thu Jul 7 23:45:15 2011
@@ -1744,7 +1744,7 @@
Record *R = DI->getDef();
// Direct reference to a leaf DagNode or PatFrag? Turn it into a
- // TreePatternNode if its own. For example:
+ // TreePatternNode of its own. For example:
/// (foo GPR, imm) -> (foo GPR, (imm))
if (R->isSubClassOf("SDNode") || R->isSubClassOf("PatFrag"))
return ParseTreePattern(new DagInit(DI, "",
Modified: llvm/branches/type-system-rewrite/utils/TableGen/CodeGenInstruction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/utils/TableGen/CodeGenInstruction.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/utils/TableGen/CodeGenInstruction.cpp (original)
+++ llvm/branches/type-system-rewrite/utils/TableGen/CodeGenInstruction.cpp Thu Jul 7 23:45:15 2011
@@ -311,6 +311,8 @@
isAsCheapAsAMove = R->getValueAsBit("isAsCheapAsAMove");
hasExtraSrcRegAllocReq = R->getValueAsBit("hasExtraSrcRegAllocReq");
hasExtraDefRegAllocReq = R->getValueAsBit("hasExtraDefRegAllocReq");
+ isCodeGenOnly = R->getValueAsBit("isCodeGenOnly");
+ isPseudo = R->getValueAsBit("isPseudo");
ImplicitDefs = R->getValueAsListOfDefs("Defs");
ImplicitUses = R->getValueAsListOfDefs("Uses");
Modified: llvm/branches/type-system-rewrite/utils/TableGen/CodeGenInstruction.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/utils/TableGen/CodeGenInstruction.h?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/utils/TableGen/CodeGenInstruction.h (original)
+++ llvm/branches/type-system-rewrite/utils/TableGen/CodeGenInstruction.h Thu Jul 7 23:45:15 2011
@@ -235,6 +235,8 @@
bool isAsCheapAsAMove;
bool hasExtraSrcRegAllocReq;
bool hasExtraDefRegAllocReq;
+ bool isCodeGenOnly;
+ bool isPseudo;
CodeGenInstruction(Record *R);
Modified: llvm/branches/type-system-rewrite/utils/TableGen/EDEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/utils/TableGen/EDEmitter.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/utils/TableGen/EDEmitter.cpp (original)
+++ llvm/branches/type-system-rewrite/utils/TableGen/EDEmitter.cpp Thu Jul 7 23:45:15 2011
@@ -774,6 +774,11 @@
for (index = 0; index < numInstructions; ++index) {
const CodeGenInstruction& inst = *numberedInstructions[index];
+ // We don't need to do anything for pseudo-instructions, as we'll never
+ // see them here. We'll only see real instructions.
+ if (inst.isPseudo)
+ continue;
+
CompoundConstantEmitter *infoStruct = new CompoundConstantEmitter;
infoArray.addEntry(infoStruct);
Modified: llvm/branches/type-system-rewrite/utils/TableGen/FixedLenDecoderEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/utils/TableGen/FixedLenDecoderEmitter.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/utils/TableGen/FixedLenDecoderEmitter.cpp (original)
+++ llvm/branches/type-system-rewrite/utils/TableGen/FixedLenDecoderEmitter.cpp Thu Jul 7 23:45:15 2011
@@ -1225,14 +1225,14 @@
//
// This also removes pseudo instructions from considerations of disassembly,
// which is a better design and less fragile than the name matchings.
- BitsInit &Bits = getBitsField(Def, "Inst");
- if (Bits.allInComplete()) return false;
-
// Ignore "asm parser only" instructions.
if (Def.getValueAsBit("isAsmParserOnly") ||
Def.getValueAsBit("isCodeGenOnly"))
return false;
+ BitsInit &Bits = getBitsField(Def, "Inst");
+ if (Bits.allInComplete()) return false;
+
std::vector<OperandInfo> InsnOperands;
// If the instruction has specified a custom decoding hook, use that instead
@@ -1354,7 +1354,8 @@
void FixedLenDecoderEmitter::populateInstructions() {
for (unsigned i = 0, e = NumberedInstructions.size(); i < e; ++i) {
Record *R = NumberedInstructions[i]->TheDef;
- if (R->getValueAsString("Namespace") == "TargetOpcode")
+ if (R->getValueAsString("Namespace") == "TargetOpcode" ||
+ R->getValueAsBit("isPseudo"))
continue;
if (populateInstruction(*NumberedInstructions[i], i))
Modified: llvm/branches/type-system-rewrite/utils/TableGen/SubtargetEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/utils/TableGen/SubtargetEmitter.cpp?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/utils/TableGen/SubtargetEmitter.cpp (original)
+++ llvm/branches/type-system-rewrite/utils/TableGen/SubtargetEmitter.cpp Thu Jul 7 23:45:15 2011
@@ -605,8 +605,7 @@
<< "// subtarget options.\n"
<< "void llvm::";
OS << Target;
- OS << "Subtarget::ParseSubtargetFeatures(const std::string &FS,\n"
- << " const std::string &CPU) {\n"
+ OS << "Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {\n"
<< " DEBUG(dbgs() << \"\\nFeatures:\" << FS);\n"
<< " DEBUG(dbgs() << \"\\nCPU:\" << CPU);\n";
@@ -615,11 +614,7 @@
return;
}
- OS << " SubtargetFeatures Features(FS);\n"
- << " uint64_t Bits = Features.getFeatureBits(CPU, "
- << Target << "SubTypeKV, " << NumProcs << ",\n"
- << " " << Target << "FeatureKV, "
- << NumFeatures << ");\n";
+ OS << " uint64_t Bits = ReInitMCSubtargetInfo(CPU, FS);\n";
for (unsigned i = 0; i < Features.size(); i++) {
// Next record
@@ -629,10 +624,12 @@
const std::string &Attribute = R->getValueAsString("Attribute");
if (Value=="true" || Value=="false")
- OS << " if ((Bits & " << Target << "::" << Instance << ") != 0) "
+ OS << " if ((Bits & " << Target << "::"
+ << Instance << ") != 0) "
<< Attribute << " = " << Value << ";\n";
else
- OS << " if ((Bits & " << Target << "::" << Instance << ") != 0 && "
+ OS << " if ((Bits & " << Target << "::"
+ << Instance << ") != 0 && "
<< Attribute << " < " << Value << ") "
<< Attribute << " = " << Value << ";\n";
}
@@ -648,12 +645,18 @@
EmitSourceFileHeader("Subtarget Enumeration Source Fragment", OS);
+ OS << "\n#ifdef GET_SUBTARGETINFO_ENUM\n";
+ OS << "#undef GET_SUBTARGETINFO_ENUM\n";
+
+ OS << "namespace llvm {\n";
+ Enumeration(OS, "SubtargetFeature", true);
+ OS << "} // End llvm namespace \n";
+ OS << "#endif // GET_SUBTARGETINFO_ENUM\n\n";
+
OS << "\n#ifdef GET_SUBTARGETINFO_MC_DESC\n";
OS << "#undef GET_SUBTARGETINFO_MC_DESC\n";
OS << "namespace llvm {\n";
- Enumeration(OS, "SubtargetFeature", true);
- OS<<"\n";
unsigned NumFeatures = FeatureKeyValues(OS);
OS<<"\n";
unsigned NumProcs = CPUKeyValues(OS);
@@ -663,8 +666,8 @@
// MCInstrInfo initialization routine.
OS << "static inline void Init" << Target
- << "MCSubtargetInfo(MCSubtargetInfo *II) {\n";
- OS << " II->InitMCSubtargetInfo(";
+ << "MCSubtargetInfo(MCSubtargetInfo *II, StringRef CPU, StringRef FS) {\n";
+ OS << " II->InitMCSubtargetInfo(CPU, FS, ";
if (NumFeatures)
OS << Target << "FeatureKV, ";
else
@@ -702,7 +705,8 @@
std::string ClassName = Target + "GenSubtargetInfo";
OS << "namespace llvm {\n";
OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n"
- << " explicit " << ClassName << "();\n"
+ << " explicit " << ClassName << "(StringRef TT, StringRef CPU, "
+ << "StringRef FS);\n"
<< "};\n";
OS << "} // End llvm namespace \n";
@@ -712,9 +716,10 @@
OS << "#undef GET_SUBTARGETINFO_CTOR\n";
OS << "namespace llvm {\n";
- OS << ClassName << "::" << ClassName << "()\n"
+ OS << ClassName << "::" << ClassName << "(StringRef TT, StringRef CPU, "
+ << "StringRef FS)\n"
<< " : TargetSubtargetInfo() {\n"
- << " InitMCSubtargetInfo(";
+ << " InitMCSubtargetInfo(CPU, FS, ";
if (NumFeatures)
OS << Target << "FeatureKV, ";
else
Modified: llvm/branches/type-system-rewrite/utils/llvmbuild
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/type-system-rewrite/utils/llvmbuild?rev=134684&r1=134683&r2=134684&view=diff
==============================================================================
--- llvm/branches/type-system-rewrite/utils/llvmbuild (original)
+++ llvm/branches/type-system-rewrite/utils/llvmbuild Thu Jul 7 23:45:15 2011
@@ -200,7 +200,8 @@
# See if we can find source directories.
for src in options.src:
- for component in ["llvm", "llvm-gcc", "gcc", "dragonegg"]:
+ for component in components:
+ component = component.rstrip("2")
compsrc = src + "/" + component
if (not os.path.isdir(compsrc)):
parser.error("'" + compsrc + "' does not exist")
@@ -410,6 +411,8 @@
configure_flags = dict(
llvm=dict(debug=["--prefix=" + self.install_prefix,
"--with-extra-options=-Werror",
+ "--enable-assertions",
+ "--disable-optimized",
"--with-cxx-include-root=" + cxxroot,
"--with-cxx-include-arch=" + cxxarch],
release=["--prefix=" + self.install_prefix,
@@ -419,7 +422,9 @@
"--with-cxx-include-arch=" + cxxarch],
paranoid=["--prefix=" + self.install_prefix,
"--with-extra-options=-Werror",
+ "--enable-assertions",
"--enable-expensive-checks",
+ "--disable-optimized",
"--with-cxx-include-root=" + cxxroot,
"--with-cxx-include-arch=" + cxxarch]),
llvm_gcc=dict(debug=["--prefix=" + self.install_prefix,
@@ -444,6 +449,8 @@
"--enable-languages=c,c++"]),
llvm2=dict(debug=["--prefix=" + self.install_prefix,
"--with-extra-options=-Werror",
+ "--enable-assertions",
+ "--disable-optimized",
"--with-llvmgccdir=" + self.install_prefix + "/bin",
"--with-cxx-include-root=" + cxxroot,
"--with-cxx-include-arch=" + cxxarch],
@@ -455,7 +462,9 @@
"--with-cxx-include-arch=" + cxxarch],
paranoid=["--prefix=" + self.install_prefix,
"--with-extra-options=-Werror",
+ "--enable-assertions",
"--enable-expensive-checks",
+ "--disable-optimized",
"--with-llvmgccdir=" + self.install_prefix + "/bin",
"--with-cxx-include-root=" + cxxroot,
"--with-cxx-include-arch=" + cxxarch]),
@@ -611,7 +620,7 @@
release=dict(),
paranoid=dict()))
- for component in ["llvm", "llvm-gcc", "llvm2", "gcc", "dragonegg"]:
+ for component in components:
comp = component[:]
srcdir = source + "/" + comp.rstrip("2")
@@ -625,7 +634,7 @@
config_args = configure_flags[comp_key][build][:]
config_args.extend(getattr(self.options,
- "extra_" + comp_key
+ "extra_" + comp_key.rstrip("2")
+ "_config_flags").split())
self.logger.info("Configuring " + component + " in " + builddir)
@@ -703,6 +712,8 @@
# Global constants
build_abbrev = dict(debug="dbg", release="opt", paranoid="par")
+#components = ["llvm", "llvm-gcc", "llvm2", "gcc", "dragonegg"]
+components = ["llvm", "llvm2", "gcc", "dragonegg"]
# Parse options
parser = optparse.OptionParser(version="%prog 1.0")
@@ -718,7 +729,10 @@
format='%(name)-13s: %(message)s')
source_abbrev = get_path_abbrevs(set(options.src))
-branch_abbrev = get_path_abbrevs(set(options.branch))
+
+branch_abbrev = None
+if options.branch is not None:
+ branch_abbrev = get_path_abbrevs(set(options.branch))
work_queue = queue.Queue()
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