[llvm-branch-commits] [llvm-branch] r123265 - /llvm/branches/Apple/Hartnell/lib/Target/X86/X86ISelLowering.cpp

[Bill Wendling]

Author: void
Date: Tue Jan 11 13:51:30 2011
New Revision: 123265

URL: http://llvm.org/viewvc/llvm-project?rev=123265&view=rev
Log:
Merge r122206 into Hartnell.

Modified:
    llvm/branches/Apple/Hartnell/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/branches/Apple/Hartnell/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Hartnell/lib/Target/X86/X86ISelLowering.cpp?rev=123265&r1=123264&r2=123265&view=diff
==============================================================================
--- llvm/branches/Apple/Hartnell/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/Apple/Hartnell/lib/Target/X86/X86ISelLowering.cpp Tue Jan 11 13:51:30 2011
@@ -8846,7 +8846,7 @@
 /// if the load addresses are consecutive, non-overlapping, and in the right
 /// order.
 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
-                                     const TargetLowering &TLI) {
+                                     TargetLowering::DAGCombinerInfo &DCI) {
   DebugLoc dl = N->getDebugLoc();
   EVT VT = N->getValueType(0);
   ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
@@ -8854,6 +8854,11 @@
   if (VT.getSizeInBits() != 128)
     return SDValue();
 
+  // Don't create instructions with illegal types after legalize types has run.
+  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
+  if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
+    return SDValue();
+
   SmallVector<SDValue, 16> Elts;
   for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
     Elts.push_back(DAG.getShuffleScalarElt(SVN, i));
@@ -9838,7 +9843,7 @@
   SelectionDAG &DAG = DCI.DAG;
   switch (N->getOpcode()) {
   default: break;
-  case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
+  case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI);
   case ISD::EXTRACT_VECTOR_ELT:
                         return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
   case ISD::SELECT:         return PerformSELECTCombine(N, DAG, Subtarget);