[llvm-branch-commits] [llvm-branch] r114538 - /llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.cpp

[Gabor Greif]

Author: ggreif
Date: Wed Sep 22 03:06:38 2010
New Revision: 114538

URL: http://llvm.org/viewvc/llvm-project?rev=114538&view=rev
Log:
merge r114506 from trunk

Modified:
    llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.cpp   (contents, props changed)

Modified: llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=114538&r1=114537&r2=114538&view=diff
==============================================================================
--- llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.cpp Wed Sep 22 03:06:38 2010
@@ -1461,7 +1461,8 @@
 
   // Check that CPSR isn't set between the comparison instruction and the one we
   // want to change.
-  MachineBasicBlock::const_iterator I = CmpInstr, E = MI;
+  MachineBasicBlock::const_iterator I = CmpInstr, E = MI,
+    B = MI->getParent()->begin();
   --I;
   for (; I != E; --I) {
     const MachineInstr &Instr = *I;
@@ -1475,6 +1476,10 @@
       if (MO.getReg() == ARM::CPSR)
         return false;
     }
+
+    if (I == B)
+      // The 'and' is below the comparison instruction.
+      return false;
   }
 
   // Set the "zero" bit in CPSR.

Propchange: llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.cpp
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Wed Sep 22 03:06:38 2010
@@ -1 +1 @@
-/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp:114430
+/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp:114430,114506