[llvm-branch-commits] [llvm-branch] r114301 - in /llvm/branches/ggreif/arm-peephole: lib/Target/ARM/ARMBaseInstrInfo.cpp test/CodeGen/ARM/arm-and-tst-peephole.ll

[Gabor Greif]

Author: ggreif
Date: Sat Sep 18 16:53:12 2010
New Revision: 114301

URL: http://llvm.org/viewvc/llvm-project?rev=114301&view=rev
Log:
look through COPY and expect the AND just behind
this makes the optimization happen on Thumb-2

Modified:
    llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/branches/ggreif/arm-peephole/test/CodeGen/ARM/arm-and-tst-peephole.ll

Modified: llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=114301&r1=114300&r2=114301&view=diff
==============================================================================
--- llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.cpp Sat Sep 18 16:53:12 2010
@@ -1396,14 +1396,22 @@
   return false;
 }
 
-static bool isSuitableForMask(const MachineInstr &MI, unsigned SrcReg,
+static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
                               int CmpMask) {
-  switch (MI.getOpcode()) {
+  switch (MI->getOpcode()) {
     case ARM::ANDri:
     case ARM::t2ANDri:
-      if (SrcReg == MI.getOperand(1).getReg() &&
-          CmpMask == MI.getOperand(2).getImm())
+      if (SrcReg == MI->getOperand(1).getReg() &&
+          CmpMask == MI->getOperand(2).getImm())
         return true;
+      break;
+    case ARM::COPY: {
+      // walk down
+      const MachineInstr &Copy = *MI;
+      MachineBasicBlock::iterator a(next(MachineBasicBlock::iterator(MI)));
+      MI = a;
+      return isSuitableForMask(MI, Copy.getOperand(0).getReg(), CmpMask);
+    }
   }
 
   return false;
@@ -1428,16 +1436,15 @@
 
   // Masked compares sometimes use the same register as the corresponding 'and'.
   if (CmpMask != ~0) {
-    if (!isSuitableForMask(*MI, SrcReg, CmpMask)) {
+    if (!isSuitableForMask(MI, SrcReg, CmpMask)) {
       MI = 0;
       for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(SrcReg),
            UE = MRI.use_end(); UI != UE; ++UI) {
         if (UI->getParent() != CmpInstr->getParent()) continue;
-        MachineInstr &PotentialAND = *UI;
+        MachineInstr *PotentialAND = &*UI;
         if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask))
           continue;
-        SrcReg = PotentialAND.getOperand(0).getReg();
-        MI = &PotentialAND;
+        MI = PotentialAND;
         break;
       }
       if (!MI) return false;

Modified: llvm/branches/ggreif/arm-peephole/test/CodeGen/ARM/arm-and-tst-peephole.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/arm-peephole/test/CodeGen/ARM/arm-and-tst-peephole.ll?rev=114301&r1=114300&r2=114301&view=diff
==============================================================================
--- llvm/branches/ggreif/arm-peephole/test/CodeGen/ARM/arm-and-tst-peephole.ll (original)
+++ llvm/branches/ggreif/arm-peephole/test/CodeGen/ARM/arm-and-tst-peephole.ll Sat Sep 18 16:53:12 2010
@@ -27,8 +27,7 @@
 ; THUMB-NEXT: tst r4, r5
 ; THUMB-NEXT: beq .LBB0_5
 
-; T2:      and lr, r12, #3
-; T2-NEXT: tst.w r12, #3
+; T2:      ands r12, r12, #3
 ; T2-NEXT: beq .LBB0_5
 
   %and = and i32 %0, 3