[llvm-branch-commits] [llvm-branch] r117527 - in /llvm/branches/wendling/eh: ./ cmake/modules/ docs/ include/llvm/ include/llvm/Analysis/ include/llvm/Support/ lib/Bitcode/Writer/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/MC/ lib/MC/MCParser/ lib/System/ lib/System/Win32/ lib/Target/ARM/ lib/Target/ARM/InstPrinter/ lib/Target/MBlaze/ lib/Target/MBlaze/AsmParser/ lib/Target/MBlaze/Disassembler/ lib/Target/X86/ lib/Target/X86/AsmParser/ lib/Transforms/InstCombine/ lib/VMCore/ test/CodeGen/ARM/ test/CodeGen/X86/ test/MC/ARM/ te...
Bill Wendling
isanbard at gmail.com
Wed Oct 27 21:47:43 PDT 2010
Author: void
Date: Wed Oct 27 23:47:43 2010
New Revision: 117527
URL: http://llvm.org/viewvc/llvm-project?rev=117527&view=rev
Log:
Merge to ToT.
Added:
llvm/branches/wendling/eh/lib/Target/MBlaze/Disassembler/
- copied from r117525, llvm/trunk/lib/Target/MBlaze/Disassembler/
llvm/branches/wendling/eh/lib/Target/MBlaze/Disassembler/CMakeLists.txt
- copied unchanged from r117525, llvm/trunk/lib/Target/MBlaze/Disassembler/CMakeLists.txt
llvm/branches/wendling/eh/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp
- copied unchanged from r117525, llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp
llvm/branches/wendling/eh/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h
- copied unchanged from r117525, llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.h
llvm/branches/wendling/eh/lib/Target/MBlaze/Disassembler/Makefile
- copied unchanged from r117525, llvm/trunk/lib/Target/MBlaze/Disassembler/Makefile
llvm/branches/wendling/eh/test/MC/ARM/neon-abs-encoding.ll
- copied unchanged from r117525, llvm/trunk/test/MC/ARM/neon-abs-encoding.ll
llvm/branches/wendling/eh/test/MC/ARM/neon-bitcount-encoding.ll
- copied unchanged from r117525, llvm/trunk/test/MC/ARM/neon-bitcount-encoding.ll
llvm/branches/wendling/eh/test/MC/ARM/neon-convert-encoding.ll
- copied unchanged from r117525, llvm/trunk/test/MC/ARM/neon-convert-encoding.ll
llvm/branches/wendling/eh/test/MC/ARM/neon-dup-encoding.ll
- copied unchanged from r117525, llvm/trunk/test/MC/ARM/neon-dup-encoding.ll
llvm/branches/wendling/eh/test/MC/ARM/neon-neg-encoding.ll
- copied unchanged from r117525, llvm/trunk/test/MC/ARM/neon-neg-encoding.ll
llvm/branches/wendling/eh/test/MC/ARM/neon-reverse-encoding.ll
- copied unchanged from r117525, llvm/trunk/test/MC/ARM/neon-reverse-encoding.ll
llvm/branches/wendling/eh/test/MC/ARM/neon-shiftaccum-encoding.ll
- copied unchanged from r117525, llvm/trunk/test/MC/ARM/neon-shiftaccum-encoding.ll
llvm/branches/wendling/eh/test/MC/ARM/neon-shuffle-encoding.ll
- copied unchanged from r117525, llvm/trunk/test/MC/ARM/neon-shuffle-encoding.ll
llvm/branches/wendling/eh/test/MC/ARM/neon-table-encoding.ll
- copied unchanged from r117525, llvm/trunk/test/MC/ARM/neon-table-encoding.ll
llvm/branches/wendling/eh/test/MC/ELF/abs.s
- copied unchanged from r117525, llvm/trunk/test/MC/ELF/abs.s
llvm/branches/wendling/eh/test/MC/ELF/invalid-symver.s
- copied unchanged from r117525, llvm/trunk/test/MC/ELF/invalid-symver.s
llvm/branches/wendling/eh/test/MC/ELF/symref.s
- copied unchanged from r117525, llvm/trunk/test/MC/ELF/symref.s
llvm/branches/wendling/eh/test/Transforms/InstCombine/select-crash.ll
- copied unchanged from r117525, llvm/trunk/test/Transforms/InstCombine/select-crash.ll
Modified:
llvm/branches/wendling/eh/ (props changed)
llvm/branches/wendling/eh/cmake/modules/LLVMLibDeps.cmake
llvm/branches/wendling/eh/docs/CodeGenerator.html
llvm/branches/wendling/eh/docs/LangRef.html
llvm/branches/wendling/eh/include/llvm/Analysis/DebugInfo.h
llvm/branches/wendling/eh/include/llvm/Instructions.h
llvm/branches/wendling/eh/include/llvm/Support/ELF.h
llvm/branches/wendling/eh/include/llvm/Support/IRBuilder.h
llvm/branches/wendling/eh/lib/Bitcode/Writer/BitcodeWriter.cpp
llvm/branches/wendling/eh/lib/Bitcode/Writer/ValueEnumerator.cpp
llvm/branches/wendling/eh/lib/CodeGen/MachineVerifier.cpp
llvm/branches/wendling/eh/lib/CodeGen/PrologEpilogInserter.cpp
llvm/branches/wendling/eh/lib/CodeGen/ScheduleDAGInstrs.cpp
llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
llvm/branches/wendling/eh/lib/CodeGen/SplitKit.cpp
llvm/branches/wendling/eh/lib/CodeGen/SplitKit.h
llvm/branches/wendling/eh/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
llvm/branches/wendling/eh/lib/MC/ELFObjectWriter.cpp
llvm/branches/wendling/eh/lib/MC/MCParser/ELFAsmParser.cpp
llvm/branches/wendling/eh/lib/System/Makefile
llvm/branches/wendling/eh/lib/System/Win32/Signals.inc
llvm/branches/wendling/eh/lib/Target/ARM/ARMAsmPrinter.cpp
llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseRegisterInfo.cpp
llvm/branches/wendling/eh/lib/Target/ARM/ARMCodeEmitter.cpp
llvm/branches/wendling/eh/lib/Target/ARM/ARMFastISel.cpp
llvm/branches/wendling/eh/lib/Target/ARM/ARMISelDAGToDAG.cpp
llvm/branches/wendling/eh/lib/Target/ARM/ARMISelLowering.cpp
llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrFormats.td
llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrInfo.cpp
llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrInfo.td
llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrNEON.td
llvm/branches/wendling/eh/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
llvm/branches/wendling/eh/lib/Target/ARM/ARMMCCodeEmitter.cpp
llvm/branches/wendling/eh/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
llvm/branches/wendling/eh/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp
llvm/branches/wendling/eh/lib/Target/MBlaze/CMakeLists.txt
llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeDelaySlotFiller.cpp
llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeInstrFSL.td
llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeInstrFormats.td
llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeInstrInfo.h
llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeInstrInfo.td
llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeMCAsmInfo.cpp
llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeMCAsmInfo.h
llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp
llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeTargetMachine.cpp
llvm/branches/wendling/eh/lib/Target/MBlaze/Makefile
llvm/branches/wendling/eh/lib/Target/MBlaze/TODO
llvm/branches/wendling/eh/lib/Target/X86/AsmParser/X86AsmParser.cpp
llvm/branches/wendling/eh/lib/Target/X86/X86ISelLowering.cpp
llvm/branches/wendling/eh/lib/Target/X86/X86InstrSSE.td
llvm/branches/wendling/eh/lib/Target/X86/X86InstrSystem.td
llvm/branches/wendling/eh/lib/Transforms/InstCombine/InstCombineSelect.cpp
llvm/branches/wendling/eh/lib/VMCore/AsmWriter.cpp
llvm/branches/wendling/eh/test/CodeGen/ARM/shifter_operand.ll
llvm/branches/wendling/eh/test/CodeGen/ARM/vrev.ll
llvm/branches/wendling/eh/test/CodeGen/X86/avx-intrinsics-x86.ll
llvm/branches/wendling/eh/test/CodeGen/X86/avx-intrinsics-x86_64.ll
llvm/branches/wendling/eh/test/MC/ARM/neon-mov-encoding.ll
llvm/branches/wendling/eh/test/MC/ELF/relocation-386.s
llvm/branches/wendling/eh/test/MC/ELF/relocation.s
llvm/branches/wendling/eh/test/MC/ELF/section.s
llvm/branches/wendling/eh/test/MC/X86/x86-32.s
llvm/branches/wendling/eh/utils/TableGen/EDEmitter.cpp
llvm/branches/wendling/eh/utils/TableGen/X86RecognizableInstr.cpp
Propchange: llvm/branches/wendling/eh/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Wed Oct 27 23:47:43 2010
@@ -1,2 +1,2 @@
/llvm/branches/Apple/Pertwee:110850,110961
-/llvm/trunk:104459-117418
+/llvm/trunk:104459-117525
Modified: llvm/branches/wendling/eh/cmake/modules/LLVMLibDeps.cmake
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/cmake/modules/LLVMLibDeps.cmake?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/cmake/modules/LLVMLibDeps.cmake (original)
+++ llvm/branches/wendling/eh/cmake/modules/LLVMLibDeps.cmake Wed Oct 27 23:47:43 2010
@@ -33,9 +33,10 @@
set(MSVC_LIB_DEPS_LLVMMBlazeAsmParser LLVMMBlazeInfo LLVMMC LLVMMCParser LLVMSupport LLVMSystem LLVMTarget)
set(MSVC_LIB_DEPS_LLVMMBlazeAsmPrinter LLVMMC LLVMSupport LLVMSystem)
set(MSVC_LIB_DEPS_LLVMMBlazeCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMBlazeAsmPrinter LLVMMBlazeInfo LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget)
+set(MSVC_LIB_DEPS_LLVMMBlazeDisassembler LLVMMBlazeCodeGen LLVMMBlazeInfo LLVMMC LLVMSupport)
set(MSVC_LIB_DEPS_LLVMMBlazeInfo LLVMSupport)
set(MSVC_LIB_DEPS_LLVMMC LLVMSupport LLVMSystem)
-set(MSVC_LIB_DEPS_LLVMMCDisassembler LLVMARMAsmParser LLVMARMCodeGen LLVMARMDisassembler LLVMARMInfo LLVMAlphaAsmPrinter LLVMAlphaCodeGen LLVMAlphaInfo LLVMBlackfinAsmPrinter LLVMBlackfinCodeGen LLVMBlackfinInfo LLVMCBackend LLVMCBackendInfo LLVMCellSPUAsmPrinter LLVMCellSPUCodeGen LLVMCellSPUInfo LLVMCppBackend LLVMCppBackendInfo LLVMMBlazeAsmParser LLVMMBlazeCodeGen LLVMMBlazeInfo LLVMMC LLVMMCParser LLVMMSP430CodeGen LLVMMSP430Info LLVMMipsAsmPrinter LLVMMipsCodeGen LLVMMipsInfo LLVMPTXAsmPrinter LLVMPTXCodeGen LLVMPTXInfo LLVMPowerPCAsmPrinter LLVMPowerPCCodeGen LLVMPowerPCInfo LLVMSparcAsmPrinter LLVMSparcCodeGen LLVMSparcInfo LLVMSupport LLVMSystem LLVMSystemZAsmPrinter LLVMSystemZCodeGen LLVMSystemZInfo LLVMX86AsmParser LLVMX86CodeGen LLVMX86Disassembler LLVMX86Info LLVMXCoreAsmPrinter LLVMXCoreCodeGen LLVMXCoreInfo)
+set(MSVC_LIB_DEPS_LLVMMCDisassembler LLVMARMAsmParser LLVMARMCodeGen LLVMARMDisassembler LLVMARMInfo LLVMAlphaAsmPrinter LLVMAlphaCodeGen LLVMAlphaInfo LLVMBlackfinAsmPrinter LLVMBlackfinCodeGen LLVMBlackfinInfo LLVMCBackend LLVMCBackendInfo LLVMCellSPUAsmPrinter LLVMCellSPUCodeGen LLVMCellSPUInfo LLVMCppBackend LLVMCppBackendInfo LLVMMBlazeAsmParser LLVMMBlazeCodeGen LLVMMBlazeDisassembler LLVMMBlazeInfo LLVMMC LLVMMCParser LLVMMSP430CodeGen LLVMMSP430Info LLVMMipsAsmPrinter LLVMMipsCodeGen LLVMMipsInfo LLVMPTXAsmPrinter LLVMPTXCodeGen LLVMPTXInfo LLVMPowerPCAsmPrinter LLVMPowerPCCodeGen LLVMPowerPCInfo LLVMSparcAsmPrinter LLVMSparcCodeGen LLVMSparcInfo LLVMSupport LLVMSystem LLVMSystemZAsmPrinter LLVMSystemZCodeGen LLVMSystemZInfo LLVMX86AsmParser LLVMX86CodeGen LLVMX86Disassembler LLVMX86Info LLVMXCoreAsmPrinter LLVMXCoreCodeGen LLVMXCoreInfo)
set(MSVC_LIB_DEPS_LLVMMCParser LLVMMC LLVMSupport LLVMSystem)
set(MSVC_LIB_DEPS_LLVMMSP430AsmPrinter LLVMMC LLVMSupport LLVMSystem)
set(MSVC_LIB_DEPS_LLVMMSP430CodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMMSP430AsmPrinter LLVMMSP430Info LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget)
Modified: llvm/branches/wendling/eh/docs/CodeGenerator.html
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/docs/CodeGenerator.html?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/docs/CodeGenerator.html (original)
+++ llvm/branches/wendling/eh/docs/CodeGenerator.html Wed Oct 27 23:47:43 2010
@@ -2160,6 +2160,10 @@
must include an assembly parser and general inline assembly support for full
inline assembly support in the .o writer.</p>
+<p>Targets that don't support this feature can obviously still write out .o
+files, they just rely on having an external assembler to translate from a .s
+file to a .o file (as is the case for many C compilers).</p>
+
</div>
<!-- _______________________________________________________________________ -->
Modified: llvm/branches/wendling/eh/docs/LangRef.html
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/docs/LangRef.html?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/docs/LangRef.html (original)
+++ llvm/branches/wendling/eh/docs/LangRef.html Wed Oct 27 23:47:43 2010
@@ -2162,8 +2162,8 @@
<p>The string '<tt>undef</tt>' can be used anywhere a constant is expected, and
indicates that the user of the value may receive an unspecified bit-pattern.
- Undefined values may be of any type (other than label or void) and be used
- anywhere a constant is permitted.</p>
+ Undefined values may be of any type (other than '<tt>label</tt>'
+ or '<tt>void</tt>') and be used anywhere a constant is permitted.</p>
<p>Undefined values are useful because they indicate to the compiler that the
program is well defined no matter what value is used. This gives the
@@ -2182,7 +2182,7 @@
</pre>
<p>This is safe because all of the output bits are affected by the undef bits.
-Any output bit can have a zero or one depending on the input bits.</p>
+ Any output bit can have a zero or one depending on the input bits.</p>
<pre class="doc_code">
%A = or %X, undef
@@ -2196,13 +2196,14 @@
</pre>
<p>These logical operations have bits that are not always affected by the input.
-For example, if "%X" has a zero bit, then the output of the 'and' operation will
-always be a zero, no matter what the corresponding bit from the undef is. As
-such, it is unsafe to optimize or assume that the result of the and is undef.
-However, it is safe to assume that all bits of the undef could be 0, and
-optimize the and to 0. Likewise, it is safe to assume that all the bits of
-the undef operand to the or could be set, allowing the or to be folded to
--1.</p>
+ For example, if <tt>%X</tt> has a zero bit, then the output of the
+ '<tt>and</tt>' operation will always be a zero for that bit, no matter what
+ the corresponding bit from the '<tt>undef</tt>' is. As such, it is unsafe to
+ optimize or assume that the result of the '<tt>and</tt>' is '<tt>undef</tt>'.
+ However, it is safe to assume that all bits of the '<tt>undef</tt>' could be
+ 0, and optimize the '<tt>and</tt>' to 0. Likewise, it is safe to assume that
+ all the bits of the '<tt>undef</tt>' operand to the '<tt>or</tt>' could be
+ set, allowing the '<tt>or</tt>' to be folded to -1.</p>
<pre class="doc_code">
%A = select undef, %X, %Y
@@ -2218,13 +2219,14 @@
%C = undef
</pre>
-<p>This set of examples show that undefined select (and conditional branch)
-conditions can go "either way" but they have to come from one of the two
-operands. In the %A example, if %X and %Y were both known to have a clear low
-bit, then %A would have to have a cleared low bit. However, in the %C example,
-the optimizer is allowed to assume that the undef operand could be the same as
-%Y, allowing the whole select to be eliminated.</p>
-
+<p>This set of examples shows that undefined '<tt>select</tt>' (and conditional
+ branch) conditions can go <em>either way</em>, but they have to come from one
+ of the two operands. In the <tt>%A</tt> example, if <tt>%X</tt> and
+ <tt>%Y</tt> were both known to have a clear low bit, then <tt>%A</tt> would
+ have to have a cleared low bit. However, in the <tt>%C</tt> example, the
+ optimizer is allowed to assume that the '<tt>undef</tt>' operand could be the
+ same as <tt>%Y</tt>, allowing the whole '<tt>select</tt>' to be
+ eliminated.</p>
<pre class="doc_code">
%A = xor undef, undef
@@ -2245,16 +2247,17 @@
%F = undef
</pre>
-<p>This example points out that two undef operands are not necessarily the same.
-This can be surprising to people (and also matches C semantics) where they
-assume that "X^X" is always zero, even if X is undef. This isn't true for a
-number of reasons, but the short answer is that an undef "variable" can
-arbitrarily change its value over its "live range". This is true because the
-"variable" doesn't actually <em>have a live range</em>. Instead, the value is
-logically read from arbitrary registers that happen to be around when needed,
-so the value is not necessarily consistent over time. In fact, %A and %C need
-to have the same semantics or the core LLVM "replace all uses with" concept
-would not hold.</p>
+<p>This example points out that two '<tt>undef</tt>' operands are not
+ necessarily the same. This can be surprising to people (and also matches C
+ semantics) where they assume that "<tt>X^X</tt>" is always zero, even
+ if <tt>X</tt> is undefined. This isn't true for a number of reasons, but the
+ short answer is that an '<tt>undef</tt>' "variable" can arbitrarily change
+ its value over its "live range". This is true because the variable doesn't
+ actually <em>have a live range</em>. Instead, the value is logically read
+ from arbitrary registers that happen to be around when needed, so the value
+ is not necessarily consistent over time. In fact, <tt>%A</tt> and <tt>%C</tt>
+ need to have the same semantics or the core LLVM "replace all uses with"
+ concept would not hold.</p>
<pre class="doc_code">
%A = fdiv undef, %X
@@ -2265,17 +2268,17 @@
</pre>
<p>These examples show the crucial difference between an <em>undefined
-value</em> and <em>undefined behavior</em>. An undefined value (like undef) is
-allowed to have an arbitrary bit-pattern. This means that the %A operation
-can be constant folded to undef because the undef could be an SNaN, and fdiv is
-not (currently) defined on SNaN's. However, in the second example, we can make
-a more aggressive assumption: because the undef is allowed to be an arbitrary
-value, we are allowed to assume that it could be zero. Since a divide by zero
-has <em>undefined behavior</em>, we are allowed to assume that the operation
-does not execute at all. This allows us to delete the divide and all code after
-it: since the undefined operation "can't happen", the optimizer can assume that
-it occurs in dead code.
-</p>
+ value</em> and <em>undefined behavior</em>. An undefined value (like
+ '<tt>undef</tt>') is allowed to have an arbitrary bit-pattern. This means that
+ the <tt>%A</tt> operation can be constant folded to '<tt>undef</tt>', because
+ the '<tt>undef</tt>' could be an SNaN, and <tt>fdiv</tt> is not (currently)
+ defined on SNaN's. However, in the second example, we can make a more
+ aggressive assumption: because the <tt>undef</tt> is allowed to be an
+ arbitrary value, we are allowed to assume that it could be zero. Since a
+ divide by zero has <em>undefined behavior</em>, we are allowed to assume that
+ the operation does not execute at all. This allows us to delete the divide and
+ all code after it. Because the undefined operation "can't happen", the
+ optimizer can assume that it occurs in dead code.</p>
<pre class="doc_code">
a: store undef -> %X
@@ -2285,11 +2288,11 @@
b: unreachable
</pre>
-<p>These examples reiterate the fdiv example: a store "of" an undefined value
-can be assumed to not have any effect: we can assume that the value is
-overwritten with bits that happen to match what was already there. However, a
-store "to" an undefined location could clobber arbitrary memory, therefore, it
-has undefined behavior.</p>
+<p>These examples reiterate the <tt>fdiv</tt> example: a store <em>of</em> an
+ undefined value can be assumed to not have any effect; we can assume that the
+ value is overwritten with bits that happen to match what was already there.
+ However, a store <em>to</em> an undefined location could clobber arbitrary
+ memory, therefore, it has undefined behavior.</p>
</div>
@@ -2410,18 +2413,17 @@
the address of the entry block is illegal.</p>
<p>This value only has defined behavior when used as an operand to the
- '<a href="#i_indirectbr"><tt>indirectbr</tt></a>' instruction or for comparisons
- against null. Pointer equality tests between labels addresses is undefined
- behavior - though, again, comparison against null is ok, and no label is
- equal to the null pointer. This may also be passed around as an opaque
- pointer sized value as long as the bits are not inspected. This allows
- <tt>ptrtoint</tt> and arithmetic to be performed on these values so long as
- the original value is reconstituted before the <tt>indirectbr</tt>.</p>
-
-<p>Finally, some targets may provide defined semantics when
- using the value as the operand to an inline assembly, but that is target
- specific.
- </p>
+ '<a href="#i_indirectbr"><tt>indirectbr</tt></a>' instruction, or for
+ comparisons against null. Pointer equality tests between labels addresses
+ results in undefined behavior — though, again, comparison against null
+ is ok, and no label is equal to the null pointer. This may be passed around
+ as an opaque pointer sized value as long as the bits are not inspected. This
+ allows <tt>ptrtoint</tt> and arithmetic to be performed on these values so
+ long as the original value is reconstituted before the <tt>indirectbr</tt>
+ instruction.</p>
+
+<p>Finally, some targets may provide defined semantics when using the value as
+ the operand to an inline assembly, but that is target specific.</p>
</div>
@@ -2436,7 +2438,7 @@
to be used as constants. Constant expressions may be of
any <a href="#t_firstclass">first class</a> type and may involve any LLVM
operation that does not have side effects (e.g. load and call are not
- supported). The following is the syntax for constant expressions:</p>
+ supported). The following is the syntax for constant expressions:</p>
<dl>
<dt><b><tt>trunc (CST to TYPE)</tt></b></dt>
@@ -7682,7 +7684,7 @@
the <tt>AllocaInst</tt> stack slot to be before local variables on the
stack. This is to ensure that if a local variable on the stack is
overwritten, it will destroy the value of the guard. When the function exits,
- the guard on the stack is checked against the original guard. If they're
+ the guard on the stack is checked against the original guard. If they are
different, then the program aborts by calling the <tt>__stack_chk_fail()</tt>
function.</p>
@@ -7702,25 +7704,24 @@
</pre>
<h5>Overview:</h5>
-<p>The <tt>llvm.objectsize</tt> intrinsic is designed to provide information
- to the optimizers to discover at compile time either a) when an
- operation like memcpy will either overflow a buffer that corresponds to
- an object, or b) to determine that a runtime check for overflow isn't
- necessary. An object in this context means an allocation of a
- specific class, structure, array, or other object.</p>
+<p>The <tt>llvm.objectsize</tt> intrinsic is designed to provide information to
+ the optimizers to determine at compile time whether a) an operation (like
+ memcpy) will overflow a buffer that corresponds to an object, or b) that a
+ runtime check for overflow isn't necessary. An object in this context means
+ an allocation of a specific class, structure, array, or other object.</p>
<h5>Arguments:</h5>
-<p>The <tt>llvm.objectsize</tt> intrinsic takes two arguments. The first
+<p>The <tt>llvm.objectsize</tt> intrinsic takes two arguments. The first
argument is a pointer to or into the <tt>object</tt>. The second argument
- is a boolean 0 or 1. This argument determines whether you want the
- maximum (0) or minimum (1) bytes remaining. This needs to be a literal 0 or
+ is a boolean 0 or 1. This argument determines whether you want the
+ maximum (0) or minimum (1) bytes remaining. This needs to be a literal 0 or
1, variables are not allowed.</p>
<h5>Semantics:</h5>
<p>The <tt>llvm.objectsize</tt> intrinsic is lowered to either a constant
- representing the size of the object concerned or <tt>i32/i64 -1 or 0</tt>
- (depending on the <tt>type</tt> argument if the size cannot be determined
- at compile time.</p>
+ representing the size of the object concerned, or <tt>i32/i64 -1 or 0</tt>,
+ depending on the <tt>type</tt> argument, if the size cannot be determined at
+ compile time.</p>
</div>
Modified: llvm/branches/wendling/eh/include/llvm/Analysis/DebugInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Analysis/DebugInfo.h?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Analysis/DebugInfo.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Analysis/DebugInfo.h Wed Oct 27 23:47:43 2010
@@ -734,7 +734,7 @@
bool isDefinition,
unsigned VK = 0,
unsigned VIndex = 0,
- DIType = DIType(),
+ DIType ContainingType = DIType(),
unsigned Flags = 0,
bool isOptimized = false,
Function *Fn = 0);
Modified: llvm/branches/wendling/eh/include/llvm/Instructions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Instructions.h?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Instructions.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Instructions.h Wed Oct 27 23:47:43 2010
@@ -43,7 +43,7 @@
public:
explicit AllocaInst(const Type *Ty, Value *ArraySize = 0,
const Twine &Name = "", Instruction *InsertBefore = 0);
- AllocaInst(const Type *Ty, Value *ArraySize,
+ AllocaInst(const Type *Ty, Value *ArraySize,
const Twine &Name, BasicBlock *InsertAtEnd);
AllocaInst(const Type *Ty, const Twine &Name, Instruction *InsertBefore = 0);
@@ -166,8 +166,8 @@
unsigned getPointerAddressSpace() const {
return cast<PointerType>(getPointerOperand()->getType())->getAddressSpace();
}
-
-
+
+
// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const LoadInst *) { return true; }
static inline bool classof(const Instruction *I) {
@@ -237,7 +237,7 @@
Value *getValueOperand() { return getOperand(0); }
const Value *getValueOperand() const { return getOperand(0); }
-
+
Value *getPointerOperand() { return getOperand(1); }
const Value *getPointerOperand() const { return getOperand(1); }
static unsigned getPointerOperandIndex() { return 1U; }
@@ -245,7 +245,7 @@
unsigned getPointerAddressSpace() const {
return cast<PointerType>(getPointerOperand()->getType())->getAddressSpace();
}
-
+
// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const StoreInst *) { return true; }
static inline bool classof(const Instruction *I) {
@@ -289,8 +289,10 @@
const Twine &NameStr);
void init(Value *Ptr, Value *Idx, const Twine &NameStr);
- template<typename InputIterator>
- void init(Value *Ptr, InputIterator IdxBegin, InputIterator IdxEnd,
+ template<typename RandomAccessIterator>
+ void init(Value *Ptr,
+ RandomAccessIterator IdxBegin,
+ RandomAccessIterator IdxEnd,
const Twine &NameStr,
// This argument ensures that we have an iterator we can
// do arithmetic on in constant time
@@ -313,10 +315,10 @@
/// Null is returned if the indices are invalid for the specified
/// pointer type.
///
- template<typename InputIterator>
+ template<typename RandomAccessIterator>
static const Type *getIndexedType(const Type *Ptr,
- InputIterator IdxBegin,
- InputIterator IdxEnd,
+ RandomAccessIterator IdxBegin,
+ RandomAccessIterator IdxEnd,
// This argument ensures that we
// have an iterator we can do
// arithmetic on in constant time
@@ -331,18 +333,19 @@
}
/// Constructors - Create a getelementptr instruction with a base pointer an
- /// list of indices. The first ctor can optionally insert before an existing
+ /// list of indices. The first ctor can optionally insert before an existing
/// instruction, the second appends the new instruction to the specified
/// BasicBlock.
- template<typename InputIterator>
- inline GetElementPtrInst(Value *Ptr, InputIterator IdxBegin,
- InputIterator IdxEnd,
+ template<typename RandomAccessIterator>
+ inline GetElementPtrInst(Value *Ptr, RandomAccessIterator IdxBegin,
+ RandomAccessIterator IdxEnd,
unsigned Values,
const Twine &NameStr,
Instruction *InsertBefore);
- template<typename InputIterator>
+ template<typename RandomAccessIterator>
inline GetElementPtrInst(Value *Ptr,
- InputIterator IdxBegin, InputIterator IdxEnd,
+ RandomAccessIterator IdxBegin,
+ RandomAccessIterator IdxEnd,
unsigned Values,
const Twine &NameStr, BasicBlock *InsertAtEnd);
@@ -355,23 +358,24 @@
protected:
virtual GetElementPtrInst *clone_impl() const;
public:
- template<typename InputIterator>
- static GetElementPtrInst *Create(Value *Ptr, InputIterator IdxBegin,
- InputIterator IdxEnd,
+ template<typename RandomAccessIterator>
+ static GetElementPtrInst *Create(Value *Ptr, RandomAccessIterator IdxBegin,
+ RandomAccessIterator IdxEnd,
const Twine &NameStr = "",
Instruction *InsertBefore = 0) {
- typename std::iterator_traits<InputIterator>::difference_type Values =
- 1 + std::distance(IdxBegin, IdxEnd);
+ typename std::iterator_traits<RandomAccessIterator>::difference_type
+ Values = 1 + std::distance(IdxBegin, IdxEnd);
return new(Values)
GetElementPtrInst(Ptr, IdxBegin, IdxEnd, Values, NameStr, InsertBefore);
}
- template<typename InputIterator>
+ template<typename RandomAccessIterator>
static GetElementPtrInst *Create(Value *Ptr,
- InputIterator IdxBegin, InputIterator IdxEnd,
+ RandomAccessIterator IdxBegin,
+ RandomAccessIterator IdxEnd,
const Twine &NameStr,
BasicBlock *InsertAtEnd) {
- typename std::iterator_traits<InputIterator>::difference_type Values =
- 1 + std::distance(IdxBegin, IdxEnd);
+ typename std::iterator_traits<RandomAccessIterator>::difference_type
+ Values = 1 + std::distance(IdxBegin, IdxEnd);
return new(Values)
GetElementPtrInst(Ptr, IdxBegin, IdxEnd, Values, NameStr, InsertAtEnd);
}
@@ -391,9 +395,10 @@
/// Create an "inbounds" getelementptr. See the documentation for the
/// "inbounds" flag in LangRef.html for details.
- template<typename InputIterator>
- static GetElementPtrInst *CreateInBounds(Value *Ptr, InputIterator IdxBegin,
- InputIterator IdxEnd,
+ template<typename RandomAccessIterator>
+ static GetElementPtrInst *CreateInBounds(Value *Ptr,
+ RandomAccessIterator IdxBegin,
+ RandomAccessIterator IdxEnd,
const Twine &NameStr = "",
Instruction *InsertBefore = 0) {
GetElementPtrInst *GEP = Create(Ptr, IdxBegin, IdxEnd,
@@ -401,10 +406,10 @@
GEP->setIsInBounds(true);
return GEP;
}
- template<typename InputIterator>
+ template<typename RandomAccessIterator>
static GetElementPtrInst *CreateInBounds(Value *Ptr,
- InputIterator IdxBegin,
- InputIterator IdxEnd,
+ RandomAccessIterator IdxBegin,
+ RandomAccessIterator IdxEnd,
const Twine &NameStr,
BasicBlock *InsertAtEnd) {
GetElementPtrInst *GEP = Create(Ptr, IdxBegin, IdxEnd,
@@ -441,12 +446,12 @@
/// Null is returned if the indices are invalid for the specified
/// pointer type.
///
- template<typename InputIterator>
+ template<typename RandomAccessIterator>
static const Type *getIndexedType(const Type *Ptr,
- InputIterator IdxBegin,
- InputIterator IdxEnd) {
+ RandomAccessIterator IdxBegin,
+ RandomAccessIterator IdxEnd) {
return getIndexedType(Ptr, IdxBegin, IdxEnd,
- typename std::iterator_traits<InputIterator>::
+ typename std::iterator_traits<RandomAccessIterator>::
iterator_category());
}
@@ -472,7 +477,7 @@
static unsigned getPointerOperandIndex() {
return 0U; // get index for modifying correct operand
}
-
+
unsigned getPointerAddressSpace() const {
return cast<PointerType>(getType())->getAddressSpace();
}
@@ -523,10 +528,10 @@
struct OperandTraits<GetElementPtrInst> : public VariadicOperandTraits<1> {
};
-template<typename InputIterator>
+template<typename RandomAccessIterator>
GetElementPtrInst::GetElementPtrInst(Value *Ptr,
- InputIterator IdxBegin,
- InputIterator IdxEnd,
+ RandomAccessIterator IdxBegin,
+ RandomAccessIterator IdxEnd,
unsigned Values,
const Twine &NameStr,
Instruction *InsertBefore)
@@ -539,12 +544,13 @@
OperandTraits<GetElementPtrInst>::op_end(this) - Values,
Values, InsertBefore) {
init(Ptr, IdxBegin, IdxEnd, NameStr,
- typename std::iterator_traits<InputIterator>::iterator_category());
+ typename std::iterator_traits<RandomAccessIterator>
+ ::iterator_category());
}
-template<typename InputIterator>
+template<typename RandomAccessIterator>
GetElementPtrInst::GetElementPtrInst(Value *Ptr,
- InputIterator IdxBegin,
- InputIterator IdxEnd,
+ RandomAccessIterator IdxBegin,
+ RandomAccessIterator IdxEnd,
unsigned Values,
const Twine &NameStr,
BasicBlock *InsertAtEnd)
@@ -557,7 +563,8 @@
OperandTraits<GetElementPtrInst>::op_end(this) - Values,
Values, InsertAtEnd) {
init(Ptr, IdxBegin, IdxEnd, NameStr,
- typename std::iterator_traits<InputIterator>::iterator_category());
+ typename std::iterator_traits<RandomAccessIterator>
+ ::iterator_category());
}
@@ -575,7 +582,7 @@
class ICmpInst: public CmpInst {
protected:
/// @brief Clone an indentical ICmpInst
- virtual ICmpInst *clone_impl() const;
+ virtual ICmpInst *clone_impl() const;
public:
/// @brief Constructor with insert-before-instruction semantics.
ICmpInst(
@@ -746,7 +753,7 @@
assert(getOperand(0)->getType()->isFPOrFPVectorTy() &&
"Invalid operand types for FCmp instruction");
}
-
+
/// @brief Constructor with insert-at-end semantics.
FCmpInst(
BasicBlock &InsertAtEnd, ///< Block to insert into.
@@ -838,8 +845,10 @@
void init(Value *Func, Value *Actual);
void init(Value *Func);
- template<typename InputIterator>
- void init(Value *Func, InputIterator ArgBegin, InputIterator ArgEnd,
+ template<typename RandomAccessIterator>
+ void init(Value *Func,
+ RandomAccessIterator ArgBegin,
+ RandomAccessIterator ArgEnd,
const Twine &NameStr,
// This argument ensures that we have an iterator we can
// do arithmetic on in constant time
@@ -851,24 +860,26 @@
setName(NameStr);
}
- /// Construct a CallInst given a range of arguments. InputIterator
+ /// Construct a CallInst given a range of arguments. RandomAccessIterator
/// must be a random-access iterator pointing to contiguous storage
- /// (e.g. a std::vector<>::iterator). Checks are made for
+ /// (e.g. a std::vector<>::iterator). Checks are made for
/// random-accessness but not for contiguous storage as that would
/// incur runtime overhead.
/// @brief Construct a CallInst from a range of arguments
- template<typename InputIterator>
- CallInst(Value *Func, InputIterator ArgBegin, InputIterator ArgEnd,
+ template<typename RandomAccessIterator>
+ CallInst(Value *Func,
+ RandomAccessIterator ArgBegin, RandomAccessIterator ArgEnd,
const Twine &NameStr, Instruction *InsertBefore);
- /// Construct a CallInst given a range of arguments. InputIterator
+ /// Construct a CallInst given a range of arguments. RandomAccessIterator
/// must be a random-access iterator pointing to contiguous storage
/// (e.g. a std::vector<>::iterator). Checks are made for
/// random-accessness but not for contiguous storage as that would
/// incur runtime overhead.
/// @brief Construct a CallInst from a range of arguments
- template<typename InputIterator>
- inline CallInst(Value *Func, InputIterator ArgBegin, InputIterator ArgEnd,
+ template<typename RandomAccessIterator>
+ inline CallInst(Value *Func,
+ RandomAccessIterator ArgBegin, RandomAccessIterator ArgEnd,
const Twine &NameStr, BasicBlock *InsertAtEnd);
CallInst(Value *F, Value *Actual, const Twine &NameStr,
@@ -881,17 +892,19 @@
protected:
virtual CallInst *clone_impl() const;
public:
- template<typename InputIterator>
+ template<typename RandomAccessIterator>
static CallInst *Create(Value *Func,
- InputIterator ArgBegin, InputIterator ArgEnd,
+ RandomAccessIterator ArgBegin,
+ RandomAccessIterator ArgEnd,
const Twine &NameStr = "",
Instruction *InsertBefore = 0) {
return new(unsigned(ArgEnd - ArgBegin + 1))
CallInst(Func, ArgBegin, ArgEnd, NameStr, InsertBefore);
}
- template<typename InputIterator>
+ template<typename RandomAccessIterator>
static CallInst *Create(Value *Func,
- InputIterator ArgBegin, InputIterator ArgEnd,
+ RandomAccessIterator ArgBegin,
+ RandomAccessIterator ArgEnd,
const Twine &NameStr, BasicBlock *InsertAtEnd) {
return new(unsigned(ArgEnd - ArgBegin + 1))
CallInst(Func, ArgBegin, ArgEnd, NameStr, InsertAtEnd);
@@ -984,7 +997,7 @@
unsigned getParamAlignment(unsigned i) const {
return AttributeList.getParamAlignment(i);
}
-
+
/// @brief Return true if the call should not be inlined.
bool isNoInline() const { return paramHasAttr(~0, Attribute::NoInline); }
void setIsNoInline(bool Value = true) {
@@ -1052,7 +1065,7 @@
void setCalledFunction(Value* Fn) {
Op<-1>() = Fn;
}
-
+
/// isInlineAsm - Check if this call is an inline asm statement.
bool isInlineAsm() const {
return isa<InlineAsm>(Op<-1>());
@@ -1078,8 +1091,9 @@
struct OperandTraits<CallInst> : public VariadicOperandTraits<1> {
};
-template<typename InputIterator>
-CallInst::CallInst(Value *Func, InputIterator ArgBegin, InputIterator ArgEnd,
+template<typename RandomAccessIterator>
+CallInst::CallInst(Value *Func,
+ RandomAccessIterator ArgBegin, RandomAccessIterator ArgEnd,
const Twine &NameStr, BasicBlock *InsertAtEnd)
: Instruction(cast<FunctionType>(cast<PointerType>(Func->getType())
->getElementType())->getReturnType(),
@@ -1087,11 +1101,13 @@
OperandTraits<CallInst>::op_end(this) - (ArgEnd - ArgBegin + 1),
unsigned(ArgEnd - ArgBegin + 1), InsertAtEnd) {
init(Func, ArgBegin, ArgEnd, NameStr,
- typename std::iterator_traits<InputIterator>::iterator_category());
+ typename std::iterator_traits<RandomAccessIterator>
+ ::iterator_category());
}
-template<typename InputIterator>
-CallInst::CallInst(Value *Func, InputIterator ArgBegin, InputIterator ArgEnd,
+template<typename RandomAccessIterator>
+CallInst::CallInst(Value *Func,
+ RandomAccessIterator ArgBegin, RandomAccessIterator ArgEnd,
const Twine &NameStr, Instruction *InsertBefore)
: Instruction(cast<FunctionType>(cast<PointerType>(Func->getType())
->getElementType())->getReturnType(),
@@ -1099,7 +1115,8 @@
OperandTraits<CallInst>::op_end(this) - (ArgEnd - ArgBegin + 1),
unsigned(ArgEnd - ArgBegin + 1), InsertBefore) {
init(Func, ArgBegin, ArgEnd, NameStr,
- typename std::iterator_traits<InputIterator>::iterator_category());
+ typename std::iterator_traits<RandomAccessIterator>
+ ::iterator_category());
}
@@ -1156,7 +1173,7 @@
Value *getCondition() { return Op<0>(); }
Value *getTrueValue() { return Op<1>(); }
Value *getFalseValue() { return Op<2>(); }
-
+
/// areInvalidOperands - Return a string if the specified operands are invalid
/// for a select operation, otherwise return null.
static const char *areInvalidOperands(Value *Cond, Value *True, Value *False);
@@ -1256,12 +1273,12 @@
Value *getIndexOperand() { return Op<1>(); }
const Value *getVectorOperand() const { return Op<0>(); }
const Value *getIndexOperand() const { return Op<1>(); }
-
+
const VectorType *getVectorOperandType() const {
return reinterpret_cast<const VectorType*>(getVectorOperand()->getType());
}
-
-
+
+
/// Transparently provide more efficient getOperand methods.
DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
@@ -1411,8 +1428,9 @@
const Twine &NameStr);
void init(unsigned Idx, const Twine &NameStr);
- template<typename InputIterator>
- void init(InputIterator IdxBegin, InputIterator IdxEnd,
+ template<typename RandomAccessIterator>
+ void init(RandomAccessIterator IdxBegin,
+ RandomAccessIterator IdxEnd,
const Twine &NameStr,
// This argument ensures that we have an iterator we can
// do arithmetic on in constant time
@@ -1439,10 +1457,10 @@
static const Type *getIndexedType(const Type *Agg,
const unsigned *Idx, unsigned NumIdx);
- template<typename InputIterator>
+ template<typename RandomAccessIterator>
static const Type *getIndexedType(const Type *Ptr,
- InputIterator IdxBegin,
- InputIterator IdxEnd,
+ RandomAccessIterator IdxBegin,
+ RandomAccessIterator IdxEnd,
// This argument ensures that we
// have an iterator we can do
// arithmetic on in constant time
@@ -1460,14 +1478,16 @@
/// value and a list of indices. The first ctor can optionally insert before
/// an existing instruction, the second appends the new instruction to the
/// specified BasicBlock.
- template<typename InputIterator>
- inline ExtractValueInst(Value *Agg, InputIterator IdxBegin,
- InputIterator IdxEnd,
+ template<typename RandomAccessIterator>
+ inline ExtractValueInst(Value *Agg,
+ RandomAccessIterator IdxBegin,
+ RandomAccessIterator IdxEnd,
const Twine &NameStr,
Instruction *InsertBefore);
- template<typename InputIterator>
+ template<typename RandomAccessIterator>
inline ExtractValueInst(Value *Agg,
- InputIterator IdxBegin, InputIterator IdxEnd,
+ RandomAccessIterator IdxBegin,
+ RandomAccessIterator IdxEnd,
const Twine &NameStr, BasicBlock *InsertAtEnd);
// allocate space for exactly one operand
@@ -1478,17 +1498,19 @@
virtual ExtractValueInst *clone_impl() const;
public:
- template<typename InputIterator>
- static ExtractValueInst *Create(Value *Agg, InputIterator IdxBegin,
- InputIterator IdxEnd,
+ template<typename RandomAccessIterator>
+ static ExtractValueInst *Create(Value *Agg,
+ RandomAccessIterator IdxBegin,
+ RandomAccessIterator IdxEnd,
const Twine &NameStr = "",
Instruction *InsertBefore = 0) {
return new
ExtractValueInst(Agg, IdxBegin, IdxEnd, NameStr, InsertBefore);
}
- template<typename InputIterator>
+ template<typename RandomAccessIterator>
static ExtractValueInst *Create(Value *Agg,
- InputIterator IdxBegin, InputIterator IdxEnd,
+ RandomAccessIterator IdxBegin,
+ RandomAccessIterator IdxEnd,
const Twine &NameStr,
BasicBlock *InsertAtEnd) {
return new ExtractValueInst(Agg, IdxBegin, IdxEnd, NameStr, InsertAtEnd);
@@ -1516,12 +1538,12 @@
/// Null is returned if the indices are invalid for the specified
/// pointer type.
///
- template<typename InputIterator>
+ template<typename RandomAccessIterator>
static const Type *getIndexedType(const Type *Ptr,
- InputIterator IdxBegin,
- InputIterator IdxEnd) {
+ RandomAccessIterator IdxBegin,
+ RandomAccessIterator IdxEnd) {
return getIndexedType(Ptr, IdxBegin, IdxEnd,
- typename std::iterator_traits<InputIterator>::
+ typename std::iterator_traits<RandomAccessIterator>::
iterator_category());
}
static const Type *getIndexedType(const Type *Ptr, unsigned Idx);
@@ -1558,29 +1580,31 @@
}
};
-template<typename InputIterator>
+template<typename RandomAccessIterator>
ExtractValueInst::ExtractValueInst(Value *Agg,
- InputIterator IdxBegin,
- InputIterator IdxEnd,
+ RandomAccessIterator IdxBegin,
+ RandomAccessIterator IdxEnd,
const Twine &NameStr,
Instruction *InsertBefore)
: UnaryInstruction(checkType(getIndexedType(Agg->getType(),
IdxBegin, IdxEnd)),
ExtractValue, Agg, InsertBefore) {
init(IdxBegin, IdxEnd, NameStr,
- typename std::iterator_traits<InputIterator>::iterator_category());
+ typename std::iterator_traits<RandomAccessIterator>
+ ::iterator_category());
}
-template<typename InputIterator>
+template<typename RandomAccessIterator>
ExtractValueInst::ExtractValueInst(Value *Agg,
- InputIterator IdxBegin,
- InputIterator IdxEnd,
+ RandomAccessIterator IdxBegin,
+ RandomAccessIterator IdxEnd,
const Twine &NameStr,
BasicBlock *InsertAtEnd)
: UnaryInstruction(checkType(getIndexedType(Agg->getType(),
IdxBegin, IdxEnd)),
ExtractValue, Agg, InsertAtEnd) {
init(IdxBegin, IdxEnd, NameStr,
- typename std::iterator_traits<InputIterator>::iterator_category());
+ typename std::iterator_traits<RandomAccessIterator>
+ ::iterator_category());
}
@@ -1600,9 +1624,9 @@
const Twine &NameStr);
void init(Value *Agg, Value *Val, unsigned Idx, const Twine &NameStr);
- template<typename InputIterator>
+ template<typename RandomAccessIterator>
void init(Value *Agg, Value *Val,
- InputIterator IdxBegin, InputIterator IdxEnd,
+ RandomAccessIterator IdxBegin, RandomAccessIterator IdxEnd,
const Twine &NameStr,
// This argument ensures that we have an iterator we can
// do arithmetic on in constant time
@@ -1624,14 +1648,16 @@
/// value, a value to insert, and a list of indices. The first ctor can
/// optionally insert before an existing instruction, the second appends
/// the new instruction to the specified BasicBlock.
- template<typename InputIterator>
- inline InsertValueInst(Value *Agg, Value *Val, InputIterator IdxBegin,
- InputIterator IdxEnd,
+ template<typename RandomAccessIterator>
+ inline InsertValueInst(Value *Agg, Value *Val,
+ RandomAccessIterator IdxBegin,
+ RandomAccessIterator IdxEnd,
const Twine &NameStr,
Instruction *InsertBefore);
- template<typename InputIterator>
+ template<typename RandomAccessIterator>
inline InsertValueInst(Value *Agg, Value *Val,
- InputIterator IdxBegin, InputIterator IdxEnd,
+ RandomAccessIterator IdxBegin,
+ RandomAccessIterator IdxEnd,
const Twine &NameStr, BasicBlock *InsertAtEnd);
/// Constructors - These two constructors are convenience methods because one
@@ -1649,17 +1675,19 @@
return User::operator new(s, 2);
}
- template<typename InputIterator>
- static InsertValueInst *Create(Value *Agg, Value *Val, InputIterator IdxBegin,
- InputIterator IdxEnd,
+ template<typename RandomAccessIterator>
+ static InsertValueInst *Create(Value *Agg, Value *Val,
+ RandomAccessIterator IdxBegin,
+ RandomAccessIterator IdxEnd,
const Twine &NameStr = "",
Instruction *InsertBefore = 0) {
return new InsertValueInst(Agg, Val, IdxBegin, IdxEnd,
NameStr, InsertBefore);
}
- template<typename InputIterator>
+ template<typename RandomAccessIterator>
static InsertValueInst *Create(Value *Agg, Value *Val,
- InputIterator IdxBegin, InputIterator IdxEnd,
+ RandomAccessIterator IdxBegin,
+ RandomAccessIterator IdxEnd,
const Twine &NameStr,
BasicBlock *InsertAtEnd) {
return new InsertValueInst(Agg, Val, IdxBegin, IdxEnd,
@@ -1729,31 +1757,33 @@
struct OperandTraits<InsertValueInst> : public FixedNumOperandTraits<2> {
};
-template<typename InputIterator>
+template<typename RandomAccessIterator>
InsertValueInst::InsertValueInst(Value *Agg,
Value *Val,
- InputIterator IdxBegin,
- InputIterator IdxEnd,
+ RandomAccessIterator IdxBegin,
+ RandomAccessIterator IdxEnd,
const Twine &NameStr,
Instruction *InsertBefore)
: Instruction(Agg->getType(), InsertValue,
OperandTraits<InsertValueInst>::op_begin(this),
2, InsertBefore) {
init(Agg, Val, IdxBegin, IdxEnd, NameStr,
- typename std::iterator_traits<InputIterator>::iterator_category());
+ typename std::iterator_traits<RandomAccessIterator>
+ ::iterator_category());
}
-template<typename InputIterator>
+template<typename RandomAccessIterator>
InsertValueInst::InsertValueInst(Value *Agg,
Value *Val,
- InputIterator IdxBegin,
- InputIterator IdxEnd,
+ RandomAccessIterator IdxBegin,
+ RandomAccessIterator IdxEnd,
const Twine &NameStr,
BasicBlock *InsertAtEnd)
: Instruction(Agg->getType(), InsertValue,
OperandTraits<InsertValueInst>::op_begin(this),
2, InsertAtEnd) {
init(Agg, Val, IdxBegin, IdxEnd, NameStr,
- typename std::iterator_traits<InputIterator>::iterator_category());
+ typename std::iterator_traits<RandomAccessIterator>
+ ::iterator_category());
}
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(InsertValueInst, Value)
@@ -1839,7 +1869,7 @@
BasicBlock *getIncomingBlock(unsigned i) const {
return cast<BasicBlock>(getOperand(i*2+1));
}
-
+
/// getIncomingBlock - Return incoming basic block corresponding
/// to an operand of the PHI.
///
@@ -1847,7 +1877,7 @@
assert(this == U.getUser() && "Iterator doesn't point to PHI's Uses?");
return cast<BasicBlock>((&U + 1)->get());
}
-
+
/// getIncomingBlock - Return incoming basic block corresponding
/// to value use iterator.
///
@@ -1855,8 +1885,8 @@
BasicBlock *getIncomingBlock(value_use_iterator<U> I) const {
return getIncomingBlock(I.getUse());
}
-
-
+
+
void setIncomingBlock(unsigned i, BasicBlock *BB) {
setOperand(i*2+1, (Value*)BB);
}
@@ -2300,7 +2330,7 @@
/// here to make memory allocation more efficient. This constructor can also
/// autoinsert before another instruction.
IndirectBrInst(Value *Address, unsigned NumDests, Instruction *InsertBefore);
-
+
/// IndirectBrInst ctor - Create a new indirectbr instruction, specifying an
/// Address to jump to. The number of expected destinations can be specified
/// here to make memory allocation more efficient. This constructor also
@@ -2318,32 +2348,32 @@
return new IndirectBrInst(Address, NumDests, InsertAtEnd);
}
~IndirectBrInst();
-
+
/// Provide fast operand accessors.
DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
-
+
// Accessor Methods for IndirectBrInst instruction.
Value *getAddress() { return getOperand(0); }
const Value *getAddress() const { return getOperand(0); }
void setAddress(Value *V) { setOperand(0, V); }
-
-
+
+
/// getNumDestinations - return the number of possible destinations in this
/// indirectbr instruction.
unsigned getNumDestinations() const { return getNumOperands()-1; }
-
+
/// getDestination - Return the specified destination.
BasicBlock *getDestination(unsigned i) { return getSuccessor(i); }
const BasicBlock *getDestination(unsigned i) const { return getSuccessor(i); }
-
+
/// addDestination - Add a destination.
///
void addDestination(BasicBlock *Dest);
-
+
/// removeDestination - This method removes the specified successor from the
/// indirectbr instruction.
void removeDestination(unsigned i);
-
+
unsigned getNumSuccessors() const { return getNumOperands()-1; }
BasicBlock *getSuccessor(unsigned i) const {
return cast<BasicBlock>(getOperand(i+1));
@@ -2351,7 +2381,7 @@
void setSuccessor(unsigned i, BasicBlock *NewSucc) {
setOperand(i+1, (Value*)NewSucc);
}
-
+
// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const IndirectBrInst *) { return true; }
static inline bool classof(const Instruction *I) {
@@ -2371,8 +2401,8 @@
};
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(IndirectBrInst, Value)
-
-
+
+
//===----------------------------------------------------------------------===//
// InvokeInst Class
//===----------------------------------------------------------------------===//
@@ -2393,10 +2423,11 @@
Value *PersFn, Value *CatchAllTy, BasicBlock *CatchAll,
unsigned NumCatches, Value * const *Args, unsigned NumArgs);
- template<typename InputIterator>
+ template<typename RandomAccessIterator>
void init(Value *Func, BasicBlock *IfNormal, BasicBlock *IfException,
Value *PersFn, Value *CatchAllTy, BasicBlock *CatchAll,
- unsigned NumCatches, InputIterator ArgBegin, InputIterator ArgEnd,
+ unsigned NumCatches,
+ RandomAccessIterator ArgBegin, RandomAccessIterator ArgEnd,
const Twine &NameStr,
// This argument ensures that we have an iterator we can
// do arithmetic on in constant time
@@ -2410,42 +2441,45 @@
}
/// Construct an InvokeInst given a range of arguments.
- /// InputIterator must be a random-access iterator pointing to
+ /// RandomAccessIterator must be a random-access iterator pointing to
/// contiguous storage (e.g. a std::vector<>::iterator). Checks are
/// made for random-accessness but not for contiguous storage as
/// that would incur runtime overhead.
///
/// @brief Construct an InvokeInst from a range of arguments
- template<typename InputIterator>
+ template<typename RandomAccessIterator>
inline InvokeInst(Value *Func, BasicBlock *IfNormal, BasicBlock *IfException,
Value *PersFn, Value *CatchAllTy, BasicBlock *CatchAll,
- unsigned NumCatches, InputIterator ArgBegin,
- InputIterator ArgEnd, unsigned Values,
+ unsigned NumCatches,
+ RandomAccessIterator ArgBegin, RandomAccessIterator ArgEnd,
+ unsigned Values,
const Twine &NameStr, Instruction *InsertBefore);
/// Construct an InvokeInst given a range of arguments.
- /// InputIterator must be a random-access iterator pointing to
+ /// RandomAccessIterator must be a random-access iterator pointing to
/// contiguous storage (e.g. a std::vector<>::iterator). Checks are
/// made for random-accessness but not for contiguous storage as
/// that would incur runtime overhead.
///
/// @brief Construct an InvokeInst from a range of arguments
- template<typename InputIterator>
+ template<typename RandomAccessIterator>
inline InvokeInst(Value *Func, BasicBlock *IfNormal, BasicBlock *IfException,
Value *PersFn, Value *CatchAllTy, BasicBlock *CatchAll,
- unsigned NumCatches, InputIterator ArgBegin,
- InputIterator ArgEnd, unsigned Values, const Twine &NameStr,
+ unsigned NumCatches,
+ RandomAccessIterator ArgBegin, RandomAccessIterator ArgEnd,
+ unsigned Values, const Twine &NameStr,
BasicBlock *InsertAtEnd);
protected:
virtual InvokeInst *clone_impl() const;
public:
~InvokeInst();
- template<typename InputIterator>
+ template<typename RandomAccessIterator>
static InvokeInst *Create(Value *Func,
BasicBlock *IfNormal, BasicBlock *IfException,
Value *PersFn, Value *CatchAllTy,
BasicBlock *CatchAll, unsigned NumCatches,
- InputIterator ArgBegin, InputIterator ArgEnd,
+ RandomAccessIterator ArgBegin,
+ RandomAccessIterator ArgEnd,
const Twine &NameStr = "",
Instruction *InsertBefore = 0) {
unsigned Values(ArgEnd - ArgBegin + 4);
@@ -2454,12 +2488,13 @@
ArgBegin, ArgEnd,
Values, NameStr, InsertBefore);
}
- template<typename InputIterator>
+ template<typename RandomAccessIterator>
static InvokeInst *Create(Value *Func,
BasicBlock *IfNormal, BasicBlock *IfException,
Value *PersFn, Value *CatchAllTy,
BasicBlock *CatchAll, unsigned NumCatches,
- InputIterator ArgBegin, InputIterator ArgEnd,
+ RandomAccessIterator ArgBegin,
+ RandomAccessIterator ArgEnd,
const Twine &NameStr,
BasicBlock *InsertAtEnd) {
unsigned Values(ArgEnd - ArgBegin + 4);
@@ -2601,6 +2636,9 @@
Op<-1>() = V;
}
+ bool hasCatchAll() const {
+ return CatchAllList != 0;
+ }
Value *getCatchAllType() const {
return CatchAllList[0];
}
@@ -2615,6 +2653,9 @@
}
/// getCatchType - Return the specified catch type.
+ bool hasCatches() const {
+ return CatchList != 0;
+ }
Value *getCatchType(unsigned I) {
assert(I < getNumCatches() && "Illegal catch type to get!");
return CatchList[I * 2];
@@ -2687,12 +2728,14 @@
struct OperandTraits<InvokeInst> : public VariadicOperandTraits<3> {
};
-template<typename InputIterator>
+template<typename RandomAccessIterator>
InvokeInst::InvokeInst(Value *Func,
BasicBlock *IfNormal, BasicBlock *IfException,
Value *PersFn, Value *CatchAllTy, BasicBlock *CatchAll,
- unsigned NumCatches, InputIterator ArgBegin,
- InputIterator ArgEnd, unsigned Values,
+ unsigned NumCatches,
+ RandomAccessIterator ArgBegin,
+ RandomAccessIterator ArgEnd,
+ unsigned Values,
const Twine &NameStr, Instruction *InsertBefore)
: TerminatorInst(cast<FunctionType>(cast<PointerType>(Func->getType())
->getElementType())->getReturnType(),
@@ -2701,14 +2744,17 @@
Values, InsertBefore) {
init(Func, IfNormal, IfException, PersFn, CatchAllTy, CatchAll,
NumCatches, ArgBegin, ArgEnd, NameStr,
- typename std::iterator_traits<InputIterator>::iterator_category());
+ typename std::iterator_traits<RandomAccessIterator>
+ ::iterator_category());
}
-template<typename InputIterator>
+template<typename RandomAccessIterator>
InvokeInst::InvokeInst(Value *Func,
BasicBlock *IfNormal, BasicBlock *IfException,
Value *PersFn, Value *CatchAllTy, BasicBlock *CatchAll,
- unsigned NumCatches, InputIterator ArgBegin,
- InputIterator ArgEnd, unsigned Values,
+ unsigned NumCatches,
+ RandomAccessIterator ArgBegin,
+ RandomAccessIterator ArgEnd,
+ unsigned Values,
const Twine &NameStr, BasicBlock *InsertAtEnd)
: TerminatorInst(cast<FunctionType>(cast<PointerType>(Func->getType())
->getElementType())->getReturnType(),
@@ -2717,7 +2763,8 @@
Values, InsertAtEnd) {
init(Func, IfNormal, IfException, PersFn, CatchAllTy, CatchAll,
NumCatches, ArgBegin, ArgEnd, NameStr,
- typename std::iterator_traits<InputIterator>::iterator_category());
+ typename std::iterator_traits<RandomAccessIterator>
+ ::iterator_category());
}
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(InvokeInst, Value)
Modified: llvm/branches/wendling/eh/include/llvm/Support/ELF.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Support/ELF.h?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Support/ELF.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Support/ELF.h Wed Oct 27 23:47:43 2010
@@ -232,10 +232,35 @@
R_386_GOTOFF = 9,
R_386_GOTPC = 10,
R_386_32PLT = 11,
+ R_386_TLS_TPOFF = 14,
+ R_386_TLS_IE = 15,
+ R_386_TLS_GOTIE = 16,
+ R_386_TLS_LE = 17,
+ R_386_TLS_GD = 18,
+ R_386_TLS_LDM = 19,
R_386_16 = 20,
R_386_PC16 = 21,
R_386_8 = 22,
- R_386_PC8 = 23
+ R_386_PC8 = 23,
+ R_386_TLS_GD_32 = 24,
+ R_386_TLS_GD_PUSH = 25,
+ R_386_TLS_GD_CALL = 26,
+ R_386_TLS_GD_POP = 27,
+ R_386_TLS_LDM_32 = 28,
+ R_386_TLS_LDM_PUSH = 29,
+ R_386_TLS_LDM_CALL = 30,
+ R_386_TLS_LDM_POP = 31,
+ R_386_TLS_LDO_32 = 32,
+ R_386_TLS_IE_32 = 33,
+ R_386_TLS_LE_32 = 34,
+ R_386_TLS_DTPMOD32 = 35,
+ R_386_TLS_DTPOFF32 = 36,
+ R_386_TLS_TPOFF32 = 37,
+ R_386_TLS_GOTDESC = 39,
+ R_386_TLS_DESC_CALL = 40,
+ R_386_TLS_DESC = 41,
+ R_386_IRELATIVE = 42,
+ R_386_NUM = 43
};
// Section header.
Modified: llvm/branches/wendling/eh/include/llvm/Support/IRBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Support/IRBuilder.h?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Support/IRBuilder.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Support/IRBuilder.h Wed Oct 27 23:47:43 2010
@@ -46,50 +46,50 @@
BasicBlock::iterator InsertPt;
LLVMContext &Context;
public:
-
+
IRBuilderBase(LLVMContext &context)
: Context(context) {
ClearInsertionPoint();
}
-
+
//===--------------------------------------------------------------------===//
// Builder configuration methods
//===--------------------------------------------------------------------===//
-
+
/// ClearInsertionPoint - Clear the insertion point: created instructions will
/// not be inserted into a block.
void ClearInsertionPoint() {
BB = 0;
}
-
+
BasicBlock *GetInsertBlock() const { return BB; }
BasicBlock::iterator GetInsertPoint() const { return InsertPt; }
LLVMContext &getContext() const { return Context; }
-
+
/// SetInsertPoint - This specifies that created instructions should be
/// appended to the end of the specified block.
void SetInsertPoint(BasicBlock *TheBB) {
BB = TheBB;
InsertPt = BB->end();
}
-
+
/// SetInsertPoint - This specifies that created instructions should be
/// inserted at the specified point.
void SetInsertPoint(BasicBlock *TheBB, BasicBlock::iterator IP) {
BB = TheBB;
InsertPt = IP;
}
-
+
/// SetCurrentDebugLocation - Set location information used by debugging
/// information.
void SetCurrentDebugLocation(const DebugLoc &L) {
CurDbgLocation = L;
}
-
+
/// getCurrentDebugLocation - Get location information used by debugging
/// information.
const DebugLoc &getCurrentDebugLocation() const { return CurDbgLocation; }
-
+
/// SetInstDebugLocation - If this builder has a current debug location, set
/// it on the specified instruction.
void SetInstDebugLocation(Instruction *I) const {
@@ -142,7 +142,7 @@
//===--------------------------------------------------------------------===//
// Miscellaneous creation methods.
//===--------------------------------------------------------------------===//
-
+
/// CreateGlobalString - Make a new global variable with an initializer that
/// has array of i8 type filled in with the nul terminated string value
/// specified. If Name is specified, it is the name of the global variable
@@ -178,65 +178,65 @@
ConstantInt *getInt32(uint32_t C) {
return ConstantInt::get(getInt32Ty(), C);
}
-
+
/// getInt64 - Get a constant 64-bit value.
ConstantInt *getInt64(uint64_t C) {
return ConstantInt::get(getInt64Ty(), C);
}
-
+
//===--------------------------------------------------------------------===//
// Type creation methods
//===--------------------------------------------------------------------===//
-
+
/// getInt1Ty - Fetch the type representing a single bit
const IntegerType *getInt1Ty() {
return Type::getInt1Ty(Context);
}
-
+
/// getInt8Ty - Fetch the type representing an 8-bit integer.
const IntegerType *getInt8Ty() {
return Type::getInt8Ty(Context);
}
-
+
/// getInt16Ty - Fetch the type representing a 16-bit integer.
const IntegerType *getInt16Ty() {
return Type::getInt16Ty(Context);
}
-
+
/// getInt32Ty - Fetch the type resepresenting a 32-bit integer.
const IntegerType *getInt32Ty() {
return Type::getInt32Ty(Context);
}
-
+
/// getInt64Ty - Fetch the type representing a 64-bit integer.
const IntegerType *getInt64Ty() {
return Type::getInt64Ty(Context);
}
-
+
/// getFloatTy - Fetch the type representing a 32-bit floating point value.
const Type *getFloatTy() {
return Type::getFloatTy(Context);
}
-
+
/// getDoubleTy - Fetch the type representing a 64-bit floating point value.
const Type *getDoubleTy() {
return Type::getDoubleTy(Context);
}
-
+
/// getVoidTy - Fetch the type representing void.
const Type *getVoidTy() {
return Type::getVoidTy(Context);
}
-
+
const PointerType *getInt8PtrTy() {
return Type::getInt8PtrTy(Context);
}
-
+
/// getCurrentFunctionReturnType - Get the return type of the current function
/// that we're emitting into.
const Type *getCurrentFunctionReturnType() const;
};
-
+
/// IRBuilder - This provides a uniform API for creating instructions and
/// inserting them into a basic block: either at the end of a BasicBlock, or
/// at a specific iterator location in a block.
@@ -258,25 +258,25 @@
IRBuilder(LLVMContext &C, const T &F, const Inserter &I = Inserter())
: IRBuilderBase(C), Inserter(I), Folder(F) {
}
-
+
explicit IRBuilder(LLVMContext &C) : IRBuilderBase(C), Folder(C) {
}
-
+
explicit IRBuilder(BasicBlock *TheBB, const T &F)
: IRBuilderBase(TheBB->getContext()), Folder(F) {
SetInsertPoint(TheBB);
}
-
+
explicit IRBuilder(BasicBlock *TheBB)
: IRBuilderBase(TheBB->getContext()), Folder(Context) {
SetInsertPoint(TheBB);
}
-
+
IRBuilder(BasicBlock *TheBB, BasicBlock::iterator IP, const T& F)
: IRBuilderBase(TheBB->getContext()), Folder(F) {
SetInsertPoint(TheBB, IP);
}
-
+
IRBuilder(BasicBlock *TheBB, BasicBlock::iterator IP)
: IRBuilderBase(TheBB->getContext()), Folder(Context) {
SetInsertPoint(TheBB, IP);
@@ -288,7 +288,7 @@
/// isNamePreserving - Return true if this builder is configured to actually
/// add the requested names to IR created through it.
bool isNamePreserving() const { return preserveNames; }
-
+
/// Insert - Insert and return the specified instruction.
template<typename InstTy>
InstTy *Insert(InstTy *I, const Twine &Name = "") const {
@@ -313,7 +313,7 @@
ReturnInst *CreateRet(Value *V) {
return Insert(ReturnInst::Create(Context, V));
}
-
+
/// CreateAggregateRet - Create a sequence of N insertvalue instructions,
/// with one Value from the retVals array each, that build a aggregate
/// return value one value at a time, and a ret instruction to return
@@ -383,12 +383,14 @@
NumCatches, Args, Args+3), Name);
}
/// CreateInvoke - Create an invoke instruction.
- template<typename InputIterator>
+ template<typename RandomAccessIterator>
InvokeInst *CreateInvoke(Value *Callee, BasicBlock *NormalDest,
BasicBlock *UnwindDest, Value *PersonalityFn,
- Value *CatchAllTy, BasicBlock *CatchAll,
- unsigned NumCatches, InputIterator ArgBegin,
- InputIterator ArgEnd, const Twine &Name = "") {
+ Value *CatchAllTy, BasicBlock *CatchAll,
+ unsigned NumCatches,
+ RandomAccessIterator ArgBegin,
+ RandomAccessIterator ArgEnd,
+ const Twine &Name = "") {
return Insert(InvokeInst::Create(Callee, NormalDest, UnwindDest,
PersonalityFn, CatchAllTy, CatchAll,
NumCatches, ArgBegin, ArgEnd), Name);
@@ -697,12 +699,14 @@
StoreInst *CreateStore(Value *Val, Value *Ptr, bool isVolatile = false) {
return Insert(new StoreInst(Val, Ptr, isVolatile));
}
- template<typename InputIterator>
- Value *CreateGEP(Value *Ptr, InputIterator IdxBegin, InputIterator IdxEnd,
+ template<typename RandomAccessIterator>
+ Value *CreateGEP(Value *Ptr,
+ RandomAccessIterator IdxBegin,
+ RandomAccessIterator IdxEnd,
const Twine &Name = "") {
if (Constant *PC = dyn_cast<Constant>(Ptr)) {
// Every index must be constant.
- InputIterator i;
+ RandomAccessIterator i;
for (i = IdxBegin; i < IdxEnd; ++i)
if (!isa<Constant>(*i))
break;
@@ -711,12 +715,13 @@
}
return Insert(GetElementPtrInst::Create(Ptr, IdxBegin, IdxEnd), Name);
}
- template<typename InputIterator>
- Value *CreateInBoundsGEP(Value *Ptr, InputIterator IdxBegin,
- InputIterator IdxEnd, const Twine &Name = "") {
+ template<typename RandomAccessIterator>
+ Value *CreateInBoundsGEP(Value *Ptr, RandomAccessIterator IdxBegin,
+ RandomAccessIterator IdxEnd,
+ const Twine &Name = "") {
if (Constant *PC = dyn_cast<Constant>(Ptr)) {
// Every index must be constant.
- InputIterator i;
+ RandomAccessIterator i;
for (i = IdxBegin; i < IdxEnd; ++i)
if (!isa<Constant>(*i))
break;
@@ -746,7 +751,7 @@
if (Constant *PC = dyn_cast<Constant>(Ptr))
return Folder.CreateGetElementPtr(PC, &Idx, 1);
- return Insert(GetElementPtrInst::Create(Ptr, &Idx, &Idx+1), Name);
+ return Insert(GetElementPtrInst::Create(Ptr, &Idx, &Idx+1), Name);
}
Value *CreateConstInBoundsGEP1_32(Value *Ptr, unsigned Idx0,
const Twine &Name = "") {
@@ -757,7 +762,7 @@
return Insert(GetElementPtrInst::CreateInBounds(Ptr, &Idx, &Idx+1), Name);
}
- Value *CreateConstGEP2_32(Value *Ptr, unsigned Idx0, unsigned Idx1,
+ Value *CreateConstGEP2_32(Value *Ptr, unsigned Idx0, unsigned Idx1,
const Twine &Name = "") {
Value *Idxs[] = {
ConstantInt::get(Type::getInt32Ty(Context), Idx0),
@@ -767,7 +772,7 @@
if (Constant *PC = dyn_cast<Constant>(Ptr))
return Folder.CreateGetElementPtr(PC, Idxs, 2);
- return Insert(GetElementPtrInst::Create(Ptr, Idxs, Idxs+2), Name);
+ return Insert(GetElementPtrInst::Create(Ptr, Idxs, Idxs+2), Name);
}
Value *CreateConstInBoundsGEP2_32(Value *Ptr, unsigned Idx0, unsigned Idx1,
const Twine &Name = "") {
@@ -787,7 +792,7 @@
if (Constant *PC = dyn_cast<Constant>(Ptr))
return Folder.CreateGetElementPtr(PC, &Idx, 1);
- return Insert(GetElementPtrInst::Create(Ptr, &Idx, &Idx+1), Name);
+ return Insert(GetElementPtrInst::Create(Ptr, &Idx, &Idx+1), Name);
}
Value *CreateConstInBoundsGEP1_64(Value *Ptr, uint64_t Idx0,
const Twine &Name = "") {
@@ -808,7 +813,7 @@
if (Constant *PC = dyn_cast<Constant>(Ptr))
return Folder.CreateGetElementPtr(PC, Idxs, 2);
- return Insert(GetElementPtrInst::Create(Ptr, Idxs, Idxs+2), Name);
+ return Insert(GetElementPtrInst::Create(Ptr, Idxs, Idxs+2), Name);
}
Value *CreateConstInBoundsGEP2_64(Value *Ptr, uint64_t Idx0, uint64_t Idx1,
const Twine &Name = "") {
@@ -825,7 +830,7 @@
Value *CreateStructGEP(Value *Ptr, unsigned Idx, const Twine &Name = "") {
return CreateConstInBoundsGEP2_32(Ptr, 0, Idx, Name);
}
-
+
/// CreateGlobalStringPtr - Same as CreateGlobalString, but return a pointer
/// with "i8*" type instead of a pointer to array of i8.
Value *CreateGlobalStringPtr(const char *Str = "", const Twine &Name = "") {
@@ -834,7 +839,7 @@
Value *Args[] = { zero, zero };
return CreateInBoundsGEP(gv, Args, Args+2, Name);
}
-
+
//===--------------------------------------------------------------------===//
// Instruction creation methods: Cast/Conversion Operators
//===--------------------------------------------------------------------===//
@@ -1068,9 +1073,9 @@
return Insert(CallInst::Create(Callee, Args, Args+5), Name);
}
- template<typename InputIterator>
- CallInst *CreateCall(Value *Callee, InputIterator ArgBegin,
- InputIterator ArgEnd, const Twine &Name = "") {
+ template<typename RandomAccessIterator>
+ CallInst *CreateCall(Value *Callee, RandomAccessIterator ArgBegin,
+ RandomAccessIterator ArgEnd, const Twine &Name = "") {
return Insert(CallInst::Create(Callee, ArgBegin, ArgEnd), Name);
}
@@ -1120,10 +1125,10 @@
return Insert(ExtractValueInst::Create(Agg, Idx), Name);
}
- template<typename InputIterator>
+ template<typename RandomAccessIterator>
Value *CreateExtractValue(Value *Agg,
- InputIterator IdxBegin,
- InputIterator IdxEnd,
+ RandomAccessIterator IdxBegin,
+ RandomAccessIterator IdxEnd,
const Twine &Name = "") {
if (Constant *AggC = dyn_cast<Constant>(Agg))
return Folder.CreateExtractValue(AggC, IdxBegin, IdxEnd - IdxBegin);
@@ -1138,10 +1143,10 @@
return Insert(InsertValueInst::Create(Agg, Val, Idx), Name);
}
- template<typename InputIterator>
+ template<typename RandomAccessIterator>
Value *CreateInsertValue(Value *Agg, Value *Val,
- InputIterator IdxBegin,
- InputIterator IdxEnd,
+ RandomAccessIterator IdxBegin,
+ RandomAccessIterator IdxEnd,
const Twine &Name = "") {
if (Constant *AggC = dyn_cast<Constant>(Agg))
if (Constant *ValC = dyn_cast<Constant>(Val))
Modified: llvm/branches/wendling/eh/lib/Bitcode/Writer/BitcodeWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Bitcode/Writer/BitcodeWriter.cpp?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Bitcode/Writer/BitcodeWriter.cpp (original)
+++ llvm/branches/wendling/eh/lib/Bitcode/Writer/BitcodeWriter.cpp Wed Oct 27 23:47:43 2010
@@ -1064,7 +1064,8 @@
Vals.push_back(VE.getValueID(II->getCatchDest(i)));
}
- if (II->getCatchAllType()) {
+
+ if (II->hasCatchAll()) {
Vals.push_back(1);
PushValueAndType(II->getCatchAllType(), InstID, Vals, VE);
Vals.push_back(VE.getValueID(II->getCatchAllDest()));
Modified: llvm/branches/wendling/eh/lib/Bitcode/Writer/ValueEnumerator.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Bitcode/Writer/ValueEnumerator.cpp?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Bitcode/Writer/ValueEnumerator.cpp (original)
+++ llvm/branches/wendling/eh/lib/Bitcode/Writer/ValueEnumerator.cpp Wed Oct 27 23:47:43 2010
@@ -425,13 +425,28 @@
// Add all function-level constants to the value table.
for (Function::const_iterator BB = F.begin(), E = F.end(); BB != E; ++BB) {
- for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I!=E; ++I)
+ for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I!=E; ++I) {
for (User::const_op_iterator OI = I->op_begin(), E = I->op_end();
OI != E; ++OI) {
if ((isa<Constant>(*OI) && !isa<GlobalValue>(*OI)) ||
isa<InlineAsm>(*OI))
EnumerateValue(*OI);
}
+
+ if (const InvokeInst *II = dyn_cast<InvokeInst>(I)) {
+ for (unsigned i = 0, e = II->getNumCatches(); i != e; ++i) {
+ Value *V = II->getCatchType(i);
+ if ((isa<Constant>(V) && !isa<GlobalValue>(V)) || isa<InlineAsm>(V))
+ EnumerateValue(V);
+ }
+
+ if (II->hasCatchAll()) {
+ Value *V = II->getCatchAllType();
+ if ((isa<Constant>(V) && !isa<GlobalValue>(V)) || isa<InlineAsm>(V))
+ EnumerateValue(V);
+ }
+ }
+ }
BasicBlocks.push_back(BB);
ValueMap[BB] = BasicBlocks.size();
}
Modified: llvm/branches/wendling/eh/lib/CodeGen/MachineVerifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/MachineVerifier.cpp?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/MachineVerifier.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/MachineVerifier.cpp Wed Oct 27 23:47:43 2010
@@ -1069,11 +1069,13 @@
}
// Check the LI only has one connected component.
- ConnectedVNInfoEqClasses ConEQ(*LiveInts);
- unsigned NumComp = ConEQ.Classify(&LI);
- if (NumComp > 1) {
- report("Multiple connected components in live interval", MF);
- *OS << NumComp << " components in " << LI << '\n';
+ if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
+ ConnectedVNInfoEqClasses ConEQ(*LiveInts);
+ unsigned NumComp = ConEQ.Classify(&LI);
+ if (NumComp > 1) {
+ report("Multiple connected components in live interval", MF);
+ *OS << NumComp << " components in " << LI << '\n';
+ }
}
}
}
Modified: llvm/branches/wendling/eh/lib/CodeGen/PrologEpilogInserter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/PrologEpilogInserter.cpp?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/PrologEpilogInserter.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/PrologEpilogInserter.cpp Wed Oct 27 23:47:43 2010
@@ -759,8 +759,8 @@
// If this instruction has a FrameIndex operand, we need to
// use that target machine register info object to eliminate
// it.
- TRI.eliminateFrameIndex(MI, SPAdj,
- FrameIndexVirtualScavenging ? NULL : RS);
+ TRI.eliminateFrameIndex(MI, SPAdj,
+ FrameIndexVirtualScavenging ? NULL : RS);
// Reset the iterator if we were at the beginning of the BB.
if (AtBeginning) {
Modified: llvm/branches/wendling/eh/lib/CodeGen/ScheduleDAGInstrs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/ScheduleDAGInstrs.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/ScheduleDAGInstrs.cpp Wed Oct 27 23:47:43 2010
@@ -168,9 +168,16 @@
}
} else {
// For others, e.g. fallthrough, conditional branch, assume the exit
- // uses all the registers.
- // FIXME: This causes too much compile time regression. We need to compute
- // liveout instead.
+ // uses all the registers that are livein to the successor blocks.
+ SmallSet<unsigned, 8> Seen;
+ for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
+ SE = BB->succ_end(); SI != SE; ++SI)
+ for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
+ E = (*SI)->livein_end(); I != E; ++I) {
+ unsigned Reg = *I;
+ if (Seen.insert(Reg))
+ Uses[Reg].push_back(&ExitSU);
+ }
}
}
Modified: llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp Wed Oct 27 23:47:43 2010
@@ -82,6 +82,7 @@
Fn = &fn;
MF = &mf;
RegInfo = &MF->getRegInfo();
+ MachineModuleInfo &MMI = MF->getMMI();
// Check whether the function can return without sret-demotion.
SmallVector<ISD::OutputArg, 4> Outs;
@@ -138,7 +139,6 @@
// during the initial isel pass through the IR so that it is done
// in a predictable order.
if (const DbgDeclareInst *DI = dyn_cast<DbgDeclareInst>(I)) {
- MachineModuleInfo &MMI = MF->getMMI();
if (MMI.hasDebugInfo() &&
DIVariable(DI->getVariable()).Verify() &&
!DI->getDebugLoc().isUnknown()) {
@@ -163,9 +163,11 @@
}
}
- // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
+ // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
// also creates the initial PHI MachineInstrs, though none of the input
// operands are populated.
+
+ // SmallVector<const InvokeInst*, 16> Invokes;
for (BB = Fn->begin(); BB != EB; ++BB) {
MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
MBBMap[BB] = MBB;
@@ -201,18 +203,38 @@
PHIReg += NumRegisters;
}
}
+#if 0
+ if (const InvokeInst *Invoke = dyn_cast<InvokeInst>(BB->getTerminator()))
+ Invokes.push_back(Invoke);
+#endif
+ }
- if (const InvokeInst *Invoke = dyn_cast<InvokeInst>(BB->getTerminator())) {
- MachineModuleInfo &MMI = MF->getMMI();
-
- // Add personality function.
- MMI.addPersonality(Invoke->getPersonalityFn()->stripPointerCasts());
+#if 0
+ for (SmallVectorImpl<const InvokeInst*>::iterator
+ I = Invokes.begin(), E = Invokes.end(); I != E; ++I) {
+ const InvokeInst *Invoke = *I;
+
+ // Add personality function.
+ MMI.addPersonality(Invoke->getPersonalityFn()->stripPointerCasts());
+
+ // Mark landing pad blocks.
+ const Value *Ty = 0;
+ const BasicBlock *Dest = Invoke->getUnwindDest();
+ MBBMap[Dest]->setIsLandingPad();
+
+ if (Invoke->hasCatchAll()) {
+ Ty = Invoke->getCatchAllType()->stripPointerCasts();
+ Dest = Invoke->getCatchAllDest();
+ MBBMap[Dest]->setIsLandingPad();
+ }
- // Mark landing pad blocks.
- for (unsigned I = 1, E = Invoke->getNumSuccessors(); I < E; ++I)
- MBBMap[Invoke->getSuccessor(I)]->setIsLandingPad();
+ for (unsigned CI = 0, CE = Invoke->getNumCatches(); CI < CE; ++CI) {
+ Ty = Invoke->getCatchType(CI)->stripPointerCasts();
+ Dest = Invoke->getCatchDest(CI);
+ MBBMap[Dest]->setIsLandingPad();
}
}
+#endif
}
/// clear - Clear out all the function-specific state. This returns this
Modified: llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Wed Oct 27 23:47:43 2010
@@ -1683,29 +1683,31 @@
void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
- // Retrieve successors.
- MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
- SmallVector<MachineBasicBlock*, 8> CatchBlocks;
-
- for (unsigned i = 1, e = I.getNumSuccessors(); i != e; ++i)
- CatchBlocks.push_back(FuncInfo.MBBMap[I.getSuccessor(i)]);
+ // Create a landing pad for the invoke instruction.
+ MachineFunction *MF = InvokeMBB->getParent();
+ MachineBasicBlock *LandingPad = MF->CreateMachineBasicBlock(I.getParent());
+ LandingPad->setIsLandingPad();
+ MF->insert(llvm::next(InvokeMBB), LandingPad);
const Value *Callee = I.getCalledValue();
if (isa<InlineAsm>(Callee))
visitInlineAsm(&I);
else
- LowerCallTo(&I, getValue(Callee), false, CatchBlocks);
+ LowerCallTo(&I, getValue(Callee), false, LandingPad);
// If the value of the invoke is used outside of its defining block, make it
// available as a virtual register.
CopyToExportRegsIfNeeded(&I);
+ MachineBasicBlock *Return = FuncInfo.MBBMap[I.getNormalDest()];
+
// Update successor info
InvokeMBB->addSuccessor(Return);
+ InvokeMBB->addSuccessor(LandingPad);
- for (SmallVectorImpl<MachineBasicBlock*>::iterator
- i = CatchBlocks.begin(), e = CatchBlocks.end(); i != e; ++i)
- InvokeMBB->addSuccessor(*i);
+ // All of the catch blocks are successors to the landing pad.
+ for (unsigned i = 1, e = I.getNumSuccessors(); i != e; ++i)
+ LandingPad->addSuccessor(FuncInfo.MBBMap[I.getSuccessor(i)]);
// Drop into normal successor.
DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
@@ -4243,20 +4245,19 @@
}
case Intrinsic::eh_filter: {
// Add the filter IDs to the machine function.
- MachineFunction &MF = DAG.getMachineFunction();
- MachineModuleInfo &MMI = MF.getMMI();
- for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
- const Value *V = I.getArgOperand(i)->stripPointerCasts();
- MMI.addFilterTypeInfo(cast<const GlobalVariable>(V));
- }
+ MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
+ for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i)
+ MMI.addFilterTypeInfo(ExtractTypeInfo(I.getArgOperand(i)));
return 0;
}
case Intrinsic::eh_exception: {
// Insert the EXCEPTIONADDR instruction.
// EH-FIXME: I don't think that this should be a hard/fast rule anymore.
+#if 0
assert(FuncInfo.MBBMap[I.getParent()]->isLandingPad() &&
"Call to eh.exception not in landing pad!");
+#endif
SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
SDValue Ops[1] = { DAG.getRoot() };
SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
@@ -4675,14 +4676,8 @@
}
void SelectionDAGBuilder::
-LowerCallTo(ImmutableCallSite CS, SDValue Callee, bool isTailCall) {
- SmallVector<MachineBasicBlock*, 1> CatchBlocks;
- LowerCallTo(CS, Callee, isTailCall, CatchBlocks);
-}
-
-void SelectionDAGBuilder::
LowerCallTo(ImmutableCallSite CS, SDValue Callee, bool isTailCall,
- SmallVectorImpl<MachineBasicBlock*> &CatchBlocks) {
+ MachineBasicBlock *LandingPad) {
const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
const Type *RetTy = FTy->getReturnType();
@@ -4744,7 +4739,7 @@
Args.push_back(Entry);
}
- if (!CatchBlocks.empty()) {
+ if (LandingPad) {
// Insert a label before the invoke call to mark the try range. This can be
// used to detect deletion of the invoke via the MachineModuleInfo.
BeginLabel = MMI.getContext().CreateTempSymbol();
@@ -4759,8 +4754,8 @@
MMI.setCurrentCallSite(0);
}
- // Both PendingLoads and PendingExports must be flushed here;
- // this call might not return.
+ // Both PendingLoads and PendingExports must be flushed here. This call
+ // might not return.
(void)getRoot();
DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel));
}
@@ -4856,14 +4851,14 @@
else
HasTailCall = true;
- if (!CatchBlocks.empty()) {
+ if (LandingPad) {
// Insert a label at the end of the invoke call to mark the try range. This
// can be used to detect deletion of the invoke via the MachineModuleInfo.
MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel));
// Inform MachineModuleInfo of range.
-///EH-FIXME: MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
+ MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
}
}
Modified: llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h Wed Oct 27 23:47:43 2010
@@ -395,9 +395,8 @@
bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB);
void CopyToExportRegsIfNeeded(const Value *V);
void ExportFromCurrentBlock(const Value *V);
- void LowerCallTo(ImmutableCallSite CS, SDValue Callee, bool IsTailCall);
void LowerCallTo(ImmutableCallSite CS, SDValue Callee, bool IsTailCall,
- SmallVectorImpl<MachineBasicBlock*> &CatchBlocks);
+ MachineBasicBlock *CatchBlocks = 0);
/// UpdateSplitBlock - When an MBB was split during scheduling, update the
/// references that ned to refer to the last resulting block.
Modified: llvm/branches/wendling/eh/lib/CodeGen/SplitKit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SplitKit.cpp?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SplitKit.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SplitKit.cpp Wed Oct 27 23:47:43 2010
@@ -155,7 +155,7 @@
BlockPtrSet &CriticalExits) {
CriticalExits.clear();
- // A critical exit block has curli line-in, and has a predecessor that is not
+ // A critical exit block has curli live-in, and has a predecessor that is not
// in the loop nor a loop predecessor. For such an exit block, the edges
// carrying the new variable must be moved to a new pre-exit block.
for (BlockPtrSet::iterator I = Blocks.Exits.begin(), E = Blocks.Exits.end();
@@ -181,6 +181,38 @@
}
}
+void SplitAnalysis::getCriticalPreds(const SplitAnalysis::LoopBlocks &Blocks,
+ BlockPtrSet &CriticalPreds) {
+ CriticalPreds.clear();
+
+ // A critical predecessor block has curli live-out, and has a successor that
+ // has curli live-in and is not in the loop nor a loop exit block. For such a
+ // predecessor block, we must carry the value in both the 'inside' and
+ // 'outside' registers.
+ for (BlockPtrSet::iterator I = Blocks.Preds.begin(), E = Blocks.Preds.end();
+ I != E; ++I) {
+ const MachineBasicBlock *Pred = *I;
+ // Definitely not a critical edge.
+ if (Pred->succ_size() == 1)
+ continue;
+ // This block may not have curli live out at all if there is a PHI.
+ if (!lis_.isLiveOutOfMBB(*curli_, Pred))
+ continue;
+ // Does this block have a successor outside the loop?
+ for (MachineBasicBlock::const_pred_iterator SI = Pred->succ_begin(),
+ SE = Pred->succ_end(); SI != SE; ++SI) {
+ const MachineBasicBlock *Succ = *SI;
+ if (Blocks.Loop.count(Succ) || Blocks.Exits.count(Succ))
+ continue;
+ if (!lis_.isLiveInToMBB(*curli_, Succ))
+ continue;
+ // This is a critical predecessor block.
+ CriticalPreds.insert(Pred);
+ break;
+ }
+ }
+}
+
/// canSplitCriticalExits - Return true if it is possible to insert new exit
/// blocks before the blocks in CriticalExits.
bool
@@ -480,7 +512,7 @@
// extendTo - Find the last li_ value defined in MBB at or before Idx. The
// parentli_ is assumed to be live at Idx. Extend the live range to Idx.
// Return the found VNInfo, or NULL.
-VNInfo *LiveIntervalMap::extendTo(MachineBasicBlock *MBB, SlotIndex Idx) {
+VNInfo *LiveIntervalMap::extendTo(const MachineBasicBlock *MBB, SlotIndex Idx) {
assert(li_ && "call reset first");
LiveInterval::iterator I = std::upper_bound(li_->begin(), li_->end(), Idx);
if (I == li_->begin())
@@ -829,6 +861,16 @@
dupli_.addSimpleRange(LR.start, LR.end, LR.valno);
}
}
+
+ // Extend dupli_ to be live out of any critical loop predecessors.
+ // This means we have multiple registers live out of those blocks.
+ // The alternative would be to split the critical edges.
+ if (criticalPreds_.empty())
+ return;
+ for (SplitAnalysis::BlockPtrSet::iterator I = criticalPreds_.begin(),
+ E = criticalPreds_.end(); I != E; ++I)
+ dupli_.extendTo(*I, lis_.getMBBEndIdx(*I).getPrevSlot());
+ criticalPreds_.clear();
}
void SplitEditor::finish() {
@@ -892,6 +934,9 @@
sa_.getCriticalExits(Blocks, CriticalExits);
assert(CriticalExits.empty() && "Cannot break critical exits yet");
+ // Get critical predecessors so computeRemainder can deal with them.
+ sa_.getCriticalPreds(Blocks, criticalPreds_);
+
// Create new live interval for the loop.
openIntv();
Modified: llvm/branches/wendling/eh/lib/CodeGen/SplitKit.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SplitKit.h?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SplitKit.h (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SplitKit.h Wed Oct 27 23:47:43 2010
@@ -122,6 +122,11 @@
bool canSplitCriticalExits(const LoopBlocks &Blocks,
BlockPtrSet &CriticalExits);
+ /// getCriticalPreds - Get the set of loop predecessors with critical edges to
+ /// blocks outside the loop that have curli live in. We don't have to break
+ /// these edges, but they do require special treatment.
+ void getCriticalPreds(const LoopBlocks &Blocks, BlockPtrSet &CriticalPreds);
+
/// getBestSplitLoop - Return the loop where curli may best be split to a
/// separate register, or NULL.
const MachineLoop *getBestSplitLoop();
@@ -195,7 +200,7 @@
// extendTo - Find the last li_ value defined in MBB at or before Idx. The
// parentli is assumed to be live at Idx. Extend the live range to include
// Idx. Return the found VNInfo, or NULL.
- VNInfo *extendTo(MachineBasicBlock *MBB, SlotIndex Idx);
+ VNInfo *extendTo(const MachineBasicBlock *MBB, SlotIndex Idx);
/// isMapped - Return true is ParentVNI is a known mapped value. It may be a
/// simple 1-1 mapping or a complex mapping to later defs.
@@ -266,6 +271,10 @@
/// truncating any overlap with intervals_.
void addTruncSimpleRange(SlotIndex Start, SlotIndex End, VNInfo *VNI);
+ /// criticalPreds_ - Set of basic blocks where both dupli and openli should be
+ /// live out because of a critical edge.
+ SplitAnalysis::BlockPtrSet criticalPreds_;
+
/// computeRemainder - Compute the dupli liveness as the complement of all the
/// new intervals.
void computeRemainder();
Modified: llvm/branches/wendling/eh/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/TargetLoweringObjectFileImpl.cpp?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/TargetLoweringObjectFileImpl.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/TargetLoweringObjectFileImpl.cpp Wed Oct 27 23:47:43 2010
@@ -308,7 +308,7 @@
bool EmitUniquedSection;
if (Kind.isText())
EmitUniquedSection = TM.getFunctionSections();
- else
+ else
EmitUniquedSection = TM.getDataSections();
// If this global is linkonce/weak and the target handles this by emitting it
@@ -464,7 +464,7 @@
break;
}
}
-
+
TargetLoweringObjectFile::Initialize(Ctx, TM);
TextSection // .text
@@ -483,20 +483,20 @@
= getContext().getMachOSection("__DATA", "__thread_bss",
MCSectionMachO::S_THREAD_LOCAL_ZEROFILL,
SectionKind::getThreadBSS());
-
+
// TODO: Verify datarel below.
TLSTLVSection // .tlv
= getContext().getMachOSection("__DATA", "__thread_vars",
MCSectionMachO::S_THREAD_LOCAL_VARIABLES,
SectionKind::getDataRel());
-
+
TLSThreadInitSection
= getContext().getMachOSection("__DATA", "__thread_init",
MCSectionMachO::S_THREAD_LOCAL_INIT_FUNCTION_POINTERS,
SectionKind::getDataRel());
-
+
CStringSection // .cstring
- = getContext().getMachOSection("__TEXT", "__cstring",
+ = getContext().getMachOSection("__TEXT", "__cstring",
MCSectionMachO::S_CSTRING_LITERALS,
SectionKind::getMergeable1ByteCString());
UStringSection
@@ -507,7 +507,7 @@
MCSectionMachO::S_4BYTE_LITERALS,
SectionKind::getMergeableConst4());
EightByteConstantSection // .literal8
- = getContext().getMachOSection("__TEXT", "__literal8",
+ = getContext().getMachOSection("__TEXT", "__literal8",
MCSectionMachO::S_8BYTE_LITERALS,
SectionKind::getMergeableConst8());
@@ -531,14 +531,14 @@
MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
SectionKind::getText());
ConstTextCoalSection
- = getContext().getMachOSection("__TEXT", "__const_coal",
+ = getContext().getMachOSection("__TEXT", "__const_coal",
MCSectionMachO::S_COALESCED,
SectionKind::getReadOnly());
ConstDataSection // .const_data
= getContext().getMachOSection("__DATA", "__const", 0,
SectionKind::getReadOnlyWithRel());
DataCoalSection
- = getContext().getMachOSection("__DATA","__datacoal_nt",
+ = getContext().getMachOSection("__DATA","__datacoal_nt",
MCSectionMachO::S_COALESCED,
SectionKind::getDataRel());
DataCommonSection
@@ -548,7 +548,7 @@
DataBSSSection
= getContext().getMachOSection("__DATA","__bss", MCSectionMachO::S_ZEROFILL,
SectionKind::getBSS());
-
+
LazySymbolPointerSection
= getContext().getMachOSection("__DATA", "__la_symbol_ptr",
@@ -590,7 +590,7 @@
// Debug Information.
DwarfAbbrevSection =
- getContext().getMachOSection("__DWARF", "__debug_abbrev",
+ getContext().getMachOSection("__DWARF", "__debug_abbrev",
MCSectionMachO::S_ATTR_DEBUG,
SectionKind::getMetadata());
DwarfInfoSection =
@@ -637,7 +637,7 @@
getContext().getMachOSection("__DWARF", "__debug_inlined",
MCSectionMachO::S_ATTR_DEBUG,
SectionKind::getMetadata());
-
+
TLSExtraDataSection = TLSTLVSection;
}
@@ -679,7 +679,7 @@
const MCSection *TargetLoweringObjectFileMachO::
SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind,
Mangler *Mang, const TargetMachine &TM) const {
-
+
// Handle thread local data.
if (Kind.isThreadBSS()) return TLSBSSSection;
if (Kind.isThreadData()) return TLSDataSection;
@@ -699,7 +699,7 @@
if (Kind.isMergeable1ByteCString() &&
TM.getTargetData()->getPreferredAlignment(cast<GlobalVariable>(GV)) < 32)
return CStringSection;
-
+
// Do not put 16-bit arrays in the UString section if they have an
// externally visible label, this runs into issues with certain linker
// versions.
@@ -735,7 +735,7 @@
// with the .zerofill directive (aka .lcomm).
if (Kind.isBSSLocal())
return DataBSSSection;
-
+
// Otherwise, just drop the variable in the normal data section.
return DataSection;
}
@@ -952,6 +952,7 @@
else if (K.isText())
Flags |=
COFF::IMAGE_SCN_MEM_EXECUTE |
+ COFF::IMAGE_SCN_MEM_READ |
COFF::IMAGE_SCN_CNT_CODE;
else if (K.isBSS ())
Flags |=
Modified: llvm/branches/wendling/eh/lib/MC/ELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/MC/ELFObjectWriter.cpp?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/MC/ELFObjectWriter.cpp (original)
+++ llvm/branches/wendling/eh/lib/MC/ELFObjectWriter.cpp Wed Oct 27 23:47:43 2010
@@ -79,12 +79,20 @@
}
static bool RelocNeedsGOT(unsigned Type) {
+ // FIXME: Can we use the VariantKind?
switch (Type) {
default:
return false;
case ELF::R_X86_64_GOT32:
case ELF::R_X86_64_PLT32:
case ELF::R_X86_64_GOTPCREL:
+ case ELF::R_X86_64_TPOFF32:
+ case ELF::R_X86_64_TLSGD:
+ case ELF::R_X86_64_GOTTPOFF:
+ case ELF::R_386_TLS_GD:
+ case ELF::R_386_TLS_LE_32:
+ case ELF::R_386_TLS_IE:
+ case ELF::R_386_TLS_LE:
return true;
}
}
@@ -134,6 +142,7 @@
};
SmallPtrSet<const MCSymbol *, 16> UsedInReloc;
+ DenseMap<const MCSymbol *, const MCSymbol *> Renames;
llvm::DenseMap<const MCSectionData*,
std::vector<ELFRelocationEntry> > Relocations;
@@ -292,8 +301,7 @@
void CreateMetadataSections(MCAssembler &Asm, MCAsmLayout &Layout);
- void ExecutePostLayoutBinding(MCAssembler &Asm) {
- }
+ void ExecutePostLayoutBinding(MCAssembler &Asm);
void WriteSecHdrEntry(uint32_t Name, uint32_t Type, uint64_t Flags,
uint64_t Address, uint64_t Offset,
@@ -441,13 +449,42 @@
const MCSymbol *S = &Symbol;
while (S->isVariable()) {
const MCExpr *Value = S->getVariableValue();
- assert (Value->getKind() == MCExpr::SymbolRef && "Unimplemented");
+ if (Value->getKind() != MCExpr::SymbolRef)
+ return *S;
const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Value);
S = &Ref->getSymbol();
}
return *S;
}
+void ELFObjectWriterImpl::ExecutePostLayoutBinding(MCAssembler &Asm) {
+ // The presence of symbol versions causes undefined symbols and
+ // versions declared with @@@ to be renamed.
+
+ for (MCAssembler::symbol_iterator it = Asm.symbol_begin(),
+ ie = Asm.symbol_end(); it != ie; ++it) {
+ const MCSymbol &Alias = it->getSymbol();
+ if (!Alias.isVariable())
+ continue;
+ const MCSymbol &Symbol = AliasedSymbol(Alias);
+ StringRef AliasName = Alias.getName();
+ size_t Pos = AliasName.find('@');
+ if (Pos == StringRef::npos)
+ continue;
+
+ StringRef Rest = AliasName.substr(Pos);
+ if (!Symbol.isUndefined() && !Rest.startswith("@@@"))
+ continue;
+
+ // FIXME: produce a better error message.
+ if (Symbol.isUndefined() && Rest.startswith("@@") &&
+ !Rest.startswith("@@@"))
+ report_fatal_error("A @@ version cannot be undefined");
+
+ Renames.insert(std::make_pair(&Symbol, &Alias));
+ }
+}
+
void ELFObjectWriterImpl::WriteSymbol(MCDataFragment *F, ELFSymbolData &MSD,
const MCAsmLayout &Layout) {
MCSymbolData &OrigData = *MSD.SymbolData;
@@ -592,6 +629,9 @@
bool IsPCRel = isFixupKindX86PCRel(Fixup.getKind());
if (!Target.isAbsolute()) {
Symbol = &AliasedSymbol(Target.getSymA()->getSymbol());
+ const MCSymbol *Renamed = Renames.lookup(Symbol);
+ if (Renamed)
+ Symbol = Renamed;
MCSymbolData &SD = Asm.getSymbolData(*Symbol);
MCFragment *F = SD.getFragment();
@@ -655,6 +695,12 @@
case llvm::MCSymbolRefExpr::VK_GOTPCREL:
Type = ELF::R_X86_64_GOTPCREL;
break;
+ case MCSymbolRefExpr::VK_GOTTPOFF:
+ Type = ELF::R_X86_64_GOTTPOFF;
+ break;
+ case MCSymbolRefExpr::VK_TLSGD:
+ Type = ELF::R_X86_64_TLSGD;
+ break;
}
} else {
switch ((unsigned)Fixup.getKind()) {
@@ -675,6 +721,9 @@
case MCSymbolRefExpr::VK_GOTPCREL:
Type = ELF::R_X86_64_GOTPCREL;
break;
+ case MCSymbolRefExpr::VK_TPOFF:
+ Type = ELF::R_X86_64_TPOFF32;
+ break;
}
break;
case FK_Data_4:
@@ -722,6 +771,18 @@
case MCSymbolRefExpr::VK_GOTOFF:
Type = ELF::R_386_GOTOFF;
break;
+ case MCSymbolRefExpr::VK_TLSGD:
+ Type = ELF::R_386_TLS_GD;
+ break;
+ case MCSymbolRefExpr::VK_TPOFF:
+ Type = ELF::R_386_TLS_LE_32;
+ break;
+ case MCSymbolRefExpr::VK_INDNTPOFF:
+ Type = ELF::R_386_TLS_IE;
+ break;
+ case MCSymbolRefExpr::VK_NTPOFF:
+ Type = ELF::R_386_TLS_LE;
+ break;
}
break;
case FK_Data_2: Type = ELF::R_386_16; break;
@@ -764,11 +825,19 @@
}
static bool isInSymtab(const MCAssembler &Asm, const MCSymbolData &Data,
- bool Used) {
+ bool Used, bool Renamed) {
if (Used)
return true;
+ if (Renamed)
+ return false;
+
const MCSymbol &Symbol = Data.getSymbol();
+
+ const MCSymbol &A = AliasedSymbol(Symbol);
+ if (&A != &Symbol && A.isUndefined())
+ return false;
+
if (!Asm.isSymbolLinkerVisible(Symbol) && !Symbol.isUndefined())
return false;
@@ -815,57 +884,58 @@
ie = Asm.symbol_end(); it != ie; ++it) {
const MCSymbol &Symbol = it->getSymbol();
- if (!isInSymtab(Asm, *it, UsedInReloc.count(&Symbol)))
+ if (!isInSymtab(Asm, *it, UsedInReloc.count(&Symbol),
+ Renames.count(&Symbol)))
continue;
ELFSymbolData MSD;
MSD.SymbolData = it;
bool Local = isLocal(*it);
+ const MCSymbol &RefSymbol = AliasedSymbol(Symbol);
- bool Add = false;
if (it->isCommon()) {
assert(!Local);
MSD.SectionIndex = ELF::SHN_COMMON;
- Add = true;
- } else if (Symbol.isAbsolute()) {
+ } else if (Symbol.isAbsolute() || RefSymbol.isVariable()) {
MSD.SectionIndex = ELF::SHN_ABS;
- Add = true;
- } else if (Symbol.isVariable()) {
- const MCSymbol &RefSymbol = AliasedSymbol(Symbol);
- if (RefSymbol.isDefined()) {
- MSD.SectionIndex = SectionIndexMap.lookup(&RefSymbol.getSection());
- assert(MSD.SectionIndex && "Invalid section index!");
- Add = true;
- }
- } else if (Symbol.isUndefined()) {
- assert(!Local);
+ } else if (RefSymbol.isUndefined()) {
MSD.SectionIndex = ELF::SHN_UNDEF;
// FIXME: Undefined symbols are global, but this is the first place we
// are able to set it.
if (GetBinding(*it) == ELF::STB_LOCAL)
SetBinding(*it, ELF::STB_GLOBAL);
- Add = true;
} else {
- MSD.SectionIndex = SectionIndexMap.lookup(&Symbol.getSection());
+ MSD.SectionIndex = SectionIndexMap.lookup(&RefSymbol.getSection());
assert(MSD.SectionIndex && "Invalid section index!");
- Add = true;
}
- if (Add) {
- uint64_t &Entry = StringIndexMap[Symbol.getName()];
- if (!Entry) {
- Entry = StringTable.size();
- StringTable += Symbol.getName();
- StringTable += '\x00';
- }
- MSD.StringIndex = Entry;
- if (MSD.SectionIndex == ELF::SHN_UNDEF)
- UndefinedSymbolData.push_back(MSD);
- else if (Local)
- LocalSymbolData.push_back(MSD);
- else
- ExternalSymbolData.push_back(MSD);
+ // The @@@ in symbol version is replaced with @ in undefined symbols and
+ // @@ in defined ones.
+ StringRef Name = Symbol.getName();
+ size_t Pos = Name.find("@@@");
+ std::string FinalName;
+ if (Pos != StringRef::npos) {
+ StringRef Prefix = Name.substr(0, Pos);
+ unsigned n = MSD.SectionIndex == ELF::SHN_UNDEF ? 2 : 1;
+ StringRef Suffix = Name.substr(Pos + n);
+ FinalName = Prefix.str() + Suffix.str();
+ } else {
+ FinalName = Name.str();
}
+
+ uint64_t &Entry = StringIndexMap[FinalName];
+ if (!Entry) {
+ Entry = StringTable.size();
+ StringTable += FinalName;
+ StringTable += '\x00';
+ }
+ MSD.StringIndex = Entry;
+ if (MSD.SectionIndex == ELF::SHN_UNDEF)
+ UndefinedSymbolData.push_back(MSD);
+ else if (Local)
+ LocalSymbolData.push_back(MSD);
+ else
+ ExternalSymbolData.push_back(MSD);
}
// Symbols are required to be in lexicographic order.
Modified: llvm/branches/wendling/eh/lib/MC/MCParser/ELFAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/MC/MCParser/ELFAsmParser.cpp?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/MC/MCParser/ELFAsmParser.cpp (original)
+++ llvm/branches/wendling/eh/lib/MC/MCParser/ELFAsmParser.cpp Wed Oct 27 23:47:43 2010
@@ -12,6 +12,7 @@
#include "llvm/ADT/Twine.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCParser/MCAsmLexer.h"
#include "llvm/MC/MCSectionELF.h"
#include "llvm/MC/MCStreamer.h"
@@ -51,6 +52,7 @@
AddDirectiveHandler<&ELFAsmParser::ParseDirectivePrevious>(".previous");
AddDirectiveHandler<&ELFAsmParser::ParseDirectiveType>(".type");
AddDirectiveHandler<&ELFAsmParser::ParseDirectiveIdent>(".ident");
+ AddDirectiveHandler<&ELFAsmParser::ParseDirectiveSymver>(".symver");
}
// FIXME: Part of this logic is duplicated in the MCELFStreamer. What is
@@ -116,6 +118,7 @@
bool ParseDirectivePrevious(StringRef, SMLoc);
bool ParseDirectiveType(StringRef, SMLoc);
bool ParseDirectiveIdent(StringRef, SMLoc);
+ bool ParseDirectiveSymver(StringRef, SMLoc);
private:
bool ParseSectionName(StringRef &SectionName);
@@ -237,6 +240,15 @@
return TokError("unexpected token in directive");
unsigned Flags = 0;
+ unsigned Type = MCSectionELF::SHT_NULL;
+
+ // Set the defaults first.
+ if (SectionName == ".fini" || SectionName == ".init") {
+ Type = MCSectionELF::SHT_PROGBITS;
+ Flags |= MCSectionELF::SHF_ALLOC;
+ Flags |= MCSectionELF::SHF_EXECINSTR;
+ }
+
for (unsigned i = 0; i < FlagsStr.size(); i++) {
switch (FlagsStr[i]) {
case 'a':
@@ -268,7 +280,6 @@
}
}
- unsigned Type = MCSectionELF::SHT_NULL;
if (!TypeName.empty()) {
if (TypeName == "init_array")
Type = MCSectionELF::SHT_INIT_ARRAY;
@@ -377,6 +388,33 @@
return false;
}
+/// ParseDirectiveSymver
+/// ::= .symver foo, bar2 at zed
+bool ELFAsmParser::ParseDirectiveSymver(StringRef, SMLoc) {
+ StringRef Name;
+ if (getParser().ParseIdentifier(Name))
+ return TokError("expected identifier in directive");
+
+ if (getLexer().isNot(AsmToken::Comma))
+ return TokError("expected a comma");
+
+ Lex();
+
+ StringRef AliasName;
+ if (getParser().ParseIdentifier(AliasName))
+ return TokError("expected identifier in directive");
+
+ if (AliasName.find('@') == StringRef::npos)
+ return TokError("expected a '@' in the name");
+
+ MCSymbol *Alias = getContext().GetOrCreateSymbol(AliasName);
+ MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);
+ const MCExpr *Value = MCSymbolRefExpr::Create(Sym, getContext());
+
+ getStreamer().EmitAssignment(Alias, Value);
+ return false;
+}
+
namespace llvm {
MCAsmParserExtension *createELFAsmParser() {
Modified: llvm/branches/wendling/eh/lib/System/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/System/Makefile?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/System/Makefile (original)
+++ llvm/branches/wendling/eh/lib/System/Makefile Wed Oct 27 23:47:43 2010
@@ -11,11 +11,6 @@
LIBRARYNAME = LLVMSystem
BUILD_ARCHIVE = 1
REQUIRES_RTTI = 1
-include $(LEVEL)/Makefile.config
-
-ifeq ($(HOST_OS),MingW)
- REQUIRES_EH := 1
-endif
EXTRA_DIST = Unix Win32 README.txt
Modified: llvm/branches/wendling/eh/lib/System/Win32/Signals.inc
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/System/Win32/Signals.inc?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/System/Win32/Signals.inc (original)
+++ llvm/branches/wendling/eh/lib/System/Win32/Signals.inc Wed Oct 27 23:47:43 2010
@@ -208,8 +208,7 @@
}
static LONG WINAPI LLVMUnhandledExceptionFilter(LPEXCEPTION_POINTERS ep) {
- try {
- Cleanup();
+ Cleanup();
#ifdef _WIN64
// TODO: provide a x64 friendly version of the following
@@ -248,7 +247,8 @@
fprintf(stderr, "%08lX", PC);
// Print the parameters. Assume there are four.
- fprintf(stderr, " (0x%08lX 0x%08lX 0x%08lX 0x%08lX)", StackFrame.Params[0],
+ fprintf(stderr, " (0x%08lX 0x%08lX 0x%08lX 0x%08lX)",
+ StackFrame.Params[0],
StackFrame.Params[1], StackFrame.Params[2], StackFrame.Params[3]);
// Verify the PC belongs to a module in this process.
@@ -291,10 +291,6 @@
#endif
- } catch (...) {
- assert(0 && "Crashed in LLVMUnhandledExceptionFilter");
- }
-
if (ExitOnUnhandledExceptions)
_exit(-3);
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMAsmPrinter.cpp?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMAsmPrinter.cpp Wed Oct 27 23:47:43 2010
@@ -870,11 +870,11 @@
switch (MI->getOpcode()) {
default:
llvm_unreachable("Unexpected opcode!");
- case ARM::PICSTR: Opcode = ARM::STR; break;
- case ARM::PICSTRB: Opcode = ARM::STRB; break;
+ case ARM::PICSTR: Opcode = ARM::STRrs; break;
+ case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
case ARM::PICSTRH: Opcode = ARM::STRH; break;
case ARM::PICLDR: Opcode = ARM::LDRrs; break;
- case ARM::PICLDRB: Opcode = ARM::LDRB; break;
+ case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
case ARM::PICLDRH: Opcode = ARM::LDRH; break;
case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
@@ -1161,10 +1161,9 @@
}
{
MCInst TmpInst;
- TmpInst.setOpcode(ARM::STR);
+ TmpInst.setOpcode(ARM::STRi12);
TmpInst.addOperand(MCOperand::CreateReg(ValReg));
TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
- TmpInst.addOperand(MCOperand::CreateReg(0));
TmpInst.addOperand(MCOperand::CreateImm(4));
// Predicate.
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseInstrInfo.cpp Wed Oct 27 23:47:43 2010
@@ -676,9 +676,9 @@
switch (RC->getID()) {
case ARM::GPRRegClassID:
- AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
+ AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
.addReg(SrcReg, getKillRegState(isKill))
- .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
+ .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
break;
case ARM::SPRRegClassID:
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
@@ -755,7 +755,7 @@
int &FrameIndex) const {
switch (MI->getOpcode()) {
default: break;
- case ARM::STR:
+ case ARM::STRrs:
case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
if (MI->getOperand(1).isFI() &&
MI->getOperand(2).isReg() &&
@@ -766,6 +766,7 @@
return MI->getOperand(0).getReg();
}
break;
+ case ARM::STRi12:
case ARM::t2STRi12:
case ARM::tSpill:
case ARM::VSTRD:
@@ -1080,7 +1081,7 @@
default:
return false;
case ARM::LDRi12:
- case ARM::LDRB:
+ case ARM::LDRBi12:
case ARM::LDRD:
case ARM::LDRH:
case ARM::LDRSB:
@@ -1099,7 +1100,7 @@
default:
return false;
case ARM::LDRi12:
- case ARM::LDRB:
+ case ARM::LDRBi12:
case ARM::LDRD:
case ARM::LDRH:
case ARM::LDRSB:
@@ -1419,8 +1420,15 @@
if ((unsigned)Offset <= Mask * Scale) {
// Replace the FrameIndex with sp
MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
- if (isSub)
- ImmedOffset |= 1 << NumBits;
+ // FIXME: When addrmode2 goes away, this will simplify (like the
+ // T2 version), as the LDR.i12 versions don't need the encoding
+ // tricks for the offset value.
+ if (isSub) {
+ if (AddrMode == ARMII::AddrMode_i12)
+ ImmedOffset = -ImmedOffset;
+ else
+ ImmedOffset |= 1 << NumBits;
+ }
ImmOp.ChangeToImmediate(ImmedOffset);
Offset = 0;
return true;
@@ -1428,8 +1436,12 @@
// Otherwise, it didn't fit. Pull in what we can to simplify the immed.
ImmedOffset = ImmedOffset & Mask;
- if (isSub)
- ImmedOffset |= 1 << NumBits;
+ if (isSub) {
+ if (AddrMode == ARMII::AddrMode_i12)
+ ImmedOffset = -ImmedOffset;
+ else
+ ImmedOffset |= 1 << NumBits;
+ }
ImmOp.ChangeToImmediate(ImmedOffset);
Offset &= ~(Mask*Scale);
}
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseRegisterInfo.cpp Wed Oct 27 23:47:43 2010
@@ -1376,8 +1376,8 @@
// return false for everything else.
unsigned Opc = MI->getOpcode();
switch (Opc) {
- case ARM::LDRi12: case ARM::LDRH: case ARM::LDRB:
- case ARM::STR: case ARM::STRH: case ARM::STRB:
+ case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
+ case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
case ARM::t2LDRi12: case ARM::t2LDRi8:
case ARM::t2STRi12: case ARM::t2STRi8:
case ARM::VLDRS: case ARM::VLDRD:
@@ -1711,7 +1711,7 @@
// Build the new SUBri to adjust SP for integer callee-save spill area.
emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCSSize);
- movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI);
+ movePastCSLoadStoreOps(MBB, MBBI, ARM::STRi12, ARM::t2STRi12, 1, STI);
// Set FP to point to the stack slot that contains the previous FP.
bool HasFP = hasFP(MF);
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMCodeEmitter.cpp?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMCodeEmitter.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMCodeEmitter.cpp Wed Oct 27 23:47:43 2010
@@ -175,7 +175,27 @@
unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
unsigned Op) const { return 0; }
unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
- const { return 0; }
+ const {
+ // {17-13} = reg
+ // {12} = (U)nsigned (add == '1', sub == '0')
+ // {11-0} = imm12
+ const MachineOperand &MO = MI.getOperand(Op);
+ const MachineOperand &MO1 = MI.getOperand(Op + 1);
+ if (!MO.isReg()) {
+ emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
+ return 0;
+ }
+ unsigned Reg = getARMRegisterNumbering(MO.getReg());
+ int32_t Imm12 = MO1.getImm();
+ uint32_t Binary;
+ Binary = Imm12 & 0xfff;
+ if (Imm12 >= 0)
+ Binary |= (1 << 12);
+ Binary |= (Reg << 13);
+ return Binary;
+ }
+ unsigned getNEONVcvtImm32(const MachineInstr &MI, unsigned Op) const {
+ return 0; }
/// getMovi32Value - Return binary encoding of operand for movw/movt. If the
/// machine operand requires relocation, record the relocation and return
@@ -946,6 +966,13 @@
// Part of binary is determined by TableGn.
unsigned Binary = getBinaryCodeForInstr(MI);
+ // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done.
+ if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp ||
+ MI.getOpcode() == ARM::STRi12) {
+ emitWordLE(Binary);
+ return;
+ }
+
// Set the conditional execution predicate
Binary |= II->getPredicate(&MI) << ARMII::CondShift;
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMFastISel.cpp?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMFastISel.cpp Wed Oct 27 23:47:43 2010
@@ -684,9 +684,9 @@
}
void ARMFastISel::ARMSimplifyRegOffset(unsigned &Base, int &Offset, EVT VT) {
-
+
assert(VT.isSimple() && "Non-simple types are invalid here!");
-
+
bool needsLowering = false;
switch (VT.getSimpleVT().SimpleTy) {
default:
@@ -704,7 +704,7 @@
needsLowering = ((Offset & 0xff) != Offset);
break;
}
-
+
// Since the offset is too large for the load/store instruction
// get the reg+offset into a register.
if (needsLowering) {
@@ -746,7 +746,7 @@
RC = ARM::GPRRegisterClass;
break;
case MVT::i8:
- Opc = isThumb ? ARM::t2LDRBi12 : ARM::LDRB;
+ Opc = isThumb ? ARM::t2LDRBi12 : ARM::LDRBi12;
RC = ARM::GPRRegisterClass;
break;
case MVT::i32:
@@ -766,16 +766,14 @@
}
ResultReg = createResultReg(RC);
-
+
ARMSimplifyRegOffset(Base, Offset, VT);
-
+
// addrmode5 output depends on the selection dag addressing dividing the
// offset by 4 that it then later multiplies. Do this here as well.
if (isFloat)
Offset /= 4;
-
- // The thumb and floating point instructions both take 2 operands, ARM takes
- // another register.
+
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(Opc), ResultReg)
.addReg(Base).addImm(Offset));
@@ -807,17 +805,19 @@
unsigned Base, int Offset) {
unsigned StrOpc;
bool isFloat = false;
+ bool needReg0Op = false;
switch (VT.getSimpleVT().SimpleTy) {
default: return false;
case MVT::i1:
case MVT::i8:
- StrOpc = isThumb ? ARM::t2STRBi12 : ARM::STRB;
+ StrOpc = isThumb ? ARM::t2STRBi12 : ARM::STRBi12;
break;
case MVT::i16:
StrOpc = isThumb ? ARM::t2STRHi12 : ARM::STRH;
+ needReg0Op = true;
break;
case MVT::i32:
- StrOpc = isThumb ? ARM::t2STRi12 : ARM::STR;
+ StrOpc = isThumb ? ARM::t2STRi12 : ARM::STRi12;
break;
case MVT::f32:
if (!Subtarget->hasVFP2()) return false;
@@ -832,15 +832,16 @@
}
ARMSimplifyRegOffset(Base, Offset, VT);
-
+
// addrmode5 output depends on the selection dag addressing dividing the
// offset by 4 that it then later multiplies. Do this here as well.
if (isFloat)
Offset /= 4;
-
- // The thumb addressing mode has operands swapped from the arm addressing
- // mode, the floating point one only has two operands.
- if (isFloat || isThumb)
+
+
+ // FIXME: The 'needReg0Op' bit goes away once STRH is converted to
+ // not use the mega-addrmode stuff.
+ if (!needReg0Op)
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(StrOpc))
.addReg(SrcReg).addReg(Base).addImm(Offset));
@@ -1244,12 +1245,12 @@
EVT SrcVT, unsigned &ResultReg) {
unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc,
Src, /*TODO: Kill=*/false);
-
+
if (RR != 0) {
ResultReg = RR;
return true;
} else
- return false;
+ return false;
}
// This is largely taken directly from CCAssignFnForNode - we don't support
@@ -1367,7 +1368,7 @@
} else if (VA.needsCustom()) {
// TODO: We need custom lowering for vector (v2f64) args.
if (VA.getLocVT() != MVT::f64) return false;
-
+
CCValAssign &NextVA = ArgLocs[++i];
// TODO: Only handle register args for now.
@@ -1420,7 +1421,7 @@
UsedRegs.push_back(RVLocs[0].getLocReg());
UsedRegs.push_back(RVLocs[1].getLocReg());
-
+
// Finally update the result.
UpdateValueMap(I, ResultReg);
} else {
@@ -1444,10 +1445,10 @@
bool ARMFastISel::SelectRet(const Instruction *I) {
const ReturnInst *Ret = cast<ReturnInst>(I);
const Function &F = *I->getParent()->getParent();
-
+
if (!FuncInfo.CanLowerReturn)
return false;
-
+
if (F.isVarArg())
return false;
@@ -1472,7 +1473,7 @@
return false;
CCValAssign &VA = ValLocs[0];
-
+
// Don't bother handling odd stuff for now.
if (VA.getLocInfo() != CCValAssign::Full)
return false;
@@ -1483,7 +1484,7 @@
// says Full but the types don't match.
if (VA.getValVT() != TLI.getValueType(RV->getType()))
return false;
-
+
// Make the copy.
unsigned SrcReg = Reg + VA.getValNo();
unsigned DstReg = VA.getLocReg();
@@ -1497,7 +1498,7 @@
// Mark the register as live out of the function.
MRI.addLiveOut(VA.getLocReg());
}
-
+
unsigned RetOpc = isThumb ? ARM::tBX_RET : ARM::BX_RET;
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(RetOpc)));
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMISelDAGToDAG.cpp Wed Oct 27 23:47:43 2010
@@ -78,8 +78,12 @@
SDNode *Select(SDNode *N);
+ bool isShifterOpProfitable(const SDValue &Shift,
+ ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
bool SelectShifterOperandReg(SDValue N, SDValue &A,
SDValue &B, SDValue &C);
+ bool SelectShiftShifterOperandReg(SDValue N, SDValue &A,
+ SDValue &B, SDValue &C);
bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
@@ -246,6 +250,17 @@
}
+bool ARMDAGToDAGISel::isShifterOpProfitable(const SDValue &Shift,
+ ARM_AM::ShiftOpc ShOpcVal,
+ unsigned ShAmt) {
+ if (!Subtarget->isCortexA9())
+ return true;
+ if (Shift.hasOneUse())
+ return true;
+ // R << 2 is free.
+ return ShOpcVal == ARM_AM::lsl && ShAmt == 2;
+}
+
bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue N,
SDValue &BaseReg,
SDValue &ShReg,
@@ -266,6 +281,32 @@
ShImmVal = RHS->getZExtValue() & 31;
} else {
ShReg = N.getOperand(1);
+ if (!isShifterOpProfitable(N, ShOpcVal, ShImmVal))
+ return false;
+ }
+ Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
+ MVT::i32);
+ return true;
+}
+
+bool ARMDAGToDAGISel::SelectShiftShifterOperandReg(SDValue N,
+ SDValue &BaseReg,
+ SDValue &ShReg,
+ SDValue &Opc) {
+ ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
+
+ // Don't match base register only case. That is matched to a separate
+ // lower complexity pattern with explicit register operand.
+ if (ShOpcVal == ARM_AM::no_shift) return false;
+
+ BaseReg = N.getOperand(0);
+ unsigned ShImmVal = 0;
+ // Do not check isShifterOpProfitable. This must return true.
+ if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
+ ShReg = CurDAG->getRegister(0, MVT::i32);
+ ShImmVal = RHS->getZExtValue() & 31;
+ } else {
+ ShReg = N.getOperand(1);
}
Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
MVT::i32);
@@ -321,7 +362,8 @@
bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
SDValue &Opc) {
- if (N.getOpcode() == ISD::MUL) {
+ if (N.getOpcode() == ISD::MUL &&
+ (!Subtarget->isCortexA9() || N.hasOneUse())) {
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
// X * [3,5,9] -> X + X * [2,4,8] etc.
int RHSC = (int)RHS->getZExtValue();
@@ -357,6 +399,10 @@
}
}
+ if (Subtarget->isCortexA9() && !N.hasOneUse())
+ // Compute R +/- (R << N) and reuse it.
+ return false;
+
// Otherwise this is R +/- [possibly shifted] R.
ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
@@ -371,14 +417,20 @@
if (ConstantSDNode *Sh =
dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
ShAmt = Sh->getZExtValue();
- Offset = N.getOperand(1).getOperand(0);
+ if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
+ Offset = N.getOperand(1).getOperand(0);
+ else {
+ ShAmt = 0;
+ ShOpcVal = ARM_AM::no_shift;
+ }
} else {
ShOpcVal = ARM_AM::no_shift;
}
}
// Try matching (R shl C) + (R).
- if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
+ if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift &&
+ !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
if (ShOpcVal != ARM_AM::no_shift) {
// Check to see if the RHS of the shift is a constant, if not, we can't
@@ -386,8 +438,15 @@
if (ConstantSDNode *Sh =
dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
ShAmt = Sh->getZExtValue();
- Offset = N.getOperand(0).getOperand(0);
- Base = N.getOperand(1);
+ if (!Subtarget->isCortexA9() ||
+ (N.hasOneUse() &&
+ isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt))) {
+ Offset = N.getOperand(0).getOperand(0);
+ Base = N.getOperand(1);
+ } else {
+ ShAmt = 0;
+ ShOpcVal = ARM_AM::no_shift;
+ }
} else {
ShOpcVal = ARM_AM::no_shift;
}
@@ -408,7 +467,8 @@
SDValue &Base,
SDValue &Offset,
SDValue &Opc) {
- if (N.getOpcode() == ISD::MUL) {
+ if (N.getOpcode() == ISD::MUL &&
+ (!Subtarget->isCortexA9() || N.hasOneUse())) {
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
// X * [3,5,9] -> X + X * [2,4,8] etc.
int RHSC = (int)RHS->getZExtValue();
@@ -474,6 +534,16 @@
}
}
+ if (Subtarget->isCortexA9() && !N.hasOneUse()) {
+ // Compute R +/- (R << N) and reuse it.
+ Base = N;
+ Offset = CurDAG->getRegister(0, MVT::i32);
+ Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
+ ARM_AM::no_shift),
+ MVT::i32);
+ return AM2_BASE;
+ }
+
// Otherwise this is R +/- [possibly shifted] R.
ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
@@ -488,14 +558,20 @@
if (ConstantSDNode *Sh =
dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
ShAmt = Sh->getZExtValue();
- Offset = N.getOperand(1).getOperand(0);
+ if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
+ Offset = N.getOperand(1).getOperand(0);
+ else {
+ ShAmt = 0;
+ ShOpcVal = ARM_AM::no_shift;
+ }
} else {
ShOpcVal = ARM_AM::no_shift;
}
}
// Try matching (R shl C) + (R).
- if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
+ if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift &&
+ !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
if (ShOpcVal != ARM_AM::no_shift) {
// Check to see if the RHS of the shift is a constant, if not, we can't
@@ -503,8 +579,15 @@
if (ConstantSDNode *Sh =
dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
ShAmt = Sh->getZExtValue();
- Offset = N.getOperand(0).getOperand(0);
- Base = N.getOperand(1);
+ if (!Subtarget->isCortexA9() ||
+ (N.hasOneUse() &&
+ isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt))) {
+ Offset = N.getOperand(0).getOperand(0);
+ Base = N.getOperand(1);
+ } else {
+ ShAmt = 0;
+ ShOpcVal = ARM_AM::no_shift;
+ }
} else {
ShOpcVal = ARM_AM::no_shift;
}
@@ -543,7 +626,12 @@
// it.
if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
ShAmt = Sh->getZExtValue();
- Offset = N.getOperand(0);
+ if (isShifterOpProfitable(N, ShOpcVal, ShAmt))
+ Offset = N.getOperand(0);
+ else {
+ ShAmt = 0;
+ ShOpcVal = ARM_AM::no_shift;
+ }
} else {
ShOpcVal = ARM_AM::no_shift;
}
@@ -959,6 +1047,12 @@
return false;
}
+ if (Subtarget->isCortexA9() && !N.hasOneUse()) {
+ // Compute R + (R << [1,2,3]) and reuse it.
+ Base = N;
+ return false;
+ }
+
// Look for (R + R) or (R + (R << [1,2,3])).
unsigned ShAmt = 0;
Base = N.getOperand(0);
@@ -977,11 +1071,12 @@
// it.
if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
ShAmt = Sh->getZExtValue();
- if (ShAmt >= 4) {
+ if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt))
+ OffReg = OffReg.getOperand(0);
+ else {
ShAmt = 0;
ShOpcVal = ARM_AM::no_shift;
- } else
- OffReg = OffReg.getOperand(0);
+ }
} else {
ShOpcVal = ARM_AM::no_shift;
}
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMISelLowering.cpp?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMISelLowering.cpp Wed Oct 27 23:47:43 2010
@@ -460,6 +460,7 @@
setTargetDAGCombine(ISD::ANY_EXTEND);
setTargetDAGCombine(ISD::SELECT_CC);
setTargetDAGCombine(ISD::BUILD_VECTOR);
+ setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
}
computeRegisterProperties();
@@ -4531,6 +4532,59 @@
return SDValue();
}
+/// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
+/// ISD::VECTOR_SHUFFLE.
+static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
+ // The LLVM shufflevector instruction does not require the shuffle mask
+ // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
+ // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
+ // operands do not match the mask length, they are extended by concatenating
+ // them with undef vectors. That is probably the right thing for other
+ // targets, but for NEON it is better to concatenate two double-register
+ // size vector operands into a single quad-register size vector. Do that
+ // transformation here:
+ // shuffle(concat(v1, undef), concat(v2, undef)) ->
+ // shuffle(concat(v1, v2), undef)
+ SDValue Op0 = N->getOperand(0);
+ SDValue Op1 = N->getOperand(1);
+ if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
+ Op1.getOpcode() != ISD::CONCAT_VECTORS ||
+ Op0.getNumOperands() != 2 ||
+ Op1.getNumOperands() != 2)
+ return SDValue();
+ SDValue Concat0Op1 = Op0.getOperand(1);
+ SDValue Concat1Op1 = Op1.getOperand(1);
+ if (Concat0Op1.getOpcode() != ISD::UNDEF ||
+ Concat1Op1.getOpcode() != ISD::UNDEF)
+ return SDValue();
+ // Skip the transformation if any of the types are illegal.
+ const TargetLowering &TLI = DAG.getTargetLoweringInfo();
+ EVT VT = N->getValueType(0);
+ if (!TLI.isTypeLegal(VT) ||
+ !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
+ !TLI.isTypeLegal(Concat1Op1.getValueType()))
+ return SDValue();
+
+ SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
+ Op0.getOperand(0), Op1.getOperand(0));
+ // Translate the shuffle mask.
+ SmallVector<int, 16> NewMask;
+ unsigned NumElts = VT.getVectorNumElements();
+ unsigned HalfElts = NumElts/2;
+ ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
+ for (unsigned n = 0; n < NumElts; ++n) {
+ int MaskElt = SVN->getMaskElt(n);
+ int NewElt = -1;
+ if (MaskElt < (int)HalfElts)
+ NewElt = MaskElt;
+ else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
+ NewElt = HalfElts + MaskElt - NumElts;
+ NewMask.push_back(NewElt);
+ }
+ return DAG.getVectorShuffle(VT, N->getDebugLoc(), NewConcat,
+ DAG.getUNDEF(VT), NewMask.data());
+}
+
/// PerformVDUPLANECombine - Target-specific dag combine xforms for
/// ARMISD::VDUPLANE.
static SDValue PerformVDUPLANECombine(SDNode *N, SelectionDAG &DAG) {
@@ -4939,6 +4993,7 @@
case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI.DAG);
+ case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI.DAG);
case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
case ISD::SHL:
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrFormats.td?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrFormats.td Wed Oct 27 23:47:43 2010
@@ -401,9 +401,10 @@
// loads
-// LDR/LDRB
-class AIldr1<bits<3> op, bit opc22, dag oops, dag iops, AddrMode am, Format f,
- InstrItinClass itin, string opc, string asm, list<dag> pattern>
+// LDR/LDRB/STR/STRB
+class AIldst1<bits<3> op, bit opc22, bit isLd, dag oops, dag iops, AddrMode am,
+ Format f, InstrItinClass itin, string opc, string asm,
+ list<dag> pattern>
: I<oops, iops, am, Size4Bytes, IndexModeNone, f, itin, opc, asm,
"", pattern> {
let Inst{27-25} = op;
@@ -411,7 +412,7 @@
// 23 == U
let Inst{22} = opc22;
let Inst{21} = 0; // 21 == W
- let Inst{20} = 1;
+ let Inst{20} = isLd;
}
// LDRH/LDRSB/LDRSH/LDRD
class AIldr2<bits<4> op, bit opc22, bit opc20, dag oops, dag iops, AddrMode am,
@@ -1867,6 +1868,16 @@
let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
let Pattern = pattern;
list<Predicate> Predicates = [HasNEON];
+
+ bits<5> V;
+ bits<4> R;
+ bits<4> p;
+ bits<4> lane;
+
+ let Inst{31-28} = p{3-0};
+ let Inst{7} = V{4};
+ let Inst{19-16} = V{3-0};
+ let Inst{15-12} = R{3-0};
}
class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
dag oops, dag iops, InstrItinClass itin,
@@ -1895,6 +1906,15 @@
let Inst{11-7} = 0b11000;
let Inst{6} = op6;
let Inst{4} = 0;
+
+ bits<5> Vd;
+ bits<5> Vm;
+ bits<4> lane;
+
+ let Inst{22} = Vd{4};
+ let Inst{15-12} = Vd{3-0};
+ let Inst{5} = Vm{4};
+ let Inst{3-0} = Vm{3-0};
}
// NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrInfo.cpp?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrInfo.cpp Wed Oct 27 23:47:43 2010
@@ -39,7 +39,7 @@
return ARM::LDRH;
case ARM::LDRB_PRE:
case ARM::LDRB_POST:
- return ARM::LDRB;
+ return ARM::LDRBi12;
case ARM::LDRSH_PRE:
case ARM::LDRSH_POST:
return ARM::LDRSH;
@@ -48,13 +48,13 @@
return ARM::LDRSB;
case ARM::STR_PRE:
case ARM::STR_POST:
- return ARM::STR;
+ return ARM::STRi12;
case ARM::STRH_PRE:
case ARM::STRH_POST:
return ARM::STRH;
case ARM::STRB_PRE:
case ARM::STRB_POST:
- return ARM::STRB;
+ return ARM::STRBi12;
}
return 0;
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrInfo.td?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrInfo.td Wed Oct 27 23:47:43 2010
@@ -299,6 +299,10 @@
let PrintMethod = "printPCLabel";
}
+def neon_vcvt_imm32 : Operand<i32> {
+ string EncoderMethod = "getNEONVcvtImm32";
+}
+
// rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
int32_t v = (int32_t)N->getZExtValue();
@@ -321,6 +325,13 @@
let PrintMethod = "printSORegOperand";
let MIOperandInfo = (ops GPR, GPR, i32imm);
}
+def shift_so_reg : Operand<i32>, // reg reg imm
+ ComplexPattern<i32, 3, "SelectShiftShifterOperandReg",
+ [shl,srl,sra,rotr]> {
+ string EncoderMethod = "getSORegOpValue";
+ let PrintMethod = "printSORegOperand";
+ let MIOperandInfo = (ops GPR, GPR, i32imm);
+}
// so_imm - Match a 32-bit shifter_operand immediate operand, which is an
// 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
@@ -397,6 +408,7 @@
def ldst_so_reg : Operand<i32>,
ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
// FIXME: Simplify the printer
+ // FIXME: Add EncoderMethod for this addressing mode
let PrintMethod = "printAddrMode2Operand";
let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
}
@@ -808,7 +820,7 @@
// Note: We use the complex addrmode_imm12 rather than just an input
// GPR and a constrained immediate so that we can use this to match
// frame index references and avoid matching constant pool references.
- def i12 : AIldr1<0b010, opc22, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
+ def i12 : AIldst1<0b010, opc22, 1, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
[(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
bits<4> Rt;
@@ -818,7 +830,7 @@
let Inst{15-12} = Rt;
let Inst{11-0} = addr{11-0}; // imm12
}
- def rs : AIldr1<0b011, opc22, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
+ def rs : AIldst1<0b011, opc22, 1, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
[(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
bits<4> Rt;
@@ -830,6 +842,32 @@
}
}
+multiclass AI_str1<bit opc22, string opc, InstrItinClass iii,
+ InstrItinClass iir, PatFrag opnode> {
+ // Note: We use the complex addrmode_imm12 rather than just an input
+ // GPR and a constrained immediate so that we can use this to match
+ // frame index references and avoid matching constant pool references.
+ def i12 : AIldst1<0b010, opc22, 0, (outs),
+ (ins GPR:$Rt, addrmode_imm12:$addr),
+ AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
+ [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
+ bits<4> Rt;
+ bits<17> addr;
+ let Inst{23} = addr{12}; // U (add = ('U' == 1))
+ let Inst{19-16} = addr{16-13}; // Rn
+ let Inst{15-12} = Rt;
+ let Inst{11-0} = addr{11-0}; // imm12
+ }
+ def rs : AIldst1<0b011, opc22, 0, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
+ AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
+ [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
+ bits<4> Rt;
+ bits<17> shift;
+ let Inst{23} = shift{12}; // U (add = ('U' == 1))
+ let Inst{19-16} = shift{16-13}; // Rn
+ let Inst{11-0} = shift{11-0};
+ }
+}
//===----------------------------------------------------------------------===//
// Instructions
//===----------------------------------------------------------------------===//
@@ -1400,13 +1438,19 @@
// Load
-defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_i, IIC_iLoad_r,
- UnOpFrag<(load node:$Src)>>;
+defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_i, IIC_iLoad_r,
+ UnOpFrag<(load node:$Src)>>;
+defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_r,
+ UnOpFrag<(zextloadi8 node:$Src)>>;
+defm STR : AI_str1<0, "str", IIC_iStore_i, IIC_iStore_r,
+ BinOpFrag<(store node:$LHS, node:$RHS)>>;
+defm STRB : AI_str1<1, "strb", IIC_iStore_bh_i, IIC_iStore_bh_r,
+ BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
// Special LDR for loads from non-pc-relative constpools.
let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
isReMaterializable = 1 in
-def LDRcp : AIldr1<0b010, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
+def LDRcp : AIldst1<0b010, 0, 1, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr", []> {
bits<4> Rt;
bits<17> addr;
@@ -1421,10 +1465,6 @@
IIC_iLoad_bh_r, "ldrh", "\t$dst, $addr",
[(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
-def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
- IIC_iLoad_bh_r, "ldrb", "\t$dst, $addr",
- [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
-
// Loads with sign extension
def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
IIC_iLoad_bh_r, "ldrsh", "\t$dst, $addr",
@@ -1528,19 +1568,12 @@
}
// Store
-def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStore_r,
- "str", "\t$src, $addr",
- [(store GPR:$src, addrmode2:$addr)]>;
// Stores with truncate
def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm,
IIC_iStore_bh_r, "strh", "\t$src, $addr",
[(truncstorei16 GPR:$src, addrmode3:$addr)]>;
-def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm,
- IIC_iStore_bh_r, "strb", "\t$src, $addr",
- [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
-
// Store doubleword
let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
@@ -1689,9 +1722,10 @@
let Inst{15-12} = Rd;
}
-def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins so_reg:$src),
+def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
DPSoRegFrm, IIC_iMOVsr,
- "mov", "\t$Rd, $src", [(set GPR:$Rd, so_reg:$src)]>, UnaryDP {
+ "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg:$src)]>,
+ UnaryDP {
bits<4> Rd;
bits<12> src;
let Inst{15-12} = Rd;
@@ -3165,11 +3199,16 @@
Requires<[IsARM, IsDarwin]>;
// zextload i1 -> zextload i8
-def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
+//def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
+def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
+def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
// extload -> zextload
-def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
-def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
+def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
+def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
+def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
+def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
+
def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrNEON.td?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrNEON.td Wed Oct 27 23:47:43 2010
@@ -1730,33 +1730,33 @@
// both double- and quad-register.
class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
- : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
- (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
- OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
- [(set DPR:$dst, (Ty (add DPR:$src1,
- (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
+ : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
+ (ins DPR:$src1, DPR:$Vm, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
+ OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
+ [(set DPR:$Vd, (Ty (add DPR:$src1,
+ (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
- : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
- (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
- OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
- [(set QPR:$dst, (Ty (add QPR:$src1,
- (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
+ : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
+ (ins QPR:$src1, QPR:$Vm, i32imm:$SIMM), N2RegVShRFrm, IIC_VPALiD,
+ OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
+ [(set QPR:$Vd, (Ty (add QPR:$src1,
+ (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
// Shift by immediate and insert,
// both double- and quad-register.
class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
- : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$dst),
- (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), f, IIC_VSHLiD,
- OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
- [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
+ : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
+ (ins DPR:$src1, DPR:$Vm, i32imm:$SIMM), f, IIC_VSHLiD,
+ OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
+ [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
Format f, string OpcodeStr, string Dt, ValueType Ty,SDNode ShOp>
- : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$dst),
- (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), f, IIC_VSHLiQ,
- OpcodeStr, Dt, "$dst, $src2, $SIMM", "$src1 = $dst",
- [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
+ : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
+ (ins QPR:$src1, QPR:$Vm, i32imm:$SIMM), f, IIC_VSHLiQ,
+ OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
+ [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
// Convert, with fractional bits immediate,
// both double- and quad-register.
@@ -1764,16 +1764,16 @@
string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
Intrinsic IntOp>
: N2VImm<op24, op23, op11_8, op7, 0, op4,
- (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), NVCVTFrm,
- IIC_VUNAD, OpcodeStr, Dt, "$dst, $src, $SIMM", "",
- [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
+ (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
+ IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
+ [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
Intrinsic IntOp>
: N2VImm<op24, op23, op11_8, op7, 1, op4,
- (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), NVCVTFrm,
- IIC_VUNAQ, OpcodeStr, Dt, "$dst, $src, $SIMM", "",
- [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
+ (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
+ IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
+ [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
//===----------------------------------------------------------------------===//
// Multiclasses
@@ -3501,30 +3501,44 @@
// VMOV : Vector Get Lane (move scalar to ARM core register)
def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
- (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
- IIC_VMOVSI, "vmov", "s8", "$dst, $src[$lane]",
- [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
- imm:$lane))]>;
+ (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
+ IIC_VMOVSI, "vmov", "s8", "$R, $V[$lane]",
+ [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
+ imm:$lane))]> {
+ let Inst{21} = lane{2};
+ let Inst{6-5} = lane{1-0};
+}
def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
- (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
- IIC_VMOVSI, "vmov", "s16", "$dst, $src[$lane]",
- [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
- imm:$lane))]>;
+ (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
+ IIC_VMOVSI, "vmov", "s16", "$R, $V[$lane]",
+ [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
+ imm:$lane))]> {
+ let Inst{21} = lane{1};
+ let Inst{6} = lane{0};
+}
def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
- (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
- IIC_VMOVSI, "vmov", "u8", "$dst, $src[$lane]",
- [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
- imm:$lane))]>;
+ (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
+ IIC_VMOVSI, "vmov", "u8", "$R, $V[$lane]",
+ [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
+ imm:$lane))]> {
+ let Inst{21} = lane{2};
+ let Inst{6-5} = lane{1-0};
+}
def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
- (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
- IIC_VMOVSI, "vmov", "u16", "$dst, $src[$lane]",
- [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
- imm:$lane))]>;
+ (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
+ IIC_VMOVSI, "vmov", "u16", "$R, $V[$lane]",
+ [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
+ imm:$lane))]> {
+ let Inst{21} = lane{1};
+ let Inst{6} = lane{0};
+}
def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
- (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
- IIC_VMOVSI, "vmov", "32", "$dst, $src[$lane]",
- [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
- imm:$lane))]>;
+ (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
+ IIC_VMOVSI, "vmov", "32", "$R, $V[$lane]",
+ [(set GPR:$R, (extractelt (v2i32 DPR:$V),
+ imm:$lane))]> {
+ let Inst{21} = lane{0};
+}
// def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
(VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
@@ -3560,22 +3574,30 @@
// VMOV : Vector Set Lane (move ARM core register to scalar)
-let Constraints = "$src1 = $dst" in {
-def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$dst),
- (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
- IIC_VMOVISL, "vmov", "8", "$dst[$lane], $src2",
- [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
- GPR:$src2, imm:$lane))]>;
-def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$dst),
- (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
- IIC_VMOVISL, "vmov", "16", "$dst[$lane], $src2",
- [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
- GPR:$src2, imm:$lane))]>;
-def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$dst),
- (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
- IIC_VMOVISL, "vmov", "32", "$dst[$lane], $src2",
- [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
- GPR:$src2, imm:$lane))]>;
+let Constraints = "$src1 = $V" in {
+def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
+ (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
+ IIC_VMOVISL, "vmov", "8", "$V[$lane], $R",
+ [(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
+ GPR:$R, imm:$lane))]> {
+ let Inst{21} = lane{2};
+ let Inst{6-5} = lane{1-0};
+}
+def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
+ (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
+ IIC_VMOVISL, "vmov", "16", "$V[$lane], $R",
+ [(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
+ GPR:$R, imm:$lane))]> {
+ let Inst{21} = lane{1};
+ let Inst{6} = lane{0};
+}
+def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
+ (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
+ IIC_VMOVISL, "vmov", "32", "$V[$lane], $R",
+ [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
+ GPR:$R, imm:$lane))]> {
+ let Inst{21} = lane{0};
+}
}
def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
(v16i8 (INSERT_SUBREG QPR:$src1,
@@ -3679,14 +3701,30 @@
// Inst{19-16} is partially specified depending on the element size.
-def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8>;
-def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16>;
-def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32>;
-def VDUPLNfd : VDUPLND<{?,1,0,0}, "vdup", "32", v2f32>;
-def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8>;
-def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16>;
-def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32>;
-def VDUPLNfq : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4f32, v2f32>;
+def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8> {
+ let Inst{19-17} = lane{2-0};
+}
+def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16> {
+ let Inst{19-18} = lane{1-0};
+}
+def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32> {
+ let Inst{19} = lane{0};
+}
+def VDUPLNfd : VDUPLND<{?,1,0,0}, "vdup", "32", v2f32> {
+ let Inst{19} = lane{0};
+}
+def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8> {
+ let Inst{19-17} = lane{2-0};
+}
+def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16> {
+ let Inst{19-18} = lane{1-0};
+}
+def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32> {
+ let Inst{19} = lane{0};
+}
+def VDUPLNfq : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4f32, v2f32> {
+ let Inst{19} = lane{0};
+}
def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
(v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
@@ -3833,14 +3871,20 @@
(ins DPR:$lhs, DPR:$rhs, i32imm:$index), NVExtFrm,
IIC_VEXTD, OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
[(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
- (Ty DPR:$rhs), imm:$index)))]>;
+ (Ty DPR:$rhs), imm:$index)))]> {
+ bits<4> index;
+ let Inst{11-8} = index{3-0};
+}
class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
: N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$dst),
(ins QPR:$lhs, QPR:$rhs, i32imm:$index), NVExtFrm,
IIC_VEXTQ, OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "",
[(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
- (Ty QPR:$rhs), imm:$index)))]>;
+ (Ty QPR:$rhs), imm:$index)))]> {
+ bits<4> index;
+ let Inst{11-8} = index{3-0};
+}
def VEXTd8 : VEXTd<"vext", "8", v8i8>;
def VEXTd16 : VEXTd<"vext", "16", v4i16>;
@@ -3886,24 +3930,24 @@
// VTBL : Vector Table Lookup
def VTBL1
- : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$dst),
- (ins DPR:$tbl1, DPR:$src), NVTBLFrm, IIC_VTB1,
- "vtbl", "8", "$dst, \\{$tbl1\\}, $src", "",
- [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>;
+ : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
+ (ins DPR:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
+ "vtbl", "8", "$Vd, \\{$Vn\\}, $Vm", "",
+ [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 DPR:$Vn, DPR:$Vm)))]>;
let hasExtraSrcRegAllocReq = 1 in {
def VTBL2
- : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst),
- (ins DPR:$tbl1, DPR:$tbl2, DPR:$src), NVTBLFrm, IIC_VTB2,
- "vtbl", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "", []>;
+ : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
+ (ins DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTB2,
+ "vtbl", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "", []>;
def VTBL3
- : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$dst),
- (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), NVTBLFrm, IIC_VTB3,
- "vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src", "", []>;
+ : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
+ (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm), NVTBLFrm, IIC_VTB3,
+ "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm", "", []>;
def VTBL4
- : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$dst),
- (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src),
+ : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
+ (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm),
NVTBLFrm, IIC_VTB4,
- "vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src", "", []>;
+ "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm", "", []>;
} // hasExtraSrcRegAllocReq = 1
def VTBL2Pseudo
@@ -3915,27 +3959,27 @@
// VTBX : Vector Table Extension
def VTBX1
- : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst),
- (ins DPR:$orig, DPR:$tbl1, DPR:$src), NVTBLFrm, IIC_VTBX1,
- "vtbx", "8", "$dst, \\{$tbl1\\}, $src", "$orig = $dst",
- [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1
- DPR:$orig, DPR:$tbl1, DPR:$src)))]>;
+ : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
+ (ins DPR:$orig, DPR:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1,
+ "vtbx", "8", "$Vd, \\{$Vn\\}, $Vm", "$orig = $Vd",
+ [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
+ DPR:$orig, DPR:$Vn, DPR:$Vm)))]>;
let hasExtraSrcRegAllocReq = 1 in {
def VTBX2
- : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst),
- (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), NVTBLFrm, IIC_VTBX2,
- "vtbx", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "$orig = $dst", []>;
+ : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
+ (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
+ "vtbx", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "$orig = $Vd", []>;
def VTBX3
- : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$dst),
- (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src),
+ : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
+ (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm),
NVTBLFrm, IIC_VTBX3,
- "vtbx", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src",
- "$orig = $dst", []>;
+ "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm",
+ "$orig = $Vd", []>;
def VTBX4
- : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1,
- DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), NVTBLFrm, IIC_VTBX4,
- "vtbx", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src",
- "$orig = $dst", []>;
+ : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd), (ins DPR:$orig, DPR:$Vn,
+ DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
+ "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm",
+ "$orig = $Vd", []>;
} // hasExtraSrcRegAllocReq = 1
def VTBX2Pseudo
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Wed Oct 27 23:47:43 2010
@@ -133,7 +133,7 @@
case ARM::LDRi12:
++NumLDMGened;
return ARM::LDM;
- case ARM::STR:
+ case ARM::STRi12:
++NumSTMGened;
return ARM::STM;
case ARM::t2LDRi8:
@@ -174,7 +174,7 @@
}
static bool isi32Store(unsigned Opc) {
- return Opc == ARM::STR || isT2i32Store(Opc);
+ return Opc == ARM::STRi12 || isT2i32Store(Opc);
}
/// MergeOps - Create and insert a LDM or STM with Base as base register and
@@ -441,7 +441,7 @@
switch (MI->getOpcode()) {
default: return 0;
case ARM::LDRi12:
- case ARM::STR:
+ case ARM::STRi12:
case ARM::t2LDRi8:
case ARM::t2LDRi12:
case ARM::t2STRi8:
@@ -579,7 +579,7 @@
static unsigned getPreIndexedLoadStoreOpcode(unsigned Opc) {
switch (Opc) {
case ARM::LDRi12: return ARM::LDR_PRE;
- case ARM::STR: return ARM::STR_PRE;
+ case ARM::STRi12: return ARM::STR_PRE;
case ARM::VLDRS: return ARM::VLDMS_UPD;
case ARM::VLDRD: return ARM::VLDMD_UPD;
case ARM::VSTRS: return ARM::VSTMS_UPD;
@@ -598,7 +598,7 @@
static unsigned getPostIndexedLoadStoreOpcode(unsigned Opc) {
switch (Opc) {
case ARM::LDRi12: return ARM::LDR_POST;
- case ARM::STR: return ARM::STR_POST;
+ case ARM::STRi12: return ARM::STR_POST;
case ARM::VLDRS: return ARM::VLDMS_UPD;
case ARM::VLDRD: return ARM::VLDMD_UPD;
case ARM::VSTRS: return ARM::VSTMS_UPD;
@@ -629,16 +629,10 @@
DebugLoc dl = MI->getDebugLoc();
bool isAM5 = (Opcode == ARM::VLDRD || Opcode == ARM::VLDRS ||
Opcode == ARM::VSTRD || Opcode == ARM::VSTRS);
- bool isAM2 = (Opcode == ARM::LDRi12 || Opcode == ARM::STR);
- // FIXME: This special handling of LDRi12 is hackery until all of the ARM
- // LDR/STR insns are moved away from the addrmode2 mega-instruction to
- // the split (LDRi12/LDRrs) style instructions.
- if (Opcode == ARM::LDRi12 || isT2i32Load(Opcode) || isT2i32Store(Opcode))
+ bool isAM2 = (Opcode == ARM::LDRi12 || Opcode == ARM::STRi12);
+ if (isi32Load(Opcode) || isi32Store(Opcode))
if (MI->getOperand(2).getImm() != 0)
return false;
- if (isAM2 && Opcode != ARM::LDRi12
- && ARM_AM::getAM2Offset(MI->getOperand(3).getImm()) != 0)
- return false;
if (isAM5 && ARM_AM::getAM5Offset(MI->getOperand(2).getImm()) != 0)
return false;
@@ -786,8 +780,6 @@
int Opcode = MI->getOpcode();
switch (Opcode) {
default: break;
- case ARM::STR:
- return MI->getOperand(1).isReg() && MI->getOperand(2).getReg() == 0;
case ARM::VLDRS:
case ARM::VSTRS:
return MI->getOperand(1).isReg();
@@ -795,6 +787,7 @@
case ARM::VSTRD:
return MI->getOperand(1).isReg();
case ARM::LDRi12:
+ case ARM::STRi12:
case ARM::t2LDRi8:
case ARM::t2LDRi12:
case ARM::t2STRi8:
@@ -822,7 +815,6 @@
static int getMemoryOpOffset(const MachineInstr *MI) {
int Opcode = MI->getOpcode();
- bool isAM2 = Opcode == ARM::STR;
bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD;
unsigned NumOperands = MI->getDesc().getNumOperands();
unsigned OffField = MI->getOperand(NumOperands-3).getImm();
@@ -830,17 +822,12 @@
if (Opcode == ARM::t2LDRi12 || Opcode == ARM::t2LDRi8 ||
Opcode == ARM::t2STRi12 || Opcode == ARM::t2STRi8 ||
Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8 ||
- Opcode == ARM::LDRi12)
+ Opcode == ARM::LDRi12 || Opcode == ARM::STRi12)
return OffField;
- int Offset = isAM2
- ? ARM_AM::getAM2Offset(OffField)
- : (isAM3 ? ARM_AM::getAM3Offset(OffField)
- : ARM_AM::getAM5Offset(OffField) * 4);
- if (isAM2) {
- if (ARM_AM::getAM2Op(OffField) == ARM_AM::sub)
- Offset = -Offset;
- } else if (isAM3) {
+ int Offset = isAM3 ? ARM_AM::getAM3Offset(OffField)
+ : ARM_AM::getAM5Offset(OffField) * 4;
+ if (isAM3) {
if (ARM_AM::getAM3Op(OffField) == ARM_AM::sub)
Offset = -Offset;
} else {
@@ -852,35 +839,24 @@
static void InsertLDR_STR(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &MBBI,
- int OffImm, bool isDef,
+ int Offset, bool isDef,
DebugLoc dl, unsigned NewOpc,
unsigned Reg, bool RegDeadKill, bool RegUndef,
unsigned BaseReg, bool BaseKill, bool BaseUndef,
- unsigned OffReg, bool OffKill, bool OffUndef,
+ bool OffKill, bool OffUndef,
ARMCC::CondCodes Pred, unsigned PredReg,
const TargetInstrInfo *TII, bool isT2) {
- int Offset = OffImm;
- if (!isT2) {
- if (OffImm < 0)
- Offset = ARM_AM::getAM2Opc(ARM_AM::sub, -OffImm, ARM_AM::no_shift);
- else
- Offset = ARM_AM::getAM2Opc(ARM_AM::add, OffImm, ARM_AM::no_shift);
- }
if (isDef) {
MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(),
TII->get(NewOpc))
.addReg(Reg, getDefRegState(true) | getDeadRegState(RegDeadKill))
.addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
- if (!isT2)
- MIB.addReg(OffReg, getKillRegState(OffKill)|getUndefRegState(OffUndef));
MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
} else {
MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(),
TII->get(NewOpc))
.addReg(Reg, getKillRegState(RegDeadKill) | getUndefRegState(RegUndef))
.addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
- if (!isT2)
- MIB.addReg(OffReg, getKillRegState(OffKill)|getUndefRegState(OffUndef));
MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
}
}
@@ -911,14 +887,13 @@
unsigned BaseReg = BaseOp.getReg();
bool BaseKill = BaseOp.isKill();
bool BaseUndef = BaseOp.isUndef();
- unsigned OffReg = isT2 ? 0 : MI->getOperand(3).getReg();
bool OffKill = isT2 ? false : MI->getOperand(3).isKill();
bool OffUndef = isT2 ? false : MI->getOperand(3).isUndef();
int OffImm = getMemoryOpOffset(MI);
unsigned PredReg = 0;
ARMCC::CondCodes Pred = llvm::getInstrPredicate(MI, PredReg);
- if (OddRegNum > EvenRegNum && OffReg == 0 && OffImm == 0) {
+ if (OddRegNum > EvenRegNum && OffImm == 0) {
// Ascending register numbers and no offset. It's safe to change it to a
// ldm or stm.
unsigned NewOpc = (isLd)
@@ -946,28 +921,24 @@
NewBBI = llvm::prior(MBBI);
} else {
// Split into two instructions.
- assert((!isT2 || !OffReg) &&
- "Thumb2 ldrd / strd does not encode offset register!");
unsigned NewOpc = (isLd)
? (isT2 ? (OffImm < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12)
- : (isT2 ? (OffImm < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STR);
+ : (isT2 ? (OffImm < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STRi12);
DebugLoc dl = MBBI->getDebugLoc();
// If this is a load and base register is killed, it may have been
// re-defed by the load, make sure the first load does not clobber it.
if (isLd &&
(BaseKill || OffKill) &&
- (TRI->regsOverlap(EvenReg, BaseReg) ||
- (OffReg && TRI->regsOverlap(EvenReg, OffReg)))) {
- assert(!TRI->regsOverlap(OddReg, BaseReg) &&
- (!OffReg || !TRI->regsOverlap(OddReg, OffReg)));
+ (TRI->regsOverlap(EvenReg, BaseReg))) {
+ assert(!TRI->regsOverlap(OddReg, BaseReg));
InsertLDR_STR(MBB, MBBI, OffImm+4, isLd, dl, NewOpc,
OddReg, OddDeadKill, false,
- BaseReg, false, BaseUndef, OffReg, false, OffUndef,
+ BaseReg, false, BaseUndef, false, OffUndef,
Pred, PredReg, TII, isT2);
NewBBI = llvm::prior(MBBI);
InsertLDR_STR(MBB, MBBI, OffImm, isLd, dl, NewOpc,
EvenReg, EvenDeadKill, false,
- BaseReg, BaseKill, BaseUndef, OffReg, OffKill, OffUndef,
+ BaseReg, BaseKill, BaseUndef, OffKill, OffUndef,
Pred, PredReg, TII, isT2);
} else {
if (OddReg == EvenReg && EvenDeadKill) {
@@ -979,12 +950,12 @@
}
InsertLDR_STR(MBB, MBBI, OffImm, isLd, dl, NewOpc,
EvenReg, EvenDeadKill, EvenUndef,
- BaseReg, false, BaseUndef, OffReg, false, OffUndef,
+ BaseReg, false, BaseUndef, false, OffUndef,
Pred, PredReg, TII, isT2);
NewBBI = llvm::prior(MBBI);
InsertLDR_STR(MBB, MBBI, OffImm+4, isLd, dl, NewOpc,
OddReg, OddDeadKill, OddUndef,
- BaseReg, BaseKill, BaseUndef, OffReg, OffKill, OffUndef,
+ BaseReg, BaseKill, BaseUndef, OffKill, OffUndef,
Pred, PredReg, TII, isT2);
}
if (isLd)
@@ -1256,7 +1227,7 @@
bool CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1, DebugLoc &dl,
unsigned &NewOpc, unsigned &EvenReg,
unsigned &OddReg, unsigned &BaseReg,
- unsigned &OffReg, int &Offset,
+ int &Offset,
unsigned &PredReg, ARMCC::CondCodes &Pred,
bool &isT2);
bool RescheduleOps(MachineBasicBlock *MBB,
@@ -1336,8 +1307,7 @@
DebugLoc &dl,
unsigned &NewOpc, unsigned &EvenReg,
unsigned &OddReg, unsigned &BaseReg,
- unsigned &OffReg, int &Offset,
- unsigned &PredReg,
+ int &Offset, unsigned &PredReg,
ARMCC::CondCodes &Pred,
bool &isT2) {
// Make sure we're allowed to generate LDRD/STRD.
@@ -1349,7 +1319,7 @@
unsigned Opcode = Op0->getOpcode();
if (Opcode == ARM::LDRi12)
NewOpc = ARM::LDRD;
- else if (Opcode == ARM::STR)
+ else if (Opcode == ARM::STRi12)
NewOpc = ARM::STRD;
else if (Opcode == ARM::t2LDRi8 || Opcode == ARM::t2LDRi12) {
NewOpc = ARM::t2LDRDi8;
@@ -1362,11 +1332,6 @@
} else
return false;
- // Make sure the offset registers match.
- if (!isT2 && Opcode != ARM::LDRi12 &&
- (Op0->getOperand(2).getReg() != Op1->getOperand(2).getReg()))
- return false;
-
// Make sure the base address satisfies i64 ld / st alignment requirement.
if (!Op0->hasOneMemOperand() ||
!(*Op0->memoperands_begin())->getValue() ||
@@ -1376,7 +1341,7 @@
unsigned Align = (*Op0->memoperands_begin())->getAlignment();
const Function *Func = MF->getFunction();
unsigned ReqAlign = STI->hasV6Ops()
- ? TD->getABITypeAlignment(Type::getInt64Ty(Func->getContext()))
+ ? TD->getABITypeAlignment(Type::getInt64Ty(Func->getContext()))
: 8; // Pre-v6 need 8-byte align
if (Align < ReqAlign)
return false;
@@ -1410,8 +1375,6 @@
if (EvenReg == OddReg)
return false;
BaseReg = Op0->getOperand(1).getReg();
- if (!isT2 && Opcode != ARM::LDRi12)
- OffReg = Op0->getOperand(2).getReg();
Pred = llvm::getInstrPredicate(Op0, PredReg);
dl = Op0->getDebugLoc();
return true;
@@ -1499,14 +1462,14 @@
MachineInstr *Op0 = Ops.back();
MachineInstr *Op1 = Ops[Ops.size()-2];
unsigned EvenReg = 0, OddReg = 0;
- unsigned BaseReg = 0, OffReg = 0, PredReg = 0;
+ unsigned BaseReg = 0, PredReg = 0;
ARMCC::CondCodes Pred = ARMCC::AL;
bool isT2 = false;
unsigned NewOpc = 0;
int Offset = 0;
DebugLoc dl;
if (NumMove == 2 && CanFormLdStDWord(Op0, Op1, dl, NewOpc,
- EvenReg, OddReg, BaseReg, OffReg,
+ EvenReg, OddReg, BaseReg,
Offset, PredReg, Pred, isT2)) {
Ops.pop_back();
Ops.pop_back();
@@ -1518,10 +1481,9 @@
.addReg(EvenReg, RegState::Define)
.addReg(OddReg, RegState::Define)
.addReg(BaseReg);
- // For now, we're converting from LDRi12 to an insn that still
+ // FIXME: We're converting from LDRi12 to an insn that still
// uses addrmode2, so we need an explicit offset reg. It should
- // always by reg0 since we're transforming LDRi12s. The old
- // was just being paranoid in allowing for anything else.
+ // always by reg0 since we're transforming LDRi12s.
if (!isT2)
MIB.addReg(0);
MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
@@ -1532,8 +1494,11 @@
.addReg(EvenReg)
.addReg(OddReg)
.addReg(BaseReg);
+ // FIXME: We're converting from LDRi12 to an insn that still
+ // uses addrmode2, so we need an explicit offset reg. It should
+ // always by reg0 since we're transforming STRi12s.
if (!isT2)
- MIB.addReg(OffReg);
+ MIB.addReg(0);
MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
++NumSTRDFormed;
}
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMMCCodeEmitter.cpp Wed Oct 27 23:47:43 2010
@@ -91,6 +91,10 @@
unsigned getImmMinusOneOpValue(const MCInst &MI, unsigned Op) const {
return MI.getOperand(Op).getImm() - 1;
}
+
+ unsigned getNEONVcvtImm32(const MCInst &MI, unsigned Op) const {
+ return 64 - MI.getOperand(Op).getImm();
+ }
unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op) const;
Modified: llvm/branches/wendling/eh/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Wed Oct 27 23:47:43 2010
@@ -612,8 +612,11 @@
O << "[" << getRegisterName(MO1.getReg());
- unsigned OffImm = MO2.getImm();
- if (OffImm) // Don't print +0.
+ int32_t OffImm = (int32_t)MO2.getImm();
+ // Don't print +0.
+ if (OffImm < 0)
+ O << ", #-" << -OffImm;
+ else if (OffImm > 0)
O << ", #" << OffImm;
O << "]";
}
Modified: llvm/branches/wendling/eh/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp Wed Oct 27 23:47:43 2010
@@ -72,10 +72,6 @@
bool ParseDirectiveWord(unsigned Size, SMLoc L);
- bool ParseDirectiveThumb(SMLoc L);
-
- bool ParseDirectiveThumbFunc(SMLoc L);
-
bool ParseDirectiveCode(SMLoc L);
bool ParseDirectiveSyntax(SMLoc L);
@@ -750,10 +746,6 @@
StringRef IDVal = DirectiveID.getIdentifier();
if (IDVal == ".word")
return ParseDirectiveWord(4, DirectiveID.getLoc());
- else if (IDVal == ".thumb")
- return ParseDirectiveThumb(DirectiveID.getLoc());
- else if (IDVal == ".thumb_func")
- return ParseDirectiveThumbFunc(DirectiveID.getLoc());
else if (IDVal == ".code")
return ParseDirectiveCode(DirectiveID.getLoc());
else if (IDVal == ".syntax")
@@ -786,36 +778,6 @@
return false;
}
-/// ParseDirectiveThumb
-/// ::= .thumb
-bool MBlazeAsmParser::ParseDirectiveThumb(SMLoc L) {
- if (getLexer().isNot(AsmToken::EndOfStatement))
- return Error(L, "unexpected token in directive");
- Parser.Lex();
-
- // TODO: set thumb mode
- // TODO: tell the MC streamer the mode
- // getParser().getStreamer().Emit???();
- return false;
-}
-
-/// ParseDirectiveThumbFunc
-/// ::= .thumbfunc symbol_name
-bool MBlazeAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
- const AsmToken &Tok = Parser.getTok();
- if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
- return Error(L, "unexpected token in .syntax directive");
- Parser.Lex(); // Consume the identifier token.
-
- if (getLexer().isNot(AsmToken::EndOfStatement))
- return Error(L, "unexpected token in directive");
- Parser.Lex();
-
- // TODO: mark symbol as a thumb symbol
- // getParser().getStreamer().Emit???();
- return false;
-}
-
/// ParseDirectiveSyntax
/// ::= .syntax unified | divided
bool MBlazeAsmParser::ParseDirectiveSyntax(SMLoc L) {
Modified: llvm/branches/wendling/eh/lib/Target/MBlaze/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/MBlaze/CMakeLists.txt?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/MBlaze/CMakeLists.txt (original)
+++ llvm/branches/wendling/eh/lib/Target/MBlaze/CMakeLists.txt Wed Oct 27 23:47:43 2010
@@ -12,6 +12,7 @@
tablegen(MBlazeGenCallingConv.inc -gen-callingconv)
tablegen(MBlazeGenSubtarget.inc -gen-subtarget)
tablegen(MBlazeGenIntrinsics.inc -gen-tgt-intrinsic)
+tablegen(MBlazeGenEDInfo.inc -gen-enhanced-disassembly-info)
add_llvm_target(MBlazeCodeGen
MBlazeDelaySlotFiller.cpp
Modified: llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeDelaySlotFiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeDelaySlotFiller.cpp?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeDelaySlotFiller.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeDelaySlotFiller.cpp Wed Oct 27 23:47:43 2010
@@ -7,7 +7,8 @@
//
//===----------------------------------------------------------------------===//
//
-// Simple pass to fills delay slots with NOPs.
+// A pass that attempts to fill instructions with delay slots. If no
+// instructions can be moved into the delay slot then a NOP is placed there.
//
//===----------------------------------------------------------------------===//
Modified: llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeInstrFSL.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeInstrFSL.td?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeInstrFSL.td (original)
+++ llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeInstrFSL.td Wed Oct 27 23:47:43 2010
@@ -11,7 +11,7 @@
// FSL Instruction Formats
//===----------------------------------------------------------------------===//
class FSLGet<bits<6> op, bits<5> flags, string instr_asm, Intrinsic OpNode> :
- MBlazeInst<op, FFSL, (outs GPR:$dst), (ins fslimm:$b),
+ MBlazeInst<op, FRCX, (outs GPR:$dst), (ins fslimm:$b),
!strconcat(instr_asm, " $dst, $b"),
[(set GPR:$dst, (OpNode immZExt4:$b))],IIAlu>
{
@@ -27,7 +27,7 @@
}
class FSLGetD<bits<6> op, bits<5> flags, string instr_asm, Intrinsic OpNode> :
- MBlazeInst<op, FFSLD, (outs GPR:$dst), (ins GPR:$b),
+ MBlazeInst<op, FRCR, (outs GPR:$dst), (ins GPR:$b),
!strconcat(instr_asm, " $dst, $b"),
[(set GPR:$dst, (OpNode GPR:$b))], IIAlu>
{
@@ -43,7 +43,7 @@
}
class FSLPut<bits<6> op, bits<4> flags, string instr_asm, Intrinsic OpNode> :
- MBlazeInst<op, FFSL, (outs), (ins GPR:$v, fslimm:$b),
+ MBlazeInst<op, FCRCX, (outs), (ins GPR:$v, fslimm:$b),
!strconcat(instr_asm, " $v, $b"),
[(OpNode GPR:$v, immZExt4:$b)], IIAlu>
{
@@ -59,7 +59,7 @@
}
class FSLPutD<bits<6> op, bits<4> flags, string instr_asm, Intrinsic OpNode> :
- MBlazeInst<op, FFSLD, (outs), (ins GPR:$v, GPR:$b),
+ MBlazeInst<op, FCRR, (outs), (ins GPR:$v, GPR:$b),
!strconcat(instr_asm, " $v, $b"),
[(OpNode GPR:$v, GPR:$b)], IIAlu>
{
@@ -75,7 +75,7 @@
}
class FSLPutT<bits<6> op, bits<4> flags, string instr_asm, Intrinsic OpNode> :
- MBlazeInst<op, FFSLT, (outs), (ins fslimm:$b),
+ MBlazeInst<op, FCX, (outs), (ins fslimm:$b),
!strconcat(instr_asm, " $b"),
[(OpNode immZExt4:$b)], IIAlu>
{
@@ -90,7 +90,7 @@
}
class FSLPutTD<bits<6> op, bits<4> flags, string instr_asm, Intrinsic OpNode> :
- MBlazeInst<op, FFSLTD, (outs), (ins GPR:$b),
+ MBlazeInst<op, FCR, (outs), (ins GPR:$b),
!strconcat(instr_asm, " $b"),
[(OpNode GPR:$b)], IIAlu>
{
Modified: llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeInstrFormats.td?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeInstrFormats.td (original)
+++ llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeInstrFormats.td Wed Oct 27 23:47:43 2010
@@ -15,17 +15,24 @@
}
def FPseudo : Format<0>;
-def FRRR : Format<1>;
-def FRRI : Format<2>;
-def FRIR : Format<3>;
-def FFSL : Format<4>;
-def FFSLD : Format<5>;
-def FFSLT : Format<6>;
-def FFSLTD : Format<7>;
-def FR : Format<8>;
-def FI : Format<9>;
-def FRR : Format<10>;
-def FRI : Format<11>;
+def FRRR : Format<1>; // ADD, RSUB, OR, etc.
+def FRRI : Format<2>; // ADDI, RSUBI, ORI, etc.
+def FCRR : Format<3>; // PUTD, WDC, WIC, BEQ, BNE, BGE, etc.
+def FCRI : Format<4>; // RTID, RTED, RTSD, BEQI, BNEI, BGEI, etc.
+def FRCR : Format<5>; // BRLD, BRALD, GETD
+def FRCI : Format<6>; // BRLID, BRALID, MSRCLR, MSRSET
+def FCCR : Format<7>; // BR, BRA, BRD, etc.
+def FCCI : Format<8>; // IMM, BRI, BRAI, BRID, etc.
+def FRRCI : Format<9>; // BSRLI, BSRAI, BSLLI
+def FRRC : Format<10>; // SEXT8, SEXT16, SRA, SRC, SRL, FLT, FINT, FSQRT
+def FRCX : Format<11>; // GET
+def FRCS : Format<12>; // MFS
+def FCRCS : Format<13>; // MTS
+def FCRCX : Format<14>; // PUT
+def FCX : Format<15>; // TPUT
+def FCR : Format<16>; // TPUTD
+def FRIR : Format<17>; // RSUBI
+def FC : Format<18>; // NOP
//===----------------------------------------------------------------------===//
// Describe MBlaze instructions format
Modified: llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeInstrInfo.h?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeInstrInfo.h (original)
+++ llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeInstrInfo.h Wed Oct 27 23:47:43 2010
@@ -138,21 +138,26 @@
// PseudoFrm - This represents an instruction that is a pseudo instruction
// or one that has not been implemented yet. It is illegal to code generate
// it, but tolerated for intermediate implementation stages.
- Pseudo = 0,
-
- RegRegReg = 1,
- RegRegImm = 2,
- RegImmReg = 3,
- FSL = 4,
- FSLD = 5,
- FSLT = 6,
- FSLTD = 7,
- Reg = 8,
- Imm = 9,
- RegReg = 10,
- RegImm = 11,
-
- FormMask = 63
+ FPseudo = 0,
+ FRRR,
+ FRRI,
+ FCRR,
+ FCRI,
+ FRCR,
+ FRCI,
+ FCCR,
+ FCCI,
+ FRRCI,
+ FRRC,
+ FRCX,
+ FRCS,
+ FCRCS,
+ FCRCX,
+ FCX,
+ FCR,
+ FRIR,
+ FC,
+ FormMask = 63
//===------------------------------------------------------------------===//
// MBlaze Specific MachineOperand flags.
Modified: llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeInstrInfo.td?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeInstrInfo.td (original)
+++ llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeInstrInfo.td Wed Oct 27 23:47:43 2010
@@ -203,6 +203,11 @@
[(set GPR:$dst, (OpNode GPR:$b, immZExt16:$c))],
IIAlu>;
+class PatCmp<bits<6> op, bits<11> flags, string instr_asm> :
+ TA<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
+ !strconcat(instr_asm, " $dst, $b, $c"),
+ [], IIAlu>;
+
//===----------------------------------------------------------------------===//
// Memory Access Instructions
//===----------------------------------------------------------------------===//
@@ -211,6 +216,11 @@
!strconcat(instr_asm, " $dst, $addr"),
[(set (i32 GPR:$dst), (OpNode xaddr:$addr))], IILoad>;
+class LoadW<bits<6> op, bits<11> flags, string instr_asm> :
+ TA<op, flags, (outs GPR:$dst), (ins memrr:$addr),
+ !strconcat(instr_asm, " $dst, $addr"),
+ [], IILoad>;
+
class LoadMI<bits<6> op, string instr_asm, PatFrag OpNode> :
TBR<op, (outs GPR:$dst), (ins memri:$addr),
!strconcat(instr_asm, " $dst, $addr"),
@@ -221,6 +231,11 @@
!strconcat(instr_asm, " $dst, $addr"),
[(OpNode (i32 GPR:$dst), xaddr:$addr)], IIStore>;
+class StoreW<bits<6> op, bits<11> flags, string instr_asm> :
+ TA<op, flags, (outs), (ins GPR:$dst, memrr:$addr),
+ !strconcat(instr_asm, " $dst, $addr"),
+ [], IIStore>;
+
class StoreMI<bits<6> op, string instr_asm, PatFrag OpNode> :
TBR<op, (outs), (ins GPR:$dst, memri:$addr),
!strconcat(instr_asm, " $dst, $addr"),
@@ -231,10 +246,11 @@
//===----------------------------------------------------------------------===//
class Branch<bits<6> op, bits<5> br, bits<11> flags, string instr_asm> :
TA<op, flags, (outs), (ins GPR:$target),
- !strconcat(instr_asm, " $target"),
- [], IIBranch> {
+ !strconcat(instr_asm, " $target"),
+ [], IIBranch> {
let rd = 0x0;
let ra = br;
+ let Form = FCCR;
}
class BranchI<bits<6> op, bits<5> br, string instr_asm> :
@@ -243,25 +259,26 @@
[], IIBranch> {
let rd = 0;
let ra = br;
+ let Form = FCCI;
}
//===----------------------------------------------------------------------===//
// Branch and Link Instructions
//===----------------------------------------------------------------------===//
class BranchL<bits<6> op, bits<5> br, bits<11> flags, string instr_asm> :
- TA<op, flags, (outs), (ins GPR:$target),
- !strconcat(instr_asm, " r15, $target"),
+ TA<op, flags, (outs), (ins GPR:$link, GPR:$target),
+ !strconcat(instr_asm, " $link, $target"),
[], IIBranch> {
- let rd = 15;
let ra = br;
+ let Form = FRCR;
}
class BranchLI<bits<6> op, bits<5> br, string instr_asm> :
- TB<op, (outs), (ins calltarget:$target),
- !strconcat(instr_asm, " r15, $target"),
+ TB<op, (outs), (ins GPR:$link, calltarget:$target),
+ !strconcat(instr_asm, " $link, $target"),
[], IIBranch> {
- let rd = 15;
let ra = br;
+ let Form = FRCI;
}
//===----------------------------------------------------------------------===//
@@ -274,6 +291,7 @@
!strconcat(instr_asm, " $a, $b, $offset"),
[], IIBranch> {
let rd = br;
+ let Form = FCRR;
}
class BranchCI<bits<6> op, bits<5> br, string instr_asm, PatFrag cond_op> :
@@ -281,6 +299,7 @@
!strconcat(instr_asm, " $a, $offset"),
[], IIBranch> {
let rd = br;
+ let Form = FCRI;
}
//===----------------------------------------------------------------------===//
@@ -295,6 +314,9 @@
def AND : Logic<0x21, 0x000, "and ", and>;
def OR : Logic<0x20, 0x000, "or ", or>;
def XOR : Logic<0x22, 0x000, "xor ", xor>;
+ def PCMPBF : PatCmp<0x20, 0x400, "pcmpbf ">;
+ def PCMPEQ : PatCmp<0x23, 0x400, "pcmpeq ">;
+ def PCMPNE : PatCmp<0x22, 0x400, "pcmpne ">;
}
let isAsCheapAsAMove = 1 in {
@@ -364,7 +386,10 @@
let canFoldAsLoad = 1, isReMaterializable = 1 in {
def LBU : LoadM<0x30, "lbu ", zextloadi8>;
def LHU : LoadM<0x31, "lhu ", zextloadi16>;
- def LW : LoadM<0x32, "lw ", load>;
+
+ def LW : LoadW<0x32, 0x0, "lw ">;
+ def LWR : LoadW<0x32, 0x2, "lwr ">;
+ def LWX : LoadW<0x32, 0x4, "lwx ">;
def LBUI : LoadMI<0x38, "lbui ", zextloadi8>;
def LHUI : LoadMI<0x39, "lhui ", zextloadi16>;
@@ -373,7 +398,10 @@
def SB : StoreM<0x34, "sb ", truncstorei8>;
def SH : StoreM<0x35, "sh ", truncstorei16>;
- def SW : StoreM<0x36, "sw ", store>;
+
+ def SW : StoreW<0x36, 0x0, "sw ">;
+ def SWR : StoreW<0x36, 0x2, "swr ">;
+ def SWX : StoreW<0x36, 0x4, "swx ">;
def SBI : StoreMI<0x3C, "sbi ", truncstorei8>;
def SHI : StoreMI<0x3D, "shi ", truncstorei16>;
@@ -383,13 +411,12 @@
// MBlaze branch instructions
//===----------------------------------------------------------------------===//
-let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, isBarrier = 1,
- Form = FI in {
+let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in {
def BRI : BranchI<0x2E, 0x00, "bri ">;
def BRAI : BranchI<0x2E, 0x08, "brai ">;
}
-let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, Form = FRI in {
+let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in {
def BEQI : BranchCI<0x2F, 0x00, "beqi ", seteq>;
def BNEI : BranchCI<0x2F, 0x01, "bnei ", setne>;
def BLTI : BranchCI<0x2F, 0x02, "blti ", setlt>;
@@ -399,13 +426,12 @@
}
let isBranch = 1, isIndirectBranch = 1, isTerminator = 1, hasCtrlDep = 1,
- isBarrier = 1, Form = FR in {
+ isBarrier = 1 in {
def BR : Branch<0x26, 0x00, 0x000, "br ">;
def BRA : Branch<0x26, 0x08, 0x000, "bra ">;
}
-let isBranch = 1, isIndirectBranch = 1, isTerminator = 1, hasCtrlDep = 1,
- Form = FRR in {
+let isBranch = 1, isIndirectBranch = 1, isTerminator = 1, hasCtrlDep = 1 in {
def BEQ : BranchC<0x27, 0x00, 0x000, "beq ", seteq>;
def BNE : BranchC<0x27, 0x01, 0x000, "bne ", setne>;
def BLT : BranchC<0x27, 0x02, 0x000, "blt ", setlt>;
@@ -415,13 +441,12 @@
}
let isBranch = 1, isTerminator = 1, hasDelaySlot = 1, hasCtrlDep = 1,
- isBarrier = 1, Form = FI in {
+ isBarrier = 1 in {
def BRID : BranchI<0x2E, 0x10, "brid ">;
def BRAID : BranchI<0x2E, 0x18, "braid ">;
}
-let isBranch = 1, isTerminator = 1, hasDelaySlot = 1, hasCtrlDep = 1,
- Form = FRI in {
+let isBranch = 1, isTerminator = 1, hasDelaySlot = 1, hasCtrlDep = 1 in {
def BEQID : BranchCI<0x2F, 0x10, "beqid ", seteq>;
def BNEID : BranchCI<0x2F, 0x11, "bneid ", setne>;
def BLTID : BranchCI<0x2F, 0x12, "bltid ", setlt>;
@@ -430,14 +455,14 @@
def BGEID : BranchCI<0x2F, 0x15, "bgeid ", setge>;
}
-let isBranch = 1, isIndirectBranch = 1, isTerminator = 1, Form = FR,
+let isBranch = 1, isIndirectBranch = 1, isTerminator = 1,
hasDelaySlot = 1, hasCtrlDep = 1, isBarrier = 1 in {
def BRD : Branch<0x26, 0x10, 0x000, "brd ">;
def BRAD : Branch<0x26, 0x18, 0x000, "brad ">;
}
let isBranch = 1, isIndirectBranch = 1, isTerminator = 1,
- hasDelaySlot = 1, hasCtrlDep = 1, Form = FRR in {
+ hasDelaySlot = 1, hasCtrlDep = 1 in {
def BEQD : BranchC<0x27, 0x10, 0x000, "beqd ", seteq>;
def BNED : BranchC<0x27, 0x11, 0x000, "bned ", setne>;
def BLTD : BranchC<0x27, 0x12, 0x000, "bltd ", setlt>;
@@ -446,7 +471,7 @@
def BGED : BranchC<0x27, 0x15, 0x000, "bged ", setge>;
}
-let isCall = 1, hasDelaySlot = 1, hasCtrlDep = 1, isBarrier = 1, Form = FI,
+let isCall = 1, hasDelaySlot = 1, hasCtrlDep = 1, isBarrier = 1,
Defs = [R3,R4,R5,R6,R7,R8,R9,R10,R11,R12],
Uses = [R1,R5,R6,R7,R8,R9,R10] in {
def BRLID : BranchLI<0x2E, 0x14, "brlid ">;
@@ -454,7 +479,7 @@
}
let isCall = 1, hasDelaySlot = 1, hasCtrlDep = 1, isIndirectBranch = 1,
- isBarrier = 1, Form = FR,
+ isBarrier = 1,
Defs = [R3,R4,R5,R6,R7,R8,R9,R10,R11,R12],
Uses = [R1,R5,R6,R7,R8,R9,R10] in {
def BRLD : BranchL<0x26, 0x14, 0x000, "brld ">;
@@ -462,10 +487,34 @@
}
let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1,
- hasCtrlDep=1, rd=0x10, imm16=0x8, Form=FR in {
- def RTSD : TB<0x2D, (outs), (ins GPR:$target),
- "rtsd $target, 8",
- [(MBlazeRet GPR:$target)],
+ hasCtrlDep=1, rd=0x10, Form=FCRI in {
+ def RTSD : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm),
+ "rtsd $target, $imm",
+ [],
+ IIBranch>;
+}
+
+let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1,
+ hasCtrlDep=1, rd=0x11, Form=FCRI in {
+ def RTID : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm),
+ "rtsd $target, $imm",
+ [],
+ IIBranch>;
+}
+
+let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1,
+ hasCtrlDep=1, rd=0x12, Form=FCRI in {
+ def RTBD : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm),
+ "rtsd $target, $imm",
+ [],
+ IIBranch>;
+}
+
+let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1,
+ hasCtrlDep=1, rd=0x14, Form=FCRI in {
+ def RTED : TB<0x2D, (outs), (ins GPR:$target, simm16:$imm),
+ "rtsd $target, $imm",
+ [],
IIBranch>;
}
@@ -474,7 +523,7 @@
//===----------------------------------------------------------------------===//
let neverHasSideEffects = 1 in {
- def NOP : MBlazeInst< 0x20, FRRR, (outs), (ins), "nop ", [], IIAlu>;
+ def NOP : MBlazeInst< 0x20, FC, (outs), (ins), "nop ", [], IIAlu>;
}
let usesCustomInserter = 1 in {
@@ -520,6 +569,38 @@
}
//===----------------------------------------------------------------------===//
+// Misc. instructions
+//===----------------------------------------------------------------------===//
+def MFS : MBlazeInst<0x25, FPseudo, (outs), (ins), "mfs", [], IIAlu> {
+}
+
+def MTS : MBlazeInst<0x25, FPseudo, (outs), (ins), "mts", [], IIAlu> {
+}
+
+def MSRSET : MBlazeInst<0x25, FPseudo, (outs), (ins), "msrset", [], IIAlu> {
+}
+
+def MSRCLR : MBlazeInst<0x25, FPseudo, (outs), (ins), "msrclr", [], IIAlu> {
+}
+
+let rd=0x0, Form=FCRR in {
+ def WDC : TA<0x24, 0x64, (outs), (ins GPR:$a, GPR:$b),
+ "wdc $a, $b", [], IIAlu>;
+ def WDCF : TA<0x24, 0x74, (outs), (ins GPR:$a, GPR:$b),
+ "wdc.flush $a, $b", [], IIAlu>;
+ def WDCC : TA<0x24, 0x66, (outs), (ins GPR:$a, GPR:$b),
+ "wdc.clear $a, $b", [], IIAlu>;
+ def WIC : TA<0x24, 0x68, (outs), (ins GPR:$a, GPR:$b),
+ "wic $a, $b", [], IIAlu>;
+}
+
+def BRK : Branch<0x26, 0x0C, 0x000, "brk ">;
+def BRKI : BranchI<0x2E, 0x0C, "brki ">;
+
+def IMM : MBlazeInst<0x2C, FCCI, (outs), (ins simm16:$imm),
+ "imm $imm", [], IIAlu>;
+
+//===----------------------------------------------------------------------===//
// Arbitrary patterns that map to one or more instructions
//===----------------------------------------------------------------------===//
@@ -536,9 +617,14 @@
def : Pat<(sext_inreg GPR:$src, i8), (SEXT8 GPR:$src)>;
// Call
-def : Pat<(MBlazeJmpLink (i32 tglobaladdr:$dst)), (BRLID tglobaladdr:$dst)>;
-def : Pat<(MBlazeJmpLink (i32 texternalsym:$dst)),(BRLID texternalsym:$dst)>;
-def : Pat<(MBlazeJmpLink GPR:$dst), (BRLD GPR:$dst)>;
+def : Pat<(MBlazeJmpLink (i32 tglobaladdr:$dst)),
+ (BRLID (i32 R15), tglobaladdr:$dst)>;
+
+def : Pat<(MBlazeJmpLink (i32 texternalsym:$dst)),
+ (BRLID (i32 R15), texternalsym:$dst)>;
+
+def : Pat<(MBlazeJmpLink GPR:$dst),
+ (BRLD (i32 R15), GPR:$dst)>;
// Shift Instructions
def : Pat<(shl GPR:$L, GPR:$R), (ShiftL GPR:$L, GPR:$R)>;
@@ -613,6 +699,9 @@
(i32 GPR:$T), (i32 GPR:$F), SETULE),
(Select_CC GPR:$T, GPR:$F, (CMPU GPR:$L, GPR:$R), 6)>;
+// Ret instructions
+def : Pat<(MBlazeRet GPR:$target), (RTSD GPR:$target, 0x8)>;
+
// BR instructions
def : Pat<(br bb:$T), (BRID bb:$T)>;
def : Pat<(brind GPR:$T), (BRD GPR:$T)>;
@@ -660,6 +749,10 @@
def : Pat<(extloadi8 xaddr:$src), (i32 (LBU xaddr:$src))>;
def : Pat<(extloadi16 xaddr:$src), (i32 (LHU xaddr:$src))>;
+// 32-bit load and store
+def : Pat<(store (i32 GPR:$dst), xaddr:$addr), (SW GPR:$dst, xaddr:$addr)>;
+def : Pat<(load xaddr:$addr), (i32 (LW xaddr:$addr))>;
+
// Peepholes
def : Pat<(store (i32 0), iaddr:$dst), (SWI (i32 R0), iaddr:$dst)>;
Modified: llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeMCAsmInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeMCAsmInfo.cpp?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeMCAsmInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeMCAsmInfo.cpp Wed Oct 27 23:47:43 2010
@@ -14,7 +14,7 @@
#include "MBlazeMCAsmInfo.h"
using namespace llvm;
-MBlazeMCAsmInfo::MBlazeMCAsmInfo(const Target &T, StringRef TT) {
+MBlazeMCAsmInfo::MBlazeMCAsmInfo() {
AlignmentIsInBytes = false;
Data16bitsDirective = "\t.half\t";
Data32bitsDirective = "\t.word\t";
Modified: llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeMCAsmInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeMCAsmInfo.h?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeMCAsmInfo.h (original)
+++ llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeMCAsmInfo.h Wed Oct 27 23:47:43 2010
@@ -22,7 +22,7 @@
class MBlazeMCAsmInfo : public MCAsmInfo {
public:
- explicit MBlazeMCAsmInfo(const Target &T, StringRef TT);
+ explicit MBlazeMCAsmInfo();
};
} // namespace llvm
Modified: llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp Wed Oct 27 23:47:43 2010
@@ -103,6 +103,8 @@
}
void EmitIMM(const MCOperand &imm, unsigned &CurByte, raw_ostream &OS) const;
+ void EmitIMM(const MCInst &MI, unsigned op, unsigned &CurByte,
+ raw_ostream &OS) const;
void EmitImmediate(const MCInst &MI,
unsigned opNo, MCFixupKind FixupKind,
@@ -153,6 +155,18 @@
}
void MBlazeMCCodeEmitter::
+EmitIMM(const MCInst &MI, unsigned op, unsigned &CurByte,
+ raw_ostream &OS) const {
+ MCOperand mcop = MI.getOperand(op);
+ if (mcop.isExpr()) {
+ EmitByte(0x0D, CurByte, OS);
+ EmitByte(0x00, CurByte, OS);
+ EmitRawByte(0, CurByte, OS);
+ EmitRawByte(0, CurByte, OS);
+ }
+}
+
+void MBlazeMCCodeEmitter::
EmitImmediate(const MCInst &MI, unsigned opNo, MCFixupKind FixupKind,
unsigned &CurByte, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups) const {
@@ -166,6 +180,8 @@
}
}
+
+
void MBlazeMCCodeEmitter::
EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups) const {
@@ -177,24 +193,28 @@
switch ((TSFlags & MBlazeII::FormMask)) {
default: break;
- case MBlazeII::Pseudo:
+ case MBlazeII::FPseudo:
// Pseudo instructions don't get encoded.
return;
- case MBlazeII::RegRegImm:
+ case MBlazeII::FRRI:
EmitImmediate( MI, 2, FK_Data_4, CurByte, OS, Fixups );
break;
- case MBlazeII::RegImmReg:
+ case MBlazeII::FRIR:
EmitImmediate( MI, 1, FK_Data_4, CurByte, OS, Fixups );
break;
- case MBlazeII::RegImm:
+ case MBlazeII::FCRI:
EmitImmediate( MI, 1, MCFixupKind(MBlaze::reloc_pcrel_2byte), CurByte, OS,
Fixups );
break;
- case MBlazeII::Imm:
+ case MBlazeII::FRCI:
+ EmitImmediate( MI, 1, MCFixupKind(MBlaze::reloc_pcrel_4byte), CurByte, OS,
+ Fixups );
+
+ case MBlazeII::FCCI:
EmitImmediate( MI, 0, MCFixupKind(MBlaze::reloc_pcrel_4byte), CurByte, OS,
Fixups );
break;
@@ -207,19 +227,17 @@
EmitConstant(Value, 4, CurByte, OS);
break;
+ case MBlaze::BRLID:
+ case MBlaze::BRALID:
+ EmitIMM(MI,1,CurByte,OS);
+ EmitConstant(Value, 4, CurByte, OS);
+ break;
+
case MBlaze::BRI:
case MBlaze::BRAI:
case MBlaze::BRID:
case MBlaze::BRAID:
- case MBlaze::BRLID:
- case MBlaze::BRALID:
- MCOperand op = MI.getOperand(0);
- if (op.isExpr()) {
- EmitByte(0x0D, CurByte, OS);
- EmitByte(0x00, CurByte, OS);
- EmitRawByte(0, CurByte, OS);
- EmitRawByte(0, CurByte, OS);
- }
+ EmitIMM(MI,0,CurByte,OS);
EmitConstant(Value, 4, CurByte, OS);
break;
}
Modified: llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeTargetMachine.cpp?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeTargetMachine.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeTargetMachine.cpp Wed Oct 27 23:47:43 2010
@@ -21,6 +21,14 @@
#include "llvm/Target/TargetRegistry.h"
using namespace llvm;
+static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
+ Triple TheTriple(TT);
+ switch (TheTriple.getOS()) {
+ default:
+ return new MBlazeMCAsmInfo();
+ }
+}
+
static MCStreamer *createMCStreamer(const Target &T, const std::string &TT,
MCContext &Ctx, TargetAsmBackend &TAB,
raw_ostream &_OS,
@@ -46,7 +54,9 @@
extern "C" void LLVMInitializeMBlazeTarget() {
// Register the target.
RegisterTargetMachine<MBlazeTargetMachine> X(TheMBlazeTarget);
- RegisterAsmInfo<MBlazeMCAsmInfo> A(TheMBlazeTarget);
+
+ // Register the target asm info.
+ RegisterAsmInfoFn A(TheMBlazeTarget, createMCAsmInfo);
// Register the MC code emitter
TargetRegistry::RegisterCodeEmitter(TheMBlazeTarget,
Modified: llvm/branches/wendling/eh/lib/Target/MBlaze/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/MBlaze/Makefile?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/MBlaze/Makefile (original)
+++ llvm/branches/wendling/eh/lib/Target/MBlaze/Makefile Wed Oct 27 23:47:43 2010
@@ -16,9 +16,10 @@
MBlazeGenInstrInfo.inc MBlazeGenAsmWriter.inc \
MBlazeGenDAGISel.inc MBlazeGenAsmMatcher.inc \
MBlazeGenCodeEmitter.inc MBlazeGenCallingConv.inc \
- MBlazeGenSubtarget.inc MBlazeGenIntrinsics.inc
+ MBlazeGenSubtarget.inc MBlazeGenIntrinsics.inc \
+ MBlazeGenEDInfo.inc
-DIRS = InstPrinter AsmParser TargetInfo
+DIRS = InstPrinter AsmParser Disassembler TargetInfo
include $(LEVEL)/Makefile.common
Modified: llvm/branches/wendling/eh/lib/Target/MBlaze/TODO
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/MBlaze/TODO?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/MBlaze/TODO (original)
+++ llvm/branches/wendling/eh/lib/Target/MBlaze/TODO Wed Oct 27 23:47:43 2010
@@ -30,3 +30,5 @@
slots but I'm not sure that is necessary.
- The processor itineraries are copied from a different backend
and need to be updated to model the MicroBlaze correctly.
+ - Look at the MBlazeGenFastISel.inc stuff and make use of it
+ if appropriate.
Modified: llvm/branches/wendling/eh/lib/Target/X86/AsmParser/X86AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/AsmParser/X86AsmParser.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/AsmParser/X86AsmParser.cpp Wed Oct 27 23:47:43 2010
@@ -703,6 +703,15 @@
.Case("fwait", "wait")
.Case("movzx", "movzb") // FIXME: Not correct.
.Case("fildq", "fildll")
+ .Case("fcompi", "fcomip")
+ .Case("fucompi", "fucomip")
+ .Case("fldcww", "fldcw")
+ .Case("fnstcww", "fnstcw")
+ .Case("fstcww", "fstcw")
+ .Case("fnstsww", "fnstsw")
+ .Case("fstsww", "fstsw")
+ .Case("verrw", "verr")
+ .Case("ud2a", "ud2")
.Default(Name);
// FIXME: Hack to recognize cmp<comparison code>{ss,sd,ps,pd}.
@@ -991,9 +1000,20 @@
NameLoc, NameLoc));
}
+ // The assembler accepts this instruction with no operand as a synonym for an
+ // instruction taking %st(1),%st(0). e.g. "fcompi" -> "fcompi %st(1),st(0)".
+ if (Name == "fcompi" && Operands.size() == 1) {
+ Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(1)"),
+ NameLoc, NameLoc));
+ Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(0)"),
+ NameLoc, NameLoc));
+ }
+
// The assembler accepts these instructions with two few operands as a synonym
// for taking %st(1),%st(0) or X, %st(0).
- if ((Name == "fcomi" || Name == "fucomi") && Operands.size() < 3) {
+ if ((Name == "fcomi" || Name == "fucomi" || Name == "fucompi" ||
+ Name == "fcompi" ) &&
+ Operands.size() < 3) {
if (Operands.size() == 1)
Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(1)"),
NameLoc, NameLoc));
@@ -1177,7 +1197,7 @@
// FIXME: This should be replaced with a real .td file alias mechanism.
if (Op->getToken() == "fstsw" || Op->getToken() == "fstcw" ||
Op->getToken() == "finit" || Op->getToken() == "fsave" ||
- Op->getToken() == "fstenv") {
+ Op->getToken() == "fstenv" || Op->getToken() == "fclex") {
MCInst Inst;
Inst.setOpcode(X86::WAIT);
Out.EmitInstruction(Inst);
@@ -1189,6 +1209,7 @@
.Case("fstcw", "fnstcw")
.Case("fstenv", "fnstenv")
.Case("fstsw", "fnstsw")
+ .Case("fclex", "fnclex")
.Default(0);
assert(Repl && "Unknown wait-prefixed instruction");
delete Operands[0];
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86ISelLowering.cpp?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86ISelLowering.cpp Wed Oct 27 23:47:43 2010
@@ -104,8 +104,8 @@
setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2");
setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
- setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::X86_StdCall);
- setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::X86_StdCall);
+ setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C);
+ setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C);
}
if (Subtarget->isTargetDarwin()) {
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86InstrSSE.td?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86InstrSSE.td Wed Oct 27 23:47:43 2010
@@ -654,10 +654,10 @@
int_x86_sse_cvttss2si64, f32mem, load,
"cvttss2si">, XS, VEX, VEX_W;
defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
- f128mem, load, "cvttss2si">, XD, VEX;
+ f128mem, load, "cvttsd2si">, XD, VEX;
defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
int_x86_sse2_cvttsd2si64, f128mem, load,
- "cvttss2si">, XD, VEX, VEX_W;
+ "cvttsd2si">, XD, VEX, VEX_W;
}
defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
f32mem, load, "cvttss2si">, XS;
@@ -665,10 +665,10 @@
int_x86_sse_cvttss2si64, f32mem, load,
"cvttss2si{q}">, XS, REX_W;
defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
- f128mem, load, "cvttss2si">, XD;
+ f128mem, load, "cvttsd2si">, XD;
defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
int_x86_sse2_cvttsd2si64, f128mem, load,
- "cvttss2si{q}">, XD, REX_W;
+ "cvttsd2si{q}">, XD, REX_W;
let isAsmParserOnly = 1, Pattern = []<dag> in {
defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86InstrSystem.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86InstrSystem.td?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86InstrSystem.td (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86InstrSystem.td Wed Oct 27 23:47:43 2010
@@ -21,8 +21,10 @@
// CPU flow control instructions
-let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
+let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
+ def UD2B : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
+}
def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
Modified: llvm/branches/wendling/eh/lib/Transforms/InstCombine/InstCombineSelect.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/InstCombine/InstCombineSelect.cpp?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/InstCombine/InstCombineSelect.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/InstCombine/InstCombineSelect.cpp Wed Oct 27 23:47:43 2010
@@ -639,6 +639,10 @@
Value *NegVal; // Compute -Z
if (Constant *C = dyn_cast<Constant>(SubOp->getOperand(1))) {
NegVal = ConstantExpr::getNeg(C);
+ } else if (SI.getType()->isFloatingPointTy()) {
+ NegVal = InsertNewInstBefore(
+ BinaryOperator::CreateFNeg(SubOp->getOperand(1),
+ "tmp"), SI);
} else {
NegVal = InsertNewInstBefore(
BinaryOperator::CreateNeg(SubOp->getOperand(1),
@@ -654,7 +658,10 @@
NewFalseOp, SI.getName() + ".p");
NewSel = InsertNewInstBefore(NewSel, SI);
- return BinaryOperator::CreateAdd(SubOp->getOperand(0), NewSel);
+ if (SI.getType()->isFloatingPointTy())
+ return BinaryOperator::CreateFAdd(SubOp->getOperand(0), NewSel);
+ else
+ return BinaryOperator::CreateAdd(SubOp->getOperand(0), NewSel);
}
}
}
Modified: llvm/branches/wendling/eh/lib/VMCore/AsmWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/VMCore/AsmWriter.cpp?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/VMCore/AsmWriter.cpp (original)
+++ llvm/branches/wendling/eh/lib/VMCore/AsmWriter.cpp Wed Oct 27 23:47:43 2010
@@ -1958,7 +1958,7 @@
Out << " ]\n";
}
- if (II->getCatchAllType()) {
+ if (II->hasCatchAll()) {
Out << " catchall [";
writeOperand(II->getCatchAllType(), true);
Out << ", ";
Modified: llvm/branches/wendling/eh/test/CodeGen/ARM/shifter_operand.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/CodeGen/ARM/shifter_operand.ll?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/CodeGen/ARM/shifter_operand.ll (original)
+++ llvm/branches/wendling/eh/test/CodeGen/ARM/shifter_operand.ll Wed Oct 27 23:47:43 2010
@@ -1,18 +1,72 @@
-; RUN: llc < %s -march=arm | grep add | grep lsl
-; RUN: llc < %s -march=arm | grep bic | grep asr
+; RUN: llc < %s -mtriple=armv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8
+; RUN: llc < %s -mtriple=armv7-apple-darwin -mcpu=cortex-a9 | FileCheck %s -check-prefix=A9
+; rdar://8576755
define i32 @test1(i32 %X, i32 %Y, i8 %sh) {
- %shift.upgrd.1 = zext i8 %sh to i32 ; <i32> [#uses=1]
- %A = shl i32 %Y, %shift.upgrd.1 ; <i32> [#uses=1]
- %B = add i32 %X, %A ; <i32> [#uses=1]
+; A8: test1:
+; A8: add r0, r0, r1, lsl r2
+
+; A9: test1:
+; A9: add r0, r0, r1, lsl r2
+ %shift.upgrd.1 = zext i8 %sh to i32
+ %A = shl i32 %Y, %shift.upgrd.1
+ %B = add i32 %X, %A
ret i32 %B
}
define i32 @test2(i32 %X, i32 %Y, i8 %sh) {
- %shift.upgrd.2 = zext i8 %sh to i32 ; <i32> [#uses=1]
- %A = ashr i32 %Y, %shift.upgrd.2 ; <i32> [#uses=1]
- %B = xor i32 %A, -1 ; <i32> [#uses=1]
- %C = and i32 %X, %B ; <i32> [#uses=1]
+; A8: test2:
+; A8: bic r0, r0, r1, asr r2
+
+; A9: test2:
+; A9: bic r0, r0, r1, asr r2
+ %shift.upgrd.2 = zext i8 %sh to i32
+ %A = ashr i32 %Y, %shift.upgrd.2
+ %B = xor i32 %A, -1
+ %C = and i32 %X, %B
ret i32 %C
}
+
+define i32 @test3(i32 %base, i32 %base2, i32 %offset) {
+entry:
+; A8: test3:
+; A8: ldr r0, [r0, r2, lsl #2]
+; A8: ldr r1, [r1, r2, lsl #2]
+
+; lsl #2 is free
+; A9: test3:
+; A9: ldr r1, [r1, r2, lsl #2]
+; A9: ldr r0, [r0, r2, lsl #2]
+ %tmp1 = shl i32 %offset, 2
+ %tmp2 = add i32 %base, %tmp1
+ %tmp3 = inttoptr i32 %tmp2 to i32*
+ %tmp4 = add i32 %base2, %tmp1
+ %tmp5 = inttoptr i32 %tmp4 to i32*
+ %tmp6 = load i32* %tmp3
+ %tmp7 = load i32* %tmp5
+ %tmp8 = add i32 %tmp7, %tmp6
+ ret i32 %tmp8
+}
+
+declare i8* @malloc(...)
+
+define fastcc void @test4() nounwind {
+entry:
+; A8: test4:
+; A8: ldr r1, [r0, r0, lsl #2]
+; A8: str r1, [r0, r0, lsl #2]
+
+; A9: test4:
+; A9: add r0, r0, r0, lsl #2
+; A9: ldr r1, [r0]
+; A9: str r1, [r0]
+ %0 = tail call i8* (...)* @malloc(i32 undef) nounwind
+ %1 = bitcast i8* %0 to i32*
+ %2 = sext i16 undef to i32
+ %3 = getelementptr inbounds i32* %1, i32 %2
+ %4 = load i32* %3, align 4
+ %5 = add nsw i32 %4, 1
+ store i32 %5, i32* %3, align 4
+ ret void
+}
Modified: llvm/branches/wendling/eh/test/CodeGen/ARM/vrev.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/CodeGen/ARM/vrev.ll?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/CodeGen/ARM/vrev.ll (original)
+++ llvm/branches/wendling/eh/test/CodeGen/ARM/vrev.ll Wed Oct 27 23:47:43 2010
@@ -129,3 +129,21 @@
%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 5, i32 4, i32 7, i32 undef>
ret <8 x i16> %tmp2
}
+
+; A vcombine feeding a VREV should not obscure things. Radar 8597007.
+
+define void @test_with_vcombine(<4 x float>* %v) nounwind {
+;CHECK: test_with_vcombine:
+;CHECK-NOT: vext
+;CHECK: vrev64.32
+ %tmp1 = load <4 x float>* %v, align 16
+ %tmp2 = bitcast <4 x float> %tmp1 to <2 x double>
+ %tmp3 = extractelement <2 x double> %tmp2, i32 0
+ %tmp4 = bitcast double %tmp3 to <2 x float>
+ %tmp5 = extractelement <2 x double> %tmp2, i32 1
+ %tmp6 = bitcast double %tmp5 to <2 x float>
+ %tmp7 = fadd <2 x float> %tmp6, %tmp6
+ %tmp8 = shufflevector <2 x float> %tmp4, <2 x float> %tmp7, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
+ store <4 x float> %tmp8, <4 x float>* %v, align 16
+ ret void
+}
Modified: llvm/branches/wendling/eh/test/CodeGen/X86/avx-intrinsics-x86.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/CodeGen/X86/avx-intrinsics-x86.ll?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/CodeGen/X86/avx-intrinsics-x86.ll (original)
+++ llvm/branches/wendling/eh/test/CodeGen/X86/avx-intrinsics-x86.ll Wed Oct 27 23:47:43 2010
@@ -230,7 +230,7 @@
define i32 @test_x86_sse2_cvttsd2si(<2 x double> %a0) {
- ; CHECK: vcvttss2si
+ ; CHECK: vcvttsd2si
%res = call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> %a0) ; <i32> [#uses=1]
ret i32 %res
}
Modified: llvm/branches/wendling/eh/test/CodeGen/X86/avx-intrinsics-x86_64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/CodeGen/X86/avx-intrinsics-x86_64.ll?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/CodeGen/X86/avx-intrinsics-x86_64.ll (original)
+++ llvm/branches/wendling/eh/test/CodeGen/X86/avx-intrinsics-x86_64.ll Wed Oct 27 23:47:43 2010
@@ -17,7 +17,7 @@
define i64 @test_x86_sse2_cvttsd2si64(<2 x double> %a0) {
- ; CHECK: vcvttss2si
+ ; CHECK: vcvttsd2si
%res = call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %a0) ; <i64> [#uses=1]
ret i64 %res
}
Modified: llvm/branches/wendling/eh/test/MC/ARM/neon-mov-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/MC/ARM/neon-mov-encoding.ll?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/MC/ARM/neon-mov-encoding.ll (original)
+++ llvm/branches/wendling/eh/test/MC/ARM/neon-mov-encoding.ll Wed Oct 27 23:47:43 2010
@@ -167,3 +167,265 @@
; CHECK: vmvn.i32 d16, #0x20FFFF @ encoding: [0x30,0x0d,0xc2,0xf2]
ret <2 x i32> < i32 4292804608, i32 4292804608 >
}
+
+define <8 x i16> @vmovls8(<8 x i8>* %A) nounwind {
+ %tmp1 = load <8 x i8>* %A
+; CHECK: vmovl.s8 q8, d16 @ encoding: [0x30,0x0a,0xc8,0xf2]
+ %tmp2 = sext <8 x i8> %tmp1 to <8 x i16>
+ ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vmovls16(<4 x i16>* %A) nounwind {
+ %tmp1 = load <4 x i16>* %A
+; CHECK: vmovl.s16 q8, d16 @ encoding: [0x30,0x0a,0xd0,0xf2]
+ %tmp2 = sext <4 x i16> %tmp1 to <4 x i32>
+ ret <4 x i32> %tmp2
+}
+
+define <2 x i64> @vmovls32(<2 x i32>* %A) nounwind {
+ %tmp1 = load <2 x i32>* %A
+; CHECK: vmovl.s32 q8, d16 @ encoding: [0x30,0x0a,0xe0,0xf2]
+ %tmp2 = sext <2 x i32> %tmp1 to <2 x i64>
+ ret <2 x i64> %tmp2
+}
+
+define <8 x i16> @vmovlu8(<8 x i8>* %A) nounwind {
+ %tmp1 = load <8 x i8>* %A
+; CHECK: vmovl.u8 q8, d16 @ encoding: [0x30,0x0a,0xc8,0xf3]
+ %tmp2 = zext <8 x i8> %tmp1 to <8 x i16>
+ ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vmovlu16(<4 x i16>* %A) nounwind {
+ %tmp1 = load <4 x i16>* %A
+; CHECK: vmovl.u16 q8, d16 @ encoding: [0x30,0x0a,0xd0,0xf3]
+ %tmp2 = zext <4 x i16> %tmp1 to <4 x i32>
+ ret <4 x i32> %tmp2
+}
+
+define <2 x i64> @vmovlu32(<2 x i32>* %A) nounwind {
+ %tmp1 = load <2 x i32>* %A
+; CHECK: vmovl.u32 q8, d16 @ encoding: [0x30,0x0a,0xe0,0xf3]
+ %tmp2 = zext <2 x i32> %tmp1 to <2 x i64>
+ ret <2 x i64> %tmp2
+}
+
+define <8 x i8> @vmovni16(<8 x i16>* %A) nounwind {
+ %tmp1 = load <8 x i16>* %A
+; CHECK: vmovn.i16 d16, q8 @ encoding: [0x20,0x02,0xf2,0xf3]
+ %tmp2 = trunc <8 x i16> %tmp1 to <8 x i8>
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vmovni32(<4 x i32>* %A) nounwind {
+ %tmp1 = load <4 x i32>* %A
+; CHECK: vmovn.i32 d16, q8 @ encoding: [0x20,0x02,0xf6,0xf3]
+ %tmp2 = trunc <4 x i32> %tmp1 to <4 x i16>
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vmovni64(<2 x i64>* %A) nounwind {
+ %tmp1 = load <2 x i64>* %A
+; CHECK: vmovn.i64 d16, q8 @ encoding: [0x20,0x02,0xfa,0xf3]
+ %tmp2 = trunc <2 x i64> %tmp1 to <2 x i32>
+ ret <2 x i32> %tmp2
+}
+
+define <8 x i8> @vqmovns16(<8 x i16>* %A) nounwind {
+ %tmp1 = load <8 x i16>* %A
+; CHECK: vqmovn.s16 d16, q8 @ encoding: [0xa0,0x02,0xf2,0xf3]
+ %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16> %tmp1)
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vqmovns32(<4 x i32>* %A) nounwind {
+ %tmp1 = load <4 x i32>* %A
+; CHECK: vqmovn.s32 d16, q8 @ encoding: [0xa0,0x02,0xf6,0xf3]
+ %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32> %tmp1)
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vqmovns64(<2 x i64>* %A) nounwind {
+ %tmp1 = load <2 x i64>* %A
+; CHECK: vqmovn.s64 d16, q8 @ encoding: [0xa0,0x02,0xfa,0xf3]
+ %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64> %tmp1)
+ ret <2 x i32> %tmp2
+}
+
+define <8 x i8> @vqmovnu16(<8 x i16>* %A) nounwind {
+ %tmp1 = load <8 x i16>* %A
+; CHECK: vqmovn.u16 d16, q8 @ encoding: [0xe0,0x02,0xf2,0xf3]
+ %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16> %tmp1)
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vqmovnu32(<4 x i32>* %A) nounwind {
+ %tmp1 = load <4 x i32>* %A
+; CHECK: vqmovn.u32 d16, q8 @ encoding: [0xe0,0x02,0xf6,0xf3]
+ %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32> %tmp1)
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vqmovnu64(<2 x i64>* %A) nounwind {
+ %tmp1 = load <2 x i64>* %A
+; CHECK: vqmovn.u64 d16, q8 @ encoding: [0xe0,0x02,0xfa,0xf3]
+ %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64> %tmp1)
+ ret <2 x i32> %tmp2
+}
+
+define <8 x i8> @vqmovuns16(<8 x i16>* %A) nounwind {
+ %tmp1 = load <8 x i16>* %A
+; CHECK: vqmovun.s16 d16, q8 @ encoding: [0x60,0x02,0xf2,0xf3]
+ %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16> %tmp1)
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vqmovuns32(<4 x i32>* %A) nounwind {
+ %tmp1 = load <4 x i32>* %A
+; CHECK: vqmovun.s32 d16, q8 @ encoding: [0x60,0x02,0xf6,0xf3]
+ %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32> %tmp1)
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vqmovuns64(<2 x i64>* %A) nounwind {
+ %tmp1 = load <2 x i64>* %A
+; CHECK: vqmovun.s64 d16, q8 @ encoding: [0x60,0x02,0xfa,0xf3]
+ %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64> %tmp1)
+ ret <2 x i32> %tmp2
+}
+
+declare <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64>) nounwind readnone
+
+declare <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64>) nounwind readnone
+
+declare <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64>) nounwind readnone
+
+define i32 @vget_lanes8(<8 x i8>* %A) nounwind {
+ %tmp1 = load <8 x i8>* %A
+; CHECK: vmov.s8 r0, d16[1] @ encoding: [0xb0,0x0b,0x50,0xee]
+ %tmp2 = extractelement <8 x i8> %tmp1, i32 1
+ %tmp3 = sext i8 %tmp2 to i32
+ ret i32 %tmp3
+}
+
+define i32 @vget_lanes16(<4 x i16>* %A) nounwind {
+ %tmp1 = load <4 x i16>* %A
+; CHECK: vmov.s16 r0, d16[1] @ encoding: [0xf0,0x0b,0x10,0xee]
+ %tmp2 = extractelement <4 x i16> %tmp1, i32 1
+ %tmp3 = sext i16 %tmp2 to i32
+ ret i32 %tmp3
+}
+
+define i32 @vget_laneu8(<8 x i8>* %A) nounwind {
+ %tmp1 = load <8 x i8>* %A
+; CHECK: vmov.u8 r0, d16[1] @ encoding: [0xb0,0x0b,0xd0,0xee]
+ %tmp2 = extractelement <8 x i8> %tmp1, i32 1
+ %tmp3 = zext i8 %tmp2 to i32
+ ret i32 %tmp3
+}
+
+define i32 @vget_laneu16(<4 x i16>* %A) nounwind {
+ %tmp1 = load <4 x i16>* %A
+; CHECK: vmov.u16 r0, d16[1] @ encoding: [0xf0,0x0b,0x90,0xee]
+ %tmp2 = extractelement <4 x i16> %tmp1, i32 1
+ %tmp3 = zext i16 %tmp2 to i32
+ ret i32 %tmp3
+}
+
+; Do a vector add to keep the extraction from being done directly from memory.
+define i32 @vget_lanei32(<2 x i32>* %A) nounwind {
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = add <2 x i32> %tmp1, %tmp1
+; CHECK: vmov.32 r0, d16[1] @ encoding: [0x90,0x0b,0x30,0xee]
+ %tmp3 = extractelement <2 x i32> %tmp2, i32 1
+ ret i32 %tmp3
+}
+
+define i32 @vgetQ_lanes8(<16 x i8>* %A) nounwind {
+ %tmp1 = load <16 x i8>* %A
+; CHECK: vmov.s8 r0, d16[1] @ encoding: [0xb0,0x0b,0x50,0xee]
+ %tmp2 = extractelement <16 x i8> %tmp1, i32 1
+ %tmp3 = sext i8 %tmp2 to i32
+ ret i32 %tmp3
+}
+
+define i32 @vgetQ_lanes16(<8 x i16>* %A) nounwind {
+ %tmp1 = load <8 x i16>* %A
+; CHECK: vmov.s16 r0, d16[1] @ encoding: [0xf0,0x0b,0x10,0xee]
+ %tmp2 = extractelement <8 x i16> %tmp1, i32 1
+ %tmp3 = sext i16 %tmp2 to i32
+ ret i32 %tmp3
+}
+
+define i32 @vgetQ_laneu8(<16 x i8>* %A) nounwind {
+ %tmp1 = load <16 x i8>* %A
+; CHECK: vmov.u8 r0, d16[1] @ encoding: [0xb0,0x0b,0xd0,0xee]
+ %tmp2 = extractelement <16 x i8> %tmp1, i32 1
+ %tmp3 = zext i8 %tmp2 to i32
+ ret i32 %tmp3
+}
+
+define i32 @vgetQ_laneu16(<8 x i16>* %A) nounwind {
+ %tmp1 = load <8 x i16>* %A
+; CHECK: vmov.u16 r0, d16[1] @ encoding: [0xf0,0x0b,0x90,0xee]
+ %tmp2 = extractelement <8 x i16> %tmp1, i32 1
+ %tmp3 = zext i16 %tmp2 to i32
+ ret i32 %tmp3
+}
+
+; Do a vector add to keep the extraction from being done directly from memory.
+define i32 @vgetQ_lanei32(<4 x i32>* %A) nounwind {
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = add <4 x i32> %tmp1, %tmp1
+; CHECK: vmov.32 r0, d16[1] @ encoding: [0x90,0x0b,0x30,0xee]
+ %tmp3 = extractelement <4 x i32> %tmp2, i32 1
+ ret i32 %tmp3
+}
+
+define <8 x i8> @vset_lane8(<8 x i8>* %A, i8 %B) nounwind {
+ %tmp1 = load <8 x i8>* %A
+; CHECK: vmov.8 d16[1], r1 @ encoding: [0xb0,0x1b,0x40,0xee]
+ %tmp2 = insertelement <8 x i8> %tmp1, i8 %B, i32 1
+ ret <8 x i8> %tmp2
+}
+
+define <4 x i16> @vset_lane16(<4 x i16>* %A, i16 %B) nounwind {
+ %tmp1 = load <4 x i16>* %A
+; CHECK: vmov.16 d16[1], r1 @ encoding: [0xf0,0x1b,0x00,0xee
+ %tmp2 = insertelement <4 x i16> %tmp1, i16 %B, i32 1
+ ret <4 x i16> %tmp2
+}
+
+define <2 x i32> @vset_lane32(<2 x i32>* %A, i32 %B) nounwind {
+ %tmp1 = load <2 x i32>* %A
+; CHECK: vmov.32 d16[1], r1 @ encoding: [0x90,0x1b,0x20,0xee]
+ %tmp2 = insertelement <2 x i32> %tmp1, i32 %B, i32 1
+ ret <2 x i32> %tmp2
+}
+
+define <16 x i8> @vsetQ_lane8(<16 x i8>* %A, i8 %B) nounwind {
+ %tmp1 = load <16 x i8>* %A
+; CHECK: vmov.8 d18[1], r1 @ encoding: [0xb0,0x1b,0x42,0xee]
+ %tmp2 = insertelement <16 x i8> %tmp1, i8 %B, i32 1
+ ret <16 x i8> %tmp2
+}
+
+define <8 x i16> @vsetQ_lane16(<8 x i16>* %A, i16 %B) nounwind {
+ %tmp1 = load <8 x i16>* %A
+; CHECK: vmov.16 d18[1], r1 @ encoding: [0xf0,0x1b,0x02,0xee]
+ %tmp2 = insertelement <8 x i16> %tmp1, i16 %B, i32 1
+ ret <8 x i16> %tmp2
+}
+
+define <4 x i32> @vsetQ_lane32(<4 x i32>* %A, i32 %B) nounwind {
+ %tmp1 = load <4 x i32>* %A
+; CHECK: vmov.32 d18[1], r1 @ encoding: [0x90,0x1b,0x22,0xee]
+ %tmp2 = insertelement <4 x i32> %tmp1, i32 %B, i32 1
+ ret <4 x i32> %tmp2
+}
Modified: llvm/branches/wendling/eh/test/MC/ELF/relocation-386.s
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/MC/ELF/relocation-386.s?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/MC/ELF/relocation-386.s (original)
+++ llvm/branches/wendling/eh/test/MC/ELF/relocation-386.s Wed Oct 27 23:47:43 2010
@@ -50,6 +50,33 @@
// CHECK-NEXT: ('r_type', 0x00000003
// CHECK-NEXT: ),
+// Relocation 5 (foo at TLSGD) is of type R_386_TLS_GD
+// CHECK-NEXT: # Relocation 0x00000005
+// CHECK-NEXT: (('r_offset', 0x00000020)
+// CHECK-NEXT: ('r_sym', 0x0000000b)
+// CHECK-NEXT: ('r_type', 0x00000012)
+// CHECK-NEXT: ),
+
+// Relocation 6 ($foo at TPOFF) is of type R_386_TLS_LE_32
+// CHECK-NEXT: # Relocation 0x00000006
+// CHECK-NEXT: (('r_offset', 0x00000025)
+// CHECK-NEXT: ('r_sym', 0x0000000b)
+// CHECK-NEXT: ('r_type', 0x00000022)
+// CHECK-NEXT: ),
+
+// Relocation 7 (foo at INDNTPOFF) is of type R_386_TLS_IE
+// CHECK-NEXT: # Relocation 0x00000007
+// CHECK-NEXT: (('r_offset', 0x0000002b)
+// CHECK-NEXT: ('r_sym', 0x0000000b)
+// CHECK-NEXT: ('r_type', 0x0000000f)
+// CHECK-NEXT: ),
+
+// Relocation 8 (foo at NTPOFF) is of type R_386_TLS_LE
+// CHECK-NEXT: # Relocation 0x00000008
+// CHECK-NEXT: (('r_offset', 0x00000031)
+// CHECK-NEXT: ('r_sym', 0x0000000b)
+// CHECK-NEXT: ('r_type', 0x00000011)
+
.text
bar:
leal .Lfoo at GOTOFF(%ebx), %eax
@@ -66,6 +93,11 @@
movl bar2j at GOT(%eax), %eax
+ leal foo at TLSGD(, %ebx,1), %eax
+ movl $foo at TPOFF, %edx
+ movl foo at INDNTPOFF, %ecx
+ addl foo at NTPOFF(%eax), %eax
+
.section .rodata.str1.16,"aMS", at progbits,1
.Lfoo:
.asciz "bool llvm::llvm_start_multithreaded()"
Modified: llvm/branches/wendling/eh/test/MC/ELF/relocation.s
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/MC/ELF/relocation.s?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/MC/ELF/relocation.s (original)
+++ llvm/branches/wendling/eh/test/MC/ELF/relocation.s Wed Oct 27 23:47:43 2010
@@ -1,14 +1,17 @@
// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s
-// Test that we produce a R_X86_64_32S or R_X86_64_32.
+// Test that we produce the correct relocation.
bar:
- movl $bar, %edx // R_X86_64_32
- movq $bar, %rdx // R_X86_64_32S
- movq $bar, bar(%rip) // R_X86_64_32S
- movl bar, %edx // R_X86_64_32S
- movq bar, %rdx // R_X86_64_32S
-.long bar // R_X86_64_32
+ movl $bar, %edx # R_X86_64_32
+ movq $bar, %rdx # R_X86_64_32S
+ movq $bar, bar(%rip) # R_X86_64_32S
+ movl bar, %edx # R_X86_64_32S
+ movq bar, %rdx # R_X86_64_32S
+.long bar # R_X86_64_32
+ leaq foo at GOTTPOFF(%rip), %rax # R_X86_64_GOTTPOFF
+ leaq foo at TLSGD(%rip), %rax # R_X86_64_TLSGD
+ leaq foo at TPOFF(%rax), %rax # R_X86_64_TPOFF32
// CHECK: # Section 0x00000001
// CHECK: (('sh_name', 0x00000001) # '.text'
@@ -55,3 +58,21 @@
// CHECK-NEXT: ('r_sym', 0x00000002)
// CHECK-NEXT: ('r_type', 0x0000000a)
// CHECK-NEXT: ('r_addend',
+
+// CHECK: # Relocation 0x00000006
+// CHECK-NEXT: (('r_offset', 0x0000002d)
+// CHECK-NEXT: ('r_sym', 0x00000006)
+// CHECK-NEXT: ('r_type', 0x00000016)
+// CHECK-NEXT: ('r_addend', 0xfffffffc)
+
+// CHECK: # Relocation 0x00000007
+// CHECK-NEXT: (('r_offset', 0x00000034)
+// CHECK-NEXT: ('r_sym', 0x00000006)
+// CHECK-NEXT: ('r_type', 0x00000013)
+// CHECK-NEXT: ('r_addend', 0xfffffffc)
+
+// CHECK: # Relocation 0x00000008
+// CHECK-NEXT: (('r_offset', 0x0000003b)
+// CHECK-NEXT: ('r_sym', 0x00000006)
+// CHECK-NEXT: ('r_type', 0x00000017)
+// CHECK-NEXT: ('r_addend', 0x00000000)
Modified: llvm/branches/wendling/eh/test/MC/ELF/section.s
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/MC/ELF/section.s?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/MC/ELF/section.s (original)
+++ llvm/branches/wendling/eh/test/MC/ELF/section.s Wed Oct 27 23:47:43 2010
@@ -9,3 +9,31 @@
// CHECK: ('sh_name', 0x00000012) # '.note.GNU-stack'
// CHECK: ('sh_name', 0x00000022) # '.note.GNU-'
// CHECK: ('sh_name', 0x0000002d) # '-.note.GNU'
+
+// Test that the dafults for init and fini are used
+
+.section .init
+.section .fini
+
+// CHECK: (('sh_name', 0x00000038) # '.init'
+// CHECK-NEXT: ('sh_type', 0x00000001)
+// CHECK-NEXT: ('sh_flags', 0x00000006)
+// CHECK-NEXT: ('sh_addr', 0x00000000)
+// CHECK-NEXT: ('sh_offset', 0x00000040)
+// CHECK-NEXT: ('sh_size', 0x00000000)
+// CHECK-NEXT: ('sh_link', 0x00000000)
+// CHECK-NEXT: ('sh_info', 0x00000000)
+// CHECK-NEXT: ('sh_addralign', 0x00000001)
+// CHECK-NEXT: ('sh_entsize', 0x00000000)
+// CHECK-NEXT: ),
+// CHECK-NEXT: # Section 0x00000008
+// CHECK-NEXT: (('sh_name', 0x0000003e) # '.fini'
+// CHECK-NEXT: ('sh_type', 0x00000001)
+// CHECK-NEXT: ('sh_flags', 0x00000006)
+// CHECK-NEXT: ('sh_addr', 0x00000000)
+// CHECK-NEXT: ('sh_offset', 0x00000040)
+// CHECK-NEXT: ('sh_size', 0x00000000)
+// CHECK-NEXT: ('sh_link', 0x00000000)
+// CHECK-NEXT: ('sh_info', 0x00000000)
+// CHECK-NEXT: ('sh_addralign', 0x00000001)
+// CHECK-NEXT: ('sh_entsize', 0x00000000)
Modified: llvm/branches/wendling/eh/test/MC/X86/x86-32.s
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/MC/X86/x86-32.s?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/MC/X86/x86-32.s (original)
+++ llvm/branches/wendling/eh/test/MC/X86/x86-32.s Wed Oct 27 23:47:43 2010
@@ -702,3 +702,91 @@
// CHECK: sidt 4(%eax)
// CHECK: encoding: [0x0f,0x01,0x48,0x04]
sidtl 4(%eax)
+
+// CHECK: fcomip %st(2), %st(0)
+// CHECK: encoding: [0xdf,0xf2]
+ fcompi %st(2),%st
+
+// CHECK: fcomip %st(2), %st(0)
+// CHECK: encoding: [0xdf,0xf2]
+ fcompi %st(2)
+
+// CHECK: fcomip %st(1), %st(0)
+// CHECK: encoding: [0xdf,0xf1]
+ fcompi
+
+// CHECK: fucomip %st(2), %st(0)
+// CHECK: encoding: [0xdf,0xea]
+ fucompi %st(2),%st
+
+// CHECK: fucomip %st(2), %st(0)
+// CHECK: encoding: [0xdf,0xea]
+ fucompi %st(2)
+
+// CHECK: fucomip %st(1), %st(0)
+// CHECK: encoding: [0xdf,0xe9]
+ fucompi
+
+// CHECK: fldcw 32493
+// CHECK: encoding: [0xd9,0x2d,0xed,0x7e,0x00,0x00]
+ fldcww 0x7eed
+
+// CHECK: fldcw 32493
+// CHECK: encoding: [0xd9,0x2d,0xed,0x7e,0x00,0x00]
+ fldcw 0x7eed
+
+// CHECK: fnstcw 32493
+// CHECK: encoding: [0xd9,0x3d,0xed,0x7e,0x00,0x00]
+ fnstcww 0x7eed
+
+// CHECK: fnstcw 32493
+// CHECK: encoding: [0xd9,0x3d,0xed,0x7e,0x00,0x00]
+ fnstcw 0x7eed
+
+// CHECK: wait
+// CHECK: encoding: [0x9b]
+ fstcww 0x7eed
+
+// CHECK: wait
+// CHECK: encoding: [0x9b]
+ fstcw 0x7eed
+
+// CHECK: fnstsw 32493
+// CHECK: encoding: [0xdd,0x3d,0xed,0x7e,0x00,0x00]
+ fnstsww 0x7eed
+
+// CHECK: fnstsw 32493
+// CHECK: encoding: [0xdd,0x3d,0xed,0x7e,0x00,0x00]
+ fnstsw 0x7eed
+
+// CHECK: wait
+// CHECK: encoding: [0x9b]
+ fstsww 0x7eed
+
+// CHECK: wait
+// CHECK: encoding: [0x9b]
+ fstsw 0x7eed
+
+// CHECK: verr 32493
+// CHECK: encoding: [0x0f,0x00,0x25,0xed,0x7e,0x00,0x00]
+ verrw 0x7eed
+
+// CHECK: verr 32493
+// CHECK: encoding: [0x0f,0x00,0x25,0xed,0x7e,0x00,0x00]
+ verr 0x7eed
+
+// CHECK: wait
+// CHECK: encoding: [0x9b]
+ fclex
+
+// CHECK: fnclex
+// CHECK: encoding: [0xdb,0xe2]
+ fnclex
+
+// CHECK: ud2
+// CHECK: encoding: [0x0f,0x0b]
+ ud2a
+
+// CHECK: ud2b
+// CHECK: encoding: [0x0f,0xb9]
+ ud2b
Modified: llvm/branches/wendling/eh/utils/TableGen/EDEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/utils/TableGen/EDEmitter.cpp?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/utils/TableGen/EDEmitter.cpp (original)
+++ llvm/branches/wendling/eh/utils/TableGen/EDEmitter.cpp Wed Oct 27 23:47:43 2010
@@ -582,9 +582,11 @@
IMM("t_imm_s4");
IMM("pclabel");
IMM("shift_imm");
+ IMM("neon_vcvt_imm32");
MISC("brtarget", "kOperandTypeARMBranchTarget"); // ?
MISC("so_reg", "kOperandTypeARMSoReg"); // R, R, I
+ MISC("shift_so_reg", "kOperandTypeARMSoReg"); // R, R, I
MISC("t2_so_reg", "kOperandTypeThumb2SoReg"); // R, I
MISC("so_imm", "kOperandTypeARMSoImm"); // I
MISC("rot_imm", "kOperandTypeARMRotImm"); // I
Modified: llvm/branches/wendling/eh/utils/TableGen/X86RecognizableInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/utils/TableGen/X86RecognizableInstr.cpp?rev=117527&r1=117526&r2=117527&view=diff
==============================================================================
--- llvm/branches/wendling/eh/utils/TableGen/X86RecognizableInstr.cpp (original)
+++ llvm/branches/wendling/eh/utils/TableGen/X86RecognizableInstr.cpp Wed Oct 27 23:47:43 2010
@@ -114,7 +114,6 @@
EXTENSION_TABLE(72) \
EXTENSION_TABLE(73) \
EXTENSION_TABLE(ae) \
- EXTENSION_TABLE(b9) \
EXTENSION_TABLE(ba) \
EXTENSION_TABLE(c7)
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