[llvm-branch-commits] [llvm-branch] r116934 - in /llvm/branches/ggreif/peephole-infrastructure: include/llvm/Target/TargetInstrInfo.h lib/Target/ARM/ARMBaseInstrInfo.cpp

[Gabor Greif]

Author: ggreif
Date: Wed Oct 20 11:54:22 2010
New Revision: 116934

URL: http://llvm.org/viewvc/llvm-project?rev=116934&view=rev
Log:
establish and use adaptors

Modified:
    llvm/branches/ggreif/peephole-infrastructure/include/llvm/Target/TargetInstrInfo.h
    llvm/branches/ggreif/peephole-infrastructure/lib/Target/ARM/ARMBaseInstrInfo.cpp

Modified: llvm/branches/ggreif/peephole-infrastructure/include/llvm/Target/TargetInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/peephole-infrastructure/include/llvm/Target/TargetInstrInfo.h?rev=116934&r1=116933&r2=116934&view=diff
==============================================================================
--- llvm/branches/ggreif/peephole-infrastructure/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/branches/ggreif/peephole-infrastructure/include/llvm/Target/TargetInstrInfo.h Wed Oct 20 11:54:22 2010
@@ -57,7 +57,7 @@
   }
 };
 
-/// CmpOpportunity - Decribing opportunities for CMP(-like) instructions
+/// CmpOpportunity - Describing opportunities for CMP(-like) instructions
 struct CmpOpportunity : Opportunity {
   typedef bool (*DispatchFun)(const CmpOpportunity&, MachineInstr *CmpInstr,
                               MachineInstr *MI, const MachineRegisterInfo &MRI,
@@ -65,6 +65,35 @@
   DispatchFun Dispatch;
   unsigned SrcReg;
   CmpOpportunity(unsigned SrcReg) : SrcReg(SrcReg) {}
+  template <class SUB, bool (SUB::*FUN)(MachineInstr*, MachineInstr*,
+                                        const MachineRegisterInfo&,
+                                        MachineBasicBlock::iterator&) const>
+  void optimizeWith() {
+    Dispatch = &dispatch<SUB, FUN>;
+  }
+
+  template <class SUB, bool (SUB::*FUN)(MachineInstr*, MachineInstr*,
+                                        const MachineRegisterInfo&,
+                                        MachineBasicBlock::iterator&) const>
+  static bool dispatch(const CmpOpportunity& self, MachineInstr *CmpInstr,
+                       MachineInstr *MI, const MachineRegisterInfo &MRI,
+                       MachineBasicBlock::iterator &MII) {
+    return (static_cast<const SUB&>(self).*FUN)(CmpInstr, MI, MRI, MII);
+  }
+
+  template <bool (*FUN)(MachineInstr*, MachineInstr*,
+                        MachineBasicBlock::iterator&)>
+  void optimizeWith() {
+    Dispatch = &dispatch2<FUN>;
+  }
+
+  template <bool (*FUN)(MachineInstr*, MachineInstr*,
+                        MachineBasicBlock::iterator&)>
+  static bool dispatch2(const CmpOpportunity& self, MachineInstr *CmpInstr,
+                        MachineInstr *MI, const MachineRegisterInfo &MRI,
+                        MachineBasicBlock::iterator &MII) {
+    return FUN(CmpInstr, MI, MII);
+  }
 };
 
 

Modified: llvm/branches/ggreif/peephole-infrastructure/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/peephole-infrastructure/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=116934&r1=116933&r2=116934&view=diff
==============================================================================
--- llvm/branches/ggreif/peephole-infrastructure/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/branches/ggreif/peephole-infrastructure/lib/Target/ARM/ARMBaseInstrInfo.cpp Wed Oct 20 11:54:22 2010
@@ -1443,10 +1443,8 @@
                      MachineBasicBlock::iterator &MII); //FIXME
 struct ImmCmpOpportunity : CmpOpportunity {
   int CmpValue;
-  ImmCmpOpportunity(unsigned SrcReg) : CmpOpportunity(SrcReg), CmpValue(0) { Dispatch = dispatch; }
-  static bool dispatch(const CmpOpportunity& self, MachineInstr *CmpInstr, MachineInstr *MI,
-                       const MachineRegisterInfo&, MachineBasicBlock::iterator &MII) {
-    return ConvertAndElide(CmpInstr, MI, MII);
+  ImmCmpOpportunity(unsigned SrcReg) : CmpOpportunity(SrcReg), CmpValue(0) {
+    optimizeWith<ConvertAndElide>();
   }
 };
 
@@ -1454,14 +1452,11 @@
   int CmpMask;
   MaskOpportunity(unsigned SrcReg, int CmpMask)
     : CmpOpportunity(SrcReg), CmpMask(CmpMask) {
-    Dispatch = static_cast<DispatchFun>(dispatch);
-  }
-  static bool dispatch(const CmpOpportunity& self, MachineInstr *CmpInstr, MachineInstr *MI,
-                       const MachineRegisterInfo &MRI, MachineBasicBlock::iterator &MII) {
-    return static_cast<const MaskOpportunity&>(self).FindCorrespondingAnd(CmpInstr, MI, MRI, MII);
+      optimizeWith<MaskOpportunity, &MaskOpportunity::FindCorrespondingAnd>();
   }
   bool FindCorrespondingAnd(MachineInstr *CmpInstr, MachineInstr *MI,
-                            const MachineRegisterInfo &MRI, MachineBasicBlock::iterator &MII) const;
+                            const MachineRegisterInfo &MRI,
+                            MachineBasicBlock::iterator &MII) const;
 };
 
 bool ARMBaseInstrInfo::