[llvm-branch-commits] [llvm-branch] r116575 - in /llvm/branches/ggreif/switch-opts: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/PeepholeOptimizer.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h
Gabor Greif
ggreif at gmail.com
Fri Oct 15 07:22:46 PDT 2010
Author: ggreif
Date: Fri Oct 15 09:22:46 2010
New Revision: 116575
URL: http://llvm.org/viewvc/llvm-project?rev=116575&view=rev
Log:
mass replace 'Opaque'-->'Opportunity'
Modified:
llvm/branches/ggreif/switch-opts/include/llvm/Target/TargetInstrInfo.h
llvm/branches/ggreif/switch-opts/lib/CodeGen/PeepholeOptimizer.cpp
llvm/branches/ggreif/switch-opts/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/branches/ggreif/switch-opts/lib/Target/ARM/ARMBaseInstrInfo.h
Modified: llvm/branches/ggreif/switch-opts/include/llvm/Target/TargetInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/switch-opts/include/llvm/Target/TargetInstrInfo.h?rev=116575&r1=116574&r2=116575&view=diff
==============================================================================
--- llvm/branches/ggreif/switch-opts/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/branches/ggreif/switch-opts/include/llvm/Target/TargetInstrInfo.h Fri Oct 15 09:22:46 2010
@@ -34,19 +34,19 @@
template<class T> class SmallVectorImpl;
-struct Opaque {
- typedef bool (*DispatchFun)(const Opaque&,
+struct Opportunity {
+ typedef bool (*DispatchFun)(const Opportunity&,
MachineInstr *CmpInstr, MachineInstr *MI,
MachineRegisterInfo &MRI,
MachineBasicBlock::iterator &MII);
DispatchFun Dispatch;
unsigned SrcReg;
- Opaque() {}
- Opaque(unsigned SrcReg) : SrcReg(SrcReg) {}
- void *operator new(size_t, Opaque&);
+ Opportunity() {}
+ Opportunity(unsigned SrcReg) : SrcReg(SrcReg) {}
+ void *operator new(size_t, Opportunity&);
};
-struct MaxOpaque : Opaque {
+struct MaxOpportunity : Opportunity {
enum { SomeSufficientNumber = sizeof(void*) * 10 };
char payload[SomeSufficientNumber];
};
@@ -602,7 +602,7 @@
/// AnalyzeCompare - For a comparison instruction, return the source register
/// in SrcReg and the value it compares against in CmpValue. Return true if
/// the comparison instruction can be analyzed.
- virtual bool AnalyzeCompare(const MachineInstr *MI, struct Opaque&) const {
+ virtual bool AnalyzeCompare(const MachineInstr *MI, Opportunity&) const {
return false;
}
@@ -611,7 +611,7 @@
/// flags register, obviating the need for a separate CMP. Update the iterator
/// *only* if a transformation took place.
virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr,
- const Opaque&,
+ const Opportunity&,
MachineBasicBlock::iterator &) const {
return false;
}
Modified: llvm/branches/ggreif/switch-opts/lib/CodeGen/PeepholeOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/switch-opts/lib/CodeGen/PeepholeOptimizer.cpp?rev=116575&r1=116574&r2=116575&view=diff
==============================================================================
--- llvm/branches/ggreif/switch-opts/lib/CodeGen/PeepholeOptimizer.cpp (original)
+++ llvm/branches/ggreif/switch-opts/lib/CodeGen/PeepholeOptimizer.cpp Fri Oct 15 09:22:46 2010
@@ -237,7 +237,7 @@
MachineBasicBlock::iterator &NextIter){
// If this instruction is a comparison against zero and isn't comparing a
// physical register, we can try to optimize it. FIXME!
- MaxOpaque Space;
+ MaxOpportunity Space;
if (!TII->AnalyzeCompare(MI, Space) ||
TargetRegisterInfo::isPhysicalRegister(Space.SrcReg))
return false;
Modified: llvm/branches/ggreif/switch-opts/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/switch-opts/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=116575&r1=116574&r2=116575&view=diff
==============================================================================
--- llvm/branches/ggreif/switch-opts/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/branches/ggreif/switch-opts/lib/Target/ARM/ARMBaseInstrInfo.cpp Fri Oct 15 09:22:46 2010
@@ -1429,36 +1429,36 @@
}
-void *llvm::Opaque::operator new(size_t need, Opaque& space) {
- assert(need <= sizeof(MaxOpaque));
+void *llvm::Opportunity::operator new(size_t need, Opportunity& space) {
+ assert(need <= sizeof(MaxOpportunity));
return &space;
}
bool ConvertAndElide(MachineInstr *CmpInstr, MachineInstr *MI,
MachineBasicBlock::iterator &MII); //FIXME
-struct ImmCmpOpaque : Opaque {
+struct ImmCmpOpportunity : Opportunity {
int CmpValue;
- ImmCmpOpaque(unsigned SrcReg, int CmpValue) : Opaque(SrcReg), CmpValue(CmpValue) { Dispatch = dispatch; }
- static bool dispatch(const Opaque& self, MachineInstr *CmpInstr, MachineInstr *MI,
+ ImmCmpOpportunity(unsigned SrcReg) : Opportunity(SrcReg), CmpValue(0) { Dispatch = dispatch; }
+ static bool dispatch(const Opportunity& self, MachineInstr *CmpInstr, MachineInstr *MI,
MachineRegisterInfo &MRI, MachineBasicBlock::iterator &MII) {
return ConvertAndElide(CmpInstr, MI, MII);
}
};
-struct MaskOpaque : Opaque {
+struct MaskOpportunity : Opportunity {
int CmpMask;
- MaskOpaque(unsigned SrcReg, int CmpMask) : Opaque(SrcReg), CmpMask(CmpMask) { Dispatch = static_cast<DispatchFun>(dispatch); }
- static bool dispatch(const Opaque& self, MachineInstr *CmpInstr, MachineInstr *MI,
+ MaskOpportunity(unsigned SrcReg, int CmpMask) : Opportunity(SrcReg), CmpMask(CmpMask) { Dispatch = static_cast<DispatchFun>(dispatch); }
+ static bool dispatch(const Opportunity& self, MachineInstr *CmpInstr, MachineInstr *MI,
MachineRegisterInfo &MRI, MachineBasicBlock::iterator &MII) {
- return static_cast<const MaskOpaque&>(self).FindCorrespondingAnd(CmpInstr, MI, MRI, MII);
+ return static_cast<const MaskOpportunity&>(self).FindCorrespondingAnd(CmpInstr, MI, MRI, MII);
}
bool FindCorrespondingAnd(MachineInstr *CmpInstr, MachineInstr *MI,
MachineRegisterInfo &MRI, MachineBasicBlock::iterator &MII) const;
};
bool ARMBaseInstrInfo::
-AnalyzeCompare(const MachineInstr *MI, Opaque& Opp) const {
+AnalyzeCompare(const MachineInstr *MI, Opportunity& Opp) const {
switch (MI->getOpcode()) {
default: break;
case ARM::CMPri:
@@ -1467,12 +1467,12 @@
case ARM::t2CMPzri: {
int CmpValue = MI->getOperand(1).getImm();
return CmpValue == 0 &&
- new(Opp) ImmCmpOpaque(MI->getOperand(0).getReg(), CmpValue);
+ new(Opp) ImmCmpOpportunity(MI->getOperand(0).getReg());
}
case ARM::TSTri:
case ARM::t2TSTri:
- return new(Opp) MaskOpaque(MI->getOperand(0).getReg(),
- MI->getOperand(1).getImm());
+ return new(Opp) MaskOpportunity(MI->getOperand(0).getReg(),
+ MI->getOperand(1).getImm());
}
return false;
@@ -1510,7 +1510,7 @@
/// comparison into one that sets the zero bit in the flags register. Update the
/// iterator *only* if a transformation took place.
bool ARMBaseInstrInfo::
-OptimizeCompareInstr(MachineInstr *CmpInstr, const Opaque& Opp, MachineBasicBlock::iterator &MII) const {
+OptimizeCompareInstr(MachineInstr *CmpInstr, const Opportunity& Opp, MachineBasicBlock::iterator &MII) const {
MachineRegisterInfo &MRI = CmpInstr->getParent()->getParent()->getRegInfo();
MachineRegisterInfo::def_iterator DI = MRI.def_begin(Opp.SrcReg);
if (llvm::next(DI) != MRI.def_end())
@@ -1521,7 +1521,8 @@
return Opp.Dispatch(Opp, CmpInstr, MI, MRI, MII);
}
-bool MaskOpaque::FindCorrespondingAnd(MachineInstr *CmpInstr,
+bool
+MaskOpportunity::FindCorrespondingAnd(MachineInstr *CmpInstr,
MachineInstr *MI,
MachineRegisterInfo &MRI,
MachineBasicBlock::iterator &MII) const {
Modified: llvm/branches/ggreif/switch-opts/lib/Target/ARM/ARMBaseInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/switch-opts/lib/Target/ARM/ARMBaseInstrInfo.h?rev=116575&r1=116574&r2=116575&view=diff
==============================================================================
--- llvm/branches/ggreif/switch-opts/lib/Target/ARM/ARMBaseInstrInfo.h (original)
+++ llvm/branches/ggreif/switch-opts/lib/Target/ARM/ARMBaseInstrInfo.h Fri Oct 15 09:22:46 2010
@@ -327,11 +327,11 @@
/// AnalyzeCompare - For a comparison instruction, return the source register
/// in SrcReg and the value it compares against in CmpValue. Return true if
/// the comparison instruction can be analyzed.
- virtual bool AnalyzeCompare(const MachineInstr *MI, Opaque&) const;
+ virtual bool AnalyzeCompare(const MachineInstr *MI, Opportunity&) const;
/// OptimizeCompareInstr - Convert the instruction to set the zero flag so
/// that we can remove a "comparison with zero".
- virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, const Opaque&,
+ virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, const Opportunity&,
MachineBasicBlock::iterator &MII) const;
virtual unsigned getNumMicroOps(const MachineInstr *MI,
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