[llvm-branch-commits] [llvm-branch] r116525 - in /llvm/branches/ggreif/switch-opts: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/PeepholeOptimizer.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h
Gabor Greif
ggreif at gmail.com
Thu Oct 14 15:00:00 PDT 2010
Author: ggreif
Date: Thu Oct 14 16:59:59 2010
New Revision: 116525
URL: http://llvm.org/viewvc/llvm-project?rev=116525&view=rev
Log:
morph the Opaque concept into a workable implementation; much cleanup still to be done
Modified:
llvm/branches/ggreif/switch-opts/include/llvm/Target/TargetInstrInfo.h
llvm/branches/ggreif/switch-opts/lib/CodeGen/PeepholeOptimizer.cpp
llvm/branches/ggreif/switch-opts/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/branches/ggreif/switch-opts/lib/Target/ARM/ARMBaseInstrInfo.h
Modified: llvm/branches/ggreif/switch-opts/include/llvm/Target/TargetInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/switch-opts/include/llvm/Target/TargetInstrInfo.h?rev=116525&r1=116524&r2=116525&view=diff
==============================================================================
--- llvm/branches/ggreif/switch-opts/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/branches/ggreif/switch-opts/include/llvm/Target/TargetInstrInfo.h Thu Oct 14 16:59:59 2010
@@ -35,8 +35,15 @@
template<class T> class SmallVectorImpl;
struct Opaque {
- void (*dispach)(const Opaque&, int);
- void *operator new(size_t, Opaque&);
+ typedef bool (*DispatchFun)(const Opaque&,
+ MachineInstr *CmpInstr, MachineInstr *MI,
+ MachineRegisterInfo &MRI,
+ MachineBasicBlock::iterator &MII);
+ DispatchFun Dispatch;
+ unsigned SrcReg;
+ Opaque() {}
+ Opaque(unsigned SrcReg) : SrcReg(SrcReg) {}
+ void *operator new(size_t, Opaque&);
};
struct MaxOpaque : Opaque {
@@ -595,8 +602,7 @@
/// AnalyzeCompare - For a comparison instruction, return the source register
/// in SrcReg and the value it compares against in CmpValue. Return true if
/// the comparison instruction can be analyzed.
- virtual bool AnalyzeCompare(const MachineInstr *MI,
- unsigned &SrcReg, int &Mask, int &Value, struct Opaque&) const {
+ virtual bool AnalyzeCompare(const MachineInstr *MI, struct Opaque&) const {
return false;
}
@@ -605,7 +611,7 @@
/// flags register, obviating the need for a separate CMP. Update the iterator
/// *only* if a transformation took place.
virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr,
- unsigned SrcReg, int Mask, int Value,
+ const Opaque&,
MachineBasicBlock::iterator &) const {
return false;
}
Modified: llvm/branches/ggreif/switch-opts/lib/CodeGen/PeepholeOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/switch-opts/lib/CodeGen/PeepholeOptimizer.cpp?rev=116525&r1=116524&r2=116525&view=diff
==============================================================================
--- llvm/branches/ggreif/switch-opts/lib/CodeGen/PeepholeOptimizer.cpp (original)
+++ llvm/branches/ggreif/switch-opts/lib/CodeGen/PeepholeOptimizer.cpp Thu Oct 14 16:59:59 2010
@@ -236,16 +236,14 @@
MachineBasicBlock *MBB,
MachineBasicBlock::iterator &NextIter){
// If this instruction is a comparison against zero and isn't comparing a
- // physical register, we can try to optimize it.
- unsigned SrcReg;
- int CmpMask, CmpValue;
+ // physical register, we can try to optimize it. FIXME!
MaxOpaque Space;
- if (!TII->AnalyzeCompare(MI, SrcReg, CmpMask, CmpValue, Space) ||
- TargetRegisterInfo::isPhysicalRegister(SrcReg))
+ if (!TII->AnalyzeCompare(MI, Space) ||
+ TargetRegisterInfo::isPhysicalRegister(Space.SrcReg))
return false;
// Attempt to optimize the comparison instruction.
- if (TII->OptimizeCompareInstr(MI, SrcReg, CmpMask, CmpValue, NextIter)) {
+ if (TII->OptimizeCompareInstr(MI, Space, NextIter)) {
++NumEliminated;
return true;
}
Modified: llvm/branches/ggreif/switch-opts/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/switch-opts/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=116525&r1=116524&r2=116525&view=diff
==============================================================================
--- llvm/branches/ggreif/switch-opts/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/branches/ggreif/switch-opts/lib/Target/ARM/ARMBaseInstrInfo.cpp Thu Oct 14 16:59:59 2010
@@ -1435,33 +1435,44 @@
}
+bool ConvertAndElide(MachineInstr *CmpInstr, MachineInstr *MI,
+ MachineBasicBlock::iterator &MII); //FIXME
struct ImmCmpOpaque : Opaque {
- int CmpValue;
+ int CmpValue;
+ ImmCmpOpaque(unsigned SrcReg, int CmpValue) : Opaque(SrcReg), CmpValue(CmpValue) { Dispatch = dispatch; }
+ static bool dispatch(const Opaque& self, MachineInstr *CmpInstr, MachineInstr *MI,
+ MachineRegisterInfo &MRI, MachineBasicBlock::iterator &MII) {
+ return ConvertAndElide(CmpInstr, MI, MII);
+ }
};
struct MaskOpaque : Opaque {
- int CmpMask;
+ int CmpMask;
+ MaskOpaque(unsigned SrcReg, int CmpMask) : Opaque(SrcReg), CmpMask(CmpMask) { Dispatch = static_cast<DispatchFun>(dispatch); }
+ static bool dispatch(const Opaque& self, MachineInstr *CmpInstr, MachineInstr *MI,
+ MachineRegisterInfo &MRI, MachineBasicBlock::iterator &MII) {
+ return static_cast<const MaskOpaque&>(self).FindCorrespondingAnd(CmpInstr, MI, MRI, MII);
+ }
+ bool FindCorrespondingAnd(MachineInstr *CmpInstr, MachineInstr *MI,
+ MachineRegisterInfo &MRI, MachineBasicBlock::iterator &MII) const;
};
bool ARMBaseInstrInfo::
-AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpMask,
- int &CmpValue, Opaque& Opp) const {
+AnalyzeCompare(const MachineInstr *MI, Opaque& Opp) const {
switch (MI->getOpcode()) {
default: break;
case ARM::CMPri:
case ARM::CMPzri:
case ARM::t2CMPri:
- case ARM::t2CMPzri:
- SrcReg = MI->getOperand(0).getReg();
- CmpMask = ~0;
- CmpValue = MI->getOperand(1).getImm();
- return new(Opp) ImmCmpOpaque;
+ case ARM::t2CMPzri: {
+ int CmpValue = MI->getOperand(1).getImm();
+ return CmpValue == 0 &&
+ new(Opp) ImmCmpOpaque(MI->getOperand(0).getReg(), CmpValue);
+ }
case ARM::TSTri:
case ARM::t2TSTri:
- SrcReg = MI->getOperand(0).getReg();
- CmpMask = MI->getOperand(1).getImm();
- CmpValue = 0;
- return new(Opp) MaskOpaque;
+ return new(Opp) MaskOpaque(MI->getOperand(0).getReg(),
+ MI->getOperand(1).getImm());
}
return false;
@@ -1499,21 +1510,23 @@
/// comparison into one that sets the zero bit in the flags register. Update the
/// iterator *only* if a transformation took place.
bool ARMBaseInstrInfo::
-OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask,
- int CmpValue, MachineBasicBlock::iterator &MII) const {
- if (CmpValue != 0)
- return false;
-
+OptimizeCompareInstr(MachineInstr *CmpInstr, const Opaque& Opp, MachineBasicBlock::iterator &MII) const {
MachineRegisterInfo &MRI = CmpInstr->getParent()->getParent()->getRegInfo();
- MachineRegisterInfo::def_iterator DI = MRI.def_begin(SrcReg);
+ MachineRegisterInfo::def_iterator DI = MRI.def_begin(Opp.SrcReg);
if (llvm::next(DI) != MRI.def_end())
// Only support one definition.
return false;
MachineInstr *MI = &*DI;
+ return Opp.Dispatch(Opp, CmpInstr, MI, MRI, MII);
+}
+bool MaskOpaque::FindCorrespondingAnd(MachineInstr *CmpInstr,
+ MachineInstr *MI,
+ MachineRegisterInfo &MRI,
+ MachineBasicBlock::iterator &MII) const {
// Masked compares sometimes use the same register as the corresponding 'and'.
- if (CmpMask != ~0) {
+ // if (CmpMask != ~0) {
if (!isSuitableForMask(MI, SrcReg, CmpMask, false)) {
MI = 0;
for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(SrcReg),
@@ -1527,8 +1540,12 @@
}
if (!MI) return false;
}
- }
+ // }
+ return ConvertAndElide(CmpInstr, MI, MII);
+}
+bool ConvertAndElide(MachineInstr *CmpInstr, MachineInstr *MI,
+ MachineBasicBlock::iterator &MII) {
// Conservatively refuse to convert an instruction which isn't in the same BB
// as the comparison.
if (MI->getParent() != CmpInstr->getParent())
Modified: llvm/branches/ggreif/switch-opts/lib/Target/ARM/ARMBaseInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/switch-opts/lib/Target/ARM/ARMBaseInstrInfo.h?rev=116525&r1=116524&r2=116525&view=diff
==============================================================================
--- llvm/branches/ggreif/switch-opts/lib/Target/ARM/ARMBaseInstrInfo.h (original)
+++ llvm/branches/ggreif/switch-opts/lib/Target/ARM/ARMBaseInstrInfo.h Thu Oct 14 16:59:59 2010
@@ -327,13 +327,11 @@
/// AnalyzeCompare - For a comparison instruction, return the source register
/// in SrcReg and the value it compares against in CmpValue. Return true if
/// the comparison instruction can be analyzed.
- virtual bool AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
- int &CmpMask, int &CmpValue, Opaque&) const;
+ virtual bool AnalyzeCompare(const MachineInstr *MI, Opaque&) const;
/// OptimizeCompareInstr - Convert the instruction to set the zero flag so
/// that we can remove a "comparison with zero".
- virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
- int CmpMask, int CmpValue,
+ virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, const Opaque&,
MachineBasicBlock::iterator &MII) const;
virtual unsigned getNumMicroOps(const MachineInstr *MI,
More information about the llvm-branch-commits
mailing list