[llvm-branch-commits] [llvm-branch] r116510 - in /llvm/branches/ggreif/switch-opts: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/PeepholeOptimizer.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h

[Gabor Greif]

Author: ggreif
Date: Thu Oct 14 15:33:59 2010
New Revision: 116510

URL: http://llvm.org/viewvc/llvm-project?rev=116510&view=rev
Log:
flesh out the Opaque concept

Modified:
    llvm/branches/ggreif/switch-opts/include/llvm/Target/TargetInstrInfo.h
    llvm/branches/ggreif/switch-opts/lib/CodeGen/PeepholeOptimizer.cpp
    llvm/branches/ggreif/switch-opts/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/branches/ggreif/switch-opts/lib/Target/ARM/ARMBaseInstrInfo.h

Modified: llvm/branches/ggreif/switch-opts/include/llvm/Target/TargetInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/switch-opts/include/llvm/Target/TargetInstrInfo.h?rev=116510&r1=116509&r2=116510&view=diff
==============================================================================
--- llvm/branches/ggreif/switch-opts/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/branches/ggreif/switch-opts/include/llvm/Target/TargetInstrInfo.h Thu Oct 14 15:33:59 2010
@@ -34,6 +34,15 @@
 
 template<class T> class SmallVectorImpl;
 
+struct Opaque {
+	void (*dispach)(const Opaque&, int);
+	void *operator new(size_t, Opaque&);
+};
+
+struct MaxOpaque : Opaque {
+  enum { SomeSufficientNumber = sizeof(void*) * 10 };
+  char payload[SomeSufficientNumber];
+};
 
 //---------------------------------------------------------------------------
 ///
@@ -587,7 +596,7 @@
   /// in SrcReg and the value it compares against in CmpValue. Return true if
   /// the comparison instruction can be analyzed.
   virtual bool AnalyzeCompare(const MachineInstr *MI,
-                              unsigned &SrcReg, int &Mask, int &Value) const {
+                              unsigned &SrcReg, int &Mask, int &Value, struct Opaque&) const {
     return false;
   }
 

Modified: llvm/branches/ggreif/switch-opts/lib/CodeGen/PeepholeOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/switch-opts/lib/CodeGen/PeepholeOptimizer.cpp?rev=116510&r1=116509&r2=116510&view=diff
==============================================================================
--- llvm/branches/ggreif/switch-opts/lib/CodeGen/PeepholeOptimizer.cpp (original)
+++ llvm/branches/ggreif/switch-opts/lib/CodeGen/PeepholeOptimizer.cpp Thu Oct 14 15:33:59 2010
@@ -239,7 +239,8 @@
   // physical register, we can try to optimize it.
   unsigned SrcReg;
   int CmpMask, CmpValue;
-  if (!TII->AnalyzeCompare(MI, SrcReg, CmpMask, CmpValue) ||
+  MaxOpaque Space;
+  if (!TII->AnalyzeCompare(MI, SrcReg, CmpMask, CmpValue, Space) ||
       TargetRegisterInfo::isPhysicalRegister(SrcReg))
     return false;
 

Modified: llvm/branches/ggreif/switch-opts/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/switch-opts/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=116510&r1=116509&r2=116510&view=diff
==============================================================================
--- llvm/branches/ggreif/switch-opts/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/branches/ggreif/switch-opts/lib/Target/ARM/ARMBaseInstrInfo.cpp Thu Oct 14 15:33:59 2010
@@ -1429,24 +1429,23 @@
 }
 
 
-struct Opaque {
-	void (*dispach)(const Opaque&, int);
-	void *operator new(size_t, Opaque&);
-};
-
-struct MaxOpaque : Opaque {
-  enum { SomeSufficientNumber = sizeof(void*) * 10 };
-  char payload[SomeSufficientNumber];
-};
-
-void *Opaque::operator new(size_t need, Opaque& space) {
+void *llvm::Opaque::operator new(size_t need, Opaque& space) {
   assert(need <= sizeof(MaxOpaque));
   return &space;
 }
 
+
+struct ImmCmpOpaque : Opaque {
+	int CmpValue;
+};
+
+struct MaskOpaque : Opaque {
+	int CmpMask;
+};
+
 bool ARMBaseInstrInfo::
 AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpMask,
-               int &CmpValue) const {
+               int &CmpValue, Opaque& Opp) const {
   switch (MI->getOpcode()) {
   default: break;
   case ARM::CMPri:
@@ -1456,13 +1455,13 @@
     SrcReg = MI->getOperand(0).getReg();
     CmpMask = ~0;
     CmpValue = MI->getOperand(1).getImm();
-    return true;
+    return new(Opp) ImmCmpOpaque;
   case ARM::TSTri:
   case ARM::t2TSTri:
     SrcReg = MI->getOperand(0).getReg();
     CmpMask = MI->getOperand(1).getImm();
     CmpValue = 0;
-    return true;
+    return new(Opp) MaskOpaque;
   }
 
   return false;

Modified: llvm/branches/ggreif/switch-opts/lib/Target/ARM/ARMBaseInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/switch-opts/lib/Target/ARM/ARMBaseInstrInfo.h?rev=116510&r1=116509&r2=116510&view=diff
==============================================================================
--- llvm/branches/ggreif/switch-opts/lib/Target/ARM/ARMBaseInstrInfo.h (original)
+++ llvm/branches/ggreif/switch-opts/lib/Target/ARM/ARMBaseInstrInfo.h Thu Oct 14 15:33:59 2010
@@ -328,7 +328,7 @@
   /// in SrcReg and the value it compares against in CmpValue. Return true if
   /// the comparison instruction can be analyzed.
   virtual bool AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
-                              int &CmpMask, int &CmpValue) const;
+                              int &CmpMask, int &CmpValue, Opaque&) const;
 
   /// OptimizeCompareInstr - Convert the instruction to set the zero flag so
   /// that we can remove a "comparison with zero".