[llvm-branch-commits] [llvm-branch] r104771 - in /llvm/branches/Apple/whitney: include/llvm/Target/TargetAsmBackend.h lib/MC/MCAssembler.cpp lib/Target/X86/X86AsmBackend.cpp

[Daniel Dunbar]

Author: ddunbar
Date: Wed May 26 17:29:11 2010
New Revision: 104771

URL: http://llvm.org/viewvc/llvm-project?rev=104771&view=rev
Log:
MC: Change RelaxInstruction to only take the input and output instructions.

Modified:
    llvm/branches/Apple/whitney/include/llvm/Target/TargetAsmBackend.h
    llvm/branches/Apple/whitney/lib/MC/MCAssembler.cpp
    llvm/branches/Apple/whitney/lib/Target/X86/X86AsmBackend.cpp

Modified: llvm/branches/Apple/whitney/include/llvm/Target/TargetAsmBackend.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/whitney/include/llvm/Target/TargetAsmBackend.h?rev=104771&r1=104770&r2=104771&view=diff
==============================================================================
--- llvm/branches/Apple/whitney/include/llvm/Target/TargetAsmBackend.h (original)
+++ llvm/branches/Apple/whitney/include/llvm/Target/TargetAsmBackend.h Wed May 26 17:29:11 2010
@@ -16,7 +16,6 @@
 class MCDataFragment;
 class MCFixup;
 class MCInst;
-class MCInstFragment;
 class MCObjectWriter;
 class MCSection;
 template<typename T>
@@ -111,13 +110,16 @@
   /// MayNeedRelaxation - Check whether the given instruction may need
   /// relaxation.
   ///
-  /// \arg Inst - The instruction to test.
+  /// \param Inst - The instruction to test.
   virtual bool MayNeedRelaxation(const MCInst &Inst) const = 0;
 
   /// RelaxInstruction - Relax the instruction in the given fragment to the next
   /// wider instruction.
-  virtual void RelaxInstruction(const MCInstFragment *IF,
-                                MCInst &Res) const = 0;
+  ///
+  /// \param Inst - The instruction to relax, which may be the same as the
+  /// output.
+  /// \parm Res [output] - On return, the relaxed instruction.
+  virtual void RelaxInstruction(const MCInst &Inst, MCInst &Res) const = 0;
 
   /// WriteNopData - Write an (optimal) nop sequence of Count bytes to the given
   /// output. If the target cannot generate such a sequence, it should return an

Modified: llvm/branches/Apple/whitney/lib/MC/MCAssembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/whitney/lib/MC/MCAssembler.cpp?rev=104771&r1=104770&r2=104771&view=diff
==============================================================================
--- llvm/branches/Apple/whitney/lib/MC/MCAssembler.cpp (original)
+++ llvm/branches/Apple/whitney/lib/MC/MCAssembler.cpp Wed May 26 17:29:11 2010
@@ -824,7 +824,7 @@
       // Relax the fragment.
 
       MCInst Relaxed;
-      getBackend().RelaxInstruction(IF, Relaxed);
+      getBackend().RelaxInstruction(IF->getInst(), Relaxed);
 
       // Encode the new instruction.
       //

Modified: llvm/branches/Apple/whitney/lib/Target/X86/X86AsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/whitney/lib/Target/X86/X86AsmBackend.cpp?rev=104771&r1=104770&r2=104771&view=diff
==============================================================================
--- llvm/branches/Apple/whitney/lib/Target/X86/X86AsmBackend.cpp (original)
+++ llvm/branches/Apple/whitney/lib/Target/X86/X86AsmBackend.cpp Wed May 26 17:29:11 2010
@@ -56,7 +56,7 @@
 
   bool MayNeedRelaxation(const MCInst &Inst) const;
 
-  void RelaxInstruction(const MCInstFragment *IF, MCInst &Res) const;
+  void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
 
   bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
 };
@@ -101,20 +101,19 @@
 
 // FIXME: Can tblgen help at all here to verify there aren't other instructions
 // we can relax?
-void X86AsmBackend::RelaxInstruction(const MCInstFragment *IF,
-                                     MCInst &Res) const {
+void X86AsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
   // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
-  unsigned RelaxedOp = getRelaxedOpcode(IF->getInst().getOpcode());
+  unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
 
-  if (RelaxedOp == IF->getInst().getOpcode()) {
+  if (RelaxedOp == Inst.getOpcode()) {
     SmallString<256> Tmp;
     raw_svector_ostream OS(Tmp);
-    IF->getInst().dump_pretty(OS);
+    Inst.dump_pretty(OS);
     OS << "\n";
     report_fatal_error("unexpected instruction to relax: " + OS.str());
   }
 
-  Res = IF->getInst();
+  Res = Inst;
   Res.setOpcode(RelaxedOp);
 }