[llvm-branch-commits] [llvm-branch] r104180 - in /llvm/branches/Apple/Hartnell: ./ include/llvm/CodeGen/ScheduleDAG.h lib/CodeGen/PostRASchedulerList.cpp lib/CodeGen/ScheduleDAGInstrs.cpp
Jim Grosbach
grosbach at apple.com
Wed May 19 16:32:32 PDT 2010
Author: grosbach
Date: Wed May 19 18:32:32 2010
New Revision: 104180
URL: http://llvm.org/viewvc/llvm-project?rev=104180&view=rev
Log:
merge 104174 104175
Modified:
llvm/branches/Apple/Hartnell/ (props changed)
llvm/branches/Apple/Hartnell/include/llvm/CodeGen/ScheduleDAG.h
llvm/branches/Apple/Hartnell/lib/CodeGen/PostRASchedulerList.cpp
llvm/branches/Apple/Hartnell/lib/CodeGen/ScheduleDAGInstrs.cpp
Propchange: llvm/branches/Apple/Hartnell/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Wed May 19 18:32:32 2010
@@ -1 +1,2 @@
/llvm/branches/Apple/Morbo:102475
+/llvm/trunk:104174-104175
Modified: llvm/branches/Apple/Hartnell/include/llvm/CodeGen/ScheduleDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Hartnell/include/llvm/CodeGen/ScheduleDAG.h?rev=104180&r1=104179&r2=104180&view=diff
==============================================================================
--- llvm/branches/Apple/Hartnell/include/llvm/CodeGen/ScheduleDAG.h (original)
+++ llvm/branches/Apple/Hartnell/include/llvm/CodeGen/ScheduleDAG.h Wed May 19 18:32:32 2010
@@ -225,7 +225,6 @@
private:
SDNode *Node; // Representative node.
MachineInstr *Instr; // Alternatively, a MachineInstr.
- MachineInstr *DbgInstr; // A dbg_value referencing this.
public:
SUnit *OrigNode; // If not this, the node from which
// this node was cloned.
@@ -256,6 +255,8 @@
bool isScheduled : 1; // True once scheduled.
bool isScheduleHigh : 1; // True if preferable to schedule high.
bool isCloned : 1; // True if this node has been cloned.
+
+ SmallVector<MachineInstr*, 4> DbgInstrList; // dbg_values referencing this.
private:
bool isDepthCurrent : 1; // True if Depth is current.
bool isHeightCurrent : 1; // True if Height is current.
@@ -268,7 +269,7 @@
/// SUnit - Construct an SUnit for pre-regalloc scheduling to represent
/// an SDNode and any nodes flagged to it.
SUnit(SDNode *node, unsigned nodenum)
- : Node(node), Instr(0), DbgInstr(0), OrigNode(0), NodeNum(nodenum),
+ : Node(node), Instr(0), OrigNode(0), NodeNum(nodenum),
NodeQueueId(0), Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
NumSuccsLeft(0), isTwoAddress(false), isCommutable(false),
hasPhysRegDefs(false), hasPhysRegClobbers(false),
@@ -280,7 +281,7 @@
/// SUnit - Construct an SUnit for post-regalloc scheduling to represent
/// a MachineInstr.
SUnit(MachineInstr *instr, unsigned nodenum)
- : Node(0), Instr(instr), DbgInstr(0), OrigNode(0), NodeNum(nodenum),
+ : Node(0), Instr(instr), OrigNode(0), NodeNum(nodenum),
NodeQueueId(0), Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
NumSuccsLeft(0), isTwoAddress(false), isCommutable(false),
hasPhysRegDefs(false), hasPhysRegClobbers(false),
@@ -291,7 +292,7 @@
/// SUnit - Construct a placeholder SUnit.
SUnit()
- : Node(0), Instr(0), DbgInstr(0), OrigNode(0), NodeNum(~0u),
+ : Node(0), Instr(0), OrigNode(0), NodeNum(~0u),
NodeQueueId(0), Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
NumSuccsLeft(0), isTwoAddress(false), isCommutable(false),
hasPhysRegDefs(false), hasPhysRegClobbers(false),
@@ -328,20 +329,6 @@
return Instr;
}
- /// setDbgInstr - Assign the debug instruction for the SUnit.
- /// This may be used during post-regalloc scheduling.
- void setDbgInstr(MachineInstr *MI) {
- assert(!Node && "Setting debug MachineInstr of SUnit with SDNode!");
- DbgInstr = MI;
- }
-
- /// getDbgInstr - Return the debug MachineInstr for this SUnit.
- /// This may be used during post-regalloc scheduling.
- MachineInstr *getDbgInstr() const {
- assert(!Node && "Reading debug MachineInstr of SUnit with SDNode!");
- return DbgInstr;
- }
-
/// addPred - This adds the specified edge as a pred of the current node if
/// not already. It also adds the current node as a successor of the
/// specified node.
Modified: llvm/branches/Apple/Hartnell/lib/CodeGen/PostRASchedulerList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Hartnell/lib/CodeGen/PostRASchedulerList.cpp?rev=104180&r1=104179&r2=104180&view=diff
==============================================================================
--- llvm/branches/Apple/Hartnell/lib/CodeGen/PostRASchedulerList.cpp (original)
+++ llvm/branches/Apple/Hartnell/lib/CodeGen/PostRASchedulerList.cpp Wed May 19 18:32:32 2010
@@ -83,7 +83,7 @@
static cl::opt<bool>
EnablePostRADbgValue("post-RA-dbg-value",
cl::desc("Enable processing of dbg_value in post-RA"),
- cl::init(false), cl::Hidden);
+ cl::init(true), cl::Hidden);
AntiDepBreaker::~AntiDepBreaker() { }
Modified: llvm/branches/Apple/Hartnell/lib/CodeGen/ScheduleDAGInstrs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Hartnell/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=104180&r1=104179&r2=104180&view=diff
==============================================================================
--- llvm/branches/Apple/Hartnell/lib/CodeGen/ScheduleDAGInstrs.cpp (original)
+++ llvm/branches/Apple/Hartnell/lib/CodeGen/ScheduleDAGInstrs.cpp Wed May 19 18:32:32 2010
@@ -210,7 +210,7 @@
assert(TRI->isPhysicalRegister(Reg) && "Virtual register encountered!");
if (MO.isDef() && DanglingDebugValue[Reg].first!=0) {
- SU->setDbgInstr(DanglingDebugValue[Reg].first);
+ SU->DbgInstrList.push_back(DanglingDebugValue[Reg].first);
DbgValueVec[DanglingDebugValue[Reg].second] = 0;
DanglingDebugValue[Reg] = std::make_pair((MachineInstr*)0, 0);
}
@@ -599,8 +599,8 @@
}
BB->insert(InsertPos, SU->getInstr());
- if (SU->getDbgInstr())
- BB->insert(InsertPos, SU->getDbgInstr());
+ for (unsigned i = 0, e = SU->DbgInstrList.size() ; i < e ; ++i)
+ BB->insert(InsertPos, SU->DbgInstrList[i]);
}
// Update the Begin iterator, as the first instruction in the block
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