[llvm-branch-commits] [llvm-branch] r104061 - in /llvm/branches/Apple/Hermes: lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMInstrFormats.td test/CodeGen/ARM/2010-05-18-PostIndexBug.ll

[Evan Cheng]

Author: evancheng
Date: Tue May 18 16:38:14 2010
New Revision: 104061

URL: http://llvm.org/viewvc/llvm-project?rev=104061&view=rev
Log:
Merge 104060.

Added:
    llvm/branches/Apple/Hermes/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll
      - copied unchanged from r104060, llvm/trunk/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll
Modified:
    llvm/branches/Apple/Hermes/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/branches/Apple/Hermes/lib/Target/ARM/ARMISelLowering.cpp
    llvm/branches/Apple/Hermes/lib/Target/ARM/ARMInstrFormats.td   (props changed)

Modified: llvm/branches/Apple/Hermes/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Hermes/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=104061&r1=104060&r2=104061&view=diff
==============================================================================
--- llvm/branches/Apple/Hermes/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/branches/Apple/Hermes/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue May 18 16:38:14 2010
@@ -4855,10 +4855,6 @@
     SDValue Offset;
     ISD::MemIndexedMode AM = ISD::UNINDEXED;
     if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
-      if (Ptr == Offset && Op->getOpcode() == ISD::ADD)
-        std::swap(BasePtr, Offset);
-      if (Ptr != BasePtr)
-        continue;
       // Don't create a indexed load / store with zero offset.
       if (isa<ConstantSDNode>(Offset) &&
           cast<ConstantSDNode>(Offset)->isNullValue())

Modified: llvm/branches/Apple/Hermes/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Hermes/lib/Target/ARM/ARMISelLowering.cpp?rev=104061&r1=104060&r2=104061&view=diff
==============================================================================
--- llvm/branches/Apple/Hermes/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/branches/Apple/Hermes/lib/Target/ARM/ARMISelLowering.cpp Tue May 18 16:38:14 2010
@@ -4369,9 +4369,11 @@
   bool isSEXTLoad = false;
   if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
     VT  = LD->getMemoryVT();
+    Ptr = LD->getBasePtr();
     isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
   } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
     VT  = ST->getMemoryVT();
+    Ptr = ST->getBasePtr();
   } else
     return false;
 
@@ -4379,13 +4381,25 @@
   bool isLegal = false;
   if (Subtarget->isThumb2())
     isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
-                                        isInc, DAG);
+                                       isInc, DAG);
   else
     isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
                                         isInc, DAG);
   if (!isLegal)
     return false;
 
+  if (Ptr != Base) {
+    // Swap base ptr and offset to catch more post-index load / store when
+    // it's legal. In Thumb2 mode, offset must be an immediate.
+    if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
+        !Subtarget->isThumb2())
+      std::swap(Base, Offset);
+
+    // Post-indexed load / store update the base pointer.
+    if (Ptr != Base)
+      return false;
+  }
+
   AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
   return true;
 }

Propchange: llvm/branches/Apple/Hermes/lib/Target/ARM/ARMInstrFormats.td
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Tue May 18 16:38:14 2010
@@ -1 +1 @@
-/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td:96032,96521,96525,96572,96621,96775,96825,96827,96990,97025,97065,97071,97538,97707,97757,97782,97797,98210,98270,98395,98398,98402,98409,98416,98427,98561,98586,98845,98977,99043,99630,99678,100568,100892,101181,101282,101303,101383,101615,102526,103995
+/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td:96032,96521,96525,96572,96621,96775,96825,96827,96990,97025,97065,97071,97538,97707,97757,97782,97797,98210,98270,98395,98398,98402,98409,98416,98427,98561,98586,98845,98977,99043,99630,99678,100568,100892,101181,101282,101303,101383,101615,102526,103995,104060