[llvm-branch-commits] [llvm-branch] r98313 - in /llvm/branches/release_27: ./ docs/CodeGenerator.html docs/LangRef.html test/CodeGen/X86/sibcall.ll test/CodeGen/X86/tailcall2.ll
Tanya Lattner
tonic at nondot.org
Thu Mar 11 16:12:21 PST 2010
Author: tbrethou
Date: Thu Mar 11 18:12:20 2010
New Revision: 98313
URL: http://llvm.org/viewvc/llvm-project?rev=98313&view=rev
Log:
Merge 97980 from mainline.
Add documentation on sibling call optimization. Rename tailcall2.ll test to sibcall.ll.
Added:
llvm/branches/release_27/test/CodeGen/X86/sibcall.ll
- copied unchanged from r97980, llvm/trunk/test/CodeGen/X86/sibcall.ll
Removed:
llvm/branches/release_27/test/CodeGen/X86/tailcall2.ll
Modified:
llvm/branches/release_27/ (props changed)
llvm/branches/release_27/docs/CodeGenerator.html
llvm/branches/release_27/docs/LangRef.html
Propchange: llvm/branches/release_27/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Thu Mar 11 18:12:20 2010
@@ -1 +1 @@
-/llvm/trunk:97965,97974,98171,98193,98203,98205,98212
+/llvm/trunk:97965,97974,97980,98171,98193,98203,98205,98212
Modified: llvm/branches/release_27/docs/CodeGenerator.html
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_27/docs/CodeGenerator.html?rev=98313&r1=98312&r2=98313&view=diff
==============================================================================
--- llvm/branches/release_27/docs/CodeGenerator.html (original)
+++ llvm/branches/release_27/docs/CodeGenerator.html Thu Mar 11 18:12:20 2010
@@ -86,6 +86,7 @@
<li><a href="#targetimpls">Target-specific Implementation Notes</a>
<ul>
<li><a href="#tailcallopt">Tail call optimization</a></li>
+ <li><a href="#sibcallopt">Sibling call optimization</a></li>
<li><a href="#x86">The X86 backend</a></li>
<li><a href="#ppc">The PowerPC backend</a>
<ul>
@@ -1735,6 +1736,50 @@
</div>
<!-- ======================================================================= -->
<div class="doc_subsection">
+ <a name="sibcallopt">Sibling call optimization</a>
+</div>
+
+<div class="doc_text">
+
+<p>Sibling call optimization is a restricted form of tail call optimization.
+ Unlike tail call optimization described in the previous section, it can be
+ performed automatically on any tail calls when <tt>-tailcallopt</tt> option
+ is not specified.</p>
+
+<p>Sibling call optimization is currently performed on x86/x86-64 when the
+ following constraints are met:</p>
+
+<ul>
+ <li>Caller and callee have the same calling convention. It can be either
+ <tt>c</tt> or <tt>fastcc</tt>.
+
+ <li>The call is a tail call - in tail position (ret immediately follows call
+ and ret uses value of call or is void).</li>
+
+ <li>Caller and callee have matching return type or the callee result is not
+ used.
+
+ <li>If any of the callee arguments are being passed in stack, they must be
+ available in caller's own incoming argument stack and the frame offsets
+ must be the same.
+</ul>
+
+<p>Example:</p>
+<div class="doc_code">
+<pre>
+declare i32 @bar(i32, i32)
+
+define i32 @foo(i32 %a, i32 %b, i32 %c) {
+entry:
+ %0 = tail call i32 @bar(i32 %a, i32 %b)
+ ret i32 %0
+}
+</pre>
+</div>
+
+</div>
+<!-- ======================================================================= -->
+<div class="doc_subsection">
<a name="x86">The X86 backend</a>
</div>
Modified: llvm/branches/release_27/docs/LangRef.html
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_27/docs/LangRef.html?rev=98313&r1=98312&r2=98313&view=diff
==============================================================================
--- llvm/branches/release_27/docs/LangRef.html (original)
+++ llvm/branches/release_27/docs/LangRef.html Thu Mar 11 18:12:20 2010
@@ -5169,8 +5169,11 @@
a <a href="#i_ret"><tt>ret</tt></a> instruction. If the "tail" marker is
present, the function call is eligible for tail call optimization,
but <a href="CodeGenerator.html#tailcallopt">might not in fact be
- optimized into a jump</a>. As of this writing, the extra requirements for
- a call to actually be optimized are:
+ optimized into a jump</a>. The code generator may optimize calls marked
+ "tail" with either 1) automatic <a href="CodeGenerator.html#sibcallopt">
+ sibling call optimization</a> when the caller and callee have
+ matching signatures, or 2) forced tail call optimization when the
+ following extra requirements are met:
<ul>
<li>Caller and callee both have the calling
convention <tt>fastcc</tt>.</li>
Removed: llvm/branches/release_27/test/CodeGen/X86/tailcall2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_27/test/CodeGen/X86/tailcall2.ll?rev=98312&view=auto
==============================================================================
--- llvm/branches/release_27/test/CodeGen/X86/tailcall2.ll (original)
+++ llvm/branches/release_27/test/CodeGen/X86/tailcall2.ll (removed)
@@ -1,218 +0,0 @@
-; RUN: llc < %s -march=x86 -asm-verbose=false | FileCheck %s -check-prefix=32
-; RUN: llc < %s -march=x86-64 -asm-verbose=false | FileCheck %s -check-prefix=64
-
-define void @t1(i32 %x) nounwind ssp {
-entry:
-; 32: t1:
-; 32: jmp {{_?}}foo
-
-; 64: t1:
-; 64: jmp {{_?}}foo
- tail call void @foo() nounwind
- ret void
-}
-
-declare void @foo()
-
-define void @t2() nounwind ssp {
-entry:
-; 32: t2:
-; 32: jmp {{_?}}foo2
-
-; 64: t2:
-; 64: jmp {{_?}}foo2
- %0 = tail call i32 @foo2() nounwind
- ret void
-}
-
-declare i32 @foo2()
-
-define void @t3() nounwind ssp {
-entry:
-; 32: t3:
-; 32: jmp {{_?}}foo3
-
-; 64: t3:
-; 64: jmp {{_?}}foo3
- %0 = tail call i32 @foo3() nounwind
- ret void
-}
-
-declare i32 @foo3()
-
-define void @t4(void (i32)* nocapture %x) nounwind ssp {
-entry:
-; 32: t4:
-; 32: call *
-; FIXME: gcc can generate a tailcall for this. But it's tricky.
-
-; 64: t4:
-; 64-NOT: call
-; 64: jmpq *
- tail call void %x(i32 0) nounwind
- ret void
-}
-
-define void @t5(void ()* nocapture %x) nounwind ssp {
-entry:
-; 32: t5:
-; 32-NOT: call
-; 32: jmpl *
-
-; 64: t5:
-; 64-NOT: call
-; 64: jmpq *
- tail call void %x() nounwind
- ret void
-}
-
-define i32 @t6(i32 %x) nounwind ssp {
-entry:
-; 32: t6:
-; 32: call {{_?}}t6
-; 32: jmp {{_?}}bar
-
-; 64: t6:
-; 64: jmp {{_?}}t6
-; 64: jmp {{_?}}bar
- %0 = icmp slt i32 %x, 10
- br i1 %0, label %bb, label %bb1
-
-bb:
- %1 = add nsw i32 %x, -1
- %2 = tail call i32 @t6(i32 %1) nounwind ssp
- ret i32 %2
-
-bb1:
- %3 = tail call i32 @bar(i32 %x) nounwind
- ret i32 %3
-}
-
-declare i32 @bar(i32)
-
-define i32 @t7(i32 %a, i32 %b, i32 %c) nounwind ssp {
-entry:
-; 32: t7:
-; 32: jmp {{_?}}bar2
-
-; 64: t7:
-; 64: jmp {{_?}}bar2
- %0 = tail call i32 @bar2(i32 %a, i32 %b, i32 %c) nounwind
- ret i32 %0
-}
-
-declare i32 @bar2(i32, i32, i32)
-
-define signext i16 @t8() nounwind ssp {
-entry:
-; 32: t8:
-; 32: call {{_?}}bar3
-
-; 64: t8:
-; 64: callq {{_?}}bar3
- %0 = tail call signext i16 @bar3() nounwind ; <i16> [#uses=1]
- ret i16 %0
-}
-
-declare signext i16 @bar3()
-
-define signext i16 @t9(i32 (i32)* nocapture %x) nounwind ssp {
-entry:
-; 32: t9:
-; 32: call *
-
-; 64: t9:
-; 64: callq *
- %0 = bitcast i32 (i32)* %x to i16 (i32)*
- %1 = tail call signext i16 %0(i32 0) nounwind
- ret i16 %1
-}
-
-define void @t10() nounwind ssp {
-entry:
-; 32: t10:
-; 32: call
-
-; 64: t10:
-; 64: callq
- %0 = tail call i32 @foo4() noreturn nounwind
- unreachable
-}
-
-declare i32 @foo4()
-
-define i32 @t11(i32 %x, i32 %y, i32 %z.0, i32 %z.1, i32 %z.2) nounwind ssp {
-; In 32-bit mode, it's emitting a bunch of dead loads that are not being
-; eliminated currently.
-
-; 32: t11:
-; 32-NOT: subl ${{[0-9]+}}, %esp
-; 32: jne
-; 32-NOT: movl
-; 32-NOT: addl ${{[0-9]+}}, %esp
-; 32: jmp {{_?}}foo5
-
-; 64: t11:
-; 64-NOT: subq ${{[0-9]+}}, %esp
-; 64-NOT: addq ${{[0-9]+}}, %esp
-; 64: jmp {{_?}}foo5
-entry:
- %0 = icmp eq i32 %x, 0
- br i1 %0, label %bb6, label %bb
-
-bb:
- %1 = tail call i32 @foo5(i32 %x, i32 %y, i32 %z.0, i32 %z.1, i32 %z.2) nounwind
- ret i32 %1
-
-bb6:
- ret i32 0
-}
-
-declare i32 @foo5(i32, i32, i32, i32, i32)
-
-%struct.t = type { i32, i32, i32, i32, i32 }
-
-define i32 @t12(i32 %x, i32 %y, %struct.t* byval align 4 %z) nounwind ssp {
-; 32: t12:
-; 32-NOT: subl ${{[0-9]+}}, %esp
-; 32-NOT: addl ${{[0-9]+}}, %esp
-; 32: jmp {{_?}}foo6
-
-; 64: t12:
-; 64-NOT: subq ${{[0-9]+}}, %esp
-; 64-NOT: addq ${{[0-9]+}}, %esp
-; 64: jmp {{_?}}foo6
-entry:
- %0 = icmp eq i32 %x, 0
- br i1 %0, label %bb2, label %bb
-
-bb:
- %1 = tail call i32 @foo6(i32 %x, i32 %y, %struct.t* byval align 4 %z) nounwind
- ret i32 %1
-
-bb2:
- ret i32 0
-}
-
-declare i32 @foo6(i32, i32, %struct.t* byval align 4)
-
-; rdar://r7717598
-%struct.ns = type { i32, i32 }
-%struct.cp = type { float, float }
-
-define %struct.ns* @t13(%struct.cp* %yy) nounwind ssp {
-; 32: t13:
-; 32-NOT: jmp
-; 32: call
-; 32: ret
-
-; 64: t13:
-; 64-NOT: jmp
-; 64: call
-; 64: ret
-entry:
- %0 = tail call fastcc %struct.ns* @foo7(%struct.cp* byval align 4 %yy, i8 signext 0) nounwind
- ret %struct.ns* %0
-}
-
-declare fastcc %struct.ns* @foo7(%struct.cp* byval align 4, i8 signext) nounwind ssp
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