[llvm-branch-commits] [llvm-branch] r98307 - in /llvm/branches/release_27: ./ docs/CodeGenerator.html docs/LangRef.html include/llvm/CallingConv.h lib/Target/X86/X86CallingConv.td lib/Target/X86/X86FastISel.cpp lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86RegisterInfo.cpp test/CodeGen/X86/ghc-cc.ll test/CodeGen/X86/ghc-cc64.ll
Tanya Lattner
tonic at nondot.org
Thu Mar 11 15:59:04 PST 2010
Author: tbrethou
Date: Thu Mar 11 17:59:04 2010
New Revision: 98307
URL: http://llvm.org/viewvc/llvm-project?rev=98307&view=rev
Log:
Merge 98212 from mainline.
add support, testcases, and dox for the new GHC calling
convention. Patch by David Terei!
Added:
llvm/branches/release_27/test/CodeGen/X86/ghc-cc.ll
- copied unchanged from r98212, llvm/trunk/test/CodeGen/X86/ghc-cc.ll
llvm/branches/release_27/test/CodeGen/X86/ghc-cc64.ll
- copied unchanged from r98212, llvm/trunk/test/CodeGen/X86/ghc-cc64.ll
Modified:
llvm/branches/release_27/ (props changed)
llvm/branches/release_27/docs/CodeGenerator.html
llvm/branches/release_27/docs/LangRef.html
llvm/branches/release_27/include/llvm/CallingConv.h
llvm/branches/release_27/lib/Target/X86/X86CallingConv.td
llvm/branches/release_27/lib/Target/X86/X86FastISel.cpp
llvm/branches/release_27/lib/Target/X86/X86ISelLowering.cpp
llvm/branches/release_27/lib/Target/X86/X86RegisterInfo.cpp
Propchange: llvm/branches/release_27/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Thu Mar 11 17:59:04 2010
@@ -1 +1 @@
-/llvm/trunk:98193,98203
+/llvm/trunk:98193,98203,98212
Modified: llvm/branches/release_27/docs/CodeGenerator.html
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_27/docs/CodeGenerator.html?rev=98307&r1=98306&r2=98307&view=diff
==============================================================================
--- llvm/branches/release_27/docs/CodeGenerator.html (original)
+++ llvm/branches/release_27/docs/CodeGenerator.html Thu Mar 11 17:59:04 2010
@@ -1678,7 +1678,8 @@
supported on x86/x86-64 and PowerPC. It is performed if:</p>
<ul>
- <li>Caller and callee have the calling convention <tt>fastcc</tt>.</li>
+ <li>Caller and callee have the calling convention <tt>fastcc</tt> or
+ <tt>cc 10</tt> (GHC call convention).</li>
<li>The call is a tail call - in tail position (ret immediately follows call
and ret uses value of call or is void).</li>
Modified: llvm/branches/release_27/docs/LangRef.html
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_27/docs/LangRef.html?rev=98307&r1=98306&r2=98307&view=diff
==============================================================================
--- llvm/branches/release_27/docs/LangRef.html (original)
+++ llvm/branches/release_27/docs/LangRef.html Thu Mar 11 17:59:04 2010
@@ -691,9 +691,9 @@
target, without having to conform to an externally specified ABI
(Application Binary Interface).
<a href="CodeGenerator.html#tailcallopt">Tail calls can only be optimized
- when this convention is used.</a> This calling convention does not
- support varargs and requires the prototype of all callees to exactly match
- the prototype of the function definition.</dd>
+ when this or the GHC convention is used.</a> This calling convention
+ does not support varargs and requires the prototype of all callees to
+ exactly match the prototype of the function definition.</dd>
<dt><b>"<tt>coldcc</tt>" - The cold calling convention</b>:</dt>
<dd>This calling convention attempts to make code in the caller as efficient
@@ -703,6 +703,26 @@
does not support varargs and requires the prototype of all callees to
exactly match the prototype of the function definition.</dd>
+ <dt><b>"<tt>cc <em>10</em></tt>" - GHC convention</b>:</dt>
+ <dd>This calling convention has been implemented specifically for use by the
+ <a href="http://www.haskell.org/ghc">Glasgow Haskell Compiler (GHC)</a>.
+ It passes everything in registers, going to extremes to achieve this by
+ disabling callee save registers. This calling convention should not be
+ used lightly but only for specific situations such as an alternative to
+ the <em>register pinning</em> performance technique often used when
+ implementing functional programming languages.At the moment only X86
+ supports this convention and it has the following limitations:
+ <ul>
+ <li>On <em>X86-32</em> only supports up to 4 bit type parameters. No
+ floating point types are supported.</li>
+ <li>On <em>X86-64</em> only supports up to 10 bit type parameters and
+ 6 floating point parameters.</li>
+ </ul>
+ This calling convention supports
+ <a href="CodeGenerator.html#tailcallopt">tail call optimization</a> but
+ requires both the caller and callee are using it.
+ </dd>
+
<dt><b>"<tt>cc <<em>n</em>></tt>" - Numbered convention</b>:</dt>
<dd>Any calling convention may be specified by number, allowing
target-specific calling conventions to be used. Target specific calling
Modified: llvm/branches/release_27/include/llvm/CallingConv.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_27/include/llvm/CallingConv.h?rev=98307&r1=98306&r2=98307&view=diff
==============================================================================
--- llvm/branches/release_27/include/llvm/CallingConv.h (original)
+++ llvm/branches/release_27/include/llvm/CallingConv.h Thu Mar 11 17:59:04 2010
@@ -44,6 +44,9 @@
// call does not break any live ranges in the caller side.
Cold = 9,
+ // GHC - Calling convention used by the Glasgow Haskell Compiler (GHC).
+ GHC = 10,
+
// Target - This is the start of the target-specific calling conventions,
// e.g. fastcall and thiscall on X86.
FirstTargetCC = 64,
Modified: llvm/branches/release_27/lib/Target/X86/X86CallingConv.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_27/lib/Target/X86/X86CallingConv.td?rev=98307&r1=98306&r2=98307&view=diff
==============================================================================
--- llvm/branches/release_27/lib/Target/X86/X86CallingConv.td (original)
+++ llvm/branches/release_27/lib/Target/X86/X86CallingConv.td Thu Mar 11 17:59:04 2010
@@ -221,6 +221,20 @@
CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 8>>
]>;
+def CC_X86_64_GHC : CallingConv<[
+ // Promote i8/i16/i32 arguments to i64.
+ CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
+
+ // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim
+ CCIfType<[i64],
+ CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
+
+ // Pass in STG registers: F1, F2, F3, F4, D1, D2
+ CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
+ CCIfSubtarget<"hasSSE1()",
+ CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>
+]>;
+
//===----------------------------------------------------------------------===//
// X86 C Calling Convention
//===----------------------------------------------------------------------===//
@@ -320,3 +334,11 @@
// Otherwise, same as everything else.
CCDelegateTo<CC_X86_32_Common>
]>;
+
+def CC_X86_32_GHC : CallingConv<[
+ // Promote i8/i16 arguments to i32.
+ CCIfType<[i8, i16], CCPromoteToType<i32>>,
+
+ // Pass in STG registers: Base, Sp, Hp, R1
+ CCIfType<[i32], CCAssignToReg<[EBX, EBP, EDI, ESI]>>
+]>;
Modified: llvm/branches/release_27/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_27/lib/Target/X86/X86FastISel.cpp?rev=98307&r1=98306&r2=98307&view=diff
==============================================================================
--- llvm/branches/release_27/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/branches/release_27/lib/Target/X86/X86FastISel.cpp Thu Mar 11 17:59:04 2010
@@ -172,7 +172,9 @@
CCAssignFn *X86FastISel::CCAssignFnForCall(CallingConv::ID CC,
bool isTaillCall) {
if (Subtarget->is64Bit()) {
- if (Subtarget->isTargetWin64())
+ if (CC == CallingConv::GHC)
+ return CC_X86_64_GHC;
+ else if (Subtarget->isTargetWin64())
return CC_X86_Win64_C;
else
return CC_X86_64_C;
@@ -182,6 +184,8 @@
return CC_X86_32_FastCall;
else if (CC == CallingConv::Fast)
return CC_X86_32_FastCC;
+ else if (CC == CallingConv::GHC)
+ return CC_X86_32_GHC;
else
return CC_X86_32_C;
}
Modified: llvm/branches/release_27/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_27/lib/Target/X86/X86ISelLowering.cpp?rev=98307&r1=98306&r2=98307&view=diff
==============================================================================
--- llvm/branches/release_27/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/release_27/lib/Target/X86/X86ISelLowering.cpp Thu Mar 11 17:59:04 2010
@@ -1378,6 +1378,8 @@
return !Subtarget->is64Bit();
case CallingConv::Fast:
return GuaranteedTailCallOpt;
+ case CallingConv::GHC:
+ return GuaranteedTailCallOpt;
}
}
@@ -1385,7 +1387,9 @@
/// given CallingConvention value.
CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
if (Subtarget->is64Bit()) {
- if (Subtarget->isTargetWin64())
+ if (CC == CallingConv::GHC)
+ return CC_X86_64_GHC;
+ else if (Subtarget->isTargetWin64())
return CC_X86_Win64_C;
else
return CC_X86_64_C;
@@ -1395,6 +1399,8 @@
return CC_X86_32_FastCall;
else if (CC == CallingConv::Fast)
return CC_X86_32_FastCC;
+ else if (CC == CallingConv::GHC)
+ return CC_X86_32_GHC;
else
return CC_X86_32_C;
}
@@ -1412,10 +1418,16 @@
/*AlwaysInline=*/true, NULL, 0, NULL, 0);
}
+/// IsTailCallConvention - Return true if the calling convention is one that
+/// supports tail call optimization.
+static bool IsTailCallConvention(CallingConv::ID CC) {
+ return (CC == CallingConv::Fast || CC == CallingConv::GHC);
+}
+
/// FuncIsMadeTailCallSafe - Return true if the function is being made into
/// a tailcall target by changing its ABI.
static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
- return GuaranteedTailCallOpt && CC == CallingConv::Fast;
+ return GuaranteedTailCallOpt && IsTailCallConvention(CC);
}
SDValue
@@ -1479,8 +1491,8 @@
bool Is64Bit = Subtarget->is64Bit();
bool IsWin64 = Subtarget->isTargetWin64();
- assert(!(isVarArg && CallConv == CallingConv::Fast) &&
- "Var args not supported with calling convention fastcc");
+ assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
+ "Var args not supported with calling convention fastcc or ghc");
// Assign locations to all of the incoming arguments.
SmallVector<CCValAssign, 16> ArgLocs;
@@ -1683,7 +1695,7 @@
} else {
BytesToPopOnReturn = 0; // Callee pops nothing.
// If this is an sret function, the return should pop the hidden pointer.
- if (!Is64Bit && CallConv != CallingConv::Fast && ArgsAreStructReturn(Ins))
+ if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
BytesToPopOnReturn = 4;
}
@@ -1779,8 +1791,8 @@
++NumTailCalls;
}
- assert(!(isVarArg && CallConv == CallingConv::Fast) &&
- "Var args not supported with calling convention fastcc");
+ assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
+ "Var args not supported with calling convention fastcc or ghc");
// Analyze operands of the call, assigning locations to each operand.
SmallVector<CCValAssign, 16> ArgLocs;
@@ -1794,7 +1806,7 @@
// This is a sibcall. The memory operands are available in caller's
// own caller's stack.
NumBytes = 0;
- else if (GuaranteedTailCallOpt && CallConv == CallingConv::Fast)
+ else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv))
NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
int FPDiff = 0;
@@ -2150,7 +2162,7 @@
unsigned NumBytesForCalleeToPush;
if (IsCalleePop(isVarArg, CallConv))
NumBytesForCalleeToPush = NumBytes; // Callee pops everything
- else if (!Is64Bit && CallConv != CallingConv::Fast && IsStructRet)
+ else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
// If this is a call to a struct-return function, the callee
// pops the hidden struct pointer, so we have to push it back.
// This is common for Darwin/X86, Linux & Mingw32 targets.
@@ -2288,14 +2300,14 @@
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins,
SelectionDAG& DAG) const {
- if (CalleeCC != CallingConv::Fast &&
+ if (!IsTailCallConvention(CalleeCC) &&
CalleeCC != CallingConv::C)
return false;
// If -tailcallopt is specified, make fastcc functions tail-callable.
const Function *CallerF = DAG.getMachineFunction().getFunction();
if (GuaranteedTailCallOpt) {
- if (CalleeCC == CallingConv::Fast &&
+ if (IsTailCallConvention(CalleeCC) &&
CallerF->getCallingConv() == CalleeCC)
return true;
return false;
Modified: llvm/branches/release_27/lib/Target/X86/X86RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_27/lib/Target/X86/X86RegisterInfo.cpp?rev=98307&r1=98306&r2=98307&view=diff
==============================================================================
--- llvm/branches/release_27/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/branches/release_27/lib/Target/X86/X86RegisterInfo.cpp Thu Mar 11 17:59:04 2010
@@ -294,13 +294,20 @@
const unsigned *
X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
bool callsEHReturn = false;
+ bool ghcCall = false;
if (MF) {
const MachineFrameInfo *MFI = MF->getFrameInfo();
const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
+ const Function *F = MF->getFunction();
+ ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
}
+ static const unsigned GhcCalleeSavedRegs[] = {
+ 0
+ };
+
static const unsigned CalleeSavedRegs32Bit[] = {
X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
};
@@ -326,7 +333,9 @@
X86::XMM14, X86::XMM15, 0
};
- if (Is64Bit) {
+ if (ghcCall) {
+ return GhcCalleeSavedRegs;
+ } else if (Is64Bit) {
if (IsWin64)
return CalleeSavedRegsWin64;
else
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