[llvm-branch-commits] [llvm-branch] r97695 - /llvm/branches/Apple/Hermes/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

[Dan Gohman]

Author: djg
Date: Wed Mar  3 18:27:07 2010
New Revision: 97695

URL: http://llvm.org/viewvc/llvm-project?rev=97695&view=rev
Log:
$ svn merge -c 97692 https://djg@llvm.org/svn/llvm-project/llvm/trunk
--- Merging r97692 into '.':
U    lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified:
    llvm/branches/Apple/Hermes/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/branches/Apple/Hermes/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Hermes/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=97695&r1=97694&r2=97695&view=diff
==============================================================================
--- llvm/branches/Apple/Hermes/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/branches/Apple/Hermes/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Mar  3 18:27:07 2010
@@ -1758,7 +1758,7 @@
   ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
   ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
   EVT VT = N1.getValueType();
-  unsigned BitWidth = VT.getSizeInBits();
+  unsigned BitWidth = VT.getScalarType().getSizeInBits();
 
   // fold vector ops
   if (VT.isVector()) {
@@ -1872,9 +1872,9 @@
     EVT MemVT = LN0->getMemoryVT();
     // If we zero all the possible extended bits, then we can turn this into
     // a zextload if we are running before legalize or the operation is legal.
-    unsigned BitWidth = N1.getValueSizeInBits();
+    unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
     if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
-                                     BitWidth - MemVT.getSizeInBits())) &&
+                           BitWidth - MemVT.getScalarType().getSizeInBits())) &&
         ((!LegalOperations && !LN0->isVolatile()) ||
          TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
       SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
@@ -1894,9 +1894,9 @@
     EVT MemVT = LN0->getMemoryVT();
     // If we zero all the possible extended bits, then we can turn this into
     // a zextload if we are running before legalize or the operation is legal.
-    unsigned BitWidth = N1.getValueSizeInBits();
+    unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
     if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
-                                     BitWidth - MemVT.getSizeInBits())) &&
+                           BitWidth - MemVT.getScalarType().getSizeInBits())) &&
         ((!LegalOperations && !LN0->isVolatile()) ||
          TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
       SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,