[llvm-branch-commits] [llvm-branch] r106694 - in /llvm/branches/Apple/Troughton: ./ lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h test/CodeGen/ARM/lsr-on-unrolled-loops.ll
Bill Wendling
isanbard at gmail.com
Wed Jun 23 16:02:33 PDT 2010
Author: void
Date: Wed Jun 23 18:02:33 2010
New Revision: 106694
URL: http://llvm.org/viewvc/llvm-project?rev=106694&view=rev
Log:
$ svn merge -c 106693 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r106693 into '.':
U test/CodeGen/ARM/lsr-on-unrolled-loops.ll
U lib/Target/ARM/ARMBaseInstrInfo.cpp
U lib/Target/ARM/ARMBaseInstrInfo.h
Modified:
llvm/branches/Apple/Troughton/ (props changed)
llvm/branches/Apple/Troughton/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/branches/Apple/Troughton/lib/Target/ARM/ARMBaseInstrInfo.h
llvm/branches/Apple/Troughton/test/CodeGen/ARM/lsr-on-unrolled-loops.ll
Propchange: llvm/branches/Apple/Troughton/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Wed Jun 23 18:02:33 2010
@@ -1 +1 @@
-/llvm/trunk:105358,105361,105369,105372,105399,105427,105437,105439,105441,105470,105473,105481,105498,105541,105554,105557,105585-105586,105634,105653,105665,105669,105677,105745,105749,105774-105775,105836,105845,105862,105886,105938,105959,105965,105969,105982,105990-105991,105997-105998,106004,106015,106021,106024,106027,106030,106051,106057,106146,106149,106152,106155,106157,106164,106199,106203-106204,106227,106229,106282,106289,106291-106292,106309,106312,106314,106318,106321,106324,106333,106336,106342,106345,106483-106484,106582,106630-106631
+/llvm/trunk:105358,105361,105369,105372,105399,105427,105437,105439,105441,105470,105473,105481,105498,105541,105554,105557,105585-105586,105634,105653,105665,105669,105677,105745,105749,105774-105775,105836,105845,105862,105886,105938,105959,105965,105969,105982,105990-105991,105997-105998,106004,106015,106021,106024,106027,106030,106051,106057,106146,106149,106152,106155,106157,106164,106199,106203-106204,106227,106229,106282,106289,106291-106292,106309,106312,106314,106318,106321,106324,106333,106336,106342,106345,106483-106484,106582,106630-106631,106693
Modified: llvm/branches/Apple/Troughton/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Troughton/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=106694&r1=106693&r2=106694&view=diff
==============================================================================
--- llvm/branches/Apple/Troughton/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/branches/Apple/Troughton/lib/Target/ARM/ARMBaseInstrInfo.cpp Wed Jun 23 18:02:33 2010
@@ -1308,6 +1308,107 @@
return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
}
+/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
+/// determine if two loads are loading from the same base address. It should
+/// only return true if the base pointers are the same and the only differences
+/// between the two addresses is the offset. It also returns the offsets by
+/// reference.
+bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
+ int64_t &Offset1,
+ int64_t &Offset2) const {
+ // Don't worry about Thumb: just ARM and Thumb2.
+ if (Subtarget.isThumb1Only()) return false;
+
+ if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
+ return false;
+
+ switch (Load1->getMachineOpcode()) {
+ default:
+ return false;
+ case ARM::LDR:
+ case ARM::LDRB:
+ case ARM::LDRD:
+ case ARM::LDRH:
+ case ARM::LDRSB:
+ case ARM::LDRSH:
+ case ARM::VLDRD:
+ case ARM::VLDRS:
+ case ARM::t2LDRi8:
+ case ARM::t2LDRDi8:
+ case ARM::t2LDRSHi8:
+ case ARM::t2LDRi12:
+ case ARM::t2LDRSHi12:
+ break;
+ }
+
+ switch (Load2->getMachineOpcode()) {
+ default:
+ return false;
+ case ARM::LDR:
+ case ARM::LDRB:
+ case ARM::LDRD:
+ case ARM::LDRH:
+ case ARM::LDRSB:
+ case ARM::LDRSH:
+ case ARM::VLDRD:
+ case ARM::VLDRS:
+ case ARM::t2LDRi8:
+ case ARM::t2LDRDi8:
+ case ARM::t2LDRSHi8:
+ case ARM::t2LDRi12:
+ case ARM::t2LDRSHi12:
+ break;
+ }
+
+ // Check if base addresses and chain operands match.
+ if (Load1->getOperand(0) != Load2->getOperand(0) ||
+ Load1->getOperand(4) != Load2->getOperand(4))
+ return false;
+
+ // Index should be Reg0.
+ if (Load1->getOperand(3) != Load2->getOperand(3))
+ return false;
+
+ // Determine the offsets.
+ if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
+ isa<ConstantSDNode>(Load2->getOperand(1))) {
+ Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
+ Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
+ return true;
+ }
+
+ return false;
+}
+
+/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
+/// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
+/// be scheduled togther. On some targets if two loads are loading from
+/// addresses in the same cache line, it's better if they are scheduled
+/// together. This function takes two integers that represent the load offsets
+/// from the common base address. It returns true if it decides it's desirable
+/// to schedule the two loads together. "NumLoads" is the number of loads that
+/// have already been scheduled after Load1.
+bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
+ int64_t Offset1, int64_t Offset2,
+ unsigned NumLoads) const {
+ // Don't worry about Thumb: just ARM and Thumb2.
+ if (Subtarget.isThumb1Only()) return false;
+
+ assert(Offset2 > Offset1);
+
+ if ((Offset2 - Offset1) / 8 > 64)
+ return false;
+
+ if (Load1->getMachineOpcode() != Load2->getMachineOpcode())
+ return false; // FIXME: overly conservative?
+
+ // Four loads in a row should be sufficient.
+ if (NumLoads >= 3)
+ return false;
+
+ return true;
+}
+
bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
const MachineBasicBlock *MBB,
const MachineFunction &MF) const {
Modified: llvm/branches/Apple/Troughton/lib/Target/ARM/ARMBaseInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Troughton/lib/Target/ARM/ARMBaseInstrInfo.h?rev=106694&r1=106693&r2=106694&view=diff
==============================================================================
--- llvm/branches/Apple/Troughton/lib/Target/ARM/ARMBaseInstrInfo.h (original)
+++ llvm/branches/Apple/Troughton/lib/Target/ARM/ARMBaseInstrInfo.h Wed Jun 23 18:02:33 2010
@@ -319,6 +319,26 @@
virtual bool produceSameValue(const MachineInstr *MI0,
const MachineInstr *MI1) const;
+ /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
+ /// determine if two loads are loading from the same base address. It should
+ /// only return true if the base pointers are the same and the only
+ /// differences between the two addresses is the offset. It also returns the
+ /// offsets by reference.
+ virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
+ int64_t &Offset1, int64_t &Offset2)const;
+
+ /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
+ /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
+ /// be scheduled togther. On some targets if two loads are loading from
+ /// addresses in the same cache line, it's better if they are scheduled
+ /// together. This function takes two integers that represent the load offsets
+ /// from the common base address. It returns true if it decides it's desirable
+ /// to schedule the two loads together. "NumLoads" is the number of loads that
+ /// have already been scheduled after Load1.
+ virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
+ int64_t Offset1, int64_t Offset2,
+ unsigned NumLoads) const;
+
virtual bool isSchedulingBoundary(const MachineInstr *MI,
const MachineBasicBlock *MBB,
const MachineFunction &MF) const;
Modified: llvm/branches/Apple/Troughton/test/CodeGen/ARM/lsr-on-unrolled-loops.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Troughton/test/CodeGen/ARM/lsr-on-unrolled-loops.ll?rev=106694&r1=106693&r2=106694&view=diff
==============================================================================
--- llvm/branches/Apple/Troughton/test/CodeGen/ARM/lsr-on-unrolled-loops.ll (original)
+++ llvm/branches/Apple/Troughton/test/CodeGen/ARM/lsr-on-unrolled-loops.ll Wed Jun 23 18:02:33 2010
@@ -626,9 +626,11 @@
; LSR should use count-down iteration to avoid requiring the trip count
; in a register, and it shouldn't require any reloads here.
-; CHECK: subs r3, #1
-; CHECK-NEXT: cmp r3, #0
-; CHECK-NEXT: bne.w
+; CHECK: @ %bb24
+; CHECK-NEXT: @ in Loop: Header=BB1_1 Depth=1
+; CHECK-NEXT: sub{{.*}} [[REGISTER:r[0-9]+]], #1
+; CHECK-NEXT: cmp{{.*}} [[REGISTER]], #0
+; CHECK-NEXT: bne.w
%92 = icmp eq i32 %tmp81, %indvar78 ; <i1> [#uses=1]
%indvar.next79 = add i32 %indvar78, 1 ; <i32> [#uses=1]
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