[llvm-branch-commits] [llvm-branch] r106519 - in /llvm/branches/Apple/Troughton: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/BranchFolding.cpp lib/CodeGen/BranchFolding.h lib/CodeGen/TargetInstrInfoImpl.cpp lib/Target/ARM/Thumb2ITBlockPass.cpp lib/Target/ARM/Thumb2InstrInfo.cpp lib/Target/ARM/Thumb2InstrInfo.h test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll
Evan Cheng
evan.cheng at apple.com
Mon Jun 21 18:22:43 PDT 2010
Author: evancheng
Date: Mon Jun 21 20:22:43 2010
New Revision: 106519
URL: http://llvm.org/viewvc/llvm-project?rev=106519&view=rev
Log:
Merge 106517.
Added:
llvm/branches/Apple/Troughton/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll
- copied unchanged from r106517, llvm/trunk/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll
Modified:
llvm/branches/Apple/Troughton/include/llvm/Target/TargetInstrInfo.h
llvm/branches/Apple/Troughton/lib/CodeGen/BranchFolding.cpp
llvm/branches/Apple/Troughton/lib/CodeGen/BranchFolding.h
llvm/branches/Apple/Troughton/lib/CodeGen/TargetInstrInfoImpl.cpp
llvm/branches/Apple/Troughton/lib/Target/ARM/Thumb2ITBlockPass.cpp
llvm/branches/Apple/Troughton/lib/Target/ARM/Thumb2InstrInfo.cpp
llvm/branches/Apple/Troughton/lib/Target/ARM/Thumb2InstrInfo.h
Modified: llvm/branches/Apple/Troughton/include/llvm/Target/TargetInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Troughton/include/llvm/Target/TargetInstrInfo.h?rev=106519&r1=106518&r2=106519&view=diff
==============================================================================
--- llvm/branches/Apple/Troughton/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/branches/Apple/Troughton/include/llvm/Target/TargetInstrInfo.h Mon Jun 21 20:22:43 2010
@@ -326,6 +326,14 @@
/// used by the tail merging pass.
virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
MachineBasicBlock *NewDest) const = 0;
+
+ /// isLegalToSplitMBBAt - Return true if it's legal to split the given basic
+ /// block at the specified instruction (i.e. instruction would be the start
+ /// of a new basic block).
+ virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI) const {
+ return true;
+ }
/// copyRegToReg - Emit instructions to copy between a pair of registers. It
/// returns false if the target does not how to copy between the specified
Modified: llvm/branches/Apple/Troughton/lib/CodeGen/BranchFolding.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Troughton/lib/CodeGen/BranchFolding.cpp?rev=106519&r1=106518&r2=106519&view=diff
==============================================================================
--- llvm/branches/Apple/Troughton/lib/CodeGen/BranchFolding.cpp (original)
+++ llvm/branches/Apple/Troughton/lib/CodeGen/BranchFolding.cpp Mon Jun 21 20:22:43 2010
@@ -370,6 +370,9 @@
/// iterator. This returns the new MBB.
MachineBasicBlock *BranchFolder::SplitMBBAt(MachineBasicBlock &CurMBB,
MachineBasicBlock::iterator BBI1) {
+ if (!TII->isLegalToSplitMBBAt(CurMBB, BBI1))
+ return 0;
+
MachineFunction &MF = *CurMBB.getParent();
// Create the fall-through block.
@@ -612,9 +615,10 @@
/// CreateCommonTailOnlyBlock - None of the blocks to be tail-merged consist
/// only of the common tail. Create a block that does by splitting one.
-unsigned BranchFolder::CreateCommonTailOnlyBlock(MachineBasicBlock *&PredBB,
- unsigned maxCommonTailLength) {
- unsigned commonTailIndex = 0;
+bool BranchFolder::CreateCommonTailOnlyBlock(MachineBasicBlock *&PredBB,
+ unsigned maxCommonTailLength,
+ unsigned &commonTailIndex) {
+ commonTailIndex = 0;
unsigned TimeEstimate = ~0U;
for (unsigned i = 0, e = SameTails.size(); i != e; ++i) {
// Use PredBB if possible; that doesn't require a new branch.
@@ -642,6 +646,11 @@
<< maxCommonTailLength);
MachineBasicBlock *newMBB = SplitMBBAt(*MBB, BBI);
+ if (!newMBB) {
+ DEBUG(dbgs() << "... failed!");
+ return false;
+ }
+
SameTails[commonTailIndex].setBlock(newMBB);
SameTails[commonTailIndex].setTailStartPos(newMBB->begin());
@@ -649,7 +658,7 @@
if (PredBB == MBB)
PredBB = newMBB;
- return commonTailIndex;
+ return true;
}
// See if any of the blocks in MergePotentials (which all have a common single
@@ -744,7 +753,11 @@
!SameTails[commonTailIndex].tailIsWholeBlock())) {
// None of the blocks consist entirely of the common tail.
// Split a block so that one does.
- commonTailIndex = CreateCommonTailOnlyBlock(PredBB, maxCommonTailLength);
+ if (!CreateCommonTailOnlyBlock(PredBB,
+ maxCommonTailLength, commonTailIndex)) {
+ RemoveBlocksWithHash(CurHash, SuccBB, PredBB);
+ continue;
+ }
}
MachineBasicBlock *MBB = SameTails[commonTailIndex].getBlock();
Modified: llvm/branches/Apple/Troughton/lib/CodeGen/BranchFolding.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Troughton/lib/CodeGen/BranchFolding.h?rev=106519&r1=106518&r2=106519&view=diff
==============================================================================
--- llvm/branches/Apple/Troughton/lib/CodeGen/BranchFolding.h (original)
+++ llvm/branches/Apple/Troughton/lib/CodeGen/BranchFolding.h Mon Jun 21 20:22:43 2010
@@ -102,8 +102,9 @@
MachineBasicBlock *PredBB);
void RemoveBlocksWithHash(unsigned CurHash, MachineBasicBlock* SuccBB,
MachineBasicBlock* PredBB);
- unsigned CreateCommonTailOnlyBlock(MachineBasicBlock *&PredBB,
- unsigned maxCommonTailLength);
+ bool CreateCommonTailOnlyBlock(MachineBasicBlock *&PredBB,
+ unsigned maxCommonTailLength,
+ unsigned &commonTailIndex);
bool OptimizeBranches(MachineFunction &MF);
bool OptimizeBlock(MachineBasicBlock *MBB);
Modified: llvm/branches/Apple/Troughton/lib/CodeGen/TargetInstrInfoImpl.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Troughton/lib/CodeGen/TargetInstrInfoImpl.cpp?rev=106519&r1=106518&r2=106519&view=diff
==============================================================================
--- llvm/branches/Apple/Troughton/lib/CodeGen/TargetInstrInfoImpl.cpp (original)
+++ llvm/branches/Apple/Troughton/lib/CodeGen/TargetInstrInfoImpl.cpp Mon Jun 21 20:22:43 2010
@@ -28,6 +28,8 @@
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
+/// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
+/// after it, replacing it with an unconditional branch to NewDest.
void
TargetInstrInfoImpl::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
MachineBasicBlock *NewDest) const {
Modified: llvm/branches/Apple/Troughton/lib/Target/ARM/Thumb2ITBlockPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Troughton/lib/Target/ARM/Thumb2ITBlockPass.cpp?rev=106519&r1=106518&r2=106519&view=diff
==============================================================================
--- llvm/branches/Apple/Troughton/lib/Target/ARM/Thumb2ITBlockPass.cpp (original)
+++ llvm/branches/Apple/Troughton/lib/Target/ARM/Thumb2ITBlockPass.cpp Mon Jun 21 20:22:43 2010
@@ -62,13 +62,6 @@
char Thumb2ITBlockPass::ID = 0;
}
-static ARMCC::CondCodes getPredicate(const MachineInstr *MI, unsigned &PredReg){
- unsigned Opc = MI->getOpcode();
- if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
- return ARMCC::AL;
- return llvm::getInstrPredicate(MI, PredReg);
-}
-
bool
Thumb2ITBlockPass::MoveCPSRUseUp(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
@@ -82,7 +75,7 @@
for (unsigned i = 0; i < 4; ++i) {
MachineInstr *MI = &*I;
unsigned MPredReg = 0;
- ARMCC::CondCodes MCC = getPredicate(MI, MPredReg);
+ ARMCC::CondCodes MCC = llvm::getITInstrPredicate(MI, MPredReg);
if (MCC != ARMCC::AL) {
if (MPredReg != PredReg || (MCC != CC && MCC != OCC))
return false;
@@ -209,7 +202,7 @@
return false;
unsigned PredReg = 0;
- ARMCC::CondCodes CC = getPredicate(First, PredReg);
+ ARMCC::CondCodes CC = llvm::getITInstrPredicate(First, PredReg);
if (CC == ARMCC::AL)
return Modified;
@@ -222,7 +215,7 @@
return Modified;
MachineInstr *NMI = &*MBBI;
unsigned NPredReg = 0;
- ARMCC::CondCodes NCC = getPredicate(NMI, NPredReg);
+ ARMCC::CondCodes NCC = llvm::getITInstrPredicate(NMI, NPredReg);
if (NCC != CC && NCC != OCC) {
if (NCC != ARMCC::AL)
return Modified;
@@ -321,7 +314,7 @@
while (I != E && I->isDebugValue())
++I;
unsigned NPredReg = 0;
- ARMCC::CondCodes NCC = getPredicate(I, NPredReg);
+ ARMCC::CondCodes NCC = llvm::getITInstrPredicate(I, NPredReg);
if (NCC == CC || NCC == OCC)
return true;
}
@@ -339,7 +332,7 @@
MachineInstr *MI = &*MBBI;
DebugLoc dl = MI->getDebugLoc();
unsigned PredReg = 0;
- ARMCC::CondCodes CC = getPredicate(MI, PredReg);
+ ARMCC::CondCodes CC = llvm::getITInstrPredicate(MI, PredReg);
if (CC == ARMCC::AL) {
++MBBI;
continue;
@@ -375,7 +368,7 @@
MI = NMI;
unsigned NPredReg = 0;
- ARMCC::CondCodes NCC = getPredicate(NMI, NPredReg);
+ ARMCC::CondCodes NCC = llvm::getITInstrPredicate(NMI, NPredReg);
if (NCC == CC || NCC == OCC) {
Mask |= (NCC & 1) << Pos;
// Add implicit use of ITSTATE.
Modified: llvm/branches/Apple/Troughton/lib/Target/ARM/Thumb2InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Troughton/lib/Target/ARM/Thumb2InstrInfo.cpp?rev=106519&r1=106518&r2=106519&view=diff
==============================================================================
--- llvm/branches/Apple/Troughton/lib/Target/ARM/Thumb2InstrInfo.cpp (original)
+++ llvm/branches/Apple/Troughton/lib/Target/ARM/Thumb2InstrInfo.cpp Mon Jun 21 20:22:43 2010
@@ -88,6 +88,14 @@
}
bool
+Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI) const {
+ unsigned PredReg = 0;
+ return llvm::getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
+}
+
+
+bool
Thumb2InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,
@@ -605,3 +613,11 @@
MBB->insert(++MBBI, SrcMI);
}
}
+
+ARMCC::CondCodes
+llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
+ unsigned Opc = MI->getOpcode();
+ if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
+ return ARMCC::AL;
+ return llvm::getInstrPredicate(MI, PredReg);
+}
Modified: llvm/branches/Apple/Troughton/lib/Target/ARM/Thumb2InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Troughton/lib/Target/ARM/Thumb2InstrInfo.h?rev=106519&r1=106518&r2=106519&view=diff
==============================================================================
--- llvm/branches/Apple/Troughton/lib/Target/ARM/Thumb2InstrInfo.h (original)
+++ llvm/branches/Apple/Troughton/lib/Target/ARM/Thumb2InstrInfo.h Mon Jun 21 20:22:43 2010
@@ -35,6 +35,9 @@
void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
MachineBasicBlock *NewDest) const;
+ bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI) const;
+
bool copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,
@@ -68,6 +71,13 @@
ScheduleHazardRecognizer *
CreateTargetPostRAHazardRecognizer(const InstrItineraryData &II) const;
};
+
+/// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical
+/// to llvm::getInstrPredicate except it returns AL for conditional branch
+/// instructions which are "predicated", but are not in IT blocks.
+ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
+
+
}
#endif // THUMB2INSTRUCTIONINFO_H
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