[llvm-branch-commits] [llvm-branch] r106369 - in /llvm/branches/Apple/Troughton: lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMInstrInfo.td test/CodeGen/ARM/call-tc.ll test/CodeGen/Thumb/2010-06-18-SibCallCrash.ll test/CodeGen/Thumb2/thumb2-call-tc.ll
Evan Cheng
evan.cheng at apple.com
Fri Jun 18 18:12:29 PDT 2010
Author: evancheng
Date: Fri Jun 18 20:12:29 2010
New Revision: 106369
URL: http://llvm.org/viewvc/llvm-project?rev=106369&view=rev
Log:
Merge 106362 and 106368.
Added:
llvm/branches/Apple/Troughton/test/CodeGen/Thumb/2010-06-18-SibCallCrash.ll
- copied unchanged from r106368, llvm/trunk/test/CodeGen/Thumb/2010-06-18-SibCallCrash.ll
Modified:
llvm/branches/Apple/Troughton/lib/Target/ARM/ARMISelLowering.cpp
llvm/branches/Apple/Troughton/lib/Target/ARM/ARMInstrInfo.td
llvm/branches/Apple/Troughton/test/CodeGen/ARM/call-tc.ll
llvm/branches/Apple/Troughton/test/CodeGen/Thumb2/thumb2-call-tc.ll
Modified: llvm/branches/Apple/Troughton/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Troughton/lib/Target/ARM/ARMISelLowering.cpp?rev=106369&r1=106368&r2=106369&view=diff
==============================================================================
--- llvm/branches/Apple/Troughton/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/branches/Apple/Troughton/lib/Target/ARM/ARMISelLowering.cpp Fri Jun 18 20:12:29 2010
@@ -1389,7 +1389,6 @@
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins,
SelectionDAG& DAG) const {
-
const Function *CallerF = DAG.getMachineFunction().getFunction();
CallingConv::ID CallerCC = CallerF->getCallingConv();
bool CCMatch = CallerCC == CalleeCC;
@@ -1407,19 +1406,29 @@
if (isCalleeStructRet || isCallerStructRet)
return false;
- // On Thumb, for the moment, we can only do this to functions defined in this
- // compilation, or to indirect calls. A Thumb B to an ARM function is not
- // easily fixed up in the linker, unlike BL.
- if (Subtarget->isThumb()) {
- if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
+ // FIXME: Completely disable sibcal for Thumb1 since Thumb1RegisterInfo::
+ // emitEpilogue is not ready for them.
+ if (Subtarget->isThumb1Only())
+ return false;
+
+ if (isa<ExternalSymbolSDNode>(Callee))
+ return false;
+
+ if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
+ if (Subtarget->isThumb1Only())
+ return false;
+
+ // On Thumb, for the moment, we can only do this to functions defined in this
+ // compilation, or to indirect calls. A Thumb B to an ARM function is not
+ // easily fixed up in the linker, unlike BL.
+ if (Subtarget->isThumb()) {
const GlobalValue *GV = G->getGlobal();
if (GV->isDeclaration() || GV->isWeakForLinker())
return false;
- } else if (isa<ExternalSymbolSDNode>(Callee)) {
- return false;
}
}
+
// If the calling conventions do not match, then we'd better make sure the
// results are returned in the same way as what the caller expects.
if (!CCMatch) {
Modified: llvm/branches/Apple/Troughton/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Troughton/lib/Target/ARM/ARMInstrInfo.td?rev=106369&r1=106368&r2=106369&view=diff
==============================================================================
--- llvm/branches/Apple/Troughton/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/branches/Apple/Troughton/lib/Target/ARM/ARMInstrInfo.td Fri Jun 18 20:12:29 2010
@@ -1040,33 +1040,26 @@
D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
D27, D28, D29, D30, D31, PC],
Uses = [SP] in {
- def TCRETURNdi : AInoP<(outs), (ins i32imm:$dst, variable_ops),
- Pseudo, IIC_Br,
- "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>;
-
- def TCRETURNri : AInoP<(outs), (ins tcGPR:$dst, variable_ops),
- Pseudo, IIC_Br,
- "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>;
-
- def TAILJMPd : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
- IIC_Br, "b.w\t$dst @ TAILCALL",
- []>, Requires<[IsDarwin]>;
-
- def TAILJMPr : AXI<(outs), (ins tcGPR:$dst, variable_ops),
- BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
- []>, Requires<[IsDarwin]> {
- let Inst{7-4} = 0b0001;
- let Inst{19-8} = 0b111111111111;
- let Inst{27-20} = 0b00010010;
- let Inst{31-28} = 0b1110;
- }
-
- // FIXME: This is a hack so that MCInst lowering can preserve the TAILCALL
- // marker on instructions, while still being able to relax.
-// let isCodeGenOnly = 1 in {
-// def TAILJMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
-// "jmp\t$dst @ TAILCALL", []>,
-// Requires<[IsARM, IsDarwin]>;
+ def TCRETURNdi : AInoP<(outs), (ins i32imm:$dst, variable_ops),
+ Pseudo, IIC_Br,
+ "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>;
+
+ def TCRETURNri : AInoP<(outs), (ins tcGPR:$dst, variable_ops),
+ Pseudo, IIC_Br,
+ "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>;
+
+ def TAILJMPd : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
+ IIC_Br, "b.w\t$dst @ TAILCALL",
+ []>, Requires<[IsDarwin]>;
+
+ def TAILJMPr : AXI<(outs), (ins tcGPR:$dst, variable_ops),
+ BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
+ []>, Requires<[IsDarwin]> {
+ let Inst{7-4} = 0b0001;
+ let Inst{19-8} = 0b111111111111;
+ let Inst{27-20} = 0b00010010;
+ let Inst{31-28} = 0b1110;
+ }
}
// Non-Darwin versions (the difference is R9).
@@ -1075,33 +1068,30 @@
D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
D27, D28, D29, D30, D31, PC],
Uses = [SP] in {
- def TCRETURNdiND : AInoP<(outs), (ins i32imm:$dst, variable_ops),
- Pseudo, IIC_Br,
- "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>;
-
- def TCRETURNriND : AInoP<(outs), (ins tGPR:$dst, variable_ops),
- Pseudo, IIC_Br,
- "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>;
-
- def TAILJMPdND : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
- IIC_Br, "b.w\t$dst @ TAILCALL",
- []>, Requires<[IsNotDarwin]>;
-
- def TAILJMPrND : AXI<(outs), (ins tGPR:$dst, variable_ops),
- BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
- []>, Requires<[IsNotDarwin]> {
- let Inst{7-4} = 0b0001;
- let Inst{19-8} = 0b111111111111;
- let Inst{27-20} = 0b00010010;
- let Inst{31-28} = 0b1110;
- }
-
- // FIXME: This is a hack so that MCInst lowering can preserve the TAILCALL
- // marker on instructions, while still being able to relax.
-// let isCodeGenOnly = 1 in {
-// def TAILJMP_1ND : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
-// "jmp\t$dst @ TAILCALL", []>,
-// Requires<[IsARM, IsNotDarwin]>;
+ def TCRETURNdiND : AInoP<(outs), (ins i32imm:$dst, variable_ops),
+ Pseudo, IIC_Br,
+ "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>;
+
+ def TCRETURNriND : AInoP<(outs), (ins tGPR:$dst, variable_ops),
+ Pseudo, IIC_Br,
+ "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>;
+
+ def TAILJMPdND : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
+ IIC_Br, "b\t$dst @ TAILCALL",
+ []>, Requires<[IsARM, IsNotDarwin]>;
+
+ def TAILJMPdNDt : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
+ IIC_Br, "b.w\t$dst @ TAILCALL",
+ []>, Requires<[IsThumb, IsNotDarwin]>;
+
+ def TAILJMPrND : AXI<(outs), (ins tGPR:$dst, variable_ops),
+ BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
+ []>, Requires<[IsNotDarwin]> {
+ let Inst{7-4} = 0b0001;
+ let Inst{19-8} = 0b111111111111;
+ let Inst{27-20} = 0b00010010;
+ let Inst{31-28} = 0b1110;
+ }
}
}
Modified: llvm/branches/Apple/Troughton/test/CodeGen/ARM/call-tc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Troughton/test/CodeGen/ARM/call-tc.ll?rev=106369&r1=106368&r2=106369&view=diff
==============================================================================
--- llvm/branches/Apple/Troughton/test/CodeGen/ARM/call-tc.ll (original)
+++ llvm/branches/Apple/Troughton/test/CodeGen/ARM/call-tc.ll Fri Jun 18 20:12:29 2010
@@ -7,22 +7,25 @@
declare void @g(i32, i32, i32, i32)
-define void @f() {
+define void @t1() {
+; CHECKELF: t1:
; CHECKELF: PLT
call void @g( i32 1, i32 2, i32 3, i32 4 )
ret void
}
-define void @g.upgrd.1() {
+define void @t2() {
+; CHECKV4: t2:
; CHECKV4: bx r0 @ TAILCALL
+; CHECKV5: t2:
; CHECKV5: bx r0 @ TAILCALL
%tmp = load i32 ()** @t ; <i32 ()*> [#uses=1]
%tmp.upgrd.2 = tail call i32 %tmp( ) ; <i32> [#uses=0]
ret void
}
-define i32* @m_231b(i32, i32, i32*, i32*, i32*) nounwind {
-; CHECKV4: m_231b
+define i32* @t3(i32, i32, i32*, i32*, i32*) nounwind {
+; CHECKV4: t3:
; CHECKV4: bx r{{.*}}
BB0:
%5 = inttoptr i32 %0 to i32* ; <i32*> [#uses=1]
Modified: llvm/branches/Apple/Troughton/test/CodeGen/Thumb2/thumb2-call-tc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Troughton/test/CodeGen/Thumb2/thumb2-call-tc.ll?rev=106369&r1=106368&r2=106369&view=diff
==============================================================================
--- llvm/branches/Apple/Troughton/test/CodeGen/Thumb2/thumb2-call-tc.ll (original)
+++ llvm/branches/Apple/Troughton/test/CodeGen/Thumb2/thumb2-call-tc.ll Fri Jun 18 20:12:29 2010
@@ -11,7 +11,7 @@
; LINUX: f:
; LINUX: bl g
- call void @g( i32 1, i32 2, i32 3, i32 4 )
+ tail call void @g( i32 1, i32 2, i32 3, i32 4 )
ret void
}
More information about the llvm-branch-commits
mailing list