[llvm-branch-commits] [llvm-branch] r105421 - in /llvm/branches/Apple/Morbo: lib/CodeGen/SelectionDAG/TargetLowering.cpp test/CodeGen/X86/promote-assert-zext.ll
Dan Gohman
gohman at apple.com
Thu Jun 3 14:56:48 PDT 2010
Author: djg
Date: Thu Jun 3 16:56:48 2010
New Revision: 105421
URL: http://llvm.org/viewvc/llvm-project?rev=105421&view=rev
Log:
$ svn merge -c 105406 https://djg@llvm.org/svn/llvm-project/llvm/trunk
--- Merging r105406 into '.':
A test/CodeGen/X86/promote-assert-zext.ll
U lib/CodeGen/SelectionDAG/TargetLowering.cpp
Added:
llvm/branches/Apple/Morbo/test/CodeGen/X86/promote-assert-zext.ll
- copied unchanged from r105406, llvm/trunk/test/CodeGen/X86/promote-assert-zext.ll
Modified:
llvm/branches/Apple/Morbo/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Modified: llvm/branches/Apple/Morbo/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=105421&r1=105420&r2=105421&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/branches/Apple/Morbo/lib/CodeGen/SelectionDAG/TargetLowering.cpp Thu Jun 3 16:56:48 2010
@@ -1487,13 +1487,17 @@
break;
}
case ISD::AssertZext: {
- EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
- APInt InMask = APInt::getLowBitsSet(BitWidth,
- VT.getSizeInBits());
- if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask,
+ // Demand all the bits of the input that are demanded in the output.
+ // The low bits are obvious; the high bits are demanded because we're
+ // asserting that they're zero here.
+ if (SimplifyDemandedBits(Op.getOperand(0), NewMask,
KnownZero, KnownOne, TLO, Depth+1))
return true;
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
+
+ EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
+ APInt InMask = APInt::getLowBitsSet(BitWidth,
+ VT.getSizeInBits());
KnownZero |= ~InMask & NewMask;
break;
}
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