[llvm-branch-commits] [llvm-branch] r107861 - in /llvm/branches/wendling/eh: ./ docs/ include/llvm/ include/llvm/ADT/ include/llvm/Analysis/ include/llvm/CodeGen/ include/llvm/Support/ include/llvm/Target/ lib/Analysis/ lib/Analysis/IPA/ lib/Archive/ lib/AsmParser/ lib/Bitcode/Reader/ lib/Bitcode/Writer/ lib/CodeGen/ lib/CodeGen/AsmPrinter/ lib/CodeGen/SelectionDAG/ lib/CompilerDriver/ lib/ExecutionEngine/ lib/ExecutionEngine/Interpreter/ lib/ExecutionEngine/JIT/ lib/Linker/ lib/MC/ lib/MC/MCParser/ lib/Support/ lib/System/ l...
Bill Wendling
isanbard at gmail.com
Thu Jul 8 01:14:10 PDT 2010
Author: void
Date: Thu Jul 8 03:14:09 2010
New Revision: 107861
URL: http://llvm.org/viewvc/llvm-project?rev=107861&view=rev
Log:
Merge with ToT.
Added:
llvm/branches/wendling/eh/include/llvm/CodeGen/FunctionLoweringInfo.h
- copied unchanged from r107860, llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h
llvm/branches/wendling/eh/include/llvm/Target/TargetCallingConv.h
- copied unchanged from r107860, llvm/trunk/include/llvm/Target/TargetCallingConv.h
llvm/branches/wendling/eh/lib/CodeGen/CallingConvLower.cpp
- copied unchanged from r107860, llvm/trunk/lib/CodeGen/CallingConvLower.cpp
Removed:
llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/CallingConvLower.cpp
llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.h
Modified:
llvm/branches/wendling/eh/ (props changed)
llvm/branches/wendling/eh/Makefile
llvm/branches/wendling/eh/Makefile.config.in
llvm/branches/wendling/eh/Makefile.rules
llvm/branches/wendling/eh/docs/AliasAnalysis.html
llvm/branches/wendling/eh/docs/DebuggingJITedCode.html (contents, props changed)
llvm/branches/wendling/eh/docs/GetElementPtr.html
llvm/branches/wendling/eh/docs/HowToReleaseLLVM.html
llvm/branches/wendling/eh/docs/LangRef.html
llvm/branches/wendling/eh/docs/MakefileGuide.html
llvm/branches/wendling/eh/docs/Passes.html
llvm/branches/wendling/eh/include/llvm/ADT/Triple.h
llvm/branches/wendling/eh/include/llvm/Analysis/AliasAnalysis.h
llvm/branches/wendling/eh/include/llvm/Analysis/Passes.h
llvm/branches/wendling/eh/include/llvm/CodeGen/CallingConvLower.h
llvm/branches/wendling/eh/include/llvm/CodeGen/FastISel.h
llvm/branches/wendling/eh/include/llvm/CodeGen/MachineBasicBlock.h
llvm/branches/wendling/eh/include/llvm/CodeGen/RegisterCoalescer.h
llvm/branches/wendling/eh/include/llvm/CodeGen/RegisterScavenging.h
llvm/branches/wendling/eh/include/llvm/CodeGen/SelectionDAG.h
llvm/branches/wendling/eh/include/llvm/CodeGen/SelectionDAGISel.h
llvm/branches/wendling/eh/include/llvm/CodeGen/SelectionDAGNodes.h
llvm/branches/wendling/eh/include/llvm/Instructions.h
llvm/branches/wendling/eh/include/llvm/Support/CallSite.h
llvm/branches/wendling/eh/include/llvm/Support/ELF.h
llvm/branches/wendling/eh/include/llvm/Support/IRBuilder.h
llvm/branches/wendling/eh/include/llvm/Target/TargetInstrInfo.h
llvm/branches/wendling/eh/include/llvm/Target/TargetLowering.h
llvm/branches/wendling/eh/include/llvm/Target/TargetRegisterInfo.h
llvm/branches/wendling/eh/lib/Analysis/ (props changed)
llvm/branches/wendling/eh/lib/Analysis/AliasAnalysis.cpp
llvm/branches/wendling/eh/lib/Analysis/AliasAnalysisEvaluator.cpp
llvm/branches/wendling/eh/lib/Analysis/BasicAliasAnalysis.cpp
llvm/branches/wendling/eh/lib/Analysis/ConstantFolding.cpp
llvm/branches/wendling/eh/lib/Analysis/IPA/ (props changed)
llvm/branches/wendling/eh/lib/Analysis/Lint.cpp
llvm/branches/wendling/eh/lib/Archive/ (props changed)
llvm/branches/wendling/eh/lib/AsmParser/ (props changed)
llvm/branches/wendling/eh/lib/Bitcode/Reader/ (props changed)
llvm/branches/wendling/eh/lib/Bitcode/Writer/ (props changed)
llvm/branches/wendling/eh/lib/CodeGen/ (props changed)
llvm/branches/wendling/eh/lib/CodeGen/AsmPrinter/ (props changed)
llvm/branches/wendling/eh/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
llvm/branches/wendling/eh/lib/CodeGen/AsmPrinter/DwarfDebug.h
llvm/branches/wendling/eh/lib/CodeGen/CMakeLists.txt
llvm/branches/wendling/eh/lib/CodeGen/LLVMTargetMachine.cpp
llvm/branches/wendling/eh/lib/CodeGen/LiveIntervalAnalysis.cpp
llvm/branches/wendling/eh/lib/CodeGen/LowerSubregs.cpp
llvm/branches/wendling/eh/lib/CodeGen/MachineBasicBlock.cpp
llvm/branches/wendling/eh/lib/CodeGen/MachineFunction.cpp
llvm/branches/wendling/eh/lib/CodeGen/ProcessImplicitDefs.cpp
llvm/branches/wendling/eh/lib/CodeGen/PrologEpilogInserter.cpp
llvm/branches/wendling/eh/lib/CodeGen/RegisterCoalescer.cpp
llvm/branches/wendling/eh/lib/CodeGen/RegisterScavenging.cpp
llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/ (props changed)
llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/CMakeLists.txt
llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/FastISel.cpp
llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/branches/wendling/eh/lib/CodeGen/SimpleRegisterCoalescing.cpp
llvm/branches/wendling/eh/lib/CodeGen/SimpleRegisterCoalescing.h
llvm/branches/wendling/eh/lib/CodeGen/Spiller.cpp
llvm/branches/wendling/eh/lib/CodeGen/StackProtector.cpp
llvm/branches/wendling/eh/lib/CodeGen/TargetInstrInfoImpl.cpp
llvm/branches/wendling/eh/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
llvm/branches/wendling/eh/lib/CodeGen/TwoAddressInstructionPass.cpp
llvm/branches/wendling/eh/lib/CompilerDriver/ (props changed)
llvm/branches/wendling/eh/lib/ExecutionEngine/ (props changed)
llvm/branches/wendling/eh/lib/ExecutionEngine/Interpreter/ (props changed)
llvm/branches/wendling/eh/lib/ExecutionEngine/JIT/ (props changed)
llvm/branches/wendling/eh/lib/Linker/ (props changed)
llvm/branches/wendling/eh/lib/MC/ (props changed)
llvm/branches/wendling/eh/lib/MC/MCParser/ (props changed)
llvm/branches/wendling/eh/lib/MC/MachObjectWriter.cpp
llvm/branches/wendling/eh/lib/Support/ (props changed)
llvm/branches/wendling/eh/lib/Support/Triple.cpp
llvm/branches/wendling/eh/lib/Support/raw_ostream.cpp
llvm/branches/wendling/eh/lib/System/ (props changed)
llvm/branches/wendling/eh/lib/System/Unix/Program.inc
llvm/branches/wendling/eh/lib/Target/ (props changed)
llvm/branches/wendling/eh/lib/Target/ARM/ (props changed)
llvm/branches/wendling/eh/lib/Target/ARM/ARMAddressingModes.h
llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseRegisterInfo.cpp
llvm/branches/wendling/eh/lib/Target/ARM/ARMConstantIslandPass.cpp
llvm/branches/wendling/eh/lib/Target/ARM/ARMISelDAGToDAG.cpp
llvm/branches/wendling/eh/lib/Target/ARM/ARMISelLowering.cpp
llvm/branches/wendling/eh/lib/Target/ARM/ARMISelLowering.h
llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrInfo.td
llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrNEON.td
llvm/branches/wendling/eh/lib/Target/ARM/AsmParser/ (props changed)
llvm/branches/wendling/eh/lib/Target/ARM/AsmPrinter/ (props changed)
llvm/branches/wendling/eh/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
llvm/branches/wendling/eh/lib/Target/ARM/Disassembler/ (props changed)
llvm/branches/wendling/eh/lib/Target/ARM/NEONMoveFix.cpp
llvm/branches/wendling/eh/lib/Target/ARM/TargetInfo/ (props changed)
llvm/branches/wendling/eh/lib/Target/Alpha/ (props changed)
llvm/branches/wendling/eh/lib/Target/Alpha/AlphaISelLowering.cpp
llvm/branches/wendling/eh/lib/Target/Alpha/AlphaISelLowering.h
llvm/branches/wendling/eh/lib/Target/Alpha/AsmPrinter/ (props changed)
llvm/branches/wendling/eh/lib/Target/Alpha/TargetInfo/ (props changed)
llvm/branches/wendling/eh/lib/Target/Blackfin/ (props changed)
llvm/branches/wendling/eh/lib/Target/Blackfin/AsmPrinter/ (props changed)
llvm/branches/wendling/eh/lib/Target/Blackfin/BlackfinISelLowering.cpp
llvm/branches/wendling/eh/lib/Target/Blackfin/BlackfinISelLowering.h
llvm/branches/wendling/eh/lib/Target/Blackfin/TargetInfo/ (props changed)
llvm/branches/wendling/eh/lib/Target/CBackend/ (props changed)
llvm/branches/wendling/eh/lib/Target/CBackend/TargetInfo/ (props changed)
llvm/branches/wendling/eh/lib/Target/CellSPU/ (props changed)
llvm/branches/wendling/eh/lib/Target/CellSPU/AsmPrinter/ (props changed)
llvm/branches/wendling/eh/lib/Target/CellSPU/SPUISelLowering.cpp
llvm/branches/wendling/eh/lib/Target/CellSPU/SPUISelLowering.h
llvm/branches/wendling/eh/lib/Target/CellSPU/TargetInfo/ (props changed)
llvm/branches/wendling/eh/lib/Target/CppBackend/ (props changed)
llvm/branches/wendling/eh/lib/Target/CppBackend/TargetInfo/ (props changed)
llvm/branches/wendling/eh/lib/Target/MBlaze/ (props changed)
llvm/branches/wendling/eh/lib/Target/MBlaze/AsmPrinter/ (props changed)
llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeISelLowering.cpp
llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeISelLowering.h
llvm/branches/wendling/eh/lib/Target/MBlaze/TargetInfo/ (props changed)
llvm/branches/wendling/eh/lib/Target/MSIL/ (props changed)
llvm/branches/wendling/eh/lib/Target/MSIL/TargetInfo/ (props changed)
llvm/branches/wendling/eh/lib/Target/MSP430/ (props changed)
llvm/branches/wendling/eh/lib/Target/MSP430/AsmPrinter/ (props changed)
llvm/branches/wendling/eh/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
llvm/branches/wendling/eh/lib/Target/MSP430/MSP430ISelLowering.cpp
llvm/branches/wendling/eh/lib/Target/MSP430/MSP430ISelLowering.h
llvm/branches/wendling/eh/lib/Target/MSP430/TargetInfo/ (props changed)
llvm/branches/wendling/eh/lib/Target/Mips/ (props changed)
llvm/branches/wendling/eh/lib/Target/Mips/AsmPrinter/ (props changed)
llvm/branches/wendling/eh/lib/Target/Mips/MipsISelLowering.cpp
llvm/branches/wendling/eh/lib/Target/Mips/MipsISelLowering.h
llvm/branches/wendling/eh/lib/Target/Mips/TargetInfo/ (props changed)
llvm/branches/wendling/eh/lib/Target/PIC16/ (props changed)
llvm/branches/wendling/eh/lib/Target/PIC16/AsmPrinter/ (props changed)
llvm/branches/wendling/eh/lib/Target/PIC16/PIC16ISelLowering.cpp
llvm/branches/wendling/eh/lib/Target/PIC16/PIC16ISelLowering.h
llvm/branches/wendling/eh/lib/Target/PIC16/PIC16Passes/ (props changed)
llvm/branches/wendling/eh/lib/Target/PIC16/TargetInfo/ (props changed)
llvm/branches/wendling/eh/lib/Target/PowerPC/ (props changed)
llvm/branches/wendling/eh/lib/Target/PowerPC/AsmPrinter/ (props changed)
llvm/branches/wendling/eh/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/branches/wendling/eh/lib/Target/PowerPC/PPCISelLowering.h
llvm/branches/wendling/eh/lib/Target/PowerPC/TargetInfo/ (props changed)
llvm/branches/wendling/eh/lib/Target/Sparc/ (props changed)
llvm/branches/wendling/eh/lib/Target/Sparc/AsmPrinter/ (props changed)
llvm/branches/wendling/eh/lib/Target/Sparc/SparcISelLowering.cpp
llvm/branches/wendling/eh/lib/Target/Sparc/SparcISelLowering.h
llvm/branches/wendling/eh/lib/Target/Sparc/TargetInfo/ (props changed)
llvm/branches/wendling/eh/lib/Target/SystemZ/ (props changed)
llvm/branches/wendling/eh/lib/Target/SystemZ/AsmPrinter/ (props changed)
llvm/branches/wendling/eh/lib/Target/SystemZ/SystemZISelLowering.cpp
llvm/branches/wendling/eh/lib/Target/SystemZ/SystemZISelLowering.h
llvm/branches/wendling/eh/lib/Target/SystemZ/TargetInfo/ (props changed)
llvm/branches/wendling/eh/lib/Target/TargetRegisterInfo.cpp
llvm/branches/wendling/eh/lib/Target/X86/ (props changed)
llvm/branches/wendling/eh/lib/Target/X86/AsmParser/ (props changed)
llvm/branches/wendling/eh/lib/Target/X86/AsmParser/X86AsmParser.cpp
llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/ (props changed)
llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp
llvm/branches/wendling/eh/lib/Target/X86/Disassembler/ (props changed)
llvm/branches/wendling/eh/lib/Target/X86/TargetInfo/ (props changed)
llvm/branches/wendling/eh/lib/Target/X86/X86AsmBackend.cpp
llvm/branches/wendling/eh/lib/Target/X86/X86FastISel.cpp
llvm/branches/wendling/eh/lib/Target/X86/X86FixupKinds.h
llvm/branches/wendling/eh/lib/Target/X86/X86ISelDAGToDAG.cpp
llvm/branches/wendling/eh/lib/Target/X86/X86ISelLowering.cpp
llvm/branches/wendling/eh/lib/Target/X86/X86ISelLowering.h
llvm/branches/wendling/eh/lib/Target/X86/X86Instr64bit.td
llvm/branches/wendling/eh/lib/Target/X86/X86InstrFormats.td
llvm/branches/wendling/eh/lib/Target/X86/X86InstrInfo.cpp
llvm/branches/wendling/eh/lib/Target/X86/X86InstrInfo.h
llvm/branches/wendling/eh/lib/Target/X86/X86InstrInfo.td
llvm/branches/wendling/eh/lib/Target/X86/X86InstrSSE.td
llvm/branches/wendling/eh/lib/Target/X86/X86MCCodeEmitter.cpp
llvm/branches/wendling/eh/lib/Target/X86/X86TargetMachine.cpp
llvm/branches/wendling/eh/lib/Target/XCore/ (props changed)
llvm/branches/wendling/eh/lib/Target/XCore/AsmPrinter/ (props changed)
llvm/branches/wendling/eh/lib/Target/XCore/TargetInfo/ (props changed)
llvm/branches/wendling/eh/lib/Target/XCore/XCoreISelLowering.cpp
llvm/branches/wendling/eh/lib/Target/XCore/XCoreISelLowering.h
llvm/branches/wendling/eh/lib/Transforms/Hello/ (props changed)
llvm/branches/wendling/eh/lib/Transforms/IPO/ (props changed)
llvm/branches/wendling/eh/lib/Transforms/IPO/MergeFunctions.cpp
llvm/branches/wendling/eh/lib/Transforms/InstCombine/ (props changed)
llvm/branches/wendling/eh/lib/Transforms/Instrumentation/ (props changed)
llvm/branches/wendling/eh/lib/Transforms/Scalar/ (props changed)
llvm/branches/wendling/eh/lib/Transforms/Scalar/ScalarReplAggregates.cpp
llvm/branches/wendling/eh/lib/Transforms/Utils/ (props changed)
llvm/branches/wendling/eh/lib/VMCore/ (props changed)
llvm/branches/wendling/eh/lib/VMCore/AsmWriter.cpp
llvm/branches/wendling/eh/lib/VMCore/Metadata.cpp
llvm/branches/wendling/eh/projects/sample/ (props changed)
llvm/branches/wendling/eh/projects/sample/lib/sample/ (props changed)
llvm/branches/wendling/eh/projects/sample/tools/sample/ (props changed)
llvm/branches/wendling/eh/runtime/libprofile/ (props changed)
llvm/branches/wendling/eh/tools/bugpoint/ (props changed)
llvm/branches/wendling/eh/tools/edis/ (props changed)
llvm/branches/wendling/eh/tools/llc/ (props changed)
llvm/branches/wendling/eh/tools/lli/ (props changed)
llvm/branches/wendling/eh/tools/llvm-ar/ (props changed)
llvm/branches/wendling/eh/tools/llvm-as/ (props changed)
llvm/branches/wendling/eh/tools/llvm-bcanalyzer/ (props changed)
llvm/branches/wendling/eh/tools/llvm-dis/ (props changed)
llvm/branches/wendling/eh/tools/llvm-extract/ (props changed)
llvm/branches/wendling/eh/tools/llvm-ld/ (props changed)
llvm/branches/wendling/eh/tools/llvm-link/ (props changed)
llvm/branches/wendling/eh/tools/llvm-mc/ (props changed)
llvm/branches/wendling/eh/tools/llvm-nm/ (props changed)
llvm/branches/wendling/eh/tools/llvm-prof/ (props changed)
llvm/branches/wendling/eh/tools/llvm-ranlib/ (props changed)
llvm/branches/wendling/eh/tools/llvm-stub/ (props changed)
llvm/branches/wendling/eh/tools/llvmc/driver/ (props changed)
llvm/branches/wendling/eh/tools/llvmc/plugins/Base/ (props changed)
llvm/branches/wendling/eh/tools/llvmc/plugins/Clang/ (props changed)
llvm/branches/wendling/eh/tools/lto/ (props changed)
llvm/branches/wendling/eh/tools/opt/ (props changed)
llvm/branches/wendling/eh/unittests/ADT/ (props changed)
llvm/branches/wendling/eh/unittests/ExecutionEngine/ (props changed)
llvm/branches/wendling/eh/unittests/ExecutionEngine/JIT/ (props changed)
llvm/branches/wendling/eh/unittests/Support/ (props changed)
llvm/branches/wendling/eh/unittests/Transforms/Utils/ (props changed)
llvm/branches/wendling/eh/unittests/VMCore/ (props changed)
llvm/branches/wendling/eh/utils/FileCheck/ (props changed)
llvm/branches/wendling/eh/utils/FileUpdate/ (props changed)
llvm/branches/wendling/eh/utils/NewNightlyTest.pl
llvm/branches/wendling/eh/utils/PerfectShuffle/ (props changed)
llvm/branches/wendling/eh/utils/TableGen/ (props changed)
llvm/branches/wendling/eh/utils/TableGen/ARMDecoderEmitter.cpp
llvm/branches/wendling/eh/utils/TableGen/EDEmitter.cpp
llvm/branches/wendling/eh/utils/TableGen/X86RecognizableInstr.cpp
llvm/branches/wendling/eh/utils/count/ (props changed)
llvm/branches/wendling/eh/utils/fpcmp/ (props changed)
llvm/branches/wendling/eh/utils/not/ (props changed)
llvm/branches/wendling/eh/utils/unittest/UnitTestMain/ (props changed)
llvm/branches/wendling/eh/utils/unittest/googletest/ (props changed)
Propchange: llvm/branches/wendling/eh/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -20,3 +20,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Thu Jul 8 03:14:09 2010
@@ -1 +1 @@
-/llvm/trunk:104459-107652
+/llvm/trunk:104459-107860
Modified: llvm/branches/wendling/eh/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/Makefile?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/Makefile (original)
+++ llvm/branches/wendling/eh/Makefile Thu Jul 8 03:14:09 2010
@@ -180,8 +180,8 @@
# that it gets executed last.
ifneq ($(BUILD_DIRS_ONLY),1)
all::
- $(Echo) '*****' Completed $(BuildMode)$(AssertMode) Build
-ifeq ($(BuildMode),Debug)
+ $(Echo) '*****' Completed $(BuildMode) Build
+ifneq ($(ENABLE_OPTIMIZED),1)
$(Echo) '*****' Note: Debug build can be 10 times slower than an
$(Echo) '*****' optimized build. Use 'make ENABLE_OPTIMIZED=1' to
$(Echo) '*****' make an optimized build. Alternatively you can
Modified: llvm/branches/wendling/eh/Makefile.config.in
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/Makefile.config.in?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/Makefile.config.in (original)
+++ llvm/branches/wendling/eh/Makefile.config.in Thu Jul 8 03:14:09 2010
@@ -222,8 +222,8 @@
# When ENABLE_PROFILING is enabled, profile instrumentation is done
# and output is put into the "<Flavor>+Profile" directories, where
-# <Flavor> is either Debug or Release depending on how other builkd
-# flags are set.. Otherwise, output is put in the <Flavor>
+# <Flavor> is either Debug or Release depending on how other build
+# flags are set. Otherwise, output is put in the <Flavor>
# directories.
#ENABLE_PROFILING = 1
@ENABLE_PROFILING@
Modified: llvm/branches/wendling/eh/Makefile.rules
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/Makefile.rules?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/Makefile.rules (original)
+++ llvm/branches/wendling/eh/Makefile.rules Thu Jul 8 03:14:09 2010
@@ -398,12 +398,11 @@
# If DISABLE_ASSERTIONS=1 is specified (make command line or configured),
# then disable assertions by defining the appropriate preprocessor symbols.
-ifdef DISABLE_ASSERTIONS
- # Indicate that assertions are turned off using a minus sign
- BuildMode := $(BuildMode)-Asserts
- CPP.Defines += -DNDEBUG
-else
+ifndef DISABLE_ASSERTIONS
+ BuildMode := $(BuildMode)+Asserts
CPP.Defines += -D_DEBUG
+else
+ CPP.Defines += -DNDEBUG
endif
# If ENABLE_EXPENSIVE_CHECKS=1 is specified (make command line or
Modified: llvm/branches/wendling/eh/docs/AliasAnalysis.html
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/docs/AliasAnalysis.html?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/docs/AliasAnalysis.html (original)
+++ llvm/branches/wendling/eh/docs/AliasAnalysis.html Thu Jul 8 03:14:09 2010
@@ -117,6 +117,11 @@
call. The <tt>AliasAnalysis</tt> interface also exposes some helper methods
which allow you to get mod/ref information for arbitrary instructions.</p>
+<p>All <tt>AliasAnalysis</tt> interfaces require that in queries involving
+multiple values, values which are not
+<a href="LangRef.html#constants">constants</a> are all defined within the
+same function.</p>
+
</div>
<!-- ======================================================================= -->
@@ -181,9 +186,13 @@
</div>
<div class="doc_text">
-The <tt>alias</tt> method is the primary interface used to determine whether or
-not two memory objects alias each other. It takes two memory objects as input
-and returns MustAlias, MayAlias, or NoAlias as appropriate.
+<p>The <tt>alias</tt> method is the primary interface used to determine whether
+or not two memory objects alias each other. It takes two memory objects as
+input and returns MustAlias, MayAlias, or NoAlias as appropriate.</p>
+
+<p>Like all <tt>AliasAnalysis</tt> interfaces, the <tt>alias</tt> method requires
+that either the two pointer values be defined within the same function, or at
+least one of the values is a <a href="LangRef.html#constants">constant</a>.</p>
</div>
<!-- _______________________________________________________________________ -->
@@ -202,10 +211,8 @@
and reallocation.</p>
<p>As an exception to this is with the
-<a href="LangRef.html#noalias"><tt>noalias</tt></a> keyword. AliasAnalysis
-implementations may choose to respect the <tt>noalias</tt> keyword and ignore
-the "irrelevant" dependencies, provided their clients do not need to be aware
-of these dependencies for correctness.</p>
+<a href="LangRef.html#noalias"><tt>noalias</tt></a> keyword; the "irrelevant"
+dependencies are ignored.</p>
<p>The MayAlias response is used whenever the two pointers might refer to the
same object. If the two memory objects overlap, but do not start at the same
Modified: llvm/branches/wendling/eh/docs/DebuggingJITedCode.html
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/docs/DebuggingJITedCode.html?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/docs/DebuggingJITedCode.html (original)
+++ llvm/branches/wendling/eh/docs/DebuggingJITedCode.html Thu Jul 8 03:14:09 2010
@@ -9,87 +9,24 @@
<div class="doc_title">Debugging JITed Code With GDB</div>
<ol>
- <li><a href="#introduction">Introduction</a></li>
- <li><a href="#quickstart">Quickstart</a></li>
- <li><a href="#example">Example with clang and lli</a></li>
+ <li><a href="#example">Example usage</a></li>
+ <li><a href="#background">Background</a></li>
</ol>
<div class="doc_author">Written by Reid Kleckner</div>
<!--=========================================================================-->
-<div class="doc_section"><a name="introduction">Introduction</a></div>
+<div class="doc_section"><a name="example">Example usage</a></div>
<!--=========================================================================-->
<div class="doc_text">
-<p>Without special runtime support, debugging dynamically generated code with
-GDB (as well as most debuggers) can be quite painful. Debuggers generally read
-debug information from the object file of the code, but for JITed code, there is
-no such file to look for.
-</p>
-
-<p>Depending on the architecture, this can impact the debugging experience in
-different ways. For example, on most 32-bit x86 architectures, you can simply
-compile with -fno-omit-frame-pointer for GCC and -disable-fp-elim for LLVM.
-When GDB creates a backtrace, it can properly unwind the stack, but the stack
-frames owned by JITed code have ??'s instead of the appropriate symbol name.
-However, on Linux x86_64 in particular, GDB relies on the DWARF CFA debug
-information to unwind the stack, so even if you compile your program to leave
-the frame pointer untouched, GDB will usually be unable to unwind the stack past
-any JITed code stack frames.
+<p>In order to debug code JITed by LLVM, you need GDB 7.0 or newer, which is
+available on most modern distributions of Linux. The version of GDB that Apple
+ships with XCode has been frozen at 6.3 for a while. LLDB may be a better
+option for debugging JITed code on Mac OS X.
</p>
-<p>In order to communicate the necessary debug info to GDB, an interface for
-registering JITed code with debuggers has been designed and implemented for
-GDB and LLVM. At a high level, whenever LLVM generates new machine code, it
-also generates an object file in memory containing the debug information. LLVM
-then adds the object file to the global list of object files and calls a special
-function (__jit_debug_register_code) marked noinline that GDB knows about. When
-GDB attaches to a process, it puts a breakpoint in this function and loads all
-of the object files in the global list. When LLVM calls the registration
-function, GDB catches the breakpoint signal, loads the new object file from
-LLVM's memory, and resumes the execution. In this way, GDB can get the
-necessary debug information.
-</p>
-
-<p>At the time of this writing, LLVM only supports architectures that use ELF
-object files and it only generates symbols and DWARF CFA information. However,
-it would be easy to add more information to the object file, so we don't need to
-coordinate with GDB to get better debug information.
-</p>
-</div>
-
-<!--=========================================================================-->
-<div class="doc_section"><a name="quickstart">Quickstart</a></div>
-<!--=========================================================================-->
-<div class="doc_text">
-
-<p>In order to debug code JITed by LLVM, you need to install a recent version
-of GDB. The interface was added on 2009-08-19, so you need a snapshot of GDB
-more recent than that. Either download a snapshot of GDB or checkout CVS as
-instructed <a href="http://www.gnu.org/software/gdb/current/">here</a>. Here
-are the commands for doing a checkout and building the code:
-</p>
-
-<pre class="doc_code">
-$ cvs -z 3 -d :pserver:anoncvs at sourceware.org:/cvs/src co gdb
-$ mv src gdb # You probably don't want this checkout called "src".
-$ cd gdb
-$ ./configure --prefix="$GDB_INSTALL"
-$ make
-$ make install
-</pre>
-
-<p>You can then use -jit-emit-debug in the LLVM command line arguments to enable
-the interface.
-</p>
-</div>
-
-<!--=========================================================================-->
-<div class="doc_section"><a name="example">Example with clang and lli</a></div>
-<!--=========================================================================-->
-<div class="doc_text">
-
-<p>For example, consider debugging running lli on the following C code in
-foo.c:
+<p>Consider debugging the following code compiled with clang and run through
+lli:
</p>
<pre class="doc_code">
@@ -119,7 +56,9 @@
<pre class="doc_code">
# Compile foo.c to bitcode. You can use either clang or llvm-gcc with this
# command line. Both require -fexceptions, or the calls are all marked
-# 'nounwind' which disables DWARF CFA info.
+# 'nounwind' which disables DWARF exception handling info. Custom frontends
+# should avoid adding this attribute to JITed code, since it interferes with
+# DWARF CFA generation at the moment.
$ clang foo.c -fexceptions -emit-llvm -c -o foo.bc
# Run foo.bc under lli with -jit-emit-debug. If you built lli in debug mode,
@@ -143,18 +82,60 @@
#3 0x00007ffff7f5502a in main ()
#4 0x00000000007c0225 in llvm::JIT::runFunction(llvm::Function*,
std::vector<llvm::GenericValue,
- std::allocator<llvm::GenericValue> > const&) ()
+ std::allocator<llvm::GenericValue> > const&) ()
#5 0x00000000007d6d98 in
llvm::ExecutionEngine::runFunctionAsMain(llvm::Function*,
std::vector<std::string,
- std::allocator<std::string> > const&, char const* const*) ()
+ std::allocator<std::string> > const&, char const* const*) ()
#6 0x00000000004dab76 in main ()
</pre>
-</div>
<p>As you can see, GDB can correctly unwind the stack and has the appropriate
function names.
</p>
+</div>
+
+<!--=========================================================================-->
+<div class="doc_section"><a name="background">Background</a></div>
+<!--=========================================================================-->
+<div class="doc_text">
+
+<p>Without special runtime support, debugging dynamically generated code with
+GDB (as well as most debuggers) can be quite painful. Debuggers generally read
+debug information from the object file of the code, but for JITed code, there is
+no such file to look for.
+</p>
+
+<p>Depending on the architecture, this can impact the debugging experience in
+different ways. For example, on most 32-bit x86 architectures, you can simply
+compile with -fno-omit-frame-pointer for GCC and -disable-fp-elim for LLVM.
+When GDB creates a backtrace, it can properly unwind the stack, but the stack
+frames owned by JITed code have ??'s instead of the appropriate symbol name.
+However, on Linux x86_64 in particular, GDB relies on the DWARF call frame
+address (CFA) debug information to unwind the stack, so even if you compile
+your program to leave the frame pointer untouched, GDB will usually be unable
+to unwind the stack past any JITed code stack frames.
+</p>
+
+<p>In order to communicate the necessary debug info to GDB, an interface for
+registering JITed code with debuggers has been designed and implemented for
+GDB and LLVM. At a high level, whenever LLVM generates new machine code, it
+also generates an object file in memory containing the debug information. LLVM
+then adds the object file to the global list of object files and calls a special
+function (__jit_debug_register_code) marked noinline that GDB knows about. When
+GDB attaches to a process, it puts a breakpoint in this function and loads all
+of the object files in the global list. When LLVM calls the registration
+function, GDB catches the breakpoint signal, loads the new object file from
+LLVM's memory, and resumes the execution. In this way, GDB can get the
+necessary debug information.
+</p>
+
+<p>At the time of this writing, LLVM only supports architectures that use ELF
+object files and it only generates symbols and DWARF CFA information. However,
+it would be easy to add more information to the object file, so we don't need to
+coordinate with GDB to get better debug information.
+</p>
+</div>
<!-- *********************************************************************** -->
<hr>
@@ -165,7 +146,7 @@
src="http://www.w3.org/Icons/valid-html401-blue" alt="Valid HTML 4.01"></a>
<a href="mailto:reid.kleckner at gmail.com">Reid Kleckner</a><br>
<a href="http://llvm.org">The LLVM Compiler Infrastructure</a><br>
- Last modified: $Date: 2009-01-01 23:10:51 -0800 (Thu, 01 Jan 2009) $
+ Last modified: $Date$
</address>
</body>
</html>
Propchange: llvm/branches/wendling/eh/docs/DebuggingJITedCode.html
------------------------------------------------------------------------------
svn:keywords = Date
Modified: llvm/branches/wendling/eh/docs/GetElementPtr.html
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/docs/GetElementPtr.html?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/docs/GetElementPtr.html (original)
+++ llvm/branches/wendling/eh/docs/GetElementPtr.html Thu Jul 8 03:14:09 2010
@@ -64,7 +64,8 @@
<div class="doc_text">
<p>This document seeks to dispel the mystery and confusion surrounding LLVM's
- GetElementPtr (GEP) instruction. Questions about the wily GEP instruction are
+ <a href="LangRef.html#i_getelementptr">GetElementPtr</a> (GEP) instruction.
+ Questions about the wily GEP instruction are
probably the most frequently occurring questions once a developer gets down to
coding with LLVM. Here we lay out the sources of confusion and show that the
GEP instruction is really quite simple.
@@ -653,7 +654,8 @@
<li>Support C, C-like languages, and languages which can be
conceptually lowered into C (this covers a lot).</li>
<li>Support optimizations such as those that are common in
- C compilers.</li>
+ C compilers. In particular, GEP is a cornerstone of LLVM's
+ <a href="LangRef.html#pointeraliasing">pointer aliasing model</a>.</li>
<li>Provide a consistent method for computing addresses so that
address computations don't need to be a part of load and
store instructions in the IR.</li>
Modified: llvm/branches/wendling/eh/docs/HowToReleaseLLVM.html
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/docs/HowToReleaseLLVM.html?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/docs/HowToReleaseLLVM.html (original)
+++ llvm/branches/wendling/eh/docs/HowToReleaseLLVM.html Thu Jul 8 03:14:09 2010
@@ -213,13 +213,13 @@
<div class="doc_text">
The build of <tt>llvm</tt>, <tt>llvm-gcc</tt>, and <tt>clang</tt> must be free
-of errors and warnings in both debug, release, and release-asserts builds.
+of errors and warnings in both debug, release+asserts, and release builds.
If all builds are clean, then the release passes build qualification.
<ol>
<li>debug: ENABLE_OPTIMIZED=0</li>
-<li>release: ENABLE_OPTIMIZED=1</li>
-<li>release-asserts: ENABLE_OPTIMIZED=1 DISABLE_ASSERTIONS=1</li>
+<li>release+asserts: ENABLE_OPTIMIZED=1</li>
+<li>release: ENABLE_OPTIMIZED=1 DISABLE_ASSERTIONS=1</li>
</ol>
</div>
@@ -227,7 +227,7 @@
<div class="doc_subsubsection"><a name="build">Build LLVM</a></div>
<div class="doc_text">
<p>
- Build both debug, release (optimized), and release-asserts versions of
+ Build both debug, release+asserts (optimized), and release versions of
LLVM on all supported platforms. Direction to build llvm are
<a href="http://llvm.org/docs/GettingStarted.html#quickstart">here</a>.
</p>
@@ -264,7 +264,7 @@
Binary Distribution</a></div>
<div class="doc_text">
<p>
- Creating the Clang binary distribution (debug/release/release-asserts) requires
+ Creating the Clang binary distribution (debug/release/release) requires
performing the following steps for each supported platform:
</p>
@@ -429,7 +429,7 @@
</a></div>
<div class="doc_text">
<p>
- The final stages of the release process involving taging the release branch,
+ The final stages of the release process involving tagging the release branch,
updating documentation that refers to the release, and updating the demo
page.</p>
<p>FIXME: Add a note if anything needs to be done to the clang website.
Modified: llvm/branches/wendling/eh/docs/LangRef.html
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/docs/LangRef.html?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/docs/LangRef.html (original)
+++ llvm/branches/wendling/eh/docs/LangRef.html Thu Jul 8 03:14:09 2010
@@ -1062,7 +1062,15 @@
The caller shares the responsibility with the callee for ensuring that
these requirements are met.
For further details, please see the discussion of the NoAlias response in
- <a href="AliasAnalysis.html#MustMayNo">alias analysis</a>.</dd>
+ <a href="AliasAnalysis.html#MustMayNo">alias analysis</a>.<br>
+<br>
+ Note that this definition of <tt>noalias</tt> is intentionally
+ similar to the definition of <tt>restrict</tt> in C99 for function
+ arguments, though it is slightly weaker.
+<br>
+ For function return values, C99's <tt>restrict</tt> is not meaningful,
+ while LLVM's <tt>noalias</tt> is.
+ </dd>
<dt><tt><b><a name="nocapture">nocapture</a></b></tt></dt>
<dd>This indicates that the callee does not make any copies of the pointer
@@ -1139,15 +1147,21 @@
this function is desirable (such as the "inline" keyword in C/C++). It
is just a hint; it imposes no requirements on the inliner.</dd>
+ <dt><tt><b>naked</b></tt></dt>
+ <dd>This attribute disables prologue / epilogue emission for the function.
+ This can have very system-specific consequences.</dd>
+
+ <dt><tt><b>noimplicitfloat</b></tt></dt>
+ <dd>This attributes disables implicit floating point instructions.</dd>
+
<dt><tt><b>noinline</b></tt></dt>
<dd>This attribute indicates that the inliner should never inline this
function in any situation. This attribute may not be used together with
the <tt>alwaysinline</tt> attribute.</dd>
- <dt><tt><b>optsize</b></tt></dt>
- <dd>This attribute suggests that optimization passes and code generator passes
- make choices that keep the code size of this function low, and otherwise
- do optimizations specifically to reduce code size.</dd>
+ <dt><tt><b>noredzone</b></tt></dt>
+ <dd>This attribute indicates that the code generator should not use a red
+ zone, even if the target-specific ABI normally permits it.</dd>
<dt><tt><b>noreturn</b></tt></dt>
<dd>This function attribute indicates that the function never returns
@@ -1159,6 +1173,11 @@
unwind or exceptional control flow. If the function does unwind, its
runtime behavior is undefined.</dd>
+ <dt><tt><b>optsize</b></tt></dt>
+ <dd>This attribute suggests that optimization passes and code generator passes
+ make choices that keep the code size of this function low, and otherwise
+ do optimizations specifically to reduce code size.</dd>
+
<dt><tt><b>readnone</b></tt></dt>
<dd>This attribute indicates that the function computes its result (or decides
to unwind an exception) based strictly on its arguments, without
@@ -1201,17 +1220,6 @@
function that doesn't have an <tt>sspreq</tt> attribute or which has
an <tt>ssp</tt> attribute, then the resulting function will have
an <tt>sspreq</tt> attribute.</dd>
-
- <dt><tt><b>noredzone</b></tt></dt>
- <dd>This attribute indicates that the code generator should not use a red
- zone, even if the target-specific ABI normally permits it.</dd>
-
- <dt><tt><b>noimplicitfloat</b></tt></dt>
- <dd>This attributes disables implicit floating point instructions.</dd>
-
- <dt><tt><b>naked</b></tt></dt>
- <dd>This attribute disables prologue / epilogue emission for the function.
- This can have very system-specific consequences.</dd>
</dl>
</div>
@@ -2397,7 +2405,8 @@
<li>An instruction with externally visible side effects depends on the most
recent preceding instruction with externally visible side effects, following
- the order in the IR. (This includes volatile loads and stores.)</li>
+ the order in the IR. (This includes
+ <a href="#volatile">volatile operations</a>.)</li>
<li>An instruction <i>control-depends</i> on a
<a href="#terminators">terminator instruction</a>
Modified: llvm/branches/wendling/eh/docs/MakefileGuide.html
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/docs/MakefileGuide.html?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/docs/MakefileGuide.html (original)
+++ llvm/branches/wendling/eh/docs/MakefileGuide.html Thu Jul 8 03:14:09 2010
@@ -652,7 +652,7 @@
the profiled tools (<tt>gmon.out</tt>).</dd>
<dt><a name="DISABLE_ASSERTIONS"><tt>DISABLE_ASSERTIONS</tt></a></dt>
<dd>If set to any value, causes the build to disable assertions, even if
- building a release or profile build. This will exclude all assertion check
+ building a debug or profile build. This will exclude all assertion check
code from the build. LLVM will execute faster, but with little help when
things go wrong.</dd>
<dt><a name="EXPERIMENTAL_DIRS"><tt>EXPERIMENTAL_DIRS</tt></a></dt>
Modified: llvm/branches/wendling/eh/docs/Passes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/docs/Passes.html?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/docs/Passes.html (original)
+++ llvm/branches/wendling/eh/docs/Passes.html Thu Jul 8 03:14:09 2010
@@ -27,7 +27,7 @@
my $o = $order{$1};
$o = "000" unless defined $o;
push @x, "$o<tr><td><a href=\"#$1\">-$1</a></td><td>$2</td></tr>\n";
- push @y, "$o <a name=\"$1\">$2</a>\n";
+ push @y, "$o <a name=\"$1\">-$1: $2</a>\n";
}
@x = map { s/^\d\d\d//; $_ } sort @x;
@y = map { s/^\d\d\d//; $_ } sort @y;
@@ -91,29 +91,46 @@
<tr><td><a href="#dot-postdom-only">-dot-postdom-only</a></td><td>Print post dominator tree of function to 'dot' file (with no function bodies)</td></tr>
<tr><td><a href="#globalsmodref-aa">-globalsmodref-aa</a></td><td>Simple mod/ref analysis for globals</td></tr>
<tr><td><a href="#instcount">-instcount</a></td><td>Counts the various types of Instructions</td></tr>
+<tr><td><a href="#interprocedural-aa-eval">-interprocedural-aa-eval</a></td><td>Exhaustive Interprocedural Alias Analysis Precision Evaluator</td></tr>
+<tr><td><a href="#interprocedural-basic-aa">-interprocedural-basic-aa</a></td><td>Interprocedural Basic Alias Analysis</td></tr>
<tr><td><a href="#intervals">-intervals</a></td><td>Interval Partition Construction</td></tr>
-<tr><td><a href="#loops">-loops</a></td><td>Natural Loop Construction</td></tr>
+<tr><td><a href="#iv-users">-iv-users</a></td><td>Induction Variable Users</td></tr>
+<tr><td><a href="#lazy-value-info">-lazy-value-info</a></td><td>Lazy Value Information Analysis</td></tr>
+<tr><td><a href="#lda">-lda</a></td><td>Loop Dependence Analysis</td></tr>
+<tr><td><a href="#libcall-aa">-libcall-aa</a></td><td>LibCall Alias Analysis</td></tr>
+<tr><td><a href="#lint">-lint</a></td><td>Check for common errors in LLVM IR</td></tr>
+<tr><td><a href="#live-values">-live-values</a></td><td>Value Liveness Analysis</td></tr>
+<tr><td><a href="#loops">-loops</a></td><td>Natural Loop Information</td></tr>
<tr><td><a href="#memdep">-memdep</a></td><td>Memory Dependence Analysis</td></tr>
+<tr><td><a href="#module-debuginfo">-module-debuginfo</a></td><td>Prints module debug info metadata</td></tr>
<tr><td><a href="#no-aa">-no-aa</a></td><td>No Alias Analysis (always returns 'may' alias)</td></tr>
<tr><td><a href="#no-profile">-no-profile</a></td><td>No Profile Information</td></tr>
+<tr><td><a href="#pointertracking">-pointertracking</a></td><td>Track pointer bounds</td></tr>
<tr><td><a href="#postdomfrontier">-postdomfrontier</a></td><td>Post-Dominance Frontier Construction</td></tr>
<tr><td><a href="#postdomtree">-postdomtree</a></td><td>Post-Dominator Tree Construction</td></tr>
<tr><td><a href="#print-alias-sets">-print-alias-sets</a></td><td>Alias Set Printer</td></tr>
<tr><td><a href="#print-callgraph">-print-callgraph</a></td><td>Print a call graph</td></tr>
<tr><td><a href="#print-callgraph-sccs">-print-callgraph-sccs</a></td><td>Print SCCs of the Call Graph</td></tr>
<tr><td><a href="#print-cfg-sccs">-print-cfg-sccs</a></td><td>Print SCCs of each function CFG</td></tr>
+<tr><td><a href="#print-dbginfo">-print-dbginfo</a></td><td>Print debug info in human readable form</td></tr>
+<tr><td><a href="#print-dom-info">-print-dom-info</a></td><td>Dominator Info Printer</td></tr>
<tr><td><a href="#print-externalfnconstants">-print-externalfnconstants</a></td><td>Print external fn callsites passed constants</td></tr>
<tr><td><a href="#print-function">-print-function</a></td><td>Print function to stderr</td></tr>
<tr><td><a href="#print-module">-print-module</a></td><td>Print module to stderr</td></tr>
<tr><td><a href="#print-used-types">-print-used-types</a></td><td>Find Used Types</td></tr>
+<tr><td><a href="#profile-estimator">-profile-estimator</a></td><td>Estimate profiling information</td></tr>
<tr><td><a href="#profile-loader">-profile-loader</a></td><td>Load profile information from llvmprof.out</td></tr>
+<tr><td><a href="#profile-verifier">-profile-verifier</a></td><td>Verify profiling information</td></tr>
<tr><td><a href="#scalar-evolution">-scalar-evolution</a></td><td>Scalar Evolution Analysis</td></tr>
+<tr><td><a href="#scev-aa">-scev-aa</a></td><td>ScalarEvolution-based Alias Analysis</td></tr>
<tr><td><a href="#targetdata">-targetdata</a></td><td>Target Data Layout</td></tr>
<tr><th colspan="2"><b>TRANSFORM PASSES</b></th></tr>
<tr><th>Option</th><th>Name</th></tr>
+<tr><td><a href="#abcd">-abcd</a></td><td>Remove redundant conditional branches</td></tr>
<tr><td><a href="#adce">-adce</a></td><td>Aggressive Dead Code Elimination</td></tr>
+<tr><td><a href="#always-inline">-always-inline</a></td><td>Inliner for always_inline functions</td></tr>
<tr><td><a href="#argpromotion">-argpromotion</a></td><td>Promote 'by reference' arguments to scalars</td></tr>
<tr><td><a href="#block-placement">-block-placement</a></td><td>Profile Guided Basic Block Placement</td></tr>
<tr><td><a href="#break-crit-edges">-break-crit-edges</a></td><td>Break critical edges in CFG</td></tr>
@@ -125,16 +142,14 @@
<tr><td><a href="#deadtypeelim">-deadtypeelim</a></td><td>Dead Type Elimination</td></tr>
<tr><td><a href="#die">-die</a></td><td>Dead Instruction Elimination</td></tr>
<tr><td><a href="#dse">-dse</a></td><td>Dead Store Elimination</td></tr>
+<tr><td><a href="#functionattrs">-functionattrs</a></td><td>Deduce function attributes</td></tr>
<tr><td><a href="#globaldce">-globaldce</a></td><td>Dead Global Elimination</td></tr>
<tr><td><a href="#globalopt">-globalopt</a></td><td>Global Variable Optimizer</td></tr>
<tr><td><a href="#gvn">-gvn</a></td><td>Global Value Numbering</td></tr>
<tr><td><a href="#indvars">-indvars</a></td><td>Canonicalize Induction Variables</td></tr>
<tr><td><a href="#inline">-inline</a></td><td>Function Integration/Inlining</td></tr>
-<tr><td><a href="#insert-block-profiling">-insert-block-profiling</a></td><td>Insert instrumentation for block profiling</td></tr>
<tr><td><a href="#insert-edge-profiling">-insert-edge-profiling</a></td><td>Insert instrumentation for edge profiling</td></tr>
-<tr><td><a href="#insert-function-profiling">-insert-function-profiling</a></td><td>Insert instrumentation for function profiling</td></tr>
-<tr><td><a href="#insert-null-profiling-rs">-insert-null-profiling-rs</a></td><td>Measure profiling framework overhead</td></tr>
-<tr><td><a href="#insert-rs-profiling-framework">-insert-rs-profiling-framework</a></td><td>Insert random sampling instrumentation framework</td></tr>
+<tr><td><a href="#insert-optimal-edge-profiling">-insert-optimal-edge-profiling</a></td><td>Insert optimal instrumentation for edge profiling</td></tr>
<tr><td><a href="#instcombine">-instcombine</a></td><td>Combine redundant instructions</td></tr>
<tr><td><a href="#internalize">-internalize</a></td><td>Internalize Global Symbols</td></tr>
<tr><td><a href="#ipconstprop">-ipconstprop</a></td><td>Interprocedural constant propagation</td></tr>
@@ -156,16 +171,27 @@
<tr><td><a href="#lowerswitch">-lowerswitch</a></td><td>Lower SwitchInst's to branches</td></tr>
<tr><td><a href="#mem2reg">-mem2reg</a></td><td>Promote Memory to Register</td></tr>
<tr><td><a href="#memcpyopt">-memcpyopt</a></td><td>Optimize use of memcpy and friends</td></tr>
+<tr><td><a href="#mergefunc">-mergefunc</a></td><td>Merge Functions</td></tr>
<tr><td><a href="#mergereturn">-mergereturn</a></td><td>Unify function exit nodes</td></tr>
+<tr><td><a href="#partial-inliner">-partial-inliner</a></td><td>Partial Inliner</td></tr>
+<tr><td><a href="#partialspecialization">-partialspecialization</a></td><td>Partial Specialization</td></tr>
<tr><td><a href="#prune-eh">-prune-eh</a></td><td>Remove unused exception handling info</td></tr>
<tr><td><a href="#reassociate">-reassociate</a></td><td>Reassociate expressions</td></tr>
<tr><td><a href="#reg2mem">-reg2mem</a></td><td>Demote all values to stack slots</td></tr>
<tr><td><a href="#scalarrepl">-scalarrepl</a></td><td>Scalar Replacement of Aggregates</td></tr>
<tr><td><a href="#sccp">-sccp</a></td><td>Sparse Conditional Constant Propagation</td></tr>
+<tr><td><a href="#sink">-sink</a></td><td>Code Sinking</td></tr>
<tr><td><a href="#simplify-libcalls">-simplify-libcalls</a></td><td>Simplify well-known library calls</td></tr>
+<tr><td><a href="#simplify-libcalls-halfpowr">-simplify-libcalls-halfpowr</a></td><td>Simplify half_powr library calls</td></tr>
<tr><td><a href="#simplifycfg">-simplifycfg</a></td><td>Simplify the CFG</td></tr>
+<tr><td><a href="#split-geps">-split-geps</a></td><td>Split complex GEPs into simple GEPs</td></tr>
+<tr><td><a href="#ssi">-ssi</a></td><td>Static Single Information Construction</td></tr>
+<tr><td><a href="#ssi-everything">-ssi-everything</a></td><td>Static Single Information Construction (everything, intended for debugging)</td></tr>
<tr><td><a href="#strip">-strip</a></td><td>Strip all symbols from a module</td></tr>
+<tr><td><a href="#strip-dead-debug-info">-strip-dead-debug-info</a></td><td>Strip debug info for unused symbols</td></tr>
<tr><td><a href="#strip-dead-prototypes">-strip-dead-prototypes</a></td><td>Remove unused function declarations</td></tr>
+<tr><td><a href="#strip-debug-declare">-strip-debug-declare</a></td><td>Strip all llvm.dbg.declare intrinsics</td></tr>
+<tr><td><a href="#strip-nondebug">-strip-nondebug</a></td><td>Strip all symbols, except dbg symbols, from a module</td></tr>
<tr><td><a href="#sretpromotion">-sretpromotion</a></td><td>Promote sret arguments</td></tr>
<tr><td><a href="#tailcallelim">-tailcallelim</a></td><td>Tail Call Elimination</td></tr>
<tr><td><a href="#tailduplicate">-tailduplicate</a></td><td>Tail Duplication</td></tr>
@@ -175,6 +201,7 @@
<tr><th>Option</th><th>Name</th></tr>
<tr><td><a href="#deadarghaX0r">-deadarghaX0r</a></td><td>Dead Argument Hacking (BUGPOINT USE ONLY; DO NOT USE)</td></tr>
<tr><td><a href="#extract-blocks">-extract-blocks</a></td><td>Extract Basic Blocks From Module (for bugpoint use)</td></tr>
+<tr><td><a href="#instnamer">-instnamer</a></td><td>Assign names to anonymous instructions</td></tr>
<tr><td><a href="#preverify">-preverify</a></td><td>Preliminary module verification</td></tr>
<tr><td><a href="#verify">-verify</a></td><td>Module Verifier</td></tr>
<tr><td><a href="#view-cfg">-view-cfg</a></td><td>View CFG of function</td></tr>
@@ -194,7 +221,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="aa-eval">Exhaustive Alias Analysis Precision Evaluator</a>
+ <a name="aa-eval">-aa-eval: Exhaustive Alias Analysis Precision Evaluator</a>
</div>
<div class="doc_text">
<p>This is a simple N^2 alias analysis accuracy evaluator.
@@ -208,7 +235,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="basicaa">Basic Alias Analysis (default AA impl)</a>
+ <a name="basicaa">-basicaa: Basic Alias Analysis (default AA impl)</a>
</div>
<div class="doc_text">
<p>
@@ -220,7 +247,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="basiccg">Basic CallGraph Construction</a>
+ <a name="basiccg">-basiccg: Basic CallGraph Construction</a>
</div>
<div class="doc_text">
<p>Yet to be written.</p>
@@ -228,7 +255,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="codegenprepare">Optimize for code generation</a>
+ <a name="codegenprepare">-codegenprepare: Optimize for code generation</a>
</div>
<div class="doc_text">
<p>
@@ -240,7 +267,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="count-aa">Count Alias Analysis Query Responses</a>
+ <a name="count-aa">-count-aa: Count Alias Analysis Query Responses</a>
</div>
<div class="doc_text">
<p>
@@ -251,7 +278,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="debug-aa">AA use debugger</a>
+ <a name="debug-aa">-debug-aa: AA use debugger</a>
</div>
<div class="doc_text">
<p>
@@ -268,7 +295,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="domfrontier">Dominance Frontier Construction</a>
+ <a name="domfrontier">-domfrontier: Dominance Frontier Construction</a>
</div>
<div class="doc_text">
<p>
@@ -279,7 +306,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="domtree">Dominator Tree Construction</a>
+ <a name="domtree">-domtree: Dominator Tree Construction</a>
</div>
<div class="doc_text">
<p>
@@ -290,7 +317,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="dot-callgraph">Print Call Graph to 'dot' file</a>
+ <a name="dot-callgraph">-dot-callgraph: Print Call Graph to 'dot' file</a>
</div>
<div class="doc_text">
<p>
@@ -302,7 +329,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="dot-cfg">Print CFG of function to 'dot' file</a>
+ <a name="dot-cfg">-dot-cfg: Print CFG of function to 'dot' file</a>
</div>
<div class="doc_text">
<p>
@@ -314,7 +341,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="dot-cfg-only">Print CFG of function to 'dot' file (with no function bodies)</a>
+ <a name="dot-cfg-only">-dot-cfg-only: Print CFG of function to 'dot' file (with no function bodies)</a>
</div>
<div class="doc_text">
<p>
@@ -327,7 +354,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="dot-dom">Print dominator tree of function to 'dot' file</a>
+ <a name="dot-dom">-dot-dom: Print dominator tree of function to 'dot' file</a>
</div>
<div class="doc_text">
<p>
@@ -339,7 +366,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="dot-dom-only">Print dominator tree of function to 'dot' file (with no
+ <a name="dot-dom-only">-dot-dom-only: Print dominator tree of function to 'dot' file (with no
function bodies)</a>
</div>
<div class="doc_text">
@@ -353,7 +380,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="dot-postdom">Print post dominator tree of function to 'dot' file</a>
+ <a name="dot-postdom">dot-postdom: Print post dominator tree of function to 'dot' file</a>
</div>
<div class="doc_text">
<p>
@@ -365,7 +392,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="dot-postdom-only">Print post dominator tree of function to 'dot' file
+ <a name="dot-postdom-only">dot-postdom-only: Print post dominator tree of function to 'dot' file
(with no function bodies)</a>
</div>
<div class="doc_text">
@@ -379,7 +406,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="globalsmodref-aa">Simple mod/ref analysis for globals</a>
+ <a name="globalsmodref-aa">-globalsmodref-aa: Simple mod/ref analysis for globals</a>
</div>
<div class="doc_text">
<p>
@@ -392,7 +419,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="instcount">Counts the various types of Instructions</a>
+ <a name="instcount">-instcount: Counts the various types of Instructions</a>
</div>
<div class="doc_text">
<p>
@@ -402,7 +429,30 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="intervals">Interval Partition Construction</a>
+ <a name="interprocedural-aa-eval">-interprocedural-aa-eval: Exhaustive Interprocedural Alias Analysis Precision Evaluator</a>
+</div>
+<div class="doc_text">
+ <p>This pass implements a simple N^2 alias analysis accuracy evaluator.
+ Basically, for each function in the program, it simply queries to see how the
+ alias analysis implementation answers alias queries between each pair of
+ pointers in the function.
+ </p>
+</div>
+
+<!-------------------------------------------------------------------------- -->
+<div class="doc_subsection">
+ <a name="interprocedural-basic-aa">-interprocedural-basic-aa: Interprocedural Basic Alias Analysis</a>
+</div>
+<div class="doc_text">
+ <p>This pass defines the default implementation of the Alias Analysis interface
+ that simply implements a few identities (two different globals cannot alias,
+ etc), but otherwise does no analysis.
+ </p>
+</div>
+
+<!-------------------------------------------------------------------------- -->
+<div class="doc_subsection">
+ <a name="intervals">-intervals: Interval Partition Construction</a>
</div>
<div class="doc_text">
<p>
@@ -418,7 +468,80 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="loops">Natural Loop Construction</a>
+ <a name="iv-users">-iv-users: Induction Variable Users</a>
+</div>
+<div class="doc_text">
+ <p>Bookkeeping for "interesting" users of expressions computed from
+ induction variables.</p>
+</div>
+
+<!-------------------------------------------------------------------------- -->
+<div class="doc_subsection">
+ <a name="lazy-value-info">-lazy-value-info: Lazy Value Information Analysis</a>
+</div>
+<div class="doc_text">
+ <p>Interface for lazy computation of value constraint information.</p>
+</div>
+
+<!-------------------------------------------------------------------------- -->
+<div class="doc_subsection">
+ <a name="lda">-lda: Loop Dependence Analysis</a>
+</div>
+<div class="doc_text">
+ <p>Loop dependence analysis framework, which is used to detect dependences in
+ memory accesses in loops.</p>
+</div>
+
+<!-------------------------------------------------------------------------- -->
+<div class="doc_subsection">
+ <a name="libcall-aa">-libcall-aa: LibCall Alias Analysis</a>
+</div>
+<div class="doc_text">
+ <p>LibCall Alias Analysis.</p>
+</div>
+
+<!-------------------------------------------------------------------------- -->
+<div class="doc_subsection">
+ <a name="lint">-lint: Check for common errors in LLVM IR</a>
+</div>
+<div class="doc_text">
+ <p>This pass statically checks for common and easily-identified constructs
+ which produce undefined or likely unintended behavior in LLVM IR.</p>
+
+ <p>It is not a guarantee of correctness, in two ways. First, it isn't
+ comprehensive. There are checks which could be done statically which are
+ not yet implemented. Some of these are indicated by TODO comments, but
+ those aren't comprehensive either. Second, many conditions cannot be
+ checked statically. This pass does no dynamic instrumentation, so it
+ can't check for all possible problems.</p>
+
+ <p>Another limitation is that it assumes all code will be executed. A store
+ through a null pointer in a basic block which is never reached is harmless,
+ but this pass will warn about it anyway.</p>
+
+ <p>Optimization passes may make conditions that this pass checks for more or
+ less obvious. If an optimization pass appears to be introducing a warning,
+ it may be that the optimization pass is merely exposing an existing
+ condition in the code.</p>
+
+ <p>This code may be run before instcombine. In many cases, instcombine checks
+ for the same kinds of things and turns instructions with undefined behavior
+ into unreachable (or equivalent). Because of this, this pass makes some
+ effort to look through bitcasts and so on.
+ </p>
+</div>
+
+<!-------------------------------------------------------------------------- -->
+<div class="doc_subsection">
+ <a name="live-values">-live-values: Values Liveness Analysis</a>
+</div>
+<div class="doc_text">
+ <p>LLVM IR Value liveness analysis pass.</p>
+</div>
+
+<!-------------------------------------------------------------------------- -->
+<div class="doc_subsection">
+ <a name="loops">-loops: Natural Loop Construction</a>
</div>
<div class="doc_text">
<p>
@@ -431,7 +554,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="memdep">Memory Dependence Analysis</a>
+ <a name="memdep">-memdep: Memory Dependence Analysis</a>
</div>
<div class="doc_text">
<p>
@@ -444,7 +567,20 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="no-aa">No Alias Analysis (always returns 'may' alias)</a>
+ <a name="module-debuginfo">-module-debuginfo: Prints module debug info metadata</a>
+</div>
+<div class="doc_text">
+ <p>This pass decodes the debug info metadata in a module and prints in a
+ (sufficiently-prepared-) human-readable form.
+
+ For example, run this pass from opt along with the -analyze option, and
+ it'll print to standard output.
+ </p>
+</div>
+
+<!-------------------------------------------------------------------------- -->
+<div class="doc_subsection">
+ <a name="no-aa">-no-aa: No Alias Analysis (always returns 'may' alias)</a>
</div>
<div class="doc_text">
<p>
@@ -456,7 +592,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="no-profile">No Profile Information</a>
+ <a name="no-profile">-no-profile: No Profile Information</a>
</div>
<div class="doc_text">
<p>
@@ -467,7 +603,16 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="postdomfrontier">Post-Dominance Frontier Construction</a>
+ <a name="pointertracking">-pointertracking: Track pointer bounds.</a>
+</div>
+<div class="doc_text">
+ <p>Tracking of pointer bounds.
+ </p>
+</div>
+
+<!-------------------------------------------------------------------------- -->
+<div class="doc_subsection">
+ <a name="postdomfrontier">-postdomfrontier: Post-Dominance Frontier Construction</a>
</div>
<div class="doc_text">
<p>
@@ -478,7 +623,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="postdomtree">Post-Dominator Tree Construction</a>
+ <a name="postdomtree">-postdomtree: Post-Dominator Tree Construction</a>
</div>
<div class="doc_text">
<p>
@@ -489,7 +634,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="print-alias-sets">Alias Set Printer</a>
+ <a name="print-alias-sets">-print-alias-sets: Alias Set Printer</a>
</div>
<div class="doc_text">
<p>Yet to be written.</p>
@@ -497,7 +642,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="print-callgraph">Print a call graph</a>
+ <a name="print-callgraph">-print-callgraph: Print a call graph</a>
</div>
<div class="doc_text">
<p>
@@ -508,7 +653,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="print-callgraph-sccs">Print SCCs of the Call Graph</a>
+ <a name="print-callgraph-sccs">-print-callgraph-sccs: Print SCCs of the Call Graph</a>
</div>
<div class="doc_text">
<p>
@@ -519,7 +664,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="print-cfg-sccs">Print SCCs of each function CFG</a>
+ <a name="print-cfg-sccs">-print-cfg-sccs: Print SCCs of each function CFG</a>
</div>
<div class="doc_text">
<p>
@@ -530,7 +675,31 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="print-externalfnconstants">Print external fn callsites passed constants</a>
+ <a name="print-dbginfo">-print-dbginfo: Print debug info in human readable form</a>
+</div>
+<div class="doc_text">
+ <p>Pass that prints instructions, and associated debug info:
+ <ul>
+
+ <li>source/line/col information</li>
+ <li>original variable name</li>
+ <li>original type name</li>
+ </ul>
+
+ </p>
+</div>
+
+<!-------------------------------------------------------------------------- -->
+<div class="doc_subsection">
+ <a name="print-dom-info">-print-dom-info: Dominator Info Printer</a>
+</div>
+<div class="doc_text">
+ <p>Dominator Info Printer.</p>
+</div>
+
+<!-------------------------------------------------------------------------- -->
+<div class="doc_subsection">
+ <a name="print-externalfnconstants">-print-externalfnconstants: Print external fn callsites passed constants</a>
</div>
<div class="doc_text">
<p>
@@ -543,7 +712,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="print-function">Print function to stderr</a>
+ <a name="print-function">-print-function: Print function to stderr</a>
</div>
<div class="doc_text">
<p>
@@ -555,7 +724,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="print-module">Print module to stderr</a>
+ <a name="print-module">-print-module: Print module to stderr</a>
</div>
<div class="doc_text">
<p>
@@ -565,7 +734,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="print-used-types">Find Used Types</a>
+ <a name="print-used-types">-print-used-types: Find Used Types</a>
</div>
<div class="doc_text">
<p>
@@ -576,7 +745,17 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="profile-loader">Load profile information from llvmprof.out</a>
+ <a name="profile-estimator">-profile-estimator: Estimate profiling information</a>
+</div>
+<div class="doc_text">
+ <p>Profiling information that estimates the profiling information
+ in a very crude and unimaginative way.
+ </p>
+</div>
+
+<!-------------------------------------------------------------------------- -->
+<div class="doc_subsection">
+ <a name="profile-loader">-profile-loader: Load profile information from llvmprof.out</a>
</div>
<div class="doc_text">
<p>
@@ -587,7 +766,15 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="scalar-evolution">Scalar Evolution Analysis</a>
+ <a name="profile-verifier">-profile-verifier: Verify profiling information</a>
+</div>
+<div class="doc_text">
+ <p>Pass that checks profiling information for plausibility.</p>
+</div>
+
+<!-------------------------------------------------------------------------- -->
+<div class="doc_subsection">
+ <a name="scalar-evolution">-scalar-evolution: Scalar Evolution Analysis</a>
</div>
<div class="doc_text">
<p>
@@ -606,7 +793,45 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="targetdata">Target Data Layout</a>
+ <a name="scev-aa">-scev-aa: </a>
+</div>
+<div class="doc_text">
+ <p>Simple alias analysis implemented in terms of ScalarEvolution queries.
+
+ This differs from traditional loop dependence analysis in that it tests
+ for dependencies within a single iteration of a loop, rather than
+ dependencies between different iterations.
+
+ ScalarEvolution has a more complete understanding of pointer arithmetic
+ than BasicAliasAnalysis' collection of ad-hoc analyses.
+ </p>
+</div>
+
+<!-------------------------------------------------------------------------- -->
+<div class="doc_subsection">
+ <a name="strip-dead-debug-info">-strip-dead-debug-info: Strip debug info for unused symbols</a>
+</div>
+<div class="doc_text">
+ <p>
+ performs code stripping. this transformation can delete:
+ </p>
+
+ <ol>
+ <li>names for virtual registers</li>
+ <li>symbols for internal globals and functions</li>
+ <li>debug information</li>
+ </ol>
+
+ <p>
+ note that this transformation makes code much less readable, so it should
+ only be used in situations where the <tt>strip</tt> utility would be used,
+ such as reducing code size or making it harder to reverse engineer code.
+ </p>
+</div>
+
+<!-------------------------------------------------------------------------- -->
+<div class="doc_subsection">
+ <a name="targetdata">-targetdata: Target Data Layout</a>
</div>
<div class="doc_text">
<p>Provides other passes access to information on how the size and alignment
@@ -621,7 +846,22 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="adce">Aggressive Dead Code Elimination</a>
+ <a name="abcd">-abcd: Remove redundant conditional branches</a>
+</div>
+<div class="doc_text">
+ <p>ABCD removes conditional branch instructions that can be proved redundant.
+ With the SSI representation, each variable has a constraint. By analyzing these
+ constraints we can prove that a branch is redundant. When a branch is proved
+ redundant it means that one direction will always be taken; thus, we can change
+ this branch into an unconditional jump.</p>
+ <p>It is advisable to run <a href="#simplifycfg">SimplifyCFG</a> and
+ <a href="#adce">Aggressive Dead Code Elimination</a> after ABCD
+ to clean up the code.</p>
+</div>
+
+<!-------------------------------------------------------------------------- -->
+<div class="doc_subsection">
+ <a name="adce">-adce: Aggressive Dead Code Elimination</a>
</div>
<div class="doc_text">
<p>ADCE aggressively tries to eliminate code. This pass is similar to
@@ -632,7 +872,16 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="argpromotion">Promote 'by reference' arguments to scalars</a>
+ <a name="always-inline">-always-inline: Inliner for always_inline functions</a>
+</div>
+<div class="doc_text">
+ <p>A custom inliner that handles only functions that are marked as
+ "always inline".</p>
+</div>
+
+<!-------------------------------------------------------------------------- -->
+<div class="doc_subsection">
+ <a name="argpromotion">-argpromotion: Promote 'by reference' arguments to scalars</a>
</div>
<div class="doc_text">
<p>
@@ -663,7 +912,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="block-placement">Profile Guided Basic Block Placement</a>
+ <a name="block-placement">-block-placement: Profile Guided Basic Block Placement</a>
</div>
<div class="doc_text">
<p>This pass is a very simple profile guided basic block placement algorithm.
@@ -675,7 +924,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="break-crit-edges">Break critical edges in CFG</a>
+ <a name="break-crit-edges">-break-crit-edges: Break critical edges in CFG</a>
</div>
<div class="doc_text">
<p>
@@ -688,7 +937,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="codegenprepare">Prepare a function for code generation</a>
+ <a name="codegenprepare">-codegenprepare: Prepare a function for code generation</a>
</div>
<div class="doc_text">
This pass munges the code in the input function to better prepare it for
@@ -698,7 +947,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="constmerge">Merge Duplicate Global Constants</a>
+ <a name="constmerge">-constmerge: Merge Duplicate Global Constants</a>
</div>
<div class="doc_text">
<p>
@@ -711,7 +960,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="constprop">Simple constant propagation</a>
+ <a name="constprop">-constprop: Simple constant propagation</a>
</div>
<div class="doc_text">
<p>This file implements constant propagation and merging. It looks for
@@ -727,7 +976,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="dce">Dead Code Elimination</a>
+ <a name="dce">-dce: Dead Code Elimination</a>
</div>
<div class="doc_text">
<p>
@@ -739,7 +988,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="deadargelim">Dead Argument Elimination</a>
+ <a name="deadargelim">-deadargelim: Dead Argument Elimination</a>
</div>
<div class="doc_text">
<p>
@@ -757,7 +1006,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="deadtypeelim">Dead Type Elimination</a>
+ <a name="deadtypeelim">-deadtypeelim: Dead Type Elimination</a>
</div>
<div class="doc_text">
<p>
@@ -769,7 +1018,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="die">Dead Instruction Elimination</a>
+ <a name="die">-die: Dead Instruction Elimination</a>
</div>
<div class="doc_text">
<p>
@@ -780,7 +1029,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="dse">Dead Store Elimination</a>
+ <a name="dse">-dse: Dead Store Elimination</a>
</div>
<div class="doc_text">
<p>
@@ -791,7 +1040,22 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="globaldce">Dead Global Elimination</a>
+ <a name="functionattrs">-functionattrs: Deduce function attributes</a>
+</div>
+<div class="doc_text">
+ <p>A simple interprocedural pass which walks the call-graph, looking for
+ functions which do not access or only read non-local memory, and marking them
+ readnone/readonly. In addition, it marks function arguments (of pointer type)
+ 'nocapture' if a call to the function does not create any copies of the pointer
+ value that outlive the call. This more or less means that the pointer is only
+ dereferenced, and not returned from the function or stored in a global.
+ This pass is implemented as a bottom-up traversal of the call-graph.
+ </p>
+</div>
+
+<!-------------------------------------------------------------------------- -->
+<div class="doc_subsection">
+ <a name="globaldce">-globaldce: Dead Global Elimination</a>
</div>
<div class="doc_text">
<p>
@@ -805,7 +1069,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="globalopt">Global Variable Optimizer</a>
+ <a name="globalopt">-globalopt: Global Variable Optimizer</a>
</div>
<div class="doc_text">
<p>
@@ -817,7 +1081,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="gvn">Global Value Numbering</a>
+ <a name="gvn">-gvn: Global Value Numbering</a>
</div>
<div class="doc_text">
<p>
@@ -826,10 +1090,9 @@
</p>
</div>
-
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="indvars">Canonicalize Induction Variables</a>
+ <a name="indvars">-indvars: Canonicalize Induction Variables</a>
</div>
<div class="doc_text">
<p>
@@ -880,7 +1143,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="inline">Function Integration/Inlining</a>
+ <a name="inline">-inline: Function Integration/Inlining</a>
</div>
<div class="doc_text">
<p>
@@ -890,26 +1153,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="insert-block-profiling">Insert instrumentation for block profiling</a>
-</div>
-<div class="doc_text">
- <p>
- This pass instruments the specified program with counters for basic block
- profiling, which counts the number of times each basic block executes. This
- is the most basic form of profiling, which can tell which blocks are hot, but
- cannot reliably detect hot paths through the CFG.
- </p>
-
- <p>
- Note that this implementation is very naïve. Control equivalent regions of
- the CFG should not require duplicate counters, but it does put duplicate
- counters in.
- </p>
-</div>
-
-<!-------------------------------------------------------------------------- -->
-<div class="doc_subsection">
- <a name="insert-edge-profiling">Insert instrumentation for edge profiling</a>
+ <a name="insert-edge-profiling">-insert-edge-profiling: Insert instrumentation for edge profiling</a>
</div>
<div class="doc_text">
<p>
@@ -927,51 +1171,18 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="insert-function-profiling">Insert instrumentation for function profiling</a>
+ <a name="insert-optimal-edge-profiling">-insert-optimal-edge-profiling: Insert optimal instrumentation for edge profiling</a>
</div>
<div class="doc_text">
- <p>
- This pass instruments the specified program with counters for function
- profiling, which counts the number of times each function is called.
- </p>
-</div>
-
-<!-------------------------------------------------------------------------- -->
-<div class="doc_subsection">
- <a name="insert-null-profiling-rs">Measure profiling framework overhead</a>
-</div>
-<div class="doc_text">
- <p>
- The basic profiler that does nothing. It is the default profiler and thus
- terminates <code>RSProfiler</code> chains. It is useful for measuring
- framework overhead.
- </p>
-</div>
-
-<!-------------------------------------------------------------------------- -->
-<div class="doc_subsection">
- <a name="insert-rs-profiling-framework">Insert random sampling instrumentation framework</a>
-</div>
-<div class="doc_text">
- <p>
- The second stage of the random-sampling instrumentation framework, duplicates
- all instructions in a function, ignoring the profiling code, then connects the
- two versions together at the entry and at backedges. At each connection point
- a choice is made as to whether to jump to the profiled code (take a sample) or
- execute the unprofiled code.
- </p>
-
- <p>
- After this pass, it is highly recommended to run<a href="#mem2reg">mem2reg</a>
- and <a href="#adce">adce</a>. <a href="#instcombine">instcombine</a>,
- <a href="#load-vn">load-vn</a>, <a href="#gdce">gdce</a>, and
- <a href="#dse">dse</a> also are good to run afterwards.
+ <p>This pass instruments the specified program with counters for edge profiling.
+ Edge profiling can give a reasonable approximation of the hot paths through a
+ program, and is used for a wide variety of program transformations.
</p>
</div>
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="instcombine">Combine redundant instructions</a>
+ <a name="instcombine">-instcombine: Combine redundant instructions</a>
</div>
<div class="doc_text">
<p>
@@ -1025,7 +1236,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="internalize">Internalize Global Symbols</a>
+ <a name="internalize">-internalize: Internalize Global Symbols</a>
</div>
<div class="doc_text">
<p>
@@ -1037,7 +1248,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="ipconstprop">Interprocedural constant propagation</a>
+ <a name="ipconstprop">-ipconstprop: Interprocedural constant propagation</a>
</div>
<div class="doc_text">
<p>
@@ -1051,7 +1262,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="ipsccp">Interprocedural Sparse Conditional Constant Propagation</a>
+ <a name="ipsccp">-ipsccp: Interprocedural Sparse Conditional Constant Propagation</a>
</div>
<div class="doc_text">
<p>
@@ -1062,7 +1273,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="jump-threading">Thread control through conditional blocks</a>
+ <a name="jump-threading">-jump-threading: Thread control through conditional blocks</a>
</div>
<div class="doc_text">
<p>
@@ -1091,7 +1302,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="lcssa">Loop-Closed SSA Form Pass</a>
+ <a name="lcssa">-lcssa: Loop-Closed SSA Form Pass</a>
</div>
<div class="doc_text">
<p>
@@ -1120,7 +1331,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="licm">Loop Invariant Code Motion</a>
+ <a name="licm">-licm: Loop Invariant Code Motion</a>
</div>
<div class="doc_text">
<p>
@@ -1156,7 +1367,7 @@
</div>
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="loop-deletion">Dead Loop Deletion Pass</a>
+ <a name="loop-deletion">-loop-deletion: Dead Loop Deletion Pass</a>
</div>
<div class="doc_text">
<p>
@@ -1169,7 +1380,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="loop-extract">Extract loops into new functions</a>
+ <a name="loop-extract">-loop-extract: Extract loops into new functions</a>
</div>
<div class="doc_text">
<p>
@@ -1182,7 +1393,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="loop-extract-single">Extract at most one loop into a new function</a>
+ <a name="loop-extract-single">-loop-extract-single: Extract at most one loop into a new function</a>
</div>
<div class="doc_text">
<p>
@@ -1194,7 +1405,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="loop-index-split">Index Split Loops</a>
+ <a name="loop-index-split">-loop-index-split: Index Split Loops</a>
</div>
<div class="doc_text">
<p>
@@ -1205,7 +1416,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="loop-reduce">Loop Strength Reduction</a>
+ <a name="loop-reduce">-loop-reduce: Loop Strength Reduction</a>
</div>
<div class="doc_text">
<p>
@@ -1219,7 +1430,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="loop-rotate">Rotate Loops</a>
+ <a name="loop-rotate">-loop-rotate: Rotate Loops</a>
</div>
<div class="doc_text">
<p>A simple loop rotation transformation.</p>
@@ -1227,7 +1438,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="loop-unroll">Unroll loops</a>
+ <a name="loop-unroll">-loop-unroll: Unroll loops</a>
</div>
<div class="doc_text">
<p>
@@ -1239,7 +1450,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="loop-unswitch">Unswitch loops</a>
+ <a name="loop-unswitch">-loop-unswitch: Unswitch loops</a>
</div>
<div class="doc_text">
<p>
@@ -1269,7 +1480,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="loopsimplify">Canonicalize natural loops</a>
+ <a name="loopsimplify">-loopsimplify: Canonicalize natural loops</a>
</div>
<div class="doc_text">
<p>
@@ -1310,7 +1521,23 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="lowerinvoke">Lower invoke and unwind, for unwindless code generators</a>
+ <a name="lowerallocs">-lowerallocs: Lower allocations from instructions to calls</a>
+</div>
+<div class="doc_text">
+ <p>
+ Turn <tt>malloc</tt> and <tt>free</tt> instructions into <tt>@malloc</tt> and
+ <tt>@free</tt> calls.
+ </p>
+
+ <p>
+ This is a target-dependent tranformation because it depends on the size of
+ data types and alignment constraints.
+ </p>
+</div>
+
+<!-------------------------------------------------------------------------- -->
+<div class="doc_subsection">
+ <a name="lowerinvoke">-lowerinvoke: Lower invoke and unwind, for unwindless code generators</a>
</div>
<div class="doc_text">
<p>
@@ -1351,7 +1578,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="lowersetjmp">Lower Set Jump</a>
+ <a name="lowersetjmp">-lowersetjmp: Lower Set Jump</a>
</div>
<div class="doc_text">
<p>
@@ -1380,7 +1607,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="lowerswitch">Lower SwitchInst's to branches</a>
+ <a name="lowerswitch">-lowerswitch: Lower SwitchInst's to branches</a>
</div>
<div class="doc_text">
<p>
@@ -1392,7 +1619,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="mem2reg">Promote Memory to Register</a>
+ <a name="mem2reg">-mem2reg: Promote Memory to Register</a>
</div>
<div class="doc_text">
<p>
@@ -1408,7 +1635,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="memcpyopt">Optimize use of memcpy and friend</a>
+ <a name="memcpyopt">-memcpyopt: Optimize use of memcpy and friend</a>
</div>
<div class="doc_text">
<p>
@@ -1419,7 +1646,28 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="mergereturn">Unify function exit nodes</a>
+ <a name="mergefunc">-mergefunc: Merge Functions</a>
+</div>
+<div class="doc_text">
+ <p>This pass looks for equivalent functions that are mergable and folds them.
+
+ A hash is computed from the function, based on its type and number of
+ basic blocks.
+
+ Once all hashes are computed, we perform an expensive equality comparison
+ on each function pair. This takes n^2/2 comparisons per bucket, so it's
+ important that the hash function be high quality. The equality comparison
+ iterates through each instruction in each basic block.
+
+ When a match is found the functions are folded. If both functions are
+ overridable, we move the functionality into a new internal function and
+ leave two overridable thunks to it.
+ </p>
+</div>
+
+<!-------------------------------------------------------------------------- -->
+<div class="doc_subsection">
+ <a name="mergereturn">-mergereturn: Unify function exit nodes</a>
</div>
<div class="doc_text">
<p>
@@ -1430,7 +1678,33 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="prune-eh">Remove unused exception handling info</a>
+ <a name="partial-inliner">-partial-inliner: Partial Inliner</a>
+</div>
+<div class="doc_text">
+ <p>This pass performs partial inlining, typically by inlining an if
+ statement that surrounds the body of the function.
+ </p>
+</div>
+
+<!-------------------------------------------------------------------------- -->
+<div class="doc_subsection">
+ <a name="partialspecialization">-partialspecialization: Partial Specialization</a>
+</div>
+<div class="doc_text">
+ <p>This pass finds function arguments that are often a common constant and
+ specializes a version of the called function for that constant.
+
+ This pass simply does the cloning for functions it specializes. It depends
+ on <a href="#ipsccp">IPSCCP</a> and <a href="#deadargelim">DAE</a> to clean up the results.
+
+ The initial heuristic favors constant arguments that are used in control
+ flow.
+ </p>
+</div>
+
+<!-------------------------------------------------------------------------- -->
+<div class="doc_subsection">
+ <a name="prune-eh">-prune-eh: Remove unused exception handling info</a>
</div>
<div class="doc_text">
<p>
@@ -1443,7 +1717,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="reassociate">Reassociate expressions</a>
+ <a name="reassociate">-reassociate: Reassociate expressions</a>
</div>
<div class="doc_text">
<p>
@@ -1466,7 +1740,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="reg2mem">Demote all values to stack slots</a>
+ <a name="reg2mem">-reg2mem: Demote all values to stack slots</a>
</div>
<div class="doc_text">
<p>
@@ -1483,7 +1757,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="scalarrepl">Scalar Replacement of Aggregates</a>
+ <a name="scalarrepl">-scalarrepl: Scalar Replacement of Aggregates</a>
</div>
<div class="doc_text">
<p>
@@ -1505,7 +1779,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="sccp">Sparse Conditional Constant Propagation</a>
+ <a name="sccp">-sccp: Sparse Conditional Constant Propagation</a>
</div>
<div class="doc_text">
<p>
@@ -1528,7 +1802,17 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="simplify-libcalls">Simplify well-known library calls</a>
+ <a name="sink">-sink: Code Sinking</a>
+</div>
+<div class="doc_text">
+ <p>This pass moves instructions into successor blocks, when possible, so that
+ they aren't executed on paths where their results aren't needed.
+ </p>
+</div>
+
+<!-------------------------------------------------------------------------- -->
+<div class="doc_subsection">
+ <a name="simplify-libcalls">-simplify-libcalls: Simplify well-known library calls</a>
</div>
<div class="doc_text">
<p>
@@ -1541,7 +1825,17 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="simplifycfg">Simplify the CFG</a>
+ <a name="simplify-libcalls-halfpowr">-simplify-libcalls-halfpowr: Simplify half_powr library calls</a>
+</div>
+<div class="doc_text">
+ <p>Simple pass that applies an experimental transformation on calls
+ to specific functions.
+ </p>
+</div>
+
+<!-------------------------------------------------------------------------- -->
+<div class="doc_subsection">
+ <a name="simplifycfg">-simplifycfg: Simplify the CFG</a>
</div>
<div class="doc_text">
<p>
@@ -1560,11 +1854,48 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="strip">Strip all symbols from a module</a>
+ <a name="split-geps">-split-geps: Split complex GEPs into simple GEPs</a>
+</div>
+<div class="doc_text">
+ <p>This function breaks GEPs with more than 2 non-zero operands into smaller
+ GEPs each with no more than 2 non-zero operands. This exposes redundancy
+ between GEPs with common initial operand sequences.
+ </p>
+</div>
+
+<!-------------------------------------------------------------------------- -->
+<div class="doc_subsection">
+ <a name="ssi">-ssi: Static Single Information Construction</a>
+</div>
+<div class="doc_text">
+ <p>This pass converts a list of variables to the Static Single Information
+ form.
+
+ We are building an on-demand representation, that is, we do not convert
+ every single variable in the target function to SSI form. Rather, we receive
+ a list of target variables that must be converted. We also do not
+ completely convert a target variable to the SSI format. Instead, we only
+ change the variable in the points where new information can be attached
+ to its live range, that is, at branch points.
+ </p>
+</div>
+
+<!-------------------------------------------------------------------------- -->
+<div class="doc_subsection">
+ <a name="ssi-everything">-ssi-everything: Static Single Information Construction (everything, intended for debugging)</a>
+</div>
+<div class="doc_text">
+ <p>A pass that runs <a href="#ssi">SSI</a> on every non-void variable, intended for debugging.
+ </p>
+</div>
+
+<!-------------------------------------------------------------------------- -->
+<div class="doc_subsection">
+ <a name="strip">-strip: Strip all symbols from a module</a>
</div>
<div class="doc_text">
<p>
- Performs code stripping. This transformation can delete:
+ performs code stripping. this transformation can delete:
</p>
<ol>
@@ -1574,7 +1905,7 @@
</ol>
<p>
- Note that this transformation makes code much less readable, so it should
+ note that this transformation makes code much less readable, so it should
only be used in situations where the <tt>strip</tt> utility would be used,
such as reducing code size or making it harder to reverse engineer code.
</p>
@@ -1582,7 +1913,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="strip-dead-prototypes">Remove unused function declarations</a>
+ <a name="strip-dead-prototypes">-strip-dead-prototypes: Remove unused function declarations</a>
</div>
<div class="doc_text">
<p>
@@ -1595,7 +1926,41 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="sretpromotion">Promote sret arguments</a>
+ <a name="strip-debug-declare">-strip-debug-declare: Strip all llvm.dbg.declare intrinsics</a>
+</div>
+<div class="doc_text">
+ <p>This pass implements code stripping. Specifically, it can delete:
+ <ul>
+ <li>names for virtual registers</li>
+ <li>symbols for internal globals and functions</li>
+ <li>debug information</li>
+ </ul>
+ Note that this transformation makes code much less readable, so it should
+ only be used in situations where the 'strip' utility would be used, such as
+ reducing code size or making it harder to reverse engineer code.
+ </p>
+</div>
+
+<!-------------------------------------------------------------------------- -->
+<div class="doc_subsection">
+ <a name="strip-nondebug">-strip-nondebug: Strip all symbols, except dbg symbols, from a module</a>
+</div>
+<div class="doc_text">
+ <p>This pass implements code stripping. Specifically, it can delete:
+ <ul>
+ <li>names for virtual registers</li>
+ <li>symbols for internal globals and functions</li>
+ <li>debug information</li>
+ </ul>
+ Note that this transformation makes code much less readable, so it should
+ only be used in situations where the 'strip' utility would be used, such as
+ reducing code size or making it harder to reverse engineer code.
+ </p>
+</div>
+
+<!-------------------------------------------------------------------------- -->
+<div class="doc_subsection">
+ <a name="sretpromotion">-sretpromotion: Promote sret arguments</a>
</div>
<div class="doc_text">
<p>
@@ -1618,7 +1983,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="tailcallelim">Tail Call Elimination</a>
+ <a name="tailcallelim">-tailcallelim: Tail Call Elimination</a>
</div>
<div class="doc_text">
<p>
@@ -1650,7 +2015,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="tailduplicate">Tail Duplication</a>
+ <a name="tailduplicate">-tailduplicate: Tail Duplication</a>
</div>
<div class="doc_text">
<p>
@@ -1670,7 +2035,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="deadarghaX0r">Dead Argument Hacking (BUGPOINT USE ONLY; DO NOT USE)</a>
+ <a name="deadarghaX0r">-deadarghaX0r: Dead Argument Hacking (BUGPOINT USE ONLY; DO NOT USE)</a>
</div>
<div class="doc_text">
<p>
@@ -1681,7 +2046,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="extract-blocks">Extract Basic Blocks From Module (for bugpoint use)</a>
+ <a name="extract-blocks">-extract-blocks: Extract Basic Blocks From Module (for bugpoint use)</a>
</div>
<div class="doc_text">
<p>
@@ -1691,7 +2056,19 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="preverify">Preliminary module verification</a>
+ <a name="instnamer">-instnamer: Assign names to anonymous instructions</a>
+</div>
+<div class="doc_text">
+ <p>This is a little utility pass that gives instructions names, this is mostly
+ useful when diffing the effect of an optimization because deleting an
+ unnamed instruction can change all other instruction numbering, making the
+ diff very noisy.
+ </p>
+</div>
+
+<!-------------------------------------------------------------------------- -->
+<div class="doc_subsection">
+ <a name="preverify">-preverify: Preliminary module verification</a>
</div>
<div class="doc_text">
<p>
@@ -1707,7 +2084,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="verify">Module Verifier</a>
+ <a name="verify">-verify: Module Verifier</a>
</div>
<div class="doc_text">
<p>
@@ -1758,7 +2135,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="view-cfg">View CFG of function</a>
+ <a name="view-cfg">-view-cfg: View CFG of function</a>
</div>
<div class="doc_text">
<p>
@@ -1768,7 +2145,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="view-cfg-only">View CFG of function (with no function bodies)</a>
+ <a name="view-cfg-only">-view-cfg-only: View CFG of function (with no function bodies)</a>
</div>
<div class="doc_text">
<p>
@@ -1779,7 +2156,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="view-dom">View dominator tree of function</a>
+ <a name="view-dom">-view-dom: View dominator tree of function</a>
</div>
<div class="doc_text">
<p>
@@ -1789,7 +2166,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="view-dom-only">View dominator tree of function (with no function
+ <a name="view-dom-only">-view-dom-only: View dominator tree of function (with no function
bodies)
</a>
</div>
@@ -1802,7 +2179,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="view-postdom">View post dominator tree of function</a>
+ <a name="view-postdom">-view-postdom: View post dominator tree of function</a>
</div>
<div class="doc_text">
<p>
@@ -1812,7 +2189,7 @@
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
- <a name="view-postdom-only">View post dominator tree of function (with no
+ <a name="view-postdom-only">-view-postdom-only: View post dominator tree of function (with no
function bodies)
</a>
</div>
Modified: llvm/branches/wendling/eh/include/llvm/ADT/Triple.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/ADT/Triple.h?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/ADT/Triple.h (original)
+++ llvm/branches/wendling/eh/include/llvm/ADT/Triple.h Thu Jul 8 03:14:09 2010
@@ -100,7 +100,8 @@
Psp,
Solaris,
Win32,
- Haiku
+ Haiku,
+ Minix
};
private:
Modified: llvm/branches/wendling/eh/include/llvm/Analysis/AliasAnalysis.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Analysis/AliasAnalysis.h?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Analysis/AliasAnalysis.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Analysis/AliasAnalysis.h Thu Jul 8 03:14:09 2010
@@ -323,10 +323,10 @@
/// identifiable object. This returns true for:
/// Global Variables and Functions (but not Global Aliases)
/// Allocas and Mallocs
-/// ByVal and NoAlias Arguments, if Interprocedural is false
-/// NoAlias returns, if Interprocedural is false
+/// ByVal and NoAlias Arguments
+/// NoAlias returns
///
-bool isIdentifiedObject(const Value *V, bool Interprocedural = false);
+bool isIdentifiedObject(const Value *V);
} // End llvm namespace
Modified: llvm/branches/wendling/eh/include/llvm/Analysis/Passes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Analysis/Passes.h?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Analysis/Passes.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Analysis/Passes.h Thu Jul 8 03:14:09 2010
@@ -53,13 +53,6 @@
//===--------------------------------------------------------------------===//
//
- // createInterproceduralAAEvalPass - This pass implements a simple
- // N^2 interprocedural alias analysis accuracy evaluator.
- //
- Pass *createInterproceduralAAEvalPass();
-
- //===--------------------------------------------------------------------===//
- //
// createNoAAPass - This pass implements a "I don't know" alias analysis.
//
ImmutablePass *createNoAAPass();
@@ -67,23 +60,12 @@
//===--------------------------------------------------------------------===//
//
// createBasicAliasAnalysisPass - This pass implements the default alias
- // analysis. This analysis respects the noalias attribute, so it is not
- // suitable for some interprocedural uses (see the discussion of noalias
- // in AliasAnalysis.html for details).
+ // analysis.
//
ImmutablePass *createBasicAliasAnalysisPass();
//===--------------------------------------------------------------------===//
//
- // createInterproceduralBasicAliasAnalysisPass - This pass is similar to
- // baiscaa, except that it properly supports queries to values which live
- // in different functions. Unlike the regular BasicAliasAnalysis, this
- // implementation does not respect the noalias attribute.
- //
- ImmutablePass *createInterproceduralBasicAliasAnalysisPass();
-
- //===--------------------------------------------------------------------===//
- //
/// createLibCallAliasAnalysisPass - Create an alias analysis pass that knows
/// about the semantics of a set of libcalls specified by LCI. The newly
/// constructed pass takes ownership of the pointer that is provided.
Modified: llvm/branches/wendling/eh/include/llvm/CodeGen/CallingConvLower.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/CodeGen/CallingConvLower.h?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/CodeGen/CallingConvLower.h (original)
+++ llvm/branches/wendling/eh/include/llvm/CodeGen/CallingConvLower.h Thu Jul 8 03:14:09 2010
@@ -17,14 +17,13 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/ValueTypes.h"
-#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/Target/TargetCallingConv.h"
#include "llvm/CallingConv.h"
namespace llvm {
class TargetRegisterInfo;
class TargetMachine;
class CCState;
- class SDNode;
/// CCValAssign - Represent assignment of one arg/retval to a location.
class CCValAssign {
@@ -35,6 +34,9 @@
ZExt, // The value is zero extended in the location.
AExt, // The value is extended with undefined upper bits.
BCvt, // The value is bit-converted in the location.
+ VExt, // The value is vector-widened in the location.
+ // FIXME: Not implemented yet. Code that uses AExt to mean
+ // vector-widen should be fixed to use VExt instead.
Indirect // The location contains pointer to the value.
// TODO: a subset of the value is in the location.
};
Modified: llvm/branches/wendling/eh/include/llvm/CodeGen/FastISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/CodeGen/FastISel.h?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/CodeGen/FastISel.h (original)
+++ llvm/branches/wendling/eh/include/llvm/CodeGen/FastISel.h Thu Jul 8 03:14:09 2010
@@ -24,6 +24,7 @@
class AllocaInst;
class ConstantFP;
+class FunctionLoweringInfo;
class Instruction;
class MachineBasicBlock;
class MachineConstantPool;
@@ -45,14 +46,7 @@
protected:
MachineBasicBlock *MBB;
DenseMap<const Value *, unsigned> LocalValueMap;
- DenseMap<const Value *, unsigned> &ValueMap;
- DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap;
- DenseMap<const AllocaInst *, int> &StaticAllocaMap;
- std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate;
-#ifndef NDEBUG
- SmallSet<const Instruction *, 8> &CatchInfoLost;
-#endif
- MachineFunction &MF;
+ FunctionLoweringInfo &FuncInfo;
MachineRegisterInfo &MRI;
MachineFrameInfo &MFI;
MachineConstantPool &MCP;
@@ -113,15 +107,7 @@
virtual ~FastISel();
protected:
- FastISel(MachineFunction &mf,
- DenseMap<const Value *, unsigned> &vm,
- DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
- DenseMap<const AllocaInst *, int> &am,
- std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate
-#ifndef NDEBUG
- , SmallSet<const Instruction *, 8> &cil
-#endif
- );
+ explicit FastISel(FunctionLoweringInfo &funcInfo);
/// TargetSelectInstruction - This method is called by target-independent
/// code when the normal FastISel process fails to select an instruction.
Modified: llvm/branches/wendling/eh/include/llvm/CodeGen/MachineBasicBlock.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/CodeGen/MachineBasicBlock.h?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/CodeGen/MachineBasicBlock.h (original)
+++ llvm/branches/wendling/eh/include/llvm/CodeGen/MachineBasicBlock.h Thu Jul 8 03:14:09 2010
@@ -259,6 +259,11 @@
/// machine basic block (i.e., copies all the successors fromMBB and
/// remove all the successors from fromMBB).
void transferSuccessors(MachineBasicBlock *fromMBB);
+
+ /// transferSuccessorsAndUpdatePHIs - Transfers all the successors, as
+ /// in transferSuccessors, and update PHI operands in the successor blocks
+ /// which refer to fromMBB to refer to this.
+ void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB);
/// isSuccessor - Return true if the specified MBB is a successor of this
/// block.
@@ -277,6 +282,13 @@
/// branch to do so (e.g., a table jump). True is a conservative answer.
bool canFallThrough();
+ /// Returns a pointer to the first instructon in this block that is not a
+ /// PHINode instruction. When adding instruction to the beginning of the
+ /// basic block, they should be added before the returned value, not before
+ /// the first instruction, which might be PHI.
+ /// Returns end() is there's no non-PHI instruction.
+ iterator getFirstNonPHI();
+
/// getFirstTerminator - returns an iterator to the first terminator
/// instruction of this basic block. If a terminator does not exist,
/// it returns end()
Modified: llvm/branches/wendling/eh/include/llvm/CodeGen/RegisterCoalescer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/CodeGen/RegisterCoalescer.h?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/CodeGen/RegisterCoalescer.h (original)
+++ llvm/branches/wendling/eh/include/llvm/CodeGen/RegisterCoalescer.h Thu Jul 8 03:14:09 2010
@@ -165,9 +165,6 @@
/// virtual register.
unsigned subIdx_;
- /// origDstReg_ - dstReg_ without subreg adjustments.
- unsigned origDstReg_;
-
/// partial_ - True when the original copy was a partial subregister copy.
bool partial_;
@@ -192,8 +189,7 @@
public:
CoalescerPair(const TargetInstrInfo &tii, const TargetRegisterInfo &tri)
: tii_(tii), tri_(tri), dstReg_(0), srcReg_(0), subIdx_(0),
- origDstReg_(0), partial_(false), crossClass_(false), flipped_(false),
- newRC_(0) {}
+ partial_(false), crossClass_(false), flipped_(false), newRC_(0) {}
/// setRegisters - set registers to match the copy instruction MI. Return
/// false if MI is not a coalescable copy instruction.
@@ -232,10 +228,6 @@
/// coalesced into, or 0.
unsigned getSubIdx() const { return subIdx_; }
- /// getOrigDstReg - Return DstReg as it appeared in the original copy
- /// instruction before any subreg adjustments.
- unsigned getOrigDstReg() const { return isPhys() ? origDstReg_ : dstReg_; }
-
/// getNewRC - Return the register class of the coalesced register.
const TargetRegisterClass *getNewRC() const { return newRC_; }
};
Modified: llvm/branches/wendling/eh/include/llvm/CodeGen/RegisterScavenging.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/CodeGen/RegisterScavenging.h?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/CodeGen/RegisterScavenging.h (original)
+++ llvm/branches/wendling/eh/include/llvm/CodeGen/RegisterScavenging.h Thu Jul 8 03:14:09 2010
@@ -98,10 +98,24 @@
/// getRegsUsed - return all registers currently in use in used.
void getRegsUsed(BitVector &used, bool includeReserved);
+ /// getRegsAvailable - Return all available registers in the register class
+ /// in Mask.
+ void getRegsAvailable(const TargetRegisterClass *RC, BitVector &Mask);
+
/// FindUnusedReg - Find a unused register of the specified register class.
/// Return 0 if none is found.
unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const;
+ /// findSurvivorReg - Return the candidate register that is unused for the
+ /// longest after StartMI. UseMI is set to the instruction where the search
+ /// stopped.
+ ///
+ /// No more than InstrLimit instructions are inspected.
+ unsigned findSurvivorReg(MachineBasicBlock::iterator StartMI,
+ BitVector &Candidates,
+ unsigned InstrLimit,
+ MachineBasicBlock::iterator &UseMI);
+
/// setScavengingFrameIndex / getScavengingFrameIndex - accessor and setter of
/// ScavengingFrameIndex.
void setScavengingFrameIndex(int FI) { ScavengingFrameIndex = FI; }
@@ -147,11 +161,6 @@
/// Add Reg and its aliases to BV.
void addRegWithAliases(BitVector &BV, unsigned Reg);
- unsigned findSurvivorReg(MachineBasicBlock::iterator MI,
- BitVector &Candidates,
- unsigned InstrLimit,
- MachineBasicBlock::iterator &UseMI);
-
};
} // End llvm namespace
Modified: llvm/branches/wendling/eh/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/CodeGen/SelectionDAG.h?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/branches/wendling/eh/include/llvm/CodeGen/SelectionDAG.h Thu Jul 8 03:14:09 2010
@@ -348,13 +348,13 @@
SDValue getTargetConstantFP(const ConstantFP &Val, EVT VT) {
return getConstantFP(Val, VT, true);
}
- SDValue getGlobalAddress(const GlobalValue *GV, EVT VT,
+ SDValue getGlobalAddress(const GlobalValue *GV, DebugLoc DL, EVT VT,
int64_t offset = 0, bool isTargetGA = false,
unsigned char TargetFlags = 0);
- SDValue getTargetGlobalAddress(const GlobalValue *GV, EVT VT,
+ SDValue getTargetGlobalAddress(const GlobalValue *GV, DebugLoc DL, EVT VT,
int64_t offset = 0,
unsigned char TargetFlags = 0) {
- return getGlobalAddress(GV, VT, offset, true, TargetFlags);
+ return getGlobalAddress(GV, DL, VT, offset, true, TargetFlags);
}
SDValue getFrameIndex(int FI, EVT VT, bool isTarget = false);
SDValue getTargetFrameIndex(int FI, EVT VT) {
@@ -632,18 +632,20 @@
SDValue getLoad(EVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr,
const Value *SV, int SVOffset, bool isVolatile,
bool isNonTemporal, unsigned Alignment);
- SDValue getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, EVT VT,
+ SDValue getExtLoad(ISD::LoadExtType ExtType, EVT VT, DebugLoc dl,
SDValue Chain, SDValue Ptr, const Value *SV,
int SVOffset, EVT MemVT, bool isVolatile,
bool isNonTemporal, unsigned Alignment);
SDValue getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base,
- SDValue Offset, ISD::MemIndexedMode AM);
- SDValue getLoad(ISD::MemIndexedMode AM, DebugLoc dl, ISD::LoadExtType ExtType,
- EVT VT, SDValue Chain, SDValue Ptr, SDValue Offset,
+ SDValue Offset, ISD::MemIndexedMode AM);
+ SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
+ EVT VT, DebugLoc dl,
+ SDValue Chain, SDValue Ptr, SDValue Offset,
const Value *SV, int SVOffset, EVT MemVT,
bool isVolatile, bool isNonTemporal, unsigned Alignment);
- SDValue getLoad(ISD::MemIndexedMode AM, DebugLoc dl, ISD::LoadExtType ExtType,
- EVT VT, SDValue Chain, SDValue Ptr, SDValue Offset,
+ SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
+ EVT VT, DebugLoc dl,
+ SDValue Chain, SDValue Ptr, SDValue Offset,
EVT MemVT, MachineMemOperand *MMO);
/// getStore - Helper function to build ISD::STORE nodes.
Modified: llvm/branches/wendling/eh/include/llvm/CodeGen/SelectionDAGISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/CodeGen/SelectionDAGISel.h?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/CodeGen/SelectionDAGISel.h (original)
+++ llvm/branches/wendling/eh/include/llvm/CodeGen/SelectionDAGISel.h Thu Jul 8 03:14:09 2010
@@ -285,7 +285,6 @@
void FinishBasicBlock(MachineBasicBlock *BB);
MachineBasicBlock *SelectBasicBlock(MachineBasicBlock *BB,
- const BasicBlock *LLVMBB,
BasicBlock::const_iterator Begin,
BasicBlock::const_iterator End,
bool &HadTailCall);
Modified: llvm/branches/wendling/eh/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/CodeGen/SelectionDAGNodes.h?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/branches/wendling/eh/include/llvm/CodeGen/SelectionDAGNodes.h Thu Jul 8 03:14:09 2010
@@ -1154,7 +1154,7 @@
int64_t Offset;
unsigned char TargetFlags;
friend class SelectionDAG;
- GlobalAddressSDNode(unsigned Opc, const GlobalValue *GA, EVT VT,
+ GlobalAddressSDNode(unsigned Opc, DebugLoc DL, const GlobalValue *GA, EVT VT,
int64_t o, unsigned char TargetFlags);
public:
@@ -1464,127 +1464,6 @@
}
};
-namespace ISD {
- struct ArgFlagsTy {
- private:
- static const uint64_t NoFlagSet = 0ULL;
- static const uint64_t ZExt = 1ULL<<0; ///< Zero extended
- static const uint64_t ZExtOffs = 0;
- static const uint64_t SExt = 1ULL<<1; ///< Sign extended
- static const uint64_t SExtOffs = 1;
- static const uint64_t InReg = 1ULL<<2; ///< Passed in register
- static const uint64_t InRegOffs = 2;
- static const uint64_t SRet = 1ULL<<3; ///< Hidden struct-ret ptr
- static const uint64_t SRetOffs = 3;
- static const uint64_t ByVal = 1ULL<<4; ///< Struct passed by value
- static const uint64_t ByValOffs = 4;
- static const uint64_t Nest = 1ULL<<5; ///< Nested fn static chain
- static const uint64_t NestOffs = 5;
- static const uint64_t ByValAlign = 0xFULL << 6; //< Struct alignment
- static const uint64_t ByValAlignOffs = 6;
- static const uint64_t Split = 1ULL << 10;
- static const uint64_t SplitOffs = 10;
- static const uint64_t OrigAlign = 0x1FULL<<27;
- static const uint64_t OrigAlignOffs = 27;
- static const uint64_t ByValSize = 0xffffffffULL << 32; //< Struct size
- static const uint64_t ByValSizeOffs = 32;
-
- static const uint64_t One = 1ULL; //< 1 of this type, for shifts
-
- uint64_t Flags;
- public:
- ArgFlagsTy() : Flags(0) { }
-
- bool isZExt() const { return Flags & ZExt; }
- void setZExt() { Flags |= One << ZExtOffs; }
-
- bool isSExt() const { return Flags & SExt; }
- void setSExt() { Flags |= One << SExtOffs; }
-
- bool isInReg() const { return Flags & InReg; }
- void setInReg() { Flags |= One << InRegOffs; }
-
- bool isSRet() const { return Flags & SRet; }
- void setSRet() { Flags |= One << SRetOffs; }
-
- bool isByVal() const { return Flags & ByVal; }
- void setByVal() { Flags |= One << ByValOffs; }
-
- bool isNest() const { return Flags & Nest; }
- void setNest() { Flags |= One << NestOffs; }
-
- unsigned getByValAlign() const {
- return (unsigned)
- ((One << ((Flags & ByValAlign) >> ByValAlignOffs)) / 2);
- }
- void setByValAlign(unsigned A) {
- Flags = (Flags & ~ByValAlign) |
- (uint64_t(Log2_32(A) + 1) << ByValAlignOffs);
- }
-
- bool isSplit() const { return Flags & Split; }
- void setSplit() { Flags |= One << SplitOffs; }
-
- unsigned getOrigAlign() const {
- return (unsigned)
- ((One << ((Flags & OrigAlign) >> OrigAlignOffs)) / 2);
- }
- void setOrigAlign(unsigned A) {
- Flags = (Flags & ~OrigAlign) |
- (uint64_t(Log2_32(A) + 1) << OrigAlignOffs);
- }
-
- unsigned getByValSize() const {
- return (unsigned)((Flags & ByValSize) >> ByValSizeOffs);
- }
- void setByValSize(unsigned S) {
- Flags = (Flags & ~ByValSize) | (uint64_t(S) << ByValSizeOffs);
- }
-
- /// getArgFlagsString - Returns the flags as a string, eg: "zext align:4".
- std::string getArgFlagsString();
-
- /// getRawBits - Represent the flags as a bunch of bits.
- uint64_t getRawBits() const { return Flags; }
- };
-
- /// InputArg - This struct carries flags and type information about a
- /// single incoming (formal) argument or incoming (from the perspective
- /// of the caller) return value virtual register.
- ///
- struct InputArg {
- ArgFlagsTy Flags;
- EVT VT;
- bool Used;
-
- InputArg() : VT(MVT::Other), Used(false) {}
- InputArg(ISD::ArgFlagsTy flags, EVT vt, bool used)
- : Flags(flags), VT(vt), Used(used) {
- assert(VT.isSimple() &&
- "InputArg value type must be Simple!");
- }
- };
-
- /// OutputArg - This struct carries flags and a value for a
- /// single outgoing (actual) argument or outgoing (from the perspective
- /// of the caller) return value virtual register.
- ///
- struct OutputArg {
- ArgFlagsTy Flags;
- SDValue Val;
-
- /// IsFixed - Is this a "fixed" value, ie not passed through a vararg "...".
- bool IsFixed;
-
- OutputArg() : IsFixed(false) {}
- OutputArg(ISD::ArgFlagsTy flags, SDValue val, bool isfixed)
- : Flags(flags), Val(val), IsFixed(isfixed) {
- assert(Val.getValueType().isSimple() &&
- "OutputArg value type must be Simple!");
- }
- };
-}
-
/// VTSDNode - This class is used to represent EVT's, which are used
/// to parameterize some operations.
class VTSDNode : public SDNode {
Modified: llvm/branches/wendling/eh/include/llvm/Instructions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Instructions.h?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Instructions.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Instructions.h Thu Jul 8 03:14:09 2010
@@ -886,14 +886,14 @@
InputIterator ArgBegin, InputIterator ArgEnd,
const Twine &NameStr = "",
Instruction *InsertBefore = 0) {
- return new((unsigned)(ArgEnd - ArgBegin + 1))
+ return new(unsigned(ArgEnd - ArgBegin + 1))
CallInst(Func, ArgBegin, ArgEnd, NameStr, InsertBefore);
}
template<typename InputIterator>
static CallInst *Create(Value *Func,
InputIterator ArgBegin, InputIterator ArgEnd,
const Twine &NameStr, BasicBlock *InsertAtEnd) {
- return new((unsigned)(ArgEnd - ArgBegin + 1))
+ return new(unsigned(ArgEnd - ArgBegin + 1))
CallInst(Func, ArgBegin, ArgEnd, NameStr, InsertAtEnd);
}
static CallInst *Create(Value *F, Value *Actual,
@@ -940,8 +940,25 @@
unsigned(isTC));
}
+ /// @deprecated these "define hacks" will go away soon
+ /// @brief coerce out-of-tree code to abandon the low-level interfaces
+ /// @detail see below comments and update your code to high-level interfaces
+ /// in LLVM v2.8-only code
+ /// - getOperand(N+1) ---> getArgOperand(N)
+ /// - setOperand(N+1, V) ---> setArgOperand(N, V)
+ /// - getNumOperands() ---> getNumArgOperands()+1 // note the "+1"!
+ ///
+ /// in backward compatible code please consult llvm/Support/CallSite.h,
+ /// you should create a callsite using the CallInst pointer and call its
+ /// methods
+ ///
+# define public private
+# define protected private
/// Provide fast operand accessors
DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
+# undef public
+# undef protected
+public:
enum { ArgOffset = 1 }; ///< temporary, do not use for new code!
unsigned getNumArgOperands() const { return getNumOperands() - 1; }
@@ -951,11 +968,12 @@
/// Provide compile-time errors for accessing operand 0
/// @deprecated these will go away soon
/// @detail see below comments and update your code to high-level interfaces
- /// - getOperand(0) ---> getCalledValue()
+ /// - getOperand(0) ---> getCalledValue(), or possibly getCalledFunction
/// - setOperand(0, V) ---> setCalledFunction(V)
///
private:
- void getOperand(void*); // NO IMPL ---> use getCalledValue (or possibly getCalledFunction) instead
+ void getOperand(void*); // NO IMPL ---> use getCalledValue (or possibly
+ // getCalledFunction) instead
void setOperand(void*, Value*); // NO IMPL ---> use setCalledFunction instead
public:
@@ -1098,11 +1116,15 @@
->getElementType())->getReturnType(),
Instruction::Call,
OperandTraits<CallInst>::op_end(this) - (ArgEnd - ArgBegin + 1),
- (unsigned)(ArgEnd - ArgBegin + 1), InsertBefore) {
+ unsigned(ArgEnd - ArgBegin + 1), InsertBefore) {
init(Func, ArgBegin, ArgEnd, NameStr,
typename std::iterator_traits<InputIterator>::iterator_category());
}
+
+// Note: if you get compile errors about private methods then
+// please update your code to use the high-level operand
+// interfaces. See line 943 above.
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(CallInst, Value)
//===----------------------------------------------------------------------===//
Modified: llvm/branches/wendling/eh/include/llvm/Support/CallSite.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Support/CallSite.h?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Support/CallSite.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Support/CallSite.h Thu Jul 8 03:14:09 2010
@@ -256,14 +256,14 @@
/// Returns the operand number of the first argument
unsigned getArgumentOffset() const {
if (isCall())
- return 1; // Skip Function (ATM)
+ return CallInst::ArgOffset; // Skip Function (ATM)
else
return 0; // Args are at the front
}
unsigned getArgumentEndOffset() const {
if (isCall())
- return 0; // Unchanged (ATM)
+ return CallInst::ArgOffset ? 0 : 1; // Unchanged (ATM)
else
// An invoke.
return 4; // Skip PersFn, BB, BB, Function
Modified: llvm/branches/wendling/eh/include/llvm/Support/ELF.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Support/ELF.h?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Support/ELF.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Support/ELF.h Thu Jul 8 03:14:09 2010
@@ -135,9 +135,64 @@
ELFDATA2MSB = 2 // Big-endian object file
};
-// OS ABI identification -- unused.
+// OS ABI identification.
enum {
- ELFOSABI_NONE = 0
+ ELFOSABI_NONE = 0, // UNIX System V ABI
+ ELFOSABI_HPUX = 1, // HP-UX operating system
+ ELFOSABI_NETBSD = 2, // NetBSD
+ ELFOSABI_LINUX = 3, // GNU/Linux
+ ELFOSABI_HURD = 4, // GNU/Hurd
+ ELFOSABI_SOLARIS = 6, // Solaris
+ ELFOSABI_AIX = 7, // AIX
+ ELFOSABI_IRIX = 8, // IRIX
+ ELFOSABI_FREEBSD = 9, // FreeBSD
+ ELFOSABI_TRU64 = 10, // TRU64 UNIX
+ ELFOSABI_MODESTO = 11, // Novell Modesto
+ ELFOSABI_OPENBSD = 12, // OpenBSD
+ ELFOSABI_OPENVMS = 13, // OpenVMS
+ ELFOSABI_NSK = 14, // Hewlett-Packard Non-Stop Kernel
+ ELFOSABI_AROS = 15, // AROS
+ ELFOSABI_FENIXOS = 16, // FenixOS
+ ELFOSABI_C6000_ELFABI = 64, // Bare-metal TMS320C6000
+ ELFOSABI_C6000_LINUX = 65, // Linux TMS320C6000
+ ELFOSABI_ARM = 97, // ARM
+ ELFOSABI_STANDALONE = 255 // Standalone (embedded) application
+};
+
+// X86_64 relocations.
+enum {
+ R_X86_64_NONE = 0,
+ R_X86_64_64 = 1,
+ R_X86_64_PC32 = 2,
+ R_X86_64_GOT32 = 3,
+ R_X86_64_PLT32 = 4,
+ R_X86_64_COPY = 5,
+ R_X86_64_GLOB_DAT = 6,
+ R_X86_64_JUMP_SLOT = 7,
+ R_X86_64_RELATIVE = 8,
+ R_X86_64_GOTPCREL = 9,
+ R_X86_64_32 = 10,
+ R_X86_64_32S = 11,
+ R_X86_64_16 = 12,
+ R_X86_64_PC16 = 13,
+ R_X86_64_8 = 14,
+ R_X86_64_PC8 = 15,
+ R_X86_64_DTPMOD64 = 16,
+ R_X86_64_DTPOFF64 = 17,
+ R_X86_64_TPOFF64 = 18,
+ R_X86_64_TLSGD = 19,
+ R_X86_64_TLSLD = 20,
+ R_X86_64_DTPOFF32 = 21,
+ R_X86_64_GOTTPOFF = 22,
+ R_X86_64_TPOFF32 = 23,
+ R_X86_64_PC64 = 24,
+ R_X86_64_GOTOFF64 = 25,
+ R_X86_64_GOTPC32 = 26,
+ R_X86_64_SIZE32 = 32,
+ R_X86_64_SIZE64 = 33,
+ R_X86_64_GOTPC32_TLSDESC = 34,
+ R_X86_64_TLSDESC_CALL = 35,
+ R_X86_64_TLSDESC = 36
};
// Section header.
@@ -280,6 +335,43 @@
};
};
+// Relocation entry, without explicit addend.
+struct Elf64_Rel {
+ Elf64_Addr r_offset; // Location (file byte offset, or program virtual addr).
+ Elf64_Xword r_info; // Symbol table index and type of relocation to apply.
+
+ // These accessors and mutators correspond to the ELF64_R_SYM, ELF64_R_TYPE,
+ // and ELF64_R_INFO macros defined in the ELF specification:
+ Elf64_Xword getSymbol () const { return (r_info >> 32); }
+ unsigned char getType () const {
+ return (unsigned char) (r_info & 0xffffffffL);
+ }
+ void setSymbol (Elf32_Word s) { setSymbolAndType (s, getType ()); }
+ void setType (unsigned char t) { setSymbolAndType (getSymbol(), t); }
+ void setSymbolAndType (Elf64_Xword s, unsigned char t) {
+ r_info = (s << 32) + (t&0xffffffffL);
+ };
+};
+
+// Relocation entry with explicit addend.
+struct Elf64_Rela {
+ Elf64_Addr r_offset; // Location (file byte offset, or program virtual addr).
+ Elf64_Xword r_info; // Symbol table index and type of relocation to apply.
+ Elf64_Sxword r_addend; // Compute value for relocatable field by adding this.
+
+ // These accessors and mutators correspond to the ELF64_R_SYM, ELF64_R_TYPE,
+ // and ELF64_R_INFO macros defined in the ELF specification:
+ Elf64_Xword getSymbol () const { return (r_info >> 32); }
+ unsigned char getType () const {
+ return (unsigned char) (r_info & 0xffffffffL);
+ }
+ void setSymbol (Elf64_Xword s) { setSymbolAndType (s, getType ()); }
+ void setType (unsigned char t) { setSymbolAndType (getSymbol(), t); }
+ void setSymbolAndType (Elf64_Xword s, unsigned char t) {
+ r_info = (s << 32) + (t&0xffffffffL);
+ };
+};
+
// Program header.
struct Elf32_Phdr {
Elf32_Word p_type; // Type of segment
Modified: llvm/branches/wendling/eh/include/llvm/Support/IRBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Support/IRBuilder.h?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Support/IRBuilder.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Support/IRBuilder.h Thu Jul 8 03:14:09 2010
@@ -97,6 +97,48 @@
I->setDebugLoc(CurDbgLocation);
}
+ /// InsertPoint - A saved insertion point.
+ class InsertPoint {
+ BasicBlock *Block;
+ BasicBlock::iterator Point;
+
+ public:
+ /// Creates a new insertion point which doesn't point to anything.
+ InsertPoint() : Block(0) {}
+
+ /// Creates a new insertion point at the given location.
+ InsertPoint(BasicBlock *InsertBlock, BasicBlock::iterator InsertPoint)
+ : Block(InsertBlock), Point(InsertPoint) {}
+
+ /// isSet - Returns true if this insert point is set.
+ bool isSet() const { return (Block != 0); }
+
+ llvm::BasicBlock *getBlock() const { return Block; }
+ llvm::BasicBlock::iterator getPoint() const { return Point; }
+ };
+
+ /// saveIP - Returns the current insert point.
+ InsertPoint saveIP() const {
+ return InsertPoint(GetInsertBlock(), GetInsertPoint());
+ }
+
+ /// saveAndClearIP - Returns the current insert point, clearing it
+ /// in the process.
+ InsertPoint saveAndClearIP() {
+ InsertPoint IP(GetInsertBlock(), GetInsertPoint());
+ ClearInsertionPoint();
+ return IP;
+ }
+
+ /// restoreIP - Sets the current insert point to a previously-saved
+ /// location.
+ void restoreIP(InsertPoint IP) {
+ if (IP.isSet())
+ SetInsertPoint(IP.getBlock(), IP.getPoint());
+ else
+ ClearInsertionPoint();
+ }
+
//===--------------------------------------------------------------------===//
// Miscellaneous creation methods.
//===--------------------------------------------------------------------===//
@@ -106,33 +148,88 @@
/// specified. If Name is specified, it is the name of the global variable
/// created.
Value *CreateGlobalString(const char *Str = "", const Twine &Name = "");
+
+ /// getInt1 - Get a constant value representing either true or false.
+ ConstantInt *getInt1(bool V) {
+ return ConstantInt::get(getInt1Ty(), V);
+ }
+
+ /// getTrue - Get the constant value for i1 true.
+ ConstantInt *getTrue() {
+ return ConstantInt::getTrue(Context);
+ }
+
+ /// getFalse - Get the constant value for i1 false.
+ ConstantInt *getFalse() {
+ return ConstantInt::getFalse(Context);
+ }
+
+ /// getInt8 - Get a constant 8-bit value.
+ ConstantInt *getInt8(int8_t C) {
+ return ConstantInt::getSigned(getInt8Ty(), C);
+ }
+
+ /// getInt8 - Get a constant 8-bit value.
+ ConstantInt *getInt8(uint8_t C) {
+ return ConstantInt::get(getInt8Ty(), C);
+ }
+
+ /// getInt16 - Get a constant 16-bit value.
+ ConstantInt *getInt16(int16_t C) {
+ return ConstantInt::getSigned(getInt16Ty(), C);
+ }
+
+ /// getInt16 - Get a constant 16-bit value.
+ ConstantInt *getInt16(uint16_t C) {
+ return ConstantInt::get(getInt16Ty(), C);
+ }
+
+ /// getInt32 - Get a constant 32-bit value.
+ ConstantInt *getInt32(int32_t C) {
+ return ConstantInt::getSigned(getInt32Ty(), C);
+ }
+
+ /// getInt32 - Get a constant 32-bit value.
+ ConstantInt *getInt32(uint32_t C) {
+ return ConstantInt::get(getInt32Ty(), C);
+ }
+
+ /// getInt64 - Get a constant 64-bit value.
+ ConstantInt *getInt64(int64_t C) {
+ return ConstantInt::getSigned(getInt64Ty(), C);
+ }
+
+ /// getInt64 - Get a constant 64-bit value.
+ ConstantInt *getInt64(uint64_t C) {
+ return ConstantInt::get(getInt64Ty(), C);
+ }
//===--------------------------------------------------------------------===//
// Type creation methods
//===--------------------------------------------------------------------===//
/// getInt1Ty - Fetch the type representing a single bit
- const Type *getInt1Ty() {
+ const IntegerType *getInt1Ty() {
return Type::getInt1Ty(Context);
}
/// getInt8Ty - Fetch the type representing an 8-bit integer.
- const Type *getInt8Ty() {
+ const IntegerType *getInt8Ty() {
return Type::getInt8Ty(Context);
}
/// getInt16Ty - Fetch the type representing a 16-bit integer.
- const Type *getInt16Ty() {
+ const IntegerType *getInt16Ty() {
return Type::getInt16Ty(Context);
}
/// getInt32Ty - Fetch the type resepresenting a 32-bit integer.
- const Type *getInt32Ty() {
+ const IntegerType *getInt32Ty() {
return Type::getInt32Ty(Context);
}
/// getInt64Ty - Fetch the type representing a 64-bit integer.
- const Type *getInt64Ty() {
+ const IntegerType *getInt64Ty() {
return Type::getInt64Ty(Context);
}
@@ -151,7 +248,7 @@
return Type::getVoidTy(Context);
}
- const Type *getInt8PtrTy() {
+ const PointerType *getInt8PtrTy() {
return Type::getInt8PtrTy(Context);
}
Modified: llvm/branches/wendling/eh/include/llvm/Target/TargetInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Target/TargetInstrInfo.h?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Target/TargetInstrInfo.h Thu Jul 8 03:14:09 2010
@@ -369,7 +369,13 @@
assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!");
return false;
}
-
+
+ /// copyPhysReg - Emit instructions to copy a pair of physical registers.
+ virtual void copyPhysReg(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI, DebugLoc DL,
+ unsigned DestReg, unsigned SrcReg,
+ bool KillSrc) const =0;
+
/// storeRegToStackSlot - Store the specified register of the given register
/// class to the specified stack frame index. The store instruction is to be
/// added to the given machine basic block before the specified machine
@@ -661,6 +667,10 @@
virtual ScheduleHazardRecognizer *
CreateTargetPostRAHazardRecognizer(const InstrItineraryData&) const;
+ virtual void copyPhysReg(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI, DebugLoc DL,
+ unsigned DestReg, unsigned SrcReg,
+ bool KillSrc) const;
};
} // End llvm namespace
Modified: llvm/branches/wendling/eh/include/llvm/Target/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Target/TargetLowering.h?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Target/TargetLowering.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Target/TargetLowering.h Thu Jul 8 03:14:09 2010
@@ -32,6 +32,7 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/Support/DebugLoc.h"
+#include "llvm/Target/TargetCallingConv.h"
#include "llvm/Target/TargetMachine.h"
#include <climits>
#include <map>
@@ -42,6 +43,7 @@
class CallInst;
class Function;
class FastISel;
+ class FunctionLoweringInfo;
class MachineBasicBlock;
class MachineFunction;
class MachineFrameInfo;
@@ -1144,6 +1146,7 @@
LowerCall(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const {
@@ -1158,7 +1161,7 @@
virtual bool CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<EVT> &OutTys,
const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
- SelectionDAG &DAG) const
+ LLVMContext &Context) const
{
// Return true by default to get preexisting behavior.
return true;
@@ -1172,6 +1175,7 @@
virtual SDValue
LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
DebugLoc dl, SelectionDAG &DAG) const {
assert(0 && "Not Implemented");
return SDValue(); // this is here to silence compiler errors
@@ -1220,16 +1224,7 @@
/// createFastISel - This method returns a target specific FastISel object,
/// or null if the target does not support "fast" ISel.
- virtual FastISel *
- createFastISel(MachineFunction &,
- DenseMap<const Value *, unsigned> &,
- DenseMap<const BasicBlock *, MachineBasicBlock *> &,
- DenseMap<const AllocaInst *, int> &,
- std::vector<std::pair<MachineInstr*, unsigned> > &
-#ifndef NDEBUG
- , SmallSet<const Instruction *, 8> &CatchInfoLost
-#endif
- ) const {
+ virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const {
return 0;
}
Modified: llvm/branches/wendling/eh/include/llvm/Target/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Target/TargetRegisterInfo.h?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Target/TargetRegisterInfo.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Target/TargetRegisterInfo.h Thu Jul 8 03:14:09 2010
@@ -320,7 +320,8 @@
getPhysicalRegisterRegClass(unsigned Reg, EVT VT = MVT::Other) const;
/// getMinimalPhysRegClass - Returns the Register Class of a physical
- /// register of the given type.
+ /// register of the given type, picking the most sub register class of
+ /// the right type that contains this physreg.
const TargetRegisterClass *
getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const;
Propchange: llvm/branches/wendling/eh/lib/Analysis/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -6,3 +6,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Modified: llvm/branches/wendling/eh/lib/Analysis/AliasAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/AliasAnalysis.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/AliasAnalysis.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/AliasAnalysis.cpp Thu Jul 8 03:14:09 2010
@@ -229,20 +229,18 @@
/// identifiable object. This returns true for:
/// Global Variables and Functions (but not Global Aliases)
/// Allocas and Mallocs
-/// ByVal and NoAlias Arguments, if Interprocedural is false
-/// NoAlias returns, if Interprocedural is false
+/// ByVal and NoAlias Arguments
+/// NoAlias returns
///
-bool llvm::isIdentifiedObject(const Value *V, bool Interprocedural) {
+bool llvm::isIdentifiedObject(const Value *V) {
if (isa<AllocaInst>(V))
return true;
if (isa<GlobalValue>(V) && !isa<GlobalAlias>(V))
return true;
- if (!Interprocedural) {
- if (isNoAliasCall(V))
- return true;
- if (const Argument *A = dyn_cast<Argument>(V))
- return A->hasNoAliasAttr() || A->hasByValAttr();
- }
+ if (isNoAliasCall(V))
+ return true;
+ if (const Argument *A = dyn_cast<Argument>(V))
+ return A->hasNoAliasAttr() || A->hasByValAttr();
return false;
}
Modified: llvm/branches/wendling/eh/lib/Analysis/AliasAnalysisEvaluator.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/AliasAnalysisEvaluator.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/AliasAnalysisEvaluator.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/AliasAnalysisEvaluator.cpp Thu Jul 8 03:14:09 2010
@@ -21,7 +21,6 @@
#include "llvm/DerivedTypes.h"
#include "llvm/Function.h"
#include "llvm/Instructions.h"
-#include "llvm/Module.h"
#include "llvm/Pass.h"
#include "llvm/Analysis/Passes.h"
#include "llvm/Analysis/AliasAnalysis.h"
@@ -45,21 +44,20 @@
static cl::opt<bool> PrintModRef("print-modref", cl::ReallyHidden);
namespace {
- /// AAEval - Base class for exhaustive alias analysis evaluators.
- class AAEval {
- protected:
+ class AAEval : public FunctionPass {
unsigned NoAlias, MayAlias, MustAlias;
unsigned NoModRef, Mod, Ref, ModRef;
- SetVector<Value *> Pointers;
- SetVector<CallSite> CallSites;
+ public:
+ static char ID; // Pass identification, replacement for typeid
+ AAEval() : FunctionPass(&ID) {}
- void getAnalysisUsage(AnalysisUsage &AU) const {
+ virtual void getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<AliasAnalysis>();
AU.setPreservesAll();
}
- void doInitialization(Module &M) {
+ bool doInitialization(Module &M) {
NoAlias = MayAlias = MustAlias = 0;
NoModRef = Mod = Ref = ModRef = 0;
@@ -67,85 +65,19 @@
PrintNoAlias = PrintMayAlias = PrintMustAlias = true;
PrintNoModRef = PrintMod = PrintRef = PrintModRef = true;
}
- }
-
- void runOnFunction(Function &F);
- void evaluate(AliasAnalysis *AA, Module *M);
- void doFinalization(Module &M);
- };
-
- class FunctionAAEval : public FunctionPass, AAEval {
- public:
- static char ID; // Pass identification, replacement for typeid
- FunctionAAEval() : FunctionPass(&ID) {}
-
- virtual void getAnalysisUsage(AnalysisUsage &AU) const {
- return AAEval::getAnalysisUsage(AU);
- }
-
- virtual bool doInitialization(Module &M) {
- AAEval::doInitialization(M);
- return false;
- }
-
- virtual bool runOnFunction(Function &F) {
- AAEval::runOnFunction(F);
-
- if (PrintNoAlias || PrintMayAlias || PrintMustAlias ||
- PrintNoModRef || PrintMod || PrintRef || PrintModRef)
- errs() << "Function: " << F.getName() << ": " << Pointers.size()
- << " pointers, " << CallSites.size() << " call sites\n";
-
- AAEval::evaluate(&getAnalysis<AliasAnalysis>(), F.getParent());
- return false;
- }
-
- virtual bool doFinalization(Module &M) {
- AAEval::doFinalization(M);
return false;
}
- };
-
- class InterproceduralAAEval : public ModulePass, AAEval {
- public:
- static char ID; // Pass identification, replacement for typeid
- InterproceduralAAEval() : ModulePass(&ID) {}
-
- virtual void getAnalysisUsage(AnalysisUsage &AU) const {
- return AAEval::getAnalysisUsage(AU);
- }
-
- virtual bool runOnModule(Module &M) {
- AAEval::doInitialization(M);
- for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I)
- AAEval::runOnFunction(*I);
-
- if (PrintNoAlias || PrintMayAlias || PrintMustAlias ||
- PrintNoModRef || PrintMod || PrintRef || PrintModRef)
- errs() << "Module: " << Pointers.size()
- << " pointers, " << CallSites.size() << " call sites\n";
- AAEval::evaluate(&getAnalysis<AliasAnalysis>(), &M);
- AAEval::doFinalization(M);
- return false;
- }
+ bool runOnFunction(Function &F);
+ bool doFinalization(Module &M);
};
}
-char FunctionAAEval::ID = 0;
-static RegisterPass<FunctionAAEval>
+char AAEval::ID = 0;
+static RegisterPass<AAEval>
X("aa-eval", "Exhaustive Alias Analysis Precision Evaluator", false, true);
-FunctionPass *llvm::createAAEvalPass() { return new FunctionAAEval(); }
-
-char InterproceduralAAEval::ID = 0;
-static RegisterPass<InterproceduralAAEval>
-Y("interprocedural-aa-eval",
- "Exhaustive Interprocedural Alias Analysis Precision Evaluator", false, true);
-
-Pass *llvm::createInterproceduralAAEvalPass() {
- return new InterproceduralAAEval();
-}
+FunctionPass *llvm::createAAEvalPass() { return new AAEval(); }
static void PrintResults(const char *Msg, bool P, const Value *V1,
const Value *V2, const Module *M) {
@@ -180,7 +112,12 @@
&& !isa<ConstantPointerNull>(V);
}
-void AAEval::runOnFunction(Function &F) {
+bool AAEval::runOnFunction(Function &F) {
+ AliasAnalysis &AA = getAnalysis<AliasAnalysis>();
+
+ SetVector<Value *> Pointers;
+ SetVector<CallSite> CallSites;
+
for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I)
if (I->getType()->isPointerTy()) // Add all pointer arguments.
Pointers.insert(I);
@@ -210,31 +147,33 @@
if (CS.getInstruction()) CallSites.insert(CS);
}
-}
-void AAEval::evaluate(AliasAnalysis *AA, Module *M) {
+ if (PrintNoAlias || PrintMayAlias || PrintMustAlias ||
+ PrintNoModRef || PrintMod || PrintRef || PrintModRef)
+ errs() << "Function: " << F.getName() << ": " << Pointers.size()
+ << " pointers, " << CallSites.size() << " call sites\n";
// iterate over the worklist, and run the full (n^2)/2 disambiguations
for (SetVector<Value *>::iterator I1 = Pointers.begin(), E = Pointers.end();
I1 != E; ++I1) {
unsigned I1Size = ~0u;
const Type *I1ElTy = cast<PointerType>((*I1)->getType())->getElementType();
- if (I1ElTy->isSized()) I1Size = AA->getTypeStoreSize(I1ElTy);
+ if (I1ElTy->isSized()) I1Size = AA.getTypeStoreSize(I1ElTy);
for (SetVector<Value *>::iterator I2 = Pointers.begin(); I2 != I1; ++I2) {
unsigned I2Size = ~0u;
const Type *I2ElTy =cast<PointerType>((*I2)->getType())->getElementType();
- if (I2ElTy->isSized()) I2Size = AA->getTypeStoreSize(I2ElTy);
+ if (I2ElTy->isSized()) I2Size = AA.getTypeStoreSize(I2ElTy);
- switch (AA->alias(*I1, I1Size, *I2, I2Size)) {
+ switch (AA.alias(*I1, I1Size, *I2, I2Size)) {
case AliasAnalysis::NoAlias:
- PrintResults("NoAlias", PrintNoAlias, *I1, *I2, M);
+ PrintResults("NoAlias", PrintNoAlias, *I1, *I2, F.getParent());
++NoAlias; break;
case AliasAnalysis::MayAlias:
- PrintResults("MayAlias", PrintMayAlias, *I1, *I2, M);
+ PrintResults("MayAlias", PrintMayAlias, *I1, *I2, F.getParent());
++MayAlias; break;
case AliasAnalysis::MustAlias:
- PrintResults("MustAlias", PrintMustAlias, *I1, *I2, M);
+ PrintResults("MustAlias", PrintMustAlias, *I1, *I2, F.getParent());
++MustAlias; break;
default:
errs() << "Unknown alias query result!\n";
@@ -251,20 +190,20 @@
V != Ve; ++V) {
unsigned Size = ~0u;
const Type *ElTy = cast<PointerType>((*V)->getType())->getElementType();
- if (ElTy->isSized()) Size = AA->getTypeStoreSize(ElTy);
+ if (ElTy->isSized()) Size = AA.getTypeStoreSize(ElTy);
- switch (AA->getModRefInfo(*C, *V, Size)) {
+ switch (AA.getModRefInfo(*C, *V, Size)) {
case AliasAnalysis::NoModRef:
- PrintModRefResults("NoModRef", PrintNoModRef, I, *V, M);
+ PrintModRefResults("NoModRef", PrintNoModRef, I, *V, F.getParent());
++NoModRef; break;
case AliasAnalysis::Mod:
- PrintModRefResults(" Mod", PrintMod, I, *V, M);
+ PrintModRefResults(" Mod", PrintMod, I, *V, F.getParent());
++Mod; break;
case AliasAnalysis::Ref:
- PrintModRefResults(" Ref", PrintRef, I, *V, M);
+ PrintModRefResults(" Ref", PrintRef, I, *V, F.getParent());
++Ref; break;
case AliasAnalysis::ModRef:
- PrintModRefResults(" ModRef", PrintModRef, I, *V, M);
+ PrintModRefResults(" ModRef", PrintModRef, I, *V, F.getParent());
++ModRef; break;
default:
errs() << "Unknown alias query result!\n";
@@ -272,8 +211,7 @@
}
}
- Pointers.clear();
- CallSites.clear();
+ return false;
}
static void PrintPercent(unsigned Num, unsigned Sum) {
@@ -281,7 +219,7 @@
<< ((Num*1000ULL/Sum) % 10) << "%)\n";
}
-void AAEval::doFinalization(Module &M) {
+bool AAEval::doFinalization(Module &M) {
unsigned AliasSum = NoAlias + MayAlias + MustAlias;
errs() << "===== Alias Analysis Evaluator Report =====\n";
if (AliasSum == 0) {
@@ -317,4 +255,6 @@
<< NoModRef*100/ModRefSum << "%/" << Mod*100/ModRefSum << "%/"
<< Ref*100/ModRefSum << "%/" << ModRef*100/ModRefSum << "%\n";
}
+
+ return false;
}
Modified: llvm/branches/wendling/eh/lib/Analysis/BasicAliasAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/BasicAliasAnalysis.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/BasicAliasAnalysis.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/BasicAliasAnalysis.cpp Thu Jul 8 03:14:09 2010
@@ -194,6 +194,7 @@
// BasicAliasAnalysis Pass
//===----------------------------------------------------------------------===//
+#ifndef NDEBUG
static const Function *getParent(const Value *V) {
if (const Instruction *inst = dyn_cast<Instruction>(V))
return inst->getParent()->getParent();
@@ -204,15 +205,6 @@
return NULL;
}
-static bool sameParent(const Value *O1, const Value *O2) {
-
- const Function *F1 = getParent(O1);
- const Function *F2 = getParent(O2);
-
- return F1 && F1 == F2;
-}
-
-#ifdef XDEBUG
static bool notDifferentParent(const Value *O1, const Value *O2) {
const Function *F1 = getParent(O1);
@@ -227,25 +219,14 @@
/// Because it doesn't chain to a previous alias analysis (like -no-aa), it
/// derives from the NoAA class.
struct BasicAliasAnalysis : public NoAA {
- /// Interprocedural - Flag for "interprocedural" mode, where we must
- /// support queries of values which live in different functions.
- bool Interprocedural;
-
static char ID; // Class identification, replacement for typeinfo
- BasicAliasAnalysis()
- : NoAA(&ID), Interprocedural(false) {}
- BasicAliasAnalysis(void *PID, bool interprocedural)
- : NoAA(PID), Interprocedural(interprocedural) {}
+ BasicAliasAnalysis() : NoAA(&ID) {}
AliasResult alias(const Value *V1, unsigned V1Size,
const Value *V2, unsigned V2Size) {
assert(Visited.empty() && "Visited must be cleared after use!");
-#ifdef XDEBUG
- assert((Interprocedural || notDifferentParent(V1, V2)) &&
- "BasicAliasAnalysis (-basicaa) doesn't support interprocedural "
- "queries; use InterproceduralAliasAnalysis "
- "(-interprocedural-basic-aa) instead.");
-#endif
+ assert(notDifferentParent(V1, V2) &&
+ "BasicAliasAnalysis doesn't support interprocedural queries.");
AliasResult Alias = aliasCheck(V1, V1Size, V2, V2Size);
Visited.clear();
return Alias;
@@ -324,6 +305,9 @@
/// simple "address taken" analysis on local objects.
AliasAnalysis::ModRefResult
BasicAliasAnalysis::getModRefInfo(CallSite CS, Value *P, unsigned Size) {
+ assert(notDifferentParent(CS.getInstruction(), P) &&
+ "AliasAnalysis query involving multiple functions!");
+
const Value *Object = P->getUnderlyingObject();
// If this is a tail call and P points to a stack location, we know that
@@ -336,16 +320,10 @@
if (CI->isTailCall())
return NoModRef;
- // If we can identify an object and it's known to be within the
- // same function as the call, we can ignore interprocedural concerns.
- bool EffectivelyInterprocedural =
- Interprocedural && !sameParent(Object, CS.getInstruction());
-
// If the pointer is to a locally allocated object that does not escape,
// then the call can not mod/ref the pointer unless the call takes the pointer
// as an argument, and itself doesn't capture it.
if (!isa<Constant>(Object) && CS.getInstruction() != Object &&
- !EffectivelyInterprocedural &&
isNonEscapingLocalObject(Object)) {
bool PassedAsArg = false;
unsigned ArgNo = 0;
@@ -765,39 +743,42 @@
if (CPN->getType()->getAddressSpace() == 0)
return NoAlias;
- // If we can identify two objects and they're known to be within the
- // same function, we can ignore interprocedural concerns.
- bool EffectivelyInterprocedural =
- Interprocedural && !sameParent(O1, O2);
-
if (O1 != O2) {
// If V1/V2 point to two different objects we know that we have no alias.
- if (isIdentifiedObject(O1, EffectivelyInterprocedural) &&
- isIdentifiedObject(O2, EffectivelyInterprocedural))
+ if (isIdentifiedObject(O1) && isIdentifiedObject(O2))
return NoAlias;
// Constant pointers can't alias with non-const isIdentifiedObject objects.
- if ((isa<Constant>(O1) &&
- isIdentifiedObject(O2, EffectivelyInterprocedural) &&
- !isa<Constant>(O2)) ||
- (isa<Constant>(O2) &&
- isIdentifiedObject(O1, EffectivelyInterprocedural) &&
- !isa<Constant>(O1)))
+ if ((isa<Constant>(O1) && isIdentifiedObject(O2) && !isa<Constant>(O2)) ||
+ (isa<Constant>(O2) && isIdentifiedObject(O1) && !isa<Constant>(O1)))
return NoAlias;
// Arguments can't alias with local allocations or noalias calls
// in the same function.
- if (!EffectivelyInterprocedural &&
- ((isa<Argument>(O1) && (isa<AllocaInst>(O2) || isNoAliasCall(O2))) ||
+ if (((isa<Argument>(O1) && (isa<AllocaInst>(O2) || isNoAliasCall(O2))) ||
(isa<Argument>(O2) && (isa<AllocaInst>(O1) || isNoAliasCall(O1)))))
return NoAlias;
// Most objects can't alias null.
- if ((isa<ConstantPointerNull>(V2) && isKnownNonNull(O1)) ||
- (isa<ConstantPointerNull>(V1) && isKnownNonNull(O2)))
+ if ((isa<ConstantPointerNull>(O2) && isKnownNonNull(O1)) ||
+ (isa<ConstantPointerNull>(O1) && isKnownNonNull(O2)))
return NoAlias;
- }
+ // If one pointer is the result of a call/invoke or load and the other is a
+ // non-escaping local object within the same function, then we know the
+ // object couldn't escape to a point where the call could return it.
+ //
+ // Note that if the pointers are in different functions, there are a
+ // variety of complications. A call with a nocapture argument may still
+ // temporary store the nocapture argument's value in a temporary memory
+ // location if that memory location doesn't escape. Or it may pass a
+ // nocapture value to other functions as long as they don't capture it.
+ if (isEscapeSource(O1) && isNonEscapingLocalObject(O2))
+ return NoAlias;
+ if (isEscapeSource(O2) && isNonEscapingLocalObject(O1))
+ return NoAlias;
+ }
+
// If the size of one access is larger than the entire object on the other
// side, then we know such behavior is undefined and can assume no alias.
if (TD)
@@ -805,22 +786,6 @@
(V2Size != ~0U && isObjectSmallerThan(O1, V2Size, *TD)))
return NoAlias;
- // If one pointer is the result of a call/invoke or load and the other is a
- // non-escaping local object within the same function, then we know the
- // object couldn't escape to a point where the call could return it.
- //
- // Note that if the pointers are in different functions, there are a
- // variety of complications. A call with a nocapture argument may still
- // temporary store the nocapture argument's value in a temporary memory
- // location if that memory location doesn't escape. Or it may pass a
- // nocapture value to other functions as long as they don't capture it.
- if (O1 != O2 && !EffectivelyInterprocedural) {
- if (isEscapeSource(O1) && isNonEscapingLocalObject(O2))
- return NoAlias;
- if (isEscapeSource(O2) && isNonEscapingLocalObject(O1))
- return NoAlias;
- }
-
// FIXME: This isn't aggressively handling alias(GEP, PHI) for example: if the
// GEP can't simplify, we don't even look at the PHI cases.
if (!isa<GEPOperator>(V1) && isa<GEPOperator>(V2)) {
@@ -850,33 +815,3 @@
// Make sure that anything that uses AliasAnalysis pulls in this file.
DEFINING_FILE_FOR(BasicAliasAnalysis)
-
-//===----------------------------------------------------------------------===//
-// InterproceduralBasicAliasAnalysis Pass
-//===----------------------------------------------------------------------===//
-
-namespace {
- /// InterproceduralBasicAliasAnalysis - This is similar to basicaa, except
- /// that it properly supports queries to values which live in different
- /// functions.
- ///
- /// Note that we don't currently take this to the extreme, analyzing all
- /// call sites of a function to answer a query about an Argument.
- ///
- struct InterproceduralBasicAliasAnalysis : public BasicAliasAnalysis {
- static char ID; // Class identification, replacement for typeinfo
- InterproceduralBasicAliasAnalysis() : BasicAliasAnalysis(&ID, true) {}
- };
-}
-
-// Register this pass...
-char InterproceduralBasicAliasAnalysis::ID = 0;
-static RegisterPass<InterproceduralBasicAliasAnalysis>
-W("interprocedural-basic-aa", "Interprocedural Basic Alias Analysis", false, true);
-
-// Declare that we implement the AliasAnalysis interface
-static RegisterAnalysisGroup<AliasAnalysis> Z(W);
-
-ImmutablePass *llvm::createInterproceduralBasicAliasAnalysisPass() {
- return new InterproceduralBasicAliasAnalysis();
-}
Modified: llvm/branches/wendling/eh/lib/Analysis/ConstantFolding.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/ConstantFolding.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/ConstantFolding.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/ConstantFolding.cpp Thu Jul 8 03:14:09 2010
@@ -772,9 +772,9 @@
case Instruction::ICmp:
case Instruction::FCmp: assert(0 && "Invalid for compares");
case Instruction::Call:
- if (Function *F = dyn_cast<Function>(Ops[0]))
+ if (Function *F = dyn_cast<Function>(Ops[CallInst::ArgOffset ? 0:NumOps-1]))
if (canConstantFoldCallTo(F))
- return ConstantFoldCall(F, Ops+1, NumOps-1);
+ return ConstantFoldCall(F, Ops+CallInst::ArgOffset, NumOps-1);
return 0;
case Instruction::PtrToInt:
// If the input is a inttoptr, eliminate the pair. This requires knowing
Propchange: llvm/branches/wendling/eh/lib/Analysis/IPA/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -6,3 +6,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Modified: llvm/branches/wendling/eh/lib/Analysis/Lint.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/Lint.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/Lint.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/Lint.cpp Thu Jul 8 03:14:09 2010
@@ -19,7 +19,8 @@
//
// Another limitation is that it assumes all code will be executed. A store
// through a null pointer in a basic block which is never reached is harmless,
-// but this pass will warn about it anyway.
+// but this pass will warn about it anyway. This is the main reason why most
+// of these checks live here instead of in the Verifier pass.
//
// Optimization passes may make conditions that this pass checks for more or
// less obvious. If an optimization pass appears to be introducing a warning,
@@ -200,6 +201,8 @@
// fairly common mistake to neglect to name a function.
Assert1(F.hasName() || F.hasLocalLinkage(),
"Unusual: Unnamed function with non-local linkage", &F);
+
+ // TODO: Check for irreducible control flow.
}
void Lint::visitCallSite(CallSite CS) {
@@ -223,6 +226,7 @@
"argument count", &I);
// Check argument types (in case the callee was casted) and attributes.
+ // TODO: Verify that caller and callee attributes are compatible.
Function::arg_iterator PI = F->arg_begin(), PE = F->arg_end();
CallSite::arg_iterator AI = CS.arg_begin(), AE = CS.arg_end();
for (; AI != AE; ++AI) {
@@ -360,6 +364,7 @@
}
// TODO: Check that the reference is in bounds.
+// TODO: Check readnone/readonly function attributes.
void Lint::visitMemoryReference(Instruction &I,
Value *Ptr, unsigned Size, unsigned Align,
const Type *Ty, unsigned Flags) {
@@ -500,6 +505,8 @@
// This isn't undefined behavior, it's just an obvious pessimization.
Assert1(&I.getParent()->getParent()->getEntryBlock() == I.getParent(),
"Pessimization: Static alloca outside of entry block", &I);
+
+ // TODO: Check for an unusual size (MSB set?)
}
void Lint::visitVAArgInst(VAArgInst &I) {
Propchange: llvm/branches/wendling/eh/lib/Archive/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -6,3 +6,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/AsmParser/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -6,3 +6,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Bitcode/Reader/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -6,3 +6,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Bitcode/Writer/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -6,3 +6,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/CodeGen/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/CodeGen/AsmPrinter/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Modified: llvm/branches/wendling/eh/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Thu Jul 8 03:14:09 2010
@@ -44,7 +44,8 @@
static cl::opt<bool> PrintDbgScope("print-dbgscope", cl::Hidden,
cl::desc("Print DbgScope information for each machine instruction"));
-static cl::opt<bool> DisableDebugInfoPrinting("disable-debug-info-print", cl::Hidden,
+static cl::opt<bool> DisableDebugInfoPrinting("disable-debug-info-print",
+ cl::Hidden,
cl::desc("Disable debug info printing"));
static cl::opt<bool> UnknownLocations("use-unknown-locations", cl::Hidden,
@@ -79,15 +80,13 @@
/// IndexTyDie - An anonymous type for index type. Owned by CUDie.
DIE *IndexTyDie;
- /// GVToDieMap - Tracks the mapping of unit level debug informaton
+ /// MDNodeToDieMap - Tracks the mapping of unit level debug informaton
/// variables to debug information entries.
- /// FIXME : Rename GVToDieMap -> NodeToDieMap
- DenseMap<const MDNode *, DIE *> GVToDieMap;
+ DenseMap<const MDNode *, DIE *> MDNodeToDieMap;
- /// GVToDIEEntryMap - Tracks the mapping of unit level debug informaton
+ /// MDNodeToDIEEntryMap - Tracks the mapping of unit level debug informaton
/// descriptors to debug information entries using a DIEEntry proxy.
- /// FIXME : Rename
- DenseMap<const MDNode *, DIEEntry *> GVToDIEEntryMap;
+ DenseMap<const MDNode *, DIEEntry *> MDNodeToDIEEntryMap;
/// Globals - A map of globally visible named entities for this unit.
///
@@ -123,25 +122,25 @@
/// getDIE - Returns the debug information entry map slot for the
/// specified debug variable.
- DIE *getDIE(const MDNode *N) { return GVToDieMap.lookup(N); }
+ DIE *getDIE(const MDNode *N) { return MDNodeToDieMap.lookup(N); }
/// insertDIE - Insert DIE into the map.
void insertDIE(const MDNode *N, DIE *D) {
- GVToDieMap.insert(std::make_pair(N, D));
+ MDNodeToDieMap.insert(std::make_pair(N, D));
}
/// getDIEEntry - Returns the debug information entry for the speciefied
/// debug variable.
DIEEntry *getDIEEntry(const MDNode *N) {
- DenseMap<const MDNode *, DIEEntry *>::iterator I = GVToDIEEntryMap.find(N);
- if (I == GVToDIEEntryMap.end())
+ DenseMap<const MDNode *, DIEEntry *>::iterator I = MDNodeToDIEEntryMap.find(N);
+ if (I == MDNodeToDIEEntryMap.end())
return NULL;
return I->second;
}
/// insertDIEEntry - Insert debug information entry into the map.
void insertDIEEntry(const MDNode *N, DIEEntry *E) {
- GVToDIEEntryMap.insert(std::make_pair(N, E));
+ MDNodeToDIEEntryMap.insert(std::make_pair(N, E));
}
/// addDie - Adds or interns the DIE to the compile unit.
@@ -1072,8 +1071,9 @@
if (!Name.empty())
addString(&Buffer, dwarf::DW_AT_name, dwarf::DW_FORM_string, Name);
- if (Tag == dwarf::DW_TAG_enumeration_type || Tag == dwarf::DW_TAG_class_type ||
- Tag == dwarf::DW_TAG_structure_type || Tag == dwarf::DW_TAG_union_type) {
+ if (Tag == dwarf::DW_TAG_enumeration_type || Tag == dwarf::DW_TAG_class_type
+ || Tag == dwarf::DW_TAG_structure_type || Tag == dwarf::DW_TAG_union_type)
+ {
// Add size if non-zero (derived types might be zero-sized.)
if (Size)
addUInt(&Buffer, dwarf::DW_AT_byte_size, 0, Size);
@@ -1389,6 +1389,7 @@
DIE *DwarfDebug::updateSubprogramScopeDIE(const MDNode *SPNode) {
CompileUnit *SPCU = getCompileUnit(SPNode);
DIE *SPDie = SPCU->getDIE(SPNode);
+
assert(SPDie && "Unable to find subprogram DIE!");
DISubprogram SP(SPNode);
@@ -1422,6 +1423,14 @@
SPCU->addDie(SPDie);
}
+ // Pick up abstract subprogram DIE.
+ if (DIE *AbsSPDIE = AbstractSPDies.lookup(SPNode)) {
+ SPDie = new DIE(dwarf::DW_TAG_subprogram);
+ addDIEEntry(SPDie, dwarf::DW_AT_abstract_origin,
+ dwarf::DW_FORM_ref4, AbsSPDIE);
+ SPCU->addDie(SPDie);
+ }
+
addLabel(SPDie, dwarf::DW_AT_low_pc, dwarf::DW_FORM_addr,
Asm->GetTempSymbol("func_begin", Asm->getFunctionNumber()));
addLabel(SPDie, dwarf::DW_AT_high_pc, dwarf::DW_FORM_addr,
@@ -1615,11 +1624,13 @@
// FIXME : Handle getNumOperands != 3
if (DVInsn->getNumOperands() == 3) {
if (DVInsn->getOperand(0).isReg())
- updated = addRegisterAddress(VariableDie, DVLabel, DVInsn->getOperand(0));
+ updated =
+ addRegisterAddress(VariableDie, DVLabel, DVInsn->getOperand(0));
else if (DVInsn->getOperand(0).isImm())
updated = addConstantValue(VariableDie, DVLabel, DVInsn->getOperand(0));
else if (DVInsn->getOperand(0).isFPImm())
- updated = addConstantFPValue(VariableDie, DVLabel, DVInsn->getOperand(0));
+ updated =
+ addConstantFPValue(VariableDie, DVLabel, DVInsn->getOperand(0));
} else {
MachineLocation Location = Asm->getDebugValueLocation(DVInsn);
if (Location.getReg()) {
@@ -1693,8 +1704,12 @@
ScopeDIE = constructInlinedScopeDIE(Scope);
else if (DS.isSubprogram()) {
ProcessedSPNodes.insert(DS);
- if (Scope->isAbstractScope())
+ if (Scope->isAbstractScope()) {
ScopeDIE = getCompileUnit(DS)->getDIE(DS);
+ // Note down abstract DIE.
+ if (ScopeDIE)
+ AbstractSPDies.insert(std::make_pair(DS, ScopeDIE));
+ }
else
ScopeDIE = updateSubprogramScopeDIE(DS);
}
@@ -2270,7 +2285,8 @@
const MachineInstr *Begin = NULL;
const MachineInstr *End = NULL;
for (SmallVector<const MachineInstr *, 4>::iterator
- MVI = MultipleValues.begin(), MVE = MultipleValues.end(); MVI != MVE; ++MVI) {
+ MVI = MultipleValues.begin(), MVE = MultipleValues.end();
+ MVI != MVE; ++MVI) {
if (!Begin) {
Begin = *MVI;
continue;
@@ -2375,7 +2391,8 @@
}
/// getOrCreateDbgScope - Create DbgScope for the scope.
-DbgScope *DwarfDebug::getOrCreateDbgScope(const MDNode *Scope, const MDNode *InlinedAt) {
+DbgScope *DwarfDebug::getOrCreateDbgScope(const MDNode *Scope,
+ const MDNode *InlinedAt) {
if (!InlinedAt) {
DbgScope *WScope = DbgScopeMap.lookup(Scope);
if (WScope)
@@ -2548,7 +2565,8 @@
// current instruction scope does not match scope of first instruction
// in this range then create a new instruction range.
DbgRange R(RangeBeginMI, PrevMI);
- MI2ScopeMap[RangeBeginMI] = getOrCreateDbgScope(PrevScope, PrevInlinedAt);
+ MI2ScopeMap[RangeBeginMI] = getOrCreateDbgScope(PrevScope,
+ PrevInlinedAt);
MIRanges.push_back(R);
}
@@ -2771,7 +2789,7 @@
if (ProcessedSPNodes.count((*AI)->getScopeNode()) == 0)
constructScopeDIE(*AI);
}
-
+
DIE *CurFnDIE = constructScopeDIE(CurrentFnDbgScope);
if (!DisableFramePointerElim(*MF))
@@ -2852,7 +2870,8 @@
/// recordSourceLine - Register a source line with debug info. Returns the
/// unique label that was emitted and which provides correspondence to
/// the source line list.
-MCSymbol *DwarfDebug::recordSourceLine(unsigned Line, unsigned Col, const MDNode *S) {
+MCSymbol *DwarfDebug::recordSourceLine(unsigned Line, unsigned Col,
+ const MDNode *S) {
StringRef Dir;
StringRef Fn;
@@ -3597,8 +3616,9 @@
unsigned char Size = Asm->getTargetData().getPointerSize();
Asm->OutStreamer.EmitLabel(Asm->GetTempSymbol("debug_loc", 0));
unsigned index = 1;
- for (SmallVector<DotDebugLocEntry, 4>::iterator I = DotDebugLocEntries.begin(),
- E = DotDebugLocEntries.end(); I != E; ++I, ++index) {
+ for (SmallVector<DotDebugLocEntry, 4>::iterator
+ I = DotDebugLocEntries.begin(), E = DotDebugLocEntries.end();
+ I != E; ++I, ++index) {
DotDebugLocEntry Entry = *I;
if (Entry.isEmpty()) {
Asm->OutStreamer.EmitIntValue(0, Size, /*addrspace*/0);
Modified: llvm/branches/wendling/eh/lib/CodeGen/AsmPrinter/DwarfDebug.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/AsmPrinter/DwarfDebug.h (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/AsmPrinter/DwarfDebug.h Thu Jul 8 03:14:09 2010
@@ -156,6 +156,9 @@
/// not included DbgScopeMap. AbstractScopes owns its DbgScope*s.
DenseMap<const MDNode *, DbgScope *> AbstractScopes;
+ /// AbstractSPDies - Collection of abstract subprogram DIEs.
+ DenseMap<const MDNode *, DIE *> AbstractSPDies;
+
/// AbstractScopesList - Tracks abstract scopes constructed while processing
/// a function. This list is cleared during endFunction().
SmallVector<DbgScope *, 4>AbstractScopesList;
Modified: llvm/branches/wendling/eh/lib/CodeGen/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/CMakeLists.txt?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/CMakeLists.txt (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/CMakeLists.txt Thu Jul 8 03:14:09 2010
@@ -3,6 +3,7 @@
Analysis.cpp
BranchFolding.cpp
CalcSpillWeights.cpp
+ CallingConvLower.cpp
CodePlacementOpt.cpp
CriticalAntiDepBreaker.cpp
DeadMachineInstructionElim.cpp
Modified: llvm/branches/wendling/eh/lib/CodeGen/LLVMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/LLVMTargetMachine.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/LLVMTargetMachine.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/LLVMTargetMachine.cpp Thu Jul 8 03:14:09 2010
@@ -272,7 +272,8 @@
PM.add(createDwarfEHPass(this, OptLevel==CodeGenOpt::None));
break;
case ExceptionHandling::Dwarf:
- PM.add(createDwarfEHPass(this, OptLevel==CodeGenOpt::None));
+///EH-FIXME: Try to get by without the DwarfEHPass.
+///EH-FIXME: PM.add(createDwarfEHPass(this, OptLevel==CodeGenOpt::None));
break;
case ExceptionHandling::None:
PM.add(createLowerInvokePass(getTargetLowering()));
Modified: llvm/branches/wendling/eh/lib/CodeGen/LiveIntervalAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/LiveIntervalAnalysis.cpp Thu Jul 8 03:14:09 2010
@@ -265,7 +265,7 @@
if (MO.getReg() == Reg && MO.isDef()) {
assert(MI.getOperand(MOIdx).getSubReg() != MO.getSubReg() &&
MI.getOperand(MOIdx).getSubReg() &&
- MO.getSubReg());
+ (MO.getSubReg() || MO.isImplicit()));
return true;
}
}
Modified: llvm/branches/wendling/eh/lib/CodeGen/LowerSubregs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/LowerSubregs.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/LowerSubregs.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/LowerSubregs.cpp Thu Jul 8 03:14:09 2010
@@ -85,7 +85,7 @@
if (MII->addRegisterDead(DstReg, TRI))
break;
assert(MII != MI->getParent()->begin() &&
- "copyRegToReg output doesn't reference destination register!");
+ "copyPhysReg output doesn't reference destination register!");
}
}
@@ -102,7 +102,7 @@
if (MII->addRegisterKilled(SrcReg, TRI, AddIfNotFound))
break;
assert(MII != MI->getParent()->begin() &&
- "copyRegToReg output doesn't reference source register!");
+ "copyPhysReg output doesn't reference source register!");
}
}
@@ -155,13 +155,7 @@
DEBUG(dbgs() << "subreg: eliminated!");
} else {
- // Insert copy
- const TargetRegisterClass *TRCS = TRI->getPhysicalRegisterRegClass(DstReg);
- const TargetRegisterClass *TRCD = TRI->getPhysicalRegisterRegClass(SrcReg);
- bool Emitted = TII->copyRegToReg(*MBB, MI, DstReg, SrcReg, TRCD, TRCS,
- MI->getDebugLoc());
- (void)Emitted;
- assert(Emitted && "Subreg and Dst must be of compatible register class");
+ TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstReg, SrcReg, false);
// Transfer the kill/dead flags, if needed.
if (MI->getOperand(0).isDead())
TransferDeadFlag(MI, DstReg, TRI);
@@ -215,18 +209,11 @@
}
DEBUG(dbgs() << "subreg: eliminated!");
} else {
- // Insert sub-register copy
- const TargetRegisterClass *TRC0= TRI->getPhysicalRegisterRegClass(DstSubReg);
- const TargetRegisterClass *TRC1= TRI->getPhysicalRegisterRegClass(InsReg);
- bool Emitted = TII->copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1,
- MI->getDebugLoc());
- (void)Emitted;
- assert(Emitted && "Subreg and Dst must be of compatible register class");
+ TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg,
+ MI->getOperand(2).isKill());
// Transfer the kill/dead flags, if needed.
if (MI->getOperand(0).isDead())
TransferDeadFlag(MI, DstSubReg, TRI);
- if (MI->getOperand(2).isKill())
- TransferKillFlag(MI, InsReg, TRI);
DEBUG({
MachineBasicBlock::iterator dMI = MI;
dbgs() << "subreg: " << *(--dMI);
@@ -280,18 +267,13 @@
}
} else {
// Insert sub-register copy
- const TargetRegisterClass *TRC0= TRI->getPhysicalRegisterRegClass(DstSubReg);
- const TargetRegisterClass *TRC1= TRI->getPhysicalRegisterRegClass(InsReg);
if (MI->getOperand(2).isUndef())
// If the source register being inserted is undef, then this becomes a
// KILL.
BuildMI(*MBB, MI, MI->getDebugLoc(),
TII->get(TargetOpcode::KILL), DstSubReg);
else {
- bool Emitted = TII->copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1,
- MI->getDebugLoc());
- (void)Emitted;
- assert(Emitted && "Subreg and Dst must be of compatible register class");
+ TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg, false);
}
MachineBasicBlock::iterator CopyMI = MI;
--CopyMI;
@@ -343,21 +325,11 @@
}
DEBUG(dbgs() << "real copy: " << *MI);
- // Ask target for a lowered copy instruction.
- const TargetRegisterClass *DstRC =
- TRI->getPhysicalRegisterRegClass(DstMO.getReg());
- const TargetRegisterClass *SrcRC =
- TRI->getPhysicalRegisterRegClass(SrcMO.getReg());
- bool Emitted = TII->copyRegToReg(*MI->getParent(), MI,
- DstMO.getReg(), SrcMO.getReg(),
- DstRC, SrcRC, MI->getDebugLoc());
- (void)Emitted;
- assert(Emitted && "Cannot emit copy");
+ TII->copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(),
+ DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill());
if (DstMO.isDead())
TransferDeadFlag(MI, DstMO.getReg(), TRI);
- if (SrcMO.isKill())
- TransferKillFlag(MI, SrcMO.getReg(), TRI, true);
if (MI->getNumOperands() > 2)
TransferImplicitDefs(MI);
DEBUG({
Modified: llvm/branches/wendling/eh/lib/CodeGen/MachineBasicBlock.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/MachineBasicBlock.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/MachineBasicBlock.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/MachineBasicBlock.cpp Thu Jul 8 03:14:09 2010
@@ -139,6 +139,13 @@
Parent->getParent()->DeleteMachineInstr(MI);
}
+MachineBasicBlock::iterator MachineBasicBlock::getFirstNonPHI() {
+ iterator I = begin();
+ while (I != end() && I->isPHI())
+ ++I;
+ return I;
+}
+
MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator() {
iterator I = end();
while (I != begin() && (--I)->getDesc().isTerminator())
@@ -335,12 +342,32 @@
if (this == fromMBB)
return;
- for (MachineBasicBlock::succ_iterator I = fromMBB->succ_begin(),
- E = fromMBB->succ_end(); I != E; ++I)
- addSuccessor(*I);
+ while (!fromMBB->succ_empty()) {
+ MachineBasicBlock *Succ = *fromMBB->succ_begin();
+ addSuccessor(Succ);
+ fromMBB->removeSuccessor(Succ);
+ }
+}
+
+void
+MachineBasicBlock::transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB) {
+ if (this == fromMBB)
+ return;
- while (!fromMBB->succ_empty())
- fromMBB->removeSuccessor(fromMBB->succ_begin());
+ while (!fromMBB->succ_empty()) {
+ MachineBasicBlock *Succ = *fromMBB->succ_begin();
+ addSuccessor(Succ);
+ fromMBB->removeSuccessor(Succ);
+
+ // Fix up any PHI nodes in the successor.
+ for (MachineBasicBlock::iterator MI = Succ->begin(), ME = Succ->end();
+ MI != ME && MI->isPHI(); ++MI)
+ for (unsigned i = 2, e = MI->getNumOperands()+1; i != e; i += 2) {
+ MachineOperand &MO = MI->getOperand(i);
+ if (MO.getMBB() == fromMBB)
+ MO.setMBB(this);
+ }
+ }
}
bool MachineBasicBlock::isSuccessor(const MachineBasicBlock *MBB) const {
Modified: llvm/branches/wendling/eh/lib/CodeGen/MachineFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/MachineFunction.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/MachineFunction.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/MachineFunction.cpp Thu Jul 8 03:14:09 2010
@@ -395,7 +395,7 @@
#ifndef NDEBUG
ViewGraph(this, "mf" + getFunction()->getNameStr());
#else
- errs() << "SelectionDAG::viewGraph is only available in debug builds on "
+ errs() << "MachineFunction::viewCFG is only available in debug builds on "
<< "systems with Graphviz or gv!\n";
#endif // NDEBUG
}
@@ -405,7 +405,7 @@
#ifndef NDEBUG
ViewGraph(this, "mf" + getFunction()->getNameStr(), true);
#else
- errs() << "SelectionDAG::viewGraph is only available in debug builds on "
+ errs() << "MachineFunction::viewCFGOnly is only available in debug builds on "
<< "systems with Graphviz or gv!\n";
#endif // NDEBUG
}
Modified: llvm/branches/wendling/eh/lib/CodeGen/ProcessImplicitDefs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/ProcessImplicitDefs.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/ProcessImplicitDefs.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/ProcessImplicitDefs.cpp Thu Jul 8 03:14:09 2010
@@ -117,10 +117,24 @@
}
}
+ // Eliminate %reg1032:sub<def> = COPY undef.
+ if (MI->isCopy() && MI->getOperand(0).getSubReg()) {
+ MachineOperand &MO = MI->getOperand(1);
+ if (ImpDefRegs.count(MO.getReg())) {
+ if (MO.isKill()) {
+ LiveVariables::VarInfo& vi = lv_->getVarInfo(MO.getReg());
+ vi.removeKill(MI);
+ }
+ MI->eraseFromParent();
+ Changed = true;
+ continue;
+ }
+ }
+
bool ChangedToImpDef = false;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand& MO = MI->getOperand(i);
- if (!MO.isReg() || !MO.isUse() || MO.isUndef())
+ if (!MO.isReg() || (MO.isDef() && !MO.getSubReg()) || MO.isUndef())
continue;
unsigned Reg = MO.getReg();
if (!Reg)
@@ -145,6 +159,12 @@
Changed = true;
MO.setIsUndef();
+ // This is a partial register redef of an implicit def.
+ // Make sure the whole register is defined by the instruction.
+ if (MO.isDef()) {
+ MI->addRegisterDefined(Reg);
+ continue;
+ }
if (MO.isKill() || MI->isRegTiedToDefOperand(i)) {
// Make sure other uses of
for (unsigned j = i+1; j != e; ++j) {
Modified: llvm/branches/wendling/eh/lib/CodeGen/PrologEpilogInserter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/PrologEpilogInserter.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/PrologEpilogInserter.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/PrologEpilogInserter.cpp Thu Jul 8 03:14:09 2010
@@ -885,10 +885,20 @@
// Scavenge a new scratch register
CurrentVirtReg = Reg;
const TargetRegisterClass *RC = Fn.getRegInfo().getRegClass(Reg);
- CurrentScratchReg = RS->FindUnusedReg(RC);
- if (CurrentScratchReg == 0)
+ const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo();
+ BitVector Candidates(TRI->getNumRegs());
+ RS->getRegsAvailable(RC, Candidates);
+
+ // If there are any registers available, use the one that's
+ // unused for the longest after this instruction. That increases
+ // the ability to reuse the value.
+ if (Candidates.any()) {
+ MachineBasicBlock::iterator UMI;
+ CurrentScratchReg = RS->findSurvivorReg(I, Candidates, 25, UMI);
+ } else {
// No register is "free". Scavenge a register.
CurrentScratchReg = RS->scavengeRegister(RC, I, SPAdj);
+ }
PrevValue = Value;
}
Modified: llvm/branches/wendling/eh/lib/CodeGen/RegisterCoalescer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/RegisterCoalescer.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/RegisterCoalescer.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/RegisterCoalescer.cpp Thu Jul 8 03:14:09 2010
@@ -83,7 +83,6 @@
std::swap(SrcSub, DstSub);
flipped_ = true;
}
- origDstReg_ = Dst;
const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
Modified: llvm/branches/wendling/eh/lib/CodeGen/RegisterScavenging.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/RegisterScavenging.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/RegisterScavenging.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/RegisterScavenging.cpp Thu Jul 8 03:14:09 2010
@@ -242,8 +242,18 @@
return 0;
}
+/// getRegsAvailable - Return all available registers in the register class
+/// in Mask.
+void RegScavenger::getRegsAvailable(const TargetRegisterClass *RC,
+ BitVector &Mask) {
+ for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
+ I != E; ++I)
+ if (!isAliasUsed(*I))
+ Mask.set(*I);
+}
+
/// findSurvivorReg - Return the candidate register that is unused for the
-/// longest after MBBI. UseMI is set to the instruction where the search
+/// longest after StargMII. UseMI is set to the instruction where the search
/// stopped.
///
/// No more than InstrLimit instructions are inspected.
Propchange: llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Modified: llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/CMakeLists.txt?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/CMakeLists.txt (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/CMakeLists.txt Thu Jul 8 03:14:09 2010
@@ -1,5 +1,4 @@
add_llvm_library(LLVMSelectionDAG
- CallingConvLower.cpp
DAGCombiner.cpp
FastISel.cpp
FunctionLoweringInfo.cpp
Removed: llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/CallingConvLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/CallingConvLower.cpp?rev=107860&view=auto
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/CallingConvLower.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/CallingConvLower.cpp (removed)
@@ -1,179 +0,0 @@
-//===-- CallingConvLower.cpp - Calling Conventions ------------------------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file implements the CCState class, used for lowering and implementing
-// calling conventions.
-//
-//===----------------------------------------------------------------------===//
-
-#include "llvm/CodeGen/CallingConvLower.h"
-#include "llvm/Support/Debug.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetData.h"
-#include "llvm/Target/TargetMachine.h"
-using namespace llvm;
-
-CCState::CCState(CallingConv::ID CC, bool isVarArg, const TargetMachine &tm,
- SmallVector<CCValAssign, 16> &locs, LLVMContext &C)
- : CallingConv(CC), IsVarArg(isVarArg), TM(tm),
- TRI(*TM.getRegisterInfo()), Locs(locs), Context(C) {
- // No stack is used.
- StackOffset = 0;
-
- UsedRegs.resize((TRI.getNumRegs()+31)/32);
-}
-
-// HandleByVal - Allocate a stack slot large enough to pass an argument by
-// value. The size and alignment information of the argument is encoded in its
-// parameter attribute.
-void CCState::HandleByVal(unsigned ValNo, EVT ValVT,
- EVT LocVT, CCValAssign::LocInfo LocInfo,
- int MinSize, int MinAlign,
- ISD::ArgFlagsTy ArgFlags) {
- unsigned Align = ArgFlags.getByValAlign();
- unsigned Size = ArgFlags.getByValSize();
- if (MinSize > (int)Size)
- Size = MinSize;
- if (MinAlign > (int)Align)
- Align = MinAlign;
- unsigned Offset = AllocateStack(Size, Align);
-
- addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
-}
-
-/// MarkAllocated - Mark a register and all of its aliases as allocated.
-void CCState::MarkAllocated(unsigned Reg) {
- UsedRegs[Reg/32] |= 1 << (Reg&31);
-
- if (const unsigned *RegAliases = TRI.getAliasSet(Reg))
- for (; (Reg = *RegAliases); ++RegAliases)
- UsedRegs[Reg/32] |= 1 << (Reg&31);
-}
-
-/// AnalyzeFormalArguments - Analyze an array of argument values,
-/// incorporating info about the formals into this state.
-void
-CCState::AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
- CCAssignFn Fn) {
- unsigned NumArgs = Ins.size();
-
- for (unsigned i = 0; i != NumArgs; ++i) {
- EVT ArgVT = Ins[i].VT;
- ISD::ArgFlagsTy ArgFlags = Ins[i].Flags;
- if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
-#ifndef NDEBUG
- dbgs() << "Formal argument #" << i << " has unhandled type "
- << ArgVT.getEVTString();
-#endif
- llvm_unreachable(0);
- }
- }
-}
-
-/// CheckReturn - Analyze the return values of a function, returning true if
-/// the return can be performed without sret-demotion, and false otherwise.
-bool CCState::CheckReturn(const SmallVectorImpl<EVT> &OutTys,
- const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
- CCAssignFn Fn) {
- // Determine which register each value should be copied into.
- for (unsigned i = 0, e = OutTys.size(); i != e; ++i) {
- EVT VT = OutTys[i];
- ISD::ArgFlagsTy ArgFlags = ArgsFlags[i];
- if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this))
- return false;
- }
- return true;
-}
-
-/// AnalyzeReturn - Analyze the returned values of a return,
-/// incorporating info about the result values into this state.
-void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
- CCAssignFn Fn) {
- // Determine which register each value should be copied into.
- for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
- EVT VT = Outs[i].Val.getValueType();
- ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
- if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) {
-#ifndef NDEBUG
- dbgs() << "Return operand #" << i << " has unhandled type "
- << VT.getEVTString();
-#endif
- llvm_unreachable(0);
- }
- }
-}
-
-
-/// AnalyzeCallOperands - Analyze the outgoing arguments to a call,
-/// incorporating info about the passed values into this state.
-void CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
- CCAssignFn Fn) {
- unsigned NumOps = Outs.size();
- for (unsigned i = 0; i != NumOps; ++i) {
- EVT ArgVT = Outs[i].Val.getValueType();
- ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
- if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
-#ifndef NDEBUG
- dbgs() << "Call operand #" << i << " has unhandled type "
- << ArgVT.getEVTString();
-#endif
- llvm_unreachable(0);
- }
- }
-}
-
-/// AnalyzeCallOperands - Same as above except it takes vectors of types
-/// and argument flags.
-void CCState::AnalyzeCallOperands(SmallVectorImpl<EVT> &ArgVTs,
- SmallVectorImpl<ISD::ArgFlagsTy> &Flags,
- CCAssignFn Fn) {
- unsigned NumOps = ArgVTs.size();
- for (unsigned i = 0; i != NumOps; ++i) {
- EVT ArgVT = ArgVTs[i];
- ISD::ArgFlagsTy ArgFlags = Flags[i];
- if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
-#ifndef NDEBUG
- dbgs() << "Call operand #" << i << " has unhandled type "
- << ArgVT.getEVTString();
-#endif
- llvm_unreachable(0);
- }
- }
-}
-
-/// AnalyzeCallResult - Analyze the return values of a call,
-/// incorporating info about the passed values into this state.
-void CCState::AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
- CCAssignFn Fn) {
- for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
- EVT VT = Ins[i].VT;
- ISD::ArgFlagsTy Flags = Ins[i].Flags;
- if (Fn(i, VT, VT, CCValAssign::Full, Flags, *this)) {
-#ifndef NDEBUG
- dbgs() << "Call result #" << i << " has unhandled type "
- << VT.getEVTString();
-#endif
- llvm_unreachable(0);
- }
- }
-}
-
-/// AnalyzeCallResult - Same as above except it's specialized for calls which
-/// produce a single value.
-void CCState::AnalyzeCallResult(EVT VT, CCAssignFn Fn) {
- if (Fn(0, VT, VT, CCValAssign::Full, ISD::ArgFlagsTy(), *this)) {
-#ifndef NDEBUG
- dbgs() << "Call result has unhandled type "
- << VT.getEVTString();
-#endif
- llvm_unreachable(0);
- }
-}
Modified: llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Jul 8 03:14:09 2010
@@ -669,7 +669,7 @@
? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD : ISD::EXTLOAD)
: LD->getExtensionType();
Replace = true;
- return DAG.getExtLoad(ExtType, dl, PVT,
+ return DAG.getExtLoad(ExtType, PVT, dl,
LD->getChain(), LD->getBasePtr(),
LD->getSrcValue(), LD->getSrcValueOffset(),
MemVT, LD->isVolatile(),
@@ -891,7 +891,7 @@
ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD : ISD::EXTLOAD)
: LD->getExtensionType();
- SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT,
+ SDValue NewLD = DAG.getExtLoad(ExtType, PVT, dl,
LD->getChain(), LD->getBasePtr(),
LD->getSrcValue(), LD->getSrcValueOffset(),
MemVT, LD->isVolatile(),
@@ -1315,7 +1315,7 @@
if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
GA->getOpcode() == ISD::GlobalAddress)
- return DAG.getGlobalAddress(GA->getGlobal(), VT,
+ return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
GA->getOffset() +
(uint64_t)N1C->getSExtValue());
// fold ((c1-A)+c2) -> (c1+c2)-A
@@ -1552,7 +1552,7 @@
if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
// fold (sub Sym, c) -> Sym-c
if (N1C && GA->getOpcode() == ISD::GlobalAddress)
- return DAG.getGlobalAddress(GA->getGlobal(), VT,
+ return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
GA->getOffset() -
(uint64_t)N1C->getSExtValue());
// fold (sub Sym+c1, Sym+c2) -> c1-c2
@@ -2198,7 +2198,7 @@
BitWidth - MemVT.getScalarType().getSizeInBits())) &&
((!LegalOperations && !LN0->isVolatile()) ||
TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
- SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
+ SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getDebugLoc(),
LN0->getChain(), LN0->getBasePtr(),
LN0->getSrcValue(),
LN0->getSrcValueOffset(), MemVT,
@@ -2221,7 +2221,7 @@
BitWidth - MemVT.getScalarType().getSizeInBits())) &&
((!LegalOperations && !LN0->isVolatile()) ||
TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
- SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
+ SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getDebugLoc(),
LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
LN0->getSrcValueOffset(), MemVT,
@@ -2255,7 +2255,7 @@
EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
SDValue NewLoad =
- DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
+ DAG.getExtLoad(ISD::ZEXTLOAD, LoadResultTy, LN0->getDebugLoc(),
LN0->getChain(), LN0->getBasePtr(),
LN0->getSrcValue(), LN0->getSrcValueOffset(),
ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
@@ -2291,7 +2291,7 @@
EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
SDValue Load =
- DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
+ DAG.getExtLoad(ISD::ZEXTLOAD, LoadResultTy, LN0->getDebugLoc(),
LN0->getChain(), NewPtr,
LN0->getSrcValue(), LN0->getSrcValueOffset(),
ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
@@ -3503,7 +3503,7 @@
DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
if (DoXform) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
+ SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N->getDebugLoc(),
LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
LN0->getSrcValueOffset(),
@@ -3547,7 +3547,7 @@
EVT MemVT = LN0->getMemoryVT();
if ((!LegalOperations && !LN0->isVolatile()) ||
TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) {
- SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
+ SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N->getDebugLoc(),
LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
LN0->getSrcValueOffset(), MemVT,
@@ -3692,7 +3692,7 @@
DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
if (DoXform) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
+ SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N->getDebugLoc(),
LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
LN0->getSrcValueOffset(),
@@ -3736,7 +3736,7 @@
EVT MemVT = LN0->getMemoryVT();
if ((!LegalOperations && !LN0->isVolatile()) ||
TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) {
- SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
+ SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N->getDebugLoc(),
LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
LN0->getSrcValueOffset(), MemVT,
@@ -3894,7 +3894,7 @@
DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
if (DoXform) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
+ SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N->getDebugLoc(),
LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
LN0->getSrcValueOffset(),
@@ -3938,8 +3938,9 @@
N0.hasOneUse()) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
EVT MemVT = LN0->getMemoryVT();
- SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(),
- VT, LN0->getChain(), LN0->getBasePtr(),
+ SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
+ N->getDebugLoc(),
+ LN0->getChain(), LN0->getBasePtr(),
LN0->getSrcValue(),
LN0->getSrcValueOffset(), MemVT,
LN0->isVolatile(), LN0->isNonTemporal(),
@@ -4108,7 +4109,7 @@
? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
LN0->isVolatile(), LN0->isNonTemporal(), NewAlign)
- : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr,
+ : DAG.getExtLoad(ExtType, VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
NewAlign);
@@ -4195,7 +4196,7 @@
((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
+ SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N->getDebugLoc(),
LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
LN0->getSrcValueOffset(), EVT,
@@ -4212,7 +4213,7 @@
((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
+ SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N->getDebugLoc(),
LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
LN0->getSrcValueOffset(), EVT,
@@ -4975,7 +4976,7 @@
((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
+ SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N->getDebugLoc(),
LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
LN0->getSrcValueOffset(),
@@ -5559,8 +5560,8 @@
if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
if (Align > LD->getAlignment())
- return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
- LD->getValueType(0),
+ return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0),
+ N->getDebugLoc(),
Chain, Ptr, LD->getSrcValue(),
LD->getSrcValueOffset(), LD->getMemoryVT(),
LD->isVolatile(), LD->isNonTemporal(), Align);
@@ -5583,8 +5584,8 @@
LD->isVolatile(), LD->isNonTemporal(),
LD->getAlignment());
} else {
- ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(),
- LD->getValueType(0),
+ ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0),
+ LD->getDebugLoc(),
BetterChain, Ptr, LD->getSrcValue(),
LD->getSrcValueOffset(),
LD->getMemoryVT(),
@@ -6649,8 +6650,8 @@
LLD->getAlignment());
} else {
Load = DAG.getExtLoad(LLD->getExtensionType(),
- TheSelect->getDebugLoc(),
TheSelect->getValueType(0),
+ TheSelect->getDebugLoc(),
LLD->getChain(), Addr, 0, 0,
LLD->getMemoryVT(),
LLD->isVolatile(),
Modified: llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/FastISel.cpp Thu Jul 8 03:14:09 2010
@@ -44,6 +44,7 @@
#include "llvm/Instructions.h"
#include "llvm/IntrinsicInst.h"
#include "llvm/CodeGen/FastISel.h"
+#include "llvm/CodeGen/FunctionLoweringInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
@@ -54,7 +55,6 @@
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/ErrorHandling.h"
-#include "FunctionLoweringInfo.h"
using namespace llvm;
bool FastISel::hasTrivialKill(const Value *V) const {
@@ -100,8 +100,8 @@
// cache values defined by Instructions across blocks, and other values
// only locally. This is because Instructions already have the SSA
// def-dominates-use requirement enforced.
- DenseMap<const Value *, unsigned>::iterator I = ValueMap.find(V);
- if (I != ValueMap.end())
+ DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(V);
+ if (I != FuncInfo.ValueMap.end())
return I->second;
unsigned Reg = LocalValueMap[V];
if (Reg != 0)
@@ -112,7 +112,7 @@
if (IsBottomUp) {
Reg = createResultReg(TLI.getRegClassFor(VT));
if (isa<Instruction>(V))
- ValueMap[V] = Reg;
+ FuncInfo.ValueMap[V] = Reg;
else
LocalValueMap[V] = Reg;
return Reg;
@@ -189,8 +189,8 @@
// cache values defined by Instructions across blocks, and other values
// only locally. This is because Instructions already have the SSA
// def-dominates-use requirement enforced.
- DenseMap<const Value *, unsigned>::iterator I = ValueMap.find(V);
- if (I != ValueMap.end())
+ DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(V);
+ if (I != FuncInfo.ValueMap.end())
return I->second;
return LocalValueMap[V];
}
@@ -207,7 +207,7 @@
return Reg;
}
- unsigned &AssignedReg = ValueMap[I];
+ unsigned &AssignedReg = FuncInfo.ValueMap[I];
if (AssignedReg == 0)
AssignedReg = Reg;
else if (Reg != AssignedReg) {
@@ -400,7 +400,7 @@
case Intrinsic::dbg_declare: {
const DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
if (!DIVariable(DI->getVariable()).Verify() ||
- !MF.getMMI().hasDebugInfo())
+ !FuncInfo.MF->getMMI().hasDebugInfo())
return true;
const Value *Address = DI->getAddress();
@@ -414,11 +414,12 @@
// those are handled in SelectionDAGBuilder.
if (AI) {
DenseMap<const AllocaInst*, int>::iterator SI =
- StaticAllocaMap.find(AI);
- if (SI == StaticAllocaMap.end()) break; // VLAs.
+ FuncInfo.StaticAllocaMap.find(AI);
+ if (SI == FuncInfo.StaticAllocaMap.end()) break; // VLAs.
int FI = SI->second;
if (!DI->getDebugLoc().isUnknown())
- MF.getMMI().setVariableDbgInfo(DI->getVariable(), FI, DI->getDebugLoc());
+ FuncInfo.MF->getMMI().setVariableDbgInfo(DI->getVariable(),
+ FI, DI->getDebugLoc());
} else
// Building the map above is target independent. Generating DBG_VALUE
// inline is target dependent; do this now.
@@ -457,7 +458,7 @@
// Add the filter IDs to the machine function.
const IntrinsicInst *II = cast<IntrinsicInst>(I);
for (unsigned i = 0, e = II->getNumArgOperands(); i != e; ++i)
- MF.addFilterID(II->getArgOperand(i)->stripPointerCasts());
+ FuncInfo.MF->addFilterID(II->getArgOperand(i)->stripPointerCasts());
return true;
}
@@ -487,10 +488,10 @@
default: break;
case TargetLowering::Expand: {
if (MBB->isLandingPad())
- AddCatchInfo(*cast<CallInst>(I), &MF.getMMI(), MBB);
+ AddCatchInfo(*cast<CallInst>(I), &FuncInfo.MF->getMMI(), MBB);
else {
#ifndef NDEBUG
- CatchInfoLost.insert(cast<CallInst>(I));
+ FuncInfo.CatchInfoLost.insert(cast<CallInst>(I));
#endif
// FIXME: Mark exception selector register as live in. Hack for PR1508.
unsigned Reg = TLI.getExceptionSelectorRegister();
@@ -799,7 +800,7 @@
if (BI->isUnconditional()) {
const BasicBlock *LLVMSucc = BI->getSuccessor(0);
- MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
+ MachineBasicBlock *MSucc = FuncInfo.MBBMap[LLVMSucc];
FastEmitBranch(MSucc, BI->getDebugLoc());
return true;
}
@@ -815,7 +816,7 @@
case Instruction::Alloca:
// FunctionLowering has the static-sized case covered.
- if (StaticAllocaMap.count(cast<AllocaInst>(I)))
+ if (FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(I)))
return true;
// Dynamic-sized alloca is not handled yet.
@@ -861,28 +862,13 @@
}
}
-FastISel::FastISel(MachineFunction &mf,
- DenseMap<const Value *, unsigned> &vm,
- DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
- DenseMap<const AllocaInst *, int> &am,
- std::vector<std::pair<MachineInstr*, unsigned> > &pn
-#ifndef NDEBUG
- , SmallSet<const Instruction *, 8> &cil
-#endif
- )
+FastISel::FastISel(FunctionLoweringInfo &funcInfo)
: MBB(0),
- ValueMap(vm),
- MBBMap(bm),
- StaticAllocaMap(am),
- PHINodesToUpdate(pn),
-#ifndef NDEBUG
- CatchInfoLost(cil),
-#endif
- MF(mf),
- MRI(MF.getRegInfo()),
- MFI(*MF.getFrameInfo()),
- MCP(*MF.getConstantPool()),
- TM(MF.getTarget()),
+ FuncInfo(funcInfo),
+ MRI(FuncInfo.MF->getRegInfo()),
+ MFI(*FuncInfo.MF->getFrameInfo()),
+ MCP(*FuncInfo.MF->getConstantPool()),
+ TM(FuncInfo.MF->getTarget()),
TD(*TM.getTargetData()),
TII(*TM.getInstrInfo()),
TLI(*TM.getTargetLowering()),
@@ -1192,14 +1178,14 @@
const TerminatorInst *TI = LLVMBB->getTerminator();
SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
- unsigned OrigNumPHINodesToUpdate = PHINodesToUpdate.size();
+ unsigned OrigNumPHINodesToUpdate = FuncInfo.PHINodesToUpdate.size();
// Check successor nodes' PHI nodes that expect a constant to be available
// from this block.
for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
const BasicBlock *SuccBB = TI->getSuccessor(succ);
if (!isa<PHINode>(SuccBB->begin())) continue;
- MachineBasicBlock *SuccMBB = MBBMap[SuccBB];
+ MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
// If this terminator has multiple identical successors (common for
// switches), only handle each succ once.
@@ -1228,7 +1214,7 @@
if (VT == MVT::i1)
VT = TLI.getTypeToTransformTo(LLVMBB->getContext(), VT);
else {
- PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
+ FuncInfo.PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
return false;
}
}
@@ -1243,10 +1229,10 @@
unsigned Reg = getRegForValue(PHIOp);
if (Reg == 0) {
- PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
+ FuncInfo.PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
return false;
}
- PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));
+ FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));
DL = DebugLoc();
}
}
Modified: llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp Thu Jul 8 03:14:09 2010
@@ -13,7 +13,7 @@
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "function-lowering-info"
-#include "FunctionLoweringInfo.h"
+#include "llvm/CodeGen/FunctionLoweringInfo.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Function.h"
#include "llvm/Instructions.h"
Removed: llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.h?rev=107860&view=auto
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.h (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.h (removed)
@@ -1,144 +0,0 @@
-//===-- FunctionLoweringInfo.h - Lower functions from LLVM IR to CodeGen --===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This implements routines for translating functions from LLVM IR into
-// Machine IR.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef FUNCTIONLOWERINGINFO_H
-#define FUNCTIONLOWERINGINFO_H
-
-#include "llvm/InlineAsm.h"
-#include "llvm/Instructions.h"
-#include "llvm/ADT/APInt.h"
-#include "llvm/ADT/DenseMap.h"
-#include "llvm/ADT/SmallVector.h"
-#ifndef NDEBUG
-#include "llvm/ADT/SmallSet.h"
-#endif
-#include "llvm/CodeGen/ValueTypes.h"
-#include "llvm/CodeGen/ISDOpcodes.h"
-#include "llvm/Support/CallSite.h"
-#include <vector>
-
-namespace llvm {
-
-class AllocaInst;
-class BasicBlock;
-class CallInst;
-class Function;
-class GlobalVariable;
-class Instruction;
-class MachineInstr;
-class MachineBasicBlock;
-class MachineFunction;
-class MachineModuleInfo;
-class MachineRegisterInfo;
-class TargetLowering;
-class Value;
-
-//===--------------------------------------------------------------------===//
-/// FunctionLoweringInfo - This contains information that is global to a
-/// function that is used when lowering a region of the function.
-///
-class FunctionLoweringInfo {
-public:
- const TargetLowering &TLI;
- const Function *Fn;
- MachineFunction *MF;
- MachineRegisterInfo *RegInfo;
-
- /// CanLowerReturn - true iff the function's return value can be lowered to
- /// registers.
- bool CanLowerReturn;
-
- /// DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg
- /// allocated to hold a pointer to the hidden sret parameter.
- unsigned DemoteRegister;
-
- /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
- DenseMap<const BasicBlock*, MachineBasicBlock *> MBBMap;
-
- /// ValueMap - Since we emit code for the function a basic block at a time,
- /// we must remember which virtual registers hold the values for
- /// cross-basic-block values.
- DenseMap<const Value*, unsigned> ValueMap;
-
- /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
- /// the entry block. This allows the allocas to be efficiently referenced
- /// anywhere in the function.
- DenseMap<const AllocaInst*, int> StaticAllocaMap;
-
- /// ArgDbgValues - A list of DBG_VALUE instructions created during isel for
- /// function arguments that are inserted after scheduling is completed.
- SmallVector<MachineInstr*, 8> ArgDbgValues;
-
-#ifndef NDEBUG
- SmallSet<const Instruction *, 8> CatchInfoLost;
- SmallSet<const Instruction *, 8> CatchInfoFound;
-#endif
-
- struct LiveOutInfo {
- unsigned NumSignBits;
- APInt KnownOne, KnownZero;
- LiveOutInfo() : NumSignBits(0), KnownOne(1, 0), KnownZero(1, 0) {}
- };
-
- /// LiveOutRegInfo - Information about live out vregs, indexed by their
- /// register number offset by 'FirstVirtualRegister'.
- std::vector<LiveOutInfo> LiveOutRegInfo;
-
- /// PHINodesToUpdate - A list of phi instructions whose operand list will
- /// be updated after processing the current basic block.
- /// TODO: This isn't per-function state, it's per-basic-block state. But
- /// there's no other convenient place for it to live right now.
- std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
-
- explicit FunctionLoweringInfo(const TargetLowering &TLI);
-
- /// set - Initialize this FunctionLoweringInfo with the given Function
- /// and its associated MachineFunction.
- ///
- void set(const Function &Fn, MachineFunction &MF);
-
- /// clear - Clear out all the function-specific state. This returns this
- /// FunctionLoweringInfo to an empty state, ready to be used for a
- /// different function.
- void clear();
-
- /// isExportedInst - Return true if the specified value is an instruction
- /// exported from its block.
- bool isExportedInst(const Value *V) {
- return ValueMap.count(V);
- }
-
- unsigned CreateReg(EVT VT);
-
- unsigned CreateRegs(const Type *Ty);
-
- unsigned InitializeRegForValue(const Value *V) {
- unsigned &R = ValueMap[V];
- assert(R == 0 && "Already initialized this value register!");
- return R = CreateRegs(V->getType());
- }
-};
-
-/// AddCatchInfo - Extract the personality and type infos from an eh.selector
-/// call, and add them to the specified machine basic block.
-void AddCatchInfo(const CallInst &I,
- MachineModuleInfo *MMI, MachineBasicBlock *MBB);
-
-/// CopyCatchInfo - Copy catch information from DestBB to SrcBB.
-void CopyCatchInfo(const BasicBlock *SrcBB, const BasicBlock *DestBB,
- MachineModuleInfo *MMI, FunctionLoweringInfo &FLI);
-
-} // end namespace llvm
-
-#endif
Modified: llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/InstrEmitter.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Thu Jul 8 03:14:09 2010
@@ -604,9 +604,10 @@
} else if (SD->getKind() == SDDbgValue::CONST) {
const Value *V = SD->getConst();
if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
- // FIXME: SDDbgValues aren't updated with legalization, so it's possible
- // to have i128 values in them at this point. As a crude workaround, just
- // drop the debug info if this happens.
+ // FIXME: SDDbgValue constants aren't updated with legalization, so it's
+ // possible to have i128 constants in them at this point. Dwarf writer
+ // does not handle i128 constants at the moment so, as a crude workaround,
+ // just drop the debug info if this happens.
if (!CI->getValue().isSignedIntN(64))
MIB.addReg(0U);
else
@@ -723,6 +724,11 @@
MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(),
cast<MachineSDNode>(Node)->memoperands_end());
+ // Insert the instruction into position in the block. This needs to
+ // happen before any custom inserter hook is called so that the
+ // hook knows where in the block to insert the replacement code.
+ MBB->insert(InsertPos, MI);
+
if (II.usesCustomInsertionHook()) {
// Insert this instruction into the basic block using a target
// specific inserter which may returns a new basic block.
@@ -731,8 +737,6 @@
return;
}
- MBB->insert(InsertPos, MI);
-
// Additional results must be an physical register def.
if (HasPhysRegOuts) {
for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
Modified: llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Jul 8 03:14:09 2010
@@ -378,8 +378,8 @@
SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
if (Extend)
- return DAG.getExtLoad(ISD::EXTLOAD, dl,
- OrigVT, DAG.getEntryNode(),
+ return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, dl,
+ DAG.getEntryNode(),
CPIdx, PseudoSourceValue::getConstantPool(),
0, VT, false, false, Alignment);
return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
@@ -456,7 +456,7 @@
8 * (StoredBytes - Offset));
// Load from the stack slot.
- SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
+ SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, dl, Store, StackPtr,
NULL, 0, MemVT, false, false, 0);
Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
@@ -558,7 +558,7 @@
// The last copy may be partial. Do an extending load.
EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
8 * (LoadedBytes - Offset));
- SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
+ SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, dl, Chain, Ptr,
LD->getSrcValue(), SVOffset + Offset,
MemVT, LD->isVolatile(),
LD->isNonTemporal(),
@@ -574,7 +574,7 @@
Stores.size());
// Finally, perform the original load only redirected to the stack slot.
- Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
+ Load = DAG.getExtLoad(LD->getExtensionType(), VT, dl, TF, StackBase,
NULL, 0, LoadedVT, false, false, 0);
// Callers expect a MERGE_VALUES node.
@@ -603,21 +603,21 @@
// Load the value in two parts
SDValue Lo, Hi;
if (TLI.isLittleEndian()) {
- Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
+ Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, dl, Chain, Ptr, LD->getSrcValue(),
SVOffset, NewLoadedVT, LD->isVolatile(),
LD->isNonTemporal(), Alignment);
Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
DAG.getConstant(IncrementSize, TLI.getPointerTy()));
- Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
+ Hi = DAG.getExtLoad(HiExtType, VT, dl, Chain, Ptr, LD->getSrcValue(),
SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
} else {
- Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
+ Hi = DAG.getExtLoad(HiExtType, VT, dl, Chain, Ptr, LD->getSrcValue(),
SVOffset, NewLoadedVT, LD->isVolatile(),
LD->isNonTemporal(), Alignment);
Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
DAG.getConstant(IncrementSize, TLI.getPointerTy()));
- Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
+ Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, dl, Chain, Ptr, LD->getSrcValue(),
SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
}
@@ -859,6 +859,8 @@
case ISD::MERGE_VALUES:
case ISD::EH_RETURN:
case ISD::FRAME_TO_ARGS_OFFSET:
+ case ISD::EH_SJLJ_SETJMP:
+ case ISD::EH_SJLJ_LONGJMP:
// These operations lie about being legal: when they claim to be legal,
// they should actually be expanded.
Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
@@ -868,8 +870,6 @@
case ISD::TRAMPOLINE:
case ISD::FRAMEADDR:
case ISD::RETURNADDR:
- case ISD::EH_SJLJ_SETJMP:
- case ISD::EH_SJLJ_LONGJMP:
// These operations lie about being legal: when they claim to be legal,
// they should actually be custom-lowered.
Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
@@ -1181,7 +1181,7 @@
ISD::LoadExtType NewExtType =
ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
- Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
+ Result = DAG.getExtLoad(NewExtType, Node->getValueType(0), dl,
Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
NVT, isVolatile, isNonTemporal, Alignment);
@@ -1217,8 +1217,8 @@
if (TLI.isLittleEndian()) {
// EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD at +2:i8, 16)
// Load the bottom RoundWidth bits.
- Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
- Node->getValueType(0), Tmp1, Tmp2,
+ Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), dl,
+ Tmp1, Tmp2,
LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
isNonTemporal, Alignment);
@@ -1226,7 +1226,7 @@
IncrementSize = RoundWidth / 8;
Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
DAG.getIntPtrConstant(IncrementSize));
- Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
+ Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), dl, Tmp1, Tmp2,
LD->getSrcValue(), SVOffset + IncrementSize,
ExtraVT, isVolatile, isNonTemporal,
MinAlign(Alignment, IncrementSize));
@@ -1246,7 +1246,7 @@
// Big endian - avoid unaligned loads.
// EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD at +2:i8
// Load the top RoundWidth bits.
- Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
+ Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), dl, Tmp1, Tmp2,
LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
isNonTemporal, Alignment);
@@ -1254,8 +1254,8 @@
IncrementSize = RoundWidth / 8;
Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
DAG.getIntPtrConstant(IncrementSize));
- Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
- Node->getValueType(0), Tmp1, Tmp2,
+ Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
+ Node->getValueType(0), dl, Tmp1, Tmp2,
LD->getSrcValue(), SVOffset + IncrementSize,
ExtraVT, isVolatile, isNonTemporal,
MinAlign(Alignment, IncrementSize));
@@ -1333,7 +1333,7 @@
"EXTLOAD should always be supported!");
// Turn the unsupported load into an EXTLOAD followed by an explicit
// zero/sign extend inreg.
- Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
+ Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), dl,
Tmp1, Tmp2, LD->getSrcValue(),
LD->getSrcValueOffset(), SrcVT,
LD->isVolatile(), LD->isNonTemporal(),
@@ -1555,7 +1555,7 @@
return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0,
false, false, 0);
else
- return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
+ return DAG.getExtLoad(ISD::EXTLOAD, Op.getValueType(), dl, Ch, StackPtr,
NULL, 0, Vec.getValueType().getVectorElementType(),
false, false, 0);
}
@@ -1787,7 +1787,7 @@
DestAlign);
assert(SlotSize < DestSize && "Unknown extension!");
- return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT,
+ return DAG.getExtLoad(ISD::EXTLOAD, DestVT, dl, Store, FIPtr, SV, 0, SlotVT,
false, false, DestAlign);
}
@@ -2185,7 +2185,7 @@
false, false, Alignment);
else {
FudgeInReg =
- LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
+ LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, dl,
DAG.getEntryNode(), CPIdx,
PseudoSourceValue::getConstantPool(), 0,
MVT::f32, false, false, Alignment));
@@ -2507,6 +2507,11 @@
case ISD::EH_LABEL:
case ISD::PREFETCH:
case ISD::VAEND:
+ case ISD::EH_SJLJ_LONGJMP:
+ Results.push_back(Node->getOperand(0));
+ break;
+ case ISD::EH_SJLJ_SETJMP:
+ Results.push_back(DAG.getConstant(0, MVT::i32));
Results.push_back(Node->getOperand(0));
break;
case ISD::MEMBARRIER: {
@@ -3150,7 +3155,7 @@
SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
- SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
+ SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, PTy, dl, Chain, Addr,
PseudoSourceValue::getJumpTable(), 0, MemVT,
false, false, 0);
Addr = LD;
Modified: llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp Thu Jul 8 03:14:09 2010
@@ -453,8 +453,8 @@
SDValue NewL;
if (L->getExtensionType() == ISD::NON_EXTLOAD) {
- NewL = DAG.getLoad(L->getAddressingMode(), dl, L->getExtensionType(),
- NVT, L->getChain(), L->getBasePtr(), L->getOffset(),
+ NewL = DAG.getLoad(L->getAddressingMode(), L->getExtensionType(),
+ NVT, dl, L->getChain(), L->getBasePtr(), L->getOffset(),
L->getSrcValue(), L->getSrcValueOffset(), NVT,
L->isVolatile(), L->isNonTemporal(), L->getAlignment());
// Legalized the chain result - switch anything that used the old chain to
@@ -464,8 +464,8 @@
}
// Do a non-extending load followed by FP_EXTEND.
- NewL = DAG.getLoad(L->getAddressingMode(), dl, ISD::NON_EXTLOAD,
- L->getMemoryVT(), L->getChain(),
+ NewL = DAG.getLoad(L->getAddressingMode(), ISD::NON_EXTLOAD,
+ L->getMemoryVT(), dl, L->getChain(),
L->getBasePtr(), L->getOffset(),
L->getSrcValue(), L->getSrcValueOffset(),
L->getMemoryVT(), L->isVolatile(),
@@ -1109,7 +1109,7 @@
assert(NVT.isByteSized() && "Expanded type not byte sized!");
assert(LD->getMemoryVT().bitsLE(NVT) && "Float type not round?");
- Hi = DAG.getExtLoad(LD->getExtensionType(), dl, NVT, Chain, Ptr,
+ Hi = DAG.getExtLoad(LD->getExtensionType(), NVT, dl, Chain, Ptr,
LD->getSrcValue(), LD->getSrcValueOffset(),
LD->getMemoryVT(), LD->isVolatile(),
LD->isNonTemporal(), LD->getAlignment());
Modified: llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Thu Jul 8 03:14:09 2010
@@ -369,7 +369,7 @@
ISD::LoadExtType ExtType =
ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
DebugLoc dl = N->getDebugLoc();
- SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
+ SDValue Res = DAG.getExtLoad(ExtType, NVT, dl, N->getChain(), N->getBasePtr(),
N->getSrcValue(), N->getSrcValueOffset(),
N->getMemoryVT(), N->isVolatile(),
N->isNonTemporal(), N->getAlignment());
@@ -1532,7 +1532,7 @@
if (N->getMemoryVT().bitsLE(NVT)) {
EVT MemVT = N->getMemoryVT();
- Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
+ Lo = DAG.getExtLoad(ExtType, NVT, dl, Ch, Ptr, N->getSrcValue(), SVOffset,
MemVT, isVolatile, isNonTemporal, Alignment);
// Remember the chain.
@@ -1565,7 +1565,7 @@
unsigned IncrementSize = NVT.getSizeInBits()/8;
Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
DAG.getIntPtrConstant(IncrementSize));
- Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(),
+ Hi = DAG.getExtLoad(ExtType, NVT, dl, Ch, Ptr, N->getSrcValue(),
SVOffset+IncrementSize, NEVT,
isVolatile, isNonTemporal,
MinAlign(Alignment, IncrementSize));
@@ -1583,7 +1583,7 @@
unsigned ExcessBits = (EBytes - IncrementSize)*8;
// Load both the high bits and maybe some of the low bits.
- Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
+ Hi = DAG.getExtLoad(ExtType, NVT, dl, Ch, Ptr, N->getSrcValue(), SVOffset,
EVT::getIntegerVT(*DAG.getContext(),
MemVT.getSizeInBits() - ExcessBits),
isVolatile, isNonTemporal, Alignment);
@@ -1592,7 +1592,7 @@
Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
DAG.getIntPtrConstant(IncrementSize));
// Load the rest of the low bits.
- Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr, N->getSrcValue(),
+ Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, dl, Ch, Ptr, N->getSrcValue(),
SVOffset+IncrementSize,
EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
isVolatile, isNonTemporal,
@@ -2455,7 +2455,7 @@
// Load the value out, extending it from f32 to the destination float type.
// FIXME: Avoid the extend by constructing the right constant pool?
- SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
+ SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, DstVT, dl, DAG.getEntryNode(),
FudgePtr, NULL, 0, MVT::f32,
false, false, Alignment);
return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
Modified: llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Thu Jul 8 03:14:09 2010
@@ -165,9 +165,10 @@
SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
assert(N->isUnindexed() && "Indexed vector load?");
- SDValue Result = DAG.getLoad(ISD::UNINDEXED, N->getDebugLoc(),
+ SDValue Result = DAG.getLoad(ISD::UNINDEXED,
N->getExtensionType(),
N->getValueType(0).getVectorElementType(),
+ N->getDebugLoc(),
N->getChain(), N->getBasePtr(),
DAG.getUNDEF(N->getBasePtr().getValueType()),
N->getSrcValue(), N->getSrcValueOffset(),
@@ -760,14 +761,14 @@
EVT LoMemVT, HiMemVT;
GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
- Lo = DAG.getLoad(ISD::UNINDEXED, dl, ExtType, LoVT, Ch, Ptr, Offset,
+ Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
SV, SVOffset, LoMemVT, isVolatile, isNonTemporal, Alignment);
unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
DAG.getIntPtrConstant(IncrementSize));
SVOffset += IncrementSize;
- Hi = DAG.getLoad(ISD::UNINDEXED, dl, ExtType, HiVT, Ch, Ptr, Offset,
+ Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
SV, SVOffset, HiMemVT, isVolatile, isNonTemporal, Alignment);
// Build a factor node to remember that this load is independent of the
@@ -1105,7 +1106,7 @@
// Load back the required element.
StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
- return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
+ return DAG.getExtLoad(ISD::EXTLOAD, N->getValueType(0), dl, Store, StackPtr,
SV, 0, EltVT, false, false, 0);
}
@@ -2351,14 +2352,14 @@
unsigned WidenNumElts = WidenVT.getVectorNumElements();
SmallVector<SDValue, 16> Ops(WidenNumElts);
unsigned Increment = LdEltVT.getSizeInBits() / 8;
- Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr, SV, SVOffset,
+ Ops[0] = DAG.getExtLoad(ExtType, EltVT, dl, Chain, BasePtr, SV, SVOffset,
LdEltVT, isVolatile, isNonTemporal, Align);
LdChain.push_back(Ops[0].getValue(1));
unsigned i = 0, Offset = Increment;
for (i=1; i < NumElts; ++i, Offset += Increment) {
SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
BasePtr, DAG.getIntPtrConstant(Offset));
- Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr, SV,
+ Ops[i] = DAG.getExtLoad(ExtType, EltVT, dl, Chain, NewBasePtr, SV,
SVOffset + Offset, LdEltVT, isVolatile,
isNonTemporal, Align);
LdChain.push_back(Ops[i].getValue(1));
Modified: llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Jul 8 03:14:09 2010
@@ -975,7 +975,7 @@
}
}
-SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV,
+SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV, DebugLoc DL,
EVT VT, int64_t Offset,
bool isTargetGA,
unsigned char TargetFlags) {
@@ -1010,7 +1010,7 @@
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
return SDValue(E, 0);
- SDNode *N = new (NodeAllocator) GlobalAddressSDNode(Opc, GV, VT,
+ SDNode *N = new (NodeAllocator) GlobalAddressSDNode(Opc, DL, GV, VT,
Offset, TargetFlags);
CSEMap.InsertNode(N, IP);
AllNodes.push_back(N);
@@ -3370,7 +3370,7 @@
// FIXME does the case above also need this?
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
assert(NVT.bitsGE(VT));
- Value = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Chain,
+ Value = DAG.getExtLoad(ISD::EXTLOAD, NVT, dl, Chain,
getMemBasePlusOffset(Src, SrcOff, DAG),
SrcSV, SrcSVOff + SrcOff, VT, isVol, false,
MinAlign(SrcAlign, SrcOff));
@@ -3895,8 +3895,8 @@
}
SDValue
-SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl,
- ISD::LoadExtType ExtType, EVT VT, SDValue Chain,
+SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
+ EVT VT, DebugLoc dl, SDValue Chain,
SDValue Ptr, SDValue Offset,
const Value *SV, int SVOffset, EVT MemVT,
bool isVolatile, bool isNonTemporal,
@@ -3919,12 +3919,12 @@
MachineMemOperand *MMO =
MF.getMachineMemOperand(SV, Flags, SVOffset,
MemVT.getStoreSize(), Alignment);
- return getLoad(AM, dl, ExtType, VT, Chain, Ptr, Offset, MemVT, MMO);
+ return getLoad(AM, ExtType, VT, dl, Chain, Ptr, Offset, MemVT, MMO);
}
SDValue
-SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl,
- ISD::LoadExtType ExtType, EVT VT, SDValue Chain,
+SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
+ EVT VT, DebugLoc dl, SDValue Chain,
SDValue Ptr, SDValue Offset, EVT MemVT,
MachineMemOperand *MMO) {
if (VT == MemVT) {
@@ -3974,18 +3974,18 @@
bool isVolatile, bool isNonTemporal,
unsigned Alignment) {
SDValue Undef = getUNDEF(Ptr.getValueType());
- return getLoad(ISD::UNINDEXED, dl, ISD::NON_EXTLOAD, VT, Chain, Ptr, Undef,
+ return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef,
SV, SVOffset, VT, isVolatile, isNonTemporal, Alignment);
}
-SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, EVT VT,
+SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, EVT VT, DebugLoc dl,
SDValue Chain, SDValue Ptr,
const Value *SV,
int SVOffset, EVT MemVT,
bool isVolatile, bool isNonTemporal,
unsigned Alignment) {
SDValue Undef = getUNDEF(Ptr.getValueType());
- return getLoad(ISD::UNINDEXED, dl, ExtType, VT, Chain, Ptr, Undef,
+ return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef,
SV, SVOffset, MemVT, isVolatile, isNonTemporal, Alignment);
}
@@ -3995,7 +3995,7 @@
LoadSDNode *LD = cast<LoadSDNode>(OrigLoad);
assert(LD->getOffset().getOpcode() == ISD::UNDEF &&
"Load is already a indexed load!");
- return getLoad(AM, dl, LD->getExtensionType(), OrigLoad.getValueType(),
+ return getLoad(AM, LD->getExtensionType(), OrigLoad.getValueType(), dl,
LD->getChain(), Base, Offset, LD->getSrcValue(),
LD->getSrcValueOffset(), LD->getMemoryVT(),
LD->isVolatile(), LD->isNonTemporal(), LD->getAlignment());
@@ -5375,9 +5375,10 @@
DropOperands();
}
-GlobalAddressSDNode::GlobalAddressSDNode(unsigned Opc, const GlobalValue *GA,
+GlobalAddressSDNode::GlobalAddressSDNode(unsigned Opc, DebugLoc DL,
+ const GlobalValue *GA,
EVT VT, int64_t o, unsigned char TF)
- : SDNode(Opc, DebugLoc(), getSDVTList(VT)), Offset(o), TargetFlags(TF) {
+ : SDNode(Opc, DL, getSDVTList(VT)), Offset(o), TargetFlags(TF) {
TheGlobal = GA;
}
Modified: llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Thu Jul 8 03:14:09 2010
@@ -14,7 +14,6 @@
#define DEBUG_TYPE "isel"
#include "SDNodeDbgValue.h"
#include "SelectionDAGBuilder.h"
-#include "FunctionLoweringInfo.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/Analysis/AliasAnalysis.h"
@@ -32,6 +31,7 @@
#include "llvm/Module.h"
#include "llvm/CodeGen/Analysis.h"
#include "llvm/CodeGen/FastISel.h"
+#include "llvm/CodeGen/FunctionLoweringInfo.h"
#include "llvm/CodeGen/GCStrategy.h"
#include "llvm/CodeGen/GCMetadata.h"
#include "llvm/CodeGen/MachineFunction.h"
@@ -852,7 +852,7 @@
return DAG.getConstant(*CI, VT);
if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
- return DAG.getGlobalAddress(GV, VT);
+ return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT);
if (isa<ConstantPointerNull>(C))
return DAG.getConstant(0, TLI.getPointerTy());
@@ -1027,6 +1027,7 @@
void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
SDValue Chain = getControlRoot();
SmallVector<ISD::OutputArg, 8> Outs;
+ SmallVector<SDValue, 8> OutVals;
if (!FuncInfo.CanLowerReturn) {
unsigned DemoteReg = FuncInfo.DemoteRegister;
@@ -1105,8 +1106,11 @@
else if (F->paramHasAttr(0, Attribute::ZExt))
Flags.setZExt();
- for (unsigned i = 0; i < NumParts; ++i)
- Outs.push_back(ISD::OutputArg(Flags, Parts[i], /*isfixed=*/true));
+ for (unsigned i = 0; i < NumParts; ++i) {
+ Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
+ /*isfixed=*/true));
+ OutVals.push_back(Parts[i]);
+ }
}
}
}
@@ -1115,7 +1119,7 @@
CallingConv::ID CallConv =
DAG.getMachineFunction().getFunction()->getCallingConv();
Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
- Outs, getCurDebugLoc(), DAG);
+ Outs, OutVals, getCurDebugLoc(), DAG);
// Verify that the target's LowerReturn behaved as expected.
assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
@@ -4583,7 +4587,7 @@
OutVTs, OutsFlags, TLI, &Offsets);
bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
- FTy->isVarArg(), OutVTs, OutsFlags, DAG);
+ FTy->isVarArg(), OutVTs, OutsFlags, FTy->getContext());
SDValue DemoteStackSlot;
@@ -5792,6 +5796,7 @@
DebugLoc dl) const {
// Handle all of the outgoing arguments.
SmallVector<ISD::OutputArg, 32> Outs;
+ SmallVector<SDValue, 32> OutVals;
for (unsigned i = 0, e = Args.size(); i != e; ++i) {
SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
@@ -5845,13 +5850,15 @@
for (unsigned j = 0; j != NumParts; ++j) {
// if it isn't first piece, alignment must be 1
- ISD::OutputArg MyFlags(Flags, Parts[j], i < NumFixedArgs);
+ ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(),
+ i < NumFixedArgs);
if (NumParts > 1 && j == 0)
MyFlags.Flags.setSplit();
else if (j != 0)
MyFlags.Flags.setOrigAlign(1);
Outs.push_back(MyFlags);
+ OutVals.push_back(Parts[j]);
}
}
}
@@ -5880,7 +5887,7 @@
SmallVector<SDValue, 4> InVals;
Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
- Outs, Ins, dl, DAG, InVals);
+ Outs, OutVals, Ins, dl, DAG, InVals);
// Verify that the target's LowerCall behaved as expected.
assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
@@ -5983,7 +5990,8 @@
FuncInfo->CanLowerReturn = TLI.CanLowerReturn(F.getCallingConv(),
F.isVarArg(),
- OutVTs, OutsFlags, DAG);
+ OutVTs, OutsFlags,
+ F.getContext());
if (!FuncInfo->CanLowerReturn) {
// Put in an sret pointer parameter before all the other parameters.
SmallVector<EVT, 1> ValueVTs;
Modified: llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Jul 8 03:14:09 2010
@@ -14,7 +14,7 @@
#define DEBUG_TYPE "isel"
#include "ScheduleDAGSDNodes.h"
#include "SelectionDAGBuilder.h"
-#include "FunctionLoweringInfo.h"
+#include "llvm/CodeGen/FunctionLoweringInfo.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/Analysis/DebugInfo.h"
@@ -321,7 +321,6 @@
MachineBasicBlock *
SelectionDAGISel::SelectBasicBlock(MachineBasicBlock *BB,
- const BasicBlock *LLVMBB,
BasicBlock::const_iterator Begin,
BasicBlock::const_iterator End,
bool &HadTailCall) {
@@ -672,13 +671,7 @@
// Initialize the Fast-ISel state, if needed.
FastISel *FastIS = 0;
if (EnableFastISel)
- FastIS = TLI.createFastISel(*MF, FuncInfo->ValueMap, FuncInfo->MBBMap,
- FuncInfo->StaticAllocaMap,
- FuncInfo->PHINodesToUpdate
-#ifndef NDEBUG
- , FuncInfo->CatchInfoLost
-#endif
- );
+ FastIS = TLI.createFastISel(*FuncInfo);
// Iterate over all basic blocks in the function.
for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
@@ -736,7 +729,7 @@
}
bool HadTailCall = false;
- BB = SelectBasicBlock(BB, LLVMBB, BI, llvm::next(BI), HadTailCall);
+ BB = SelectBasicBlock(BB, BI, llvm::next(BI), HadTailCall);
// If the call was emitted as a tail call, we're done with the block.
if (HadTailCall) {
@@ -772,7 +765,7 @@
// block.
if (BI != End) {
bool HadTailCall;
- BB = SelectBasicBlock(BB, LLVMBB, BI, End, HadTailCall);
+ BB = SelectBasicBlock(BB, BI, End, HadTailCall);
}
FinishBasicBlock(BB);
Modified: llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/TargetLowering.cpp Thu Jul 8 03:14:09 2010
@@ -2414,7 +2414,8 @@
if (ConstraintLetter != 'n') {
int64_t Offs = GA->getOffset();
if (C) Offs += C->getZExtValue();
- Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
+ Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
+ C->getDebugLoc(),
Op.getValueType(), Offs));
return;
}
Modified: llvm/branches/wendling/eh/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SimpleRegisterCoalescing.cpp Thu Jul 8 03:14:09 2010
@@ -101,6 +101,11 @@
///
bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(const CoalescerPair &CP,
MachineInstr *CopyMI) {
+ // Bail if there is no dst interval - can happen when merging physical subreg
+ // operations.
+ if (!li_->hasInterval(CP.getDstReg()))
+ return false;
+
LiveInterval &IntA =
li_->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
LiveInterval &IntB =
@@ -110,7 +115,7 @@
// BValNo is a value number in B that is defined by a copy from A. 'B3' in
// the example above.
LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
- assert(BLR != IntB.end() && "Live range not found!");
+ if (BLR == IntB.end()) return false;
VNInfo *BValNo = BLR->valno;
// Get the location that B is defined at. Two options: either this value has
@@ -206,6 +211,8 @@
// physreg has sub-registers, update their live intervals as well.
if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
+ if (!li_->hasInterval(*SR))
+ continue;
LiveInterval &SRLI = li_->getInterval(*SR);
SRLI.addRange(LiveRange(FillerStart, FillerEnd,
SRLI.getNextValue(FillerStart, 0, true,
@@ -301,23 +308,31 @@
///
/// This returns true if an interval was modified.
///
-bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
- LiveInterval &IntB,
+bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(const CoalescerPair &CP,
MachineInstr *CopyMI) {
- SlotIndex CopyIdx =
- li_->getInstructionIndex(CopyMI).getDefIndex();
-
// FIXME: For now, only eliminate the copy by commuting its def when the
// source register is a virtual register. We want to guard against cases
// where the copy is a back edge copy and commuting the def lengthen the
// live interval of the source register to the entire loop.
- if (TargetRegisterInfo::isPhysicalRegister(IntA.reg))
+ if (CP.isPhys() && CP.isFlipped())
return false;
+ // Bail if there is no dst interval.
+ if (!li_->hasInterval(CP.getDstReg()))
+ return false;
+
+ SlotIndex CopyIdx =
+ li_->getInstructionIndex(CopyMI).getDefIndex();
+
+ LiveInterval &IntA =
+ li_->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
+ LiveInterval &IntB =
+ li_->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
+
// BValNo is a value number in B that is defined by a copy from A. 'B3' in
// the example above.
LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
- assert(BLR != IntB.end() && "Live range not found!");
+ if (BLR == IntB.end()) return false;
VNInfo *BValNo = BLR->valno;
// Get the location that B is defined at. Two options: either this value has
@@ -339,6 +354,8 @@
AValNo->isUnused() || AValNo->hasPHIKill())
return false;
MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def);
+ if (!DefMI)
+ return false;
const TargetInstrDesc &TID = DefMI->getDesc();
if (!TID.isCommutable())
return false;
@@ -377,7 +394,8 @@
// clobbers from the superreg.
if (BHasSubRegs)
for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR)
- if (HasOtherReachingDefs(IntA, li_->getInterval(*SR), AValNo, 0))
+ if (li_->hasInterval(*SR) &&
+ HasOtherReachingDefs(IntA, li_->getInterval(*SR), AValNo, 0))
return false;
// If some of the uses of IntA.reg is already coalesced away, return false.
@@ -483,9 +501,11 @@
VNInfo *DeadVNI = BDeadValNos[i];
if (BHasSubRegs) {
for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
+ if (!li_->hasInterval(*SR))
+ continue;
LiveInterval &SRLI = li_->getInterval(*SR);
- const LiveRange *SRLR = SRLI.getLiveRangeContaining(DeadVNI->def);
- SRLI.removeValNo(SRLR->valno);
+ if (const LiveRange *SRLR = SRLI.getLiveRangeContaining(DeadVNI->def))
+ SRLI.removeValNo(SRLR->valno);
}
}
IntB.removeValNo(BDeadValNos[i]);
@@ -505,16 +525,6 @@
if (EI != BExtend.end())
End = EI->second;
IntB.addRange(LiveRange(AI->start, End, ValNo));
-
- // If the IntB live range is assigned to a physical register, and if that
- // physreg has sub-registers, update their live intervals as well.
- if (BHasSubRegs) {
- for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
- LiveInterval &SRLI = li_->getInterval(*SR);
- SRLI.MergeInClobberRange(*li_, AI->start, End,
- li_->getVNInfoAllocator());
- }
- }
}
ValNo->setHasPHIKill(BHasPHIKill);
@@ -1134,11 +1144,6 @@
}
}
- // We may need the source interval after JoinIntervals has destroyed it.
- OwningPtr<LiveInterval> SavedLI;
- if (CP.getOrigDstReg() != CP.getDstReg())
- SavedLI.reset(li_->dupInterval(&li_->getInterval(CP.getSrcReg())));
-
// Okay, attempt to join these two intervals. On failure, this returns false.
// Otherwise, if one of the intervals being joined is a physreg, this method
// always canonicalizes DstInt to be it. The output "SrcInt" will not have
@@ -1155,12 +1160,8 @@
// If we can eliminate the copy without merging the live ranges, do so now.
if (!CP.isPartial()) {
- LiveInterval *UseInt = &li_->getInterval(CP.getSrcReg());
- LiveInterval *DefInt = &li_->getInterval(CP.getDstReg());
- if (CP.isFlipped())
- std::swap(UseInt, DefInt);
if (AdjustCopiesBackFrom(CP, CopyMI) ||
- RemoveCopyByCommutingDef(*UseInt, *DefInt, CopyMI)) {
+ RemoveCopyByCommutingDef(CP, CopyMI)) {
JoinedCopies.insert(CopyMI);
DEBUG(dbgs() << "\tTrivial!\n");
return true;
@@ -1173,38 +1174,6 @@
return false;
}
- if (CP.isPhys()) {
- // If this is a extract_subreg where dst is a physical register, e.g.
- // cl = EXTRACT_SUBREG reg1024, 1
- // then create and update the actual physical register allocated to RHS.
- unsigned LargerDstReg = CP.getDstReg();
- if (CP.getOrigDstReg() != CP.getDstReg()) {
- if (tri_->isSubRegister(CP.getOrigDstReg(), LargerDstReg))
- LargerDstReg = CP.getOrigDstReg();
- LiveInterval &RealInt = li_->getOrCreateInterval(CP.getDstReg());
- for (LiveInterval::const_vni_iterator I = SavedLI->vni_begin(),
- E = SavedLI->vni_end(); I != E; ++I) {
- const VNInfo *ValNo = *I;
- VNInfo *NewValNo = RealInt.getNextValue(ValNo->def, ValNo->getCopy(),
- false, // updated at *
- li_->getVNInfoAllocator());
- NewValNo->setFlags(ValNo->getFlags()); // * updated here.
- RealInt.MergeValueInAsValue(*SavedLI, ValNo, NewValNo);
- }
- RealInt.weight += SavedLI->weight;
- }
-
- // Update the liveintervals of sub-registers.
- LiveInterval &LargerInt = li_->getInterval(LargerDstReg);
- for (const unsigned *AS = tri_->getSubRegisters(LargerDstReg); *AS; ++AS) {
- LiveInterval &SRI = li_->getOrCreateInterval(*AS);
- SRI.MergeInClobberRanges(*li_, LargerInt, li_->getVNInfoAllocator());
- DEBUG({
- dbgs() << "\t\tsubreg: "; SRI.print(dbgs(), tri_); dbgs() << "\n";
- });
- }
- }
-
// Coalescing to a virtual register that is of a sub-register class of the
// other. Make sure the resulting register is set to the right register class.
if (CP.isCrossClass()) {
@@ -1311,50 +1280,44 @@
LiveInterval &RHS = li_->getInterval(CP.getSrcReg());
DEBUG({ dbgs() << "\t\tRHS = "; RHS.print(dbgs(), tri_); dbgs() << "\n"; });
- // FIXME: Join into CP.getDstReg instead of CP.getOrigDstReg.
- // When looking at
- // %reg2000 = EXTRACT_SUBREG %EAX, sub_16bit
- // we really want to join %reg2000 with %AX ( = CP.getDstReg). We are actually
- // joining into %EAX ( = CP.getOrigDstReg) because it is guaranteed to have an
- // existing live interval, and we are better equipped to handle interference.
- // JoinCopy cleans up the mess by taking a copy of RHS before calling here,
- // and merging that copy into CP.getDstReg after.
-
- // If a live interval is a physical register, conservatively check if any
- // of its sub-registers is overlapping the live interval of the virtual
- // register. If so, do not coalesce.
- if (CP.isPhys() && *tri_->getSubRegisters(CP.getOrigDstReg())) {
- // If it's coalescing a virtual register to a physical register, estimate
- // its live interval length. This is the *cost* of scanning an entire live
- // interval. If the cost is low, we'll do an exhaustive check instead.
-
- // If this is something like this:
- // BB1:
- // v1024 = op
- // ...
- // BB2:
- // ...
- // RAX = v1024
- //
- // That is, the live interval of v1024 crosses a bb. Then we can't rely on
- // less conservative check. It's possible a sub-register is defined before
- // v1024 (or live in) and live out of BB1.
- if (RHS.containsOneValue() &&
- li_->intervalIsInOneMBB(RHS) &&
- li_->getApproximateInstructionCount(RHS) <= 10) {
- // Perform a more exhaustive check for some common cases.
- if (li_->conflictsWithAliasRef(RHS, CP.getOrigDstReg(), JoinedCopies))
- return false;
- } else {
- for (const unsigned* SR = tri_->getAliasSet(CP.getOrigDstReg()); *SR;
- ++SR)
- if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
+ // If a live interval is a physical register, check for interference with any
+ // aliases. The interference check implemented here is a bit more conservative
+ // than the full interfeence check below. We allow overlapping live ranges
+ // only when one is a copy of the other.
+ if (CP.isPhys()) {
+ for (const unsigned *AS = tri_->getAliasSet(CP.getDstReg()); *AS; ++AS){
+ if (!li_->hasInterval(*AS))
+ continue;
+ const LiveInterval &LHS = li_->getInterval(*AS);
+ LiveInterval::const_iterator LI = LHS.begin();
+ for (LiveInterval::const_iterator RI = RHS.begin(), RE = RHS.end();
+ RI != RE; ++RI) {
+ LI = std::lower_bound(LI, LHS.end(), RI->start);
+ // Does LHS have an overlapping live range starting before RI?
+ if ((LI != LHS.begin() && LI[-1].end > RI->start) &&
+ (RI->start != RI->valno->def ||
+ !CP.isCoalescable(li_->getInstructionFromIndex(RI->start)))) {
DEBUG({
- dbgs() << "\tInterfere with sub-register ";
- li_->getInterval(*SR).print(dbgs(), tri_);
- });
+ dbgs() << "\t\tInterference from alias: ";
+ LHS.print(dbgs(), tri_);
+ dbgs() << "\n\t\tOverlap at " << RI->start << " and no copy.\n";
+ });
return false;
}
+
+ // Check that LHS ranges beginning in this range are copies.
+ for (; LI != LHS.end() && LI->start < RI->end; ++LI) {
+ if (LI->start != LI->valno->def ||
+ !CP.isCoalescable(li_->getInstructionFromIndex(LI->start))) {
+ DEBUG({
+ dbgs() << "\t\tInterference from alias: ";
+ LHS.print(dbgs(), tri_);
+ dbgs() << "\n\t\tDef at " << LI->start << " is not a copy.\n";
+ });
+ return false;
+ }
+ }
+ }
}
}
@@ -1366,7 +1329,7 @@
DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
SmallVector<VNInfo*, 16> NewVNInfo;
- LiveInterval &LHS = li_->getInterval(CP.getOrigDstReg());
+ LiveInterval &LHS = li_->getOrCreateInterval(CP.getDstReg());
DEBUG({ dbgs() << "\t\tLHS = "; LHS.print(dbgs(), tri_); dbgs() << "\n"; });
// Loop over the value numbers of the LHS, seeing if any are defined from
Modified: llvm/branches/wendling/eh/lib/CodeGen/SimpleRegisterCoalescing.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SimpleRegisterCoalescing.h?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SimpleRegisterCoalescing.h (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SimpleRegisterCoalescing.h Thu Jul 8 03:14:09 2010
@@ -130,8 +130,7 @@
/// If the source value number is defined by a commutable instruction and
/// its other operand is coalesced to the copy dest register, see if we
/// can transform the copy into a noop by commuting the definition.
- bool RemoveCopyByCommutingDef(LiveInterval &IntA, LiveInterval &IntB,
- MachineInstr *CopyMI);
+ bool RemoveCopyByCommutingDef(const CoalescerPair &CP,MachineInstr *CopyMI);
/// TrimLiveIntervalToLastUse - If there is a last use in the same basic
/// block as the copy instruction, trim the ive interval to the last use
Modified: llvm/branches/wendling/eh/lib/CodeGen/Spiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/Spiller.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/Spiller.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/Spiller.cpp Thu Jul 8 03:14:09 2010
@@ -55,8 +55,8 @@
const TargetInstrInfo *tii;
const TargetRegisterInfo *tri;
VirtRegMap *vrm;
-
- /// Construct a spiller base.
+
+ /// Construct a spiller base.
SpillerBase(MachineFunction *mf, LiveIntervals *lis, VirtRegMap *vrm)
: mf(mf), lis(lis), vrm(vrm)
{
@@ -97,7 +97,7 @@
do {
++regItr;
} while (regItr != mri->reg_end() && (&*regItr == mi));
-
+
// Collect uses & defs for this instr.
SmallVector<unsigned, 2> indices;
bool hasUse = false;
@@ -117,7 +117,7 @@
vrm->assignVirt2StackSlot(newVReg, ss);
LiveInterval *newLI = &lis->getOrCreateInterval(newVReg);
newLI->weight = HUGE_VALF;
-
+
// Update the reg operands & kill flags.
for (unsigned i = 0; i < indices.size(); ++i) {
unsigned mopIdx = indices[i];
@@ -217,7 +217,7 @@
/// When a call to spill is placed this spiller will first try to break the
/// interval up into its component values (one new interval per value).
/// If this fails, or if a call is placed to spill a previously split interval
-/// then the spiller falls back on the standard spilling mechanism.
+/// then the spiller falls back on the standard spilling mechanism.
class SplittingSpiller : public StandardSpiller {
public:
SplittingSpiller(MachineFunction *mf, LiveIntervals *lis,
@@ -243,7 +243,7 @@
MachineRegisterInfo *mri;
const TargetInstrInfo *tii;
- const TargetRegisterInfo *tri;
+ const TargetRegisterInfo *tri;
DenseSet<LiveInterval*> alreadySplit;
bool worthTryingToSplit(LiveInterval *li) const {
@@ -260,18 +260,18 @@
SmallVector<VNInfo*, 4> vnis;
std::copy(li->vni_begin(), li->vni_end(), std::back_inserter(vnis));
-
+
for (SmallVectorImpl<VNInfo*>::iterator vniItr = vnis.begin(),
vniEnd = vnis.end(); vniItr != vniEnd; ++vniItr) {
VNInfo *vni = *vniItr;
-
+
// Skip unused VNIs.
if (vni->isUnused())
continue;
DEBUG(dbgs() << " Extracted Val #" << vni->id << " as ");
LiveInterval *splitInterval = extractVNI(li, vni);
-
+
if (splitInterval != 0) {
DEBUG(dbgs() << *splitInterval << "\n");
added.push_back(splitInterval);
@@ -283,12 +283,12 @@
} else {
DEBUG(dbgs() << "0\n");
}
- }
+ }
DEBUG(dbgs() << "Original LI: " << *li << "\n");
// If there original interval still contains some live ranges
- // add it to added and alreadySplit.
+ // add it to added and alreadySplit.
if (!li->empty()) {
added.push_back(li);
alreadySplit.insert(li);
@@ -312,7 +312,7 @@
LiveInterval *newLI = &lis->getOrCreateInterval(newVReg);
VNInfo *newVNI = newLI->createValueCopy(vni, lis->getVNInfoAllocator());
- // Start by copying all live ranges in the VN to the new interval.
+ // Start by copying all live ranges in the VN to the new interval.
for (LiveInterval::iterator rItr = li->begin(), rEnd = li->end();
rItr != rEnd; ++rItr) {
if (rItr->valno == vni) {
@@ -320,7 +320,7 @@
}
}
- // Erase the old VNI & ranges.
+ // Erase the old VNI & ranges.
li->removeValNo(vni);
// Collect all current uses of the register belonging to the given VNI.
@@ -367,8 +367,8 @@
newVNI->setIsPHIDef(false); // not a PHI def anymore.
newVNI->setIsDefAccurate(true);
} else {
- // non-PHI def. Rename the def. If it's two-addr that means renaming the use
- // and inserting a new copy too.
+ // non-PHI def. Rename the def. If it's two-addr that means renaming the
+ // use and inserting a new copy too.
MachineInstr *defInst = lis->getInstructionFromIndex(newVNI->def);
// We'll rename this now, so we can remove it from uses.
uses.erase(defInst);
@@ -384,7 +384,7 @@
twoAddrUseIsUndef = true;
}
}
-
+
SlotIndex defIdx = lis->getInstructionIndex(defInst);
newVNI->def = defIdx.getDefIndex();
@@ -402,9 +402,9 @@
true, lis->getVNInfoAllocator());
LiveRange copyRange(copyIdx.getDefIndex(),defIdx.getDefIndex(),copyVNI);
newLI->addRange(copyRange);
- }
+ }
}
-
+
for (std::set<MachineInstr*>::iterator
usesItr = uses.begin(), usesEnd = uses.end();
usesItr != usesEnd; ++usesItr) {
@@ -424,7 +424,7 @@
// Check if this instr is two address.
unsigned useOpIdx = useInst->findRegisterUseOperandIdx(li->reg);
bool isTwoAddress = useInst->isRegTiedToDefOperand(useOpIdx);
-
+
// Rename uses (and defs for two-address instrs).
for (unsigned i = 0; i < useInst->getNumOperands(); ++i) {
MachineOperand &mo = useInst->getOperand(i);
@@ -440,8 +440,8 @@
// reg.
MachineBasicBlock *useMBB = useInst->getParent();
MachineBasicBlock::iterator useItr(useInst);
- tii->copyRegToReg(*useMBB, llvm::next(useItr), li->reg, newVReg, trc, trc,
- DebugLoc());
+ tii->copyRegToReg(*useMBB, llvm::next(useItr), li->reg, newVReg, trc,
+ trc, DebugLoc());
MachineInstr *copyMI = llvm::next(useItr);
copyMI->addRegisterKilled(newVReg, tri);
SlotIndex copyIdx = lis->InsertMachineInstrInMaps(copyMI);
Modified: llvm/branches/wendling/eh/lib/CodeGen/StackProtector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/StackProtector.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/StackProtector.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/StackProtector.cpp Thu Jul 8 03:14:09 2010
@@ -153,21 +153,16 @@
// StackGuard = load __stack_chk_guard
// call void @llvm.stackprotect.create(StackGuard, StackGuardSlot)
//
- PointerType *PtrTy = PointerType::getUnqual(
- Type::getInt8Ty(RI->getContext()));
-
+ const PointerType *PtrTy = Type::getInt8PtrTy(RI->getContext());
unsigned AddressSpace, Offset;
if (TLI->getStackCookieLocation(AddressSpace, Offset)) {
- Constant *ASPtr = Constant::getNullValue(
- PointerType::get(Type::getInt8Ty(RI->getContext()), AddressSpace));
- APInt OffsetInt(32, Offset);
- Constant *OffsetVal = Constant::getIntegerValue(
- Type::getInt32Ty(RI->getContext()), OffsetInt);
- StackGuardVar = ConstantExpr::getPointerCast(
- ConstantExpr::getGetElementPtr(ASPtr, &OffsetVal, 1),
- PointerType::get(PtrTy, AddressSpace));
+ Constant *OffsetVal =
+ ConstantInt::get(Type::getInt32Ty(RI->getContext()), Offset);
+
+ StackGuardVar = ConstantExpr::getIntToPtr(OffsetVal,
+ PointerType::get(PtrTy, AddressSpace));
} else {
- StackGuardVar = M->getOrInsertGlobal("__stack_chk_guard", PtrTy);
+ StackGuardVar = M->getOrInsertGlobal("__stack_chk_guard", PtrTy);
}
BasicBlock &Entry = F->getEntryBlock();
Modified: llvm/branches/wendling/eh/lib/CodeGen/TargetInstrInfoImpl.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/TargetInstrInfoImpl.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/TargetInstrInfoImpl.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/TargetInstrInfoImpl.cpp Thu Jul 8 03:14:09 2010
@@ -365,3 +365,20 @@
CreateTargetPostRAHazardRecognizer(const InstrItineraryData &II) const {
return (ScheduleHazardRecognizer *)new PostRAHazardRecognizer(II);
}
+
+// Default implementation of copyPhysReg using copyRegToReg.
+void TargetInstrInfoImpl::copyPhysReg(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ DebugLoc DL,
+ unsigned DestReg, unsigned SrcReg,
+ bool KillSrc) const {
+ assert(TargetRegisterInfo::isPhysicalRegister(DestReg));
+ assert(TargetRegisterInfo::isPhysicalRegister(SrcReg));
+ const TargetRegisterInfo *TRI = MBB.getParent()->getTarget().getRegisterInfo();
+ const TargetRegisterClass *DRC = TRI->getPhysicalRegisterRegClass(DestReg);
+ const TargetRegisterClass *SRC = TRI->getPhysicalRegisterRegClass(SrcReg);
+ if (!copyRegToReg(MBB, MI, DestReg, SrcReg, DRC, SRC, DL))
+ llvm_unreachable("Cannot emit physreg copy instruction");
+ if (KillSrc)
+ llvm::prior(MI)->addRegisterKilled(SrcReg, TRI, true);
+}
Modified: llvm/branches/wendling/eh/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/TargetLoweringObjectFileImpl.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/TargetLoweringObjectFileImpl.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/TargetLoweringObjectFileImpl.cpp Thu Jul 8 03:14:09 2010
@@ -936,7 +936,7 @@
getCOFFSectionFlags(SectionKind K) {
unsigned Flags = 0;
- if (!K.isMetadata())
+ if (K.isMetadata())
Flags |=
COFF::IMAGE_SCN_MEM_DISCARDABLE;
else if (K.isText())
Modified: llvm/branches/wendling/eh/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/TwoAddressInstructionPass.cpp Thu Jul 8 03:14:09 2010
@@ -1218,6 +1218,19 @@
DEBUG(dbgs() << "\t\trewrite to:\t" << *mi);
}
+ // Rewrite INSERT_SUBREG as COPY now that we no longer need SSA form.
+ if (mi->isInsertSubreg()) {
+ // From %reg = INSERT_SUBREG %reg, %subreg, subidx
+ // To %reg:subidx = COPY %subreg
+ unsigned SubIdx = mi->getOperand(3).getImm();
+ mi->RemoveOperand(3);
+ assert(mi->getOperand(0).getSubReg() == 0 && "Unexpected subreg idx");
+ mi->getOperand(0).setSubReg(SubIdx);
+ mi->RemoveOperand(1);
+ mi->setDesc(TII->get(TargetOpcode::COPY));
+ DEBUG(dbgs() << "\t\tconvert to:\t" << *mi);
+ }
+
// Clear TiedOperands here instead of at the top of the loop
// since most instructions do not have tied operands.
TiedOperands.clear();
Propchange: llvm/branches/wendling/eh/lib/CompilerDriver/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -1,8 +1,9 @@
Debug
Release
Release-Asserts
-
Debug+Coverage-Asserts
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/ExecutionEngine/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/ExecutionEngine/Interpreter/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/ExecutionEngine/JIT/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Linker/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/MC/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/MC/MCParser/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Modified: llvm/branches/wendling/eh/lib/MC/MachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/MC/MachObjectWriter.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/MC/MachObjectWriter.cpp (original)
+++ llvm/branches/wendling/eh/lib/MC/MachObjectWriter.cpp Thu Jul 8 03:14:09 2010
@@ -33,6 +33,7 @@
default: llvm_unreachable("invalid fixup kind!");
case X86::reloc_pcrel_1byte:
case FK_Data_1: return 0;
+ case X86::reloc_pcrel_2byte:
case FK_Data_2: return 1;
case X86::reloc_pcrel_4byte:
case X86::reloc_riprel_4byte:
@@ -47,6 +48,7 @@
default:
return false;
case X86::reloc_pcrel_1byte:
+ case X86::reloc_pcrel_2byte:
case X86::reloc_pcrel_4byte:
case X86::reloc_riprel_4byte:
case X86::reloc_riprel_4byte_movq_load:
Propchange: llvm/branches/wendling/eh/lib/Support/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -6,3 +6,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Modified: llvm/branches/wendling/eh/lib/Support/Triple.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Support/Triple.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Support/Triple.cpp (original)
+++ llvm/branches/wendling/eh/lib/Support/Triple.cpp Thu Jul 8 03:14:09 2010
@@ -104,6 +104,7 @@
case Solaris: return "solaris";
case Win32: return "win32";
case Haiku: return "haiku";
+ case Minix: return "minix";
}
return "<invalid>";
@@ -326,7 +327,9 @@
else if (OSName.startswith("win32"))
OS = Win32;
else if (OSName.startswith("haiku"))
- OS = Haiku;
+ OS = Haiku;
+ else if (OSName.startswith("minix"))
+ OS = Minix;
else
OS = UnknownOS;
Modified: llvm/branches/wendling/eh/lib/Support/raw_ostream.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Support/raw_ostream.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Support/raw_ostream.cpp (original)
+++ llvm/branches/wendling/eh/lib/Support/raw_ostream.cpp Thu Jul 8 03:14:09 2010
@@ -481,7 +481,7 @@
}
size_t raw_fd_ostream::preferred_buffer_size() const {
-#if !defined(_MSC_VER) && !defined(__MINGW32__) && !defined(_MINIX)
+#if !defined(_MSC_VER) && !defined(__MINGW32__) && !defined(__minix)
// Windows and Minix have no st_blksize.
assert(FD >= 0 && "File not yet open!");
struct stat statbuf;
Propchange: llvm/branches/wendling/eh/lib/System/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -6,3 +6,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Modified: llvm/branches/wendling/eh/lib/System/Unix/Program.inc
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/System/Unix/Program.inc?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/System/Unix/Program.inc (original)
+++ llvm/branches/wendling/eh/lib/System/Unix/Program.inc Thu Jul 8 03:14:09 2010
@@ -310,7 +310,7 @@
// fact of having a handler at all causes the wait below to return with EINTR,
// unlike if we used SIG_IGN.
if (secondsToWait) {
-#ifndef __HAIKU__
+#if !defined(__HAIKU__) && !defined(__minix)
Act.sa_sigaction = 0;
#endif
Act.sa_handler = TimeOutHandler;
Propchange: llvm/branches/wendling/eh/lib/Target/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Target/ARM/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -6,3 +6,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMAddressingModes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMAddressingModes.h?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMAddressingModes.h (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMAddressingModes.h Thu Jul 8 03:14:09 2010
@@ -520,6 +520,8 @@
// This is stored in two operands [regaddr, align]. The first is the
// address register. The second operand is the value of the alignment
// specifier to use or zero if no explicit alignment.
+ // Valid alignments are: 0, 8, 16, and 32 bytes, depending on the specific
+ // instruction.
} // end namespace ARM_AM
} // end namespace llvm
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseInstrInfo.cpp Thu Jul 8 03:14:09 2010
@@ -718,6 +718,12 @@
if (SrcRC == ARM::DPR_8RegisterClass)
SrcRC = ARM::DPR_VFP2RegisterClass;
+ // NEONMoveFixPass will convert VFP moves to NEON moves when profitable.
+ if (DestRC == ARM::DPR_VFP2RegisterClass)
+ DestRC = ARM::DPRRegisterClass;
+ if (SrcRC == ARM::DPR_VFP2RegisterClass)
+ SrcRC = ARM::DPRRegisterClass;
+
// Allow QPR / QPR_VFP2 / QPR_8 cross-class copies.
if (DestRC == ARM::QPR_VFP2RegisterClass ||
DestRC == ARM::QPR_8RegisterClass)
@@ -750,10 +756,6 @@
Opc = (SrcRC == ARM::GPRRegisterClass ? ARM::VMOVSR : ARM::VMOVS);
else if (DestRC == ARM::DPRRegisterClass)
Opc = ARM::VMOVD;
- else if (DestRC == ARM::DPR_VFP2RegisterClass ||
- SrcRC == ARM::DPR_VFP2RegisterClass)
- // Always use neon reg-reg move if source or dest is NEON-only regclass.
- Opc = ARM::VMOVDneon;
else if (DestRC == ARM::QPRRegisterClass)
Opc = ARM::VMOVQ;
else if (DestRC == ARM::QQPRRegisterClass)
@@ -830,7 +832,7 @@
// FIXME: Neon instructions should support predicates
if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q))
- .addFrameIndex(FI).addImm(128)
+ .addFrameIndex(FI).addImm(16)
.addReg(SrcReg, getKillRegState(isKill))
.addMemOperand(MMO));
} else {
@@ -847,7 +849,7 @@
// FIXME: It's possible to only store part of the QQ register if the
// spilled def has a sub-register index.
MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VST2q32))
- .addFrameIndex(FI).addImm(128);
+ .addFrameIndex(FI).addImm(16);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
@@ -927,7 +929,7 @@
case ARM::QPR_8RegClassID:
if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q), DestReg)
- .addFrameIndex(FI).addImm(128)
+ .addFrameIndex(FI).addImm(16)
.addMemOperand(MMO));
} else {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQ), DestReg)
@@ -944,7 +946,7 @@
MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
- AddDefaultPred(MIB.addFrameIndex(FI).addImm(128).addMemOperand(MMO));
+ AddDefaultPred(MIB.addFrameIndex(FI).addImm(16).addMemOperand(MMO));
} else {
MachineInstrBuilder MIB =
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD))
@@ -1129,7 +1131,7 @@
if (MFI.getObjectAlignment(FI) >= 16 &&
getRegisterInfo().canRealignStack(MF)) {
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VST1q))
- .addFrameIndex(FI).addImm(128)
+ .addFrameIndex(FI).addImm(16)
.addReg(SrcReg,
getKillRegState(isKill) | getUndefRegState(isUndef),
SrcSubReg)
@@ -1155,7 +1157,7 @@
getDeadRegState(isDead) |
getUndefRegState(isUndef),
DstSubReg)
- .addFrameIndex(FI).addImm(128).addImm(Pred).addReg(PredReg);
+ .addFrameIndex(FI).addImm(16).addImm(Pred).addReg(PredReg);
} else {
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDMQ))
.addReg(DstReg,
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseRegisterInfo.cpp Thu Jul 8 03:14:09 2010
@@ -1663,7 +1663,8 @@
// Jump to label or value in register.
if (RetOpcode == ARM::TCRETURNdi) {
- BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPd)).
+ BuildMI(MBB, MBBI, dl,
+ TII.get(STI.isThumb() ? ARM::TAILJMPdt : ARM::TAILJMPd)).
addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
JumpTarget.getTargetFlags());
} else if (RetOpcode == ARM::TCRETURNdiND) {
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMConstantIslandPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMConstantIslandPass.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMConstantIslandPass.cpp Thu Jul 8 03:14:09 2010
@@ -337,7 +337,7 @@
if (CPChange && ++NoCPIters > 30)
llvm_unreachable("Constant Island pass failed to converge!");
DEBUG(dumpBBs());
-
+
// Clear NewWaterList now. If we split a block for branches, it should
// appear as "new water" for the next iteration of constant pool placement.
NewWaterList.clear();
@@ -361,8 +361,8 @@
// After a while, this might be made debug-only, but it is not expensive.
verify(MF);
- // If LR has been forced spilled and no far jumps (i.e. BL) has been issued.
- // Undo the spill / restore of LR if possible.
+ // If LR has been forced spilled and no far jump (i.e. BL) has been issued,
+ // undo the spill / restore of LR if possible.
if (isThumb && !HasFarJump && AFI->isLRSpilledForFarJump())
MadeChange |= UndoLRSpillRestore();
@@ -1624,7 +1624,7 @@
// constantpool tables?
MachineJumpTableInfo *MJTI = MF.getJumpTableInfo();
if (MJTI == 0) return false;
-
+
const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
for (unsigned i = 0, e = T2JumpTables.size(); i != e; ++i) {
MachineInstr *MI = T2JumpTables[i];
@@ -1661,15 +1661,25 @@
continue;
unsigned IdxReg = MI->getOperand(1).getReg();
bool IdxRegKill = MI->getOperand(1).isKill();
+
+ // Scan backwards to find the instruction that defines the base
+ // register. Due to post-RA scheduling, we can't count on it
+ // immediately preceding the branch instruction.
MachineBasicBlock::iterator PrevI = MI;
- if (PrevI == MBB->begin())
+ MachineBasicBlock::iterator B = MBB->begin();
+ while (PrevI != B && !PrevI->definesRegister(BaseReg))
+ --PrevI;
+
+ // If for some reason we didn't find it, we can't do anything, so
+ // just skip this one.
+ if (!PrevI->definesRegister(BaseReg))
continue;
- MachineInstr *AddrMI = --PrevI;
+ MachineInstr *AddrMI = PrevI;
bool OptOk = true;
- // Examine the instruction that calculate the jumptable entry address.
- // If it's not the one just before the t2BR_JT, we won't delete it, then
- // it's not worth doing the optimization.
+ // Examine the instruction that calculates the jumptable entry address.
+ // Make sure it only defines the base register and kills any uses
+ // other than the index register.
for (unsigned k = 0, eee = AddrMI->getNumOperands(); k != eee; ++k) {
const MachineOperand &MO = AddrMI->getOperand(k);
if (!MO.isReg() || !MO.getReg())
@@ -1686,9 +1696,14 @@
if (!OptOk)
continue;
- // The previous instruction should be a tLEApcrel or t2LEApcrelJT, we want
+ // Now scan back again to find the tLEApcrel or t2LEApcrelJT instruction
+ // that gave us the initial base register definition.
+ for (--PrevI; PrevI != B && !PrevI->definesRegister(BaseReg); --PrevI)
+ ;
+
+ // The instruction should be a tLEApcrel or t2LEApcrelJT; we want
// to delete it as well.
- MachineInstr *LeaMI = --PrevI;
+ MachineInstr *LeaMI = PrevI;
if ((LeaMI->getOpcode() != ARM::tLEApcrelJT &&
LeaMI->getOpcode() != ARM::t2LEApcrelJT) ||
LeaMI->getOperand(0).getReg() != BaseReg)
@@ -1732,7 +1747,7 @@
MachineJumpTableInfo *MJTI = MF.getJumpTableInfo();
if (MJTI == 0) return false;
-
+
const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
for (unsigned i = 0, e = T2JumpTables.size(); i != e; ++i) {
MachineInstr *MI = T2JumpTables[i];
@@ -1772,7 +1787,7 @@
{
MachineFunction &MF = *BB->getParent();
- // If it's the destination block is terminated by an unconditional branch,
+ // If the destination block is terminated by an unconditional branch,
// try to move it; otherwise, create a new block following the jump
// table that branches back to the actual target. This is a very simple
// heuristic. FIXME: We can definitely improve it.
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMISelDAGToDAG.cpp Thu Jul 8 03:14:09 2010
@@ -143,6 +143,11 @@
unsigned *DOpcodes, unsigned *QOpcodes0,
unsigned *QOpcodes1);
+ /// SelectVTBL - Select NEON VTBL and VTBX intrinsics. NumVecs should be 2,
+ /// 3 or 4. These are custom-selected so that a REG_SEQUENCE can be
+ /// generated to force the table registers to be consecutive.
+ SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
+
/// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
@@ -1197,7 +1202,7 @@
SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
unsigned *DOpcodes, unsigned *QOpcodes0,
unsigned *QOpcodes1) {
- assert(NumVecs >=1 && NumVecs <= 4 && "VST NumVecs out-of-range");
+ assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
DebugLoc dl = N->getDebugLoc();
SDValue MemAddr, Align;
@@ -1524,6 +1529,46 @@
return NULL;
}
+SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
+ unsigned Opc) {
+ assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range");
+ DebugLoc dl = N->getDebugLoc();
+ EVT VT = N->getValueType(0);
+ unsigned FirstTblReg = IsExt ? 2 : 1;
+
+ // Form a REG_SEQUENCE to force register allocation.
+ SDValue RegSeq;
+ SDValue V0 = N->getOperand(FirstTblReg + 0);
+ SDValue V1 = N->getOperand(FirstTblReg + 1);
+ if (NumVecs == 2)
+ RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);
+ else {
+ SDValue V2 = N->getOperand(FirstTblReg + 2);
+ // If it's a vtbl3, form a quad D-register and leave the last part as
+ // an undef.
+ SDValue V3 = (NumVecs == 3)
+ ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
+ : N->getOperand(FirstTblReg + 3);
+ RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
+ }
+
+ // Now extract the D registers back out.
+ SmallVector<SDValue, 6> Ops;
+ if (IsExt)
+ Ops.push_back(N->getOperand(1));
+ Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, VT, RegSeq));
+ Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, VT, RegSeq));
+ if (NumVecs > 2)
+ Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_2, dl, VT, RegSeq));
+ if (NumVecs > 3)
+ Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_3, dl, VT, RegSeq));
+
+ Ops.push_back(N->getOperand(FirstTblReg + NumVecs));
+ Ops.push_back(getAL(CurDAG)); // predicate
+ Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register
+ return CurDAG->getMachineNode(Opc, dl, VT, Ops.data(), Ops.size());
+}
+
SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
bool isSigned) {
if (!Subtarget->hasV6T2Ops())
@@ -2281,6 +2326,29 @@
break;
}
+ case ISD::INTRINSIC_WO_CHAIN: {
+ unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
+ switch (IntNo) {
+ default:
+ break;
+
+ case Intrinsic::arm_neon_vtbl2:
+ return SelectVTBL(N, false, 2, ARM::VTBL2);
+ case Intrinsic::arm_neon_vtbl3:
+ return SelectVTBL(N, false, 3, ARM::VTBL3);
+ case Intrinsic::arm_neon_vtbl4:
+ return SelectVTBL(N, false, 4, ARM::VTBL4);
+
+ case Intrinsic::arm_neon_vtbx2:
+ return SelectVTBL(N, true, 2, ARM::VTBX2);
+ case Intrinsic::arm_neon_vtbx3:
+ return SelectVTBL(N, true, 3, ARM::VTBX3);
+ case Intrinsic::arm_neon_vtbx4:
+ return SelectVTBL(N, true, 4, ARM::VTBX4);
+ }
+ break;
+ }
+
case ISD::CONCAT_VECTORS:
return SelectConcatVector(N);
}
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMISelLowering.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMISelLowering.cpp Thu Jul 8 03:14:09 2010
@@ -59,7 +59,7 @@
static cl::opt<bool>
EnableARMLongCalls("arm-long-calls", cl::Hidden,
- cl::desc("Generate calls via indirect call instructions."),
+ cl::desc("Generate calls via indirect call instructions"),
cl::init(false));
static cl::opt<bool>
@@ -69,7 +69,7 @@
static cl::opt<bool>
EnableARMCodePlacement("arm-code-placement", cl::Hidden,
- cl::desc("Enable code placement pass for ARM."),
+ cl::desc("Enable code placement pass for ARM"),
cl::init(false));
static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
@@ -473,6 +473,10 @@
// We want to custom lower some of our intrinsics.
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
+ if (Subtarget->isTargetDarwin()) {
+ setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
+ setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
+ }
setOperationAction(ISD::SETCC, MVT::i32, Expand);
setOperationAction(ISD::SETCC, MVT::f32, Expand);
@@ -1026,6 +1030,7 @@
CallingConv::ID CallConv, bool isVarArg,
bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const {
@@ -1039,7 +1044,7 @@
// Check if it's really possible to do a tail call.
isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
- Outs, Ins, DAG);
+ Outs, OutVals, Ins, DAG);
// We don't support GuaranteedTailCallOpt for ARM, only automatically
// detected sibcalls.
if (isTailCall) {
@@ -1079,7 +1084,7 @@
i != e;
++i, ++realArgIdx) {
CCValAssign &VA = ArgLocs[i];
- SDValue Arg = Outs[realArgIdx].Val;
+ SDValue Arg = OutVals[realArgIdx];
ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
// Promote the value if needed.
@@ -1238,7 +1243,7 @@
Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
getPointerTy(), Callee, PICLabel);
} else
- Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
+ Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy());
} else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
isDirect = true;
bool isStub = Subtarget->isTargetDarwin() &&
@@ -1333,13 +1338,7 @@
if (!TII->isLoadFromStackSlot(Def, FI))
return false;
} else {
-// unsigned Opcode = Def->getOpcode();
-// if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
-// Def->getOperand(1).isFI()) {
-// FI = Def->getOperand(1).getIndex();
-// Bytes = Flags.getByValSize();
-// } else
- return false;
+ return false;
}
} else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
if (Flags.isByVal())
@@ -1373,6 +1372,7 @@
bool isCalleeStructRet,
bool isCallerStructRet,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
SelectionDAG& DAG) const {
const Function *CallerF = DAG.getMachineFunction().getFunction();
@@ -1394,6 +1394,12 @@
// FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
// emitEpilogue is not ready for them.
+ // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
+ // LR. This means if we need to reload LR, it takes an extra instructions,
+ // which outweighs the value of the tail call; but here we don't know yet
+ // whether LR is going to be used. Probably the right approach is to
+ // generate the tail call here and turn it back into CALL/RET in
+ // emitEpilogue if LR is used.
if (Subtarget->isThumb1Only())
return false;
@@ -1403,6 +1409,13 @@
// (We could do this by loading the address of the callee into a register;
// that is an extra instruction over the direct call and burns a register
// as well, so is not likely to be a win.)
+
+ // It might be safe to remove this restriction on non-Darwin.
+
+ // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
+ // but we need to make sure there are enough registers; the only valid
+ // registers are the 4 used for parameters. We don't currently do this
+ // case.
if (isa<ExternalSymbolSDNode>(Callee))
return false;
@@ -1466,7 +1479,7 @@
++i, ++realArgIdx) {
CCValAssign &VA = ArgLocs[i];
EVT RegVT = VA.getLocVT();
- SDValue Arg = Outs[realArgIdx].Val;
+ SDValue Arg = OutVals[realArgIdx];
ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
if (VA.getLocInfo() == CCValAssign::Indirect)
return false;
@@ -1501,6 +1514,7 @@
ARMTargetLowering::LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
DebugLoc dl, SelectionDAG &DAG) const {
// CCValAssign - represent the assignment of the return value to a location.
@@ -1531,7 +1545,7 @@
CCValAssign &VA = RVLocs[i];
assert(VA.isRegLoc() && "Can only return in registers!");
- SDValue Arg = Outs[realRVLocIdx].Val;
+ SDValue Arg = OutVals[realRVLocIdx];
switch (VA.getLocInfo()) {
default: llvm_unreachable("Unknown loc info!");
@@ -1769,7 +1783,7 @@
// pair. This is always cheaper.
if (Subtarget->useMovt()) {
return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
- DAG.getTargetGlobalAddress(GV, PtrVT));
+ DAG.getTargetGlobalAddress(GV, dl, PtrVT));
} else {
SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
@@ -2259,9 +2273,44 @@
return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
}
+static bool canBitcastToInt(SDNode *Op) {
+ return Op->hasOneUse() &&
+ ISD::isNormalLoad(Op) &&
+ Op->getValueType(0) == MVT::f32;
+}
+
+static SDValue bitcastToInt(SDValue Op, SelectionDAG &DAG) {
+ if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
+ return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
+ Ld->getChain(), Ld->getBasePtr(),
+ Ld->getSrcValue(), Ld->getSrcValueOffset(),
+ Ld->isVolatile(), Ld->isNonTemporal(),
+ Ld->getAlignment());
+
+ llvm_unreachable("Unknown VFP cmp argument!");
+}
+
/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
-static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
- DebugLoc dl) {
+SDValue
+ARMTargetLowering::getVFPCmp(SDValue &LHS, SDValue &RHS, ISD::CondCode CC,
+ SDValue &ARMCC, SelectionDAG &DAG,
+ DebugLoc dl) const {
+ if (UnsafeFPMath &&
+ (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
+ CC == ISD::SETNE || CC == ISD::SETUNE) &&
+ canBitcastToInt(LHS.getNode()) && canBitcastToInt(RHS.getNode())) {
+ // If unsafe fp math optimization is enabled and there are no othter uses of
+ // the CMP operands, and the condition code is EQ oe NE, we can optimize it
+ // to an integer comparison.
+ if (CC == ISD::SETOEQ)
+ CC = ISD::SETEQ;
+ else if (CC == ISD::SETUNE)
+ CC = ISD::SETNE;
+ LHS = bitcastToInt(LHS, DAG);
+ RHS = bitcastToInt(RHS, DAG);
+ return getARMCmp(LHS, RHS, CC, ARMCC, DAG, dl);
+ }
+
SDValue Cmp;
if (!isFloatingPointZero(RHS))
Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
@@ -2291,13 +2340,13 @@
SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
- SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
+ SDValue Cmp = getVFPCmp(LHS, RHS, CC, ARMCC, DAG, dl);
SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
- ARMCC, CCR, Cmp);
+ ARMCC, CCR, Cmp);
if (CondCode2 != ARMCC::AL) {
SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
// FIXME: Needs another CMP because flag can have but one use.
- SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
+ SDValue Cmp2 = getVFPCmp(LHS, RHS, CC, ARMCC2, DAG, dl);
Result = DAG.getNode(ARMISD::CMOV, dl, VT,
Result, TrueVal, ARMCC2, CCR, Cmp2);
}
@@ -2324,8 +2373,8 @@
ARMCC::CondCodes CondCode, CondCode2;
FPCCToARMCC(CC, CondCode, CondCode2);
- SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
+ SDValue Cmp = getVFPCmp(LHS, RHS, CC, ARMCC, DAG, dl);
SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
@@ -2413,7 +2462,7 @@
return DAG.getNode(Opc, dl, VT, Op);
}
-static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
+SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
// Implement fcopysign with a fabs and a conditional fneg.
SDValue Tmp0 = Op.getOperand(0);
SDValue Tmp1 = Op.getOperand(1);
@@ -2421,8 +2470,10 @@
EVT VT = Op.getValueType();
EVT SrcVT = Tmp1.getValueType();
SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
- SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG, dl);
SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
+ SDValue FP0 = DAG.getConstantFP(0.0, SrcVT);
+ SDValue Cmp = getVFPCmp(Tmp1, FP0,
+ ISD::SETLT, ARMCC, DAG, dl);
SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
}
@@ -3637,7 +3688,12 @@
MF->insert(It, loop1MBB);
MF->insert(It, loop2MBB);
MF->insert(It, exitMBB);
- exitMBB->transferSuccessors(BB);
+
+ // Transfer the remainder of BB and its successor edges to exitMBB.
+ exitMBB->splice(exitMBB->begin(), BB,
+ llvm::next(MachineBasicBlock::iterator(MI)),
+ BB->end());
+ exitMBB->transferSuccessorsAndUpdatePHIs(BB);
// thisMBB:
// ...
@@ -3675,7 +3731,7 @@
// ...
BB = exitMBB;
- MF->DeleteMachineInstr(MI); // The instruction is gone now.
+ MI->eraseFromParent(); // The instruction is gone now.
return BB;
}
@@ -3718,7 +3774,12 @@
MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
MF->insert(It, loopMBB);
MF->insert(It, exitMBB);
- exitMBB->transferSuccessors(BB);
+
+ // Transfer the remainder of BB and its successor edges to exitMBB.
+ exitMBB->splice(exitMBB->begin(), BB,
+ llvm::next(MachineBasicBlock::iterator(MI)),
+ BB->end());
+ exitMBB->transferSuccessorsAndUpdatePHIs(BB);
MachineRegisterInfo &RegInfo = MF->getRegInfo();
unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
@@ -3763,7 +3824,7 @@
// ...
BB = exitMBB;
- MF->DeleteMachineInstr(MI); // The instruction is gone now.
+ MI->eraseFromParent(); // The instruction is gone now.
return BB;
}
@@ -3848,22 +3909,21 @@
MachineFunction *F = BB->getParent();
MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
- BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
- .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
F->insert(It, copy0MBB);
F->insert(It, sinkMBB);
- // Update machine-CFG edges by first adding all successors of the current
- // block to the new block which will contain the Phi node for the select.
- for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
- E = BB->succ_end(); I != E; ++I)
- sinkMBB->addSuccessor(*I);
- // Next, remove all successors of the current block, and add the true
- // and fallthrough blocks as its successors.
- while (!BB->succ_empty())
- BB->removeSuccessor(BB->succ_begin());
+
+ // Transfer the remainder of BB and its successor edges to sinkMBB.
+ sinkMBB->splice(sinkMBB->begin(), BB,
+ llvm::next(MachineBasicBlock::iterator(MI)),
+ BB->end());
+ sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
+
BB->addSuccessor(copy0MBB);
BB->addSuccessor(sinkMBB);
+ BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
+ .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
+
// copy0MBB:
// %FalseValue = ...
// # fallthrough to sinkMBB
@@ -3876,11 +3936,12 @@
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
// ...
BB = sinkMBB;
- BuildMI(BB, dl, TII->get(ARM::PHI), MI->getOperand(0).getReg())
+ BuildMI(*BB, BB->begin(), dl,
+ TII->get(ARM::PHI), MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
- F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
+ MI->eraseFromParent(); // The pseudo instruction is gone now.
return BB;
}
@@ -3901,7 +3962,7 @@
const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(SrcReg);
unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
? ARM::tMOVtgpr2gpr : ARM::tMOVgpr2gpr;
- BuildMI(BB, dl, TII->get(CopyOpc), ARM::SP)
+ BuildMI(*BB, MI, dl, TII->get(CopyOpc), ARM::SP)
.addReg(SrcReg, getKillRegState(SrcIsKill));
}
@@ -3933,7 +3994,7 @@
NeedPred = true; NeedCC = true; NeedOp3 = true;
break;
}
- MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(OpOpc), ARM::SP);
+ MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(OpOpc), ARM::SP);
if (OpOpc == ARM::tAND)
AddDefaultT1CC(MIB);
MIB.addReg(ARM::SP);
@@ -3949,10 +4010,10 @@
const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(DstReg);
unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
? ARM::tMOVgpr2tgpr : ARM::tMOVgpr2gpr;
- BuildMI(BB, dl, TII->get(CopyOpc))
+ BuildMI(*BB, MI, dl, TII->get(CopyOpc))
.addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead))
.addReg(ARM::SP);
- MF->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
+ MI->eraseFromParent(); // The pseudo instruction is gone now.
return BB;
}
}
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMISelLowering.h?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMISelLowering.h (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMISelLowering.h Thu Jul 8 03:14:09 2010
@@ -313,6 +313,7 @@
SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
@@ -337,6 +338,7 @@
CallingConv::ID CallConv, bool isVarArg,
bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const;
@@ -350,16 +352,20 @@
bool isCalleeStructRet,
bool isCallerStructRet,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
SelectionDAG& DAG) const;
virtual SDValue
LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
DebugLoc dl, SelectionDAG &DAG) const;
SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
SDValue &ARMCC, SelectionDAG &DAG, DebugLoc dl) const;
+ SDValue getVFPCmp(SDValue &LHS, SDValue &RHS, ISD::CondCode CC,
+ SDValue &ARMCC, SelectionDAG &DAG, DebugLoc dl) const;
MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
MachineBasicBlock *BB,
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrInfo.td?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrInfo.td Thu Jul 8 03:14:09 2010
@@ -1049,6 +1049,10 @@
"@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>;
def TAILJMPd : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
+ IIC_Br, "b\t$dst @ TAILCALL",
+ []>, Requires<[IsDarwin]>;
+
+ def TAILJMPdt: ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
IIC_Br, "b.w\t$dst @ TAILCALL",
[]>, Requires<[IsDarwin]>;
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrNEON.td?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrNEON.td Thu Jul 8 03:14:09 2010
@@ -3291,22 +3291,16 @@
def VTBL2
: N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst),
(ins DPR:$tbl1, DPR:$tbl2, DPR:$src), NVTBLFrm, IIC_VTB2,
- "vtbl", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "",
- [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl2
- DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
+ "vtbl", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "", []>;
def VTBL3
: N3V<1,1,0b11,0b1010,0,0, (outs DPR:$dst),
(ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), NVTBLFrm, IIC_VTB3,
- "vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src", "",
- [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl3
- DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
+ "vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src", "", []>;
def VTBL4
: N3V<1,1,0b11,0b1011,0,0, (outs DPR:$dst),
(ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src),
NVTBLFrm, IIC_VTB4,
- "vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src", "",
- [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl4 DPR:$tbl1, DPR:$tbl2,
- DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
+ "vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src", "", []>;
} // hasExtraSrcRegAllocReq = 1
// VTBX : Vector Table Extension
@@ -3320,23 +3314,18 @@
def VTBX2
: N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst),
(ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), NVTBLFrm, IIC_VTBX2,
- "vtbx", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "$orig = $dst",
- [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx2
- DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
+ "vtbx", "8", "$dst, \\{$tbl1, $tbl2\\}, $src", "$orig = $dst", []>;
def VTBX3
: N3V<1,1,0b11,0b1010,1,0, (outs DPR:$dst),
(ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src),
NVTBLFrm, IIC_VTBX3,
- "vtbx", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src", "$orig = $dst",
- [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx3 DPR:$orig, DPR:$tbl1,
- DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
+ "vtbx", "8", "$dst, \\{$tbl1, $tbl2, $tbl3\\}, $src",
+ "$orig = $dst", []>;
def VTBX4
: N3V<1,1,0b11,0b1011,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1,
DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), NVTBLFrm, IIC_VTBX4,
"vtbx", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src",
- "$orig = $dst",
- [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx4 DPR:$orig, DPR:$tbl1,
- DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
+ "$orig = $dst", []>;
} // hasExtraSrcRegAllocReq = 1
//===----------------------------------------------------------------------===//
Propchange: llvm/branches/wendling/eh/lib/Target/ARM/AsmParser/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Target/ARM/AsmPrinter/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Modified: llvm/branches/wendling/eh/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Thu Jul 8 03:14:09 2010
@@ -602,8 +602,12 @@
O << "[" << getRegisterName(MO1.getReg());
if (MO2.getImm()) {
+ unsigned Align = MO2.getImm();
+ assert((Align == 8 || Align == 16 || Align == 32) &&
+ "unexpected NEON load/store alignment");
+ Align <<= 3;
// FIXME: Both darwin as and GNU as violate ARM docs here.
- O << ", :" << MO2.getImm();
+ O << ", :" << Align;
}
O << "]";
}
Propchange: llvm/branches/wendling/eh/lib/Target/ARM/Disassembler/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Modified: llvm/branches/wendling/eh/lib/Target/ARM/NEONMoveFix.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/NEONMoveFix.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/NEONMoveFix.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/NEONMoveFix.cpp Thu Jul 8 03:14:09 2010
@@ -105,8 +105,8 @@
unsigned MOReg = MO.getReg();
Defs[MOReg] = MI;
- // Catch subregs as well.
- for (const unsigned *R = TRI->getSubRegisters(MOReg); *R; ++R)
+ // Catch aliases as well.
+ for (const unsigned *R = TRI->getAliasSet(MOReg); *R; ++R)
Defs[*R] = MI;
}
}
Propchange: llvm/branches/wendling/eh/lib/Target/ARM/TargetInfo/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Target/Alpha/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -6,3 +6,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Modified: llvm/branches/wendling/eh/lib/Target/Alpha/AlphaISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/Alpha/AlphaISelLowering.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/Alpha/AlphaISelLowering.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/Alpha/AlphaISelLowering.cpp Thu Jul 8 03:14:09 2010
@@ -224,6 +224,7 @@
CallingConv::ID CallConv, bool isVarArg,
bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const {
@@ -251,7 +252,7 @@
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
CCValAssign &VA = ArgLocs[i];
- SDValue Arg = Outs[i].Val;
+ SDValue Arg = OutVals[i];
// Promote the value if needed.
switch (VA.getLocInfo()) {
@@ -470,6 +471,7 @@
AlphaTargetLowering::LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
DebugLoc dl, SelectionDAG &DAG) const {
SDValue Copy = DAG.getCopyToReg(Chain, dl, Alpha::R26,
@@ -483,7 +485,7 @@
break;
//return SDValue(); // ret void is legal
case 1: {
- EVT ArgVT = Outs[0].Val.getValueType();
+ EVT ArgVT = Outs[0].VT;
unsigned ArgReg;
if (ArgVT.isInteger())
ArgReg = Alpha::R0;
@@ -492,13 +494,13 @@
ArgReg = Alpha::F0;
}
Copy = DAG.getCopyToReg(Copy, dl, ArgReg,
- Outs[0].Val, Copy.getValue(1));
+ OutVals[0], Copy.getValue(1));
if (DAG.getMachineFunction().getRegInfo().liveout_empty())
DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg);
break;
}
case 2: {
- EVT ArgVT = Outs[0].Val.getValueType();
+ EVT ArgVT = Outs[0].VT;
unsigned ArgReg1, ArgReg2;
if (ArgVT.isInteger()) {
ArgReg1 = Alpha::R0;
@@ -509,13 +511,13 @@
ArgReg2 = Alpha::F1;
}
Copy = DAG.getCopyToReg(Copy, dl, ArgReg1,
- Outs[0].Val, Copy.getValue(1));
+ OutVals[0], Copy.getValue(1));
if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(),
DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg1)
== DAG.getMachineFunction().getRegInfo().liveout_end())
DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg1);
Copy = DAG.getCopyToReg(Copy, dl, ArgReg2,
- Outs[1].Val, Copy.getValue(1));
+ OutVals[1], Copy.getValue(1));
if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(),
DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg2)
== DAG.getMachineFunction().getRegInfo().liveout_end())
@@ -539,7 +541,7 @@
false, false, 0);
SDValue Tmp = DAG.getNode(ISD::ADD, dl, MVT::i64, VAListP,
DAG.getConstant(8, MVT::i64));
- SDValue Offset = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Base.getValue(1),
+ SDValue Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, dl, Base.getValue(1),
Tmp, NULL, 0, MVT::i32, false, false, 0);
DataPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Base, Offset);
if (N->getValueType(0).isFloatingPoint())
@@ -643,10 +645,12 @@
case ISD::GlobalAddress: {
GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
const GlobalValue *GV = GSDN->getGlobal();
- SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
+ SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i64,
+ GSDN->getOffset());
// FIXME there isn't really any debug info here
- // if (!GV->hasWeakLinkage() && !GV->isDeclaration() && !GV->hasLinkOnceLinkage()) {
+ // if (!GV->hasWeakLinkage() && !GV->isDeclaration()
+ // && !GV->hasLinkOnceLinkage()) {
if (GV->hasLocalLinkage()) {
SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, GA,
DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
@@ -702,7 +706,7 @@
SDValue Result;
if (Op.getValueType() == MVT::i32)
- Result = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Chain, DataPtr,
+ Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, dl, Chain, DataPtr,
NULL, 0, MVT::i32, false, false, 0);
else
Result = DAG.getLoad(Op.getValueType(), dl, Chain, DataPtr, NULL, 0,
@@ -722,7 +726,7 @@
false, false, 0);
SDValue NP = DAG.getNode(ISD::ADD, dl, MVT::i64, SrcP,
DAG.getConstant(8, MVT::i64));
- Val = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Result,
+ Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, dl, Result,
NP, NULL,0, MVT::i32, false, false, 0);
SDValue NPD = DAG.getNode(ISD::ADD, dl, MVT::i64, DestP,
DAG.getConstant(8, MVT::i64));
@@ -863,7 +867,10 @@
MachineBasicBlock *llscMBB = F->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
- sinkMBB->transferSuccessors(thisMBB);
+ sinkMBB->splice(sinkMBB->begin(), thisMBB,
+ llvm::next(MachineBasicBlock::iterator(MI)),
+ thisMBB->end());
+ sinkMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
F->insert(It, llscMBB);
F->insert(It, sinkMBB);
@@ -912,7 +919,7 @@
thisMBB->addSuccessor(llscMBB);
llscMBB->addSuccessor(llscMBB);
llscMBB->addSuccessor(sinkMBB);
- F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
+ MI->eraseFromParent(); // The pseudo instruction is gone now.
return sinkMBB;
}
Modified: llvm/branches/wendling/eh/lib/Target/Alpha/AlphaISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/Alpha/AlphaISelLowering.h?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/Alpha/AlphaISelLowering.h (original)
+++ llvm/branches/wendling/eh/lib/Target/Alpha/AlphaISelLowering.h Thu Jul 8 03:14:09 2010
@@ -121,6 +121,7 @@
LowerCall(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const;
@@ -129,6 +130,7 @@
LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
DebugLoc dl, SelectionDAG &DAG) const;
};
}
Propchange: llvm/branches/wendling/eh/lib/Target/Alpha/AsmPrinter/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Target/Alpha/TargetInfo/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Target/Blackfin/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -15,3 +15,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Target/Blackfin/AsmPrinter/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Modified: llvm/branches/wendling/eh/lib/Target/Blackfin/BlackfinISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/Blackfin/BlackfinISelLowering.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/Blackfin/BlackfinISelLowering.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/Blackfin/BlackfinISelLowering.cpp Thu Jul 8 03:14:09 2010
@@ -143,7 +143,7 @@
DebugLoc DL = Op.getDebugLoc();
const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
- Op = DAG.getTargetGlobalAddress(GV, MVT::i32);
+ Op = DAG.getTargetGlobalAddress(GV, DL, MVT::i32);
return DAG.getNode(BFISD::Wrapper, DL, MVT::i32, Op);
}
@@ -219,6 +219,7 @@
BlackfinTargetLowering::LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
DebugLoc dl, SelectionDAG &DAG) const {
// CCValAssign - represent the assignment of the return value to locations.
@@ -244,7 +245,7 @@
for (unsigned i = 0; i != RVLocs.size(); ++i) {
CCValAssign &VA = RVLocs[i];
assert(VA.isRegLoc() && "Can only return in registers!");
- SDValue Opi = Outs[i].Val;
+ SDValue Opi = OutVals[i];
// Expand to i32 if necessary
switch (VA.getLocInfo()) {
@@ -277,6 +278,7 @@
CallingConv::ID CallConv, bool isVarArg,
bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const {
@@ -300,7 +302,7 @@
// Walk the register/memloc assignments, inserting copies/loads.
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
CCValAssign &VA = ArgLocs[i];
- SDValue Arg = Outs[i].Val;
+ SDValue Arg = OutVals[i];
// Promote the value if needed.
switch (VA.getLocInfo()) {
@@ -356,7 +358,7 @@
// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
// Likewise ExternalSymbol -> TargetExternalSymbol.
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
- Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
+ Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32);
else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
Modified: llvm/branches/wendling/eh/lib/Target/Blackfin/BlackfinISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/Blackfin/BlackfinISelLowering.h?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/Blackfin/BlackfinISelLowering.h (original)
+++ llvm/branches/wendling/eh/lib/Target/Blackfin/BlackfinISelLowering.h Thu Jul 8 03:14:09 2010
@@ -63,6 +63,7 @@
LowerCall(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const;
@@ -71,6 +72,7 @@
LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
DebugLoc dl, SelectionDAG &DAG) const;
};
} // end namespace llvm
Propchange: llvm/branches/wendling/eh/lib/Target/Blackfin/TargetInfo/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Target/CBackend/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -6,3 +6,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Target/CBackend/TargetInfo/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Target/CellSPU/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -6,3 +6,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Target/CellSPU/AsmPrinter/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Modified: llvm/branches/wendling/eh/lib/Target/CellSPU/SPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/CellSPU/SPUISelLowering.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/CellSPU/SPUISelLowering.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/CellSPU/SPUISelLowering.cpp Thu Jul 8 03:14:09 2010
@@ -953,7 +953,8 @@
EVT PtrVT = Op.getValueType();
GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
const GlobalValue *GV = GSDN->getGlobal();
- SDValue GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
+ SDValue GA = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
+ PtrVT, GSDN->getOffset());
const TargetMachine &TM = DAG.getTarget();
SDValue Zero = DAG.getConstant(0, PtrVT);
// FIXME there is no actual debug info here
@@ -1134,6 +1135,7 @@
CallingConv::ID CallConv, bool isVarArg,
bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const {
@@ -1165,7 +1167,7 @@
SmallVector<SDValue, 8> MemOpChains;
for (unsigned i = 0; i != NumOps; ++i) {
- SDValue Arg = Outs[i].Val;
+ SDValue Arg = OutVals[i];
// PtrOff will be used to store the current argument to the stack if a
// register cannot be found for it.
@@ -1232,7 +1234,7 @@
const GlobalValue *GV = G->getGlobal();
EVT CalleeVT = Callee.getValueType();
SDValue Zero = DAG.getConstant(0, PtrVT);
- SDValue GA = DAG.getTargetGlobalAddress(GV, CalleeVT);
+ SDValue GA = DAG.getTargetGlobalAddress(GV, dl, CalleeVT);
if (!ST->usingLargeMem()) {
// Turn calls to targets that are defined (i.e., have bodies) into BRSL
@@ -1338,6 +1340,7 @@
SPUTargetLowering::LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
DebugLoc dl, SelectionDAG &DAG) const {
SmallVector<CCValAssign, 16> RVLocs;
@@ -1359,7 +1362,7 @@
CCValAssign &VA = RVLocs[i];
assert(VA.isRegLoc() && "Can only return in registers!");
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
- Outs[i].Val, Flag);
+ OutVals[i], Flag);
Flag = Chain.getValue(1);
}
Modified: llvm/branches/wendling/eh/lib/Target/CellSPU/SPUISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/CellSPU/SPUISelLowering.h?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/CellSPU/SPUISelLowering.h (original)
+++ llvm/branches/wendling/eh/lib/Target/CellSPU/SPUISelLowering.h Thu Jul 8 03:14:09 2010
@@ -159,6 +159,7 @@
CallingConv::ID CallConv, bool isVarArg,
bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const;
@@ -167,6 +168,7 @@
LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
DebugLoc dl, SelectionDAG &DAG) const;
};
}
Propchange: llvm/branches/wendling/eh/lib/Target/CellSPU/TargetInfo/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Target/CppBackend/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Target/CppBackend/TargetInfo/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Target/MBlaze/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -6,3 +6,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Target/MBlaze/AsmPrinter/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Modified: llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeISelLowering.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeISelLowering.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeISelLowering.cpp Thu Jul 8 03:14:09 2010
@@ -234,6 +234,24 @@
MachineRegisterInfo &R = F->getRegInfo();
MachineBasicBlock *loop = F->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *finish = F->CreateMachineBasicBlock(LLVM_BB);
+ F->insert(It, loop);
+ F->insert(It, finish);
+
+ // Update machine-CFG edges by transfering adding all successors and
+ // remaining instructions from the current block to the new block which
+ // will contain the Phi node for the select.
+ finish->splice(finish->begin(), BB,
+ llvm::next(MachineBasicBlock::iterator(MI)),
+ BB->end());
+ finish->transferSuccessorsAndUpdatePHIs(BB);
+
+ // Add the true and fallthrough blocks as its successors.
+ BB->addSuccessor(loop);
+ BB->addSuccessor(finish);
+
+ // Next, add the finish block as a successor of the loop block
+ loop->addSuccessor(finish);
+ loop->addSuccessor(loop);
unsigned IAMT = R.createVirtualRegister(MBlaze::CPURegsRegisterClass);
BuildMI(BB, dl, TII->get(MBlaze::ANDI), IAMT)
@@ -249,26 +267,6 @@
.addReg(IAMT)
.addMBB(finish);
- F->insert(It, loop);
- F->insert(It, finish);
-
- // Update machine-CFG edges by first adding all successors of the current
- // block to the new block which will contain the Phi node for the select.
- for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
- e = BB->succ_end(); i != e; ++i)
- finish->addSuccessor(*i);
-
- // Next, remove all successors of the current block, and add the true
- // and fallthrough blocks as its successors.
- while(!BB->succ_empty())
- BB->removeSuccessor(BB->succ_begin());
- BB->addSuccessor(loop);
- BB->addSuccessor(finish);
-
- // Next, add the finish block as a successor of the loop block
- loop->addSuccessor(finish);
- loop->addSuccessor(loop);
-
unsigned DST = R.createVirtualRegister(MBlaze::CPURegsRegisterClass);
unsigned NDST = R.createVirtualRegister(MBlaze::CPURegsRegisterClass);
BuildMI(loop, dl, TII->get(MBlaze::PHI), DST)
@@ -298,12 +296,13 @@
.addReg(NAMT)
.addMBB(loop);
- BuildMI(finish, dl, TII->get(MBlaze::PHI), MI->getOperand(0).getReg())
+ BuildMI(*finish, finish->begin(), dl,
+ TII->get(MBlaze::PHI), MI->getOperand(0).getReg())
.addReg(IVAL).addMBB(BB)
.addReg(NDST).addMBB(loop);
// The pseudo instruction is no longer needed so remove it
- F->DeleteMachineInstr(MI);
+ MI->eraseFromParent();
return finish;
}
@@ -338,27 +337,23 @@
case MBlazeCC::LE: Opc = MBlaze::BGTID; break;
}
- BuildMI(BB, dl, TII->get(Opc))
- .addReg(MI->getOperand(3).getReg())
- .addMBB(dneBB);
-
F->insert(It, flsBB);
F->insert(It, dneBB);
- // Update machine-CFG edges by first adding all successors of the current
- // block to the new block which will contain the Phi node for the select.
- for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
- e = BB->succ_end(); i != e; ++i)
- dneBB->addSuccessor(*i);
-
- // Next, remove all successors of the current block, and add the true
- // and fallthrough blocks as its successors.
- while(!BB->succ_empty())
- BB->removeSuccessor(BB->succ_begin());
+ // Transfer the remainder of BB and its successor edges to dneBB.
+ dneBB->splice(dneBB->begin(), BB,
+ llvm::next(MachineBasicBlock::iterator(MI)),
+ BB->end());
+ dneBB->transferSuccessorsAndUpdatePHIs(BB);
+
BB->addSuccessor(flsBB);
BB->addSuccessor(dneBB);
flsBB->addSuccessor(dneBB);
+ BuildMI(BB, dl, TII->get(Opc))
+ .addReg(MI->getOperand(3).getReg())
+ .addMBB(dneBB);
+
// sinkMBB:
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
// ...
@@ -366,11 +361,12 @@
// .addReg(MI->getOperand(1).getReg()).addMBB(flsBB)
// .addReg(MI->getOperand(2).getReg()).addMBB(BB);
- BuildMI(dneBB, dl, TII->get(MBlaze::PHI), MI->getOperand(0).getReg())
+ BuildMI(*dneBB, dneBB->begin(), dl,
+ TII->get(MBlaze::PHI), MI->getOperand(0).getReg())
.addReg(MI->getOperand(2).getReg()).addMBB(flsBB)
.addReg(MI->getOperand(1).getReg()).addMBB(BB);
- F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
+ MI->eraseFromParent(); // The pseudo instruction is gone now.
return dneBB;
}
}
@@ -408,7 +404,7 @@
// FIXME there isn't actually debug info here
DebugLoc dl = Op.getDebugLoc();
const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
- SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
+ SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32);
return DAG.getNode(MBlazeISD::Wrap, dl, MVT::i32, GA);
}
@@ -529,6 +525,7 @@
LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
bool isVarArg, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const {
@@ -560,7 +557,7 @@
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
CCValAssign &VA = ArgLocs[i];
EVT RegVT = VA.getLocVT();
- SDValue Arg = Outs[i].Val;
+ SDValue Arg = OutVals[i];
// Promote the value if needed.
switch (VA.getLocInfo()) {
@@ -621,7 +618,7 @@
// node so that legalize doesn't hack it.
unsigned char OpFlag = MBlazeII::MO_NO_FLAG;
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
- Callee = DAG.getTargetGlobalAddress(G->getGlobal(),
+ Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
getPointerTy(), 0, OpFlag);
else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
Callee = DAG.getTargetExternalSymbol(S->getSymbol(),
@@ -839,6 +836,7 @@
SDValue MBlazeTargetLowering::
LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
DebugLoc dl, SelectionDAG &DAG) const {
// CCValAssign - represent the assignment of
// the return value to a location
@@ -867,7 +865,7 @@
assert(VA.isRegLoc() && "Can only return in registers!");
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
- Outs[i].Val, Flag);
+ OutVals[i], Flag);
// guarantee that all emitted copies are
// stuck together, avoiding something bad
Modified: llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeISelLowering.h?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeISelLowering.h (original)
+++ llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeISelLowering.h Thu Jul 8 03:14:09 2010
@@ -109,6 +109,7 @@
CallingConv::ID CallConv, bool isVarArg,
bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const;
@@ -117,6 +118,7 @@
LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
DebugLoc dl, SelectionDAG &DAG) const;
virtual MachineBasicBlock *
Propchange: llvm/branches/wendling/eh/lib/Target/MBlaze/TargetInfo/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Target/MSIL/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Target/MSIL/TargetInfo/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Target/MSP430/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -6,3 +6,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Target/MSP430/AsmPrinter/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -6,3 +6,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Modified: llvm/branches/wendling/eh/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp Thu Jul 8 03:14:09 2010
@@ -272,7 +272,8 @@
AM.Base.Reg;
if (AM.GV)
- Disp = CurDAG->getTargetGlobalAddress(AM.GV, MVT::i16, AM.Disp,
+ Disp = CurDAG->getTargetGlobalAddress(AM.GV, Op->getDebugLoc(),
+ MVT::i16, AM.Disp,
0/*AM.SymbolFlags*/);
else if (AM.CP)
Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i16,
Modified: llvm/branches/wendling/eh/lib/Target/MSP430/MSP430ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/MSP430/MSP430ISelLowering.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/MSP430/MSP430ISelLowering.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/MSP430/MSP430ISelLowering.cpp Thu Jul 8 03:14:09 2010
@@ -278,6 +278,7 @@
CallingConv::ID CallConv, bool isVarArg,
bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const {
@@ -290,7 +291,7 @@
case CallingConv::Fast:
case CallingConv::C:
return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
- Outs, Ins, dl, DAG, InVals);
+ Outs, OutVals, Ins, dl, DAG, InVals);
case CallingConv::MSP430_INTR:
report_fatal_error("ISRs cannot be called directly");
return SDValue();
@@ -387,6 +388,7 @@
MSP430TargetLowering::LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
DebugLoc dl, SelectionDAG &DAG) const {
// CCValAssign - represent the assignment of the return value to a location
@@ -421,7 +423,7 @@
assert(VA.isRegLoc() && "Can only return in registers!");
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
- Outs[i].Val, Flag);
+ OutVals[i], Flag);
// Guarantee that all emitted copies are stuck together,
// avoiding something bad.
@@ -447,6 +449,7 @@
bool isTailCall,
const SmallVectorImpl<ISD::OutputArg>
&Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const {
@@ -471,7 +474,7 @@
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
CCValAssign &VA = ArgLocs[i];
- SDValue Arg = Outs[i].Val;
+ SDValue Arg = OutVals[i];
// Promote the value if needed.
switch (VA.getLocInfo()) {
@@ -529,7 +532,7 @@
// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
// Likewise ExternalSymbol -> TargetExternalSymbol.
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
- Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i16);
+ Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i16);
else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
@@ -642,7 +645,8 @@
int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
// Create the TargetGlobalAddress node, folding in the constant offset.
- SDValue Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
+ SDValue Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
+ getPointerTy(), Offset);
return DAG.getNode(MSP430ISD::Wrapper, Op.getDebugLoc(),
getPointerTy(), Result);
}
@@ -1070,7 +1074,10 @@
// Update machine-CFG edges by transferring all successors of the current
// block to the block containing instructions after shift.
- RemBB->transferSuccessors(BB);
+ RemBB->splice(RemBB->begin(), BB,
+ llvm::next(MachineBasicBlock::iterator(MI)),
+ BB->end());
+ RemBB->transferSuccessorsAndUpdatePHIs(BB);
// Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB
BB->addSuccessor(LoopBB);
@@ -1116,11 +1123,11 @@
// RemBB:
// DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
- BuildMI(RemBB, dl, TII.get(MSP430::PHI), DstReg)
+ BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg)
.addReg(SrcReg).addMBB(BB)
.addReg(ShiftReg2).addMBB(LoopBB);
- F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
+ MI->eraseFromParent(); // The pseudo instruction is gone now.
return RemBB;
}
@@ -1158,18 +1165,22 @@
MachineFunction *F = BB->getParent();
MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
- BuildMI(BB, dl, TII.get(MSP430::JCC))
- .addMBB(copy1MBB)
- .addImm(MI->getOperand(3).getImm());
F->insert(I, copy0MBB);
F->insert(I, copy1MBB);
// Update machine-CFG edges by transferring all successors of the current
// block to the new block which will contain the Phi node for the select.
- copy1MBB->transferSuccessors(BB);
+ copy1MBB->splice(copy1MBB->begin(), BB,
+ llvm::next(MachineBasicBlock::iterator(MI)),
+ BB->end());
+ copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
// Next, add the true and fallthrough blocks as its successors.
BB->addSuccessor(copy0MBB);
BB->addSuccessor(copy1MBB);
+ BuildMI(BB, dl, TII.get(MSP430::JCC))
+ .addMBB(copy1MBB)
+ .addImm(MI->getOperand(3).getImm());
+
// copy0MBB:
// %FalseValue = ...
// # fallthrough to copy1MBB
@@ -1182,11 +1193,11 @@
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
// ...
BB = copy1MBB;
- BuildMI(BB, dl, TII.get(MSP430::PHI),
+ BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI),
MI->getOperand(0).getReg())
.addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
.addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
- F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
+ MI->eraseFromParent(); // The pseudo instruction is gone now.
return BB;
}
Modified: llvm/branches/wendling/eh/lib/Target/MSP430/MSP430ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/MSP430/MSP430ISelLowering.h?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/MSP430/MSP430ISelLowering.h (original)
+++ llvm/branches/wendling/eh/lib/Target/MSP430/MSP430ISelLowering.h Thu Jul 8 03:14:09 2010
@@ -127,6 +127,7 @@
CallingConv::ID CallConv, bool isVarArg,
bool isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const;
@@ -155,6 +156,7 @@
LowerCall(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const;
@@ -163,6 +165,7 @@
LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
DebugLoc dl, SelectionDAG &DAG) const;
virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
Propchange: llvm/branches/wendling/eh/lib/Target/MSP430/TargetInfo/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Target/Mips/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -6,3 +6,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Target/Mips/AsmPrinter/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Modified: llvm/branches/wendling/eh/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/Mips/MipsISelLowering.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/Mips/MipsISelLowering.cpp Thu Jul 8 03:14:09 2010
@@ -284,6 +284,18 @@
MachineFunction *F = BB->getParent();
MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
+ F->insert(It, copy0MBB);
+ F->insert(It, sinkMBB);
+
+ // Transfer the remainder of BB and its successor edges to sinkMBB.
+ sinkMBB->splice(sinkMBB->begin(), BB,
+ llvm::next(MachineBasicBlock::iterator(MI)),
+ BB->end());
+ sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
+
+ // Next, add the true and fallthrough blocks as its successors.
+ BB->addSuccessor(copy0MBB);
+ BB->addSuccessor(sinkMBB);
// Emit the right instruction according to the type of the operands compared
if (isFPCmp) {
@@ -296,20 +308,6 @@
BuildMI(BB, dl, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
.addReg(Mips::ZERO).addMBB(sinkMBB);
- F->insert(It, copy0MBB);
- F->insert(It, sinkMBB);
- // Update machine-CFG edges by first adding all successors of the current
- // block to the new block which will contain the Phi node for the select.
- for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
- e = BB->succ_end(); i != e; ++i)
- sinkMBB->addSuccessor(*i);
- // Next, remove all successors of the current block, and add the true
- // and fallthrough blocks as its successors.
- while(!BB->succ_empty())
- BB->removeSuccessor(BB->succ_begin());
- BB->addSuccessor(copy0MBB);
- BB->addSuccessor(sinkMBB);
-
// copy0MBB:
// %FalseValue = ...
// # fallthrough to sinkMBB
@@ -322,11 +320,12 @@
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
// ...
BB = sinkMBB;
- BuildMI(BB, dl, TII->get(Mips::PHI), MI->getOperand(0).getReg())
+ BuildMI(*BB, BB->begin(), dl,
+ TII->get(Mips::PHI), MI->getOperand(0).getReg())
.addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
.addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
- F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
+ MI->eraseFromParent(); // The pseudo instruction is gone now.
return BB;
}
}
@@ -490,21 +489,21 @@
// %gp_rel relocation
if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
- SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32, 0,
+ SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
MipsII::MO_GPREL);
SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1);
SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode);
}
// %hi/%lo relocation
- SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32, 0,
+ SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
MipsII::MO_ABS_HILO);
SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GA, 1);
SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
} else {
- SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32, 0,
+ SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
MipsII::MO_GOT);
SDValue ResNode = DAG.getLoad(MVT::i32, dl,
DAG.getEntryNode(), GA, NULL, 0,
@@ -768,6 +767,7 @@
CallingConv::ID CallConv, bool isVarArg,
bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const {
@@ -808,7 +808,7 @@
// Walk the register/memloc assignments, inserting copies/loads.
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
- SDValue Arg = Outs[i].Val;
+ SDValue Arg = OutVals[i];
CCValAssign &VA = ArgLocs[i];
// Promote the value if needed.
@@ -889,7 +889,7 @@
// node so that legalize doesn't hack it.
unsigned char OpFlag = IsPIC ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG;
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
- Callee = DAG.getTargetGlobalAddress(G->getGlobal(),
+ Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
getPointerTy(), 0, OpFlag);
else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
Callee = DAG.getTargetExternalSymbol(S->getSymbol(),
@@ -1169,6 +1169,7 @@
MipsTargetLowering::LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
DebugLoc dl, SelectionDAG &DAG) const {
// CCValAssign - represent the assignment of
@@ -1198,7 +1199,7 @@
assert(VA.isRegLoc() && "Can only return in registers!");
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
- Outs[i].Val, Flag);
+ OutVals[i], Flag);
// guarantee that all emitted copies are
// stuck together, avoiding something bad
Modified: llvm/branches/wendling/eh/lib/Target/Mips/MipsISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/Mips/MipsISelLowering.h?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/Mips/MipsISelLowering.h (original)
+++ llvm/branches/wendling/eh/lib/Target/Mips/MipsISelLowering.h Thu Jul 8 03:14:09 2010
@@ -120,6 +120,7 @@
CallingConv::ID CallConv, bool isVarArg,
bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const;
@@ -128,6 +129,7 @@
LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
DebugLoc dl, SelectionDAG &DAG) const;
virtual MachineBasicBlock *
Propchange: llvm/branches/wendling/eh/lib/Target/Mips/TargetInfo/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Target/PIC16/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -6,3 +6,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Target/PIC16/AsmPrinter/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Modified: llvm/branches/wendling/eh/lib/Target/PIC16/PIC16ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/PIC16/PIC16ISelLowering.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/PIC16/PIC16ISelLowering.cpp Thu Jul 8 03:14:09 2010
@@ -672,7 +672,8 @@
// FIXME there isn't really debug info here
DebugLoc dl = G->getDebugLoc();
- SDValue TGA = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i8,
+ SDValue TGA = DAG.getTargetGlobalAddress(G->getGlobal(), N->getDebugLoc(),
+ MVT::i8,
G->getOffset());
SDValue Offset = DAG.getConstant(0, MVT::i8);
@@ -1120,6 +1121,7 @@
LowerIndirectCallArguments(SDValue Chain, SDValue InFlag,
SDValue DataAddr_Lo, SDValue DataAddr_Hi,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG) const {
unsigned NumOps = Outs.size();
@@ -1136,7 +1138,7 @@
unsigned RetVals = Ins.size();
for (unsigned i = 0, ArgOffset = RetVals; i < NumOps; i++) {
// Get the arguments
- Arg = Outs[i].Val;
+ Arg = OutVals[i];
Ops.clear();
Ops.push_back(Chain);
@@ -1158,6 +1160,7 @@
SDValue PIC16TargetLowering::
LowerDirectCallArguments(SDValue ArgLabel, SDValue Chain, SDValue InFlag,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
DebugLoc dl, SelectionDAG &DAG) const {
unsigned NumOps = Outs.size();
std::string Name;
@@ -1183,7 +1186,7 @@
SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
for (unsigned i=0, Offset = 0; i<NumOps; i++) {
// Get the argument
- Arg = Outs[i].Val;
+ Arg = OutVals[i];
StoreOffset = (Offset + AddressOffset);
// Store the argument on frame
@@ -1282,6 +1285,7 @@
PIC16TargetLowering::LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
DebugLoc dl, SelectionDAG &DAG) const {
// Number of values to return
@@ -1298,7 +1302,7 @@
SDValue BS = DAG.getConstant(1, MVT::i8);
SDValue RetVal;
for(unsigned i=0;i<NumRet; ++i) {
- RetVal = Outs[i].Val;
+ RetVal = OutVals[i];
Chain = DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other, Chain, RetVal,
ES, BS,
DAG.getConstant (i, MVT::i8));
@@ -1374,6 +1378,7 @@
CallingConv::ID CallConv, bool isVarArg,
bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const {
@@ -1428,7 +1433,7 @@
// Considering the GlobalAddressNode case here.
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
const GlobalValue *GV = G->getGlobal();
- Callee = DAG.getTargetGlobalAddress(GV, MVT::i8);
+ Callee = DAG.getTargetGlobalAddress(GV, dl, MVT::i8);
Name = G->getGlobal()->getName();
} else {// Considering the ExternalSymbol case here
ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Callee);
@@ -1461,12 +1466,13 @@
SDValue CallArgs;
if (IsDirectCall) {
CallArgs = LowerDirectCallArguments(ArgLabel, Chain, OperFlag,
- Outs, dl, DAG);
+ Outs, OutVals, dl, DAG);
Chain = getChain(CallArgs);
OperFlag = getOutFlag(CallArgs);
} else {
CallArgs = LowerIndirectCallArguments(Chain, OperFlag, DataAddr_Lo,
- DataAddr_Hi, Outs, Ins, dl, DAG);
+ DataAddr_Hi, Outs, OutVals, Ins,
+ dl, DAG);
Chain = getChain(CallArgs);
OperFlag = getOutFlag(CallArgs);
}
@@ -1928,15 +1934,12 @@
F->insert(It, copy0MBB);
F->insert(It, sinkMBB);
- // Update machine-CFG edges by first adding all successors of the current
- // block to the new block which will contain the Phi node for the select.
- for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
- E = BB->succ_end(); I != E; ++I)
- sinkMBB->addSuccessor(*I);
- // Next, remove all successors of the current block, and add the true
- // and fallthrough blocks as its successors.
- while (!BB->succ_empty())
- BB->removeSuccessor(BB->succ_begin());
+ // Transfer the remainder of BB and its successor edges to sinkMBB.
+ sinkMBB->splice(sinkMBB->begin(), BB,
+ llvm::next(MachineBasicBlock::iterator(MI)),
+ BB->end());
+ sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
+
// Next, add the true and fallthrough blocks as its successors.
BB->addSuccessor(copy0MBB);
BB->addSuccessor(sinkMBB);
@@ -1953,11 +1956,12 @@
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
// ...
BB = sinkMBB;
- BuildMI(BB, dl, TII.get(PIC16::PHI), MI->getOperand(0).getReg())
+ BuildMI(*BB, BB->begin(), dl,
+ TII.get(PIC16::PHI), MI->getOperand(0).getReg())
.addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
.addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
- F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
+ MI->eraseFromParent(); // The pseudo instruction is gone now.
return BB;
}
Modified: llvm/branches/wendling/eh/lib/Target/PIC16/PIC16ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/PIC16/PIC16ISelLowering.h?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/PIC16/PIC16ISelLowering.h (original)
+++ llvm/branches/wendling/eh/lib/Target/PIC16/PIC16ISelLowering.h Thu Jul 8 03:14:09 2010
@@ -106,12 +106,14 @@
SDValue
LowerDirectCallArguments(SDValue ArgLabel, SDValue Chain, SDValue InFlag,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
DebugLoc dl, SelectionDAG &DAG) const;
SDValue
LowerIndirectCallArguments(SDValue Chain, SDValue InFlag,
SDValue DataAddr_Lo, SDValue DataAddr_Hi,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG) const;
@@ -143,6 +145,7 @@
LowerCall(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const;
@@ -151,6 +154,7 @@
LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
DebugLoc dl, SelectionDAG &DAG) const;
SDValue ExpandStore(SDNode *N, SelectionDAG &DAG) const;
Propchange: llvm/branches/wendling/eh/lib/Target/PIC16/PIC16Passes/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Target/PIC16/TargetInfo/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Target/PowerPC/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -6,3 +6,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Target/PowerPC/AsmPrinter/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Modified: llvm/branches/wendling/eh/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/PowerPC/PPCISelLowering.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/PowerPC/PPCISelLowering.cpp Thu Jul 8 03:14:09 2010
@@ -1203,11 +1203,11 @@
SelectionDAG &DAG) const {
EVT PtrVT = Op.getValueType();
GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
- const GlobalValue *GV = GSDN->getGlobal();
- SDValue GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
- SDValue Zero = DAG.getConstant(0, PtrVT);
// FIXME there isn't really any debug info here
DebugLoc dl = GSDN->getDebugLoc();
+ const GlobalValue *GV = GSDN->getGlobal();
+ SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, GSDN->getOffset());
+ SDValue Zero = DAG.getConstant(0, PtrVT);
const TargetMachine &TM = DAG.getTarget();
@@ -2136,6 +2136,7 @@
unsigned CC,
const SmallVectorImpl<ISD::OutputArg>
&Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
unsigned &nAltivecParamsAtEnd) {
// Count how many bytes are to be pushed on the stack, including the linkage
// area, and parameter passing area. We start with 24/48 bytes, which is
@@ -2152,9 +2153,9 @@
// 16-byte aligned.
nAltivecParamsAtEnd = 0;
for (unsigned i = 0; i != NumOps; ++i) {
- SDValue Arg = Outs[i].Val;
+ SDValue Arg = OutVals[i];
ISD::ArgFlagsTy Flags = Outs[i].Flags;
- EVT ArgVT = Arg.getValueType();
+ EVT ArgVT = Outs[i].VT;
// Varargs Altivec parameters are padded to a 16 byte boundary.
if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
@@ -2470,7 +2471,8 @@
// direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
// node so that legalize doesn't hack it.
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
- Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
+ Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
+ Callee.getValueType());
else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
@@ -2703,6 +2705,7 @@
CallingConv::ID CallConv, bool isVarArg,
bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const {
@@ -2712,11 +2715,11 @@
if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) {
return LowerCall_SVR4(Chain, Callee, CallConv, isVarArg,
- isTailCall, Outs, Ins,
+ isTailCall, Outs, OutVals, Ins,
dl, DAG, InVals);
} else {
return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
- isTailCall, Outs, Ins,
+ isTailCall, Outs, OutVals, Ins,
dl, DAG, InVals);
}
}
@@ -2726,6 +2729,7 @@
CallingConv::ID CallConv, bool isVarArg,
bool isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const {
@@ -2766,7 +2770,7 @@
unsigned NumArgs = Outs.size();
for (unsigned i = 0; i != NumArgs; ++i) {
- EVT ArgVT = Outs[i].Val.getValueType();
+ EVT ArgVT = Outs[i].VT;
ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
bool Result;
@@ -2835,7 +2839,7 @@
i != e;
++i) {
CCValAssign &VA = ArgLocs[i];
- SDValue Arg = Outs[i].Val;
+ SDValue Arg = OutVals[i];
ISD::ArgFlagsTy Flags = Outs[i].Flags;
if (Flags.isByVal()) {
@@ -2931,6 +2935,7 @@
CallingConv::ID CallConv, bool isVarArg,
bool isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const {
@@ -2958,7 +2963,7 @@
// prereserved space for [SP][CR][LR][3 x unused].
unsigned NumBytes =
CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
- Outs,
+ Outs, OutVals,
nAltivecParamsAtEnd);
// Calculate by how many bytes the stack has to be adjusted in case of tail
@@ -3022,7 +3027,7 @@
SmallVector<SDValue, 8> MemOpChains;
for (unsigned i = 0; i != NumOps; ++i) {
- SDValue Arg = Outs[i].Val;
+ SDValue Arg = OutVals[i];
ISD::ArgFlagsTy Flags = Outs[i].Flags;
// PtrOff will be used to store the current argument to the stack if a
@@ -3048,7 +3053,7 @@
// Everything else is passed left-justified.
EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
if (GPR_idx != NumGPRs) {
- SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
+ SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, PtrVT, dl, Chain, Arg,
NULL, 0, VT, false, false, 0);
MemOpChains.push_back(Load.getValue(1));
RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
@@ -3225,8 +3230,8 @@
ArgOffset = ((ArgOffset+15)/16)*16;
ArgOffset += 12*16;
for (unsigned i = 0; i != NumOps; ++i) {
- SDValue Arg = Outs[i].Val;
- EVT ArgType = Arg.getValueType();
+ SDValue Arg = OutVals[i];
+ EVT ArgType = Outs[i].VT;
if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
if (++j > NumVRs) {
@@ -3294,6 +3299,7 @@
PPCTargetLowering::LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
DebugLoc dl, SelectionDAG &DAG) const {
SmallVector<CCValAssign, 16> RVLocs;
@@ -3315,7 +3321,7 @@
CCValAssign &VA = RVLocs[i];
assert(VA.isRegLoc() && "Can only return in registers!");
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
- Outs[i].Val, Flag);
+ OutVals[i], Flag);
Flag = Chain.getValue(1);
}
@@ -4513,7 +4519,10 @@
MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
F->insert(It, loopMBB);
F->insert(It, exitMBB);
- exitMBB->transferSuccessors(BB);
+ exitMBB->splice(exitMBB->begin(), BB,
+ llvm::next(MachineBasicBlock::iterator(MI)),
+ BB->end());
+ exitMBB->transferSuccessorsAndUpdatePHIs(BB);
MachineRegisterInfo &RegInfo = F->getRegInfo();
unsigned TmpReg = (!BinOpcode) ? incr :
@@ -4578,7 +4587,10 @@
MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
F->insert(It, loopMBB);
F->insert(It, exitMBB);
- exitMBB->transferSuccessors(BB);
+ exitMBB->splice(exitMBB->begin(), BB,
+ llvm::next(MachineBasicBlock::iterator(MI)),
+ BB->end());
+ exitMBB->transferSuccessorsAndUpdatePHIs(BB);
MachineRegisterInfo &RegInfo = F->getRegInfo();
const TargetRegisterClass *RC =
@@ -4711,23 +4723,22 @@
MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
unsigned SelectPred = MI->getOperand(4).getImm();
DebugLoc dl = MI->getDebugLoc();
- BuildMI(BB, dl, TII->get(PPC::BCC))
- .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
F->insert(It, copy0MBB);
F->insert(It, sinkMBB);
- // Update machine-CFG edges by first adding all successors of the current
- // block to the new block which will contain the Phi node for the select.
- for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
- E = BB->succ_end(); I != E; ++I)
- sinkMBB->addSuccessor(*I);
- // Next, remove all successors of the current block, and add the true
- // and fallthrough blocks as its successors.
- while (!BB->succ_empty())
- BB->removeSuccessor(BB->succ_begin());
+
+ // Transfer the remainder of BB and its successor edges to sinkMBB.
+ sinkMBB->splice(sinkMBB->begin(), BB,
+ llvm::next(MachineBasicBlock::iterator(MI)),
+ BB->end());
+ sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
+
// Next, add the true and fallthrough blocks as its successors.
BB->addSuccessor(copy0MBB);
BB->addSuccessor(sinkMBB);
+ BuildMI(BB, dl, TII->get(PPC::BCC))
+ .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
+
// copy0MBB:
// %FalseValue = ...
// # fallthrough to sinkMBB
@@ -4740,7 +4751,8 @@
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
// ...
BB = sinkMBB;
- BuildMI(BB, dl, TII->get(PPC::PHI), MI->getOperand(0).getReg())
+ BuildMI(*BB, BB->begin(), dl,
+ TII->get(PPC::PHI), MI->getOperand(0).getReg())
.addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
}
@@ -4826,7 +4838,10 @@
F->insert(It, loop2MBB);
F->insert(It, midMBB);
F->insert(It, exitMBB);
- exitMBB->transferSuccessors(BB);
+ exitMBB->splice(exitMBB->begin(), BB,
+ llvm::next(MachineBasicBlock::iterator(MI)),
+ BB->end());
+ exitMBB->transferSuccessorsAndUpdatePHIs(BB);
// thisMBB:
// ...
@@ -4894,7 +4909,10 @@
F->insert(It, loop2MBB);
F->insert(It, midMBB);
F->insert(It, exitMBB);
- exitMBB->transferSuccessors(BB);
+ exitMBB->splice(exitMBB->begin(), BB,
+ llvm::next(MachineBasicBlock::iterator(MI)),
+ BB->end());
+ exitMBB->transferSuccessorsAndUpdatePHIs(BB);
MachineRegisterInfo &RegInfo = F->getRegInfo();
const TargetRegisterClass *RC =
@@ -5020,7 +5038,7 @@
llvm_unreachable("Unexpected instr type to insert");
}
- F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
+ MI->eraseFromParent(); // The pseudo instruction is gone now.
return BB;
}
Modified: llvm/branches/wendling/eh/lib/Target/PowerPC/PPCISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/PowerPC/PPCISelLowering.h?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/PowerPC/PPCISelLowering.h (original)
+++ llvm/branches/wendling/eh/lib/Target/PowerPC/PPCISelLowering.h Thu Jul 8 03:14:09 2010
@@ -435,6 +435,7 @@
LowerCall(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const;
@@ -443,6 +444,7 @@
LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
DebugLoc dl, SelectionDAG &DAG) const;
SDValue
@@ -462,6 +464,7 @@
LowerCall_Darwin(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, bool isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const;
@@ -469,6 +472,7 @@
LowerCall_SVR4(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, bool isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const;
Propchange: llvm/branches/wendling/eh/lib/Target/PowerPC/TargetInfo/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Target/Sparc/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -6,3 +6,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Target/Sparc/AsmPrinter/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Modified: llvm/branches/wendling/eh/lib/Target/Sparc/SparcISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/Sparc/SparcISelLowering.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/Sparc/SparcISelLowering.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/Sparc/SparcISelLowering.cpp Thu Jul 8 03:14:09 2010
@@ -38,6 +38,7 @@
SparcTargetLowering::LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
DebugLoc dl, SelectionDAG &DAG) const {
// CCValAssign - represent the assignment of the return value to locations.
@@ -66,7 +67,7 @@
assert(VA.isRegLoc() && "Can only return in registers!");
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
- Outs[i].Val, Flag);
+ OutVals[i], Flag);
// Guarantee that all emitted copies are stuck together with flags.
Flag = Chain.getValue(1);
@@ -146,7 +147,7 @@
unsigned Offset = 4-std::max(1U, ObjectVT.getSizeInBits()/8);
FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr,
DAG.getConstant(Offset, MVT::i32));
- Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr,
+ Load = DAG.getExtLoad(LoadOp, MVT::i32, dl, Chain, FIPtr,
NULL, 0, ObjectVT, false, false, 0);
Load = DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, Load);
}
@@ -262,6 +263,7 @@
CallingConv::ID CallConv, bool isVarArg,
bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const {
@@ -283,7 +285,7 @@
// Count the size of the outgoing arguments.
unsigned ArgsSize = 0;
for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
- switch (Outs[i].Val.getValueType().getSimpleVT().SimpleTy) {
+ switch (Outs[i].VT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unknown value type!");
case MVT::i1:
case MVT::i8:
@@ -316,7 +318,7 @@
// Walk the register/memloc assignments, inserting copies/loads.
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
CCValAssign &VA = ArgLocs[i];
- SDValue Arg = Outs[i].Val;
+ SDValue Arg = OutVals[i];
// Promote the value if needed.
switch (VA.getLocInfo()) {
@@ -358,8 +360,8 @@
unsigned ArgOffset = 68;
for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
- SDValue Val = Outs[i].Val;
- EVT ObjectVT = Val.getValueType();
+ SDValue Val = OutVals[i];
+ EVT ObjectVT = Outs[i].VT;
SDValue ValToStore(0, 0);
unsigned ObjSize;
switch (ObjectVT.getSimpleVT().SimpleTy) {
@@ -478,7 +480,7 @@
// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
// Likewise ExternalSymbol -> TargetExternalSymbol.
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
- Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
+ Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32);
else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
@@ -759,7 +761,7 @@
const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
// FIXME there isn't really any debug info here
DebugLoc dl = Op.getDebugLoc();
- SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
+ SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32);
SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, GA);
SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, GA);
@@ -1007,21 +1009,20 @@
MachineFunction *F = BB->getParent();
MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
+
+ // Transfer the remainder of BB and its successor edges to sinkMBB.
+ sinkMBB->splice(sinkMBB->begin(), BB,
+ llvm::next(MachineBasicBlock::iterator(MI)),
+ BB->end());
+ sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
+
+ // Add the true and fallthrough blocks as its successors.
+ BB->addSuccessor(copy0MBB);
+ BB->addSuccessor(sinkMBB);
+
BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
F->insert(It, copy0MBB);
F->insert(It, sinkMBB);
- // Update machine-CFG edges by first adding all successors of the current
- // block to the new block which will contain the Phi node for the select.
- for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
- E = BB->succ_end(); I != E; ++I)
- sinkMBB->addSuccessor(*I);
- // Next, remove all successors of the current block, and add the true
- // and fallthrough blocks as its successors.
- while (!BB->succ_empty())
- BB->removeSuccessor(BB->succ_begin());
- // Next, add the true and fallthrough blocks as its successors.
- BB->addSuccessor(copy0MBB);
- BB->addSuccessor(sinkMBB);
// copy0MBB:
// %FalseValue = ...
@@ -1035,11 +1036,11 @@
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
// ...
BB = sinkMBB;
- BuildMI(BB, dl, TII.get(SP::PHI), MI->getOperand(0).getReg())
+ BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg())
.addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
.addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
- F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
+ MI->eraseFromParent(); // The pseudo instruction is gone now.
return BB;
}
Modified: llvm/branches/wendling/eh/lib/Target/Sparc/SparcISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/Sparc/SparcISelLowering.h?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/Sparc/SparcISelLowering.h (original)
+++ llvm/branches/wendling/eh/lib/Target/Sparc/SparcISelLowering.h Thu Jul 8 03:14:09 2010
@@ -86,6 +86,7 @@
CallingConv::ID CallConv, bool isVarArg,
bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const;
@@ -94,6 +95,7 @@
LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
DebugLoc dl, SelectionDAG &DAG) const;
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
Propchange: llvm/branches/wendling/eh/lib/Target/Sparc/TargetInfo/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Target/SystemZ/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -14,3 +14,5 @@
SystemZGenRegisterInfo.inc
SystemZGenRegisterNames.inc
SystemZGenSubtarget.inc
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Target/SystemZ/AsmPrinter/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Modified: llvm/branches/wendling/eh/lib/Target/SystemZ/SystemZISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/SystemZ/SystemZISelLowering.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/SystemZ/SystemZISelLowering.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/SystemZ/SystemZISelLowering.cpp Thu Jul 8 03:14:09 2010
@@ -254,6 +254,7 @@
CallingConv::ID CallConv, bool isVarArg,
bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const {
@@ -266,7 +267,7 @@
case CallingConv::Fast:
case CallingConv::C:
return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
- Outs, Ins, dl, DAG, InVals);
+ Outs, OutVals, Ins, dl, DAG, InVals);
}
}
@@ -372,6 +373,7 @@
bool isTailCall,
const SmallVectorImpl<ISD::OutputArg>
&Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const {
@@ -402,7 +404,7 @@
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
CCValAssign &VA = ArgLocs[i];
- SDValue Arg = Outs[i].Val;
+ SDValue Arg = OutVals[i];
// Promote the value if needed.
switch (VA.getLocInfo()) {
@@ -464,7 +466,7 @@
// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
// Likewise ExternalSymbol -> TargetExternalSymbol.
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
- Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
+ Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy());
else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy());
@@ -550,6 +552,7 @@
SystemZTargetLowering::LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
DebugLoc dl, SelectionDAG &DAG) const {
// CCValAssign - represent the assignment of the return value to a location
@@ -575,7 +578,7 @@
// Copy the result values into the output registers.
for (unsigned i = 0; i != RVLocs.size(); ++i) {
CCValAssign &VA = RVLocs[i];
- SDValue ResValue = Outs[i].Val;
+ SDValue ResValue = OutVals[i];
assert(VA.isRegLoc() && "Can only return in registers!");
// If this is an 8/16/32-bit value, it is really should be passed promoted
@@ -729,14 +732,14 @@
SDValue Result;
if (!IsPic && !ExtraLoadRequired) {
- Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
+ Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
Offset = 0;
} else {
unsigned char OpFlags = 0;
if (ExtraLoadRequired)
OpFlags = SystemZII::MO_GOTENT;
- Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
+ Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
}
Result = DAG.getNode(SystemZISD::PCRelativeWrapper, dl,
@@ -827,16 +830,20 @@
MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
SystemZCC::CondCodes CC = (SystemZCC::CondCodes)MI->getOperand(3).getImm();
- BuildMI(BB, dl, TII.getBrCond(CC)).addMBB(copy1MBB);
F->insert(I, copy0MBB);
F->insert(I, copy1MBB);
// Update machine-CFG edges by transferring all successors of the current
// block to the new block which will contain the Phi node for the select.
- copy1MBB->transferSuccessors(BB);
+ copy1MBB->splice(copy1MBB->begin(), BB,
+ llvm::next(MachineBasicBlock::iterator(MI)),
+ BB->end());
+ copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
// Next, add the true and fallthrough blocks as its successors.
BB->addSuccessor(copy0MBB);
BB->addSuccessor(copy1MBB);
+ BuildMI(BB, dl, TII.getBrCond(CC)).addMBB(copy1MBB);
+
// copy0MBB:
// %FalseValue = ...
// # fallthrough to copy1MBB
@@ -849,11 +856,11 @@
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
// ...
BB = copy1MBB;
- BuildMI(BB, dl, TII.get(SystemZ::PHI),
+ BuildMI(*BB, BB->begin(), dl, TII.get(SystemZ::PHI),
MI->getOperand(0).getReg())
.addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
.addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
- F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
+ MI->eraseFromParent(); // The pseudo instruction is gone now.
return BB;
}
Modified: llvm/branches/wendling/eh/lib/Target/SystemZ/SystemZISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/SystemZ/SystemZISelLowering.h?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/SystemZ/SystemZISelLowering.h (original)
+++ llvm/branches/wendling/eh/lib/Target/SystemZ/SystemZISelLowering.h Thu Jul 8 03:14:09 2010
@@ -98,6 +98,7 @@
CallingConv::ID CallConv, bool isVarArg,
bool isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const;
@@ -126,6 +127,7 @@
LowerCall(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const;
@@ -134,6 +136,7 @@
LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
DebugLoc dl, SelectionDAG &DAG) const;
const SystemZSubtarget &Subtarget;
Propchange: llvm/branches/wendling/eh/lib/Target/SystemZ/TargetInfo/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Modified: llvm/branches/wendling/eh/lib/Target/TargetRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/TargetRegisterInfo.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/TargetRegisterInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/TargetRegisterInfo.cpp Thu Jul 8 03:14:09 2010
@@ -61,7 +61,8 @@
}
/// getMinimalPhysRegClass - Returns the Register Class of a physical
-/// register of the given type.
+/// register of the given type, picking the most sub register class of
+/// the right type that contains this physreg.
const TargetRegisterClass *
TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const {
assert(isPhysicalRegister(reg) && "reg must be a physical register");
Propchange: llvm/branches/wendling/eh/lib/Target/X86/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -6,3 +6,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Target/X86/AsmParser/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Modified: llvm/branches/wendling/eh/lib/Target/X86/AsmParser/X86AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/AsmParser/X86AsmParser.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/AsmParser/X86AsmParser.cpp Thu Jul 8 03:14:09 2010
@@ -693,14 +693,38 @@
unsigned SSECCIdx = IsVCMP ? 4 : 3;
unsigned SSEComparisonCode = StringSwitch<unsigned>(
PatchedName.slice(SSECCIdx, PatchedName.size() - 2))
- .Case("eq", 0)
- .Case("lt", 1)
- .Case("le", 2)
- .Case("unord", 3)
- .Case("neq", 4)
- .Case("nlt", 5)
- .Case("nle", 6)
- .Case("ord", 7)
+ .Case("eq", 0)
+ .Case("lt", 1)
+ .Case("le", 2)
+ .Case("unord", 3)
+ .Case("neq", 4)
+ .Case("nlt", 5)
+ .Case("nle", 6)
+ .Case("ord", 7)
+ .Case("eq_uq", 8)
+ .Case("nge", 9)
+ .Case("ngt", 0x0A)
+ .Case("false", 0x0B)
+ .Case("neq_oq", 0x0C)
+ .Case("ge", 0x0D)
+ .Case("gt", 0x0E)
+ .Case("true", 0x0F)
+ .Case("eq_os", 0x10)
+ .Case("lt_oq", 0x11)
+ .Case("le_oq", 0x12)
+ .Case("unord_s", 0x13)
+ .Case("neq_us", 0x14)
+ .Case("nlt_uq", 0x15)
+ .Case("nle_uq", 0x16)
+ .Case("ord_s", 0x17)
+ .Case("eq_us", 0x18)
+ .Case("nge_uq", 0x19)
+ .Case("ngt_uq", 0x1A)
+ .Case("false_os", 0x1B)
+ .Case("neq_os", 0x1C)
+ .Case("ge_oq", 0x1D)
+ .Case("gt_oq", 0x1E)
+ .Case("true_us", 0x1F)
.Default(~0U);
if (SSEComparisonCode != ~0U) {
ExtraImmOp = MCConstantExpr::Create(SSEComparisonCode,
Propchange: llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Modified: llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp Thu Jul 8 03:14:09 2010
@@ -388,6 +388,8 @@
}
if (MO.isGlobal() || MO.isCPI() || MO.isJTI() || MO.isSymbol()) {
printSymbolOperand(MO, O);
+ if (Subtarget->isPICStyleRIPRel())
+ O << "(%rip)";
return false;
}
if (MO.isReg()) {
Modified: llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp Thu Jul 8 03:14:09 2010
@@ -505,8 +505,12 @@
O << V.getName();
O << " <- ";
// Frame address. Currently handles register +- offset only.
- assert(MI->getOperand(0).isReg() && MI->getOperand(3).isImm());
- O << '['; printOperand(MI, 0, O); O << '+'; printOperand(MI, 3, O);
+ O << '[';
+ if (MI->getOperand(0).isReg() && MI->getOperand(0).getReg())
+ printOperand(MI, 0, O);
+ else
+ O << "undef";
+ O << '+'; printOperand(MI, 3, O);
O << ']';
O << "+";
printOperand(MI, NOps-2, O);
@@ -517,8 +521,9 @@
MachineLocation Location;
assert (MI->getNumOperands() == 7 && "Invalid no. of machine operands!");
// Frame address. Currently handles register +- offset only.
- assert(MI->getOperand(0).isReg() && MI->getOperand(3).isImm());
- Location.set(MI->getOperand(0).getReg(), MI->getOperand(3).getImm());
+
+ if (MI->getOperand(0).isReg() && MI->getOperand(3).isImm())
+ Location.set(MI->getOperand(0).getReg(), MI->getOperand(3).getImm());
return Location;
}
Propchange: llvm/branches/wendling/eh/lib/Target/X86/Disassembler/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -6,3 +6,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Target/X86/TargetInfo/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86AsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86AsmBackend.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86AsmBackend.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86AsmBackend.cpp Thu Jul 8 03:14:09 2010
@@ -23,13 +23,13 @@
#include "llvm/Target/TargetAsmBackend.h"
using namespace llvm;
-namespace {
static unsigned getFixupKindLog2Size(unsigned Kind) {
switch (Kind) {
default: assert(0 && "invalid fixup kind!");
case X86::reloc_pcrel_1byte:
case FK_Data_1: return 0;
+ case X86::reloc_pcrel_2byte:
case FK_Data_2: return 1;
case X86::reloc_pcrel_4byte:
case X86::reloc_riprel_4byte:
@@ -39,6 +39,7 @@
}
}
+namespace {
class X86AsmBackend : public TargetAsmBackend {
public:
X86AsmBackend(const Target &T)
@@ -60,6 +61,7 @@
bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
};
+} // end anonymous namespace
static unsigned getRelaxedOpcode(unsigned Op) {
switch (Op) {
@@ -180,6 +182,7 @@
/* *** */
+namespace {
class ELFX86AsmBackend : public X86AsmBackend {
public:
ELFX86AsmBackend(const Target &T)
@@ -281,7 +284,7 @@
}
};
-}
+} // end anonymous namespace
TargetAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
const std::string &TT) {
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86FastISel.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86FastISel.cpp Thu Jul 8 03:14:09 2010
@@ -24,6 +24,7 @@
#include "llvm/Instructions.h"
#include "llvm/IntrinsicInst.h"
#include "llvm/CodeGen/FastISel.h"
+#include "llvm/CodeGen/FunctionLoweringInfo.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
@@ -52,20 +53,7 @@
bool X86ScalarSSEf32;
public:
- explicit X86FastISel(MachineFunction &mf,
- DenseMap<const Value *, unsigned> &vm,
- DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
- DenseMap<const AllocaInst *, int> &am,
- std::vector<std::pair<MachineInstr*, unsigned> > &pn
-#ifndef NDEBUG
- , SmallSet<const Instruction *, 8> &cil
-#endif
- )
- : FastISel(mf, vm, bm, am, pn
-#ifndef NDEBUG
- , cil
-#endif
- ) {
+ explicit X86FastISel(FunctionLoweringInfo &funcInfo) : FastISel(funcInfo) {
Subtarget = &TM.getSubtarget<X86Subtarget>();
StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
X86ScalarSSEf64 = Subtarget->hasSSE2();
@@ -345,7 +333,7 @@
// Don't walk into other basic blocks; it's possible we haven't
// visited them yet, so the instructions may not yet be assigned
// virtual registers.
- if (MBBMap[I->getParent()] != MBB)
+ if (FuncInfo.MBBMap[I->getParent()] != MBB)
return false;
Opcode = I->getOpcode();
@@ -382,8 +370,9 @@
case Instruction::Alloca: {
// Do static allocas.
const AllocaInst *A = cast<AllocaInst>(V);
- DenseMap<const AllocaInst*, int>::iterator SI = StaticAllocaMap.find(A);
- if (SI != StaticAllocaMap.end()) {
+ DenseMap<const AllocaInst*, int>::iterator SI =
+ FuncInfo.StaticAllocaMap.find(A);
+ if (SI != FuncInfo.StaticAllocaMap.end()) {
AM.BaseType = X86AddressMode::FrameIndexBase;
AM.Base.FrameIndex = SI->second;
return true;
@@ -498,7 +487,7 @@
// If this reference is relative to the pic base, set it now.
if (isGlobalRelativeToPICBase(GVFlags)) {
// FIXME: How do we know Base.Reg is free??
- AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(&MF);
+ AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
}
// Unless the ABI requires an extra load, return a direct reference to
@@ -844,8 +833,8 @@
// Unconditional branches are selected by tablegen-generated code.
// Handle a conditional branch.
const BranchInst *BI = cast<BranchInst>(I);
- MachineBasicBlock *TrueMBB = MBBMap[BI->getSuccessor(0)];
- MachineBasicBlock *FalseMBB = MBBMap[BI->getSuccessor(1)];
+ MachineBasicBlock *TrueMBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
+ MachineBasicBlock *FalseMBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
// Fold the common case of a conditional branch with a comparison.
if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
@@ -1511,7 +1500,7 @@
// GOT pointer.
if (Subtarget->isPICStyleGOT()) {
TargetRegisterClass *RC = X86::GR32RegisterClass;
- unsigned Base = getInstrInfo()->getGlobalBaseReg(&MF);
+ unsigned Base = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), X86::EBX, Base, RC, RC,
DL);
assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
@@ -1758,10 +1747,10 @@
unsigned char OpFlag = 0;
if (Subtarget->isPICStyleStubPIC()) { // Not dynamic-no-pic
OpFlag = X86II::MO_PIC_BASE_OFFSET;
- PICBase = getInstrInfo()->getGlobalBaseReg(&MF);
+ PICBase = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
} else if (Subtarget->isPICStyleGOT()) {
OpFlag = X86II::MO_GOTOFF;
- PICBase = getInstrInfo()->getGlobalBaseReg(&MF);
+ PICBase = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
} else if (Subtarget->isPICStyleRIPRel() &&
TM.getCodeModel() == CodeModel::Small) {
PICBase = X86::RIP;
@@ -1784,7 +1773,7 @@
// various places, but TargetMaterializeAlloca also needs a check
// in order to avoid recursion between getRegForValue,
// X86SelectAddrss, and TargetMaterializeAlloca.
- if (!StaticAllocaMap.count(C))
+ if (!FuncInfo.StaticAllocaMap.count(C))
return 0;
X86AddressMode AM;
@@ -1798,19 +1787,7 @@
}
namespace llvm {
- llvm::FastISel *X86::createFastISel(MachineFunction &mf,
- DenseMap<const Value *, unsigned> &vm,
- DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
- DenseMap<const AllocaInst *, int> &am,
- std::vector<std::pair<MachineInstr*, unsigned> > &pn
-#ifndef NDEBUG
- , SmallSet<const Instruction *, 8> &cil
-#endif
- ) {
- return new X86FastISel(mf, vm, bm, am, pn
-#ifndef NDEBUG
- , cil
-#endif
- );
+ llvm::FastISel *X86::createFastISel(FunctionLoweringInfo &funcInfo) {
+ return new X86FastISel(funcInfo);
}
}
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86FixupKinds.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86FixupKinds.h?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86FixupKinds.h (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86FixupKinds.h Thu Jul 8 03:14:09 2010
@@ -17,6 +17,7 @@
enum Fixups {
reloc_pcrel_4byte = FirstTargetFixupKind, // 32-bit pcrel, e.g. a branch.
reloc_pcrel_1byte, // 8-bit pcrel, e.g. branch_1
+ reloc_pcrel_2byte, // 16-bit pcrel, e.g. callw
reloc_riprel_4byte, // 32-bit rip-relative
reloc_riprel_4byte_movq_load // 32-bit rip-relative in movq
};
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86ISelDAGToDAG.cpp Thu Jul 8 03:14:09 2010
@@ -223,7 +223,8 @@
// These are 32-bit even in 64-bit mode since RIP relative offset
// is 32-bit.
if (AM.GV)
- Disp = CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp,
+ Disp = CurDAG->getTargetGlobalAddress(AM.GV, DebugLoc(),
+ MVT::i32, AM.Disp,
AM.SymbolFlags);
else if (AM.CP)
Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32,
@@ -499,7 +500,7 @@
N->getOperand(0),
MemTmp, NULL, 0, MemVT,
false, false, 0);
- SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp,
+ SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, DstVT, dl, Store, MemTmp,
NULL, 0, MemVT, false, false, 0);
// We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86ISelLowering.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86ISelLowering.cpp Thu Jul 8 03:14:09 2010
@@ -1220,10 +1220,10 @@
X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<EVT> &OutTys,
const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
- SelectionDAG &DAG) const {
+ LLVMContext &Context) const {
SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
- RVLocs, *DAG.getContext());
+ RVLocs, Context);
return CCInfo.CheckReturn(OutTys, ArgsFlags, RetCC_X86);
}
@@ -1231,6 +1231,7 @@
X86TargetLowering::LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
DebugLoc dl, SelectionDAG &DAG) const {
MachineFunction &MF = DAG.getMachineFunction();
X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
@@ -1258,7 +1259,7 @@
for (unsigned i = 0; i != RVLocs.size(); ++i) {
CCValAssign &VA = RVLocs[i];
assert(VA.isRegLoc() && "Can only return in registers!");
- SDValue ValToCopy = Outs[i].Val;
+ SDValue ValToCopy = OutVals[i];
// Returns in ST0/ST1 are handled specially: these are pushed as operands to
// the RET instruction and handled by the FP Stackifier.
@@ -1816,6 +1817,7 @@
CallingConv::ID CallConv, bool isVarArg,
bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const {
@@ -1828,7 +1830,7 @@
// Check if it's really possible to do a tail call.
isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
- Outs, Ins, DAG);
+ Outs, OutVals, Ins, DAG);
// Sibcalls are automatically detected tailcalls which do not require
// ABI changes.
@@ -1888,7 +1890,7 @@
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
CCValAssign &VA = ArgLocs[i];
EVT RegVT = VA.getLocVT();
- SDValue Arg = Outs[i].Val;
+ SDValue Arg = OutVals[i];
ISD::ArgFlagsTy Flags = Outs[i].Flags;
bool isByVal = Flags.isByVal();
@@ -2027,7 +2029,7 @@
if (VA.isRegLoc())
continue;
assert(VA.isMemLoc());
- SDValue Arg = Outs[i].Val;
+ SDValue Arg = OutVals[i];
ISD::ArgFlagsTy Flags = Outs[i].Flags;
// Create frame index.
int32_t Offset = VA.getLocMemOffset()+FPDiff;
@@ -2107,7 +2109,7 @@
OpFlags = X86II::MO_DARWIN_STUB;
}
- Callee = DAG.getTargetGlobalAddress(GV, getPointerTy(),
+ Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
G->getOffset(), OpFlags);
}
} else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
@@ -2320,6 +2322,7 @@
bool isCalleeStructRet,
bool isCallerStructRet,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
SelectionDAG& DAG) const {
if (!IsTailCallConvention(CalleeCC) &&
@@ -2433,7 +2436,7 @@
((X86TargetMachine&)getTargetMachine()).getInstrInfo();
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
CCValAssign &VA = ArgLocs[i];
- SDValue Arg = Outs[i].Val;
+ SDValue Arg = OutVals[i];
ISD::ArgFlagsTy Flags = Outs[i].Flags;
if (VA.getLocInfo() == CCValAssign::Indirect)
return false;
@@ -2468,20 +2471,8 @@
}
FastISel *
-X86TargetLowering::createFastISel(MachineFunction &mf,
- DenseMap<const Value *, unsigned> &vm,
- DenseMap<const BasicBlock*, MachineBasicBlock*> &bm,
- DenseMap<const AllocaInst *, int> &am,
- std::vector<std::pair<MachineInstr*, unsigned> > &pn
-#ifndef NDEBUG
- , SmallSet<const Instruction *, 8> &cil
-#endif
- ) const {
- return X86::createFastISel(mf, vm, bm, am, pn
-#ifndef NDEBUG
- , cil
-#endif
- );
+X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
+ return X86::createFastISel(funcInfo);
}
@@ -5248,10 +5239,10 @@
if (OpFlags == X86II::MO_NO_FLAG &&
X86::isOffsetSuitableForCodeModel(Offset, M)) {
// A direct static reference to a global.
- Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
+ Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
Offset = 0;
} else {
- Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
+ Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
}
if (Subtarget->isPICStyleRIPRel() &&
@@ -5296,7 +5287,7 @@
MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
DebugLoc dl = GA->getDebugLoc();
- SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
+ SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
GA->getValueType(0),
GA->getOffset(),
OperandFlags);
@@ -5369,7 +5360,8 @@
// emit "addl x at ntpoff,%eax" (local exec) or "addl x at indntpoff,%eax" (initial
// exec)
- SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
+ SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
+ GA->getValueType(0),
GA->getOffset(), OperandFlags);
SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
@@ -5426,12 +5418,10 @@
OpFlag = X86II::MO_TLVP_PIC_BASE;
else
OpFlag = X86II::MO_TLVP;
-
- SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(),
+ DebugLoc DL = Op.getDebugLoc();
+ SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
getPointerTy(),
GA->getOffset(), OpFlag);
-
- DebugLoc DL = Op.getDebugLoc();
SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
// With PIC32, the address is actually $g + Offset.
@@ -5780,7 +5770,7 @@
// Load the value out, extending it from f32 to f80.
// FIXME: Avoid the extend by constructing the right constant pool?
- SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
+ SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, MVT::f80, dl, DAG.getEntryNode(),
FudgePtr, PseudoSourceValue::getConstantPool(),
0, MVT::f32, false, false, 4);
// Extend everything to 80 bits to force it to be done on x87.
@@ -8023,8 +8013,11 @@
F->insert(MBBIter, newMBB);
F->insert(MBBIter, nextMBB);
- // Move all successors to thisMBB to nextMBB
- nextMBB->transferSuccessors(thisMBB);
+ // Transfer the remainder of thisMBB and its successor edges to nextMBB.
+ nextMBB->splice(nextMBB->begin(), thisMBB,
+ llvm::next(MachineBasicBlock::iterator(bInstr)),
+ thisMBB->end());
+ nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
// Update thisMBB to fall through to newMBB
thisMBB->addSuccessor(newMBB);
@@ -8087,7 +8080,7 @@
// insert branch
BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
- F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
+ bInstr->eraseFromParent(); // The pseudo instruction is gone now.
return nextMBB;
}
@@ -8132,8 +8125,11 @@
F->insert(MBBIter, newMBB);
F->insert(MBBIter, nextMBB);
- // Move all successors to thisMBB to nextMBB
- nextMBB->transferSuccessors(thisMBB);
+ // Transfer the remainder of thisMBB and its successor edges to nextMBB.
+ nextMBB->splice(nextMBB->begin(), thisMBB,
+ llvm::next(MachineBasicBlock::iterator(bInstr)),
+ thisMBB->end());
+ nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
// Update thisMBB to fall through to newMBB
thisMBB->addSuccessor(newMBB);
@@ -8250,7 +8246,7 @@
// insert branch
BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
- F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
+ bInstr->eraseFromParent(); // The pseudo instruction is gone now.
return nextMBB;
}
@@ -8284,8 +8280,11 @@
F->insert(MBBIter, newMBB);
F->insert(MBBIter, nextMBB);
- // Move all successors of thisMBB to nextMBB
- nextMBB->transferSuccessors(thisMBB);
+ // Transfer the remainder of thisMBB and its successor edges to nextMBB.
+ nextMBB->splice(nextMBB->begin(), thisMBB,
+ llvm::next(MachineBasicBlock::iterator(mInstr)),
+ thisMBB->end());
+ nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
// Update thisMBB to fall through to newMBB
thisMBB->addSuccessor(newMBB);
@@ -8353,7 +8352,7 @@
// insert branch
BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
- F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
+ mInstr->eraseFromParent(); // The pseudo instruction is gone now.
return nextMBB;
}
@@ -8363,7 +8362,6 @@
X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
unsigned numArgs, bool memArg) const {
- MachineFunction *F = BB->getParent();
DebugLoc dl = MI->getDebugLoc();
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
@@ -8385,7 +8383,7 @@
BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
.addReg(X86::XMM0);
- F->DeleteMachineInstr(MI);
+ MI->eraseFromParent();
return BB;
}
@@ -8414,9 +8412,12 @@
F->insert(MBBIter, XMMSaveMBB);
F->insert(MBBIter, EndMBB);
- // Set up the CFG.
- // Move any original successors of MBB to the end block.
- EndMBB->transferSuccessors(MBB);
+ // Transfer the remainder of MBB and its successor edges to EndMBB.
+ EndMBB->splice(EndMBB->begin(), MBB,
+ llvm::next(MachineBasicBlock::iterator(MI)),
+ MBB->end());
+ EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
+
// The original block will now fall through to the XMM save block.
MBB->addSuccessor(XMMSaveMBB);
// The XMMSaveMBB will fall through to the end block.
@@ -8455,7 +8456,7 @@
.addMemOperand(MMO);
}
- F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
+ MI->eraseFromParent(); // The pseudo instruction is gone now.
return EndMBB;
}
@@ -8484,44 +8485,39 @@
MachineFunction *F = BB->getParent();
MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
- unsigned Opc =
- X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
-
- BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
F->insert(It, copy0MBB);
F->insert(It, sinkMBB);
- // Update machine-CFG edges by first adding all successors of the current
- // block to the new block which will contain the Phi node for the select.
- for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
- E = BB->succ_end(); I != E; ++I)
- sinkMBB->addSuccessor(*I);
-
- // Next, remove all successors of the current block, and add the true
- // and fallthrough blocks as its successors.
- while (!BB->succ_empty())
- BB->removeSuccessor(BB->succ_begin());
-
- // Add the true and fallthrough blocks as its successors.
- BB->addSuccessor(copy0MBB);
- BB->addSuccessor(sinkMBB);
-
// If the EFLAGS register isn't dead in the terminator, then claim that it's
// live into the sink and copy blocks.
const MachineFunction *MF = BB->getParent();
const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
BitVector ReservedRegs = TRI->getReservedRegs(*MF);
- const MachineInstr *Term = BB->getFirstTerminator();
- for (unsigned I = 0, E = Term->getNumOperands(); I != E; ++I) {
- const MachineOperand &MO = Term->getOperand(I);
- if (!MO.isReg() || MO.isKill() || MO.isDead()) continue;
+ for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
+ const MachineOperand &MO = MI->getOperand(I);
+ if (!MO.isReg() || !MO.isUse() || MO.isKill()) continue;
unsigned Reg = MO.getReg();
if (Reg != X86::EFLAGS) continue;
copy0MBB->addLiveIn(Reg);
sinkMBB->addLiveIn(Reg);
}
+ // Transfer the remainder of BB and its successor edges to sinkMBB.
+ sinkMBB->splice(sinkMBB->begin(), BB,
+ llvm::next(MachineBasicBlock::iterator(MI)),
+ BB->end());
+ sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
+
+ // Add the true and fallthrough blocks as its successors.
+ BB->addSuccessor(copy0MBB);
+ BB->addSuccessor(sinkMBB);
+
+ // Create the conditional branch instruction.
+ unsigned Opc =
+ X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
+ BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
+
// copy0MBB:
// %FalseValue = ...
// # fallthrough to sinkMBB
@@ -8530,11 +8526,12 @@
// sinkMBB:
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
// ...
- BuildMI(sinkMBB, DL, TII->get(X86::PHI), MI->getOperand(0).getReg())
+ BuildMI(*sinkMBB, sinkMBB->begin(), DL,
+ TII->get(X86::PHI), MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
- F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
+ MI->eraseFromParent(); // The pseudo instruction is gone now.
return sinkMBB;
}
@@ -8543,21 +8540,20 @@
MachineBasicBlock *BB) const {
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
DebugLoc DL = MI->getDebugLoc();
- MachineFunction *F = BB->getParent();
// The lowering is pretty easy: we're just emitting the call to _alloca. The
// non-trivial part is impdef of ESP.
// FIXME: The code should be tweaked as soon as we'll try to do codegen for
// mingw-w64.
- BuildMI(BB, DL, TII->get(X86::CALLpcrel32))
+ BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
.addExternalSymbol("_alloca")
.addReg(X86::EAX, RegState::Implicit)
.addReg(X86::ESP, RegState::Implicit)
.addReg(X86::EAX, RegState::Define | RegState::Implicit)
.addReg(X86::ESP, RegState::Define | RegState::Implicit);
- F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
+ MI->eraseFromParent(); // The pseudo instruction is gone now.
return BB;
}
@@ -8576,35 +8572,38 @@
assert(MI->getOperand(3).isGlobal() && "This should be a global");
if (Subtarget->is64Bit()) {
- MachineInstrBuilder MIB = BuildMI(BB, DL, TII->get(X86::MOV64rm), X86::RDI)
+ MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
+ TII->get(X86::MOV64rm), X86::RDI)
.addReg(X86::RIP)
.addImm(0).addReg(0)
.addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
MI->getOperand(3).getTargetFlags())
.addReg(0);
- MIB = BuildMI(BB, DL, TII->get(X86::CALL64m));
+ MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
addDirectMem(MIB, X86::RDI).addReg(0);
} else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
- MachineInstrBuilder MIB = BuildMI(BB, DL, TII->get(X86::MOV32rm), X86::EAX)
+ MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
+ TII->get(X86::MOV32rm), X86::EAX)
.addReg(0)
.addImm(0).addReg(0)
.addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
MI->getOperand(3).getTargetFlags())
.addReg(0);
- MIB = BuildMI(BB, DL, TII->get(X86::CALL32m));
+ MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
addDirectMem(MIB, X86::EAX).addReg(0);
} else {
- MachineInstrBuilder MIB = BuildMI(BB, DL, TII->get(X86::MOV32rm), X86::EAX)
+ MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
+ TII->get(X86::MOV32rm), X86::EAX)
.addReg(TII->getGlobalBaseReg(F))
.addImm(0).addReg(0)
.addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
MI->getOperand(3).getTargetFlags())
.addReg(0);
- MIB = BuildMI(BB, DL, TII->get(X86::CALL32m));
+ MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
addDirectMem(MIB, X86::EAX).addReg(0);
}
- F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
+ MI->eraseFromParent(); // The pseudo instruction is gone now.
return BB;
}
@@ -8648,23 +8647,25 @@
// mode when truncating to an integer value.
MachineFunction *F = BB->getParent();
int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
- addFrameReference(BuildMI(BB, DL, TII->get(X86::FNSTCW16m)), CWFrameIdx);
+ addFrameReference(BuildMI(*BB, MI, DL,
+ TII->get(X86::FNSTCW16m)), CWFrameIdx);
// Load the old value of the high byte of the control word...
unsigned OldCW =
F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
- addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16rm), OldCW),
+ addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
CWFrameIdx);
// Set the high part to be round to zero...
- addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
+ addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
.addImm(0xC7F);
// Reload the modified control word now...
- addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
+ addFrameReference(BuildMI(*BB, MI, DL,
+ TII->get(X86::FLDCW16m)), CWFrameIdx);
// Restore the memory image of control word to original value
- addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
+ addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
.addReg(OldCW);
// Get the X86 opcode to use.
@@ -8703,13 +8704,14 @@
} else {
AM.Disp = Op.getImm();
}
- addFullAddress(BuildMI(BB, DL, TII->get(Opc)), AM)
+ addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
.addReg(MI->getOperand(X86AddrNumOperands).getReg());
// Reload the original control word now.
- addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
+ addFrameReference(BuildMI(*BB, MI, DL,
+ TII->get(X86::FLDCW16m)), CWFrameIdx);
- F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
+ MI->eraseFromParent(); // The pseudo instruction is gone now.
return BB;
}
// String/text processing lowering.
@@ -10253,8 +10255,7 @@
// In any sort of PIC mode addresses need to be computed at runtime by
// adding in a register or some sort of table lookup. These can't
// be used as immediates.
- if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC() ||
- Subtarget->isPICStyleRIPRel())
+ if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
return;
// If we are in non-pic codegen mode, we allow the address of a global (with
@@ -10292,7 +10293,8 @@
getTargetMachine())))
return;
- Result = DAG.getTargetGlobalAddress(GV, GA->getValueType(0), Offset);
+ Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
+ GA->getValueType(0), Offset);
break;
}
}
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86ISelLowering.h?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86ISelLowering.h Thu Jul 8 03:14:09 2010
@@ -579,16 +579,7 @@
/// createFastISel - This method returns a target specific FastISel object,
/// or null if the target does not support "fast" ISel.
- virtual FastISel *
- createFastISel(MachineFunction &mf,
- DenseMap<const Value *, unsigned> &,
- DenseMap<const BasicBlock *, MachineBasicBlock *> &,
- DenseMap<const AllocaInst *, int> &,
- std::vector<std::pair<MachineInstr*, unsigned> > &
-#ifndef NDEBUG
- , SmallSet<const Instruction *, 8> &
-#endif
- ) const;
+ virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
/// getFunctionAlignment - Return the Log2 alignment of this function.
virtual unsigned getFunctionAlignment(const Function *F) const;
@@ -652,6 +643,7 @@
bool isCalleeStructRet,
bool isCallerStructRet,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
SelectionDAG& DAG) const;
bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
@@ -734,6 +726,7 @@
LowerCall(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const;
@@ -742,13 +735,14 @@
LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
DebugLoc dl, SelectionDAG &DAG) const;
virtual bool
CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<EVT> &OutTys,
const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
- SelectionDAG &DAG) const;
+ LLVMContext &Context) const;
void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl<SDValue> &Results,
SelectionDAG &DAG, unsigned NewOp) const;
@@ -818,15 +812,7 @@
};
namespace X86 {
- FastISel *createFastISel(MachineFunction &mf,
- DenseMap<const Value *, unsigned> &,
- DenseMap<const BasicBlock *, MachineBasicBlock *> &,
- DenseMap<const AllocaInst *, int> &,
- std::vector<std::pair<MachineInstr*, unsigned> > &
-#ifndef NDEBUG
- , SmallSet<const Instruction*, 8> &
-#endif
- );
+ FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
}
}
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86Instr64bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86Instr64bit.td?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86Instr64bit.td (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86Instr64bit.td Thu Jul 8 03:14:09 2010
@@ -1890,8 +1890,6 @@
(MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
(MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
-def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
- (MOV64ri tglobaltlsaddr :$dst)>, Requires<[FarData]>;
def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
(MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
@@ -1906,8 +1904,6 @@
(MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>;
def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
(MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
-def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
- (MOV64ri64i32 tglobaltlsaddr :$dst)>, Requires<[SmallCode]>;
def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
(MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>;
def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
@@ -1922,8 +1918,6 @@
(MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
(MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
-def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
- (MOV64ri32 tglobaltlsaddr :$dst)>, Requires<[KernelCode]>;
def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
(MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
@@ -1941,9 +1935,6 @@
def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
(MOV64mi32 addr:$dst, tglobaladdr:$src)>,
Requires<[NearData, IsStatic]>;
-def : Pat<(store (i64 (X86Wrapper tglobaltlsaddr:$src)), addr:$dst),
- (MOV64mi32 addr:$dst, tglobaltlsaddr:$src)>,
- Requires<[NearData, IsStatic]>;
def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
(MOV64mi32 addr:$dst, texternalsym:$src)>,
Requires<[NearData, IsStatic]>;
@@ -1981,6 +1972,17 @@
(TCRETURNdi64 texternalsym:$dst, imm:$off)>,
Requires<[In64BitMode]>;
+// tls has some funny stuff here...
+// This corresponds to movabs $foo at tpoff, %rax
+def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
+ (MOV64ri tglobaltlsaddr :$dst)>;
+// This corresponds to add $foo at tpoff, %rax
+def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)),
+ (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>;
+// This corresponds to mov foo at tpoff(%rbx), %eax
+def : Pat<(load (i64 (X86Wrapper tglobaltlsaddr :$dst))),
+ (MOV64rm tglobaltlsaddr :$dst)>;
+
// Comparisons.
// TEST R,R is smaller than CMP R,0
@@ -2349,45 +2351,3 @@
"movq\t{$src, $dst|$dst, $src}",
[(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
-//===----------------------------------------------------------------------===//
-// X86-64 SSE4.1 Instructions
-//===----------------------------------------------------------------------===//
-
-/// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
-multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
- def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
- (ins VR128:$src1, i32i8imm:$src2),
- !strconcat(OpcodeStr,
- "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
- [(set GR64:$dst,
- (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
- def mr : SS4AIi8<opc, MRMDestMem, (outs),
- (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
- !strconcat(OpcodeStr,
- "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
- [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
- addr:$dst)]>, OpSize, REX_W;
-}
-
-defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
-
-let Constraints = "$src1 = $dst" in {
- multiclass SS41I_insert64<bits<8> opc, string OpcodeStr> {
- def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
- (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
- !strconcat(OpcodeStr,
- "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
- [(set VR128:$dst,
- (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
- OpSize, REX_W;
- def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
- (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
- !strconcat(OpcodeStr,
- "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
- [(set VR128:$dst,
- (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
- imm:$src3)))]>, OpSize, REX_W;
- }
-} // Constraints = "$src1 = $dst"
-
-defm PINSRQ : SS41I_insert64<0x22, "pinsrq">;
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86InstrFormats.td?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86InstrFormats.td (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86InstrFormats.td Thu Jul 8 03:14:09 2010
@@ -50,9 +50,10 @@
def Imm8 : ImmType<1>;
def Imm8PCRel : ImmType<2>;
def Imm16 : ImmType<3>;
-def Imm32 : ImmType<4>;
-def Imm32PCRel : ImmType<5>;
-def Imm64 : ImmType<6>;
+def Imm16PCRel : ImmType<4>;
+def Imm32 : ImmType<5>;
+def Imm32PCRel : ImmType<6>;
+def Imm64 : ImmType<7>;
// FPFormat - This specifies what form this FP instruction has. This is used by
// the Floating-Point stackifier pass.
@@ -104,6 +105,7 @@
class VEX { bit hasVEXPrefix = 1; }
class VEX_W { bit hasVEX_WPrefix = 1; }
class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; }
+class VEX_I8IMM { bit hasVEX_i8ImmReg = 1; }
class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
string AsmStr, Domain d = GenericDomain>
@@ -134,6 +136,8 @@
bit hasVEXPrefix = 0; // Does this inst requires a VEX prefix?
bit hasVEX_WPrefix = 0; // Does this inst set the VEX_W field?
bit hasVEX_4VPrefix = 0; // Does this inst requires the VEX.VVVV field?
+ bit hasVEX_i8ImmReg = 0; // Does this inst requires the last source register
+ // to be encoded in a immediate field?
// TSFlags layout should be kept in sync with X86InstrInfo.h.
let TSFlags{5-0} = FormBits;
@@ -150,6 +154,7 @@
let TSFlags{32} = hasVEXPrefix;
let TSFlags{33} = hasVEX_WPrefix;
let TSFlags{34} = hasVEX_4VPrefix;
+ let TSFlags{35} = hasVEX_i8ImmReg;
}
class I<bits<8> o, Format f, dag outs, dag ins, string asm,
@@ -183,6 +188,13 @@
let CodeSize = 3;
}
+class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
+ list<dag> pattern>
+ : X86Inst<o, f, Imm16PCRel, outs, ins, asm> {
+ let Pattern = pattern;
+ let CodeSize = 3;
+}
+
class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
list<dag> pattern>
: X86Inst<o, f, Imm32PCRel, outs, ins, asm> {
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86InstrInfo.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86InstrInfo.cpp Thu Jul 8 03:14:09 2010
@@ -1913,6 +1913,9 @@
else if (SrcRC->hasSuperClass(&X86::GR32RegClass) &&
DestRC->hasSuperClass(&X86::GR32RegClass))
CommonRC = &X86::GR32RegClass;
+ else if (SrcRC->hasSuperClass(&X86::GR8RegClass) &&
+ DestRC->hasSuperClass(&X86::GR8RegClass))
+ CommonRC = &X86::GR8RegClass;
else
CommonRC = 0;
}
@@ -1929,7 +1932,9 @@
} else if (CommonRC == &X86::GR8RegClass) {
// Copying to or from a physical H register on x86-64 requires a NOREX
// move. Otherwise use a normal move.
- if ((isHReg(DestReg) || isHReg(SrcReg)) &&
+ if ((isHReg(DestReg) || isHReg(SrcReg) ||
+ SrcRC == &X86::GR8_ABCD_HRegClass ||
+ DestRC == &X86::GR8_ABCD_HRegClass) &&
TM.getSubtarget<X86Subtarget>().is64Bit())
Opc = X86::MOV8rr_NOREX;
else
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86InstrInfo.h?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86InstrInfo.h (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86InstrInfo.h Thu Jul 8 03:14:09 2010
@@ -360,9 +360,10 @@
Imm8 = 1 << ImmShift,
Imm8PCRel = 2 << ImmShift,
Imm16 = 3 << ImmShift,
- Imm32 = 4 << ImmShift,
- Imm32PCRel = 5 << ImmShift,
- Imm64 = 6 << ImmShift,
+ Imm16PCRel = 4 << ImmShift,
+ Imm32 = 5 << ImmShift,
+ Imm32PCRel = 6 << ImmShift,
+ Imm64 = 7 << ImmShift,
//===------------------------------------------------------------------===//
// FP Instruction Classification... Zero is non-fp instruction.
@@ -424,14 +425,22 @@
// those enums below are used, TSFlags must be shifted right by 32 first.
enum {
//===------------------------------------------------------------------===//
- // VEXPrefix - VEX prefixes are instruction prefixes used in AVX.
+ // VEX - A prefix used by AVX instructions
+ VEX = 1,
+
+ // VEX_W is has a opcode specific functionality, but is used in the same
+ // way as REX_W is for regular SSE instructions.
+ VEX_W = 1 << 1,
+
// VEX_4V is used to specify an additional AVX/SSE register. Several 2
// address instructions in SSE are represented as 3 address ones in AVX
// and the additional register is encoded in VEX_VVVV prefix.
- //
- VEX = 1,
- VEX_W = 1 << 1,
- VEX_4V = 1 << 2
+ VEX_4V = 1 << 2,
+
+ // VEX_I8IMM specifies that the last register used in a AVX instruction,
+ // must be encoded in the i8 immediate field. This usually happens in
+ // instructions with 4 operands.
+ VEX_I8IMM = 1 << 3
};
// getBaseOpcodeFor - This function returns the "base" X86 opcode for the
@@ -452,7 +461,8 @@
default: assert(0 && "Unknown immediate size");
case X86II::Imm8:
case X86II::Imm8PCRel: return 1;
- case X86II::Imm16: return 2;
+ case X86II::Imm16:
+ case X86II::Imm16PCRel: return 2;
case X86II::Imm32:
case X86II::Imm32PCRel: return 4;
case X86II::Imm64: return 8;
@@ -465,6 +475,7 @@
switch (TSFlags & X86II::ImmMask) {
default: assert(0 && "Unknown immediate size");
case X86II::Imm8PCRel:
+ case X86II::Imm16PCRel:
case X86II::Imm32PCRel:
return true;
case X86II::Imm8:
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86InstrInfo.td?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86InstrInfo.td Thu Jul 8 03:14:09 2010
@@ -259,6 +259,7 @@
let ParserMatchClass = X86AbsMemAsmOperand,
PrintMethod = "print_pcrel_imm" in {
def i32imm_pcrel : Operand<i32>;
+def i16imm_pcrel : Operand<i16>;
def offset8 : Operand<i64>;
def offset16 : Operand<i64>;
@@ -709,6 +710,12 @@
"lcall{w}\t{*}$dst", []>, OpSize;
def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
"lcall{l}\t{*}$dst", []>;
+
+ // callw for 16 bit code for the assembler.
+ let isAsmParserOnly = 1 in
+ def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm,
+ (outs), (ins i16imm_pcrel:$dst, variable_ops),
+ "callw\t$dst", []>, OpSize;
}
// Constructing a stack frame.
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86InstrSSE.td?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86InstrSSE.td Thu Jul 8 03:14:09 2010
@@ -3900,7 +3900,382 @@
(MOVUPSmr addr:$dst, VR128:$src)>;
//===----------------------------------------------------------------------===//
-// SSE4.1 - Misc Instructions
+// SSE4.1 - Packed Move with Sign/Zero Extend
+//===----------------------------------------------------------------------===//
+
+multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
+ def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
+ !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
+ [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
+
+ def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
+ !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
+ [(set VR128:$dst,
+ (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
+ OpSize;
+}
+
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in {
+defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
+ VEX;
+defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
+ VEX;
+defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
+ VEX;
+defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
+ VEX;
+defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
+ VEX;
+defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
+ VEX;
+}
+
+defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
+defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
+defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
+defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
+defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
+defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
+
+// Common patterns involving scalar load.
+def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
+ (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
+def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
+ (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
+
+def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
+ (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
+def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
+ (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
+
+def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
+ (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
+def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
+ (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
+
+def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
+ (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
+def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
+ (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
+
+def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
+ (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
+def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
+ (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
+
+def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
+ (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
+def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
+ (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
+
+
+multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
+ def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
+ !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
+ [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
+
+ def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
+ !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
+ [(set VR128:$dst,
+ (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
+ OpSize;
+}
+
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in {
+defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
+ VEX;
+defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
+ VEX;
+defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
+ VEX;
+defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
+ VEX;
+}
+
+defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
+defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
+defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
+defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
+
+// Common patterns involving scalar load
+def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
+ (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
+def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
+ (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
+
+def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
+ (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
+def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
+ (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
+
+
+multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
+ def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
+ !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
+ [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
+
+ // Expecting a i16 load any extended to i32 value.
+ def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
+ !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
+ [(set VR128:$dst, (IntId (bitconvert
+ (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
+ OpSize;
+}
+
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in {
+defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
+ VEX;
+defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
+ VEX;
+}
+defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
+defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
+
+// Common patterns involving scalar load
+def : Pat<(int_x86_sse41_pmovsxbq
+ (bitconvert (v4i32 (X86vzmovl
+ (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
+ (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
+
+def : Pat<(int_x86_sse41_pmovzxbq
+ (bitconvert (v4i32 (X86vzmovl
+ (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
+ (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
+
+//===----------------------------------------------------------------------===//
+// SSE4.1 - Extract Instructions
+//===----------------------------------------------------------------------===//
+
+/// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
+multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
+ def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
+ (ins VR128:$src1, i32i8imm:$src2),
+ !strconcat(OpcodeStr,
+ "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+ [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
+ OpSize;
+ def mr : SS4AIi8<opc, MRMDestMem, (outs),
+ (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
+ !strconcat(OpcodeStr,
+ "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+ []>, OpSize;
+// FIXME:
+// There's an AssertZext in the way of writing the store pattern
+// (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
+}
+
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in
+ defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
+
+defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
+
+
+/// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
+multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
+ def mr : SS4AIi8<opc, MRMDestMem, (outs),
+ (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
+ !strconcat(OpcodeStr,
+ "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+ []>, OpSize;
+// FIXME:
+// There's an AssertZext in the way of writing the store pattern
+// (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
+}
+
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in
+ defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
+
+defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
+
+
+/// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
+multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
+ def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
+ (ins VR128:$src1, i32i8imm:$src2),
+ !strconcat(OpcodeStr,
+ "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+ [(set GR32:$dst,
+ (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
+ def mr : SS4AIi8<opc, MRMDestMem, (outs),
+ (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
+ !strconcat(OpcodeStr,
+ "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+ [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
+ addr:$dst)]>, OpSize;
+}
+
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in
+ defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
+
+defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
+
+/// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
+multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
+ def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
+ (ins VR128:$src1, i32i8imm:$src2),
+ !strconcat(OpcodeStr,
+ "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+ [(set GR64:$dst,
+ (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
+ def mr : SS4AIi8<opc, MRMDestMem, (outs),
+ (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
+ !strconcat(OpcodeStr,
+ "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+ [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
+ addr:$dst)]>, OpSize, REX_W;
+}
+
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in
+ defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
+
+defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
+
+/// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
+/// destination
+multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
+ def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
+ (ins VR128:$src1, i32i8imm:$src2),
+ !strconcat(OpcodeStr,
+ "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+ [(set GR32:$dst,
+ (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
+ OpSize;
+ def mr : SS4AIi8<opc, MRMDestMem, (outs),
+ (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
+ !strconcat(OpcodeStr,
+ "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+ [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
+ addr:$dst)]>, OpSize;
+}
+
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in
+ defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
+defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
+
+// Also match an EXTRACTPS store when the store is done as f32 instead of i32.
+def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
+ imm:$src2))),
+ addr:$dst),
+ (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
+ Requires<[HasSSE41]>;
+
+//===----------------------------------------------------------------------===//
+// SSE4.1 - Insert Instructions
+//===----------------------------------------------------------------------===//
+
+multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
+ def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
+ (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
+ !if(Is2Addr,
+ !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+ !strconcat(asm,
+ "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
+ [(set VR128:$dst,
+ (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
+ def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
+ (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
+ !if(Is2Addr,
+ !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+ !strconcat(asm,
+ "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
+ [(set VR128:$dst,
+ (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
+ imm:$src3))]>, OpSize;
+}
+
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in
+ defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
+let Constraints = "$src1 = $dst" in
+ defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
+
+multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
+ def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
+ (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
+ !if(Is2Addr,
+ !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+ !strconcat(asm,
+ "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
+ [(set VR128:$dst,
+ (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
+ OpSize;
+ def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
+ (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
+ !if(Is2Addr,
+ !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+ !strconcat(asm,
+ "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
+ [(set VR128:$dst,
+ (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
+ imm:$src3)))]>, OpSize;
+}
+
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in
+ defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
+let Constraints = "$src1 = $dst" in
+ defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
+
+multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
+ def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
+ (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
+ !if(Is2Addr,
+ !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+ !strconcat(asm,
+ "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
+ [(set VR128:$dst,
+ (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
+ OpSize;
+ def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
+ (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
+ !if(Is2Addr,
+ !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+ !strconcat(asm,
+ "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
+ [(set VR128:$dst,
+ (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
+ imm:$src3)))]>, OpSize;
+}
+
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in
+ defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
+let Constraints = "$src1 = $dst" in
+ defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
+
+// insertps has a few different modes, there's the first two here below which
+// are optimized inserts that won't zero arbitrary elements in the destination
+// vector. The next one matches the intrinsic and could zero arbitrary elements
+// in the target vector.
+multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
+ def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
+ (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
+ !if(Is2Addr,
+ !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+ !strconcat(asm,
+ "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
+ [(set VR128:$dst,
+ (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
+ OpSize;
+ def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
+ (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
+ !if(Is2Addr,
+ !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+ !strconcat(asm,
+ "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
+ [(set VR128:$dst,
+ (X86insrtps VR128:$src1,
+ (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
+ imm:$src3))]>, OpSize;
+}
+
+let Constraints = "$src1 = $dst" in
+ defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in
+ defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
+
+def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
+ (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>;
+
+//===----------------------------------------------------------------------===//
+// SSE4.1 - Round Instructions
//===----------------------------------------------------------------------===//
multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd,
@@ -4078,7 +4453,11 @@
defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
-// SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
+//===----------------------------------------------------------------------===//
+// SSE4.1 - Misc Instructions
+//===----------------------------------------------------------------------===//
+
+// SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
Intrinsic IntId128> {
def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
@@ -4246,6 +4625,27 @@
defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd>;
}
+/// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in {
+ multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr> {
+ def rr : I<opc, MRMSrcReg, (outs VR128:$dst),
+ (ins VR128:$src1, VR128:$src2, VR128:$src3),
+ !strconcat(OpcodeStr,
+ "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
+ [], SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
+
+ def rm : I<opc, MRMSrcMem, (outs VR128:$dst),
+ (ins VR128:$src1, i128mem:$src2, VR128:$src3),
+ !strconcat(OpcodeStr,
+ "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
+ [], SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
+ }
+}
+
+defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd">;
+defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps">;
+defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb">;
+
/// SS41I_ternary_int - SSE 4.1 ternary operator
let Uses = [XMM0], Constraints = "$src1 = $dst" in {
multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
@@ -4270,316 +4670,230 @@
defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
-
-multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
- def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
- !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
- [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
-
- def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
- !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
- [(set VR128:$dst,
- (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
- OpSize;
+// ptest instruction we'll lower to this in X86ISelLowering primarily from
+// the intel intrinsic that corresponds to this.
+let Defs = [EFLAGS], isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in {
+def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
+ "vptest\t{$src2, $src1|$src1, $src2}",
+ [(set EFLAGS, (X86ptest VR128:$src1, VR128:$src2))]>,
+ OpSize, VEX;
+def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
+ "vptest\t{$src2, $src1|$src1, $src2}",
+ [(set EFLAGS, (X86ptest VR128:$src1, (load addr:$src2)))]>,
+ OpSize, VEX;
}
-defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
-defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
-defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
-defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
-defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
-defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
-
-// Common patterns involving scalar load.
-def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
- (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
-def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
- (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
-
-def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
- (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
-def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
- (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
-
-def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
- (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
-def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
- (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
-
-def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
- (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
-def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
- (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
-
-def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
- (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
-def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
- (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
-
-def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
- (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
-def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
- (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
+let Defs = [EFLAGS] in {
+def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
+ "ptest \t{$src2, $src1|$src1, $src2}",
+ [(set EFLAGS, (X86ptest VR128:$src1, VR128:$src2))]>,
+ OpSize;
+def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
+ "ptest \t{$src2, $src1|$src1, $src2}",
+ [(set EFLAGS, (X86ptest VR128:$src1, (load addr:$src2)))]>,
+ OpSize;
+}
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in
+def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
+ "vmovntdqa\t{$src, $dst|$dst, $src}",
+ [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
+ OpSize, VEX;
+def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
+ "movntdqa\t{$src, $dst|$dst, $src}",
+ [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
+ OpSize;
-multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
- def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
- !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
- [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
+//===----------------------------------------------------------------------===//
+// SSE4.2 - Compare Instructions
+//===----------------------------------------------------------------------===//
- def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
- !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
+/// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
+multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
+ Intrinsic IntId128, bit Is2Addr = 1> {
+ def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
+ (ins VR128:$src1, VR128:$src2),
+ !if(Is2Addr,
+ !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
+ !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
+ [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
+ OpSize;
+ def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
+ (ins VR128:$src1, i128mem:$src2),
+ !if(Is2Addr,
+ !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
+ !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
[(set VR128:$dst,
- (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
- OpSize;
+ (IntId128 VR128:$src1,
+ (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
}
-defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
-defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
-defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
-defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
-
-// Common patterns involving scalar load
-def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
- (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
-def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
- (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
-
-def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
- (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
-def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
- (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE42] in
+ defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq,
+ 0>, VEX_4V;
+let Constraints = "$src1 = $dst" in
+ defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
+def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
+ (PCMPGTQrr VR128:$src1, VR128:$src2)>;
+def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
+ (PCMPGTQrm VR128:$src1, addr:$src2)>;
-multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
- def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
- !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
- [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
+//===----------------------------------------------------------------------===//
+// SSE4.2 - String/text Processing Instructions
+//===----------------------------------------------------------------------===//
- // Expecting a i16 load any extended to i32 value.
- def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
- !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
- [(set VR128:$dst, (IntId (bitconvert
- (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
- OpSize;
+// Packed Compare Implicit Length Strings, Return Mask
+let Defs = [EFLAGS], usesCustomInserter = 1 in {
+ def PCMPISTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
+ (ins VR128:$src1, VR128:$src2, i8imm:$src3),
+ "#PCMPISTRM128rr PSEUDO!",
+ [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
+ imm:$src3))]>, OpSize;
+ def PCMPISTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
+ (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
+ "#PCMPISTRM128rm PSEUDO!",
+ [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
+ VR128:$src1, (load addr:$src2), imm:$src3))]>, OpSize;
}
-defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
-defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
-
-// Common patterns involving scalar load
-def : Pat<(int_x86_sse41_pmovsxbq
- (bitconvert (v4i32 (X86vzmovl
- (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
- (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
-
-def : Pat<(int_x86_sse41_pmovzxbq
- (bitconvert (v4i32 (X86vzmovl
- (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
- (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
-
-
-/// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
-multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
- def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
- (ins VR128:$src1, i32i8imm:$src2),
- !strconcat(OpcodeStr,
- "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
- [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
- OpSize;
- def mr : SS4AIi8<opc, MRMDestMem, (outs),
- (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
- !strconcat(OpcodeStr,
- "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
- []>, OpSize;
-// FIXME:
-// There's an AssertZext in the way of writing the store pattern
-// (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
+let Defs = [XMM0, EFLAGS], isAsmParserOnly = 1,
+ Predicates = [HasAVX, HasSSE42] in {
+ def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
+ (ins VR128:$src1, VR128:$src2, i8imm:$src3),
+ "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
+ def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
+ (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
+ "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
}
-defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
-
-
-/// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
-multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
- def mr : SS4AIi8<opc, MRMDestMem, (outs),
- (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
- !strconcat(OpcodeStr,
- "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
- []>, OpSize;
-// FIXME:
-// There's an AssertZext in the way of writing the store pattern
-// (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
+let Defs = [XMM0, EFLAGS] in {
+ def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
+ (ins VR128:$src1, VR128:$src2, i8imm:$src3),
+ "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
+ def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
+ (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
+ "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
}
-defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
-
-
-/// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
-multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
- def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
- (ins VR128:$src1, i32i8imm:$src2),
- !strconcat(OpcodeStr,
- "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
- [(set GR32:$dst,
- (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
- def mr : SS4AIi8<opc, MRMDestMem, (outs),
- (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
- !strconcat(OpcodeStr,
- "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
- [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
- addr:$dst)]>, OpSize;
+// Packed Compare Explicit Length Strings, Return Mask
+let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
+ def PCMPESTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
+ (ins VR128:$src1, VR128:$src3, i8imm:$src5),
+ "#PCMPESTRM128rr PSEUDO!",
+ [(set VR128:$dst,
+ (int_x86_sse42_pcmpestrm128
+ VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>, OpSize;
+
+ def PCMPESTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
+ (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
+ "#PCMPESTRM128rm PSEUDO!",
+ [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
+ VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>,
+ OpSize;
+}
+
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE42],
+ Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
+ def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
+ (ins VR128:$src1, VR128:$src3, i8imm:$src5),
+ "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
+ def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
+ (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
+ "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
}
-defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
-
-
-/// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
-/// destination
-multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
- def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
- (ins VR128:$src1, i32i8imm:$src2),
- !strconcat(OpcodeStr,
- "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
- [(set GR32:$dst,
- (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
- OpSize;
- def mr : SS4AIi8<opc, MRMDestMem, (outs),
- (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
- !strconcat(OpcodeStr,
- "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
- [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
- addr:$dst)]>, OpSize;
+let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
+ def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
+ (ins VR128:$src1, VR128:$src3, i8imm:$src5),
+ "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
+ def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
+ (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
+ "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
}
-defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
-
-// Also match an EXTRACTPS store when the store is done as f32 instead of i32.
-def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
- imm:$src2))),
- addr:$dst),
- (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
- Requires<[HasSSE41]>;
-
-let Constraints = "$src1 = $dst" in {
- multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> {
- def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
- (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
- !strconcat(OpcodeStr,
- "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
- [(set VR128:$dst,
- (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
- def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
- (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
- !strconcat(OpcodeStr,
- "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
- [(set VR128:$dst,
- (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
- imm:$src3))]>, OpSize;
+// Packed Compare Implicit Length Strings, Return Index
+let Defs = [ECX, EFLAGS] in {
+ multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
+ def rr : SS42AI<0x63, MRMSrcReg, (outs),
+ (ins VR128:$src1, VR128:$src2, i8imm:$src3),
+ !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
+ [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
+ (implicit EFLAGS)]>, OpSize;
+ def rm : SS42AI<0x63, MRMSrcMem, (outs),
+ (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
+ !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
+ [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
+ (implicit EFLAGS)]>, OpSize;
}
}
-defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
-
-let Constraints = "$src1 = $dst" in {
- multiclass SS41I_insert32<bits<8> opc, string OpcodeStr> {
- def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
- (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
- !strconcat(OpcodeStr,
- "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
- [(set VR128:$dst,
- (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
- OpSize;
- def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
- (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
- !strconcat(OpcodeStr,
- "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
- [(set VR128:$dst,
- (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
- imm:$src3)))]>, OpSize;
- }
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE42] in {
+defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
+ VEX;
+defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
+ VEX;
+defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
+ VEX;
+defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
+ VEX;
+defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
+ VEX;
+defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
+ VEX;
}
-defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
+defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
+defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
+defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
+defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
+defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
+defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
-// insertps has a few different modes, there's the first two here below which
-// are optimized inserts that won't zero arbitrary elements in the destination
-// vector. The next one matches the intrinsic and could zero arbitrary elements
-// in the target vector.
-let Constraints = "$src1 = $dst" in {
- multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
- def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
- (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
- !strconcat(OpcodeStr,
- "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
- [(set VR128:$dst,
- (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
- OpSize;
- def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
- (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
- !strconcat(OpcodeStr,
- "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
- [(set VR128:$dst,
- (X86insrtps VR128:$src1,
- (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
- imm:$src3))]>, OpSize;
+// Packed Compare Explicit Length Strings, Return Index
+let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
+ multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
+ def rr : SS42AI<0x61, MRMSrcReg, (outs),
+ (ins VR128:$src1, VR128:$src3, i8imm:$src5),
+ !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
+ [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
+ (implicit EFLAGS)]>, OpSize;
+ def rm : SS42AI<0x61, MRMSrcMem, (outs),
+ (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
+ !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
+ [(set ECX,
+ (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
+ (implicit EFLAGS)]>, OpSize;
}
}
-defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
-
-def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
- (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>;
-
-// ptest instruction we'll lower to this in X86ISelLowering primarily from
-// the intel intrinsic that corresponds to this.
-let Defs = [EFLAGS] in {
-def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
- "ptest \t{$src2, $src1|$src1, $src2}",
- [(set EFLAGS, (X86ptest VR128:$src1, VR128:$src2))]>,
- OpSize;
-def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
- "ptest \t{$src2, $src1|$src1, $src2}",
- [(set EFLAGS, (X86ptest VR128:$src1, (load addr:$src2)))]>,
- OpSize;
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE42] in {
+defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
+ VEX;
+defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
+ VEX;
+defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
+ VEX;
+defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
+ VEX;
+defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
+ VEX;
+defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
+ VEX;
}
-def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
- "movntdqa\t{$src, $dst|$dst, $src}",
- [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
- OpSize;
-
+defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
+defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
+defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
+defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
+defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
+defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
//===----------------------------------------------------------------------===//
-// SSE4.2 Instructions
+// SSE4.2 - CRC Instructions
//===----------------------------------------------------------------------===//
-/// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
-let Constraints = "$src1 = $dst" in {
- multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
- Intrinsic IntId128, bit Commutable = 0> {
- def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
- (ins VR128:$src1, VR128:$src2),
- !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
- [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
- OpSize {
- let isCommutable = Commutable;
- }
- def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
- (ins VR128:$src1, i128mem:$src2),
- !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
- [(set VR128:$dst,
- (IntId128 VR128:$src1,
- (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
- }
-}
-
-defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
-
-def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
- (PCMPGTQrr VR128:$src1, VR128:$src2)>;
-def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
- (PCMPGTQrm VR128:$src1, addr:$src2)>;
+// No CRC instructions have AVX equivalents
// crc intrinsic instruction
// This set of instructions are only rm, the only difference is the size
@@ -4648,133 +4962,52 @@
REX_W;
}
-// String/text processing instructions.
-let Defs = [EFLAGS], usesCustomInserter = 1 in {
-def PCMPISTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
- (ins VR128:$src1, VR128:$src2, i8imm:$src3),
- "#PCMPISTRM128rr PSEUDO!",
- [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
- imm:$src3))]>, OpSize;
-def PCMPISTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
- (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
- "#PCMPISTRM128rm PSEUDO!",
- [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, (load addr:$src2),
- imm:$src3))]>, OpSize;
-}
-
-let Defs = [XMM0, EFLAGS] in {
-def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
- (ins VR128:$src1, VR128:$src2, i8imm:$src3),
- "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
-def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
- (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
- "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
-}
-
-let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
-def PCMPESTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
- (ins VR128:$src1, VR128:$src3, i8imm:$src5),
- "#PCMPESTRM128rr PSEUDO!",
- [(set VR128:$dst,
- (int_x86_sse42_pcmpestrm128
- VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>, OpSize;
-
-def PCMPESTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
- (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
- "#PCMPESTRM128rm PSEUDO!",
- [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
- VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>,
- OpSize;
-}
-
-let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
-def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
- (ins VR128:$src1, VR128:$src3, i8imm:$src5),
- "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
-def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
- (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
- "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
-}
+//===----------------------------------------------------------------------===//
+// AES-NI Instructions
+//===----------------------------------------------------------------------===//
-let Defs = [ECX, EFLAGS] in {
- multiclass SS42AI_pcmpistri<Intrinsic IntId128> {
- def rr : SS42AI<0x63, MRMSrcReg, (outs),
- (ins VR128:$src1, VR128:$src2, i8imm:$src3),
- "pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
- [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
- (implicit EFLAGS)]>, OpSize;
- def rm : SS42AI<0x63, MRMSrcMem, (outs),
- (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
- "pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
- [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
- (implicit EFLAGS)]>, OpSize;
- }
+multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
+ Intrinsic IntId128, bit Is2Addr = 1> {
+ def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
+ (ins VR128:$src1, VR128:$src2),
+ !if(Is2Addr,
+ !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
+ !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
+ [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
+ OpSize;
+ def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
+ (ins VR128:$src1, i128mem:$src2),
+ !if(Is2Addr,
+ !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
+ !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
+ [(set VR128:$dst,
+ (IntId128 VR128:$src1,
+ (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
}
-defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
-defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
-defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
-defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
-defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
-defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
-
-let Defs = [ECX, EFLAGS] in {
-let Uses = [EAX, EDX] in {
- multiclass SS42AI_pcmpestri<Intrinsic IntId128> {
- def rr : SS42AI<0x61, MRMSrcReg, (outs),
- (ins VR128:$src1, VR128:$src3, i8imm:$src5),
- "pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
- [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
- (implicit EFLAGS)]>, OpSize;
- def rm : SS42AI<0x61, MRMSrcMem, (outs),
- (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
- "pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
- [(set ECX,
- (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
- (implicit EFLAGS)]>, OpSize;
- }
-}
+// Perform One Round of an AES Encryption/Decryption Flow
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasAES] in {
+ defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
+ int_x86_aesni_aesenc, 0>, VEX_4V;
+ defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
+ int_x86_aesni_aesenclast, 0>, VEX_4V;
+ defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
+ int_x86_aesni_aesdec, 0>, VEX_4V;
+ defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
+ int_x86_aesni_aesdeclast, 0>, VEX_4V;
}
-defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
-defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
-defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
-defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
-defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
-defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
-
-//===----------------------------------------------------------------------===//
-// AES-NI Instructions
-//===----------------------------------------------------------------------===//
-
let Constraints = "$src1 = $dst" in {
- multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
- Intrinsic IntId128, bit Commutable = 0> {
- def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
- (ins VR128:$src1, VR128:$src2),
- !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
- [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
- OpSize {
- let isCommutable = Commutable;
- }
- def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
- (ins VR128:$src1, i128mem:$src2),
- !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
- [(set VR128:$dst,
- (IntId128 VR128:$src1,
- (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
- }
+ defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
+ int_x86_aesni_aesenc>;
+ defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
+ int_x86_aesni_aesenclast>;
+ defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
+ int_x86_aesni_aesdec>;
+ defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
+ int_x86_aesni_aesdeclast>;
}
-defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
- int_x86_aesni_aesenc>;
-defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
- int_x86_aesni_aesenclast>;
-defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
- int_x86_aesni_aesdec>;
-defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
- int_x86_aesni_aesdeclast>;
-
def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
(AESENCrr VR128:$src1, VR128:$src2)>;
def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
@@ -4792,13 +5025,27 @@
def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
(AESDECLASTrm VR128:$src1, addr:$src2)>;
+// Perform the AES InvMixColumn Transformation
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasAES] in {
+ def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
+ (ins VR128:$src1),
+ "vaesimc\t{$src1, $dst|$dst, $src1}",
+ [(set VR128:$dst,
+ (int_x86_aesni_aesimc VR128:$src1))]>,
+ OpSize, VEX;
+ def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
+ (ins i128mem:$src1),
+ "vaesimc\t{$src1, $dst|$dst, $src1}",
+ [(set VR128:$dst,
+ (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
+ OpSize, VEX;
+}
def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1),
"aesimc\t{$src1, $dst|$dst, $src1}",
[(set VR128:$dst,
(int_x86_aesni_aesimc VR128:$src1))]>,
OpSize;
-
def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
(ins i128mem:$src1),
"aesimc\t{$src1, $dst|$dst, $src1}",
@@ -4806,6 +5053,22 @@
(int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
OpSize;
+// AES Round Key Generation Assist
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasAES] in {
+ def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
+ (ins VR128:$src1, i8imm:$src2),
+ "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
+ [(set VR128:$dst,
+ (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
+ OpSize, VEX;
+ def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
+ (ins i128mem:$src1, i8imm:$src2),
+ "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
+ [(set VR128:$dst,
+ (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
+ imm:$src2))]>,
+ OpSize, VEX;
+}
def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, i8imm:$src2),
"aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86MCCodeEmitter.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86MCCodeEmitter.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86MCCodeEmitter.cpp Thu Jul 8 03:14:09 2010
@@ -38,13 +38,14 @@
~X86MCCodeEmitter() {}
unsigned getNumFixupKinds() const {
- return 4;
+ return 5;
}
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
const static MCFixupKindInfo Infos[] = {
{ "reloc_pcrel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
{ "reloc_pcrel_1byte", 0, 1 * 8, MCFixupKindInfo::FKF_IsPCRel },
+ { "reloc_pcrel_2byte", 0, 2 * 8, MCFixupKindInfo::FKF_IsPCRel },
{ "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
{ "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel }
};
@@ -170,8 +171,8 @@
switch (Size) {
default: assert(0 && "Unknown immediate size");
case 1: return isPCRel ? MCFixupKind(X86::reloc_pcrel_1byte) : FK_Data_1;
+ case 2: return isPCRel ? MCFixupKind(X86::reloc_pcrel_2byte) : FK_Data_2;
case 4: return isPCRel ? MCFixupKind(X86::reloc_pcrel_4byte) : FK_Data_4;
- case 2: assert(!isPCRel); return FK_Data_2;
case 8: assert(!isPCRel); return FK_Data_8;
}
}
@@ -199,6 +200,8 @@
FixupKind == MCFixupKind(X86::reloc_riprel_4byte) ||
FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load))
ImmOffset -= 4;
+ if (FixupKind == MCFixupKind(X86::reloc_pcrel_2byte))
+ ImmOffset -= 2;
if (FixupKind == MCFixupKind(X86::reloc_pcrel_1byte))
ImmOffset -= 1;
@@ -501,6 +504,11 @@
CurOp++;
}
+ // If the last register should be encoded in the immediate field
+ // do not use any bit from VEX prefix to this register, ignore it
+ if ((TSFlags >> 32) & X86II::VEX_I8IMM)
+ NumOps--;
+
for (; CurOp != NumOps; ++CurOp) {
const MCOperand &MO = MI.getOperand(CurOp);
if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
@@ -914,11 +922,24 @@
// If there is a remaining operand, it must be a trailing immediate. Emit it
// according to the right size for the instruction.
- if (CurOp != NumOps)
- EmitImmediate(MI.getOperand(CurOp++),
- X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
- CurByte, OS, Fixups);
-
+ if (CurOp != NumOps) {
+ // The last source register of a 4 operand instruction in AVX is encoded
+ // in bits[7:4] of a immediate byte, and bits[3:0] are ignored.
+ if ((TSFlags >> 32) & X86II::VEX_I8IMM) {
+ const MCOperand &MO = MI.getOperand(CurOp++);
+ bool IsExtReg =
+ X86InstrInfo::isX86_64ExtendedReg(MO.getReg());
+ unsigned RegNum = (IsExtReg ? (1 << 7) : 0);
+ RegNum |= GetX86RegNum(MO) << 4;
+ EmitImmediate(MCOperand::CreateImm(RegNum), 1, FK_Data_1, CurByte, OS,
+ Fixups);
+ } else
+ EmitImmediate(MI.getOperand(CurOp++),
+ X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
+ CurByte, OS, Fixups);
+ }
+
+
#ifndef NDEBUG
// FIXME: Verify.
if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86TargetMachine.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86TargetMachine.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86TargetMachine.cpp Thu Jul 8 03:14:09 2010
@@ -173,14 +173,14 @@
// Install an instruction selector.
PM.add(createX86ISelDag(*this, OptLevel));
- // Install a pass to insert x87 FP_REG_KILL instructions, as needed.
- PM.add(createX87FPRegKillInserterPass());
-
return false;
}
bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM,
CodeGenOpt::Level OptLevel) {
+ // Install a pass to insert x87 FP_REG_KILL instructions, as needed.
+ PM.add(createX87FPRegKillInserterPass());
+
PM.add(createX86MaxStackAlignmentHeuristicPass());
return false; // -print-machineinstr shouldn't print after this.
}
Propchange: llvm/branches/wendling/eh/lib/Target/XCore/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -6,3 +6,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Target/XCore/AsmPrinter/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -6,3 +6,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Target/XCore/TargetInfo/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Modified: llvm/branches/wendling/eh/lib/Target/XCore/XCoreISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/XCore/XCoreISelLowering.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/XCore/XCoreISelLowering.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/XCore/XCoreISelLowering.cpp Thu Jul 8 03:14:09 2010
@@ -245,7 +245,7 @@
LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
{
const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
- SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
+ SDValue GA = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(), MVT::i32);
// If it's a debug information descriptor, don't mess with it.
if (DAG.isVerifiedDebugInfoDesc(Op))
return GA;
@@ -269,7 +269,7 @@
DebugLoc dl = Op.getDebugLoc();
// transform to label + getid() * size
const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
- SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
+ SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32);
const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
if (!GVar) {
// If GV is an alias then use the aliasee to determine size
@@ -454,12 +454,12 @@
if (LD->getAlignment() == 2) {
int SVOffset = LD->getSrcValueOffset();
- SDValue Low = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain,
+ SDValue Low = DAG.getExtLoad(ISD::ZEXTLOAD, MVT::i32, dl, Chain,
BasePtr, LD->getSrcValue(), SVOffset, MVT::i16,
LD->isVolatile(), LD->isNonTemporal(), 2);
SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr,
DAG.getConstant(2, MVT::i32));
- SDValue High = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::i32, Chain,
+ SDValue High = DAG.getExtLoad(ISD::EXTLOAD, MVT::i32, dl, Chain,
HighAddr, LD->getSrcValue(), SVOffset + 2,
MVT::i16, LD->isVolatile(),
LD->isNonTemporal(), 2);
@@ -812,6 +812,7 @@
CallingConv::ID CallConv, bool isVarArg,
bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const {
@@ -826,7 +827,7 @@
case CallingConv::Fast:
case CallingConv::C:
return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
- Outs, Ins, dl, DAG, InVals);
+ Outs, OutVals, Ins, dl, DAG, InVals);
}
}
@@ -839,6 +840,7 @@
CallingConv::ID CallConv, bool isVarArg,
bool isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const {
@@ -866,7 +868,7 @@
// Walk the register/memloc assignments, inserting copies/loads.
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
CCValAssign &VA = ArgLocs[i];
- SDValue Arg = Outs[i].Val;
+ SDValue Arg = OutVals[i];
// Promote the value if needed.
switch (VA.getLocInfo()) {
@@ -919,7 +921,7 @@
// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
// Likewise ExternalSymbol -> TargetExternalSymbol.
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
- Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
+ Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32);
else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
@@ -1135,10 +1137,10 @@
CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<EVT> &OutTys,
const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
- SelectionDAG &DAG) const {
+ LLVMContext &Context) const {
SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
- RVLocs, *DAG.getContext());
+ RVLocs, Context);
return CCInfo.CheckReturn(OutTys, ArgsFlags, RetCC_XCore);
}
@@ -1146,6 +1148,7 @@
XCoreTargetLowering::LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
DebugLoc dl, SelectionDAG &DAG) const {
// CCValAssign - represent the assignment of
@@ -1175,7 +1178,7 @@
assert(VA.isRegLoc() && "Can only return in registers!");
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
- Outs[i].Val, Flag);
+ OutVals[i], Flag);
// guarantee that all emitted copies are
// stuck together, avoiding something bad
@@ -1221,23 +1224,22 @@
MachineFunction *F = BB->getParent();
MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
- BuildMI(BB, dl, TII.get(XCore::BRFT_lru6))
- .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
F->insert(It, copy0MBB);
F->insert(It, sinkMBB);
- // Update machine-CFG edges by first adding all successors of the current
- // block to the new block which will contain the Phi node for the select.
- for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
- E = BB->succ_end(); I != E; ++I)
- sinkMBB->addSuccessor(*I);
- // Next, remove all successors of the current block, and add the true
- // and fallthrough blocks as its successors.
- while (!BB->succ_empty())
- BB->removeSuccessor(BB->succ_begin());
+
+ // Transfer the remainder of BB and its successor edges to sinkMBB.
+ sinkMBB->splice(sinkMBB->begin(), BB,
+ llvm::next(MachineBasicBlock::iterator(MI)),
+ BB->end());
+ sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
+
// Next, add the true and fallthrough blocks as its successors.
BB->addSuccessor(copy0MBB);
BB->addSuccessor(sinkMBB);
+ BuildMI(BB, dl, TII.get(XCore::BRFT_lru6))
+ .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
+
// copy0MBB:
// %FalseValue = ...
// # fallthrough to sinkMBB
@@ -1250,11 +1252,12 @@
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
// ...
BB = sinkMBB;
- BuildMI(BB, dl, TII.get(XCore::PHI), MI->getOperand(0).getReg())
+ BuildMI(*BB, BB->begin(), dl,
+ TII.get(XCore::PHI), MI->getOperand(0).getReg())
.addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
- F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
+ MI->eraseFromParent(); // The pseudo instruction is gone now.
return BB;
}
Modified: llvm/branches/wendling/eh/lib/Target/XCore/XCoreISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/XCore/XCoreISelLowering.h?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/XCore/XCoreISelLowering.h (original)
+++ llvm/branches/wendling/eh/lib/Target/XCore/XCoreISelLowering.h Thu Jul 8 03:14:09 2010
@@ -120,6 +120,7 @@
CallingConv::ID CallConv, bool isVarArg,
bool isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const;
@@ -178,6 +179,7 @@
CallingConv::ID CallConv, bool isVarArg,
bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const;
@@ -186,13 +188,14 @@
LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
DebugLoc dl, SelectionDAG &DAG) const;
virtual bool
CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<EVT> &OutTys,
const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
- SelectionDAG &DAG) const;
+ LLVMContext &Context) const;
};
}
Propchange: llvm/branches/wendling/eh/lib/Transforms/Hello/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Transforms/IPO/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Modified: llvm/branches/wendling/eh/lib/Transforms/IPO/MergeFunctions.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/IPO/MergeFunctions.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/IPO/MergeFunctions.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/IPO/MergeFunctions.cpp Thu Jul 8 03:14:09 2010
@@ -146,7 +146,7 @@
switch(Ty1->getTypeID()) {
default:
llvm_unreachable("Unknown type!");
- // Fall through in Release-Asserts mode.
+ // Fall through in Release mode.
case Type::IntegerTyID:
case Type::OpaqueTyID:
// Ty1 == Ty2 would have returned true earlier.
Propchange: llvm/branches/wendling/eh/lib/Transforms/InstCombine/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Transforms/Instrumentation/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/Transforms/Scalar/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Modified: llvm/branches/wendling/eh/lib/Transforms/Scalar/ScalarReplAggregates.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Scalar/ScalarReplAggregates.cpp Thu Jul 8 03:14:09 2010
@@ -1272,6 +1272,8 @@
// If there is an other pointer, we want to convert it to the same pointer
// type as AI has, so we can GEP through it safely.
if (OtherPtr) {
+ unsigned AddrSpace =
+ cast<PointerType>(OtherPtr->getType())->getAddressSpace();
// Remove bitcasts and all-zero GEPs from OtherPtr. This is an
// optimization, but it's also required to detect the corner case where
@@ -1279,20 +1281,8 @@
// OtherPtr may be a bitcast or GEP that currently being rewritten. (This
// function is only called for mem intrinsics that access the whole
// aggregate, so non-zero GEPs are not an issue here.)
- while (1) {
- if (BitCastInst *BC = dyn_cast<BitCastInst>(OtherPtr)) {
- OtherPtr = BC->getOperand(0);
- continue;
- }
- if (GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(OtherPtr)) {
- // All zero GEPs are effectively bitcasts.
- if (GEP->hasAllZeroIndices()) {
- OtherPtr = GEP->getOperand(0);
- continue;
- }
- }
- break;
- }
+ OtherPtr = OtherPtr->stripPointerCasts();
+
// Copying the alloca to itself is a no-op: just delete it.
if (OtherPtr == AI || OtherPtr == NewElts[0]) {
// This code will run twice for a no-op memcpy -- once for each operand.
@@ -1304,15 +1294,13 @@
return;
}
- if (ConstantExpr *BCE = dyn_cast<ConstantExpr>(OtherPtr))
- if (BCE->getOpcode() == Instruction::BitCast)
- OtherPtr = BCE->getOperand(0);
-
// If the pointer is not the right type, insert a bitcast to the right
// type.
- if (OtherPtr->getType() != AI->getType())
- OtherPtr = new BitCastInst(OtherPtr, AI->getType(), OtherPtr->getName(),
- MI);
+ const Type *NewTy =
+ PointerType::get(AI->getType()->getElementType(), AddrSpace);
+
+ if (OtherPtr->getType() != NewTy)
+ OtherPtr = new BitCastInst(OtherPtr, NewTy, OtherPtr->getName(), MI);
}
// Process each element of the aggregate.
Propchange: llvm/branches/wendling/eh/lib/Transforms/Utils/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -6,3 +6,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/lib/VMCore/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -6,3 +6,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Modified: llvm/branches/wendling/eh/lib/VMCore/AsmWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/VMCore/AsmWriter.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/VMCore/AsmWriter.cpp (original)
+++ llvm/branches/wendling/eh/lib/VMCore/AsmWriter.cpp Thu Jul 8 03:14:09 2010
@@ -70,8 +70,7 @@
// PrintEscapedString - Print each character of the specified string, escaping
// it if it is not printable or if it is an escape char.
-static void PrintEscapedString(const StringRef &Name,
- raw_ostream &Out) {
+static void PrintEscapedString(StringRef Name, raw_ostream &Out) {
for (unsigned i = 0, e = Name.size(); i != e; ++i) {
unsigned char C = Name[i];
if (isprint(C) && C != '\\' && C != '"')
@@ -1472,8 +1471,11 @@
writeOperand(GV->getInitializer(), false);
}
- if (GV->hasSection())
- Out << ", section \"" << GV->getSection() << '"';
+ if (GV->hasSection()) {
+ Out << ", section \"";
+ PrintEscapedString(GV->getSection(), Out);
+ Out << '"';
+ }
if (GV->getAlignment())
Out << ", align " << GV->getAlignment();
@@ -1631,8 +1633,11 @@
Attributes FnAttrs = Attrs.getFnAttributes();
if (FnAttrs != Attribute::None)
Out << ' ' << Attribute::getAsString(Attrs.getFnAttributes());
- if (F->hasSection())
- Out << " section \"" << F->getSection() << '"';
+ if (F->hasSection()) {
+ Out << " section \"";
+ PrintEscapedString(F->getSection(), Out);
+ Out << '"';
+ }
if (F->getAlignment())
Out << " align " << F->getAlignment();
if (F->hasGC())
Modified: llvm/branches/wendling/eh/lib/VMCore/Metadata.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/VMCore/Metadata.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/VMCore/Metadata.cpp (original)
+++ llvm/branches/wendling/eh/lib/VMCore/Metadata.cpp Thu Jul 8 03:14:09 2010
@@ -133,6 +133,7 @@
static const Function *assertLocalFunction(const MDNode *N) {
if (!N->isFunctionLocal()) return 0;
+ // FIXME: This does not handle cyclic function local metadata.
const Function *F = 0, *NewF = 0;
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
if (Value *V = N->getOperand(i)) {
Propchange: llvm/branches/wendling/eh/projects/sample/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -9,3 +9,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/projects/sample/lib/sample/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/projects/sample/tools/sample/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/runtime/libprofile/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/tools/bugpoint/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/tools/edis/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -6,3 +6,5 @@
Release+Coverage
Debug+Checks
EDInfo.inc
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/tools/llc/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/tools/lli/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/tools/llvm-ar/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/tools/llvm-as/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/tools/llvm-bcanalyzer/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/tools/llvm-dis/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/tools/llvm-extract/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/tools/llvm-ld/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/tools/llvm-link/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/tools/llvm-mc/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/tools/llvm-nm/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/tools/llvm-prof/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/tools/llvm-ranlib/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/tools/llvm-stub/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/tools/llvmc/driver/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/tools/llvmc/plugins/Base/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -7,3 +7,5 @@
Release+Coverage
Debug+Checks
AutoGenerated.inc
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/tools/llvmc/plugins/Clang/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -6,3 +6,5 @@
Release+Coverage
Debug+Checks
AutoGenerated.inc
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/tools/lto/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/tools/opt/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/unittests/ADT/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/unittests/ExecutionEngine/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/unittests/ExecutionEngine/JIT/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/unittests/Support/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/unittests/Transforms/Utils/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -6,3 +6,5 @@
Release-Asserts
Release+Coverage
*Tests
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/unittests/VMCore/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/utils/FileCheck/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/utils/FileUpdate/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Modified: llvm/branches/wendling/eh/utils/NewNightlyTest.pl
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/utils/NewNightlyTest.pl?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/utils/NewNightlyTest.pl (original)
+++ llvm/branches/wendling/eh/utils/NewNightlyTest.pl Thu Jul 8 03:14:09 2010
@@ -47,8 +47,8 @@
# -noclean Do not run 'make clean' before building.
# -nobuild Do not build llvm. If tests are enabled perform them
# on the llvm build specified in the build directory
-# -release Build an LLVM Release version
-# -release-asserts Build an LLVM ReleaseAsserts version
+# -release Build an LLVM Release+Asserts version
+# -release-asserts Build an LLVM Release version
# -disable-bindings Disable building LLVM bindings.
# -with-clang Checkout Clang source into tools/clang.
# -compileflags Next argument specifies extra options passed to make when
Propchange: llvm/branches/wendling/eh/utils/PerfectShuffle/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -6,3 +6,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/utils/TableGen/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -6,3 +6,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Modified: llvm/branches/wendling/eh/utils/TableGen/ARMDecoderEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/utils/TableGen/ARMDecoderEmitter.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/utils/TableGen/ARMDecoderEmitter.cpp (original)
+++ llvm/branches/wendling/eh/utils/TableGen/ARMDecoderEmitter.cpp Thu Jul 8 03:14:09 2010
@@ -1578,8 +1578,8 @@
// Tail calls are other patterns that generate existing instructions.
if (Name == "TCRETURNdi" || Name == "TCRETURNdiND" ||
Name == "TCRETURNri" || Name == "TCRETURNriND" ||
- Name == "TAILJMPd" || Name == "TAILJMPdND" ||
- Name == "TAILJMPdNDt" ||
+ Name == "TAILJMPd" || Name == "TAILJMPdt" ||
+ Name == "TAILJMPdND" || Name == "TAILJMPdNDt" ||
Name == "TAILJMPr" || Name == "TAILJMPrND" ||
Name == "MOVr_TC")
return false;
Modified: llvm/branches/wendling/eh/utils/TableGen/EDEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/utils/TableGen/EDEmitter.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/utils/TableGen/EDEmitter.cpp (original)
+++ llvm/branches/wendling/eh/utils/TableGen/EDEmitter.cpp Thu Jul 8 03:14:09 2010
@@ -347,6 +347,7 @@
LEA("lea64mem");
// all I
+ PCR("i16imm_pcrel");
PCR("i32imm_pcrel");
PCR("i64i32imm_pcrel");
PCR("brtarget8");
Modified: llvm/branches/wendling/eh/utils/TableGen/X86RecognizableInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/utils/TableGen/X86RecognizableInstr.cpp?rev=107861&r1=107860&r2=107861&view=diff
==============================================================================
--- llvm/branches/wendling/eh/utils/TableGen/X86RecognizableInstr.cpp (original)
+++ llvm/branches/wendling/eh/utils/TableGen/X86RecognizableInstr.cpp Thu Jul 8 03:14:09 2010
@@ -836,6 +836,7 @@
TYPE("RST", TYPE_ST)
TYPE("i128mem", TYPE_M128)
TYPE("i64i32imm_pcrel", TYPE_REL64)
+ TYPE("i16imm_pcrel", TYPE_REL16)
TYPE("i32imm_pcrel", TYPE_REL32)
TYPE("SSECC", TYPE_IMM3)
TYPE("brtarget", TYPE_RELv)
@@ -955,6 +956,7 @@
ENCODING("i64i8imm", ENCODING_IB)
ENCODING("i8imm", ENCODING_IB)
ENCODING("i64i32imm_pcrel", ENCODING_ID)
+ ENCODING("i16imm_pcrel", ENCODING_IW)
ENCODING("i32imm_pcrel", ENCODING_ID)
ENCODING("brtarget", ENCODING_Iv)
ENCODING("brtarget8", ENCODING_IB)
Propchange: llvm/branches/wendling/eh/utils/count/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/utils/fpcmp/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -6,3 +6,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/utils/not/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/utils/unittest/UnitTestMain/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -5,3 +5,5 @@
Release
Release-Asserts
Release+Coverage
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/utils/unittest/googletest/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Thu Jul 8 03:14:09 2010
@@ -6,3 +6,5 @@
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
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