[llvm-branch-commits] [llvm-branch] r107584 - in /llvm/branches/wendling/eh: ./ docs/ include/llvm/ include/llvm/Analysis/ include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/AsmPrinter/ lib/CodeGen/SelectionDAG/ lib/Target/ lib/Target/ARM/ lib/Target/ARM/AsmPrinter/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CellSPU/ lib/Target/CppBackend/ lib/Target/MBlaze/ lib/Target/MSIL/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/ lib/Target/XCore/ l...
Bill Wendling
isanbard at gmail.com
Sun Jul 4 02:07:55 PDT 2010
Author: void
Date: Sun Jul 4 04:07:55 2010
New Revision: 107584
URL: http://llvm.org/viewvc/llvm-project?rev=107584&view=rev
Log:
Another merge with ToT.
Added:
llvm/branches/wendling/eh/test/CodeGen/X86/2010-07-02-UnfoldBug.ll
- copied unchanged from r107580, llvm/trunk/test/CodeGen/X86/2010-07-02-UnfoldBug.ll
llvm/branches/wendling/eh/test/CodeGen/X86/2010-07-02-asm-alignstack.ll
- copied unchanged from r107580, llvm/trunk/test/CodeGen/X86/2010-07-02-asm-alignstack.ll
Modified:
llvm/branches/wendling/eh/ (props changed)
llvm/branches/wendling/eh/docs/AliasAnalysis.html
llvm/branches/wendling/eh/docs/LangRef.html
llvm/branches/wendling/eh/include/llvm/Analysis/AliasAnalysis.h
llvm/branches/wendling/eh/include/llvm/Analysis/Passes.h
llvm/branches/wendling/eh/include/llvm/CodeGen/LiveInterval.h
llvm/branches/wendling/eh/include/llvm/CodeGen/MachineFrameInfo.h
llvm/branches/wendling/eh/include/llvm/CodeGen/MachineInstr.h
llvm/branches/wendling/eh/include/llvm/CodeGen/SlotIndexes.h
llvm/branches/wendling/eh/include/llvm/InlineAsm.h
llvm/branches/wendling/eh/include/llvm/Instructions.h
llvm/branches/wendling/eh/include/llvm/Target/Target.td
llvm/branches/wendling/eh/include/llvm/Target/TargetOpcodes.h
llvm/branches/wendling/eh/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
llvm/branches/wendling/eh/lib/CodeGen/CalcSpillWeights.cpp
llvm/branches/wendling/eh/lib/CodeGen/InlineSpiller.cpp
llvm/branches/wendling/eh/lib/CodeGen/LiveIntervalAnalysis.cpp
llvm/branches/wendling/eh/lib/CodeGen/LowerSubregs.cpp
llvm/branches/wendling/eh/lib/CodeGen/MachineCSE.cpp
llvm/branches/wendling/eh/lib/CodeGen/MachineFunction.cpp
llvm/branches/wendling/eh/lib/CodeGen/MachineInstr.cpp
llvm/branches/wendling/eh/lib/CodeGen/OptimizePHIs.cpp
llvm/branches/wendling/eh/lib/CodeGen/PreAllocSplitting.cpp
llvm/branches/wendling/eh/lib/CodeGen/ProcessImplicitDefs.cpp
llvm/branches/wendling/eh/lib/CodeGen/PrologEpilogInserter.cpp
llvm/branches/wendling/eh/lib/CodeGen/RegAllocFast.cpp
llvm/branches/wendling/eh/lib/CodeGen/RegAllocLinearScan.cpp
llvm/branches/wendling/eh/lib/CodeGen/RegisterCoalescer.cpp
llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
llvm/branches/wendling/eh/lib/CodeGen/SimpleRegisterCoalescing.cpp
llvm/branches/wendling/eh/lib/CodeGen/TwoAddressInstructionPass.cpp
llvm/branches/wendling/eh/lib/Target/ARM/ARM.h
llvm/branches/wendling/eh/lib/Target/ARM/ARMISelLowering.cpp
llvm/branches/wendling/eh/lib/Target/ARM/ARMTargetMachine.cpp
llvm/branches/wendling/eh/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
llvm/branches/wendling/eh/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp
llvm/branches/wendling/eh/lib/Target/ARM/Thumb2ITBlockPass.cpp
llvm/branches/wendling/eh/lib/Target/Alpha/AlphaISelLowering.cpp
llvm/branches/wendling/eh/lib/Target/Blackfin/BlackfinISelLowering.cpp
llvm/branches/wendling/eh/lib/Target/CellSPU/SPUISelLowering.cpp
llvm/branches/wendling/eh/lib/Target/CppBackend/CPPBackend.cpp
llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeISelLowering.cpp
llvm/branches/wendling/eh/lib/Target/MSIL/MSILWriter.cpp
llvm/branches/wendling/eh/lib/Target/MSP430/MSP430ISelLowering.cpp
llvm/branches/wendling/eh/lib/Target/MSP430/MSP430RegisterInfo.cpp
llvm/branches/wendling/eh/lib/Target/Mips/MipsISelLowering.cpp
llvm/branches/wendling/eh/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/branches/wendling/eh/lib/Target/PowerPC/PPCRegisterInfo.cpp
llvm/branches/wendling/eh/lib/Target/README.txt
llvm/branches/wendling/eh/lib/Target/Sparc/SparcISelLowering.cpp
llvm/branches/wendling/eh/lib/Target/SystemZ/SystemZISelLowering.cpp
llvm/branches/wendling/eh/lib/Target/X86/X86ISelLowering.cpp
llvm/branches/wendling/eh/lib/Target/X86/X86InstrInfo.cpp
llvm/branches/wendling/eh/lib/Target/X86/X86InstrSSE.td
llvm/branches/wendling/eh/lib/Target/X86/X86MCCodeEmitter.cpp
llvm/branches/wendling/eh/lib/Target/X86/X86RegisterInfo.cpp
llvm/branches/wendling/eh/lib/Target/XCore/XCoreISelLowering.cpp
llvm/branches/wendling/eh/lib/Target/XCore/XCoreRegisterInfo.cpp
llvm/branches/wendling/eh/lib/Transforms/Scalar/DeadStoreElimination.cpp
llvm/branches/wendling/eh/lib/Transforms/Utils/ValueMapper.cpp
llvm/branches/wendling/eh/test/CodeGen/ARM/vmov.ll
llvm/branches/wendling/eh/test/CodeGen/Thumb/push.ll
llvm/branches/wendling/eh/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll
llvm/branches/wendling/eh/test/CodeGen/X86/inline-asm-tied.ll
llvm/branches/wendling/eh/test/CodeGen/X86/iv-users-in-other-loops.ll
llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_32-encoding.s
llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_64-encoding.s
llvm/branches/wendling/eh/utils/TableGen/CodeEmitterGen.cpp
llvm/branches/wendling/eh/utils/TableGen/CodeGenTarget.cpp
Propchange: llvm/branches/wendling/eh/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Sun Jul 4 04:07:55 2010
@@ -1 +1 @@
-/llvm/trunk:104459-107464
+/llvm/trunk:104459-107580
Modified: llvm/branches/wendling/eh/docs/AliasAnalysis.html
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/docs/AliasAnalysis.html?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/docs/AliasAnalysis.html (original)
+++ llvm/branches/wendling/eh/docs/AliasAnalysis.html Sun Jul 4 04:07:55 2010
@@ -192,12 +192,20 @@
</div>
<div class="doc_text">
-<p>The NoAlias response is used when the two pointers refer to distinct objects,
-regardless of whether the pointers compare equal. For example, freed pointers
-don't alias any pointers that were allocated afterwards. As a degenerate case,
-pointers returned by malloc(0) have no bytes for an object, and are considered
-NoAlias even when malloc returns the same pointer. The same rule applies to
-NULL pointers.</p>
+<p>The NoAlias response may be used when there is never an immediate dependence
+between any memory reference <i>based</i> on one pointer and any memory
+reference <i>based</i> the other. The most obvious example is when the two
+pointers point to non-overlapping memory ranges. Another is when the two
+pointers are only ever used for reading memory. Another is when the memory is
+freed and reallocated between accesses through one pointer and accesses through
+the other -- in this case, there is a dependence, but it's mediated by the free
+and reallocation.</p>
+
+<p>As an exception to this is with the
+<a href="LangRef.html#noalias"><tt>noalias</tt></a> keyword. AliasAnalysis
+implementations may choose to respect the <tt>noalias</tt> keyword and ignore
+the "irrelevant" dependencies, provided their clients do not need to be aware
+of these dependencies for correctness.</p>
<p>The MayAlias response is used whenever the two pointers might refer to the
same object. If the two memory objects overlap, but do not start at the same
Modified: llvm/branches/wendling/eh/docs/LangRef.html
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/docs/LangRef.html?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/docs/LangRef.html (original)
+++ llvm/branches/wendling/eh/docs/LangRef.html Sun Jul 4 04:07:55 2010
@@ -1042,7 +1042,7 @@
generator that usually indicates a desired alignment for the synthesized
stack slot.</dd>
- <dt><tt><b>sret</b></tt></dt>
+ <dt><tt><b><a name="sret">sret</a></b></tt></dt>
<dd>This indicates that the pointer parameter specifies the address of a
structure that is the return value of the function in the source program.
This pointer must be guaranteed by the caller to be valid: loads and
@@ -1050,22 +1050,26 @@
may only be applied to the first parameter. This is not a valid attribute
for return values. </dd>
- <dt><tt><b>noalias</b></tt></dt>
- <dd>This indicates that the pointer does not alias any global or any other
- parameter. The caller is responsible for ensuring that this is the
- case. On a function return value, <tt>noalias</tt> additionally indicates
- that the pointer does not alias any other pointers visible to the
- caller. For further details, please see the discussion of the NoAlias
- response in
- <a href="http://llvm.org/docs/AliasAnalysis.html#MustMayNo">alias
- analysis</a>.</dd>
+ <dt><tt><b><a name="noalias">noalias</a></b></tt></dt>
+ <dd>This indicates that pointer values
+ <a href="#pointeraliasing"><i>based</i></a> on the argument or return
+ value do not alias pointer values which are not <i>based</i> on it,
+ ignoring certain "irrelevant" dependencies.
+ For a call to the parent function, dependencies between memory
+ references from before or after the call and from those during the call
+ are "irrelevant" to the <tt>noalias</tt> keyword for the arguments and
+ return value used in that call.
+ The caller shares the responsibility with the callee for ensuring that
+ these requirements are met.
+ For further details, please see the discussion of the NoAlias response in
+ <a href="AliasAnalysis.html#MustMayNo">alias analysis</a>.</dd>
- <dt><tt><b>nocapture</b></tt></dt>
+ <dt><tt><b><a name="nocapture">nocapture</a></b></tt></dt>
<dd>This indicates that the callee does not make any copies of the pointer
that outlive the callee itself. This is not a valid attribute for return
values.</dd>
- <dt><tt><b>nest</b></tt></dt>
+ <dt><tt><b><a name="nest">nest</a></b></tt></dt>
<dd>This indicates that the pointer parameter can be excised using the
<a href="#int_trampoline">trampoline intrinsics</a>. This is not a valid
attribute for return values.</dd>
@@ -1367,29 +1371,41 @@
according to the following rules:</p>
<ul>
- <li>A pointer value formed from a
- <tt><a href="#i_getelementptr">getelementptr</a></tt> instruction
- is associated with the addresses associated with the first operand
- of the <tt>getelementptr</tt>.</li>
+ <li>A pointer value is associated with the addresses associated with
+ any value it is <i>based</i> on.
<li>An address of a global variable is associated with the address
range of the variable's storage.</li>
<li>The result value of an allocation instruction is associated with
the address range of the allocated storage.</li>
<li>A null pointer in the default address-space is associated with
no address.</li>
- <li>A pointer value formed by an
- <tt><a href="#i_inttoptr">inttoptr</a></tt> is associated with all
- address ranges of all pointer values that contribute (directly or
- indirectly) to the computation of the pointer's value.</li>
- <li>The result value of a
- <tt><a href="#i_bitcast">bitcast</a></tt> is associated with all
- addresses associated with the operand of the <tt>bitcast</tt>.</li>
<li>An integer constant other than zero or a pointer value returned
from a function not defined within LLVM may be associated with address
ranges allocated through mechanisms other than those provided by
LLVM. Such ranges shall not overlap with any ranges of addresses
allocated by mechanisms provided by LLVM.</li>
- </ul>
+</ul>
+
+<p>A pointer value is <i>based</i> on another pointer value according
+ to the following rules:</p>
+
+<ul>
+ <li>A pointer value formed from a
+ <tt><a href="#i_getelementptr">getelementptr</a></tt> operation
+ is <i>based</i> on the first operand of the <tt>getelementptr</tt>.</li>
+ <li>The result value of a
+ <tt><a href="#i_bitcast">bitcast</a></tt> is <i>based</i> on the operand
+ of the <tt>bitcast</tt>.</li>
+ <li>A pointer value formed by an
+ <tt><a href="#i_inttoptr">inttoptr</a></tt> is <i>based</i> on all
+ pointer values that contribute (directly or indirectly) to the
+ computation of the pointer's value.</li>
+ <li>The "<i>based</i> on" relationship is transitive.</li>
+</ul>
+
+<p>Note that this definition of <i>"based"</i> is intentionally
+ similar to the definition of <i>"based"</i> in C99, though it is
+ slightly weaker.</p>
<p>LLVM IR does not associate types with memory. The result type of a
<tt><a href="#i_load">load</a></tt> merely indicates the size and
@@ -6949,7 +6965,8 @@
<div class="doc_text">
<p>This intrinsic makes it possible to excise one parameter, marked with
- the <tt>nest</tt> attribute, from a function. The result is a callable
+ the <a href="#nest"><tt>nest</tt></a> attribute, from a function.
+ The result is a callable
function pointer lacking the nest parameter - the caller does not need to
provide a value for it. Instead, the value to use is stored in advance in a
"trampoline", a block of memory usually allocated on the stack, which also
Modified: llvm/branches/wendling/eh/include/llvm/Analysis/AliasAnalysis.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Analysis/AliasAnalysis.h?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Analysis/AliasAnalysis.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Analysis/AliasAnalysis.h Sun Jul 4 04:07:55 2010
@@ -165,27 +165,6 @@
/// ModRefInfo - Whether the pointer is loaded or stored to/from.
///
ModRefResult ModRefInfo;
-
- /// AccessType - Specific fine-grained access information for the argument.
- /// If none of these classifications is general enough, the
- /// getModRefBehavior method should not return AccessesArguments*. If a
- /// record is not returned for a particular argument, the argument is never
- /// dead and never dereferenced.
- enum AccessType {
- /// ScalarAccess - The pointer is dereferenced.
- ///
- ScalarAccess,
-
- /// ArrayAccess - The pointer is indexed through as an array of elements.
- ///
- ArrayAccess,
-
- /// ElementAccess ?? P->F only?
-
- /// CallsThrough - Indirect calls are made through the specified function
- /// pointer.
- CallsThrough
- };
};
/// getModRefBehavior - Return the behavior when calling the given call site.
Modified: llvm/branches/wendling/eh/include/llvm/Analysis/Passes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Analysis/Passes.h?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Analysis/Passes.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Analysis/Passes.h Sun Jul 4 04:07:55 2010
@@ -67,7 +67,9 @@
//===--------------------------------------------------------------------===//
//
// createBasicAliasAnalysisPass - This pass implements the default alias
- // analysis.
+ // analysis. This analysis respects the noalias attribute, so it is not
+ // suitable for some interprocedural uses (see the discussion of noalias
+ // in AliasAnalysis.html for details).
//
ImmutablePass *createBasicAliasAnalysisPass();
@@ -75,7 +77,8 @@
//
// createInterproceduralBasicAliasAnalysisPass - This pass is similar to
// baiscaa, except that it properly supports queries to values which live
- // in different functions.
+ // in different functions. Unlike the regular BasicAliasAnalysis, this
+ // implementation does not respect the noalias attribute.
//
ImmutablePass *createInterproceduralBasicAliasAnalysisPass();
Modified: llvm/branches/wendling/eh/include/llvm/CodeGen/LiveInterval.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/CodeGen/LiveInterval.h?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/CodeGen/LiveInterval.h (original)
+++ llvm/branches/wendling/eh/include/llvm/CodeGen/LiveInterval.h Sun Jul 4 04:07:55 2010
@@ -439,6 +439,12 @@
return I == end() ? 0 : &*I;
}
+ /// getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
+ VNInfo *getVNInfoAt(SlotIndex Idx) const {
+ const_iterator I = FindLiveRangeContaining(Idx);
+ return I == end() ? 0 : I->valno;
+ }
+
/// FindLiveRangeContaining - Return an iterator to the live range that
/// contains the specified index, or end() if there is none.
const_iterator FindLiveRangeContaining(SlotIndex Idx) const;
Modified: llvm/branches/wendling/eh/include/llvm/CodeGen/MachineFrameInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/CodeGen/MachineFrameInfo.h?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/CodeGen/MachineFrameInfo.h (original)
+++ llvm/branches/wendling/eh/include/llvm/CodeGen/MachineFrameInfo.h Sun Jul 4 04:07:55 2010
@@ -98,8 +98,7 @@
// cannot alias any other memory objects.
bool isSpillSlot;
- StackObject(uint64_t Sz, unsigned Al, int64_t SP, bool IM,
- bool isSS)
+ StackObject(uint64_t Sz, unsigned Al, int64_t SP, bool IM, bool isSS)
: SPOffset(SP), Size(Sz), Alignment(Al), isImmutable(IM),
isSpillSlot(isSS) {}
};
@@ -350,8 +349,7 @@
/// efficiency. By default, fixed objects are immutable. This returns an
/// index with a negative value.
///
- int CreateFixedObject(uint64_t Size, int64_t SPOffset,
- bool Immutable, bool isSS);
+ int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable);
/// isFixedObjectIndex - Returns true if the specified index corresponds to a
Modified: llvm/branches/wendling/eh/include/llvm/CodeGen/MachineInstr.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/CodeGen/MachineInstr.h?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/CodeGen/MachineInstr.h (original)
+++ llvm/branches/wendling/eh/include/llvm/CodeGen/MachineInstr.h Sun Jul 4 04:07:55 2010
@@ -227,7 +227,16 @@
bool isRegSequence() const {
return getOpcode() == TargetOpcode::REG_SEQUENCE;
}
-
+ bool isCopy() const {
+ return getOpcode() == TargetOpcode::COPY;
+ }
+
+ /// isCopyLike - Return true if the instruction behaves like a copy.
+ /// This does not include native copy instructions.
+ bool isCopyLike() const {
+ return isCopy() || isSubregToReg() || isExtractSubreg() || isInsertSubreg();
+ }
+
/// readsRegister - Return true if the MachineInstr reads the specified
/// register. If TargetRegisterInfo is passed, then it also checks if there
/// is a read of a super-register.
Modified: llvm/branches/wendling/eh/include/llvm/CodeGen/SlotIndexes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/CodeGen/SlotIndexes.h?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/CodeGen/SlotIndexes.h (original)
+++ llvm/branches/wendling/eh/include/llvm/CodeGen/SlotIndexes.h Sun Jul 4 04:07:55 2010
@@ -663,15 +663,20 @@
MachineBasicBlock::iterator miItr(mi);
bool needRenumber = false;
IndexListEntry *newEntry;
-
+ // Get previous index, considering that not all instructions are indexed.
IndexListEntry *prevEntry;
- if (miItr == mbb->begin()) {
+ for (;;) {
// If mi is at the mbb beginning, get the prev index from the mbb.
- prevEntry = &mbbRangeItr->second.first.entry();
- } else {
- // Otherwise get it from the previous instr.
- MachineBasicBlock::iterator pItr(prior(miItr));
- prevEntry = &getInstructionIndex(pItr).entry();
+ if (miItr == mbb->begin()) {
+ prevEntry = &mbbRangeItr->second.first.entry();
+ break;
+ }
+ // Otherwise rewind until we find a mapped instruction.
+ Mi2IndexMap::const_iterator itr = mi2iMap.find(--miItr);
+ if (itr != mi2iMap.end()) {
+ prevEntry = &itr->second.entry();
+ break;
+ }
}
// Get next entry from previous entry.
Modified: llvm/branches/wendling/eh/include/llvm/InlineAsm.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/InlineAsm.h?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/InlineAsm.h (original)
+++ llvm/branches/wendling/eh/include/llvm/InlineAsm.h Sun Jul 4 04:07:55 2010
@@ -154,7 +154,8 @@
Op_InputChain = 0,
Op_AsmString = 1,
Op_MDNode = 2,
- Op_FirstOperand = 3,
+ Op_IsAlignStack = 3,
+ Op_FirstOperand = 4,
Kind_RegUse = 1,
Kind_RegDef = 2,
Modified: llvm/branches/wendling/eh/include/llvm/Instructions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Instructions.h?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Instructions.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Instructions.h Sun Jul 4 04:07:55 2010
@@ -940,8 +940,24 @@
unsigned(isTC));
}
+ /// @deprecated these "define hacks" will go away soon
+ /// @brief coerce out-of-tree code to abandon the low-level interfaces
+ /// @detail see below comments and update your code to high-level interfaces
+ /// in LLVM v2.8-only code
+ /// - getOperand(N+1) ---> getArgOperand(N)
+ /// - setOperand(N+1, V) ---> setArgOperand(N, V)
+ /// - getNumOperands() ---> getNumArgOperands()+1 // note the "+1"!
+ ///
+ /// in backward compatible code please consult llvm/Support/CallSite.h,
+ /// you should create a callsite using the CallInst pointer and call its methods
+ ///
+# define public private
+# define protected private
/// Provide fast operand accessors
DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
+# undef public
+# undef protected
+public:
enum { ArgOffset = 1 }; ///< temporary, do not use for new code!
unsigned getNumArgOperands() const { return getNumOperands() - 1; }
@@ -951,7 +967,7 @@
/// Provide compile-time errors for accessing operand 0
/// @deprecated these will go away soon
/// @detail see below comments and update your code to high-level interfaces
- /// - getOperand(0) ---> getCalledValue()
+ /// - getOperand(0) ---> getCalledValue(), or possibly getCalledFunction()
/// - setOperand(0, V) ---> setCalledFunction(V)
///
private:
@@ -1107,6 +1123,10 @@
typename std::iterator_traits<InputIterator>::iterator_category());
}
+
+// Note: if you get compile errors about private methods then
+// please update your code to use the high-level operand
+// interfaces. See line 943 above.
DEFINE_TRANSPARENT_OPERAND_ACCESSORS(CallInst, Value)
//===----------------------------------------------------------------------===//
Modified: llvm/branches/wendling/eh/include/llvm/Target/Target.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Target/Target.td?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Target/Target.td (original)
+++ llvm/branches/wendling/eh/include/llvm/Target/Target.td Sun Jul 4 04:07:55 2010
@@ -396,24 +396,23 @@
}
// Standard Pseudo Instructions.
-let isCodeGenOnly = 1 in {
+// This list must match TargetOpcodes.h and CodeGenTarget.cpp.
+// Only these instructions are allowed in the TargetOpcode namespace.
+let isCodeGenOnly = 1, Namespace = "TargetOpcode" in {
def PHI : Instruction {
let OutOperandList = (outs);
let InOperandList = (ins variable_ops);
let AsmString = "PHINODE";
- let Namespace = "TargetOpcode";
}
def INLINEASM : Instruction {
let OutOperandList = (outs);
let InOperandList = (ins variable_ops);
let AsmString = "";
- let Namespace = "TargetOpcode";
}
def DBG_LABEL : Instruction {
let OutOperandList = (outs);
let InOperandList = (ins i32imm:$id);
let AsmString = "";
- let Namespace = "TargetOpcode";
let hasCtrlDep = 1;
let isNotDuplicable = 1;
}
@@ -421,7 +420,6 @@
let OutOperandList = (outs);
let InOperandList = (ins i32imm:$id);
let AsmString = "";
- let Namespace = "TargetOpcode";
let hasCtrlDep = 1;
let isNotDuplicable = 1;
}
@@ -429,7 +427,6 @@
let OutOperandList = (outs);
let InOperandList = (ins i32imm:$id);
let AsmString = "";
- let Namespace = "TargetOpcode";
let hasCtrlDep = 1;
let isNotDuplicable = 1;
}
@@ -437,21 +434,18 @@
let OutOperandList = (outs);
let InOperandList = (ins variable_ops);
let AsmString = "";
- let Namespace = "TargetOpcode";
let neverHasSideEffects = 1;
}
def EXTRACT_SUBREG : Instruction {
let OutOperandList = (outs unknown:$dst);
let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
let AsmString = "";
- let Namespace = "TargetOpcode";
let neverHasSideEffects = 1;
}
def INSERT_SUBREG : Instruction {
let OutOperandList = (outs unknown:$dst);
let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
let AsmString = "";
- let Namespace = "TargetOpcode";
let neverHasSideEffects = 1;
let Constraints = "$supersrc = $dst";
}
@@ -459,7 +453,6 @@
let OutOperandList = (outs unknown:$dst);
let InOperandList = (ins);
let AsmString = "";
- let Namespace = "TargetOpcode";
let neverHasSideEffects = 1;
let isReMaterializable = 1;
let isAsCheapAsAMove = 1;
@@ -468,14 +461,12 @@
let OutOperandList = (outs unknown:$dst);
let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
let AsmString = "";
- let Namespace = "TargetOpcode";
let neverHasSideEffects = 1;
}
def COPY_TO_REGCLASS : Instruction {
let OutOperandList = (outs unknown:$dst);
let InOperandList = (ins unknown:$src, i32imm:$regclass);
let AsmString = "";
- let Namespace = "TargetOpcode";
let neverHasSideEffects = 1;
let isAsCheapAsAMove = 1;
}
@@ -483,15 +474,19 @@
let OutOperandList = (outs);
let InOperandList = (ins variable_ops);
let AsmString = "DBG_VALUE";
- let Namespace = "TargetOpcode";
let isAsCheapAsAMove = 1;
}
-
def REG_SEQUENCE : Instruction {
let OutOperandList = (outs unknown:$dst);
let InOperandList = (ins variable_ops);
let AsmString = "";
- let Namespace = "TargetOpcode";
+ let neverHasSideEffects = 1;
+ let isAsCheapAsAMove = 1;
+}
+def COPY : Instruction {
+ let OutOperandList = (outs unknown:$dst);
+ let InOperandList = (ins unknown:$src);
+ let AsmString = "";
let neverHasSideEffects = 1;
let isAsCheapAsAMove = 1;
}
Modified: llvm/branches/wendling/eh/include/llvm/Target/TargetOpcodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Target/TargetOpcodes.h?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Target/TargetOpcodes.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Target/TargetOpcodes.h Sun Jul 4 04:07:55 2010
@@ -15,27 +15,31 @@
#define LLVM_TARGET_TARGETOPCODES_H
namespace llvm {
-
+
/// Invariant opcodes: All instruction sets have these as their low opcodes.
+///
+/// Every instruction defined here must also appear in Target.td and the order
+/// must be the same as in CodeGenTarget.cpp.
+///
namespace TargetOpcode {
- enum {
+ enum {
PHI = 0,
INLINEASM = 1,
DBG_LABEL = 2,
EH_LABEL = 3,
GC_LABEL = 4,
-
+
/// KILL - This instruction is a noop that is used only to adjust the
/// liveness of registers. This can be useful when dealing with
/// sub-registers.
KILL = 5,
-
+
/// EXTRACT_SUBREG - This instruction takes two operands: a register
/// that has subregisters, and a subregister index. It returns the
/// extracted subregister value. This is commonly used to implement
/// truncation operations on target architectures which support it.
EXTRACT_SUBREG = 6,
-
+
/// INSERT_SUBREG - This instruction takes three operands: a register that
/// has subregisters, a register providing an insert value, and a
/// subregister index. It returns the value of the first register with the
@@ -43,16 +47,16 @@
/// defined by an IMPLICIT_DEF, because it is commonly used to implement
/// anyext operations on target architectures which support it.
INSERT_SUBREG = 7,
-
+
/// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
IMPLICIT_DEF = 8,
-
+
/// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that
/// the first operand is an immediate integer constant. This constant is
/// often zero, because it is commonly used to assert that the instruction
/// defining the register implicitly clears the high bits.
SUBREG_TO_REG = 9,
-
+
/// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
/// register-to-register copy into a specific register class. This is only
/// used between instruction selection and MachineInstr creation, before
@@ -71,7 +75,11 @@
/// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5
/// After register coalescing references of v1024 should be replace with
/// v1027:3, v1025 with v1027:4, etc.
- REG_SEQUENCE = 12
+ REG_SEQUENCE = 12,
+
+ /// COPY - Target-independent register copy. This instruction can also be
+ /// used to copy between subregisters of virtual registers.
+ COPY = 13
};
} // end namespace TargetOpcode
} // end namespace llvm
Modified: llvm/branches/wendling/eh/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp Sun Jul 4 04:07:55 2010
@@ -279,7 +279,7 @@
// Okay, we finally have a value number. Ask the target to print this
// operand!
if (CurVariant == -1 || CurVariant == AsmPrinterVariant) {
- unsigned OpNo = 1;
+ unsigned OpNo = 2;
bool Error = false;
Modified: llvm/branches/wendling/eh/lib/CodeGen/CalcSpillWeights.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/CalcSpillWeights.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/CalcSpillWeights.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/CalcSpillWeights.cpp Sun Jul 4 04:07:55 2010
@@ -116,7 +116,7 @@
SmallVector<LiveInterval*, 4> spillIs;
if (lis->isReMaterializable(li, spillIs, isLoad)) {
// If all of the definitions of the interval are re-materializable,
- // it is a preferred candidate for spilling. If non of the defs are
+ // it is a preferred candidate for spilling. If none of the defs are
// loads, then it's potentially very cheap to re-materialize.
// FIXME: this gets much more complicated once we support non-trivial
// re-materialization.
Modified: llvm/branches/wendling/eh/lib/CodeGen/InlineSpiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/InlineSpiller.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/InlineSpiller.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/InlineSpiller.cpp Sun Jul 4 04:07:55 2010
@@ -39,10 +39,17 @@
// Variables that are valid during spill(), but used by multiple methods.
LiveInterval *li_;
+ std::vector<LiveInterval*> *newIntervals_;
const TargetRegisterClass *rc_;
int stackSlot_;
const SmallVectorImpl<LiveInterval*> *spillIs_;
+ // Values of the current interval that can potentially remat.
+ SmallPtrSet<VNInfo*, 8> reMattable_;
+
+ // Values in reMattable_ that failed to remat at some point.
+ SmallPtrSet<VNInfo*, 8> usedValues_;
+
~InlineSpiller() {}
public:
@@ -58,7 +65,13 @@
std::vector<LiveInterval*> &newIntervals,
SmallVectorImpl<LiveInterval*> &spillIs,
SlotIndex *earliestIndex);
- bool reMaterialize(LiveInterval &NewLI, MachineBasicBlock::iterator MI);
+
+private:
+ bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx,
+ SlotIndex UseIdx);
+ bool reMaterializeFor(MachineBasicBlock::iterator MI);
+ void reMaterializeAll();
+
bool foldMemoryOperand(MachineBasicBlock::iterator MI,
const SmallVectorImpl<unsigned> &Ops);
void insertReload(LiveInterval &NewLI, MachineBasicBlock::iterator MI);
@@ -75,79 +88,180 @@
}
}
-/// reMaterialize - Attempt to rematerialize li_->reg before MI instead of
+/// allUsesAvailableAt - Return true if all registers used by OrigMI at
+/// OrigIdx are also available with the same value at UseIdx.
+bool InlineSpiller::allUsesAvailableAt(const MachineInstr *OrigMI,
+ SlotIndex OrigIdx,
+ SlotIndex UseIdx) {
+ OrigIdx = OrigIdx.getUseIndex();
+ UseIdx = UseIdx.getUseIndex();
+ for (unsigned i = 0, e = OrigMI->getNumOperands(); i != e; ++i) {
+ const MachineOperand &MO = OrigMI->getOperand(i);
+ if (!MO.isReg() || !MO.getReg() || MO.getReg() == li_->reg)
+ continue;
+ // Reserved registers are OK.
+ if (MO.isUndef() || !lis_.hasInterval(MO.getReg()))
+ continue;
+ // We don't want to move any defs.
+ if (MO.isDef())
+ return false;
+ // We cannot depend on virtual registers in spillIs_. They will be spilled.
+ for (unsigned si = 0, se = spillIs_->size(); si != se; ++si)
+ if ((*spillIs_)[si]->reg == MO.getReg())
+ return false;
+
+ LiveInterval &LI = lis_.getInterval(MO.getReg());
+ const VNInfo *OVNI = LI.getVNInfoAt(OrigIdx);
+ if (!OVNI)
+ continue;
+ if (OVNI != LI.getVNInfoAt(UseIdx))
+ return false;
+ }
+ return true;
+}
+
+/// reMaterializeFor - Attempt to rematerialize li_->reg before MI instead of
/// reloading it.
-bool InlineSpiller::reMaterialize(LiveInterval &NewLI,
- MachineBasicBlock::iterator MI) {
+bool InlineSpiller::reMaterializeFor(MachineBasicBlock::iterator MI) {
SlotIndex UseIdx = lis_.getInstructionIndex(MI).getUseIndex();
- LiveRange *LR = li_->getLiveRangeContaining(UseIdx);
- if (!LR) {
- DEBUG(dbgs() << "\tundef at " << UseIdx << ", adding <undef> flags.\n");
+ VNInfo *OrigVNI = li_->getVNInfoAt(UseIdx);
+ if (!OrigVNI) {
+ DEBUG(dbgs() << "\tadding <undef> flags: ");
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (MO.isReg() && MO.isUse() && MO.getReg() == li_->reg)
MO.setIsUndef();
}
+ DEBUG(dbgs() << UseIdx << '\t' << *MI);
return true;
}
-
- // Find the instruction that defined this value of li_->reg.
- if (!LR->valno->isDefAccurate())
- return false;
- SlotIndex OrigDefIdx = LR->valno->def;
- MachineInstr *OrigDefMI = lis_.getInstructionFromIndex(OrigDefIdx);
- if (!OrigDefMI)
+ if (!reMattable_.count(OrigVNI)) {
+ DEBUG(dbgs() << "\tusing non-remat valno " << OrigVNI->id << ": "
+ << UseIdx << '\t' << *MI);
return false;
-
- // FIXME: Provide AliasAnalysis argument.
- if (!tii_.isTriviallyReMaterializable(OrigDefMI))
+ }
+ MachineInstr *OrigMI = lis_.getInstructionFromIndex(OrigVNI->def);
+ if (!allUsesAvailableAt(OrigMI, OrigVNI->def, UseIdx)) {
+ usedValues_.insert(OrigVNI);
+ DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << *MI);
return false;
+ }
- // A rematerializable instruction may be using other virtual registers.
- // Make sure they are available at the new location.
- for (unsigned i = 0, e = OrigDefMI->getNumOperands(); i != e; ++i) {
- MachineOperand &MO = OrigDefMI->getOperand(i);
- if (!MO.isReg() || !MO.getReg() || MO.getReg() == li_->reg)
- continue;
- // Reserved physregs are OK. Others are not (probably from coalescing).
- if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
- if (reserved_.test(MO.getReg()))
- continue;
- else
+ // If the instruction also writes li_->reg, it had better not require the same
+ // register for uses and defs.
+ bool Reads, Writes;
+ SmallVector<unsigned, 8> Ops;
+ tie(Reads, Writes) = MI->readsWritesVirtualRegister(li_->reg, &Ops);
+ if (Writes) {
+ for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
+ MachineOperand &MO = MI->getOperand(Ops[i]);
+ if (MO.isUse() ? MI->isRegTiedToDefOperand(Ops[i]) : MO.getSubReg()) {
+ usedValues_.insert(OrigVNI);
+ DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << *MI);
return false;
+ }
}
- // We don't want to move any virtual defs.
- if (MO.isDef())
- return false;
- // We have a use of a virtual register other than li_->reg.
- if (MO.isUndef())
- continue;
- // We cannot depend on virtual registers in spillIs_. They will be spilled.
- for (unsigned si = 0, se = spillIs_->size(); si != se; ++si)
- if ((*spillIs_)[si]->reg == MO.getReg())
- return false;
-
- // Is the register available here with the same value as at OrigDefMI?
- LiveInterval &ULI = lis_.getInterval(MO.getReg());
- LiveRange *HereLR = ULI.getLiveRangeContaining(UseIdx);
- if (!HereLR)
- return false;
- LiveRange *DefLR = ULI.getLiveRangeContaining(OrigDefIdx.getUseIndex());
- if (!DefLR || DefLR->valno != HereLR->valno)
- return false;
}
- // Finally we can rematerialize OrigDefMI before MI.
+ // Alocate a new register for the remat.
+ unsigned NewVReg = mri_.createVirtualRegister(rc_);
+ vrm_.grow();
+ LiveInterval &NewLI = lis_.getOrCreateInterval(NewVReg);
+ NewLI.markNotSpillable();
+ newIntervals_->push_back(&NewLI);
+
+ // Finally we can rematerialize OrigMI before MI.
MachineBasicBlock &MBB = *MI->getParent();
- tii_.reMaterialize(MBB, MI, NewLI.reg, 0, OrigDefMI, tri_);
- SlotIndex DefIdx = lis_.InsertMachineInstrInMaps(--MI).getDefIndex();
- DEBUG(dbgs() << "\tremat: " << DefIdx << '\t' << *MI);
+ tii_.reMaterialize(MBB, MI, NewLI.reg, 0, OrigMI, tri_);
+ MachineBasicBlock::iterator RematMI = MI;
+ SlotIndex DefIdx = lis_.InsertMachineInstrInMaps(--RematMI).getDefIndex();
+ DEBUG(dbgs() << "\tremat: " << DefIdx << '\t' << *RematMI);
+
+ // Replace operands
+ for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
+ MachineOperand &MO = MI->getOperand(Ops[i]);
+ if (MO.isReg() && MO.isUse() && MO.getReg() == li_->reg) {
+ MO.setReg(NewVReg);
+ MO.setIsKill();
+ }
+ }
+ DEBUG(dbgs() << "\t " << UseIdx << '\t' << *MI);
+
VNInfo *DefVNI = NewLI.getNextValue(DefIdx, 0, true,
lis_.getVNInfoAllocator());
NewLI.addRange(LiveRange(DefIdx, UseIdx.getDefIndex(), DefVNI));
+ DEBUG(dbgs() << "\tinterval: " << NewLI << '\n');
return true;
}
+/// reMaterializeAll - Try to rematerialize as many uses of li_ as possible,
+/// and trim the live ranges after.
+void InlineSpiller::reMaterializeAll() {
+ // Do a quick scan of the interval values to find if any are remattable.
+ reMattable_.clear();
+ usedValues_.clear();
+ for (LiveInterval::const_vni_iterator I = li_->vni_begin(),
+ E = li_->vni_end(); I != E; ++I) {
+ VNInfo *VNI = *I;
+ if (VNI->isUnused() || !VNI->isDefAccurate())
+ continue;
+ MachineInstr *DefMI = lis_.getInstructionFromIndex(VNI->def);
+ if (!DefMI || !tii_.isTriviallyReMaterializable(DefMI))
+ continue;
+ reMattable_.insert(VNI);
+ }
+
+ // Often, no defs are remattable.
+ if (reMattable_.empty())
+ return;
+
+ // Try to remat before all uses of li_->reg.
+ bool anyRemat = false;
+ for (MachineRegisterInfo::use_nodbg_iterator
+ RI = mri_.use_nodbg_begin(li_->reg);
+ MachineInstr *MI = RI.skipInstruction();)
+ anyRemat |= reMaterializeFor(MI);
+
+ if (!anyRemat)
+ return;
+
+ // Remove any values that were completely rematted.
+ bool anyRemoved = false;
+ for (SmallPtrSet<VNInfo*, 8>::iterator I = reMattable_.begin(),
+ E = reMattable_.end(); I != E; ++I) {
+ VNInfo *VNI = *I;
+ if (VNI->hasPHIKill() || usedValues_.count(VNI))
+ continue;
+ MachineInstr *DefMI = lis_.getInstructionFromIndex(VNI->def);
+ DEBUG(dbgs() << "\tremoving dead def: " << VNI->def << '\t' << *DefMI);
+ lis_.RemoveMachineInstrFromMaps(DefMI);
+ vrm_.RemoveMachineInstrFromMaps(DefMI);
+ DefMI->eraseFromParent();
+ li_->removeValNo(VNI);
+ anyRemoved = true;
+ }
+
+ if (!anyRemoved)
+ return;
+
+ // Removing values may cause debug uses where li_ is not live.
+ for (MachineRegisterInfo::use_iterator RI = mri_.use_begin(li_->reg);
+ MachineInstr *MI = RI.skipInstruction();) {
+ if (!MI->isDebugValue())
+ continue;
+ // Try to preserve the debug value if li_ is live immediately after it.
+ MachineBasicBlock::iterator NextMI = MI;
+ ++NextMI;
+ if (NextMI != MI->getParent()->end() && !lis_.isNotInMIMap(NextMI)) {
+ SlotIndex NearIdx = lis_.getInstructionIndex(NextMI);
+ if (li_->liveAt(NearIdx))
+ continue;
+ }
+ DEBUG(dbgs() << "Removing debug info due to remat:" << "\t" << *MI);
+ MI->eraseFromParent();
+ }
+}
+
/// foldMemoryOperand - Try folding stack slot references in Ops into MI.
/// Return true on success, and MI will be erased.
bool InlineSpiller::foldMemoryOperand(MachineBasicBlock::iterator MI,
@@ -218,19 +332,49 @@
assert(!li->isStackSlot() && "Trying to spill a stack slot.");
li_ = li;
+ newIntervals_ = &newIntervals;
rc_ = mri_.getRegClass(li->reg);
- stackSlot_ = vrm_.assignVirt2StackSlot(li->reg);
spillIs_ = &spillIs;
+ reMaterializeAll();
+
+ // Remat may handle everything.
+ if (li_->empty())
+ return;
+
+ stackSlot_ = vrm_.assignVirt2StackSlot(li->reg);
+
// Iterate over instructions using register.
for (MachineRegisterInfo::reg_iterator RI = mri_.reg_begin(li->reg);
MachineInstr *MI = RI.skipInstruction();) {
+ // Debug values are not allowed to affect codegen.
+ if (MI->isDebugValue()) {
+ // Modify DBG_VALUE now that the value is in a spill slot.
+ uint64_t Offset = MI->getOperand(1).getImm();
+ const MDNode *MDPtr = MI->getOperand(2).getMetadata();
+ DebugLoc DL = MI->getDebugLoc();
+ if (MachineInstr *NewDV = tii_.emitFrameIndexDebugValue(mf_, stackSlot_,
+ Offset, MDPtr, DL)) {
+ DEBUG(dbgs() << "Modifying debug info due to spill:" << "\t" << *MI);
+ MachineBasicBlock *MBB = MI->getParent();
+ MBB->insert(MBB->erase(MI), NewDV);
+ } else {
+ DEBUG(dbgs() << "Removing debug info due to spill:" << "\t" << *MI);
+ MI->eraseFromParent();
+ }
+ continue;
+ }
+
// Analyze instruction.
bool Reads, Writes;
SmallVector<unsigned, 8> Ops;
tie(Reads, Writes) = MI->readsWritesVirtualRegister(li->reg, &Ops);
+ // Attempt to fold memory ops.
+ if (foldMemoryOperand(MI, Ops))
+ continue;
+
// Allocate interval around instruction.
// FIXME: Infer regclass from instruction alone.
unsigned NewVReg = mri_.createVirtualRegister(rc_);
@@ -238,14 +382,7 @@
LiveInterval &NewLI = lis_.getOrCreateInterval(NewVReg);
NewLI.markNotSpillable();
- // Attempt remat instead of reload.
- bool NeedsReload = Reads && !reMaterialize(NewLI, MI);
-
- // Attempt to fold memory ops.
- if (NewLI.empty() && foldMemoryOperand(MI, Ops))
- continue;
-
- if (NeedsReload)
+ if (Reads)
insertReload(NewLI, MI);
// Rewrite instruction operands.
Modified: llvm/branches/wendling/eh/lib/CodeGen/LiveIntervalAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/LiveIntervalAnalysis.cpp Sun Jul 4 04:07:55 2010
@@ -321,7 +321,7 @@
MachineInstr *CopyMI = NULL;
unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
- if (mi->isExtractSubreg() || mi->isInsertSubreg() || mi->isSubregToReg() ||
+ if (mi->isCopyLike() ||
tii_->isMoveInstr(*mi, SrcReg, DstReg, SrcSubReg, DstSubReg)) {
CopyMI = mi;
@@ -457,8 +457,8 @@
// A re-def may be a copy. e.g. %reg1030:6<def> = VMOVD %reg1026, ...
unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
- if (PartReDef &&
- tii_->isMoveInstr(*mi, SrcReg, DstReg, SrcSubReg, DstSubReg))
+ if (PartReDef && (mi->isCopyLike() ||
+ tii_->isMoveInstr(*mi, SrcReg, DstReg, SrcSubReg, DstSubReg)))
OldValNo->setCopy(&*mi);
// Add the new live interval which replaces the range for the input copy.
@@ -488,7 +488,7 @@
VNInfo *ValNo;
MachineInstr *CopyMI = NULL;
unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
- if (mi->isExtractSubreg() || mi->isInsertSubreg() || mi->isSubregToReg()||
+ if (mi->isCopyLike() ||
tii_->isMoveInstr(*mi, SrcReg, DstReg, SrcSubReg, DstSubReg))
CopyMI = mi;
ValNo = interval.getNextValue(defIndex, CopyMI, true, VNInfoAllocator);
@@ -605,7 +605,7 @@
else if (allocatableRegs_[MO.getReg()]) {
MachineInstr *CopyMI = NULL;
unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
- if (MI->isExtractSubreg() || MI->isInsertSubreg() || MI->isSubregToReg() ||
+ if (MI->isCopyLike() ||
tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg))
CopyMI = MI;
handlePhysicalRegisterDef(MBB, MI, MIIdx, MO,
Modified: llvm/branches/wendling/eh/lib/CodeGen/LowerSubregs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/LowerSubregs.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/LowerSubregs.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/LowerSubregs.cpp Sun Jul 4 04:07:55 2010
@@ -56,6 +56,7 @@
bool LowerExtract(MachineInstr *MI);
bool LowerInsert(MachineInstr *MI);
bool LowerSubregToReg(MachineInstr *MI);
+ bool LowerCopy(MachineInstr *MI);
void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
const TargetRegisterInfo *TRI);
@@ -321,6 +322,52 @@
return true;
}
+bool LowerSubregsInstructionPass::LowerCopy(MachineInstr *MI) {
+ MachineOperand &DstMO = MI->getOperand(0);
+ MachineOperand &SrcMO = MI->getOperand(1);
+
+ if (SrcMO.getReg() == DstMO.getReg()) {
+ DEBUG(dbgs() << "identity copy: " << *MI);
+ // No need to insert an identity copy instruction, but replace with a KILL
+ // if liveness is changed.
+ if (DstMO.isDead() || SrcMO.isUndef() || MI->getNumOperands() > 2) {
+ // We must make sure the super-register gets killed. Replace the
+ // instruction with KILL.
+ MI->setDesc(TII->get(TargetOpcode::KILL));
+ DEBUG(dbgs() << "replaced by: " << *MI);
+ return true;
+ }
+ // Vanilla identity copy.
+ MI->eraseFromParent();
+ return true;
+ }
+
+ DEBUG(dbgs() << "real copy: " << *MI);
+ // Ask target for a lowered copy instruction.
+ const TargetRegisterClass *DstRC =
+ TRI->getPhysicalRegisterRegClass(DstMO.getReg());
+ const TargetRegisterClass *SrcRC =
+ TRI->getPhysicalRegisterRegClass(SrcMO.getReg());
+ bool Emitted = TII->copyRegToReg(*MI->getParent(), MI,
+ DstMO.getReg(), SrcMO.getReg(),
+ DstRC, SrcRC, MI->getDebugLoc());
+ (void)Emitted;
+ assert(Emitted && "Cannot emit copy");
+
+ if (DstMO.isDead())
+ TransferDeadFlag(MI, DstMO.getReg(), TRI);
+ if (SrcMO.isKill())
+ TransferKillFlag(MI, SrcMO.getReg(), TRI, true);
+ if (MI->getNumOperands() > 2)
+ TransferImplicitDefs(MI);
+ DEBUG({
+ MachineBasicBlock::iterator dMI = MI;
+ dbgs() << "replaced by: " << *(--dMI);
+ });
+ MI->eraseFromParent();
+ return true;
+}
+
/// runOnMachineFunction - Reduce subregister inserts and extracts to register
/// copies.
///
@@ -346,6 +393,8 @@
MadeChange |= LowerInsert(MI);
} else if (MI->isSubregToReg()) {
MadeChange |= LowerSubregToReg(MI);
+ } else if (MI->isCopy()) {
+ MadeChange |= LowerCopy(MI);
}
mi = nmi;
}
Modified: llvm/branches/wendling/eh/lib/CodeGen/MachineCSE.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/MachineCSE.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/MachineCSE.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/MachineCSE.cpp Sun Jul 4 04:07:55 2010
@@ -241,8 +241,8 @@
static bool isCopy(const MachineInstr *MI, const TargetInstrInfo *TII) {
unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
- return TII->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) ||
- MI->isExtractSubreg() || MI->isInsertSubreg() || MI->isSubregToReg();
+ return MI->isCopyLike() ||
+ TII->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx);
}
bool MachineCSE::isCSECandidate(MachineInstr *MI) {
Modified: llvm/branches/wendling/eh/lib/CodeGen/MachineFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/MachineFunction.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/MachineFunction.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/MachineFunction.cpp Sun Jul 4 04:07:55 2010
@@ -438,10 +438,10 @@
/// index with a negative value.
///
int MachineFrameInfo::CreateFixedObject(uint64_t Size, int64_t SPOffset,
- bool Immutable, bool isSS) {
+ bool Immutable) {
assert(Size != 0 && "Cannot allocate zero size fixed stack objects!");
Objects.insert(Objects.begin(), StackObject(Size, 1, SPOffset, Immutable,
- isSS));
+ /*isSS*/false));
return -++NumFixedObjects;
}
Modified: llvm/branches/wendling/eh/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/MachineInstr.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/MachineInstr.cpp Sun Jul 4 04:07:55 2010
@@ -881,14 +881,14 @@
bool MachineInstr::
isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
if (isInlineAsm()) {
- assert(DefOpIdx >= 2);
+ assert(DefOpIdx >= 3);
const MachineOperand &MO = getOperand(DefOpIdx);
if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
return false;
// Determine the actual operand index that corresponds to this index.
unsigned DefNo = 0;
unsigned DefPart = 0;
- for (unsigned i = 1, e = getNumOperands(); i < e; ) {
+ for (unsigned i = 2, e = getNumOperands(); i < e; ) {
const MachineOperand &FMO = getOperand(i);
// After the normal asm operands there may be additional imp-def regs.
if (!FMO.isImm())
@@ -903,7 +903,7 @@
}
++DefNo;
}
- for (unsigned i = 1, e = getNumOperands(); i != e; ++i) {
+ for (unsigned i = 2, e = getNumOperands(); i != e; ++i) {
const MachineOperand &FMO = getOperand(i);
if (!FMO.isImm())
continue;
@@ -946,7 +946,7 @@
// Find the flag operand corresponding to UseOpIdx
unsigned FlagIdx, NumOps=0;
- for (FlagIdx = 1; FlagIdx < UseOpIdx; FlagIdx += NumOps+1) {
+ for (FlagIdx = 2; FlagIdx < UseOpIdx; FlagIdx += NumOps+1) {
const MachineOperand &UFMO = getOperand(FlagIdx);
// After the normal asm operands there may be additional imp-def regs.
if (!UFMO.isImm())
@@ -964,9 +964,9 @@
if (!DefOpIdx)
return true;
- unsigned DefIdx = 1;
- // Remember to adjust the index. First operand is asm string, then there
- // is a flag for each.
+ unsigned DefIdx = 2;
+ // Remember to adjust the index. First operand is asm string, second is
+ // the AlignStack bit, then there is a flag for each.
while (DefNo) {
const MachineOperand &FMO = getOperand(DefIdx);
assert(FMO.isImm());
Modified: llvm/branches/wendling/eh/lib/CodeGen/OptimizePHIs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/OptimizePHIs.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/OptimizePHIs.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/OptimizePHIs.cpp Sun Jul 4 04:07:55 2010
@@ -107,6 +107,11 @@
SrcSubIdx == 0 && DstSubIdx == 0 &&
TargetRegisterInfo::isVirtualRegister(MvSrcReg))
SrcMI = MRI->getVRegDef(MvSrcReg);
+ else if (SrcMI && SrcMI->isCopy() &&
+ !SrcMI->getOperand(0).getSubReg() &&
+ !SrcMI->getOperand(1).getSubReg() &&
+ TargetRegisterInfo::isVirtualRegister(SrcMI->getOperand(1).getReg()))
+ SrcMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg());
if (!SrcMI)
return false;
Modified: llvm/branches/wendling/eh/lib/CodeGen/PreAllocSplitting.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/PreAllocSplitting.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/PreAllocSplitting.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/PreAllocSplitting.cpp Sun Jul 4 04:07:55 2010
@@ -677,10 +677,12 @@
// If the def is a move, set the copy field.
unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
- if (TII->isMoveInstr(*DI, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
+ if (TII->isMoveInstr(*DI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
if (DstReg == LI->reg)
NewVN->setCopy(&*DI);
-
+ } else if (DI->isCopyLike() && DI->getOperand(0).getReg() == LI->reg)
+ NewVN->setCopy(&*DI);
+
NewVNs[&*DI] = NewVN;
}
Modified: llvm/branches/wendling/eh/lib/CodeGen/ProcessImplicitDefs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/ProcessImplicitDefs.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/ProcessImplicitDefs.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/ProcessImplicitDefs.cpp Sun Jul 4 04:07:55 2010
@@ -46,14 +46,15 @@
const TargetInstrInfo *tii_) {
unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
if (tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
- Reg == SrcReg && SrcSubReg == 0 && DstSubReg == 0)
+ Reg == SrcReg && DstSubReg == 0)
return true;
- if (OpIdx == 2 && MI->isSubregToReg())
- return true;
- if (OpIdx == 1 && MI->isExtractSubreg())
- return true;
- return false;
+ switch(OpIdx) {
+ case 1: return (MI->isExtractSubreg() || MI->isCopy()) &&
+ MI->getOperand(0).getSubReg() == 0;
+ case 2: return MI->isSubregToReg() && MI->getOperand(0).getSubReg() == 0;
+ default: return false;
+ }
}
/// processImplicitDefs - Process IMPLICIT_DEF instructions and make sure
@@ -219,8 +220,10 @@
// Turn a copy use into an implicit_def.
unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
- if (tii_->isMoveInstr(*RMI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
- Reg == SrcReg && SrcSubReg == 0 && DstSubReg == 0) {
+ if ((RMI->isCopy() && RMI->getOperand(1).getReg() == Reg &&
+ RMI->getOperand(0).getSubReg() == 0) ||
+ (tii_->isMoveInstr(*RMI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
+ Reg == SrcReg && DstSubReg == 0)) {
RMI->setDesc(tii_->get(TargetOpcode::IMPLICIT_DEF));
bool isKill = false;
Modified: llvm/branches/wendling/eh/lib/CodeGen/PrologEpilogInserter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/PrologEpilogInserter.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/PrologEpilogInserter.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/PrologEpilogInserter.cpp Sun Jul 4 04:07:55 2010
@@ -158,9 +158,9 @@
AdjustsStack = true;
FrameSDOps.push_back(I);
} else if (I->isInlineAsm()) {
- // An InlineAsm might be a call; assume it is to get the stack frame
- // aligned correctly for calls.
- AdjustsStack = true;
+ // Some inline asm's need a stack frame, as indicated by operand 1.
+ if (I->getOperand(1).getImm())
+ AdjustsStack = true;
}
MFI->setAdjustsStack(AdjustsStack);
@@ -260,8 +260,7 @@
if ((unsigned)FrameIdx > MaxCSFrameIndex) MaxCSFrameIndex = FrameIdx;
} else {
// Spill it to the stack where we must.
- FrameIdx = MFI->CreateFixedObject(RC->getSize(), FixedSlot->Offset,
- true, false);
+ FrameIdx = MFI->CreateFixedObject(RC->getSize(), FixedSlot->Offset, true);
}
I->setFrameIdx(FrameIdx);
@@ -642,6 +641,9 @@
for (MachineFunction::iterator BB = Fn.begin(),
E = Fn.end(); BB != E; ++BB) {
+#ifndef NDEBUG
+ int SPAdjCount = 0; // frame setup / destroy count.
+#endif
int SPAdj = 0; // SP offset due to call frame setup / destroy.
if (RS && !FrameIndexVirtualScavenging) RS->enterBasicBlock(BB);
@@ -649,6 +651,10 @@
if (I->getOpcode() == FrameSetupOpcode ||
I->getOpcode() == FrameDestroyOpcode) {
+#ifndef NDEBUG
+ // Track whether we see even pairs of them
+ SPAdjCount += I->getOpcode() == FrameSetupOpcode ? 1 : -1;
+#endif
// Remember how much SP has been adjusted to create the call
// frame.
int Size = I->getOperand(0).getImm();
@@ -715,7 +721,13 @@
if (RS && !FrameIndexVirtualScavenging && MI) RS->forward(MI);
}
- assert(SPAdj == 0 && "Unbalanced call frame setup / destroy pairs?");
+ // If we have evenly matched pairs of frame setup / destroy instructions,
+ // make sure the adjustments come out to zero. If we don't have matched
+ // pairs, we can't be sure the missing bit isn't in another basic block
+ // due to a custom inserter playing tricks, so just asserting SPAdj==0
+ // isn't sufficient. See tMOVCC on Thumb1, for example.
+ assert((SPAdjCount || SPAdj == 0) &&
+ "Unbalanced call frame setup / destroy pairs?");
}
}
Modified: llvm/branches/wendling/eh/lib/CodeGen/RegAllocFast.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/RegAllocFast.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/RegAllocFast.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/RegAllocFast.cpp Sun Jul 4 04:07:55 2010
@@ -519,10 +519,12 @@
// If there is no hint, peek at the only use of this register.
if ((!Hint || !TargetRegisterInfo::isPhysicalRegister(Hint)) &&
MRI->hasOneNonDBGUse(VirtReg)) {
+ const MachineInstr &UseMI = *MRI->use_nodbg_begin(VirtReg);
unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
// It's a copy, use the destination register as a hint.
- if (TII->isMoveInstr(*MRI->use_nodbg_begin(VirtReg),
- SrcReg, DstReg, SrcSubReg, DstSubReg))
+ if (UseMI.isCopyLike())
+ Hint = UseMI.getOperand(0).getReg();
+ else if (TII->isMoveInstr(UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg))
Hint = DstReg;
}
allocVirtReg(MI, *LRI, Hint);
@@ -771,7 +773,12 @@
// If this is a copy, we may be able to coalesce.
unsigned CopySrc, CopyDst, CopySrcSub, CopyDstSub;
- if (!TII->isMoveInstr(*MI, CopySrc, CopyDst, CopySrcSub, CopyDstSub))
+ if (MI->isCopy()) {
+ CopyDst = MI->getOperand(0).getReg();
+ CopySrc = MI->getOperand(1).getReg();
+ CopyDstSub = MI->getOperand(0).getSubReg();
+ CopySrcSub = MI->getOperand(1).getSubReg();
+ } else if (!TII->isMoveInstr(*MI, CopySrc, CopyDst, CopySrcSub, CopyDstSub))
CopySrc = CopyDst = 0;
// Track registers used by instruction.
Modified: llvm/branches/wendling/eh/lib/CodeGen/RegAllocLinearScan.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/RegAllocLinearScan.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/RegAllocLinearScan.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/RegAllocLinearScan.cpp Sun Jul 4 04:07:55 2010
@@ -83,7 +83,8 @@
// pressure, it can caused fewer GPRs to be held in the queue.
static cl::opt<unsigned>
NumRecentlyUsedRegs("linearscan-skip-count",
- cl::desc("Number of registers for linearscan to remember to skip."),
+ cl::desc("Number of registers for linearscan to remember"
+ "to skip."),
cl::init(0),
cl::Hidden);
Modified: llvm/branches/wendling/eh/lib/CodeGen/RegisterCoalescer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/RegisterCoalescer.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/RegisterCoalescer.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/RegisterCoalescer.cpp Sun Jul 4 04:07:55 2010
@@ -44,7 +44,12 @@
bool CoalescerPair::isMoveInstr(const MachineInstr *MI,
unsigned &Src, unsigned &Dst,
unsigned &SrcSub, unsigned &DstSub) const {
- if (MI->isExtractSubreg()) {
+ if (MI->isCopy()) {
+ Dst = MI->getOperand(0).getReg();
+ DstSub = MI->getOperand(0).getSubReg();
+ Src = MI->getOperand(1).getReg();
+ SrcSub = MI->getOperand(1).getSubReg();
+ } else if (MI->isExtractSubreg()) {
Dst = MI->getOperand(0).getReg();
DstSub = MI->getOperand(0).getSubReg();
Src = MI->getOperand(1).getReg();
Modified: llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/InstrEmitter.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Sun Jul 4 04:07:55 2010
@@ -834,6 +834,12 @@
const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
MI->addOperand(MachineOperand::CreateES(AsmStr));
+ // Add the isAlignStack bit.
+ int64_t isAlignStack =
+ cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_IsAlignStack))->
+ getZExtValue();
+ MI->addOperand(MachineOperand::CreateImm(isAlignStack));
+
// Add all of the operand registers to the instruction.
for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
unsigned Flags =
Modified: llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sun Jul 4 04:07:55 2010
@@ -134,7 +134,7 @@
/// whose vector element type is narrower than the original shuffle type.
/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
- SDValue N1, SDValue N2,
+ SDValue N1, SDValue N2,
SmallVectorImpl<int> &Mask) const;
bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
@@ -186,8 +186,8 @@
/// performs the same shuffe in terms of order or result bytes, but on a type
/// whose vector element type is narrower than the original shuffle type.
/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
-SDValue
-SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
+SDValue
+SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
SDValue N1, SDValue N2,
SmallVectorImpl<int> &Mask) const {
unsigned NumMaskElts = VT.getVectorNumElements();
@@ -198,12 +198,12 @@
if (NumEltsGrowth == 1)
return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
-
+
SmallVector<int, 8> NewMask;
for (unsigned i = 0; i != NumMaskElts; ++i) {
int Idx = Mask[i];
for (unsigned j = 0; j != NumEltsGrowth; ++j) {
- if (Idx < 0)
+ if (Idx < 0)
NewMask.push_back(-1);
else
NewMask.push_back(Idx * NumEltsGrowth + j);
@@ -325,7 +325,8 @@
bool OperandsLeadToDest = false;
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
OperandsLeadToDest |= // If an operand leads to Dest, so do we.
- LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo);
+ LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest,
+ NodesLeadingTo);
if (OperandsLeadToDest) {
NodesLeadingTo.insert(N);
@@ -609,7 +610,7 @@
DAG.getConstant(IncrementSize, TLI.getPointerTy()));
Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
- LD->isNonTemporal(), MinAlign(Alignment, IncrementSize));
+ LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
} else {
Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
SVOffset, NewLoadedVT, LD->isVolatile(),
@@ -618,7 +619,7 @@
DAG.getConstant(IncrementSize, TLI.getPointerTy()));
Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
- LD->isNonTemporal(), MinAlign(Alignment, IncrementSize));
+ LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
}
// aggregate the two parts
@@ -778,7 +779,7 @@
"Unexpected illegal type!");
for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
- assert((isTypeLegal(Node->getOperand(i).getValueType()) ||
+ assert((isTypeLegal(Node->getOperand(i).getValueType()) ||
Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
"Unexpected illegal type!");
@@ -1007,11 +1008,11 @@
NodesLeadingTo);
}
- // Now that we legalized all of the inputs (which may have inserted
- // libcalls) create the new CALLSEQ_START node.
+ // Now that we have legalized all of the inputs (which may have inserted
+ // libcalls), create the new CALLSEQ_START node.
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
- // Merge in the last call, to ensure that this call start after the last
+ // Merge in the last call to ensure that this call starts after the last
// call ended.
if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
@@ -1023,8 +1024,8 @@
if (Tmp1 != Node->getOperand(0)) {
SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
Ops[0] = Tmp1;
- Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), &Ops[0], Ops.size()),
- Result.getResNo());
+ Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), &Ops[0],
+ Ops.size()), Result.getResNo());
}
// Remember that the CALLSEQ_START is legalized.
@@ -1114,7 +1115,7 @@
const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
if (LD->getAlignment() < ABIAlignment){
- Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
+ Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
DAG, TLI);
Tmp3 = Result.getOperand(0);
Tmp4 = Result.getOperand(1);
@@ -1230,8 +1231,8 @@
ExtraVT, isVolatile, isNonTemporal,
MinAlign(Alignment, IncrementSize));
- // Build a factor node to remember that this load is independent of the
- // other one.
+ // Build a factor node to remember that this load is independent of
+ // the other one.
Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
Hi.getValue(1));
@@ -1259,8 +1260,8 @@
ExtraVT, isVolatile, isNonTemporal,
MinAlign(Alignment, IncrementSize));
- // Build a factor node to remember that this load is independent of the
- // other one.
+ // Build a factor node to remember that this load is independent of
+ // the other one.
Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
Hi.getValue(1));
@@ -1297,10 +1298,12 @@
// If this is an unaligned load and the target doesn't support it,
// expand it.
if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
- const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
- unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
+ const Type *Ty =
+ LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
+ unsigned ABIAlignment =
+ TLI.getTargetData()->getABITypeAlignment(Ty);
if (LD->getAlignment() < ABIAlignment){
- Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
+ Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
DAG, TLI);
Tmp1 = Result.getOperand(0);
Tmp2 = Result.getOperand(1);
@@ -1326,7 +1329,8 @@
Tmp2 = LegalizeOp(Load.getValue(1));
break;
}
- assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
+ assert(ExtType != ISD::EXTLOAD &&
+ "EXTLOAD should always be supported!");
// Turn the unsupported load into an EXTLOAD followed by an explicit
// zero/sign extend inreg.
Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
@@ -1384,7 +1388,7 @@
// expand it.
if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
- unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
+ unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
if (ST->getAlignment() < ABIAlignment)
Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
DAG, TLI);
@@ -1489,7 +1493,7 @@
// expand it.
if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
- unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
+ unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
if (ST->getAlignment() < ABIAlignment)
Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
DAG, TLI);
@@ -1588,7 +1592,7 @@
Node->getOperand(i), Idx, SV, Offset,
EltVT, false, false, 0));
} else
- Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
+ Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
Node->getOperand(i), Idx, SV, Offset,
false, false, 0));
}
@@ -2106,7 +2110,8 @@
SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
SDValue LoFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, LoOr);
SDValue HiFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, HiOr);
- SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt, TwoP84PlusTwoP52);
+ SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
+ TwoP84PlusTwoP52);
return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
}
@@ -2116,11 +2121,11 @@
if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
EVT SHVT = TLI.getShiftAmountTy();
- SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
+ SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
DAG.getConstant(UINT64_C(0x800), MVT::i64));
- SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
+ SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
@@ -2687,7 +2692,7 @@
case ISD::EXTRACT_VECTOR_ELT:
if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
// This must be an access of the only element. Return it.
- Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
+ Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
Node->getOperand(0));
else
Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
@@ -3139,7 +3144,7 @@
const TargetData &TD = *TLI.getTargetData();
unsigned EntrySize =
DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
-
+
Index = DAG.getNode(ISD::MUL, dl, PTy,
Index, DAG.getConstant(EntrySize, PTy));
SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
Modified: llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Sun Jul 4 04:07:55 2010
@@ -5453,6 +5453,10 @@
const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
+ // Remember the AlignStack bit as operand 3.
+ AsmNodeOperands.push_back(DAG.getTargetConstant(IA->isAlignStack() ? 1 : 0,
+ MVT::i1));
+
// Loop over all of the inputs, copying the operand values into the
// appropriate registers and processing the output regs.
RegsForValue RetValRegs;
@@ -5641,7 +5645,7 @@
}
// Finish up input operands. Set the input chain and add the flag last.
- AsmNodeOperands[0] = Chain;
+ AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
Modified: llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sun Jul 4 04:07:55 2010
@@ -1089,6 +1089,7 @@
Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
+ Ops.push_back(InOps[InlineAsm::Op_IsAlignStack]); // 3
unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
if (InOps[e-1].getValueType() == MVT::Flag)
Modified: llvm/branches/wendling/eh/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SimpleRegisterCoalescing.cpp Sun Jul 4 04:07:55 2010
@@ -450,20 +450,25 @@
UseMO.setIsKill(false);
}
unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
- if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
+ if (UseMI->isCopy()) {
+ if (UseMI->getOperand(0).getReg() != IntB.reg ||
+ UseMI->getOperand(0).getSubReg())
+ continue;
+ } else if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)){
+ if (DstReg != IntB.reg || DstSubIdx)
+ continue;
+ } else
continue;
- if (DstReg == IntB.reg && DstSubIdx == 0) {
- // This copy will become a noop. If it's defining a new val#,
- // remove that val# as well. However this live range is being
- // extended to the end of the existing live range defined by the copy.
- SlotIndex DefIdx = UseIdx.getDefIndex();
- const LiveRange *DLR = IntB.getLiveRangeContaining(DefIdx);
- BHasPHIKill |= DLR->valno->hasPHIKill();
- assert(DLR->valno->def == DefIdx);
- BDeadValNos.push_back(DLR->valno);
- BExtend[DLR->start] = DLR->end;
- JoinedCopies.insert(UseMI);
- }
+ // This copy will become a noop. If it's defining a new val#,
+ // remove that val# as well. However this live range is being
+ // extended to the end of the existing live range defined by the copy.
+ SlotIndex DefIdx = UseIdx.getDefIndex();
+ const LiveRange *DLR = IntB.getLiveRangeContaining(DefIdx);
+ BHasPHIKill |= DLR->valno->hasPHIKill();
+ assert(DLR->valno->def == DefIdx);
+ BDeadValNos.push_back(DLR->valno);
+ BExtend[DLR->start] = DLR->end;
+ JoinedCopies.insert(UseMI);
}
// We need to insert a new liverange: [ALR.start, LastUse). It may be we can
@@ -604,8 +609,9 @@
LastUse->setIsKill();
removeRange(li, LastUseIdx.getDefIndex(), LR->end, li_, tri_);
unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
- if (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
- DstReg == li.reg && DstSubIdx == 0) {
+ if ((LastUseMI->isCopy() && !LastUseMI->getOperand(0).getSubReg()) ||
+ (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
+ DstReg == li.reg && DstSubIdx == 0)) {
// Last use is itself an identity code.
int DeadIdx = LastUseMI->findRegisterDefOperandIdx(li.reg,
false, false, tri_);
@@ -1556,7 +1562,7 @@
// If this isn't a copy nor a extract_subreg, we can't join intervals.
unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
bool isInsUndef = false;
- if (Inst->isExtractSubreg()) {
+ if (Inst->isCopy() || Inst->isExtractSubreg()) {
DstReg = Inst->getOperand(0).getReg();
SrcReg = Inst->getOperand(1).getReg();
} else if (Inst->isInsertSubreg()) {
@@ -1793,8 +1799,7 @@
// Delete all coalesced copies.
bool DoDelete = true;
if (!tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
- assert((MI->isExtractSubreg() || MI->isInsertSubreg() ||
- MI->isSubregToReg()) && "Unrecognized copy instruction");
+ assert(MI->isCopyLike() && "Unrecognized copy instruction");
SrcReg = MI->getOperand(MI->isSubregToReg() ? 2 : 1).getReg();
if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
// Do not delete extract_subreg, insert_subreg of physical
Modified: llvm/branches/wendling/eh/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/TwoAddressInstructionPass.cpp Sun Jul 4 04:07:55 2010
@@ -382,7 +382,7 @@
DstReg = 0;
unsigned SrcSubIdx, DstSubIdx;
if (!TII->isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
- if (MI.isExtractSubreg()) {
+ if (MI.isCopy() || MI.isExtractSubreg()) {
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(1).getReg();
} else if (MI.isInsertSubreg()) {
@@ -926,14 +926,12 @@
UnfoldTID.OpInfo[LoadRegIndex].getRegClass(TRI);
unsigned Reg = MRI->createVirtualRegister(RC);
SmallVector<MachineInstr *, 2> NewMIs;
- bool Success =
- TII->unfoldMemoryOperand(MF, mi, Reg,
- /*UnfoldLoad=*/true, /*UnfoldStore=*/false,
- NewMIs);
- (void)Success;
- assert(Success &&
- "unfoldMemoryOperand failed when getOpcodeAfterMemoryUnfold "
- "succeeded!");
+ if (!TII->unfoldMemoryOperand(MF, mi, Reg,
+ /*UnfoldLoad=*/true,/*UnfoldStore=*/false,
+ NewMIs)) {
+ DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
+ return false;
+ }
assert(NewMIs.size() == 2 &&
"Unfolded a load into multiple instructions!");
// The load was previously folded, so this is the only use.
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARM.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARM.h?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARM.h (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARM.h Sun Jul 4 04:07:55 2010
@@ -101,7 +101,7 @@
FunctionPass *createARMConstantIslandPass();
FunctionPass *createNEONPreAllocPass();
FunctionPass *createNEONMoveFixPass();
-FunctionPass *createThumb2ITBlockPass(bool PreAlloc = false);
+FunctionPass *createThumb2ITBlockPass();
FunctionPass *createThumb2SizeReductionPass();
extern Target TheARMTarget, TheThumbTarget;
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMISelLowering.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMISelLowering.cpp Sun Jul 4 04:07:55 2010
@@ -1996,7 +1996,7 @@
SDValue ArgValue2;
if (NextVA.isMemLoc()) {
MachineFrameInfo *MFI = MF.getFrameInfo();
- int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true, false);
+ int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
// Create load node to retrieve arguments from the stack.
SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
@@ -2052,8 +2052,7 @@
VA = ArgLocs[++i]; // skip ahead to next loc
SDValue ArgValue2;
if (VA.isMemLoc()) {
- int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(),
- true, false);
+ int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
PseudoSourceValue::getFixedStack(FI), 0,
@@ -2120,8 +2119,7 @@
assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
- int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
- true, false);
+ int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), true);
// Create load nodes to retrieve arguments from the stack.
SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
@@ -2152,7 +2150,7 @@
AFI->setVarArgsFrameIndex(
MFI->CreateFixedObject(VARegSaveSize,
ArgOffset + VARegSaveSize - VARegSize,
- true, false));
+ true));
SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
getPointerTy());
@@ -2179,8 +2177,7 @@
&MemOps[0], MemOps.size());
} else
// This will point to the next argument passed via stack.
- AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset,
- true, false));
+ AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true));
}
return Chain;
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMTargetMachine.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMTargetMachine.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMTargetMachine.cpp Sun Jul 4 04:07:55 2010
@@ -16,17 +16,11 @@
#include "ARM.h"
#include "llvm/PassManager.h"
#include "llvm/CodeGen/Passes.h"
-#include "llvm/Support/CommandLine.h"
#include "llvm/Support/FormattedStream.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetRegistry.h"
using namespace llvm;
-static cl::opt<bool>
-EarlyITBlockFormation("thumb2-early-it-blocks", cl::Hidden,
- cl::desc("Form IT blocks early before register allocation"),
- cl::init(false));
-
static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
Triple TheTriple(TT);
switch (TheTriple.getOS()) {
@@ -109,8 +103,6 @@
if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
PM.add(createARMLoadStoreOptimizationPass(true));
- if (Subtarget.isThumb2() && EarlyITBlockFormation)
- PM.add(createThumb2ITBlockPass(true));
return true;
}
Modified: llvm/branches/wendling/eh/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Sun Jul 4 04:07:55 2010
@@ -1044,8 +1044,8 @@
Val = Imm8 << (8 * ByteNum);
} else if ((OpCmode & 0xe) == 0xc) {
// 32-bit vector elements, one byte with low bits set
- unsigned ByteNum = (OpCmode & 0x1);
- Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (1 - ByteNum)));
+ unsigned ByteNum = 1 + (OpCmode & 0x1);
+ Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum)));
} else if (OpCmode == 0x1e) {
// 64-bit vector elements
for (unsigned ByteNum = 0; ByteNum < 8; ++ByteNum) {
Modified: llvm/branches/wendling/eh/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Sun Jul 4 04:07:55 2010
@@ -799,8 +799,8 @@
Val = Imm8 << (8 * ByteNum);
} else if ((OpCmode & 0xe) == 0xc) {
// 32-bit vector elements, one byte with low bits set
- unsigned ByteNum = (OpCmode & 0x1);
- Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (1 - ByteNum)));
+ unsigned ByteNum = 1 + (OpCmode & 0x1);
+ Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum)));
} else if (OpCmode == 0x1e) {
// 64-bit vector elements
for (unsigned ByteNum = 0; ByteNum < 8; ++ByteNum) {
Modified: llvm/branches/wendling/eh/lib/Target/ARM/Thumb2ITBlockPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/Thumb2ITBlockPass.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/Thumb2ITBlockPass.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/Thumb2ITBlockPass.cpp Sun Jul 4 04:07:55 2010
@@ -27,8 +27,7 @@
public:
static char ID;
- Thumb2ITBlockPass(bool PreRA) :
- MachineFunctionPass(&ID), PreRegAlloc(PreRA) {}
+ Thumb2ITBlockPass() : MachineFunctionPass(&ID) {}
const Thumb2InstrInfo *TII;
const TargetRegisterInfo *TRI;
@@ -41,18 +40,6 @@
}
private:
- bool MoveCPSRUseUp(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator E,
- unsigned PredReg,
- ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
- bool &Done);
-
- void FindITBlockRanges(MachineBasicBlock &MBB,
- SmallVector<MachineInstr*,4> &FirstUses,
- SmallVector<MachineInstr*,4> &LastUses);
- bool InsertITBlock(MachineInstr *First, MachineInstr *Last);
- bool InsertITBlocks(MachineBasicBlock &MBB);
bool MoveCopyOutOfITBlock(MachineInstr *MI,
ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
SmallSet<unsigned, 4> &Defs,
@@ -62,189 +49,6 @@
char Thumb2ITBlockPass::ID = 0;
}
-bool
-Thumb2ITBlockPass::MoveCPSRUseUp(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator E,
- unsigned PredReg,
- ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
- bool &Done) {
- SmallSet<unsigned, 4> Defs, Uses;
- MachineBasicBlock::iterator I = MBBI;
- // Look for next CPSR use by scanning up to 4 instructions.
- for (unsigned i = 0; i < 4; ++i) {
- MachineInstr *MI = &*I;
- unsigned MPredReg = 0;
- ARMCC::CondCodes MCC = llvm::getITInstrPredicate(MI, MPredReg);
- if (MCC != ARMCC::AL) {
- if (MPredReg != PredReg || (MCC != CC && MCC != OCC))
- return false;
-
- // Check if the instruction is using any register that's defined
- // below the previous predicated instruction. Also return false if
- // it defines any register which is used in between.
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- const MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg())
- continue;
- unsigned Reg = MO.getReg();
- if (!Reg)
- continue;
- if (MO.isDef()) {
- if (Reg == PredReg || Uses.count(Reg))
- return false;
- } else {
- if (Defs.count(Reg))
- return false;
- }
- }
-
- Done = (I == E);
- MBB.remove(MI);
- MBB.insert(MBBI, MI);
- ++NumMovedInsts;
- return true;
- }
-
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- const MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg())
- continue;
- unsigned Reg = MO.getReg();
- if (!Reg)
- continue;
- if (MO.isDef()) {
- if (Reg == PredReg)
- return false;
- Defs.insert(Reg);
- } else
- Uses.insert(Reg);
- }
-
- if (I == E)
- break;
- ++I;
- }
- return false;
-}
-
-static bool isCPSRLiveout(MachineBasicBlock &MBB) {
- for (MachineBasicBlock::succ_iterator I = MBB.succ_begin(),
- E = MBB.succ_end(); I != E; ++I) {
- if ((*I)->isLiveIn(ARM::CPSR))
- return true;
- }
- return false;
-}
-
-void Thumb2ITBlockPass::FindITBlockRanges(MachineBasicBlock &MBB,
- SmallVector<MachineInstr*,4> &FirstUses,
- SmallVector<MachineInstr*,4> &LastUses) {
- bool SeenUse = false;
- MachineOperand *LastUse = 0;
- MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
- while (MBBI != E) {
- MachineInstr *MI = &*MBBI;
- ++MBBI;
-
- MachineOperand *Def = 0;
- MachineOperand *Use = 0;
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg() || MO.getReg() != ARM::CPSR)
- continue;
- if (MO.isDef()) {
- assert(Def == 0 && "Multiple defs of CPSR?");
- Def = &MO;
- } else {
- assert(Use == 0 && "Multiple uses of CPSR?");
- Use = &MO;
- }
- }
-
- if (Use) {
- LastUse = Use;
- if (!SeenUse) {
- FirstUses.push_back(MI);
- SeenUse = true;
- }
- }
- if (Def) {
- if (LastUse) {
- LastUses.push_back(LastUse->getParent());
- LastUse = 0;
- }
- SeenUse = false;
- }
- }
-
- if (LastUse) {
- // Is the last use a kill?
- if (isCPSRLiveout(MBB))
- LastUses.push_back(0);
- else
- LastUses.push_back(LastUse->getParent());
- }
-}
-
-bool Thumb2ITBlockPass::InsertITBlock(MachineInstr *First, MachineInstr *Last) {
- if (First == Last)
- return false;
-
- bool Modified = false;
- MachineBasicBlock *MBB = First->getParent();
- MachineBasicBlock::iterator MBBI = First;
- MachineBasicBlock::iterator E = Last;
-
- if (First->getDesc().isBranch() || First->getDesc().isReturn())
- return false;
-
- unsigned PredReg = 0;
- ARMCC::CondCodes CC = llvm::getITInstrPredicate(First, PredReg);
- if (CC == ARMCC::AL)
- return Modified;
-
- // Move uses of the CPSR together if possible.
- ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
-
- do {
- ++MBBI;
- if (MBBI->getDesc().isBranch() || MBBI->getDesc().isReturn())
- return Modified;
- MachineInstr *NMI = &*MBBI;
- unsigned NPredReg = 0;
- ARMCC::CondCodes NCC = llvm::getITInstrPredicate(NMI, NPredReg);
- if (NCC != CC && NCC != OCC) {
- if (NCC != ARMCC::AL)
- return Modified;
- assert(MBBI != E);
- bool Done = false;
- if (!MoveCPSRUseUp(*MBB, MBBI, E, PredReg, CC, OCC, Done))
- return Modified;
- Modified = true;
- if (Done)
- MBBI = E;
- }
- } while (MBBI != E);
- return true;
-}
-
-bool Thumb2ITBlockPass::InsertITBlocks(MachineBasicBlock &MBB) {
- SmallVector<MachineInstr*, 4> FirstUses;
- SmallVector<MachineInstr*, 4> LastUses;
- FindITBlockRanges(MBB, FirstUses, LastUses);
- assert(FirstUses.size() == LastUses.size() && "Incorrect range information!");
-
- bool Modified = false;
- for (unsigned i = 0, e = FirstUses.size(); i != e; ++i) {
- if (LastUses[i] == 0)
- // Must be the last pair where CPSR is live out of the block.
- return Modified;
- Modified |= InsertITBlock(FirstUses[i], LastUses[i]);
- }
- return Modified;
-}
-
/// TrackDefUses - Tracking what registers are being defined and used by
/// instructions in the IT block. This also tracks "dependencies", i.e. uses
/// in the IT block that are defined before the IT instruction.
@@ -417,13 +221,10 @@
for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E; ) {
MachineBasicBlock &MBB = *MFI;
++MFI;
- if (PreRegAlloc)
- Modified |= InsertITBlocks(MBB);
- else
- Modified |= InsertITInstructions(MBB);
+ Modified |= InsertITInstructions(MBB);
}
- if (Modified && !PreRegAlloc)
+ if (Modified)
AFI->setHasITBlocks(true);
return Modified;
@@ -431,6 +232,6 @@
/// createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks
/// insertion pass.
-FunctionPass *llvm::createThumb2ITBlockPass(bool PreAlloc) {
- return new Thumb2ITBlockPass(PreAlloc);
+FunctionPass *llvm::createThumb2ITBlockPass() {
+ return new Thumb2ITBlockPass();
}
Modified: llvm/branches/wendling/eh/lib/Target/Alpha/AlphaISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/Alpha/AlphaISelLowering.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/Alpha/AlphaISelLowering.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/Alpha/AlphaISelLowering.cpp Sun Jul 4 04:07:55 2010
@@ -425,7 +425,7 @@
}
} else { //more args
// Create the frame index object for this incoming parameter...
- int FI = MFI->CreateFixedObject(8, 8 * (ArgNo - 6), true, false);
+ int FI = MFI->CreateFixedObject(8, 8 * (ArgNo - 6), true);
// Create the SelectionDAG nodes corresponding to a load
//from this parameter
@@ -444,7 +444,7 @@
if (TargetRegisterInfo::isPhysicalRegister(args_int[i]))
args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass);
SDValue argt = DAG.getCopyFromReg(Chain, dl, args_int[i], MVT::i64);
- int FI = MFI->CreateFixedObject(8, -8 * (6 - i), true, false);
+ int FI = MFI->CreateFixedObject(8, -8 * (6 - i), true);
if (i == 0) FuncInfo->setVarArgsBase(FI);
SDValue SDFI = DAG.getFrameIndex(FI, MVT::i64);
LS.push_back(DAG.getStore(Chain, dl, argt, SDFI, NULL, 0,
@@ -453,7 +453,7 @@
if (TargetRegisterInfo::isPhysicalRegister(args_float[i]))
args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass);
argt = DAG.getCopyFromReg(Chain, dl, args_float[i], MVT::f64);
- FI = MFI->CreateFixedObject(8, - 8 * (12 - i), true, false);
+ FI = MFI->CreateFixedObject(8, - 8 * (12 - i), true);
SDFI = DAG.getFrameIndex(FI, MVT::i64);
LS.push_back(DAG.getStore(Chain, dl, argt, SDFI, NULL, 0,
false, false, 0));
Modified: llvm/branches/wendling/eh/lib/Target/Blackfin/BlackfinISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/Blackfin/BlackfinISelLowering.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/Blackfin/BlackfinISelLowering.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/Blackfin/BlackfinISelLowering.cpp Sun Jul 4 04:07:55 2010
@@ -205,8 +205,7 @@
} else {
assert(VA.isMemLoc() && "CCValAssign must be RegLoc or MemLoc");
unsigned ObjSize = VA.getLocVT().getStoreSize();
- int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(),
- true, false);
+ int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0,
false, false, 0));
Modified: llvm/branches/wendling/eh/lib/Target/CellSPU/SPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/CellSPU/SPUISelLowering.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/CellSPU/SPUISelLowering.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/CellSPU/SPUISelLowering.cpp Sun Jul 4 04:07:55 2010
@@ -1074,7 +1074,7 @@
// We need to load the argument to a virtual register if we determined
// above that we ran out of physical registers of the appropriate type
// or we're forced to do vararg
- int FI = MFI->CreateFixedObject(ObjSize, ArgOffset, true, false);
+ int FI = MFI->CreateFixedObject(ObjSize, ArgOffset, true);
SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, NULL, 0, false, false, 0);
ArgOffset += StackSlotSize;
@@ -1095,8 +1095,7 @@
for (; ArgRegIdx != NumArgRegs; ++ArgRegIdx) {
FuncInfo->setVarArgsFrameIndex(
- MFI->CreateFixedObject(StackSlotSize, ArgOffset,
- true, false));
+ MFI->CreateFixedObject(StackSlotSize, ArgOffset, true));
SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
unsigned VReg = MF.addLiveIn(ArgRegs[ArgRegIdx], &SPU::R32CRegClass);
SDValue ArgVal = DAG.getRegister(VReg, MVT::v16i8);
Modified: llvm/branches/wendling/eh/lib/Target/CppBackend/CPPBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/CppBackend/CPPBackend.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/CppBackend/CPPBackend.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/CppBackend/CPPBackend.cpp Sun Jul 4 04:07:55 2010
@@ -1399,8 +1399,8 @@
if (call->getNumArgOperands() > 1) {
Out << "std::vector<Value*> " << iName << "_params;";
nl(Out);
- for (unsigned i = 1; i < call->getNumOperands(); ++i) {
- Out << iName << "_params.push_back(" << opNames[i] << ");";
+ for (unsigned i = 0; i < call->getNumArgOperands(); ++i) {
+ Out << iName << "_params.push_back(" << opNames[i+1] << ");";
nl(Out);
}
Out << "CallInst* " << iName << " = CallInst::Create("
@@ -1421,6 +1421,7 @@
nl(Out) << iName << "->setTailCall("
<< (call->isTailCall() ? "true" : "false");
Out << ");";
+ nl(Out);
printAttributes(call->getAttributes(), iName);
Out << iName << "->setAttributes(" << iName << "_PAL);";
nl(Out);
Modified: llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeISelLowering.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeISelLowering.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeISelLowering.cpp Sun Jul 4 04:07:55 2010
@@ -588,7 +588,7 @@
// Create the frame index object for this incoming parameter
LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
- LastArgStackLoc, true, false);
+ LastArgStackLoc, true);
SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
@@ -777,7 +777,7 @@
// offset on PEI::calculateFrameObjectOffsets.
// Arguments are always 32-bit.
unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
- int FI = MFI->CreateFixedObject(ArgSize, 0, true, false);
+ int FI = MFI->CreateFixedObject(ArgSize, 0, true);
MBlazeFI->recordLoadArgsFI(FI, -(ArgSize+
(FirstStackArgLoc + VA.getLocMemOffset())));
@@ -808,7 +808,7 @@
unsigned LiveReg = MF.addLiveIn(Reg, RC);
SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, LiveReg, MVT::i32);
- int FI = MFI->CreateFixedObject(4, 0, true, false);
+ int FI = MFI->CreateFixedObject(4, 0, true);
MBlazeFI->recordStoreVarArgsFI(FI, -(4+(StackLoc*4)));
SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff, NULL, 0,
Modified: llvm/branches/wendling/eh/lib/Target/MSIL/MSILWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/MSIL/MSILWriter.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/MSIL/MSILWriter.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/MSIL/MSILWriter.cpp Sun Jul 4 04:07:55 2010
@@ -808,7 +808,7 @@
std::string Name;
switch (Inst->getIntrinsicID()) {
case Intrinsic::vastart:
- Name = getValueName(Inst->getOperand(1));
+ Name = getValueName(Inst->getArgOperand(0));
Name.insert(Name.length()-1,"$valist");
// Obtain the argument handle.
printSimpleInstruction("ldloca",Name.c_str());
@@ -817,20 +817,20 @@
"instance void [mscorlib]System.ArgIterator::.ctor"
"(valuetype [mscorlib]System.RuntimeArgumentHandle)");
// Save as pointer type "void*"
- printValueLoad(Inst->getOperand(1));
+ printValueLoad(Inst->getArgOperand(0));
printSimpleInstruction("ldloca",Name.c_str());
printIndirectSave(PointerType::getUnqual(
IntegerType::get(Inst->getContext(), 8)));
break;
case Intrinsic::vaend:
// Close argument list handle.
- printIndirectLoad(Inst->getOperand(1));
+ printIndirectLoad(Inst->getArgOperand(0));
printSimpleInstruction("call","instance void [mscorlib]System.ArgIterator::End()");
break;
case Intrinsic::vacopy:
// Copy "ArgIterator" valuetype.
- printIndirectLoad(Inst->getOperand(1));
- printIndirectLoad(Inst->getOperand(2));
+ printIndirectLoad(Inst->getArgOperand(0));
+ printIndirectLoad(Inst->getArgOperand(1));
printSimpleInstruction("cpobj","[mscorlib]System.ArgIterator");
break;
default:
@@ -1281,7 +1281,7 @@
case Intrinsic::vaend:
case Intrinsic::vacopy:
isVaList = true;
- VaList = Inst->getOperand(1);
+ VaList = Inst->getArgOperand(0);
break;
default:
isVaList = false;
Modified: llvm/branches/wendling/eh/lib/Target/MSP430/MSP430ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/MSP430/MSP430ISelLowering.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/MSP430/MSP430ISelLowering.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/MSP430/MSP430ISelLowering.cpp Sun Jul 4 04:07:55 2010
@@ -369,7 +369,7 @@
<< "\n";
}
// Create the frame index object for this incoming parameter...
- int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true, false);
+ int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
// Create the SelectionDAG nodes corresponding to a load
//from this parameter
@@ -888,7 +888,7 @@
// Set up a frame object for the return address.
uint64_t SlotSize = TD->getPointerSize();
ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
- true, false);
+ true);
FuncInfo->setRAIndex(ReturnAddrIndex);
}
Modified: llvm/branches/wendling/eh/lib/Target/MSP430/MSP430RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/MSP430/MSP430RegisterInfo.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/MSP430/MSP430RegisterInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/MSP430/MSP430RegisterInfo.cpp Sun Jul 4 04:07:55 2010
@@ -229,7 +229,7 @@
// Create a frame entry for the FPW register that must be saved.
if (hasFP(MF)) {
int ATTRIBUTE_UNUSED FrameIdx =
- MF.getFrameInfo()->CreateFixedObject(2, -4, true, false);
+ MF.getFrameInfo()->CreateFixedObject(2, -4, true);
assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
"Slot for FPW register must be last in order to be found!");
}
Modified: llvm/branches/wendling/eh/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/Mips/MipsISelLowering.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/Mips/MipsISelLowering.cpp Sun Jul 4 04:07:55 2010
@@ -787,7 +787,7 @@
// the stack (even if less than 4 are used as arguments)
if (Subtarget->isABI_O32()) {
int VTsize = EVT(MVT::i32).getSizeInBits()/8;
- MFI->CreateFixedObject(VTsize, (VTsize*3), true, false);
+ MFI->CreateFixedObject(VTsize, (VTsize*3), true);
CCInfo.AnalyzeCallOperands(Outs,
isVarArg ? CC_MipsO32_VarArgs : CC_MipsO32);
} else
@@ -857,7 +857,7 @@
// if O32 ABI is used. For EABI the first address is zero.
LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
- LastArgStackLoc, true, false);
+ LastArgStackLoc, true);
SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
@@ -929,7 +929,7 @@
// Create the frame index only once. SPOffset here can be anything
// (this will be fixed on processFunctionBeforeFrameFinalized)
if (MipsFI->getGPStackOffset() == -1) {
- FI = MFI->CreateFixedObject(4, 0, true, false);
+ FI = MFI->CreateFixedObject(4, 0, true);
MipsFI->setGPFI(FI);
}
MipsFI->setGPStackOffset(LastArgStackLoc);
@@ -1098,7 +1098,7 @@
// offset on PEI::calculateFrameObjectOffsets.
// Arguments are always 32-bit.
unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
- int FI = MFI->CreateFixedObject(ArgSize, 0, true, false);
+ int FI = MFI->CreateFixedObject(ArgSize, 0, true);
MipsFI->recordLoadArgsFI(FI, -(ArgSize+
(FirstStackArgLoc + VA.getLocMemOffset())));
@@ -1137,7 +1137,7 @@
unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegEnd, RC);
SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, MVT::i32);
- int FI = MFI->CreateFixedObject(4, 0, true, false);
+ int FI = MFI->CreateFixedObject(4, 0, true);
MipsFI->recordStoreVarArgsFI(FI, -(4+(StackLoc*4)));
SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff, NULL, 0,
Modified: llvm/branches/wendling/eh/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/PowerPC/PPCISelLowering.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/PowerPC/PPCISelLowering.cpp Sun Jul 4 04:07:55 2010
@@ -1631,7 +1631,7 @@
unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
- isImmutable, false);
+ isImmutable);
// Create load nodes to retrieve arguments from the stack.
SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
@@ -1700,8 +1700,7 @@
FuncInfo->setVarArgsStackOffset(
MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
- CCInfo.getNextStackOffset(),
- true, false));
+ CCInfo.getNextStackOffset(), true));
FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
@@ -1911,7 +1910,7 @@
CurArgOffset = CurArgOffset + (4 - ObjSize);
}
// The value of the object is its address.
- int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true, false);
+ int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
InVals.push_back(FIN);
if (ObjSize==1 || ObjSize==2) {
@@ -1936,7 +1935,7 @@
// the object.
if (GPR_idx != Num_GPR_Regs) {
unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
- int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true, false);
+ int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0,
@@ -2062,7 +2061,7 @@
if (needsLoad) {
int FI = MFI->CreateFixedObject(ObjSize,
CurArgOffset + (ArgSize - ObjSize),
- isImmutable, false);
+ isImmutable);
SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, NULL, 0,
false, false, 0);
@@ -2097,7 +2096,7 @@
FuncInfo->setVarArgsFrameIndex(
MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
- Depth, true, false));
+ Depth, true));
SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
// If this function is vararg, store any remaining integer argument regs
@@ -2314,8 +2313,7 @@
int NewRetAddrLoc = SPDiff + PPCFrameInfo::getReturnSaveOffset(isPPC64,
isDarwinABI);
int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
- NewRetAddrLoc,
- true, false);
+ NewRetAddrLoc, true);
EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
@@ -2328,7 +2326,7 @@
int NewFPLoc =
SPDiff + PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI);
int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
- true, false);
+ true);
SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
PseudoSourceValue::getFixedStack(NewFPIdx), 0,
@@ -2346,7 +2344,7 @@
SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
int Offset = ArgOffset + SPDiff;
uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
- int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true,false);
+ int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
SDValue FIN = DAG.getFrameIndex(FI, VT);
TailCallArgumentInfo Info;
@@ -3375,8 +3373,7 @@
// Find out what the fix offset of the frame pointer save area.
int LROffset = PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI);
// Allocate the frame index for frame pointer save area.
- RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset,
- true, false);
+ RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
// Save the result.
FI->setReturnAddrSaveIndex(RASI);
}
@@ -3402,8 +3399,7 @@
isDarwinABI);
// Allocate the frame index for frame pointer save area.
- FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset,
- true, false);
+ FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
// Save the result.
FI->setFramePointerSaveIndex(FPSI);
}
Modified: llvm/branches/wendling/eh/lib/Target/PowerPC/PPCRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/PowerPC/PPCRegisterInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/PowerPC/PPCRegisterInfo.cpp Sun Jul 4 04:07:55 2010
@@ -926,8 +926,7 @@
int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64,
isDarwinABI);
// Allocate the frame index for frame pointer save area.
- FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset,
- true, false);
+ FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
// Save the result.
FI->setFramePointerSaveIndex(FPSI);
}
@@ -935,8 +934,7 @@
// Reserve stack space to move the linkage area to in case of a tail call.
int TCSPDelta = 0;
if (GuaranteedTailCallOpt && (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
- MF.getFrameInfo()->CreateFixedObject(-1 * TCSPDelta, TCSPDelta,
- true, false);
+ MF.getFrameInfo()->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
}
// Reserve a slot closest to SP or frame pointer if we have a dynalloc or
Modified: llvm/branches/wendling/eh/lib/Target/README.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/README.txt?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/README.txt (original)
+++ llvm/branches/wendling/eh/lib/Target/README.txt Sun Jul 4 04:07:55 2010
@@ -1888,3 +1888,47 @@
(That said, we are doing a lot better than gcc on this testcase. :) )
//===---------------------------------------------------------------------===//
+
+Switch lowering generates less than ideal code for the following switch:
+define void @a(i32 %x) nounwind {
+entry:
+ switch i32 %x, label %if.end [
+ i32 0, label %if.then
+ i32 1, label %if.then
+ i32 2, label %if.then
+ i32 3, label %if.then
+ i32 5, label %if.then
+ ]
+if.then:
+ tail call void @foo() nounwind
+ ret void
+if.end:
+ ret void
+}
+declare void @foo()
+
+Generated code on x86-64 (other platforms give similar results):
+a:
+ cmpl $5, %edi
+ ja .LBB0_2
+ movl %edi, %eax
+ movl $47, %ecx
+ btq %rax, %rcx
+ jb .LBB0_3
+.LBB0_2:
+ ret
+.LBB0_3:
+ jmp foo # TAILCALL
+
+The movl+movl+btq+jb could be simplified to a cmpl+jne.
+
+Or, if we wanted to be really clever, we could simplify the whole thing to
+something like the following, which eliminates a branch:
+ xorl $1, %edi
+ cmpl $4, %edi
+ ja .LBB0_2
+ ret
+.LBB0_2:
+ jmp foo # TAILCALL
+
+//===---------------------------------------------------------------------===//
Modified: llvm/branches/wendling/eh/lib/Target/Sparc/SparcISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/Sparc/SparcISelLowering.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/Sparc/SparcISelLowering.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/Sparc/SparcISelLowering.cpp Sun Jul 4 04:07:55 2010
@@ -133,7 +133,7 @@
InVals.push_back(Arg);
} else {
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
- true, false);
+ true);
SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
SDValue Load;
if (ObjectVT == MVT::i32) {
@@ -169,7 +169,7 @@
InVals.push_back(Arg);
} else {
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
- true, false);
+ true);
SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
SDValue Load = DAG.getLoad(MVT::f32, dl, Chain, FIPtr, NULL, 0,
false, false, 0);
@@ -192,7 +192,7 @@
HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32);
} else {
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
- true, false);
+ true);
SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, NULL, 0,
false, false, 0);
@@ -205,7 +205,7 @@
LoVal = DAG.getCopyFromReg(Chain, dl, VRegLo, MVT::i32);
} else {
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4,
- true, false);
+ true);
SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, NULL, 0,
false, false, 0);
@@ -239,7 +239,7 @@
SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
- true, false);
+ true);
SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr, NULL, 0,
Modified: llvm/branches/wendling/eh/lib/Target/SystemZ/SystemZISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/SystemZ/SystemZISelLowering.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/SystemZ/SystemZISelLowering.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/SystemZ/SystemZISelLowering.cpp Sun Jul 4 04:07:55 2010
@@ -334,7 +334,7 @@
// Create the nodes corresponding to a load from this parameter slot.
// Create the frame index object for this incoming parameter...
int FI = MFI->CreateFixedObject(LocVT.getSizeInBits()/8,
- VA.getLocMemOffset(), true, false);
+ VA.getLocMemOffset(), true);
// Create the SelectionDAG nodes corresponding to a load
// from this parameter
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86ISelLowering.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86ISelLowering.cpp Sun Jul 4 04:07:55 2010
@@ -1485,11 +1485,11 @@
// could be overwritten by lowering of arguments in case of a tail call.
if (Flags.isByVal()) {
int FI = MFI->CreateFixedObject(Flags.getByValSize(),
- VA.getLocMemOffset(), isImmutable, false);
+ VA.getLocMemOffset(), isImmutable);
return DAG.getFrameIndex(FI, getPointerTy());
} else {
int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
- VA.getLocMemOffset(), isImmutable, false);
+ VA.getLocMemOffset(), isImmutable);
SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
return DAG.getLoad(ValVT, dl, Chain, FIN,
PseudoSourceValue::getFixedStack(FI), 0,
@@ -1617,8 +1617,7 @@
if (isVarArg) {
if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
CallConv != CallingConv::X86_ThisCall)) {
- FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,
- true, false));
+ FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
}
if (Is64Bit) {
unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
@@ -1790,7 +1789,7 @@
// Calculate the new stack slot for the return address.
int SlotSize = Is64Bit ? 8 : 4;
int NewReturnAddrFI =
- MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false, false);
+ MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
@@ -2020,7 +2019,7 @@
// Create frame index.
int32_t Offset = VA.getLocMemOffset()+FPDiff;
uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
- FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true, false);
+ FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
FIN = DAG.getFrameIndex(FI, getPointerTy());
if (Flags.isByVal()) {
@@ -2487,7 +2486,7 @@
// Set up a frame object for the return address.
uint64_t SlotSize = TD->getPointerSize();
ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
- false, false);
+ false);
FuncInfo->setRAIndex(ReturnAddrIndex);
}
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86InstrInfo.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86InstrInfo.cpp Sun Jul 4 04:07:55 2010
@@ -2159,7 +2159,7 @@
MachineInstr::mmo_iterator MMOBegin,
MachineInstr::mmo_iterator MMOEnd,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
- bool isAligned = (*MMOBegin)->getAlignment() >= 16;
+ bool isAligned = *MMOBegin && (*MMOBegin)->getAlignment() >= 16;
unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
DebugLoc DL;
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
@@ -2189,7 +2189,7 @@
MachineInstr::mmo_iterator MMOBegin,
MachineInstr::mmo_iterator MMOEnd,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
- bool isAligned = (*MMOBegin)->getAlignment() >= 16;
+ bool isAligned = *MMOBegin && (*MMOBegin)->getAlignment() >= 16;
unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
DebugLoc DL;
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
@@ -2693,6 +2693,13 @@
const TargetInstrDesc &TID = get(Opc);
const TargetOperandInfo &TOI = TID.OpInfo[Index];
const TargetRegisterClass *RC = TOI.getRegClass(&RI);
+ if (!MI->hasOneMemOperand() &&
+ RC == &X86::VR128RegClass &&
+ !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
+ // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
+ // conservatively assume the address is unaligned. That's bad for
+ // performance.
+ return false;
SmallVector<MachineOperand, X86AddrNumOperands> AddrOps;
SmallVector<MachineOperand,2> BeforeOps;
SmallVector<MachineOperand,2> AfterOps;
@@ -2834,7 +2841,12 @@
MachineInstr::mmo_iterator> MMOs =
MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
cast<MachineSDNode>(N)->memoperands_end());
- bool isAligned = (*MMOs.first)->getAlignment() >= 16;
+ if (!(*MMOs.first) &&
+ RC == &X86::VR128RegClass &&
+ !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
+ // Do not introduce a slow unaligned load.
+ return false;
+ bool isAligned = (*MMOs.first) && (*MMOs.first)->getAlignment() >= 16;
Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
VT, MVT::Other, &AddrOps[0], AddrOps.size());
NewNodes.push_back(Load);
@@ -2871,7 +2883,12 @@
MachineInstr::mmo_iterator> MMOs =
MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
cast<MachineSDNode>(N)->memoperands_end());
- bool isAligned = (*MMOs.first)->getAlignment() >= 16;
+ if (!(*MMOs.first) &&
+ RC == &X86::VR128RegClass &&
+ !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
+ // Do not introduce a slow unaligned store.
+ return false;
+ bool isAligned = (*MMOs.first) && (*MMOs.first)->getAlignment() >= 16;
SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
isAligned, TM),
dl, MVT::Other,
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86InstrSSE.td?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86InstrSSE.td Sun Jul 4 04:07:55 2010
@@ -3380,6 +3380,18 @@
(bitconvert (mem_frag128 addr:$src))))]>, OpSize;
}
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE3] in {
+ defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv8i8, memopv16i8,
+ int_x86_ssse3_pabs_b,
+ int_x86_ssse3_pabs_b_128>, VEX;
+ defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv4i16, memopv8i16,
+ int_x86_ssse3_pabs_w,
+ int_x86_ssse3_pabs_w_128>, VEX;
+ defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv2i32, memopv4i32,
+ int_x86_ssse3_pabs_d,
+ int_x86_ssse3_pabs_d_128>, VEX;
+}
+
defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv8i8, memopv16i8,
int_x86_ssse3_pabs_b,
int_x86_ssse3_pabs_b_128>;
@@ -3433,6 +3445,47 @@
(bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
}
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE3] in {
+let isCommutable = 0 in {
+ defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv4i16, memopv8i16,
+ int_x86_ssse3_phadd_w,
+ int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
+ defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv2i32, memopv4i32,
+ int_x86_ssse3_phadd_d,
+ int_x86_ssse3_phadd_d_128, 0>, VEX_4V;
+ defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv4i16, memopv8i16,
+ int_x86_ssse3_phadd_sw,
+ int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
+ defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv4i16, memopv8i16,
+ int_x86_ssse3_phsub_w,
+ int_x86_ssse3_phsub_w_128, 0>, VEX_4V;
+ defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv2i32, memopv4i32,
+ int_x86_ssse3_phsub_d,
+ int_x86_ssse3_phsub_d_128, 0>, VEX_4V;
+ defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv4i16, memopv8i16,
+ int_x86_ssse3_phsub_sw,
+ int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
+ defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv8i8, memopv16i8,
+ int_x86_ssse3_pmadd_ub_sw,
+ int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
+ defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv8i8, memopv16i8,
+ int_x86_ssse3_pshuf_b,
+ int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
+ defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv8i8, memopv16i8,
+ int_x86_ssse3_psign_b,
+ int_x86_ssse3_psign_b_128, 0>, VEX_4V;
+ defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv4i16, memopv8i16,
+ int_x86_ssse3_psign_w,
+ int_x86_ssse3_psign_w_128, 0>, VEX_4V;
+ defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv2i32, memopv4i32,
+ int_x86_ssse3_psign_d,
+ int_x86_ssse3_psign_d_128, 0>, VEX_4V;
+}
+defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv4i16, memopv8i16,
+ int_x86_ssse3_pmul_hr_sw,
+ int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
+}
+
// None of these have i8 immediate fields.
let ImmT = NoImm, Constraints = "$src1 = $dst" in {
let isCommutable = 0 in {
@@ -3484,26 +3537,43 @@
// SSSE3 - Packed Align Instruction Patterns
//===---------------------------------------------------------------------===//
-let Constraints = "$src1 = $dst" in {
- def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
- (ins VR64:$src1, VR64:$src2, i8imm:$src3),
- "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
- []>;
- def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
- (ins VR64:$src1, i64mem:$src2, i8imm:$src3),
- "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
- []>;
-
- def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
- (ins VR128:$src1, VR128:$src2, i8imm:$src3),
- "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
- []>, OpSize;
- def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
- (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
- "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
- []>, OpSize;
+multiclass sse3_palign<string asm, bit Is2Addr = 1> {
+ def R64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
+ (ins VR64:$src1, VR64:$src2, i8imm:$src3),
+ !if(Is2Addr,
+ !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+ !strconcat(asm,
+ "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
+ []>;
+ def R64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
+ (ins VR64:$src1, i64mem:$src2, i8imm:$src3),
+ !if(Is2Addr,
+ !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+ !strconcat(asm,
+ "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
+ []>;
+
+ def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
+ (ins VR128:$src1, VR128:$src2, i8imm:$src3),
+ !if(Is2Addr,
+ !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+ !strconcat(asm,
+ "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
+ []>, OpSize;
+ def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
+ (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
+ !if(Is2Addr,
+ !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+ !strconcat(asm,
+ "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
+ []>, OpSize;
}
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE3] in
+ defm VPALIGN : sse3_palign<"vpalignr", 0>, VEX_4V;
+let Constraints = "$src1 = $dst" in
+ defm PALIGN : sse3_palign<"palignr">;
+
let AddedComplexity = 5 in {
def : Pat<(v1i64 (palign:$src3 VR64:$src1, VR64:$src2)),
@@ -3834,7 +3904,7 @@
(MOVUPSmr addr:$dst, VR128:$src)>;
//===----------------------------------------------------------------------===//
-// SSE4.1 Instructions
+// SSE4.1 - Misc Instructions
//===----------------------------------------------------------------------===//
multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd,
@@ -3878,56 +3948,137 @@
OpSize;
}
-let Constraints = "$src1 = $dst" in {
+multiclass sse41_fp_unop_rm_avx<bits<8> opcps, bits<8> opcpd,
+ string OpcodeStr> {
+ // Intrinsic operation, reg.
+ // Vector intrinsic operation, reg
+ def PSr : SS4AIi8<opcps, MRMSrcReg,
+ (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
+ !strconcat(OpcodeStr,
+ "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+ []>, OpSize;
+
+ // Vector intrinsic operation, mem
+ def PSm : Ii8<opcps, MRMSrcMem,
+ (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
+ !strconcat(OpcodeStr,
+ "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+ []>, TA, OpSize, Requires<[HasSSE41]>;
+
+ // Vector intrinsic operation, reg
+ def PDr : SS4AIi8<opcpd, MRMSrcReg,
+ (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
+ !strconcat(OpcodeStr,
+ "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+ []>, OpSize;
+
+ // Vector intrinsic operation, mem
+ def PDm : SS4AIi8<opcpd, MRMSrcMem,
+ (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
+ !strconcat(OpcodeStr,
+ "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+ []>, OpSize;
+}
+
multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
string OpcodeStr,
Intrinsic F32Int,
- Intrinsic F64Int> {
+ Intrinsic F64Int, bit Is2Addr = 1> {
// Intrinsic operation, reg.
def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
- (outs VR128:$dst),
- (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
- !strconcat(OpcodeStr,
- "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
- [(set VR128:$dst,
- (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
- OpSize;
+ (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
+ !if(Is2Addr,
+ !strconcat(OpcodeStr,
+ "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+ !strconcat(OpcodeStr,
+ "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
+ [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
+ OpSize;
// Intrinsic operation, mem.
def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
- (outs VR128:$dst),
- (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
- !strconcat(OpcodeStr,
- "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
- [(set VR128:$dst,
- (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
- OpSize;
+ (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
+ !if(Is2Addr,
+ !strconcat(OpcodeStr,
+ "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+ !strconcat(OpcodeStr,
+ "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
+ [(set VR128:$dst,
+ (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
+ OpSize;
// Intrinsic operation, reg.
def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
- (outs VR128:$dst),
- (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
- !strconcat(OpcodeStr,
- "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
- [(set VR128:$dst,
- (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
- OpSize;
+ (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
+ !if(Is2Addr,
+ !strconcat(OpcodeStr,
+ "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+ !strconcat(OpcodeStr,
+ "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
+ [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
+ OpSize;
// Intrinsic operation, mem.
def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
- (outs VR128:$dst),
- (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
- !strconcat(OpcodeStr,
- "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
- [(set VR128:$dst,
- (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
- OpSize;
+ (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
+ !if(Is2Addr,
+ !strconcat(OpcodeStr,
+ "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+ !strconcat(OpcodeStr,
+ "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
+ [(set VR128:$dst,
+ (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
+ OpSize;
}
+
+multiclass sse41_fp_binop_rm_avx<bits<8> opcss, bits<8> opcsd,
+ string OpcodeStr> {
+ // Intrinsic operation, reg.
+ def SSr : SS4AIi8<opcss, MRMSrcReg,
+ (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
+ !strconcat(OpcodeStr,
+ "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
+ []>, OpSize;
+
+ // Intrinsic operation, mem.
+ def SSm : SS4AIi8<opcss, MRMSrcMem,
+ (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
+ !strconcat(OpcodeStr,
+ "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
+ []>, OpSize;
+
+ // Intrinsic operation, reg.
+ def SDr : SS4AIi8<opcsd, MRMSrcReg,
+ (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
+ !strconcat(OpcodeStr,
+ "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
+ []>, OpSize;
+
+ // Intrinsic operation, mem.
+ def SDm : SS4AIi8<opcsd, MRMSrcMem,
+ (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
+ !strconcat(OpcodeStr,
+ "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
+ []>, OpSize;
}
// FP round - roundss, roundps, roundsd, roundpd
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in {
+ // Intrinsic form
+ defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround",
+ int_x86_sse41_round_ps, int_x86_sse41_round_pd>,
+ VEX;
+ defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
+ int_x86_sse41_round_ss, int_x86_sse41_round_sd,
+ 0>, VEX_4V;
+ // Instructions for the assembler
+ defm VROUND : sse41_fp_unop_rm_avx<0x08, 0x09, "vround">, VEX;
+ defm VROUND : sse41_fp_binop_rm_avx<0x0A, 0x0B, "vround">, VEX_4V;
+}
+
defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round",
int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
+let Constraints = "$src1 = $dst" in
defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
@@ -3946,149 +4097,158 @@
(bitconvert (memopv8i16 addr:$src))))]>, OpSize;
}
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in
+defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
+ int_x86_sse41_phminposuw>, VEX;
defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
int_x86_sse41_phminposuw>;
/// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
-let Constraints = "$src1 = $dst" in {
- multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
- Intrinsic IntId128, bit Commutable = 0> {
- def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
- (ins VR128:$src1, VR128:$src2),
- !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
- [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
- OpSize {
- let isCommutable = Commutable;
- }
- def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
- (ins VR128:$src1, i128mem:$src2),
- !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
- [(set VR128:$dst,
- (IntId128 VR128:$src1,
- (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
- }
+multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
+ Intrinsic IntId128, bit Is2Addr = 1> {
+ let isCommutable = 1 in
+ def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
+ (ins VR128:$src1, VR128:$src2),
+ !if(Is2Addr,
+ !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
+ !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
+ [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
+ def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
+ (ins VR128:$src1, i128mem:$src2),
+ !if(Is2Addr,
+ !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
+ !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
+ [(set VR128:$dst,
+ (IntId128 VR128:$src1,
+ (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
}
-defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
- int_x86_sse41_pcmpeqq, 1>;
-defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
- int_x86_sse41_packusdw, 0>;
-defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
- int_x86_sse41_pminsb, 1>;
-defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
- int_x86_sse41_pminsd, 1>;
-defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
- int_x86_sse41_pminud, 1>;
-defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
- int_x86_sse41_pminuw, 1>;
-defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
- int_x86_sse41_pmaxsb, 1>;
-defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
- int_x86_sse41_pmaxsd, 1>;
-defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
- int_x86_sse41_pmaxud, 1>;
-defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
- int_x86_sse41_pmaxuw, 1>;
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in {
+ let isCommutable = 0 in
+ defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
+ 0>, VEX_4V;
+ defm VPCMPEQQ : SS41I_binop_rm_int<0x29, "vpcmpeqq", int_x86_sse41_pcmpeqq,
+ 0>, VEX_4V;
+ defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
+ 0>, VEX_4V;
+ defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
+ 0>, VEX_4V;
+ defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
+ 0>, VEX_4V;
+ defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
+ 0>, VEX_4V;
+ defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
+ 0>, VEX_4V;
+ defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
+ 0>, VEX_4V;
+ defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
+ 0>, VEX_4V;
+ defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
+ 0>, VEX_4V;
+ defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
+ 0>, VEX_4V;
+}
-defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq, 1>;
+let Constraints = "$src1 = $dst" in {
+ let isCommutable = 0 in
+ defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
+ defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq", int_x86_sse41_pcmpeqq>;
+ defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
+ defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
+ defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
+ defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
+ defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
+ defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
+ defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
+ defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
+ defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
+}
def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
(PCMPEQQrr VR128:$src1, VR128:$src2)>;
def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
(PCMPEQQrm VR128:$src1, addr:$src2)>;
-/// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
-let Constraints = "$src1 = $dst" in {
- multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, ValueType OpVT,
- SDNode OpNode, Intrinsic IntId128,
- bit Commutable = 0> {
- def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
- (ins VR128:$src1, VR128:$src2),
- !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
- [(set VR128:$dst, (OpNode (OpVT VR128:$src1),
- VR128:$src2))]>, OpSize {
- let isCommutable = Commutable;
- }
- def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
- (ins VR128:$src1, VR128:$src2),
- !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
- [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
- OpSize {
- let isCommutable = Commutable;
- }
- def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
- (ins VR128:$src1, i128mem:$src2),
- !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
- [(set VR128:$dst,
- (OpVT (OpNode VR128:$src1, (memop addr:$src2))))]>, OpSize;
- def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
- (ins VR128:$src1, i128mem:$src2),
- !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
- [(set VR128:$dst,
- (IntId128 VR128:$src1, (memop addr:$src2)))]>,
- OpSize;
- }
-}
-
/// SS48I_binop_rm - Simple SSE41 binary operator.
-let Constraints = "$src1 = $dst" in {
multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
- ValueType OpVT, bit Commutable = 0> {
+ ValueType OpVT, bit Is2Addr = 1> {
+ let isCommutable = 1 in
def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
- (ins VR128:$src1, VR128:$src2),
- !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
- [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
- OpSize {
- let isCommutable = Commutable;
- }
+ (ins VR128:$src1, VR128:$src2),
+ !if(Is2Addr,
+ !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
+ !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
+ [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
+ OpSize;
def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
- (ins VR128:$src1, i128mem:$src2),
- !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
- [(set VR128:$dst, (OpNode VR128:$src1,
+ (ins VR128:$src1, i128mem:$src2),
+ !if(Is2Addr,
+ !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
+ !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
+ [(set VR128:$dst, (OpNode VR128:$src1,
(bc_v4i32 (memopv2i64 addr:$src2))))]>,
- OpSize;
-}
+ OpSize;
}
-defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, 1>;
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in
+ defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, 0>, VEX_4V;
+let Constraints = "$src1 = $dst" in
+ defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32>;
/// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
-let Constraints = "$src1 = $dst" in {
- multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
- Intrinsic IntId128, bit Commutable = 0> {
- def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
- (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
- !strconcat(OpcodeStr,
- "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
- [(set VR128:$dst,
- (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
- OpSize {
- let isCommutable = Commutable;
- }
- def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
- (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
- !strconcat(OpcodeStr,
- "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
- [(set VR128:$dst,
- (IntId128 VR128:$src1,
- (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
- OpSize;
+multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
+ Intrinsic IntId128, bit Is2Addr = 1> {
+ let isCommutable = 1 in
+ def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
+ (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
+ !if(Is2Addr,
+ !strconcat(OpcodeStr,
+ "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+ !strconcat(OpcodeStr,
+ "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
+ [(set VR128:$dst,
+ (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
+ OpSize;
+ def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
+ (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
+ !if(Is2Addr,
+ !strconcat(OpcodeStr,
+ "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+ !strconcat(OpcodeStr,
+ "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
+ [(set VR128:$dst,
+ (IntId128 VR128:$src1,
+ (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
+ OpSize;
+}
+
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in {
+ let isCommutable = 0 in {
+ defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
+ 0>, VEX_4V;
+ defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
+ 0>, VEX_4V;
+ defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
+ 0>, VEX_4V;
+ defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
+ 0>, VEX_4V;
}
+ defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
+ 0>, VEX_4V;
+ defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
+ 0>, VEX_4V;
}
-defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps",
- int_x86_sse41_blendps, 0>;
-defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd",
- int_x86_sse41_blendpd, 0>;
-defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw",
- int_x86_sse41_pblendw, 0>;
-defm DPPS : SS41I_binop_rmi_int<0x40, "dpps",
- int_x86_sse41_dpps, 1>;
-defm DPPD : SS41I_binop_rmi_int<0x41, "dppd",
- int_x86_sse41_dppd, 1>;
-defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw",
- int_x86_sse41_mpsadbw, 0>;
-
+let Constraints = "$src1 = $dst" in {
+ let isCommutable = 0 in {
+ defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps>;
+ defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd>;
+ defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw>;
+ defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw>;
+ }
+ defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps>;
+ defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd>;
+}
/// SS41I_ternary_int - SSE 4.1 ternary operator
let Uses = [XMM0], Constraints = "$src1 = $dst" in {
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86MCCodeEmitter.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86MCCodeEmitter.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86MCCodeEmitter.cpp Sun Jul 4 04:07:55 2010
@@ -543,7 +543,7 @@
//
unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
- if (VEX_B && VEX_X && !VEX_W) { // 2 byte VEX prefix
+ if (VEX_B && VEX_X && !VEX_W && (VEX_5M == 1)) { // 2 byte VEX prefix
EmitByte(0xC5, CurByte, OS);
EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
return;
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86RegisterInfo.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86RegisterInfo.cpp Sun Jul 4 04:07:55 2010
@@ -674,8 +674,7 @@
// }
// [EBP]
MFI->CreateFixedObject(-TailCallReturnAddrDelta,
- (-1U*SlotSize)+TailCallReturnAddrDelta,
- true, false);
+ (-1U*SlotSize)+TailCallReturnAddrDelta, true);
}
if (hasFP(MF)) {
@@ -688,7 +687,7 @@
-(int)SlotSize +
TFI.getOffsetOfLocalArea() +
TailCallReturnAddrDelta,
- true, false);
+ true);
assert(FrameIdx == MFI->getObjectIndexBegin() &&
"Slot for EBP register must be last in order to be found!");
FrameIdx = 0;
Modified: llvm/branches/wendling/eh/lib/Target/XCore/XCoreISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/XCore/XCoreISelLowering.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/XCore/XCoreISelLowering.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/XCore/XCoreISelLowering.cpp Sun Jul 4 04:07:55 2010
@@ -1072,7 +1072,7 @@
// Create the frame index object for this incoming parameter...
int FI = MFI->CreateFixedObject(ObjSize,
LRSaveSize + VA.getLocMemOffset(),
- true, false);
+ true);
// Create the SelectionDAG nodes corresponding to a load
//from this parameter
@@ -1097,7 +1097,7 @@
// address
for (unsigned i = array_lengthof(ArgRegs) - 1; i >= FirstVAReg; --i) {
// Create a stack slot
- int FI = MFI->CreateFixedObject(4, offset, true, false);
+ int FI = MFI->CreateFixedObject(4, offset, true);
if (i == FirstVAReg) {
XFI->setVarArgsFrameIndex(FI);
}
@@ -1120,7 +1120,7 @@
// This will point to the next argument passed via stack.
XFI->setVarArgsFrameIndex(
MFI->CreateFixedObject(4, LRSaveSize + CCInfo.getNextStackOffset(),
- true, false));
+ true));
}
}
Modified: llvm/branches/wendling/eh/lib/Target/XCore/XCoreRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/XCore/XCoreRegisterInfo.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/XCore/XCoreRegisterInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/XCore/XCoreRegisterInfo.cpp Sun Jul 4 04:07:55 2010
@@ -308,7 +308,7 @@
int FrameIdx;
if (! isVarArg) {
// A fixed offset of 0 allows us to save / restore LR using entsp / retsp.
- FrameIdx = MFI->CreateFixedObject(RC->getSize(), 0, true, false);
+ FrameIdx = MFI->CreateFixedObject(RC->getSize(), 0, true);
} else {
FrameIdx = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(),
false);
Modified: llvm/branches/wendling/eh/lib/Transforms/Scalar/DeadStoreElimination.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Scalar/DeadStoreElimination.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Scalar/DeadStoreElimination.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Scalar/DeadStoreElimination.cpp Sun Jul 4 04:07:55 2010
@@ -74,7 +74,6 @@
AU.addRequired<AliasAnalysis>();
AU.addRequired<MemoryDependenceAnalysis>();
AU.addPreserved<DominatorTree>();
- AU.addPreserved<AliasAnalysis>();
AU.addPreserved<MemoryDependenceAnalysis>();
}
Modified: llvm/branches/wendling/eh/lib/Transforms/Utils/ValueMapper.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Utils/ValueMapper.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Utils/ValueMapper.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Utils/ValueMapper.cpp Sun Jul 4 04:07:55 2010
@@ -45,7 +45,7 @@
if (isa<ConstantInt>(C) || isa<ConstantFP>(C) ||
isa<ConstantPointerNull>(C) || isa<ConstantAggregateZero>(C) ||
- isa<UndefValue>(C) || isa<MDString>(C))
+ isa<UndefValue>(C))
return VMSlot = C; // Primitive constants map directly
if (ConstantArray *CA = dyn_cast<ConstantArray>(C)) {
Modified: llvm/branches/wendling/eh/test/CodeGen/ARM/vmov.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/CodeGen/ARM/vmov.ll?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/CodeGen/ARM/vmov.ll (original)
+++ llvm/branches/wendling/eh/test/CodeGen/ARM/vmov.ll Sun Jul 4 04:07:55 2010
@@ -2,135 +2,121 @@
define <8 x i8> @v_movi8() nounwind {
;CHECK: v_movi8:
-;CHECK: vmov.i8
+;CHECK: vmov.i8 d0, #0x8
ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
}
define <4 x i16> @v_movi16a() nounwind {
;CHECK: v_movi16a:
-;CHECK: vmov.i16
+;CHECK: vmov.i16 d0, #0x10
ret <4 x i16> < i16 16, i16 16, i16 16, i16 16 >
}
-; 0x1000 = 4096
define <4 x i16> @v_movi16b() nounwind {
;CHECK: v_movi16b:
-;CHECK: vmov.i16
+;CHECK: vmov.i16 d0, #0x1000
ret <4 x i16> < i16 4096, i16 4096, i16 4096, i16 4096 >
}
define <2 x i32> @v_movi32a() nounwind {
;CHECK: v_movi32a:
-;CHECK: vmov.i32
+;CHECK: vmov.i32 d0, #0x20
ret <2 x i32> < i32 32, i32 32 >
}
-; 0x2000 = 8192
define <2 x i32> @v_movi32b() nounwind {
;CHECK: v_movi32b:
-;CHECK: vmov.i32
+;CHECK: vmov.i32 d0, #0x2000
ret <2 x i32> < i32 8192, i32 8192 >
}
-; 0x200000 = 2097152
define <2 x i32> @v_movi32c() nounwind {
;CHECK: v_movi32c:
-;CHECK: vmov.i32
+;CHECK: vmov.i32 d0, #0x200000
ret <2 x i32> < i32 2097152, i32 2097152 >
}
-; 0x20000000 = 536870912
define <2 x i32> @v_movi32d() nounwind {
;CHECK: v_movi32d:
-;CHECK: vmov.i32
+;CHECK: vmov.i32 d0, #0x20000000
ret <2 x i32> < i32 536870912, i32 536870912 >
}
-; 0x20ff = 8447
define <2 x i32> @v_movi32e() nounwind {
;CHECK: v_movi32e:
-;CHECK: vmov.i32
+;CHECK: vmov.i32 d0, #0x20FF
ret <2 x i32> < i32 8447, i32 8447 >
}
-; 0x20ffff = 2162687
define <2 x i32> @v_movi32f() nounwind {
;CHECK: v_movi32f:
-;CHECK: vmov.i32
+;CHECK: vmov.i32 d0, #0x20FFFF
ret <2 x i32> < i32 2162687, i32 2162687 >
}
-; 0xff0000ff0000ffff = 18374687574888349695
define <1 x i64> @v_movi64() nounwind {
;CHECK: v_movi64:
-;CHECK: vmov.i64
+;CHECK: vmov.i64 d0, #0xFF0000FF0000FFFF
ret <1 x i64> < i64 18374687574888349695 >
}
define <16 x i8> @v_movQi8() nounwind {
;CHECK: v_movQi8:
-;CHECK: vmov.i8
+;CHECK: vmov.i8 q0, #0x8
ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
}
define <8 x i16> @v_movQi16a() nounwind {
;CHECK: v_movQi16a:
-;CHECK: vmov.i16
+;CHECK: vmov.i16 q0, #0x10
ret <8 x i16> < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
}
-; 0x1000 = 4096
define <8 x i16> @v_movQi16b() nounwind {
;CHECK: v_movQi16b:
-;CHECK: vmov.i16
+;CHECK: vmov.i16 q0, #0x1000
ret <8 x i16> < i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096 >
}
define <4 x i32> @v_movQi32a() nounwind {
;CHECK: v_movQi32a:
-;CHECK: vmov.i32
+;CHECK: vmov.i32 q0, #0x20
ret <4 x i32> < i32 32, i32 32, i32 32, i32 32 >
}
-; 0x2000 = 8192
define <4 x i32> @v_movQi32b() nounwind {
;CHECK: v_movQi32b:
-;CHECK: vmov.i32
+;CHECK: vmov.i32 q0, #0x2000
ret <4 x i32> < i32 8192, i32 8192, i32 8192, i32 8192 >
}
-; 0x200000 = 2097152
define <4 x i32> @v_movQi32c() nounwind {
;CHECK: v_movQi32c:
-;CHECK: vmov.i32
+;CHECK: vmov.i32 q0, #0x200000
ret <4 x i32> < i32 2097152, i32 2097152, i32 2097152, i32 2097152 >
}
-; 0x20000000 = 536870912
define <4 x i32> @v_movQi32d() nounwind {
;CHECK: v_movQi32d:
-;CHECK: vmov.i32
+;CHECK: vmov.i32 q0, #0x20000000
ret <4 x i32> < i32 536870912, i32 536870912, i32 536870912, i32 536870912 >
}
-; 0x20ff = 8447
define <4 x i32> @v_movQi32e() nounwind {
;CHECK: v_movQi32e:
-;CHECK: vmov.i32
+;CHECK: vmov.i32 q0, #0x20FF
ret <4 x i32> < i32 8447, i32 8447, i32 8447, i32 8447 >
}
-; 0x20ffff = 2162687
define <4 x i32> @v_movQi32f() nounwind {
;CHECK: v_movQi32f:
-;CHECK: vmov.i32
+;CHECK: vmov.i32 q0, #0x20FFFF
ret <4 x i32> < i32 2162687, i32 2162687, i32 2162687, i32 2162687 >
}
-; 0xff0000ff0000ffff = 18374687574888349695
define <2 x i64> @v_movQi64() nounwind {
;CHECK: v_movQi64:
-;CHECK: vmov.i64
+;CHECK: vmov.i64 q0, #0xFF0000FF0000FFFF
ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 >
}
Modified: llvm/branches/wendling/eh/test/CodeGen/Thumb/push.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/CodeGen/Thumb/push.ll?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/CodeGen/Thumb/push.ll (original)
+++ llvm/branches/wendling/eh/test/CodeGen/Thumb/push.ll Sun Jul 4 04:07:55 2010
@@ -5,6 +5,6 @@
; CHECK: t:
; CHECK: push {r7}
entry:
- call void asm sideeffect ".long 0xe7ffdefe", ""() nounwind
+ call void asm sideeffect alignstack ".long 0xe7ffdefe", ""() nounwind
ret void
}
Modified: llvm/branches/wendling/eh/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll (original)
+++ llvm/branches/wendling/eh/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll Sun Jul 4 04:07:55 2010
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -relocation-model=pic -disable-fp-elim -stats |& grep asm-printer | grep 83
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -relocation-model=pic -disable-fp-elim -stats |& grep asm-printer | grep 82
; rdar://6802189
; Test if linearscan is unfavoring registers for allocation to allow more reuse
Modified: llvm/branches/wendling/eh/test/CodeGen/X86/inline-asm-tied.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/CodeGen/X86/inline-asm-tied.ll?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/CodeGen/X86/inline-asm-tied.ll (original)
+++ llvm/branches/wendling/eh/test/CodeGen/X86/inline-asm-tied.ll Sun Jul 4 04:07:55 2010
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=i386-apple-darwin9 -O0 -regalloc=linearscan | grep {movl %edx, 12(%esp)} | count 2
+; RUN: llc < %s -mtriple=i386-apple-darwin9 -O0 -regalloc=linearscan | grep {movl %edx, 4(%esp)} | count 2
; rdar://6992609
target triple = "i386-apple-darwin9.0"
Modified: llvm/branches/wendling/eh/test/CodeGen/X86/iv-users-in-other-loops.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/CodeGen/X86/iv-users-in-other-loops.ll?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/CodeGen/X86/iv-users-in-other-loops.ll (original)
+++ llvm/branches/wendling/eh/test/CodeGen/X86/iv-users-in-other-loops.ll Sun Jul 4 04:07:55 2010
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=x86-64 -o %t
; RUN: not grep inc %t
; RUN: grep dec %t | count 2
-; RUN: grep addq %t | count 13
+; RUN: grep addq %t | count 12
; RUN: not grep addb %t
; RUN: not grep leaq %t
; RUN: not grep leal %t
Modified: llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_32-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_32-encoding.s?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_32-encoding.s (original)
+++ llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_32-encoding.s Sun Jul 4 04:07:55 2010
@@ -11614,3 +11614,316 @@
// CHECK: encoding: [0xc5,0xe9,0x7d,0x18]
vhsubpd (%eax), %xmm2, %xmm3
+// CHECK: vpabsb %xmm1, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x79,0x1c,0xd1]
+ vpabsb %xmm1, %xmm2
+
+// CHECK: vpabsb (%eax), %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x79,0x1c,0x10]
+ vpabsb (%eax), %xmm2
+
+// CHECK: vpabsw %xmm1, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x79,0x1d,0xd1]
+ vpabsw %xmm1, %xmm2
+
+// CHECK: vpabsw (%eax), %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x79,0x1d,0x10]
+ vpabsw (%eax), %xmm2
+
+// CHECK: vpabsd %xmm1, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x79,0x1e,0xd1]
+ vpabsd %xmm1, %xmm2
+
+// CHECK: vpabsd (%eax), %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x79,0x1e,0x10]
+ vpabsd (%eax), %xmm2
+
+// CHECK: vphaddw %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x01,0xd9]
+ vphaddw %xmm1, %xmm2, %xmm3
+
+// CHECK: vphaddw (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x01,0x18]
+ vphaddw (%eax), %xmm2, %xmm3
+
+// CHECK: vphaddd %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x02,0xd9]
+ vphaddd %xmm1, %xmm2, %xmm3
+
+// CHECK: vphaddd (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x02,0x18]
+ vphaddd (%eax), %xmm2, %xmm3
+
+// CHECK: vphaddsw %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x03,0xd9]
+ vphaddsw %xmm1, %xmm2, %xmm3
+
+// CHECK: vphaddsw (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x03,0x18]
+ vphaddsw (%eax), %xmm2, %xmm3
+
+// CHECK: vphsubw %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x05,0xd9]
+ vphsubw %xmm1, %xmm2, %xmm3
+
+// CHECK: vphsubw (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x05,0x18]
+ vphsubw (%eax), %xmm2, %xmm3
+
+// CHECK: vphsubd %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x06,0xd9]
+ vphsubd %xmm1, %xmm2, %xmm3
+
+// CHECK: vphsubd (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x06,0x18]
+ vphsubd (%eax), %xmm2, %xmm3
+
+// CHECK: vphsubsw %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x07,0xd9]
+ vphsubsw %xmm1, %xmm2, %xmm3
+
+// CHECK: vphsubsw (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x07,0x18]
+ vphsubsw (%eax), %xmm2, %xmm3
+
+// CHECK: vpmaddubsw %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x04,0xd9]
+ vpmaddubsw %xmm1, %xmm2, %xmm3
+
+// CHECK: vpmaddubsw (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x04,0x18]
+ vpmaddubsw (%eax), %xmm2, %xmm3
+
+// CHECK: vpshufb %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x00,0xd9]
+ vpshufb %xmm1, %xmm2, %xmm3
+
+// CHECK: vpshufb (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x00,0x18]
+ vpshufb (%eax), %xmm2, %xmm3
+
+// CHECK: vpsignb %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x08,0xd9]
+ vpsignb %xmm1, %xmm2, %xmm3
+
+// CHECK: vpsignb (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x08,0x18]
+ vpsignb (%eax), %xmm2, %xmm3
+
+// CHECK: vpsignw %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x09,0xd9]
+ vpsignw %xmm1, %xmm2, %xmm3
+
+// CHECK: vpsignw (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x09,0x18]
+ vpsignw (%eax), %xmm2, %xmm3
+
+// CHECK: vpsignd %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x0a,0xd9]
+ vpsignd %xmm1, %xmm2, %xmm3
+
+// CHECK: vpsignd (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x0a,0x18]
+ vpsignd (%eax), %xmm2, %xmm3
+
+// CHECK: vpmulhrsw %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x0b,0xd9]
+ vpmulhrsw %xmm1, %xmm2, %xmm3
+
+// CHECK: vpmulhrsw (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x0b,0x18]
+ vpmulhrsw (%eax), %xmm2, %xmm3
+
+// CHECK: vpalignr $7, %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe3,0x69,0x0f,0xd9,0x07]
+ vpalignr $7, %xmm1, %xmm2, %xmm3
+
+// CHECK: vpalignr $7, (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe3,0x69,0x0f,0x18,0x07]
+ vpalignr $7, (%eax), %xmm2, %xmm3
+
+// CHECK: vroundsd $7, %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe3,0x69,0x0b,0xd9,0x07]
+ vroundsd $7, %xmm1, %xmm2, %xmm3
+
+// CHECK: vroundsd $7, (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe3,0x69,0x0b,0x18,0x07]
+ vroundsd $7, (%eax), %xmm2, %xmm3
+
+// CHECK: vroundss $7, %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe3,0x69,0x0a,0xd9,0x07]
+ vroundss $7, %xmm1, %xmm2, %xmm3
+
+// CHECK: vroundss $7, (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe3,0x69,0x0a,0x18,0x07]
+ vroundss $7, (%eax), %xmm2, %xmm3
+
+// CHECK: vroundpd $7, %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe3,0x79,0x09,0xda,0x07]
+ vroundpd $7, %xmm2, %xmm3
+
+// CHECK: vroundpd $7, (%eax), %xmm3
+// CHECK: encoding: [0xc4,0xe3,0x79,0x09,0x18,0x07]
+ vroundpd $7, (%eax), %xmm3
+
+// CHECK: vroundps $7, %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe3,0x79,0x08,0xda,0x07]
+ vroundps $7, %xmm2, %xmm3
+
+// CHECK: vroundps $7, (%eax), %xmm3
+// CHECK: encoding: [0xc4,0xe3,0x79,0x08,0x18,0x07]
+ vroundps $7, (%eax), %xmm3
+
+// CHECK: vphminposuw %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x79,0x41,0xda]
+ vphminposuw %xmm2, %xmm3
+
+// CHECK: vphminposuw (%eax), %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x79,0x41,0x10]
+ vphminposuw (%eax), %xmm2
+
+// CHECK: vpackusdw %xmm2, %xmm3, %xmm1
+// CHECK: encoding: [0xc4,0xe2,0x61,0x2b,0xca]
+ vpackusdw %xmm2, %xmm3, %xmm1
+
+// CHECK: vpackusdw (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x2b,0x18]
+ vpackusdw (%eax), %xmm2, %xmm3
+
+// CHECK: vpcmpeqq %xmm2, %xmm3, %xmm1
+// CHECK: encoding: [0xc4,0xe2,0x61,0x29,0xca]
+ vpcmpeqq %xmm2, %xmm3, %xmm1
+
+// CHECK: vpcmpeqq (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x29,0x18]
+ vpcmpeqq (%eax), %xmm2, %xmm3
+
+// CHECK: vpminsb %xmm2, %xmm3, %xmm1
+// CHECK: encoding: [0xc4,0xe2,0x61,0x38,0xca]
+ vpminsb %xmm2, %xmm3, %xmm1
+
+// CHECK: vpminsb (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x38,0x18]
+ vpminsb (%eax), %xmm2, %xmm3
+
+// CHECK: vpminsd %xmm2, %xmm3, %xmm1
+// CHECK: encoding: [0xc4,0xe2,0x61,0x39,0xca]
+ vpminsd %xmm2, %xmm3, %xmm1
+
+// CHECK: vpminsd (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x39,0x18]
+ vpminsd (%eax), %xmm2, %xmm3
+
+// CHECK: vpminud %xmm2, %xmm3, %xmm1
+// CHECK: encoding: [0xc4,0xe2,0x61,0x3b,0xca]
+ vpminud %xmm2, %xmm3, %xmm1
+
+// CHECK: vpminud (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x3b,0x18]
+ vpminud (%eax), %xmm2, %xmm3
+
+// CHECK: vpminuw %xmm2, %xmm3, %xmm1
+// CHECK: encoding: [0xc4,0xe2,0x61,0x3a,0xca]
+ vpminuw %xmm2, %xmm3, %xmm1
+
+// CHECK: vpminuw (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x3a,0x18]
+ vpminuw (%eax), %xmm2, %xmm3
+
+// CHECK: vpmaxsb %xmm2, %xmm3, %xmm1
+// CHECK: encoding: [0xc4,0xe2,0x61,0x3c,0xca]
+ vpmaxsb %xmm2, %xmm3, %xmm1
+
+// CHECK: vpmaxsb (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x3c,0x18]
+ vpmaxsb (%eax), %xmm2, %xmm3
+
+// CHECK: vpmaxsd %xmm2, %xmm3, %xmm1
+// CHECK: encoding: [0xc4,0xe2,0x61,0x3d,0xca]
+ vpmaxsd %xmm2, %xmm3, %xmm1
+
+// CHECK: vpmaxsd (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x3d,0x18]
+ vpmaxsd (%eax), %xmm2, %xmm3
+
+// CHECK: vpmaxud %xmm2, %xmm3, %xmm1
+// CHECK: encoding: [0xc4,0xe2,0x61,0x3f,0xca]
+ vpmaxud %xmm2, %xmm3, %xmm1
+
+// CHECK: vpmaxud (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x3f,0x18]
+ vpmaxud (%eax), %xmm2, %xmm3
+
+// CHECK: vpmaxuw %xmm2, %xmm3, %xmm1
+// CHECK: encoding: [0xc4,0xe2,0x61,0x3e,0xca]
+ vpmaxuw %xmm2, %xmm3, %xmm1
+
+// CHECK: vpmaxuw (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x3e,0x18]
+ vpmaxuw (%eax), %xmm2, %xmm3
+
+// CHECK: vpmuldq %xmm2, %xmm3, %xmm1
+// CHECK: encoding: [0xc4,0xe2,0x61,0x28,0xca]
+ vpmuldq %xmm2, %xmm3, %xmm1
+
+// CHECK: vpmuldq (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x28,0x18]
+ vpmuldq (%eax), %xmm2, %xmm3
+
+// CHECK: vpmulld %xmm2, %xmm5, %xmm1
+// CHECK: encoding: [0xc4,0xe2,0x51,0x40,0xca]
+ vpmulld %xmm2, %xmm5, %xmm1
+
+// CHECK: vpmulld (%eax), %xmm5, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x51,0x40,0x18]
+ vpmulld (%eax), %xmm5, %xmm3
+
+// CHECK: vblendps $3, %xmm2, %xmm5, %xmm1
+// CHECK: encoding: [0xc4,0xe3,0x51,0x0c,0xca,0x03]
+ vblendps $3, %xmm2, %xmm5, %xmm1
+
+// CHECK: vblendps $3, (%eax), %xmm5, %xmm1
+// CHECK: encoding: [0xc4,0xe3,0x51,0x0c,0x08,0x03]
+ vblendps $3, (%eax), %xmm5, %xmm1
+
+// CHECK: vblendpd $3, %xmm2, %xmm5, %xmm1
+// CHECK: encoding: [0xc4,0xe3,0x51,0x0d,0xca,0x03]
+ vblendpd $3, %xmm2, %xmm5, %xmm1
+
+// CHECK: vblendpd $3, (%eax), %xmm5, %xmm1
+// CHECK: encoding: [0xc4,0xe3,0x51,0x0d,0x08,0x03]
+ vblendpd $3, (%eax), %xmm5, %xmm1
+
+// CHECK: vpblendw $3, %xmm2, %xmm5, %xmm1
+// CHECK: encoding: [0xc4,0xe3,0x51,0x0e,0xca,0x03]
+ vpblendw $3, %xmm2, %xmm5, %xmm1
+
+// CHECK: vpblendw $3, (%eax), %xmm5, %xmm1
+// CHECK: encoding: [0xc4,0xe3,0x51,0x0e,0x08,0x03]
+ vpblendw $3, (%eax), %xmm5, %xmm1
+
+// CHECK: vmpsadbw $3, %xmm2, %xmm5, %xmm1
+// CHECK: encoding: [0xc4,0xe3,0x51,0x42,0xca,0x03]
+ vmpsadbw $3, %xmm2, %xmm5, %xmm1
+
+// CHECK: vmpsadbw $3, (%eax), %xmm5, %xmm1
+// CHECK: encoding: [0xc4,0xe3,0x51,0x42,0x08,0x03]
+ vmpsadbw $3, (%eax), %xmm5, %xmm1
+
+// CHECK: vdpps $3, %xmm2, %xmm5, %xmm1
+// CHECK: encoding: [0xc4,0xe3,0x51,0x40,0xca,0x03]
+ vdpps $3, %xmm2, %xmm5, %xmm1
+
+// CHECK: vdpps $3, (%eax), %xmm5, %xmm1
+// CHECK: encoding: [0xc4,0xe3,0x51,0x40,0x08,0x03]
+ vdpps $3, (%eax), %xmm5, %xmm1
+
+// CHECK: vdppd $3, %xmm2, %xmm5, %xmm1
+// CHECK: encoding: [0xc4,0xe3,0x51,0x41,0xca,0x03]
+ vdppd $3, %xmm2, %xmm5, %xmm1
+
+// CHECK: vdppd $3, (%eax), %xmm5, %xmm1
+// CHECK: encoding: [0xc4,0xe3,0x51,0x41,0x08,0x03]
+ vdppd $3, (%eax), %xmm5, %xmm1
+
+
Modified: llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_64-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_64-encoding.s?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_64-encoding.s (original)
+++ llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_64-encoding.s Sun Jul 4 04:07:55 2010
@@ -1662,3 +1662,315 @@
// CHECK: encoding: [0xc5,0x19,0x7d,0x28]
vhsubpd (%rax), %xmm12, %xmm13
+// CHECK: vpabsb %xmm11, %xmm12
+// CHECK: encoding: [0xc4,0x42,0x79,0x1c,0xe3]
+ vpabsb %xmm11, %xmm12
+
+// CHECK: vpabsb (%rax), %xmm12
+// CHECK: encoding: [0xc4,0x62,0x79,0x1c,0x20]
+ vpabsb (%rax), %xmm12
+
+// CHECK: vpabsw %xmm11, %xmm12
+// CHECK: encoding: [0xc4,0x42,0x79,0x1d,0xe3]
+ vpabsw %xmm11, %xmm12
+
+// CHECK: vpabsw (%rax), %xmm12
+// CHECK: encoding: [0xc4,0x62,0x79,0x1d,0x20]
+ vpabsw (%rax), %xmm12
+
+// CHECK: vpabsd %xmm11, %xmm12
+// CHECK: encoding: [0xc4,0x42,0x79,0x1e,0xe3]
+ vpabsd %xmm11, %xmm12
+
+// CHECK: vpabsd (%rax), %xmm12
+// CHECK: encoding: [0xc4,0x62,0x79,0x1e,0x20]
+ vpabsd (%rax), %xmm12
+
+// CHECK: vphaddw %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x42,0x19,0x01,0xeb]
+ vphaddw %xmm11, %xmm12, %xmm13
+
+// CHECK: vphaddw (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x01,0x28]
+ vphaddw (%rax), %xmm12, %xmm13
+
+// CHECK: vphaddd %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x42,0x19,0x02,0xeb]
+ vphaddd %xmm11, %xmm12, %xmm13
+
+// CHECK: vphaddd (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x02,0x28]
+ vphaddd (%rax), %xmm12, %xmm13
+
+// CHECK: vphaddsw %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x42,0x19,0x03,0xeb]
+ vphaddsw %xmm11, %xmm12, %xmm13
+
+// CHECK: vphaddsw (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x03,0x28]
+ vphaddsw (%rax), %xmm12, %xmm13
+
+// CHECK: vphsubw %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x42,0x19,0x05,0xeb]
+ vphsubw %xmm11, %xmm12, %xmm13
+
+// CHECK: vphsubw (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x05,0x28]
+ vphsubw (%rax), %xmm12, %xmm13
+
+// CHECK: vphsubd %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x42,0x19,0x06,0xeb]
+ vphsubd %xmm11, %xmm12, %xmm13
+
+// CHECK: vphsubd (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x06,0x28]
+ vphsubd (%rax), %xmm12, %xmm13
+
+// CHECK: vphsubsw %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x42,0x19,0x07,0xeb]
+ vphsubsw %xmm11, %xmm12, %xmm13
+
+// CHECK: vphsubsw (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x07,0x28]
+ vphsubsw (%rax), %xmm12, %xmm13
+
+// CHECK: vpmaddubsw %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x42,0x19,0x04,0xeb]
+ vpmaddubsw %xmm11, %xmm12, %xmm13
+
+// CHECK: vpmaddubsw (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x04,0x28]
+ vpmaddubsw (%rax), %xmm12, %xmm13
+
+// CHECK: vpshufb %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x42,0x19,0x00,0xeb]
+ vpshufb %xmm11, %xmm12, %xmm13
+
+// CHECK: vpshufb (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x00,0x28]
+ vpshufb (%rax), %xmm12, %xmm13
+
+// CHECK: vpsignb %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x42,0x19,0x08,0xeb]
+ vpsignb %xmm11, %xmm12, %xmm13
+
+// CHECK: vpsignb (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x08,0x28]
+ vpsignb (%rax), %xmm12, %xmm13
+
+// CHECK: vpsignw %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x42,0x19,0x09,0xeb]
+ vpsignw %xmm11, %xmm12, %xmm13
+
+// CHECK: vpsignw (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x09,0x28]
+ vpsignw (%rax), %xmm12, %xmm13
+
+// CHECK: vpsignd %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x42,0x19,0x0a,0xeb]
+ vpsignd %xmm11, %xmm12, %xmm13
+
+// CHECK: vpsignd (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x0a,0x28]
+ vpsignd (%rax), %xmm12, %xmm13
+
+// CHECK: vpmulhrsw %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x42,0x19,0x0b,0xeb]
+ vpmulhrsw %xmm11, %xmm12, %xmm13
+
+// CHECK: vpmulhrsw (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x0b,0x28]
+ vpmulhrsw (%rax), %xmm12, %xmm13
+
+// CHECK: vpalignr $7, %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x43,0x19,0x0f,0xeb,0x07]
+ vpalignr $7, %xmm11, %xmm12, %xmm13
+
+// CHECK: vpalignr $7, (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x63,0x19,0x0f,0x28,0x07]
+ vpalignr $7, (%rax), %xmm12, %xmm13
+
+// CHECK: vroundsd $7, %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x43,0x19,0x0b,0xeb,0x07]
+ vroundsd $7, %xmm11, %xmm12, %xmm13
+
+// CHECK: vroundsd $7, (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x63,0x19,0x0b,0x28,0x07]
+ vroundsd $7, (%rax), %xmm12, %xmm13
+
+// CHECK: vroundss $7, %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x43,0x19,0x0a,0xeb,0x07]
+ vroundss $7, %xmm11, %xmm12, %xmm13
+
+// CHECK: vroundss $7, (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x63,0x19,0x0a,0x28,0x07]
+ vroundss $7, (%rax), %xmm12, %xmm13
+
+// CHECK: vroundpd $7, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x43,0x79,0x09,0xec,0x07]
+ vroundpd $7, %xmm12, %xmm13
+
+// CHECK: vroundpd $7, (%rax), %xmm13
+// CHECK: encoding: [0xc4,0x63,0x79,0x09,0x28,0x07]
+ vroundpd $7, (%rax), %xmm13
+
+// CHECK: vroundps $7, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x43,0x79,0x08,0xec,0x07]
+ vroundps $7, %xmm12, %xmm13
+
+// CHECK: vroundps $7, (%rax), %xmm13
+// CHECK: encoding: [0xc4,0x63,0x79,0x08,0x28,0x07]
+ vroundps $7, (%rax), %xmm13
+
+// CHECK: vphminposuw %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x42,0x79,0x41,0xec]
+ vphminposuw %xmm12, %xmm13
+
+// CHECK: vphminposuw (%rax), %xmm12
+// CHECK: encoding: [0xc4,0x62,0x79,0x41,0x20]
+ vphminposuw (%rax), %xmm12
+
+// CHECK: vpackusdw %xmm12, %xmm13, %xmm11
+// CHECK: encoding: [0xc4,0x42,0x11,0x2b,0xdc]
+ vpackusdw %xmm12, %xmm13, %xmm11
+
+// CHECK: vpackusdw (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x2b,0x28]
+ vpackusdw (%rax), %xmm12, %xmm13
+
+// CHECK: vpcmpeqq %xmm12, %xmm13, %xmm11
+// CHECK: encoding: [0xc4,0x42,0x11,0x29,0xdc]
+ vpcmpeqq %xmm12, %xmm13, %xmm11
+
+// CHECK: vpcmpeqq (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x29,0x28]
+ vpcmpeqq (%rax), %xmm12, %xmm13
+
+// CHECK: vpminsb %xmm12, %xmm13, %xmm11
+// CHECK: encoding: [0xc4,0x42,0x11,0x38,0xdc]
+ vpminsb %xmm12, %xmm13, %xmm11
+
+// CHECK: vpminsb (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x38,0x28]
+ vpminsb (%rax), %xmm12, %xmm13
+
+// CHECK: vpminsd %xmm12, %xmm13, %xmm11
+// CHECK: encoding: [0xc4,0x42,0x11,0x39,0xdc]
+ vpminsd %xmm12, %xmm13, %xmm11
+
+// CHECK: vpminsd (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x39,0x28]
+ vpminsd (%rax), %xmm12, %xmm13
+
+// CHECK: vpminud %xmm12, %xmm13, %xmm11
+// CHECK: encoding: [0xc4,0x42,0x11,0x3b,0xdc]
+ vpminud %xmm12, %xmm13, %xmm11
+
+// CHECK: vpminud (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x3b,0x28]
+ vpminud (%rax), %xmm12, %xmm13
+
+// CHECK: vpminuw %xmm12, %xmm13, %xmm11
+// CHECK: encoding: [0xc4,0x42,0x11,0x3a,0xdc]
+ vpminuw %xmm12, %xmm13, %xmm11
+
+// CHECK: vpminuw (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x3a,0x28]
+ vpminuw (%rax), %xmm12, %xmm13
+
+// CHECK: vpmaxsb %xmm12, %xmm13, %xmm11
+// CHECK: encoding: [0xc4,0x42,0x11,0x3c,0xdc]
+ vpmaxsb %xmm12, %xmm13, %xmm11
+
+// CHECK: vpmaxsb (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x3c,0x28]
+ vpmaxsb (%rax), %xmm12, %xmm13
+
+// CHECK: vpmaxsd %xmm12, %xmm13, %xmm11
+// CHECK: encoding: [0xc4,0x42,0x11,0x3d,0xdc]
+ vpmaxsd %xmm12, %xmm13, %xmm11
+
+// CHECK: vpmaxsd (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x3d,0x28]
+ vpmaxsd (%rax), %xmm12, %xmm13
+
+// CHECK: vpmaxud %xmm12, %xmm13, %xmm11
+// CHECK: encoding: [0xc4,0x42,0x11,0x3f,0xdc]
+ vpmaxud %xmm12, %xmm13, %xmm11
+
+// CHECK: vpmaxud (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x3f,0x28]
+ vpmaxud (%rax), %xmm12, %xmm13
+
+// CHECK: vpmaxuw %xmm12, %xmm13, %xmm11
+// CHECK: encoding: [0xc4,0x42,0x11,0x3e,0xdc]
+ vpmaxuw %xmm12, %xmm13, %xmm11
+
+// CHECK: vpmaxuw (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x3e,0x28]
+ vpmaxuw (%rax), %xmm12, %xmm13
+
+// CHECK: vpmuldq %xmm12, %xmm13, %xmm11
+// CHECK: encoding: [0xc4,0x42,0x11,0x28,0xdc]
+ vpmuldq %xmm12, %xmm13, %xmm11
+
+// CHECK: vpmuldq (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x28,0x28]
+ vpmuldq (%rax), %xmm12, %xmm13
+
+// CHECK: vpmulld %xmm12, %xmm5, %xmm11
+// CHECK: encoding: [0xc4,0x42,0x51,0x40,0xdc]
+ vpmulld %xmm12, %xmm5, %xmm11
+
+// CHECK: vpmulld (%rax), %xmm5, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x51,0x40,0x28]
+ vpmulld (%rax), %xmm5, %xmm13
+
+// CHECK: vblendps $3, %xmm12, %xmm5, %xmm11
+// CHECK: encoding: [0xc4,0x43,0x51,0x0c,0xdc,0x03]
+ vblendps $3, %xmm12, %xmm5, %xmm11
+
+// CHECK: vblendps $3, (%rax), %xmm5, %xmm11
+// CHECK: encoding: [0xc4,0x63,0x51,0x0c,0x18,0x03]
+ vblendps $3, (%rax), %xmm5, %xmm11
+
+// CHECK: vblendpd $3, %xmm12, %xmm5, %xmm11
+// CHECK: encoding: [0xc4,0x43,0x51,0x0d,0xdc,0x03]
+ vblendpd $3, %xmm12, %xmm5, %xmm11
+
+// CHECK: vblendpd $3, (%rax), %xmm5, %xmm11
+// CHECK: encoding: [0xc4,0x63,0x51,0x0d,0x18,0x03]
+ vblendpd $3, (%rax), %xmm5, %xmm11
+
+// CHECK: vpblendw $3, %xmm12, %xmm5, %xmm11
+// CHECK: encoding: [0xc4,0x43,0x51,0x0e,0xdc,0x03]
+ vpblendw $3, %xmm12, %xmm5, %xmm11
+
+// CHECK: vpblendw $3, (%rax), %xmm5, %xmm11
+// CHECK: encoding: [0xc4,0x63,0x51,0x0e,0x18,0x03]
+ vpblendw $3, (%rax), %xmm5, %xmm11
+
+// CHECK: vmpsadbw $3, %xmm12, %xmm5, %xmm11
+// CHECK: encoding: [0xc4,0x43,0x51,0x42,0xdc,0x03]
+ vmpsadbw $3, %xmm12, %xmm5, %xmm11
+
+// CHECK: vmpsadbw $3, (%rax), %xmm5, %xmm11
+// CHECK: encoding: [0xc4,0x63,0x51,0x42,0x18,0x03]
+ vmpsadbw $3, (%rax), %xmm5, %xmm11
+
+// CHECK: vdpps $3, %xmm12, %xmm5, %xmm11
+// CHECK: encoding: [0xc4,0x43,0x51,0x40,0xdc,0x03]
+ vdpps $3, %xmm12, %xmm5, %xmm11
+
+// CHECK: vdpps $3, (%rax), %xmm5, %xmm11
+// CHECK: encoding: [0xc4,0x63,0x51,0x40,0x18,0x03]
+ vdpps $3, (%rax), %xmm5, %xmm11
+
+// CHECK: vdppd $3, %xmm12, %xmm5, %xmm11
+// CHECK: encoding: [0xc4,0x43,0x51,0x41,0xdc,0x03]
+ vdppd $3, %xmm12, %xmm5, %xmm11
+
+// CHECK: vdppd $3, (%rax), %xmm5, %xmm11
+// CHECK: encoding: [0xc4,0x63,0x51,0x41,0x18,0x03]
+ vdppd $3, (%rax), %xmm5, %xmm11
+
Modified: llvm/branches/wendling/eh/utils/TableGen/CodeEmitterGen.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/utils/TableGen/CodeEmitterGen.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/utils/TableGen/CodeEmitterGen.cpp (original)
+++ llvm/branches/wendling/eh/utils/TableGen/CodeEmitterGen.cpp Sun Jul 4 04:07:55 2010
@@ -24,19 +24,8 @@
for (std::vector<Record*>::iterator I = Insts.begin(), E = Insts.end();
I != E; ++I) {
Record *R = *I;
- if (R->getName() == "PHI" ||
- R->getName() == "INLINEASM" ||
- R->getName() == "DBG_LABEL" ||
- R->getName() == "EH_LABEL" ||
- R->getName() == "GC_LABEL" ||
- R->getName() == "KILL" ||
- R->getName() == "EXTRACT_SUBREG" ||
- R->getName() == "INSERT_SUBREG" ||
- R->getName() == "IMPLICIT_DEF" ||
- R->getName() == "SUBREG_TO_REG" ||
- R->getName() == "COPY_TO_REGCLASS" ||
- R->getName() == "DBG_VALUE" ||
- R->getName() == "REG_SEQUENCE") continue;
+ if (R->getValueAsString("Namespace") == "TargetOpcode")
+ continue;
BitsInit *BI = R->getValueAsBitsInit("Inst");
@@ -103,19 +92,7 @@
const CodeGenInstruction *CGI = *IN;
Record *R = CGI->TheDef;
- if (R->getName() == "PHI" ||
- R->getName() == "INLINEASM" ||
- R->getName() == "DBG_LABEL" ||
- R->getName() == "EH_LABEL" ||
- R->getName() == "GC_LABEL" ||
- R->getName() == "KILL" ||
- R->getName() == "EXTRACT_SUBREG" ||
- R->getName() == "INSERT_SUBREG" ||
- R->getName() == "IMPLICIT_DEF" ||
- R->getName() == "SUBREG_TO_REG" ||
- R->getName() == "COPY_TO_REGCLASS" ||
- R->getName() == "DBG_VALUE" ||
- R->getName() == "REG_SEQUENCE") {
+ if (R->getValueAsString("Namespace") == "TargetOpcode") {
o << " 0U,\n";
continue;
}
@@ -140,22 +117,10 @@
for (std::vector<Record*>::iterator IC = Insts.begin(), EC = Insts.end();
IC != EC; ++IC) {
Record *R = *IC;
+ if (R->getValueAsString("Namespace") == "TargetOpcode")
+ continue;
const std::string &InstName = R->getName();
std::string Case("");
-
- if (InstName == "PHI" ||
- InstName == "INLINEASM" ||
- InstName == "DBG_LABEL"||
- InstName == "EH_LABEL"||
- InstName == "GC_LABEL"||
- InstName == "KILL"||
- InstName == "EXTRACT_SUBREG" ||
- InstName == "INSERT_SUBREG" ||
- InstName == "IMPLICIT_DEF" ||
- InstName == "SUBREG_TO_REG" ||
- InstName == "COPY_TO_REGCLASS" ||
- InstName == "DBG_VALUE" ||
- InstName == "REG_SEQUENCE") continue;
BitsInit *BI = R->getValueAsBitsInit("Inst");
const std::vector<RecordVal> &Vals = R->getValues();
Modified: llvm/branches/wendling/eh/utils/TableGen/CodeGenTarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/utils/TableGen/CodeGenTarget.cpp?rev=107584&r1=107583&r2=107584&view=diff
==============================================================================
--- llvm/branches/wendling/eh/utils/TableGen/CodeGenTarget.cpp (original)
+++ llvm/branches/wendling/eh/utils/TableGen/CodeGenTarget.cpp Sun Jul 4 04:07:55 2010
@@ -329,61 +329,42 @@
/// getInstructionsByEnumValue - Return all of the instructions defined by the
/// target, ordered by their enum value.
void CodeGenTarget::ComputeInstrsByEnum() const {
+ // The ordering here must match the ordering in TargetOpcodes.h.
+ const char *const FixedInstrs[] = {
+ "PHI",
+ "INLINEASM",
+ "DBG_LABEL",
+ "EH_LABEL",
+ "GC_LABEL",
+ "KILL",
+ "EXTRACT_SUBREG",
+ "INSERT_SUBREG",
+ "IMPLICIT_DEF",
+ "SUBREG_TO_REG",
+ "COPY_TO_REGCLASS",
+ "DBG_VALUE",
+ "REG_SEQUENCE",
+ "COPY",
+ 0
+ };
const DenseMap<const Record*, CodeGenInstruction*> &Insts = getInstructions();
- const CodeGenInstruction *PHI = GetInstByName("PHI", Insts);
- const CodeGenInstruction *INLINEASM = GetInstByName("INLINEASM", Insts);
- const CodeGenInstruction *DBG_LABEL = GetInstByName("DBG_LABEL", Insts);
- const CodeGenInstruction *EH_LABEL = GetInstByName("EH_LABEL", Insts);
- const CodeGenInstruction *GC_LABEL = GetInstByName("GC_LABEL", Insts);
- const CodeGenInstruction *KILL = GetInstByName("KILL", Insts);
- const CodeGenInstruction *EXTRACT_SUBREG =
- GetInstByName("EXTRACT_SUBREG", Insts);
- const CodeGenInstruction *INSERT_SUBREG =
- GetInstByName("INSERT_SUBREG", Insts);
- const CodeGenInstruction *IMPLICIT_DEF = GetInstByName("IMPLICIT_DEF", Insts);
- const CodeGenInstruction *SUBREG_TO_REG =
- GetInstByName("SUBREG_TO_REG", Insts);
- const CodeGenInstruction *COPY_TO_REGCLASS =
- GetInstByName("COPY_TO_REGCLASS", Insts);
- const CodeGenInstruction *DBG_VALUE = GetInstByName("DBG_VALUE", Insts);
- const CodeGenInstruction *REG_SEQUENCE = GetInstByName("REG_SEQUENCE", Insts);
-
- // Print out the rest of the instructions now.
- InstrsByEnum.push_back(PHI);
- InstrsByEnum.push_back(INLINEASM);
- InstrsByEnum.push_back(DBG_LABEL);
- InstrsByEnum.push_back(EH_LABEL);
- InstrsByEnum.push_back(GC_LABEL);
- InstrsByEnum.push_back(KILL);
- InstrsByEnum.push_back(EXTRACT_SUBREG);
- InstrsByEnum.push_back(INSERT_SUBREG);
- InstrsByEnum.push_back(IMPLICIT_DEF);
- InstrsByEnum.push_back(SUBREG_TO_REG);
- InstrsByEnum.push_back(COPY_TO_REGCLASS);
- InstrsByEnum.push_back(DBG_VALUE);
- InstrsByEnum.push_back(REG_SEQUENCE);
-
+ for (const char *const *p = FixedInstrs; *p; ++p) {
+ const CodeGenInstruction *Instr = GetInstByName(*p, Insts);
+ assert(Instr && "Missing target independent instruction");
+ assert(Instr->Namespace == "TargetOpcode" && "Bad namespace");
+ InstrsByEnum.push_back(Instr);
+ }
unsigned EndOfPredefines = InstrsByEnum.size();
-
+
for (DenseMap<const Record*, CodeGenInstruction*>::const_iterator
I = Insts.begin(), E = Insts.end(); I != E; ++I) {
const CodeGenInstruction *CGI = I->second;
- if (CGI != PHI &&
- CGI != INLINEASM &&
- CGI != DBG_LABEL &&
- CGI != EH_LABEL &&
- CGI != GC_LABEL &&
- CGI != KILL &&
- CGI != EXTRACT_SUBREG &&
- CGI != INSERT_SUBREG &&
- CGI != IMPLICIT_DEF &&
- CGI != SUBREG_TO_REG &&
- CGI != COPY_TO_REGCLASS &&
- CGI != DBG_VALUE &&
- CGI != REG_SEQUENCE)
+ if (CGI->Namespace != "TargetOpcode")
InstrsByEnum.push_back(CGI);
}
-
+
+ assert(InstrsByEnum.size() == Insts.size() && "Missing predefined instr");
+
// All of the instructions are now in random order based on the map iteration.
// Sort them by name.
std::sort(InstrsByEnum.begin()+EndOfPredefines, InstrsByEnum.end(),
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