[llvm-branch-commits] [llvm-branch] r107530 - in /llvm/branches/Apple/Morbo: ./ lib/CodeGen/TwoAddressInstructionPass.cpp lib/Target/ARM/ARMInstrFormats.td lib/Target/X86/X86InstrInfo.cpp test/CodeGen/X86/2010-07-02-UnfoldBug.ll
Bill Wendling
isanbard at gmail.com
Fri Jul 2 15:56:34 PDT 2010
Author: void
Date: Fri Jul 2 17:56:34 2010
New Revision: 107530
URL: http://llvm.org/viewvc/llvm-project?rev=107530&view=rev
Log:
$ svn merge -c 107509 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r107509 into '.':
A test/CodeGen/X86/2010-07-02-UnfoldBug.ll
U lib/CodeGen/TwoAddressInstructionPass.cpp
U lib/Target/X86/X86InstrInfo.cpp
Added:
llvm/branches/Apple/Morbo/test/CodeGen/X86/2010-07-02-UnfoldBug.ll
- copied unchanged from r107509, llvm/trunk/test/CodeGen/X86/2010-07-02-UnfoldBug.ll
Modified:
llvm/branches/Apple/Morbo/ (props changed)
llvm/branches/Apple/Morbo/lib/CodeGen/TwoAddressInstructionPass.cpp
llvm/branches/Apple/Morbo/lib/Target/ARM/ARMInstrFormats.td (props changed)
llvm/branches/Apple/Morbo/lib/Target/X86/X86InstrInfo.cpp
Propchange: llvm/branches/Apple/Morbo/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Fri Jul 2 17:56:34 2010
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Hermes:96832,96835,96858,96870,96876,96879,104427,104930,104971
-/llvm/trunk:98602,98604,98612,98615-98616,98675,98686,98743-98744,98768,98773,98778,98780,98810,98835,98839,98845,98855,98862,98881,98920,98977,98980,99032-99033,99043,99196,99223,99263,99282-99284,99306,99319-99321,99324,99336,99378,99418,99423,99429,99440,99455,99463,99465,99469,99484,99490,99492-99494,99507,99524,99537,99539-99540,99544,99570,99575,99598,99620,99629-99630,99636,99671,99692,99695,99697,99699,99722,99816,99835-99836,99845-99846,99848,99850,99855,99879,99881-99883,99895,99899,99910,99916,99919,99952-99954,99957,99959,99974-99975,99982,99984-99986,99988-99989,99992-99993,99995,99997-99999,100016,100035,100037-100038,100042,100044,100056,100072,100074,100078,100081-100090,100092,100094-100095,100116,100134,100184,100209,100214-100218,100220-100221,100223-100225,100231,100250,100252,100257,100261,100304,100332,100353,100384,100454-100455,100457,100466,100478,100480,100487,100494,100497,100505,100521,100553,100568,100584,100592,100609-100610,100636,100710,100736
,100742,100751,100768-100769,100771,100781,100797,100804,100837,100867,100892,100936-100937,101011,101023,101075,101077,101079,101081,101085,101154,101158,101162,101165,101181,101190,101202,101282,101294,101303,101314-101315,101317,101331,101343,101383,101392,101420,101453,101604,101615,101629,101684-101686,101805,101845,101847,101851,101855,101870,101879,101897,101925,101930,101965,101971,101979,102111,102120,102192,102202,102225,102236-102237,102358,102366,102394,102396,102405,102421,102454-102456,102463,102467-102468,102470,102481,102486-102488,102492-102493,102504-102505,102508-102510,102513,102519,102524,102526,102531,102558,102646,102653,102655,102661-102662,102672,102743,102760,102770,102791,102948,102970,102980,103001,103126,103133,103233,103314,103356,103415,103419,103439,103451,103455,103459,103757,103798,103801-103802,103804,103808,103813,103824,103829,103928,103990,103995,104066,104182,104233,104236,104265,104274,104302,104338,104412,104419,104524,104531,104640,1
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+/llvm/trunk:98602,98604,98612,98615-98616,98675,98686,98743-98744,98768,98773,98778,98780,98810,98835,98839,98845,98855,98862,98881,98920,98977,98980,99032-99033,99043,99196,99223,99263,99282-99284,99306,99319-99321,99324,99336,99378,99418,99423,99429,99440,99455,99463,99465,99469,99484,99490,99492-99494,99507,99524,99537,99539-99540,99544,99570,99575,99598,99620,99629-99630,99636,99671,99692,99695,99697,99699,99722,99816,99835-99836,99845-99846,99848,99850,99855,99879,99881-99883,99895,99899,99910,99916,99919,99952-99954,99957,99959,99974-99975,99982,99984-99986,99988-99989,99992-99993,99995,99997-99999,100016,100035,100037-100038,100042,100044,100056,100072,100074,100078,100081-100090,100092,100094-100095,100116,100134,100184,100209,100214-100218,100220-100221,100223-100225,100231,100250,100252,100257,100261,100304,100332,100353,100384,100454-100455,100457,100466,100478,100480,100487,100494,100497,100505,100521,100553,100568,100584,100592,100609-100610,100636,100710,100736
,100742,100751,100768-100769,100771,100781,100797,100804,100837,100867,100892,100936-100937,101011,101023,101075,101077,101079,101081,101085,101154,101158,101162,101165,101181,101190,101202,101282,101294,101303,101314-101315,101317,101331,101343,101383,101392,101420,101453,101604,101615,101629,101684-101686,101805,101845,101847,101851,101855,101870,101879,101897,101925,101930,101965,101971,101979,102111,102120,102192,102202,102225,102236-102237,102358,102366,102394,102396,102405,102421,102454-102456,102463,102467-102468,102470,102481,102486-102488,102492-102493,102504-102505,102508-102510,102513,102519,102524,102526,102531,102558,102646,102653,102655,102661-102662,102672,102743,102760,102770,102791,102948,102970,102980,103001,103126,103133,103233,103314,103356,103415,103419,103439,103451,103455,103459,103757,103798,103801-103802,103804,103808,103813,103824,103829,103928,103990,103995,104066,104182,104233,104236,104265,104274,104302,104338,104412,104419,104524,104531,104640,1
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/llvm-gcc-4.2/trunk:104182
Modified: llvm/branches/Apple/Morbo/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=107530&r1=107529&r2=107530&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/branches/Apple/Morbo/lib/CodeGen/TwoAddressInstructionPass.cpp Fri Jul 2 17:56:34 2010
@@ -913,14 +913,12 @@
UnfoldTID.OpInfo[LoadRegIndex].getRegClass(TRI);
unsigned Reg = MRI->createVirtualRegister(RC);
SmallVector<MachineInstr *, 2> NewMIs;
- bool Success =
- TII->unfoldMemoryOperand(MF, mi, Reg,
- /*UnfoldLoad=*/true, /*UnfoldStore=*/false,
- NewMIs);
- (void)Success;
- assert(Success &&
- "unfoldMemoryOperand failed when getOpcodeAfterMemoryUnfold "
- "succeeded!");
+ if (!TII->unfoldMemoryOperand(MF, mi, Reg,
+ /*UnfoldLoad=*/true,/*UnfoldStore=*/false,
+ NewMIs)) {
+ DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
+ return false;
+ }
assert(NewMIs.size() == 2 &&
"Unfolded a load into multiple instructions!");
// The load was previously folded, so this is the only use.
Propchange: llvm/branches/Apple/Morbo/lib/Target/ARM/ARMInstrFormats.td
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Fri Jul 2 17:56:34 2010
@@ -1,2 +1,2 @@
/llvm/branches/Apple/Hermes/lib/Target/ARM/ARMInstrFormats.td:104930
-/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td:98980,103126,103757,103928,104182,104233,104236,104265,104274,104302,104338,104412,104419,104524,104531,104640,104646,104649,104655-104656,104661,104664,104705-104706,104720,104722,104732,104737,104740,104785,104848,104858,104872,104884,104900,105092,105285,105292,105295,105360,105387,105490,105505,105741,105828-105829,105872,106066,106075,106088,106243-106244,106270,106438-106439,106515-106516,106518,106576,106582,106604,106611-106612,106772,106792,106862,106878,106895,106985,106989-106990,107025,107027,107059,107065,107085,107103,107112,107212,107228,107237,107430,107433,107440
+/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td:98980,103126,103757,103928,104182,104233,104236,104265,104274,104302,104338,104412,104419,104524,104531,104640,104646,104649,104655-104656,104661,104664,104705-104706,104720,104722,104732,104737,104740,104785,104848,104858,104872,104884,104900,105092,105285,105292,105295,105360,105387,105490,105505,105741,105828-105829,105872,106066,106075,106088,106243-106244,106270,106438-106439,106515-106516,106518,106576,106582,106604,106611-106612,106772,106792,106862,106878,106895,106985,106989-106990,107025,107027,107059,107065,107085,107103,107112,107212,107228,107237,107430,107433,107440,107509
Modified: llvm/branches/Apple/Morbo/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/lib/Target/X86/X86InstrInfo.cpp?rev=107530&r1=107529&r2=107530&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/branches/Apple/Morbo/lib/Target/X86/X86InstrInfo.cpp Fri Jul 2 17:56:34 2010
@@ -2143,7 +2143,7 @@
MachineInstr::mmo_iterator MMOBegin,
MachineInstr::mmo_iterator MMOEnd,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
- bool isAligned = (*MMOBegin)->getAlignment() >= 16;
+ bool isAligned = *MMOBegin && (*MMOBegin)->getAlignment() >= 16;
unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
DebugLoc DL;
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
@@ -2238,7 +2238,7 @@
MachineInstr::mmo_iterator MMOBegin,
MachineInstr::mmo_iterator MMOEnd,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
- bool isAligned = (*MMOBegin)->getAlignment() >= 16;
+ bool isAligned = *MMOBegin && (*MMOBegin)->getAlignment() >= 16;
unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
DebugLoc DL;
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
@@ -2743,6 +2743,13 @@
const TargetInstrDesc &TID = get(Opc);
const TargetOperandInfo &TOI = TID.OpInfo[Index];
const TargetRegisterClass *RC = TOI.getRegClass(&RI);
+ if (!MI->hasOneMemOperand() &&
+ RC == &X86::VR128RegClass &&
+ !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
+ // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
+ // conservatively assume the address is unaligned. That's bad for
+ // performance.
+ return false;
SmallVector<MachineOperand, X86AddrNumOperands> AddrOps;
SmallVector<MachineOperand,2> BeforeOps;
SmallVector<MachineOperand,2> AfterOps;
@@ -2878,7 +2885,12 @@
MachineInstr::mmo_iterator> MMOs =
MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
cast<MachineSDNode>(N)->memoperands_end());
- bool isAligned = (*MMOs.first)->getAlignment() >= 16;
+ if (!(*MMOs.first) &&
+ RC == &X86::VR128RegClass &&
+ !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
+ // Do not introduce a slow unaligned load.
+ return false;
+ bool isAligned = (*MMOs.first) && (*MMOs.first)->getAlignment() >= 16;
Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
VT, MVT::Other, &AddrOps[0], AddrOps.size());
NewNodes.push_back(Load);
@@ -2915,7 +2927,12 @@
MachineInstr::mmo_iterator> MMOs =
MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
cast<MachineSDNode>(N)->memoperands_end());
- bool isAligned = (*MMOs.first)->getAlignment() >= 16;
+ if (!(*MMOs.first) &&
+ RC == &X86::VR128RegClass &&
+ !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
+ // Do not introduce a slow unaligned store.
+ return false;
+ bool isAligned = (*MMOs.first) && (*MMOs.first)->getAlignment() >= 16;
SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
isAligned, TM),
dl, MVT::Other,
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