[llvm-branch-commits] [llvm-branch] r107512 - in /llvm/branches/Apple/Troughton: ./ lib/CodeGen/LowerSubregs.cpp lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/Target/ARM/Thumb2InstrInfo.cpp test/CodeGen/ARM/2010-06-28-DAGCombineUndef.ll test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll
Bob Wilson
bob.wilson at apple.com
Fri Jul 2 14:03:53 PDT 2010
Author: bwilson
Date: Fri Jul 2 16:03:53 2010
New Revision: 107512
URL: http://llvm.org/viewvc/llvm-project?rev=107512&view=rev
Log:
Merge some fixes for compiler crashes encountered with the xIsaVectors test
while working on Radar 8110263.
--- Merging r107097 into '.':
A test/CodeGen/ARM/2010-06-28-DAGCombineUndef.ll
U lib/CodeGen/SelectionDAG/DAGCombiner.cpp
--- Merging r107147 into '.':
U lib/Target/ARM/Thumb2InstrInfo.cpp
--- Merging r107189 into '.':
A test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll
U lib/CodeGen/LowerSubregs.cpp
Added:
llvm/branches/Apple/Troughton/test/CodeGen/ARM/2010-06-28-DAGCombineUndef.ll
- copied unchanged from r107097, llvm/trunk/test/CodeGen/ARM/2010-06-28-DAGCombineUndef.ll
llvm/branches/Apple/Troughton/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll
- copied unchanged from r107189, llvm/trunk/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll
Modified:
llvm/branches/Apple/Troughton/ (props changed)
llvm/branches/Apple/Troughton/lib/CodeGen/LowerSubregs.cpp
llvm/branches/Apple/Troughton/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/branches/Apple/Troughton/lib/Target/ARM/Thumb2InstrInfo.cpp
Propchange: llvm/branches/Apple/Troughton/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Fri Jul 2 16:03:53 2010
@@ -1 +1 @@
-/llvm/trunk:105358,105361,105369,105372,105399,105427,105437,105439,105441,105470,105473,105481,105498,105541,105554,105557,105585-105586,105634,105653,105665,105669,105677,105745,105749,105774-105775,105836,105845,105862,105886,105938,105959,105965,105969,105982,105990-105991,105997-105998,106004,106015,106021,106024,106027,106030,106051,106057,106146,106149,106152,106155,106157,106164,106199,106203-106204,106227,106229,106282,106289,106291-106292,106309,106312,106314,106318,106321,106324,106333,106336,106342,106345,106483-106484,106582,106630-106631,106820,107435,107487
+/llvm/trunk:105358,105361,105369,105372,105399,105427,105437,105439,105441,105470,105473,105481,105498,105541,105554,105557,105585-105586,105634,105653,105665,105669,105677,105745,105749,105774-105775,105836,105845,105862,105886,105938,105959,105965,105969,105982,105990-105991,105997-105998,106004,106015,106021,106024,106027,106030,106051,106057,106146,106149,106152,106155,106157,106164,106199,106203-106204,106227,106229,106282,106289,106291-106292,106309,106312,106314,106318,106321,106324,106333,106336,106342,106345,106483-106484,106582,106630-106631,106820,107097,107147,107189,107435,107487
Modified: llvm/branches/Apple/Troughton/lib/CodeGen/LowerSubregs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Troughton/lib/CodeGen/LowerSubregs.cpp?rev=107512&r1=107511&r2=107512&view=diff
==============================================================================
--- llvm/branches/Apple/Troughton/lib/CodeGen/LowerSubregs.cpp (original)
+++ llvm/branches/Apple/Troughton/lib/CodeGen/LowerSubregs.cpp Fri Jul 2 16:03:53 2010
@@ -62,6 +62,7 @@
void TransferKillFlag(MachineInstr *MI, unsigned SrcReg,
const TargetRegisterInfo *TRI,
bool AddIfNotFound = false);
+ void TransferImplicitDefs(MachineInstr *MI);
};
char LowerSubregsInstructionPass::ID = 0;
@@ -104,6 +105,22 @@
}
}
+/// TransferImplicitDefs - MI is a pseudo-instruction, and the lowered
+/// replacement instructions immediately precede it. Copy any implicit-def
+/// operands from MI to the replacement instruction.
+void
+LowerSubregsInstructionPass::TransferImplicitDefs(MachineInstr *MI) {
+ MachineBasicBlock::iterator CopyMI = MI;
+ --CopyMI;
+
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ MachineOperand &MO = MI->getOperand(i);
+ if (!MO.isReg() || !MO.isImplicit() || MO.isUse())
+ continue;
+ CopyMI->addOperand(MachineOperand::CreateReg(MO.getReg(), true, true));
+ }
+}
+
bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
MachineBasicBlock *MBB = MI->getParent();
@@ -149,6 +166,7 @@
TransferDeadFlag(MI, DstReg, TRI);
if (MI->getOperand(1).isKill())
TransferKillFlag(MI, SuperReg, TRI, true);
+ TransferImplicitDefs(MI);
DEBUG({
MachineBasicBlock::iterator dMI = MI;
dbgs() << "subreg: " << *(--dMI);
Modified: llvm/branches/Apple/Troughton/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Troughton/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=107512&r1=107511&r2=107512&view=diff
==============================================================================
--- llvm/branches/Apple/Troughton/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/branches/Apple/Troughton/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Jul 2 16:03:53 2010
@@ -2319,7 +2319,8 @@
}
// fold (or x, undef) -> -1
- if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) {
+ if (!LegalOperations &&
+ (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
}
Modified: llvm/branches/Apple/Troughton/lib/Target/ARM/Thumb2InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Troughton/lib/Target/ARM/Thumb2InstrInfo.cpp?rev=107512&r1=107511&r2=107512&view=diff
==============================================================================
--- llvm/branches/Apple/Troughton/lib/Target/ARM/Thumb2InstrInfo.cpp (original)
+++ llvm/branches/Apple/Troughton/lib/Target/ARM/Thumb2InstrInfo.cpp Fri Jul 2 16:03:53 2010
@@ -199,14 +199,14 @@
// Use a movw to materialize the 16-bit constant.
BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
.addImm(NumBytes)
- .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
+ .addImm((unsigned)Pred).addReg(PredReg);
Fits = true;
} else if ((NumBytes & 0xffff) == 0) {
// Use a movt to materialize the 32-bit constant.
BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
.addReg(DestReg)
.addImm(NumBytes >> 16)
- .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
+ .addImm((unsigned)Pred).addReg(PredReg);
Fits = true;
}
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