[llvm-branch-commits] [llvm-branch] r93675 - /llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMISelDAGToDAG.cpp

[Bob Wilson]

Author: bwilson
Date: Sat Jan 16 23:59:59 2010
New Revision: 93675

URL: http://llvm.org/viewvc/llvm-project?rev=93675&view=rev
Log:
--- Merging r93673 into '.':
U    lib/Target/ARM/ARMISelDAGToDAG.cpp

Modified:
    llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMISelDAGToDAG.cpp

Modified: llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=93675&r1=93674&r2=93675&view=diff

==============================================================================
--- llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMISelDAGToDAG.cpp Sat Jan 16 23:59:59 2010
@@ -1288,12 +1288,12 @@
   Ops.push_back(Chain);
 
   if (!IsLoad)
-    return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+7);
+    return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+8);
 
   std::vector<EVT> ResTys(NumVecs, RegVT);
   ResTys.push_back(MVT::Other);
   SDNode *VLdLn =
-    CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), NumVecs+7);
+    CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), NumVecs+8);
   // For a 64-bit vector load to D registers, nothing more needs to be done.
   if (is64BitVector)
     return VLdLn;