[llvm-branch-commits] [llvm-branch] r93460 - in /llvm/branches/Apple/Zoidberg/lib: CodeGen/LLVMTargetMachine.cpp Target/ARM/ARMBaseRegisterInfo.cpp

[Jim Grosbach]

Author: grosbach
Date: Thu Jan 14 15:43:53 2010
New Revision: 93460

URL: http://llvm.org/viewvc/llvm-project?rev=93460&view=rev
Log:
Merge 93456 93459

Modified:
    llvm/branches/Apple/Zoidberg/lib/CodeGen/LLVMTargetMachine.cpp
    llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMBaseRegisterInfo.cpp

Modified: llvm/branches/Apple/Zoidberg/lib/CodeGen/LLVMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/lib/CodeGen/LLVMTargetMachine.cpp?rev=93460&r1=93459&r2=93460&view=diff

==============================================================================
--- llvm/branches/Apple/Zoidberg/lib/CodeGen/LLVMTargetMachine.cpp (original)
+++ llvm/branches/Apple/Zoidberg/lib/CodeGen/LLVMTargetMachine.cpp Thu Jan 14 15:43:53 2010
@@ -240,8 +240,13 @@
   {
   case ExceptionHandling::SjLj:
     // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
-    PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
+    // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
+    // catch info can get misplaced when a selector ends up more than one block
+    // removed from the parent invoke(s). This could happen when a landing
+    // pad is shared by multiple invokes and is also a target of a normal
+    // edge from elsewhere.
     PM.add(createSjLjEHPass(getTargetLowering()));
+    PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
     break;
   case ExceptionHandling::Dwarf:
     PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));

Modified: llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMBaseRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=93460&r1=93459&r2=93460&view=diff

==============================================================================
--- llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
+++ llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMBaseRegisterInfo.cpp Thu Jan 14 15:43:53 2010
@@ -217,7 +217,8 @@
     ? DarwinCalleeSavedRegClasses : CalleeSavedRegClasses;
 }
 
-BitVector ARMBaseRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
+BitVector ARMBaseRegisterInfo::
+getReservedRegs(const MachineFunction &MF) const {
   // FIXME: avoid re-calculating this everytime.
   BitVector Reserved(getNumRegs());
   Reserved.set(ARM::SP);
@@ -494,7 +495,8 @@
           !MFI->hasVarSizedObjects());
 }
 
-bool ARMBaseRegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const {
+bool ARMBaseRegisterInfo::
+cannotEliminateFrame(const MachineFunction &MF) const {
   const MachineFrameInfo *MFI = MF.getFrameInfo();
   if (NoFramePointerElim && MFI->hasCalls())
     return true;
@@ -560,7 +562,7 @@
 
 void
 ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
-                                                          RegScavenger *RS) const {
+                                                       RegScavenger *RS) const {
   // This tells PEI to spill the FP as if it is any other callee-save register
   // to take advantage the eliminateFrameIndex machinery. This also ensures it
   // is spilled in the order specified by getCalleeSavedRegs() to make it easier
@@ -848,7 +850,7 @@
 }
 
 unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
-                                               const MachineFunction &MF) const {
+                                              const MachineFunction &MF) const {
   switch (Reg) {
   default: break;
   // Return 0 if either register of the pair is a special register.