[llvm-branch-commits] [llvm-branch] r93034 - in /llvm/branches/Apple/Leela-M1: lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrInfo.td test/CodeGen/X86/2010-01-08-Atomic64Bug.ll

[Stuart Hastings]

Author: stuart
Date: Fri Jan  8 18:55:21 2010
New Revision: 93034

URL: http://llvm.org/viewvc/llvm-project?rev=93034&view=rev
Log:
Backport 92985, 93020, 93028 from trunk to M1 branch.

Added:
    llvm/branches/Apple/Leela-M1/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll
Modified:
    llvm/branches/Apple/Leela-M1/lib/Target/X86/X86ISelLowering.cpp
    llvm/branches/Apple/Leela-M1/lib/Target/X86/X86InstrInfo.td

Modified: llvm/branches/Apple/Leela-M1/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela-M1/lib/Target/X86/X86ISelLowering.cpp?rev=93034&r1=93033&r2=93034&view=diff

==============================================================================
--- llvm/branches/Apple/Leela-M1/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/Apple/Leela-M1/lib/Target/X86/X86ISelLowering.cpp Fri Jan  8 18:55:21 2010
@@ -7581,7 +7581,7 @@
   for (int i=0; i < 2 + X86AddrNumOperands; ++i)
     argOpers[i] = &bInstr->getOperand(i+2);
 
-  // x86 address has 4 operands: base, index, scale, and displacement
+  // x86 address has 5 operands: base, index, scale, displacement, and segment.
   int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
 
   unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
@@ -7609,14 +7609,16 @@
   BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
     .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
 
-  unsigned tt1 = F->getRegInfo().createVirtualRegister(RC);
-  unsigned tt2 = F->getRegInfo().createVirtualRegister(RC);
+  // The subsequent operations should be using the destination registers of
+  //the PHI instructions.
   if (invSrc) {
-    MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt1).addReg(t1);
-    MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt2).addReg(t2);
+    t1 = F->getRegInfo().createVirtualRegister(RC);
+    t2 = F->getRegInfo().createVirtualRegister(RC);
+    MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
+    MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
   } else {
-    tt1 = t1;
-    tt2 = t2;
+    t1 = dest1Oper.getReg();
+    t2 = dest2Oper.getReg();
   }
 
   int valArgIndx = lastAddrIndx + 1;
@@ -7630,7 +7632,7 @@
   else
     MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
   if (regOpcL != X86::MOV32rr)
-    MIB.addReg(tt1);
+    MIB.addReg(t1);
   (*MIB).addOperand(*argOpers[valArgIndx]);
   assert(argOpers[valArgIndx + 1]->isReg() ==
          argOpers[valArgIndx]->isReg());
@@ -7641,7 +7643,7 @@
   else
     MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
   if (regOpcH != X86::MOV32rr)
-    MIB.addReg(tt2);
+    MIB.addReg(t2);
   (*MIB).addOperand(*argOpers[valArgIndx + 1]);
 
   MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX);

Modified: llvm/branches/Apple/Leela-M1/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela-M1/lib/Target/X86/X86InstrInfo.td?rev=93034&r1=93033&r2=93034&view=diff

==============================================================================
--- llvm/branches/Apple/Leela-M1/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/branches/Apple/Leela-M1/lib/Target/X86/X86InstrInfo.td Fri Jan  8 18:55:21 2010
@@ -3553,7 +3553,7 @@
                [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
 }
 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
-def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i32mem:$ptr),
+def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
                "lock\n\t"
                "cmpxchg8b\t$ptr",
                [(X86cas8 addr:$ptr)]>, TB, LOCK;

Added: llvm/branches/Apple/Leela-M1/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela-M1/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll?rev=93034&view=auto

==============================================================================
--- llvm/branches/Apple/Leela-M1/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll (added)
+++ llvm/branches/Apple/Leela-M1/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll Fri Jan  8 18:55:21 2010
@@ -0,0 +1,29 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s
+; rdar://r7512579
+
+; PHI defs in the atomic loop should be used by the add / adc
+; instructions. They should not be dead.
+
+define void @t(i64* nocapture %p) nounwind ssp {
+entry:
+; CHECK: t:
+; CHECK: movl $1
+; CHECK: movl (%ebp), %eax
+; CHECK: movl 4(%ebp), %edx
+; CHECK: LBB1_1:
+; CHECK-NOT: movl $1
+; CHECK-NOT: movl $0
+; CHECK: addl
+; CHECK: adcl
+; CHECK: lock
+; CHECK: cmpxchg8b
+; CHECK: jne
+  tail call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true)
+  %0 = tail call i64 @llvm.atomic.load.add.i64.p0i64(i64* %p, i64 1) ; <i64> [#uses=0]
+  tail call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true)
+  ret void
+}
+
+declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind
+
+declare i64 @llvm.atomic.load.add.i64.p0i64(i64* nocapture, i64) nounwind