[llvm-branch-commits] [llvm-branch] r92945 - in /llvm/branches/Apple/Zoidberg: lib/CodeGen/SelectionDAG/TargetLowering.cpp test/CodeGen/Generic/2009-04-28-i128-cmp-crash.ll
Evan Cheng
evan.cheng at apple.com
Thu Jan 7 13:08:34 PST 2010
Author: evancheng
Date: Thu Jan 7 15:08:33 2010
New Revision: 92945
URL: http://llvm.org/viewvc/llvm-project?rev=92945&view=rev
Log:
Merge 92943.
Modified:
llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/branches/Apple/Zoidberg/test/CodeGen/Generic/2009-04-28-i128-cmp-crash.ll
Modified: llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=92945&r1=92944&r2=92945&view=diff
==============================================================================
--- llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/TargetLowering.cpp Thu Jan 7 15:08:33 2010
@@ -1593,7 +1593,8 @@
if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
N0.getOperand(0).getOpcode() == ISD::CTLZ &&
N0.getOperand(1).getOpcode() == ISD::Constant) {
- unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
+ const APInt &ShAmt
+ = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
if ((C1 == 0) == (Cond == ISD::SETEQ)) {
@@ -1621,27 +1622,26 @@
N0.getOperand(0).getNode()->hasOneUse() &&
isa<ConstantSDNode>(N0.getOperand(1))) {
LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
- uint64_t bestMask = 0;
+ APInt bestMask;
unsigned bestWidth = 0, bestOffset = 0;
- if (!Lod->isVolatile() && Lod->isUnindexed() &&
- // FIXME: This uses getZExtValue() below so it only works on i64 and
- // below.
- N0.getValueType().getSizeInBits() <= 64) {
+ if (!Lod->isVolatile() && Lod->isUnindexed()) {
unsigned origWidth = N0.getValueType().getSizeInBits();
+ unsigned maskWidth = origWidth;
// We can narrow (e.g.) 16-bit extending loads on 32-bit target to
// 8 bits, but have to be careful...
if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
origWidth = Lod->getMemoryVT().getSizeInBits();
- uint64_t Mask =cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
+ const APInt &Mask =
+ cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
for (unsigned width = origWidth / 2; width>=8; width /= 2) {
- uint64_t newMask = (1ULL << width) - 1;
+ APInt newMask = APInt::getLowBitsSet(maskWidth, width);
for (unsigned offset=0; offset<origWidth/width; offset++) {
if ((newMask & Mask) == Mask) {
if (!TD->isLittleEndian())
bestOffset = (origWidth/width - offset - 1) * (width/8);
else
bestOffset = (uint64_t)offset * (width/8);
- bestMask = Mask >> (offset * (width/8) * 8);
+ bestMask = Mask.lshr(offset * (width/8) * 8);
bestWidth = width;
break;
}
@@ -1664,7 +1664,8 @@
false, NewAlign);
return DAG.getSetCC(dl, VT,
DAG.getNode(ISD::AND, dl, newVT, NewLoad,
- DAG.getConstant(bestMask, newVT)),
+ DAG.getConstant(bestMask.trunc(bestWidth),
+ newVT)),
DAG.getConstant(0LL, newVT), Cond);
}
}
@@ -1756,7 +1757,7 @@
// SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
if (N0.getOpcode() == ISD::SETCC) {
- bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getZExtValue() != 1);
+ bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
if (TrueWhenTrue)
return N0;
@@ -1881,13 +1882,12 @@
getPointerTy() : getShiftAmountTy();
if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
// Perform the xform if the AND RHS is a single bit.
- if (isPowerOf2_64(AndRHS->getZExtValue())) {
+ if (AndRHS->getAPIntValue().isPowerOf2()) {
return DAG.getNode(ISD::TRUNCATE, dl, VT,
DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
- DAG.getConstant(Log2_64(AndRHS->getZExtValue()),
- ShiftTy)));
+ DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
}
- } else if (Cond == ISD::SETEQ && C1 == AndRHS->getZExtValue()) {
+ } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
// (X & 8) == 8 --> (X & 8) >> 3
// Perform the xform if C1 is a single bit.
if (C1.isPowerOf2()) {
Modified: llvm/branches/Apple/Zoidberg/test/CodeGen/Generic/2009-04-28-i128-cmp-crash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/test/CodeGen/Generic/2009-04-28-i128-cmp-crash.ll?rev=92945&r1=92944&r2=92945&view=diff
==============================================================================
--- llvm/branches/Apple/Zoidberg/test/CodeGen/Generic/2009-04-28-i128-cmp-crash.ll (original)
+++ llvm/branches/Apple/Zoidberg/test/CodeGen/Generic/2009-04-28-i128-cmp-crash.ll Thu Jan 7 15:08:33 2010
@@ -1,5 +1,7 @@
; RUN: llc < %s
; rdar://6836460
+; rdar://7516906
+; PR5963
define i32 @test(i128* %P) nounwind {
entry:
@@ -14,3 +16,17 @@
if.end61: ; preds = %if.then50, %if.then20, %entry
ret i32 123
}
+
+define i32 @test2(i320* %P) nounwind {
+entry:
+ %tmp48 = load i320* %P
+ %and49 = and i320 %tmp48, 25108406941546723055343157692830665664409421777856138051584
+ %tobool = icmp ne i320 %and49, 0 ; <i1> [#uses=1]
+ br i1 %tobool, label %if.then50, label %if.end61
+
+if.then50: ; preds = %if.then20
+ ret i32 1241
+
+if.end61: ; preds = %if.then50, %if.then20, %entry
+ ret i32 123
+}
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