[llvm-branch-commits] [llvm-branch] r92847 - in /llvm/branches/Apple/Zoidberg: include/llvm/CodeGen/MachineInstr.h lib/CodeGen/MachineInstr.cpp lib/CodeGen/VirtRegRewriter.cpp
Jakob Stoklund Olesen
stoklund at 2pi.dk
Wed Jan 6 10:25:21 PST 2010
Author: stoklund
Date: Wed Jan 6 12:25:21 2010
New Revision: 92847
URL: http://llvm.org/viewvc/llvm-project?rev=92847&view=rev
Log:
Merge r92812 VirtRegRewriter
Modified:
llvm/branches/Apple/Zoidberg/include/llvm/CodeGen/MachineInstr.h
llvm/branches/Apple/Zoidberg/lib/CodeGen/MachineInstr.cpp
llvm/branches/Apple/Zoidberg/lib/CodeGen/VirtRegRewriter.cpp
Modified: llvm/branches/Apple/Zoidberg/include/llvm/CodeGen/MachineInstr.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/include/llvm/CodeGen/MachineInstr.h?rev=92847&r1=92846&r2=92847&view=diff
==============================================================================
--- llvm/branches/Apple/Zoidberg/include/llvm/CodeGen/MachineInstr.h (original)
+++ llvm/branches/Apple/Zoidberg/include/llvm/CodeGen/MachineInstr.h Wed Jan 6 12:25:21 2010
@@ -288,7 +288,7 @@
bool addRegisterKilled(unsigned IncomingReg,
const TargetRegisterInfo *RegInfo,
bool AddIfNotFound = false);
-
+
/// addRegisterDead - We have determined MI defined a register without a use.
/// Look for the operand that defines it and mark it as IsDead. If
/// AddIfNotFound is true, add a implicit operand if it's not found. Returns
@@ -296,6 +296,11 @@
bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
bool AddIfNotFound = false);
+ /// addRegisterDefined - We have determined MI defines a register. Make sure
+ /// there is an operand defining Reg.
+ void addRegisterDefined(unsigned IncomingReg,
+ const TargetRegisterInfo *RegInfo);
+
/// isSafeToMove - Return true if it is safe to move this instruction. If
/// SawStore is set to true, it means that there is a store (or call) between
/// the instruction's location and its intended destination.
Modified: llvm/branches/Apple/Zoidberg/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/lib/CodeGen/MachineInstr.cpp?rev=92847&r1=92846&r2=92847&view=diff
==============================================================================
--- llvm/branches/Apple/Zoidberg/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/branches/Apple/Zoidberg/lib/CodeGen/MachineInstr.cpp Wed Jan 6 12:25:21 2010
@@ -1306,3 +1306,12 @@
true /*IsDead*/));
return true;
}
+
+void MachineInstr::addRegisterDefined(unsigned IncomingReg,
+ const TargetRegisterInfo *RegInfo) {
+ MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo);
+ if (!MO || MO->getSubReg())
+ addOperand(MachineOperand::CreateReg(IncomingReg,
+ true /*IsDef*/,
+ true /*IsImp*/));
+}
Modified: llvm/branches/Apple/Zoidberg/lib/CodeGen/VirtRegRewriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/lib/CodeGen/VirtRegRewriter.cpp?rev=92847&r1=92846&r2=92847&view=diff
==============================================================================
--- llvm/branches/Apple/Zoidberg/lib/CodeGen/VirtRegRewriter.cpp (original)
+++ llvm/branches/Apple/Zoidberg/lib/CodeGen/VirtRegRewriter.cpp Wed Jan 6 12:25:21 2010
@@ -60,6 +60,33 @@
VirtRegRewriter::~VirtRegRewriter() {}
+/// substitutePhysReg - Replace virtual register in MachineOperand with a
+/// physical register. Do the right thing with the sub-register index.
+static void substitutePhysReg(MachineOperand &MO, unsigned Reg,
+ const TargetRegisterInfo &TRI) {
+ if (unsigned SubIdx = MO.getSubReg()) {
+ // Insert the physical subreg and reset the subreg field.
+ MO.setReg(TRI.getSubReg(Reg, SubIdx));
+ MO.setSubReg(0);
+
+ // Any def, dead, and kill flags apply to the full virtual register, so they
+ // also apply to the full physical register. Add imp-def/dead and imp-kill
+ // as needed.
+ MachineInstr &MI = *MO.getParent();
+ if (MO.isDef())
+ if (MO.isDead())
+ MI.addRegisterDead(Reg, &TRI, /*AddIfNotFound=*/ true);
+ else
+ MI.addRegisterDefined(Reg, &TRI);
+ else if (!MO.isUndef() &&
+ (MO.isKill() ||
+ MI.isRegTiedToDefOperand(&MO-&MI.getOperand(0))))
+ MI.addRegisterKilled(Reg, &TRI, /*AddIfNotFound=*/ true);
+ } else {
+ MO.setReg(Reg);
+ }
+}
+
namespace {
/// This class is intended for use with the new spilling framework only. It
@@ -101,10 +128,7 @@
MachineOperand &mop = regItr.getOperand();
assert(mop.isReg() && mop.getReg() == reg && "reg_iterator broken?");
++regItr;
- unsigned subRegIdx = mop.getSubReg();
- unsigned pRegOp = subRegIdx ? tri->getSubReg(pReg, subRegIdx) : pReg;
- mop.setReg(pRegOp);
- mop.setSubReg(0);
+ substitutePhysReg(mop, pReg, *tri);
changed = true;
}
}
@@ -647,12 +671,9 @@
if (TargetRegisterInfo::isPhysicalRegister(VirtReg))
continue;
assert(MO.isUse());
- unsigned SubIdx = MO.getSubReg();
unsigned Phys = VRM.getPhys(VirtReg);
assert(Phys && "Virtual register is not assigned a register?");
- unsigned RReg = SubIdx ? TRI->getSubReg(Phys, SubIdx) : Phys;
- MO.setReg(RReg);
- MO.setSubReg(0);
+ substitutePhysReg(MO, Phys, *TRI);
}
++NumReMats;
}
@@ -1004,11 +1025,12 @@
}
static
-void AssignPhysToVirtReg(MachineInstr *MI, unsigned VirtReg, unsigned PhysReg) {
+void AssignPhysToVirtReg(MachineInstr *MI, unsigned VirtReg, unsigned PhysReg,
+ const TargetRegisterInfo &TRI) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (MO.isReg() && MO.getReg() == VirtReg)
- MO.setReg(PhysReg);
+ substitutePhysReg(MO, PhysReg, TRI);
}
}
@@ -1175,7 +1197,7 @@
if (!TII->unfoldMemoryOperand(MF, &MI, VirtReg, false, false, NewMIs))
llvm_unreachable("Unable unfold the load / store folding instruction!");
assert(NewMIs.size() == 1);
- AssignPhysToVirtReg(NewMIs[0], VirtReg, PhysReg);
+ AssignPhysToVirtReg(NewMIs[0], VirtReg, PhysReg, *TRI);
VRM.transferRestorePts(&MI, NewMIs[0]);
MII = MBB.insert(MII, NewMIs[0]);
InvalidateKills(MI, TRI, RegKills, KillOps);
@@ -1191,7 +1213,7 @@
if (!TII->unfoldMemoryOperand(MF, &NextMI, VirtReg, false, false, NewMIs))
llvm_unreachable("Unable unfold the load / store folding instruction!");
assert(NewMIs.size() == 1);
- AssignPhysToVirtReg(NewMIs[0], VirtReg, PhysReg);
+ AssignPhysToVirtReg(NewMIs[0], VirtReg, PhysReg, *TRI);
VRM.transferRestorePts(&NextMI, NewMIs[0]);
MBB.insert(NextMII, NewMIs[0]);
InvalidateKills(NextMI, TRI, RegKills, KillOps);
@@ -1840,16 +1862,14 @@
RegInfo->setPhysRegUsed(Phys);
if (MO.isDef())
ReusedOperands.markClobbered(Phys);
- unsigned RReg = SubIdx ? TRI->getSubReg(Phys, SubIdx) : Phys;
- MI.getOperand(i).setReg(RReg);
- MI.getOperand(i).setSubReg(0);
+ substitutePhysReg(MO, Phys, *TRI);
if (VRM.isImplicitlyDefined(VirtReg))
// FIXME: Is this needed?
BuildMI(MBB, &MI, MI.getDebugLoc(),
- TII->get(TargetInstrInfo::IMPLICIT_DEF), RReg);
+ TII->get(TargetInstrInfo::IMPLICIT_DEF), Phys);
continue;
}
-
+
// This virtual register is now known to be a spilled value.
if (!MO.isUse())
continue; // Handle defs in the loop below (handle use&def here though)
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