[llvm-branch-commits] [llvm-branch] r96414 - in /llvm/branches/Apple/Hermes: lib/Target/PowerPC/PPCRegisterInfo.td test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll test/CodeGen/PowerPC/LargeAbsoluteAddr.ll test/CodeGen/PowerPC/indirectbr.ll
Dale Johannesen
dalej at apple.com
Tue Feb 16 15:56:56 PST 2010
Author: johannes
Date: Tue Feb 16 17:56:39 2010
New Revision: 96414
URL: http://llvm.org/viewvc/llvm-project?rev=96414&view=rev
Log:
--- Merging r96399 into '.':
U lib/Target/PowerPC/PPCRegisterInfo.td
--- Merging r96407 into '.':
U test/CodeGen/PowerPC/LargeAbsoluteAddr.ll
U test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll
U test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll
U test/CodeGen/PowerPC/indirectbr.ll
--- Merging r96413 into '.':
G test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll
Modified:
llvm/branches/Apple/Hermes/lib/Target/PowerPC/PPCRegisterInfo.td
llvm/branches/Apple/Hermes/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll
llvm/branches/Apple/Hermes/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll
llvm/branches/Apple/Hermes/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll
llvm/branches/Apple/Hermes/test/CodeGen/PowerPC/indirectbr.ll
Modified: llvm/branches/Apple/Hermes/lib/Target/PowerPC/PPCRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Hermes/lib/Target/PowerPC/PPCRegisterInfo.td?rev=96414&r1=96413&r2=96414&view=diff
==============================================================================
--- llvm/branches/Apple/Hermes/lib/Target/PowerPC/PPCRegisterInfo.td (original)
+++ llvm/branches/Apple/Hermes/lib/Target/PowerPC/PPCRegisterInfo.td Tue Feb 16 17:56:39 2010
@@ -287,10 +287,8 @@
GPRCClass::allocation_order_begin(const MachineFunction &MF) const {
// 32-bit SVR4 ABI: r2 is reserved for the OS.
// 64-bit SVR4 ABI: r2 is reserved for the TOC pointer.
- if (!MF.getTarget().getSubtarget<PPCSubtarget>().isDarwin())
- return begin()+1;
-
- return begin();
+ // Darwin: R2 is reserved for CR save/restore sequence.
+ return begin()+1;
}
GPRCClass::iterator
GPRCClass::allocation_order_end(const MachineFunction &MF) const {
@@ -325,10 +323,8 @@
G8RCClass::iterator
G8RCClass::allocation_order_begin(const MachineFunction &MF) const {
// 64-bit SVR4 ABI: r2 is reserved for the TOC pointer.
- if (!MF.getTarget().getSubtarget<PPCSubtarget>().isDarwin())
- return begin()+1;
-
- return begin();
+ // Darwin: r2 is reserved for CR save/restore sequence.
+ return begin()+1;
}
G8RCClass::iterator
G8RCClass::allocation_order_end(const MachineFunction &MF) const {
Modified: llvm/branches/Apple/Hermes/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Hermes/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll?rev=96414&r1=96413&r2=96414&view=diff
==============================================================================
--- llvm/branches/Apple/Hermes/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll (original)
+++ llvm/branches/Apple/Hermes/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll Tue Feb 16 17:56:39 2010
@@ -1,6 +1,6 @@
; RUN: llc < %s | grep {subfc r3,r5,r4}
-; RUN: llc < %s | grep {subfze r4,r2}
-; RUN: llc < %s -regalloc=local | grep {subfc r2,r5,r4}
+; RUN: llc < %s | grep {subfze r4,r6}
+; RUN: llc < %s -regalloc=local | grep {subfc r6,r5,r4}
; RUN: llc < %s -regalloc=local | grep {subfze r3,r3}
; The first argument of subfc must not be the same as any other register.
Modified: llvm/branches/Apple/Hermes/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Hermes/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll?rev=96414&r1=96413&r2=96414&view=diff
==============================================================================
--- llvm/branches/Apple/Hermes/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll (original)
+++ llvm/branches/Apple/Hermes/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll Tue Feb 16 17:56:39 2010
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=ppc32 | FileCheck %s
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin10 -mcpu=g5 | FileCheck %s
; ModuleID = '<stdin>'
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
target triple = "powerpc-apple-darwin10.0"
@@ -10,8 +10,8 @@
define void @foo(i32 %y) nounwind ssp {
entry:
; CHECK: foo
-; CHECK: add r2
-; CHECK: 0(r2)
+; CHECK: add r4
+; CHECK: 0(r4)
%y_addr = alloca i32 ; <i32*> [#uses=2]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
store i32 %y, i32* %y_addr
Modified: llvm/branches/Apple/Hermes/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Hermes/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll?rev=96414&r1=96413&r2=96414&view=diff
==============================================================================
--- llvm/branches/Apple/Hermes/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll (original)
+++ llvm/branches/Apple/Hermes/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll Tue Feb 16 17:56:39 2010
@@ -1,9 +1,9 @@
; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin | \
-; RUN: grep {stw r3, 32751}
+; RUN: grep {stw r4, 32751}
; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin | \
-; RUN: grep {stw r3, 32751}
+; RUN: grep {stw r4, 32751}
; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin | \
-; RUN: grep {std r2, 9024}
+; RUN: grep {std r3, 9024}
define void @test() {
store i32 0, i32* inttoptr (i64 48725999 to i32*)
Modified: llvm/branches/Apple/Hermes/test/CodeGen/PowerPC/indirectbr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Hermes/test/CodeGen/PowerPC/indirectbr.ll?rev=96414&r1=96413&r2=96414&view=diff
==============================================================================
--- llvm/branches/Apple/Hermes/test/CodeGen/PowerPC/indirectbr.ll (original)
+++ llvm/branches/Apple/Hermes/test/CodeGen/PowerPC/indirectbr.ll Tue Feb 16 17:56:39 2010
@@ -43,13 +43,13 @@
L1: ; preds = %L2, %bb2
%res.3 = phi i32 [ %phitmp, %L2 ], [ 2, %bb2 ] ; <i32> [#uses=1]
-; PIC: addis r4, r2, ha16(L_BA4__foo_L5-"L1$pb")
-; PIC: li r5, lo16(L_BA4__foo_L5-"L1$pb")
-; PIC: add r4, r4, r5
-; PIC: stw r4
-; STATIC: li r2, lo16(L_BA4__foo_L5)
-; STATIC: addis r2, r2, ha16(L_BA4__foo_L5)
-; STATIC: stw r2
+; PIC: addis r5, r4, ha16(L_BA4__foo_L5-"L1$pb")
+; PIC: li r6, lo16(L_BA4__foo_L5-"L1$pb")
+; PIC: add r5, r5, r6
+; PIC: stw r5
+; STATIC: li r4, lo16(L_BA4__foo_L5)
+; STATIC: addis r4, r4, ha16(L_BA4__foo_L5)
+; STATIC: stw r4
store i8* blockaddress(@foo, %L5), i8** @nextaddr, align 4
ret i32 %res.3
}
More information about the llvm-branch-commits
mailing list