[llvm-branch-commits] [llvm-branch] r95411 - in /llvm/branches/Apple/Zoidberg: lib/Target/ARM/ARMBaseRegisterInfo.cpp test/CodeGen/Thumb2/large-stack.ll test/CodeGen/Thumb2/thumb2-spill-q.ll
Bob Wilson
bob.wilson at apple.com
Fri Feb 5 11:24:33 PST 2010
Author: bwilson
Date: Fri Feb 5 13:24:32 2010
New Revision: 95411
URL: http://llvm.org/viewvc/llvm-project?rev=95411&view=rev
Log:
--- Merging r90724 into '.':
U test/CodeGen/Thumb2/thumb2-spill-q.ll
U test/CodeGen/Thumb2/large-stack.ll
U lib/Target/ARM/ARMBaseRegisterInfo.cpp
Modified:
llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMBaseRegisterInfo.cpp
llvm/branches/Apple/Zoidberg/test/CodeGen/Thumb2/large-stack.ll
llvm/branches/Apple/Zoidberg/test/CodeGen/Thumb2/thumb2-spill-q.ll
Modified: llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMBaseRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=95411&r1=95410&r2=95411&view=diff
==============================================================================
--- llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
+++ llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMBaseRegisterInfo.cpp Fri Feb 5 13:24:32 2010
@@ -591,6 +591,13 @@
MFI->calculateMaxStackAlignment();
}
+ // Spill R4 if Thumb2 function requires stack realignment - it will be used as
+ // scratch register.
+ // FIXME: It will be better just to find spare register here.
+ if (needsStackRealignment(MF) &&
+ AFI->isThumb2Function())
+ MF.getRegInfo().setPhysRegUsed(ARM::R4);
+
// Don't spill FP if the frame can be eliminated. This is determined
// by scanning the callee-save registers to see if any is used.
const unsigned *CSRegs = getCalleeSavedRegs();
@@ -1364,14 +1371,30 @@
// If we need dynamic stack realignment, do it here.
if (needsStackRealignment(MF)) {
- unsigned Opc;
unsigned MaxAlign = MFI->getMaxAlignment();
assert (!AFI->isThumb1OnlyFunction());
- Opc = AFI->isThumbFunction() ? ARM::t2BICri : ARM::BICri;
-
- AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), ARM::SP)
+ if (!AFI->isThumbFunction()) {
+ // Emit bic sp, sp, MaxAlign
+ AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
+ TII.get(ARM::BICri), ARM::SP)
.addReg(ARM::SP, RegState::Kill)
.addImm(MaxAlign-1)));
+ } else {
+ // We cannot use sp as source/dest register here, thus we're emitting the
+ // following sequence:
+ // mov r4, sp
+ // bic r4, r4, MaxAlign
+ // mov sp, r4
+ // FIXME: It will be better just to find spare register here.
+ BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::R4)
+ .addReg(ARM::SP, RegState::Kill);
+ AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
+ TII.get(ARM::t2BICri), ARM::R4)
+ .addReg(ARM::R4, RegState::Kill)
+ .addImm(MaxAlign-1)));
+ BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
+ .addReg(ARM::R4, RegState::Kill);
+ }
}
}
Modified: llvm/branches/Apple/Zoidberg/test/CodeGen/Thumb2/large-stack.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/test/CodeGen/Thumb2/large-stack.ll?rev=95411&r1=95410&r2=95411&view=diff
==============================================================================
--- llvm/branches/Apple/Zoidberg/test/CodeGen/Thumb2/large-stack.ll (original)
+++ llvm/branches/Apple/Zoidberg/test/CodeGen/Thumb2/large-stack.ll Fri Feb 5 13:24:32 2010
@@ -18,7 +18,7 @@
define i32 @test3() {
; CHECK: test3:
; CHECK: sub.w sp, sp, #805306368
-; CHECK: sub sp, #24
+; CHECK: sub sp, #20
%retval = alloca i32, align 4
%tmp = alloca i32, align 4
%a = alloca [805306369 x i8], align 16
Modified: llvm/branches/Apple/Zoidberg/test/CodeGen/Thumb2/thumb2-spill-q.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/test/CodeGen/Thumb2/thumb2-spill-q.ll?rev=95411&r1=95410&r2=95411&view=diff
==============================================================================
--- llvm/branches/Apple/Zoidberg/test/CodeGen/Thumb2/thumb2-spill-q.ll (original)
+++ llvm/branches/Apple/Zoidberg/test/CodeGen/Thumb2/thumb2-spill-q.ll Fri Feb 5 13:24:32 2010
@@ -11,7 +11,7 @@
define arm_apcscc void @aaa(%quuz* %this, i8* %block) {
; CHECK: aaa:
-; CHECK: bic sp, sp, #15
+; CHECK: bic r4, r4, #15
; CHECK: vst1.64 {{.*}}sp, :128
; CHECK: vld1.64 {{.*}}sp, :128
entry:
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