[llvm-branch-commits] [llvm-branch] r101025 - in /llvm/branches/Apple/Morbo: ./ include/llvm/CodeGen/Passes.h lib/CodeGen/LLVMTargetMachine.cpp lib/CodeGen/MachineLICM.cpp lib/Transforms/IPO/FunctionAttrs.cpp test/CodeGen/X86/postra-licm.ll
Evan Cheng
evan.cheng at apple.com
Sun Apr 11 23:35:32 PDT 2010
Author: evancheng
Date: Mon Apr 12 01:35:31 2010
New Revision: 101025
URL: http://llvm.org/viewvc/llvm-project?rev=101025&view=rev
Log:
Merge 100592, 100609, 100610, 100742, 101023.
Added:
llvm/branches/Apple/Morbo/test/CodeGen/X86/postra-licm.ll
- copied unchanged from r101023, llvm/trunk/test/CodeGen/X86/postra-licm.ll
Modified:
llvm/branches/Apple/Morbo/ (props changed)
llvm/branches/Apple/Morbo/include/llvm/CodeGen/Passes.h
llvm/branches/Apple/Morbo/lib/CodeGen/LLVMTargetMachine.cpp
llvm/branches/Apple/Morbo/lib/CodeGen/MachineLICM.cpp
llvm/branches/Apple/Morbo/lib/Transforms/IPO/FunctionAttrs.cpp (props changed)
Propchange: llvm/branches/Apple/Morbo/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Mon Apr 12 01:35:31 2010
@@ -1,2 +1,2 @@
/llvm/branches/Apple/Hermes:96832,96835,96858,96870,96876,96879
-/llvm/trunk:98602,98604,98612,98615-98616,98675,98686,98743-98744,98768,98773,98778,98780,98810,98835,98839,98845,98855,98862,98881,98920,98977,99032-99033,99043,99196,99223,99263,99282-99284,99306,99319-99321,99324,99336,99378,99418,99423,99429,99455,99463,99465,99469,99484,99490,99492-99494,99507,99524,99537,99539-99540,99544,99570,99575,99598,99620,99629-99630,99636,99671,99692,99695,99697,99699,99722,99816,99836,99845-99846,99848,99850,99855,99879,99881-99883,99895,99899,99910,99916,99919,99952-99954,99957,99959,99974-99975,99982,99984-99986,99988,99992-99993,99995,99997-99999,100016,100035,100037-100038,100042,100044,100072,100074,100081-100090,100092,100094-100095,100116,100134,100184,100209,100214-100218,100220-100221,100223-100225,100257,100261,100304,100332,100353,100384,100457,100478,100487,100497,100521,100553,100568,100584,100710,100736,100892,101011
+/llvm/trunk:98602,98604,98612,98615-98616,98675,98686,98743-98744,98768,98773,98778,98780,98810,98835,98839,98845,98855,98862,98881,98920,98977,99032-99033,99043,99196,99223,99263,99282-99284,99306,99319-99321,99324,99336,99378,99418,99423,99429,99455,99463,99465,99469,99484,99490,99492-99494,99507,99524,99537,99539-99540,99544,99570,99575,99598,99620,99629-99630,99636,99671,99692,99695,99697,99699,99722,99816,99836,99845-99846,99848,99850,99855,99879,99881-99883,99895,99899,99910,99916,99919,99952-99954,99957,99959,99974-99975,99982,99984-99986,99988,99992-99993,99995,99997-99999,100016,100035,100037-100038,100042,100044,100072,100074,100081-100090,100092,100094-100095,100116,100134,100184,100209,100214-100218,100220-100221,100223-100225,100257,100261,100304,100332,100353,100384,100457,100478,100480,100487,100494,100497,100521,100553,100568,100584,100592,100609-100610,100710,100736,100742,100751,100804,100837,100892,101011,101023
Modified: llvm/branches/Apple/Morbo/include/llvm/CodeGen/Passes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/include/llvm/CodeGen/Passes.h?rev=101025&r1=101024&r2=101025&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/include/llvm/CodeGen/Passes.h (original)
+++ llvm/branches/Apple/Morbo/include/llvm/CodeGen/Passes.h Mon Apr 12 01:35:31 2010
@@ -168,7 +168,7 @@
/// createMachineLICMPass - This pass performs LICM on machine instructions.
///
- FunctionPass *createMachineLICMPass();
+ FunctionPass *createMachineLICMPass(bool PreRegAlloc = true);
/// createMachineSinkingPass - This pass performs sinking on machine
/// instructions.
Modified: llvm/branches/Apple/Morbo/lib/CodeGen/LLVMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/lib/CodeGen/LLVMTargetMachine.cpp?rev=101025&r1=101024&r2=101025&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/lib/CodeGen/LLVMTargetMachine.cpp (original)
+++ llvm/branches/Apple/Morbo/lib/CodeGen/LLVMTargetMachine.cpp Mon Apr 12 01:35:31 2010
@@ -358,6 +358,9 @@
// kill markers.
PM.add(createStackSlotColoringPass(false));
printAndVerify(PM, "After StackSlotColoring");
+
+ // Run post-ra machine LICM to hoist reloads / remats.
+ PM.add(createMachineLICMPass(false));
}
// Run post-ra passes.
Modified: llvm/branches/Apple/Morbo/lib/CodeGen/MachineLICM.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/lib/CodeGen/MachineLICM.cpp?rev=101025&r1=101024&r2=101025&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/lib/CodeGen/MachineLICM.cpp (original)
+++ llvm/branches/Apple/Morbo/lib/CodeGen/MachineLICM.cpp Mon Apr 12 01:35:31 2010
@@ -22,8 +22,8 @@
#define DEBUG_TYPE "machine-licm"
#include "llvm/CodeGen/Passes.h"
-#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineDominators.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
@@ -33,6 +33,7 @@
#include "llvm/Target/TargetMachine.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
@@ -41,32 +42,41 @@
STATISTIC(NumHoisted, "Number of machine instructions hoisted out of loops");
STATISTIC(NumCSEed, "Number of hoisted machine instructions CSEed");
+STATISTIC(NumPostRAHoisted,
+ "Number of machine instructions hoisted out of loops post regalloc");
namespace {
class MachineLICM : public MachineFunctionPass {
- MachineConstantPool *MCP;
+ bool PreRegAlloc;
+
const TargetMachine *TM;
const TargetInstrInfo *TII;
const TargetRegisterInfo *TRI;
- BitVector AllocatableSet;
+ const MachineFrameInfo *MFI;
+ MachineRegisterInfo *RegInfo;
// Various analyses that we use...
AliasAnalysis *AA; // Alias analysis info.
- MachineLoopInfo *LI; // Current MachineLoopInfo
+ MachineLoopInfo *MLI; // Current MachineLoopInfo
MachineDominatorTree *DT; // Machine dominator tree for the cur loop
- MachineRegisterInfo *RegInfo; // Machine register information
// State that is updated as we process loops
bool Changed; // True if a loop is changed.
- bool FirstInLoop; // True if it's the first LICM in the loop.
MachineLoop *CurLoop; // The current loop we are working on.
MachineBasicBlock *CurPreheader; // The preheader for CurLoop.
+ BitVector AllocatableSet;
+
// For each opcode, keep a list of potentail CSE instructions.
DenseMap<unsigned, std::vector<const MachineInstr*> > CSEMap;
+
public:
static char ID; // Pass identification, replacement for typeid
- MachineLICM() : MachineFunctionPass(&ID) {}
+ MachineLICM() :
+ MachineFunctionPass(&ID), PreRegAlloc(true) {}
+
+ explicit MachineLICM(bool PreRA) :
+ MachineFunctionPass(&ID), PreRegAlloc(PreRA) {}
virtual bool runOnMachineFunction(MachineFunction &MF);
@@ -88,6 +98,35 @@
}
private:
+ /// CandidateInfo - Keep track of information about hoisting candidates.
+ struct CandidateInfo {
+ MachineInstr *MI;
+ int FI;
+ unsigned Def;
+ CandidateInfo(MachineInstr *mi, int fi, unsigned def)
+ : MI(mi), FI(fi), Def(def) {}
+ };
+
+ /// HoistRegionPostRA - Walk the specified region of the CFG and hoist loop
+ /// invariants out to the preheader.
+ void HoistRegionPostRA(MachineDomTreeNode *N);
+
+ /// HoistPostRA - When an instruction is found to only use loop invariant
+ /// operands that is safe to hoist, this instruction is called to do the
+ /// dirty work.
+ void HoistPostRA(MachineInstr *MI, unsigned Def);
+
+ /// ProcessMI - Examine the instruction for potentai LICM candidate. Also
+ /// gather register def and frame object update information.
+ void ProcessMI(MachineInstr *MI, unsigned *PhysRegDefs,
+ SmallSet<int, 32> &StoredFIs,
+ SmallVector<CandidateInfo, 32> &Candidates);
+
+ /// AddToLiveIns - Add 'Reg' to the livein sets of BBs in the backedge path
+ /// from MBB to LoopHeader (inclusive).
+ void AddToLiveIns(unsigned Reg,
+ MachineBasicBlock *MBB, MachineBasicBlock *LoopHeader);
+
/// IsLoopInvariantInst - Returns true if the instruction is loop
/// invariant. I.e., all virtual register operands are defined outside of
/// the loop, physical registers aren't accessed (explicitly or implicitly),
@@ -145,7 +184,9 @@
static RegisterPass<MachineLICM>
X("machinelicm", "Machine Loop Invariant Code Motion");
-FunctionPass *llvm::createMachineLICMPass() { return new MachineLICM(); }
+FunctionPass *llvm::createMachineLICMPass(bool PreRegAlloc) {
+ return new MachineLICM(PreRegAlloc);
+}
/// LoopIsOuterMostWithPreheader - Test if the given loop is the outer-most
/// loop that has a preheader.
@@ -161,26 +202,30 @@
/// loop.
///
bool MachineLICM::runOnMachineFunction(MachineFunction &MF) {
- DEBUG(dbgs() << "******** Machine LICM ********\n");
+ if (PreRegAlloc)
+ DEBUG(dbgs() << "******** Pre-regalloc Machine LICM ********\n");
+ else
+ DEBUG(dbgs() << "******** Post-regalloc Machine LICM ********\n");
- Changed = FirstInLoop = false;
- MCP = MF.getConstantPool();
+ Changed = false;
TM = &MF.getTarget();
TII = TM->getInstrInfo();
TRI = TM->getRegisterInfo();
+ MFI = MF.getFrameInfo();
RegInfo = &MF.getRegInfo();
AllocatableSet = TRI->getAllocatableSet(MF);
// Get our Loop information...
- LI = &getAnalysis<MachineLoopInfo>();
- DT = &getAnalysis<MachineDominatorTree>();
- AA = &getAnalysis<AliasAnalysis>();
+ MLI = &getAnalysis<MachineLoopInfo>();
+ DT = &getAnalysis<MachineDominatorTree>();
+ AA = &getAnalysis<AliasAnalysis>();
- for (MachineLoopInfo::iterator I = LI->begin(), E = LI->end(); I != E; ++I) {
+ for (MachineLoopInfo::iterator I = MLI->begin(), E = MLI->end(); I != E; ++I){
CurLoop = *I;
- // Only visit outer-most preheader-sporting loops.
- if (!LoopIsOuterMostWithPreheader(CurLoop))
+ // If this is done before regalloc, only visit outer-most preheader-sporting
+ // loops.
+ if (PreRegAlloc && !LoopIsOuterMostWithPreheader(CurLoop))
continue;
// Determine the block to which to hoist instructions. If we can't find a
@@ -195,14 +240,214 @@
// CSEMap is initialized for loop header when the first instruction is
// being hoisted.
- FirstInLoop = true;
- HoistRegion(DT->getNode(CurLoop->getHeader()));
- CSEMap.clear();
+ MachineDomTreeNode *N = DT->getNode(CurLoop->getHeader());
+ if (!PreRegAlloc)
+ HoistRegionPostRA(N);
+ else {
+ HoistRegion(N);
+ CSEMap.clear();
+ }
}
return Changed;
}
+/// InstructionStoresToFI - Return true if instruction stores to the
+/// specified frame.
+static bool InstructionStoresToFI(const MachineInstr *MI, int FI) {
+ for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
+ oe = MI->memoperands_end(); o != oe; ++o) {
+ if (!(*o)->isStore() || !(*o)->getValue())
+ continue;
+ if (const FixedStackPseudoSourceValue *Value =
+ dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
+ if (Value->getFrameIndex() == FI)
+ return true;
+ }
+ }
+ return false;
+}
+
+/// ProcessMI - Examine the instruction for potentai LICM candidate. Also
+/// gather register def and frame object update information.
+void MachineLICM::ProcessMI(MachineInstr *MI,
+ unsigned *PhysRegDefs,
+ SmallSet<int, 32> &StoredFIs,
+ SmallVector<CandidateInfo, 32> &Candidates) {
+ bool RuledOut = false;
+ unsigned Def = 0;
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ const MachineOperand &MO = MI->getOperand(i);
+ if (MO.isFI()) {
+ // Remember if the instruction stores to the frame index.
+ int FI = MO.getIndex();
+ if (!StoredFIs.count(FI) &&
+ MFI->isSpillSlotObjectIndex(FI) &&
+ InstructionStoresToFI(MI, FI))
+ StoredFIs.insert(FI);
+ continue;
+ }
+
+ if (!MO.isReg())
+ continue;
+ unsigned Reg = MO.getReg();
+ if (!Reg)
+ continue;
+ assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
+ "Not expecting virtual register!");
+
+ if (!MO.isDef())
+ continue;
+
+ if (MO.isImplicit()) {
+ ++PhysRegDefs[Reg];
+ for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
+ ++PhysRegDefs[*AS];
+ if (!MO.isDead())
+ // Non-dead implicit def? This cannot be hoisted.
+ RuledOut = true;
+ // No need to check if a dead implicit def is also defined by
+ // another instruction.
+ continue;
+ }
+
+ // FIXME: For now, avoid instructions with multiple defs, unless
+ // it's a dead implicit def.
+ if (Def)
+ RuledOut = true;
+ else
+ Def = Reg;
+
+ // If we have already seen another instruction that defines the same
+ // register, then this is not safe.
+ if (++PhysRegDefs[Reg] > 1)
+ // MI defined register is seen defined by another instruction in
+ // the loop, it cannot be a LICM candidate.
+ RuledOut = true;
+ for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
+ if (++PhysRegDefs[*AS] > 1)
+ RuledOut = true;
+ }
+
+ // FIXME: Only consider reloads for now. We should be able to handle
+ // remats which does not have register operands.
+ if (Def && !RuledOut) {
+ int FI;
+ if (TII->isLoadFromStackSlot(MI, FI) &&
+ MFI->isSpillSlotObjectIndex(FI))
+ Candidates.push_back(CandidateInfo(MI, FI, Def));
+ }
+}
+
+/// HoistRegionPostRA - Walk the specified region of the CFG and hoist loop
+/// invariants out to the preheader.
+void MachineLICM::HoistRegionPostRA(MachineDomTreeNode *N) {
+ assert(N != 0 && "Null dominator tree node?");
+
+ unsigned NumRegs = TRI->getNumRegs();
+ unsigned *PhysRegDefs = new unsigned[NumRegs];
+ std::fill(PhysRegDefs, PhysRegDefs + NumRegs, 0);
+
+ SmallVector<CandidateInfo, 32> Candidates;
+ SmallSet<int, 32> StoredFIs;
+
+ // Walk the entire region, count number of defs for each register, and
+ // return potential LICM candidates.
+ SmallVector<MachineDomTreeNode*, 8> WorkList;
+ WorkList.push_back(N);
+ do {
+ N = WorkList.pop_back_val();
+ MachineBasicBlock *BB = N->getBlock();
+
+ if (!CurLoop->contains(MLI->getLoopFor(BB)))
+ continue;
+ // Conservatively treat live-in's as an external def.
+ // FIXME: That means a reload that're reused in successor block(s) will not
+ // be LICM'ed.
+ for (MachineBasicBlock::const_livein_iterator I = BB->livein_begin(),
+ E = BB->livein_end(); I != E; ++I) {
+ unsigned Reg = *I;
+ ++PhysRegDefs[Reg];
+ for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
+ ++PhysRegDefs[*AS];
+ }
+
+ for (MachineBasicBlock::iterator
+ MII = BB->begin(), E = BB->end(); MII != E; ++MII) {
+ MachineInstr *MI = &*MII;
+ ProcessMI(MI, PhysRegDefs, StoredFIs, Candidates);
+ }
+
+ const std::vector<MachineDomTreeNode*> &Children = N->getChildren();
+ for (unsigned I = 0, E = Children.size(); I != E; ++I)
+ WorkList.push_back(Children[I]);
+ } while (!WorkList.empty());
+
+ // Now evaluate whether the potential candidates qualify.
+ // 1. Check if the candidate defined register is defined by another
+ // instruction in the loop.
+ // 2. If the candidate is a load from stack slot (always true for now),
+ // check if the slot is stored anywhere in the loop.
+ for (unsigned i = 0, e = Candidates.size(); i != e; ++i) {
+ if (StoredFIs.count(Candidates[i].FI))
+ continue;
+
+ if (PhysRegDefs[Candidates[i].Def] == 1)
+ HoistPostRA(Candidates[i].MI, Candidates[i].Def);
+ }
+}
+
+/// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the
+/// backedge path from MBB to LoopHeader.
+void MachineLICM::AddToLiveIns(unsigned Reg, MachineBasicBlock *MBB,
+ MachineBasicBlock *LoopHeader) {
+ SmallPtrSet<MachineBasicBlock*, 4> Visited;
+ SmallVector<MachineBasicBlock*, 4> WorkList;
+ WorkList.push_back(MBB);
+ do {
+ MBB = WorkList.pop_back_val();
+ if (!Visited.insert(MBB))
+ continue;
+ MBB->addLiveIn(Reg);
+ if (MBB == LoopHeader)
+ continue;
+ for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
+ E = MBB->pred_end(); PI != E; ++PI)
+ WorkList.push_back(*PI);
+ } while (!WorkList.empty());
+}
+
+/// HoistPostRA - When an instruction is found to only use loop invariant
+/// operands that is safe to hoist, this instruction is called to do the
+/// dirty work.
+void MachineLICM::HoistPostRA(MachineInstr *MI, unsigned Def) {
+ // Now move the instructions to the predecessor, inserting it before any
+ // terminator instructions.
+ DEBUG({
+ dbgs() << "Hoisting " << *MI;
+ if (CurPreheader->getBasicBlock())
+ dbgs() << " to MachineBasicBlock "
+ << CurPreheader->getName();
+ if (MI->getParent()->getBasicBlock())
+ dbgs() << " from MachineBasicBlock "
+ << MI->getParent()->getName();
+ dbgs() << "\n";
+ });
+
+ // Splice the instruction to the preheader.
+ MachineBasicBlock *MBB = MI->getParent();
+ CurPreheader->splice(CurPreheader->getFirstTerminator(), MBB, MI);
+
+ // Add register to livein list to BBs in the path from loop header to original
+ // BB. Note, currently it's not necessary to worry about adding it to all BB's
+ // with uses. Reload that're reused in successor block(s) are not being
+ // hoisted.
+ AddToLiveIns(Def, MBB, CurLoop->getHeader());
+
+ ++NumPostRAHoisted;
+ Changed = true;
+}
+
/// HoistRegion - Walk the specified region of the CFG (defined by all blocks
/// dominated by the specified block, and that are in the current loop) in depth
/// first order w.r.t the DominatorTree. This allows us to visit definitions
@@ -223,7 +468,6 @@
}
const std::vector<MachineDomTreeNode*> &Children = N->getChildren();
-
for (unsigned I = 0, E = Children.size(); I != E; ++I)
HoistRegion(Children[I]);
}
Propchange: llvm/branches/Apple/Morbo/lib/Transforms/IPO/FunctionAttrs.cpp
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Mon Apr 12 01:35:31 2010
@@ -1 +1 @@
-/llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp:99196,99492,99507,99524,99539-99540,99636,99699,99816,99836,99845-99846,99848,99850,99855,99879,99881-99883,99895,99899,99910,99916,99919,99952-99954,99957,99959,99974-99975,99982,99984-99986,99988,99992-99993,99995,99997-99999,100016,100035,100038,100042,100044,100072,100074,100081-100090,100092,100094-100095,100116,100132-100134,100137,100170,100184,100208-100209,100214-100218,100220-100221,100223-100225,100257,100261,100304,100384,100457,100478,100480,100487,100494,100497,100521,100553,100568,100584,100710,100736,100751,100804,100837,100892,101011
+/llvm/trunk/lib/Transforms/IPO/FunctionAttrs.cpp:99196,99492,99507,99524,99539-99540,99636,99699,99816,99836,99845-99846,99848,99850,99855,99879,99881-99883,99895,99899,99910,99916,99919,99952-99954,99957,99959,99974-99975,99982,99984-99986,99988,99992-99993,99995,99997-99999,100016,100035,100038,100042,100044,100072,100074,100081-100090,100092,100094-100095,100116,100132-100134,100137,100170,100184,100208-100209,100214-100218,100220-100221,100223-100225,100257,100261,100304,100384,100457,100478,100480,100487,100494,100497,100521,100553,100568,100584,100592,100609-100610,100710,100736,100742,100751,100804,100837,100892,101011,101023
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