[llvm-branch-commits] [llvm-branch] r83026 - in /llvm/branches/eh-experiment: include/llvm/CodeGen/SelectionDAGNodes.h include/llvm/IntrinsicInst.h lib/CodeGen/SelectionDAG/FastISel.cpp lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/PowerPC/PPCISelLowering.cpp lib/Target/X86/X86ISelLowering.cpp
Bill Wendling
isanbard at gmail.com
Mon Sep 28 16:02:52 PDT 2009
Author: void
Date: Mon Sep 28 18:02:52 2009
New Revision: 83026
URL: http://llvm.org/viewvc/llvm-project?rev=83026&view=rev
Log:
A slightly more correct version of the eh.personality intrinsic.
The purpose of this intrinsic:
- This intrinsic holds a pointer to the "personality" function. The new
experimental exception handling stuff is going to perform exception
handling explicitly. I.e., we won't be going through exception handling
tables. The reason for doing this is that LLVM's IR isn't sufficient
enough (at the present time) to encode the exception handling data and
also keep it up-to-date during transformations. The current way is to
encode the EH data in the CFG, and then do a sort of pattern matching
algorithm to try to recover this data. However, that falls apart very
quickly. This way is robust for all transformations.
Modified:
llvm/branches/eh-experiment/include/llvm/CodeGen/SelectionDAGNodes.h
llvm/branches/eh-experiment/include/llvm/IntrinsicInst.h
llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/FastISel.cpp
llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
llvm/branches/eh-experiment/lib/Target/ARM/ARMISelLowering.cpp
llvm/branches/eh-experiment/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/branches/eh-experiment/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/branches/eh-experiment/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/eh-experiment/include/llvm/CodeGen/SelectionDAGNodes.h?rev=83026&r1=83025&r2=83026&view=diff
==============================================================================
--- llvm/branches/eh-experiment/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/branches/eh-experiment/include/llvm/CodeGen/SelectionDAGNodes.h Mon Sep 28 18:02:52 2009
@@ -126,10 +126,6 @@
// the selection index of the exception thrown.
EHSELECTION,
- // RESULT, OUTCHAIN = EHPERSONALITY(INCHAIN, EXCEPTION) - This node
- // represents the selection index of the exception thrown.
- EHPERSONALITY,
-
// OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents
// 'eh_return' gcc dwarf builtin, which is used to return from
// exception. The general meaning is: adjust stack by OFFSET and pass
Modified: llvm/branches/eh-experiment/include/llvm/IntrinsicInst.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/eh-experiment/include/llvm/IntrinsicInst.h?rev=83026&r1=83025&r2=83026&view=diff
==============================================================================
--- llvm/branches/eh-experiment/include/llvm/IntrinsicInst.h (original)
+++ llvm/branches/eh-experiment/include/llvm/IntrinsicInst.h Mon Sep 28 18:02:52 2009
@@ -320,7 +320,21 @@
return isa<IntrinsicInst>(V) && classof(cast<IntrinsicInst>(V));
}
};
-
+
+ /// EHPersonalityInst - This represents the llvm.eh.personality instruction.
+ ///
+ struct EHPersonalityInst : public IntrinsicInst {
+ // Methods for support type inquiry through isa, cast, and dyn_cast:
+ static inline bool classof(const EHPersonalityInst *) { return true; }
+ static inline bool classof(const IntrinsicInst *I) {
+ return I->getIntrinsicID() == Intrinsic::eh_selector_i32 ||
+ I->getIntrinsicID() == Intrinsic::eh_selector_i64;
+ }
+ static inline bool classof(const Value *V) {
+ return isa<IntrinsicInst>(V) && classof(cast<IntrinsicInst>(V));
+ }
+ };
+
}
#endif
Modified: llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=83026&r1=83025&r2=83026&view=diff
==============================================================================
--- llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/FastISel.cpp Mon Sep 28 18:02:52 2009
@@ -479,37 +479,6 @@
}
break;
}
-
- case Intrinsic::eh_personality_i32:
- case Intrinsic::eh_personality_i64: {
- EVT VT = TLI.getValueType(I->getType());
- switch (TLI.getOperationAction(ISD::EHPERSONALITY, VT)) {
- default: break;
- case TargetLowering::Expand: {
- EVT VT = (IID == Intrinsic::eh_personality_i32 ? MVT::i32 : MVT::i64);
-
- if (MMI) {
- // FIXME: Mark exception selector register as live in. Hack for PR1508.
- unsigned Reg = TLI.getExceptionSelectorRegister();
- if (Reg) MBB->addLiveIn(Reg);
-
- const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
- unsigned ResultReg = createResultReg(RC);
- bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
- Reg, RC, RC);
- assert(InsertedCopy && "Can't copy address registers!");
- InsertedCopy = InsertedCopy;
- UpdateValueMap(I, ResultReg);
- } else {
- unsigned ResultReg =
- getRegForValue(Constant::getNullValue(I->getType()));
- UpdateValueMap(I, ResultReg);
- }
- return true;
- }
- }
- break;
- }
}
return false;
}
Modified: llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=83026&r1=83025&r2=83026&view=diff
==============================================================================
--- llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Sep 28 18:02:52 2009
@@ -2599,14 +2599,6 @@
Results.push_back(Results[0].getValue(1));
break;
}
- case ISD::EHPERSONALITY: {
- unsigned Reg = TLI.getExceptionSelectorRegister();
- assert(Reg && "Can't expand to unknown register!");
- Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg,
- Node->getValueType(0)));
- Results.push_back(Results[0].getValue(1));
- break;
- }
case ISD::EXCEPTIONADDR: {
unsigned Reg = TLI.getExceptionAddressRegister();
assert(Reg && "Can't expand to unknown register!");
Modified: llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=83026&r1=83025&r2=83026&view=diff
==============================================================================
--- llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Sep 28 18:02:52 2009
@@ -5367,7 +5367,6 @@
case ISD::EXCEPTIONADDR: return "EXCEPTIONADDR";
case ISD::LSDAADDR: return "LSDAADDR";
case ISD::EHSELECTION: return "EHSELECTION";
- case ISD::EHPERSONALITY: return "EHPERSONALITY";
case ISD::EH_RETURN: return "EH_RETURN";
case ISD::ConstantPool: return "ConstantPool";
case ISD::ExternalSymbol: return "ExternalSymbol";
Modified: llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=83026&r1=83025&r2=83026&view=diff
==============================================================================
--- llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original)
+++ llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Mon Sep 28 18:02:52 2009
@@ -67,6 +67,11 @@
cl::location(LimitFloatPrecision),
cl::init(0));
+// Forward declarations.
+static bool
+isInTailCallPosition(const Instruction *I, Attributes RetAttr,
+ const TargetLowering &TLI);
+
/// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
/// of insertvalue or extractvalue indices that identify a member, return
/// the linearized index of the start of the member.
@@ -4035,29 +4040,26 @@
case Intrinsic::eh_personality_i32:
case Intrinsic::eh_personality_i64: {
- // FIXME: Most of this was taken from eh_selector...
+ TargetLowering::ArgListTy Args; // Empty.
+ // FIXME: This "isTailCall" looks fishy here.
+ bool isTailCall = PerformTailCallOpt &&
+ isInTailCallPosition(&I, Attribute::None, TLI);
+ std::pair<SDValue, SDValue> Result =
+ TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, false,
+ 0, CallingConv::C, isTailCall, /*isReturnValueUsed=*/true,
+ getValue(I.getOperand(1)), Args, DAG,
+ getCurDebugLoc());
- // FIXME: Mark exception selector register as live in. Hack for PR1508.
- unsigned Reg = TLI.getExceptionSelectorRegister();
- if (Reg) CurMBB->addLiveIn(Reg);
+ if (Result.first.getNode())
+ setValue(&I, Result.first);
- // Insert the EHPERSONALITY instruction.
- SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
- SDValue Ops[2];
- Ops[0] = getValue(I.getOperand(1));
- Ops[1] = getRoot();
- SDValue Op = DAG.getNode(ISD::EHPERSONALITY, dl, VTs, Ops, 2);
-
- DAG.setRoot(Op.getValue(1));
+ if (Result.second.getNode())
+ DAG.setRoot(Result.second);
- MVT::SimpleValueType VT =
- (Intrinsic == Intrinsic::eh_personality_i32 ? MVT::i32 : MVT::i64);
- if (Op.getValueType().getSimpleVT() < VT)
- Op = DAG.getNode(ISD::SIGN_EXTEND, dl, VT, Op);
- else if (Op.getValueType().getSimpleVT() < VT)
- Op = DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
-
- setValue(&I, Op);
+ // This is bookkeeping so that the CIE generates correct data.
+ MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
+ ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(1));
+ MMI->addPersonality(CurMBB, cast<Function>(CE->getOperand(0)));
return 0;
}
Modified: llvm/branches/eh-experiment/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/eh-experiment/lib/Target/ARM/ARMISelLowering.cpp?rev=83026&r1=83025&r2=83026&view=diff
==============================================================================
--- llvm/branches/eh-experiment/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/branches/eh-experiment/lib/Target/ARM/ARMISelLowering.cpp Mon Sep 28 18:02:52 2009
@@ -371,7 +371,6 @@
setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
- setOperationAction(ISD::EHPERSONALITY, MVT::i32, Expand);
// FIXME: Shouldn't need this, since no register is used, but the legalizer
// doesn't yet know how to not do that for SjLj.
setExceptionSelectorRegister(ARM::R0);
Modified: llvm/branches/eh-experiment/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/eh-experiment/lib/Target/PowerPC/PPCISelLowering.cpp?rev=83026&r1=83025&r2=83026&view=diff
==============================================================================
--- llvm/branches/eh-experiment/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/branches/eh-experiment/lib/Target/PowerPC/PPCISelLowering.cpp Mon Sep 28 18:02:52 2009
@@ -188,10 +188,8 @@
setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
- setOperationAction(ISD::EHPERSONALITY, MVT::i64, Expand);
setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
- setOperationAction(ISD::EHPERSONALITY, MVT::i32, Expand);
// We want to legalize GlobalAddress and ConstantPool nodes into the
// appropriate instructions to materialize the address.
Modified: llvm/branches/eh-experiment/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/eh-experiment/lib/Target/X86/X86ISelLowering.cpp?rev=83026&r1=83025&r2=83026&view=diff
==============================================================================
--- llvm/branches/eh-experiment/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/eh-experiment/lib/Target/X86/X86ISelLowering.cpp Mon Sep 28 18:02:52 2009
@@ -383,10 +383,8 @@
setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
- setOperationAction(ISD::EHPERSONALITY, MVT::i64, Expand);
setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
- setOperationAction(ISD::EHPERSONALITY, MVT::i32, Expand);
if (Subtarget->is64Bit()) {
setExceptionPointerRegister(X86::RAX);
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