[llvm-branch-commits] [llvm-branch] r82714 - in /llvm/branches/Apple/Leela: include/llvm/Target/TargetInstrItineraries.h lib/CodeGen/ExactHazardRecognizer.cpp lib/Target/ARM/ARMSchedule.td utils/TableGen/SubtargetEmitter.cpp
Bob Wilson
bob.wilson at apple.com
Thu Sep 24 13:59:44 PDT 2009
Author: bwilson
Date: Thu Sep 24 15:59:43 2009
New Revision: 82714
URL: http://llvm.org/viewvc/llvm-project?rev=82714&view=rev
Log:
$ svn merge -c 82709 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r82709 into '.':
U include/llvm/Target/TargetInstrItineraries.h
U utils/TableGen/SubtargetEmitter.cpp
U lib/Target/ARM/ARMSchedule.td
U lib/CodeGen/ExactHazardRecognizer.cpp
Modified:
llvm/branches/Apple/Leela/include/llvm/Target/TargetInstrItineraries.h
llvm/branches/Apple/Leela/lib/CodeGen/ExactHazardRecognizer.cpp
llvm/branches/Apple/Leela/lib/Target/ARM/ARMSchedule.td
llvm/branches/Apple/Leela/utils/TableGen/SubtargetEmitter.cpp
Modified: llvm/branches/Apple/Leela/include/llvm/Target/TargetInstrItineraries.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/include/llvm/Target/TargetInstrItineraries.h?rev=82714&r1=82713&r2=82714&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/include/llvm/Target/TargetInstrItineraries.h (original)
+++ llvm/branches/Apple/Leela/include/llvm/Target/TargetInstrItineraries.h Thu Sep 24 15:59:43 2009
@@ -104,6 +104,14 @@
///
bool isEmpty() const { return Itineratries == 0; }
+ /// isEndMarker - Returns true if the index is for the end marker
+ /// itinerary.
+ ///
+ bool isEndMarker(unsigned ItinClassIndx) const {
+ return ((Itineratries[ItinClassIndx].FirstStage == ~0U) &&
+ (Itineratries[ItinClassIndx].LastStage == ~0U));
+ }
+
/// beginStage - Return the first stage of the itinerary.
///
const InstrStage *beginStage(unsigned ItinClassIndx) const {
Modified: llvm/branches/Apple/Leela/lib/CodeGen/ExactHazardRecognizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/CodeGen/ExactHazardRecognizer.cpp?rev=82714&r1=82713&r2=82714&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/CodeGen/ExactHazardRecognizer.cpp (original)
+++ llvm/branches/Apple/Leela/lib/CodeGen/ExactHazardRecognizer.cpp Thu Sep 24 15:59:43 2009
@@ -31,13 +31,11 @@
ScoreboardDepth = 1;
if (!ItinData.isEmpty()) {
for (unsigned idx = 0; ; ++idx) {
- // If the begin stage of an itinerary has 0 cycles and units,
- // then we have reached the end of the itineraries.
- const InstrStage *IS = ItinData.beginStage(idx);
- const InstrStage *E = ItinData.endStage(idx);
- if ((IS->getCycles() == 0) && (IS->getUnits() == 0))
+ if (ItinData.isEndMarker(idx))
break;
+ const InstrStage *IS = ItinData.beginStage(idx);
+ const InstrStage *E = ItinData.endStage(idx);
unsigned ItinDepth = 0;
for (; IS != E; ++IS)
ItinDepth += IS->getCycles();
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMSchedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMSchedule.td?rev=82714&r1=82713&r2=82714&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMSchedule.td (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMSchedule.td Thu Sep 24 15:59:43 2009
@@ -127,90 +127,7 @@
//===----------------------------------------------------------------------===//
// Processor instruction itineraries.
-def GenericItineraries : ProcessorItineraries<[
- InstrItinData<IIC_iALUx , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iALUi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iALUr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iALUsi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iALUsr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iUNAr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iUNAsi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iUNAsr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMPi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMPr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMPsi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMPsr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMOVi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMOVr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMOVsi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMOVsr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMOVi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMOVr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMOVsi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iCMOVsr , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMUL16 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMAC16 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMUL32 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMAC32 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMUL64 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iMAC64 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iLoadi , [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_iLoadr , [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_iLoadsi , [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_iLoadiu , [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_iLoadru , [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_iLoadsiu, [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_iLoadm , [InstrStage<2, [FU_Pipe0]>,
- InstrStage<2, [FU_LdSt0]>]>,
- InstrItinData<IIC_iStorei , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iStorer , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iStoresi , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iStoreiu , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iStoreru , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iStoresiu, [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_iStorem , [InstrStage<2, [FU_Pipe0]>]>,
- InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpSTAT , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpMOVSI , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpMOVDI , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpMOVIS , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpMOVID , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpUNA32 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpUNA64 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpCMP32 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpCMP64 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpCVTSD , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpCVTDS , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpCVTIS , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpCVTID , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpCVTSI , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpCVTDI , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpALU32 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpALU64 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpMUL32 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpMUL64 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpMAC32 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpMAC64 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpDIV32 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpDIV64 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpSQRT32 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpSQRT64 , [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpLoad32 , [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_fpLoad64 , [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_fpLoadm , [InstrStage<1, [FU_Pipe0]>,
- InstrStage<1, [FU_LdSt0]>]>,
- InstrItinData<IIC_fpStore32, [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpStore64, [InstrStage<1, [FU_Pipe0]>]>,
- InstrItinData<IIC_fpStorem , [InstrStage<1, [FU_Pipe0]>]>
-]>;
+def GenericItineraries : ProcessorItineraries<[]>;
include "ARMScheduleV6.td"
Modified: llvm/branches/Apple/Leela/utils/TableGen/SubtargetEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/utils/TableGen/SubtargetEmitter.cpp?rev=82714&r1=82713&r2=82714&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/utils/TableGen/SubtargetEmitter.cpp (original)
+++ llvm/branches/Apple/Leela/utils/TableGen/SubtargetEmitter.cpp Thu Sep 24 15:59:43 2009
@@ -413,7 +413,7 @@
// For each itinerary class
std::vector<InstrItinerary> &ItinList = *ProcListIter++;
- for (unsigned j = 0, M = ItinList.size(); j < M;) {
+ for (unsigned j = 0, M = ItinList.size(); j < M; ++j) {
InstrItinerary &Intinerary = ItinList[j];
// Emit in the form of
@@ -427,13 +427,11 @@
Intinerary.LastOperandCycle << " }";
}
- // If more in list add comma
- if (++j < M) OS << ",";
-
- OS << " // " << (j - 1) << "\n";
+ OS << ", // " << j << "\n";
}
// End processor itinerary table
+ OS << " { ~0U, ~0U, ~0U, ~0U } // end marker\n";
OS << "};\n";
}
}
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