[llvm-branch-commits] [llvm-branch] r81270 - in /llvm/branches/release_26: lib/CodeGen/SimpleRegisterCoalescing.cpp test/CodeGen/X86/2009-09-07-CoalescerBug.ll

[Tanya Lattner]

Author: tbrethou
Date: Tue Sep  8 18:29:08 2009
New Revision: 81270

URL: http://llvm.org/viewvc/llvm-project?rev=81270&view=rev
Log:
Merge 81204 from mainline (with minor tweak).
When remat'ing and destination virtual register has a sub-register index. Make sure the sub-register class matches the register class of the remat'ed instruction definition register class.

Added:
    llvm/branches/release_26/test/CodeGen/X86/2009-09-07-CoalescerBug.ll
      - copied unchanged from r81204, llvm/trunk/test/CodeGen/X86/2009-09-07-CoalescerBug.ll
Modified:
    llvm/branches/release_26/lib/CodeGen/SimpleRegisterCoalescing.cpp

Modified: llvm/branches/release_26/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_26/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=81270&r1=81269&r2=81270&view=diff

==============================================================================
--- llvm/branches/release_26/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/branches/release_26/lib/CodeGen/SimpleRegisterCoalescing.cpp Tue Sep  8 18:29:08 2009
@@ -635,6 +635,22 @@
       return false;
   }
 
+  // If destination register has a sub-register index on it, make sure it mtches
+  // the instruction register class.
+  if (DstSubIdx) {
+    const TargetInstrDesc &TID = DefMI->getDesc();
+    if (TID.getNumDefs() != 1)
+      return false;
+    const TargetRegisterClass *DstRC = mri_->getRegClass(DstReg);
+    const TargetRegisterClass *DstSubRC =
+      DstRC->getSubRegisterRegClass(DstSubIdx);
+    const TargetRegisterClass *DefRC = TID.OpInfo[0].getRegClass(tri_);
+    if (DefRC == DstRC)
+      DstSubIdx = 0;
+    else if (DefRC != DstSubRC)
+      return false;
+  }
+
   unsigned DefIdx = li_->getDefIndex(CopyIdx);
   const LiveRange *DLR= li_->getInterval(DstReg).getLiveRangeContaining(DefIdx);
   DLR->valno->setCopy(0);