[llvm-branch-commits] [llvm-branch] r85444 - in /llvm/branches/Apple/Leela: include/llvm/CodeGen/ lib/CodeGen/ lib/Target/ARM/ test/CodeGen/X86/
Bill Wendling
isanbard at gmail.com
Wed Oct 28 15:31:13 PDT 2009
Author: void
Date: Wed Oct 28 17:31:12 2009
New Revision: 85444
URL: http://llvm.org/viewvc/llvm-project?rev=85444&view=rev
Log:
$ svn merge -c 85411 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85411 into '.':
U lib/Target/ARM/ARMBaseInstrInfo.cpp
U lib/Target/ARM/ARMInstrInfo.cpp
U lib/Target/ARM/ARMInstrThumb.td
U lib/Target/ARM/Thumb1InstrInfo.cpp
U lib/Target/ARM/ARMInstrInfo.td
U lib/Target/ARM/ARMBaseInstrInfo.h
U lib/Target/ARM/Thumb2InstrInfo.cpp
$ svn merge -c 85426 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85426 into '.':
U include/llvm/CodeGen/Passes.h
U lib/CodeGen/LLVMTargetMachine.cpp
U lib/CodeGen/BranchFolding.cpp
U lib/CodeGen/IfConversion.cpp
U lib/CodeGen/BranchFolding.h
U lib/Target/ARM/ARMTargetMachine.cpp
$ svn merge -c 85441 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85441 into '.':
U test/CodeGen/X86/2008-02-18-TailMergingBug.ll
U test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll
U test/CodeGen/X86/2008-05-12-tailmerge-5.ll
G lib/CodeGen/BranchFolding.cpp
Modified:
llvm/branches/Apple/Leela/include/llvm/CodeGen/Passes.h
llvm/branches/Apple/Leela/lib/CodeGen/BranchFolding.cpp
llvm/branches/Apple/Leela/lib/CodeGen/BranchFolding.h
llvm/branches/Apple/Leela/lib/CodeGen/IfConversion.cpp
llvm/branches/Apple/Leela/lib/CodeGen/LLVMTargetMachine.cpp
llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseInstrInfo.h
llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.cpp
llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.td
llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrThumb.td
llvm/branches/Apple/Leela/lib/Target/ARM/ARMTargetMachine.cpp
llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1InstrInfo.cpp
llvm/branches/Apple/Leela/lib/Target/ARM/Thumb2InstrInfo.cpp
llvm/branches/Apple/Leela/test/CodeGen/X86/2008-02-18-TailMergingBug.ll
llvm/branches/Apple/Leela/test/CodeGen/X86/2008-05-12-tailmerge-5.ll
llvm/branches/Apple/Leela/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll
Modified: llvm/branches/Apple/Leela/include/llvm/CodeGen/Passes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/include/llvm/CodeGen/Passes.h?rev=85444&r1=85443&r2=85444&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/include/llvm/CodeGen/Passes.h (original)
+++ llvm/branches/Apple/Leela/include/llvm/CodeGen/Passes.h Wed Oct 28 17:31:12 2009
@@ -127,11 +127,10 @@
/// optimizations to delete branches to branches, eliminate branches to
/// successor blocks (creating fall throughs), and eliminating branches over
/// branches.
- FunctionPass *createBranchFoldingPass(bool DefaultEnableTailMerge,
- CodeGenOpt::Level OptLevel);
+ FunctionPass *createBranchFoldingPass(bool DefaultEnableTailMerge);
- /// IfConverter Pass - This pass performs machine code if-conversion.
- FunctionPass *createIfConverterPass(CodeGenOpt::Level OptLevel);
+ /// IfConverter Pass - This pass performs machine code if conversion.
+ FunctionPass *createIfConverterPass();
/// Code Placement Pass - This pass optimize code placement and aligns loop
/// headers to target specific alignment boundary.
Modified: llvm/branches/Apple/Leela/lib/CodeGen/BranchFolding.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/CodeGen/BranchFolding.cpp?rev=85444&r1=85443&r2=85444&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/CodeGen/BranchFolding.cpp (original)
+++ llvm/branches/Apple/Leela/lib/CodeGen/BranchFolding.cpp Wed Oct 28 17:31:12 2009
@@ -18,6 +18,7 @@
#define DEBUG_TYPE "branchfolding"
#include "BranchFolding.h"
+#include "llvm/Function.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
@@ -50,9 +51,8 @@
char BranchFolderPass::ID = 0;
-FunctionPass *llvm::createBranchFoldingPass(bool DefaultEnableTailMerge,
- CodeGenOpt::Level OptLevel) {
- return new BranchFolderPass(DefaultEnableTailMerge, OptLevel);
+FunctionPass *llvm::createBranchFoldingPass(bool DefaultEnableTailMerge) {
+ return new BranchFolderPass(DefaultEnableTailMerge);
}
bool BranchFolderPass::runOnMachineFunction(MachineFunction &MF) {
@@ -64,8 +64,7 @@
-BranchFolder::BranchFolder(bool defaultEnableTailMerge, CodeGenOpt::Level OL) {
- OptLevel = OL;
+BranchFolder::BranchFolder(bool defaultEnableTailMerge) {
switch (FlagEnableTailMerge) {
case cl::BOU_UNSET: EnableTailMerge = defaultEnableTailMerge; break;
case cl::BOU_TRUE: EnableTailMerge = true; break;
@@ -467,24 +466,23 @@
CurMPIter!=B && CurMPIter->first==CurHash;
--CurMPIter) {
for (MPIterator I = prior(CurMPIter); I->first==CurHash ; --I) {
- unsigned CommonTailLen = ComputeCommonTailLength(
- CurMPIter->second,
- I->second,
- TrialBBI1, TrialBBI2);
+ unsigned CommonTailLen = ComputeCommonTailLength(CurMPIter->second,
+ I->second,
+ TrialBBI1, TrialBBI2);
// If we will have to split a block, there should be at least
- // minCommonTailLength instructions in common; if not, and if we are not
- // optimizing for performance at the expense of code size, at worst
- // we will be replacing a fallthrough into the common tail with a
- // branch, which at worst breaks even with falling through into
- // the duplicated common tail, so 1 instruction in common is enough.
- // We will always pick a block we do not have to split as the common
- // tail if there is one.
- // (Empty blocks will get forwarded and need not be considered.)
+ // minCommonTailLength instructions in common. Otherwise, if we are
+ // optimizing for code size, 1 instruction in common is enough. At
+ // worst we will be replacing a fallthrough into the common tail with a
+ // branch, which at worst breaks even with falling through into the
+ // duplicated common tail. We will always pick a block we do not have
+ // to split as the common tail if there is one. (Empty blocks will get
+ // forwarded and need not be considered.)
+ MachineFunction *MF = CurMPIter->second->getParent();
if (CommonTailLen >= minCommonTailLength ||
- (OptLevel != CodeGenOpt::Aggressive &&
- CommonTailLen > 0 &&
- (TrialBBI1==CurMPIter->second->begin() ||
- TrialBBI2==I->second->begin()))) {
+ (CommonTailLen > 0 &&
+ MF->getFunction()->hasFnAttr(Attribute::OptimizeForSize) &&
+ (TrialBBI1 == CurMPIter->second->begin() ||
+ TrialBBI2 == I->second->begin()))) {
if (CommonTailLen > maxCommonTailLength) {
SameTails.clear();
maxCommonTailLength = CommonTailLen;
Modified: llvm/branches/Apple/Leela/lib/CodeGen/BranchFolding.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/CodeGen/BranchFolding.h?rev=85444&r1=85443&r2=85444&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/CodeGen/BranchFolding.h (original)
+++ llvm/branches/Apple/Leela/lib/CodeGen/BranchFolding.h Wed Oct 28 17:31:12 2009
@@ -12,7 +12,6 @@
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/Target/TargetMachine.h"
#include <vector>
namespace llvm {
@@ -24,7 +23,7 @@
class BranchFolder {
public:
- explicit BranchFolder(bool defaultEnableTailMerge, CodeGenOpt::Level OL);
+ explicit BranchFolder(bool defaultEnableTailMerge);
bool OptimizeFunction(MachineFunction &MF,
const TargetInstrInfo *tii,
@@ -38,7 +37,6 @@
typedef std::pair<MPIterator, MachineBasicBlock::iterator> SameTailElt;
std::vector<SameTailElt> SameTails;
- CodeGenOpt::Level OptLevel;
bool EnableTailMerge;
const TargetInstrInfo *TII;
const TargetRegisterInfo *TRI;
@@ -75,10 +73,8 @@
public BranchFolder {
public:
static char ID;
- explicit BranchFolderPass(bool defaultEnableTailMerge,
- CodeGenOpt::Level OptLevel)
- : MachineFunctionPass(&ID),
- BranchFolder(defaultEnableTailMerge, OptLevel) {}
+ explicit BranchFolderPass(bool defaultEnableTailMerge)
+ : MachineFunctionPass(&ID), BranchFolder(defaultEnableTailMerge) {}
virtual bool runOnMachineFunction(MachineFunction &MF);
virtual const char *getPassName() const { return "Control Flow Optimizer"; }
Modified: llvm/branches/Apple/Leela/lib/CodeGen/IfConversion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/CodeGen/IfConversion.cpp?rev=85444&r1=85443&r2=85444&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/CodeGen/IfConversion.cpp (original)
+++ llvm/branches/Apple/Leela/lib/CodeGen/IfConversion.cpp Wed Oct 28 17:31:12 2009
@@ -148,11 +148,9 @@
const TargetInstrInfo *TII;
bool MadeChange;
int FnNum;
- CodeGenOpt::Level OptLevel;
public:
static char ID;
- IfConverter(CodeGenOpt::Level OL) :
- MachineFunctionPass(&ID), FnNum(-1), OptLevel(OL) {}
+ IfConverter() : MachineFunctionPass(&ID), FnNum(-1) {}
virtual bool runOnMachineFunction(MachineFunction &MF);
virtual const char *getPassName() const { return "If Converter"; }
@@ -221,9 +219,10 @@
char IfConverter::ID = 0;
}
-FunctionPass *llvm::createIfConverterPass(CodeGenOpt::Level OptLevel) {
- return new IfConverter(OptLevel);
-}
+static RegisterPass<IfConverter>
+X("if-converter", "If Converter");
+
+FunctionPass *llvm::createIfConverterPass() { return new IfConverter(); }
bool IfConverter::runOnMachineFunction(MachineFunction &MF) {
TLI = MF.getTarget().getTargetLowering();
@@ -363,7 +362,7 @@
BBAnalysis.clear();
if (MadeChange) {
- BranchFolder BF(false, OptLevel);
+ BranchFolder BF(false);
BF.OptimizeFunction(MF, TII,
MF.getTarget().getRegisterInfo(),
getAnalysisIfAvailable<MachineModuleInfo>());
Modified: llvm/branches/Apple/Leela/lib/CodeGen/LLVMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/CodeGen/LLVMTargetMachine.cpp?rev=85444&r1=85443&r2=85444&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/CodeGen/LLVMTargetMachine.cpp (original)
+++ llvm/branches/Apple/Leela/lib/CodeGen/LLVMTargetMachine.cpp Wed Oct 28 17:31:12 2009
@@ -329,7 +329,7 @@
// Branch folding must be run after regalloc and prolog/epilog insertion.
if (OptLevel != CodeGenOpt::None) {
- PM.add(createBranchFoldingPass(getEnableTailMergeDefault(), OptLevel));
+ PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
printAndVerify(PM);
}
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=85444&r1=85443&r2=85444&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseInstrInfo.cpp Wed Oct 28 17:31:12 2009
@@ -249,7 +249,8 @@
// ...likewise if it ends with a branch table followed by an unconditional
// branch. The branch folder can create these, and we must get rid of them for
// correctness of Thumb constant islands.
- if (isJumpTableBranchOpcode(SecondLastOpc) &&
+ if ((isJumpTableBranchOpcode(SecondLastOpc) ||
+ isIndirectBranchOpcode(SecondLastOpc)) &&
isUncondBranchOpcode(LastOpc)) {
I = LastInst;
if (AllowModify)
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseInstrInfo.h?rev=85444&r1=85443&r2=85444&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseInstrInfo.h (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseInstrInfo.h Wed Oct 28 17:31:12 2009
@@ -293,6 +293,11 @@
Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
}
+static inline
+bool isIndirectBranchOpcode(int Opc) {
+ return Opc == ARM::BRIND || Opc == ARM::tBRIND;
+}
+
/// getInstrPredicate - If instruction is predicated, returns its predicate
/// condition, otherwise returns AL. It also returns the condition code
/// register by reference.
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.cpp?rev=85444&r1=85443&r2=85444&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.cpp Wed Oct 28 17:31:12 2009
@@ -68,6 +68,7 @@
case ARM::BX_RET: // Return.
case ARM::LDM_RET:
case ARM::B:
+ case ARM::BRIND:
case ARM::BR_JTr: // Jumptable branch.
case ARM::BR_JTm: // Jumptable branch through mem.
case ARM::BR_JTadd: // Jumptable branch add to pc.
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.td?rev=85444&r1=85443&r2=85444&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.td Wed Oct 28 17:31:12 2009
@@ -659,7 +659,7 @@
// Indirect branches
let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
- def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx $dst",
+ def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
[(brind GPR:$dst)]> {
let Inst{7-4} = 0b0001;
let Inst{19-8} = 0b111111111111;
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrThumb.td?rev=85444&r1=85443&r2=85444&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrThumb.td Wed Oct 28 17:31:12 2009
@@ -180,6 +180,12 @@
def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), IIC_Br, "bx\t$target", []>;
}
+// Indirect branches
+let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
+ def tBRIND : TI<(outs), (ins GPR:$dst), IIC_Br, "bx\t$dst",
+ [(brind GPR:$dst)]>;
+}
+
// FIXME: remove when we have a way to marking a MI with these properties.
let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
hasExtraDefRegAllocReq = 1 in
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMTargetMachine.cpp?rev=85444&r1=85443&r2=85444&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMTargetMachine.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMTargetMachine.cpp Wed Oct 28 17:31:12 2009
@@ -114,7 +114,7 @@
CodeGenOpt::Level OptLevel) {
// FIXME: temporarily disabling load / store optimization pass for Thumb1.
if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
- PM.add(createIfConverterPass(OptLevel));
+ PM.add(createIfConverterPass());
if (Subtarget.isThumb2()) {
PM.add(createThumb2ITBlockPass());
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1InstrInfo.cpp?rev=85444&r1=85443&r2=85444&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1InstrInfo.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1InstrInfo.cpp Wed Oct 28 17:31:12 2009
@@ -38,6 +38,7 @@
case ARM::tBX_RET_vararg:
case ARM::tPOP_RET:
case ARM::tB:
+ case ARM::tBRIND:
case ARM::tBR_JTr:
return true;
default:
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/Thumb2InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/Thumb2InstrInfo.cpp?rev=85444&r1=85443&r2=85444&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/Thumb2InstrInfo.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/Thumb2InstrInfo.cpp Wed Oct 28 17:31:12 2009
@@ -46,6 +46,7 @@
case ARM::tBX_RET_vararg:
case ARM::tPOP_RET:
case ARM::tB:
+ case ARM::tBRIND:
return true;
default:
break;
Modified: llvm/branches/Apple/Leela/test/CodeGen/X86/2008-02-18-TailMergingBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/X86/2008-02-18-TailMergingBug.ll?rev=85444&r1=85443&r2=85444&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/X86/2008-02-18-TailMergingBug.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/X86/2008-02-18-TailMergingBug.ll Wed Oct 28 17:31:12 2009
@@ -3,7 +3,7 @@
@.str = internal constant [48 x i8] c"transformed bounds: (%.2f, %.2f), (%.2f, %.2f)\0A\00" ; <[48 x i8]*> [#uses=1]
-define void @minmax(float* %result) nounwind {
+define void @minmax(float* %result) nounwind optsize {
entry:
%tmp2 = load float* %result, align 4 ; <float> [#uses=6]
%tmp4 = getelementptr float* %result, i32 2 ; <float*> [#uses=5]
Modified: llvm/branches/Apple/Leela/test/CodeGen/X86/2008-05-12-tailmerge-5.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/X86/2008-05-12-tailmerge-5.ll?rev=85444&r1=85443&r2=85444&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/X86/2008-05-12-tailmerge-5.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/X86/2008-05-12-tailmerge-5.ll Wed Oct 28 17:31:12 2009
@@ -6,7 +6,7 @@
target triple = "x86_64-apple-darwin8"
%struct.BoundaryAlignment = type { [3 x i8], i8, i16, i16, i8, [2 x i8] }
-define void @passing2(i64 %str.0, i64 %str.1, i16 signext %s, i32 %j, i8 signext %c, i16 signext %t, i16 signext %u, i8 signext %d) nounwind {
+define void @passing2(i64 %str.0, i64 %str.1, i16 signext %s, i32 %j, i8 signext %c, i16 signext %t, i16 signext %u, i8 signext %d) nounwind optsize {
entry:
%str_addr = alloca %struct.BoundaryAlignment ; <%struct.BoundaryAlignment*> [#uses=7]
%s_addr = alloca i16 ; <i16*> [#uses=1]
Modified: llvm/branches/Apple/Leela/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll?rev=85444&r1=85443&r2=85444&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll Wed Oct 28 17:31:12 2009
@@ -2,7 +2,7 @@
; RUN: grep {asm-printer} | grep {Number of machine instrs printed} | grep 5
; RUN: grep {leal 1(\%rsi),} %t
-define fastcc zeroext i8 @fullGtU(i32 %i1, i32 %i2) nounwind {
+define fastcc zeroext i8 @fullGtU(i32 %i1, i32 %i2) nounwind optsize {
entry:
%0 = add i32 %i2, 1 ; <i32> [#uses=1]
%1 = sext i32 %0 to i64 ; <i64> [#uses=1]
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