[llvm-branch-commits] [llvm-branch] r85374 - in /llvm/branches/Apple/Leela: include/llvm/Target/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/ARM/AsmPrinter/ lib/Target/Alpha/ lib/Target/Mips/ lib/Target/SystemZ/ lib/Target/X86/ test/CodeGen/ARM/
Evan Cheng
evan.cheng at apple.com
Tue Oct 27 22:14:26 PDT 2009
Author: evancheng
Date: Wed Oct 28 00:14:25 2009
New Revision: 85374
URL: http://llvm.org/viewvc/llvm-project?rev=85374&view=rev
Log:
Merge in 85281, 85361, and 85362.
Added:
llvm/branches/Apple/Leela/test/CodeGen/ARM/fpconsts.ll
Modified:
llvm/branches/Apple/Leela/include/llvm/Target/TargetLowering.h
llvm/branches/Apple/Leela/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/branches/Apple/Leela/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.cpp
llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.h
llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrVFP.td
llvm/branches/Apple/Leela/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
llvm/branches/Apple/Leela/lib/Target/Alpha/AlphaISelLowering.cpp
llvm/branches/Apple/Leela/lib/Target/Alpha/AlphaISelLowering.h
llvm/branches/Apple/Leela/lib/Target/Mips/MipsISelLowering.cpp
llvm/branches/Apple/Leela/lib/Target/Mips/MipsISelLowering.h
llvm/branches/Apple/Leela/lib/Target/SystemZ/SystemZISelLowering.cpp
llvm/branches/Apple/Leela/lib/Target/SystemZ/SystemZISelLowering.h
llvm/branches/Apple/Leela/lib/Target/X86/X86ISelLowering.cpp
llvm/branches/Apple/Leela/lib/Target/X86/X86ISelLowering.h
Modified: llvm/branches/Apple/Leela/include/llvm/Target/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/include/llvm/Target/TargetLowering.h?rev=85374&r1=85373&r2=85374&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/include/llvm/Target/TargetLowering.h (original)
+++ llvm/branches/Apple/Leela/include/llvm/Target/TargetLowering.h Wed Oct 28 00:14:25 2009
@@ -325,12 +325,11 @@
/// scalarizing vs using the wider vector type.
virtual EVT getWidenVectorType(EVT VT) const;
- typedef std::vector<APFloat>::const_iterator legal_fpimm_iterator;
- legal_fpimm_iterator legal_fpimm_begin() const {
- return LegalFPImmediates.begin();
- }
- legal_fpimm_iterator legal_fpimm_end() const {
- return LegalFPImmediates.end();
+ /// isFPImmLegal - Returns true if the target can instruction select the
+ /// specified FP immediate natively. If false, the legalizer will materialize
+ /// the FP immediate as a load from a constant pool.
+ virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const {
+ return false;
}
/// isShuffleMaskLegal - Targets can use this to indicate that they only
@@ -1051,12 +1050,6 @@
PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
}
- /// addLegalFPImmediate - Indicate that this target can instruction select
- /// the specified FP immediate natively.
- void addLegalFPImmediate(const APFloat& Imm) {
- LegalFPImmediates.push_back(Imm);
- }
-
/// setTargetDAGCombine - Targets should invoke this method for each target
/// independent node that they want to provide a custom DAG combiner for by
/// implementing the PerformDAGCombine virtual method.
@@ -1696,8 +1689,6 @@
ValueTypeActionImpl ValueTypeActions;
- std::vector<APFloat> LegalFPImmediates;
-
std::vector<std::pair<EVT, TargetRegisterClass*> > AvailableRegClasses;
/// TargetDAGCombineArray - Targets can specify ISD nodes that they would
Modified: llvm/branches/Apple/Leela/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=85374&r1=85373&r2=85374&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/branches/Apple/Leela/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Oct 28 00:14:25 2009
@@ -2575,16 +2575,8 @@
case ISD::ConstantFP: {
ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
// Check to see if this FP immediate is already legal.
- bool isLegal = false;
- for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
- E = TLI.legal_fpimm_end(); I != E; ++I) {
- if (CFP->isExactlyValue(*I)) {
- isLegal = true;
- break;
- }
- }
// If this is a legal constant, turn it into a TargetConstantFP node.
- if (isLegal)
+ if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
Results.push_back(SDValue(Node, 0));
else
Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI));
Modified: llvm/branches/Apple/Leela/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=85374&r1=85373&r2=85374&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/branches/Apple/Leela/lib/CodeGen/SelectionDAG/TargetLowering.cpp Wed Oct 28 00:14:25 2009
@@ -481,7 +481,7 @@
setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
// ConstantFP nodes default to expand. Targets can either change this to
- // Legal, in which case all fp constants are legal, or use addLegalFPImmediate
+ // Legal, in which case all fp constants are legal, or use isFPImmLegal()
// to optimize expansions for certain constants.
setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.cpp?rev=85374&r1=85373&r2=85374&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.cpp Wed Oct 28 00:14:25 2009
@@ -3989,3 +3989,60 @@
// The ARM target isn't yet aware of offsets.
return false;
}
+
+int ARM::getVFPf32Imm(const APFloat &FPImm) {
+ APInt Imm = FPImm.bitcastToAPInt();
+ uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
+ int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
+ int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
+
+ // We can handle 4 bits of mantissa.
+ // mantissa = (16+UInt(e:f:g:h))/16.
+ if (Mantissa & 0x7ffff)
+ return -1;
+ Mantissa >>= 19;
+ if ((Mantissa & 0xf) != Mantissa)
+ return -1;
+
+ // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
+ if (Exp < -3 || Exp > 4)
+ return -1;
+ Exp = ((Exp+3) & 0x7) ^ 4;
+
+ return ((int)Sign << 7) | (Exp << 4) | Mantissa;
+}
+
+int ARM::getVFPf64Imm(const APFloat &FPImm) {
+ APInt Imm = FPImm.bitcastToAPInt();
+ uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
+ int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
+ uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL;
+
+ // We can handle 4 bits of mantissa.
+ // mantissa = (16+UInt(e:f:g:h))/16.
+ if (Mantissa & 0xffffffffffffLL)
+ return -1;
+ Mantissa >>= 48;
+ if ((Mantissa & 0xf) != Mantissa)
+ return -1;
+
+ // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
+ if (Exp < -3 || Exp > 4)
+ return -1;
+ Exp = ((Exp+3) & 0x7) ^ 4;
+
+ return ((int)Sign << 7) | (Exp << 4) | Mantissa;
+}
+
+/// isFPImmLegal - Returns true if the target can instruction select the
+/// specified FP immediate natively. If false, the legalizer will
+/// materialize the FP immediate as a load from a constant pool.
+bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
+ if (!Subtarget->hasVFP3())
+ return false;
+ if (VT == MVT::f32)
+ return ARM::getVFPf32Imm(Imm) != -1;
+ if (VT == MVT::f64)
+ return ARM::getVFPf64Imm(Imm) != -1;
+ return false;
+}
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.h?rev=85374&r1=85373&r2=85374&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.h (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.h Wed Oct 28 00:14:25 2009
@@ -137,6 +137,13 @@
/// return the constant being splatted. The ByteSize field indicates the
/// number of bytes of each element [1248].
SDValue getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
+
+ /// getVFPf32Imm / getVFPf64Imm - If the given fp immediate can be
+ /// materialized with a VMOV.f32 / VMOV.f64 (i.e. fconsts / fconstd)
+ /// instruction, returns its 8-bit integer representation. Otherwise,
+ /// returns -1.
+ int getVFPf32Imm(const APFloat &FPImm);
+ int getVFPf64Imm(const APFloat &FPImm);
}
//===--------------------------------------------------------------------===//
@@ -224,6 +231,12 @@
bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
+
+ /// isFPImmLegal - Returns true if the target can instruction select the
+ /// specified FP immediate natively. If false, the legalizer will
+ /// materialize the FP immediate as a load from a constant pool.
+ virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
+
private:
/// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
/// make the right decision when generating code for different targets.
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrVFP.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrVFP.td?rev=85374&r1=85373&r2=85374&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrVFP.td (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrVFP.td Wed Oct 28 00:14:25 2009
@@ -31,6 +31,26 @@
def arm_fmdrr : SDNode<"ARMISD::FMDRR", SDT_FMDRR>;
//===----------------------------------------------------------------------===//
+// Operand Definitions.
+//
+
+
+def vfp_f32imm : Operand<f32>,
+ PatLeaf<(f32 fpimm), [{
+ return ARM::getVFPf32Imm(N->getValueAPF()) != -1;
+ }]> {
+ let PrintMethod = "printVFPf32ImmOperand";
+}
+
+def vfp_f64imm : Operand<f64>,
+ PatLeaf<(f64 fpimm), [{
+ return ARM::getVFPf64Imm(N->getValueAPF()) != -1;
+ }]> {
+ let PrintMethod = "printVFPf64ImmOperand";
+}
+
+
+//===----------------------------------------------------------------------===//
// Load / store Instructions.
//
@@ -408,3 +428,27 @@
let Inst{7} = 0;
let Inst{4} = 1;
}
+
+
+// Materialize FP immediates. VFP3 only.
+def FCONSTS : VFPAI<(outs SPR:$dst), (ins vfp_f32imm:$imm),
+ VFPMiscFrm, IIC_VMOVImm,
+ "fconsts", "\t$dst, $imm",
+ [(set SPR:$dst, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
+ let Inst{27-23} = 0b11101;
+ let Inst{21-20} = 0b11;
+ let Inst{11-9} = 0b101;
+ let Inst{8} = 0;
+ let Inst{7-4} = 0b0000;
+}
+
+def FCONSTD : VFPAI<(outs DPR:$dst), (ins vfp_f64imm:$imm),
+ VFPMiscFrm, IIC_VMOVImm,
+ "fconstd", "\t$dst, $imm",
+ [(set DPR:$dst, vfp_f64imm:$imm)]>, Requires<[HasVFP3]> {
+ let Inst{27-23} = 0b11101;
+ let Inst{21-20} = 0b11;
+ let Inst{11-9} = 0b101;
+ let Inst{8} = 1;
+ let Inst{7-4} = 0b0000;
+}
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=85374&r1=85373&r2=85374&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Wed Oct 28 00:14:25 2009
@@ -136,6 +136,8 @@
void printJT2BlockOperand(const MachineInstr *MI, int OpNum);
void printTBAddrMode(const MachineInstr *MI, int OpNum);
void printNoHashImmediate(const MachineInstr *MI, int OpNum);
+ void printVFPf32ImmOperand(const MachineInstr *MI, int OpNum);
+ void printVFPf64ImmOperand(const MachineInstr *MI, int OpNum);
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
unsigned AsmVariant, const char *ExtraCode);
@@ -391,9 +393,11 @@
if (Rot) {
O << "#" << Imm << ", " << Rot;
// Pretty printed version.
- if (VerboseAsm)
- O << ' ' << MAI->getCommentString()
- << ' ' << (int)ARM_AM::rotr32(Imm, Rot);
+ if (VerboseAsm) {
+ O.PadToColumn(MAI->getCommentColumn());
+ O << MAI->getCommentString() << ' ';
+ O << (int)ARM_AM::rotr32(Imm, Rot);
+ }
} else {
O << "#" << Imm;
}
@@ -968,6 +972,26 @@
O << MI->getOperand(OpNum).getImm();
}
+void ARMAsmPrinter::printVFPf32ImmOperand(const MachineInstr *MI, int OpNum) {
+ const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
+ O << ARM::getVFPf32Imm(FP->getValueAPF());
+ if (VerboseAsm) {
+ O.PadToColumn(MAI->getCommentColumn());
+ O << MAI->getCommentString() << ' ';
+ WriteAsOperand(O, FP, /*PrintType=*/false);
+ }
+}
+
+void ARMAsmPrinter::printVFPf64ImmOperand(const MachineInstr *MI, int OpNum) {
+ const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
+ O << ARM::getVFPf64Imm(FP->getValueAPF());
+ if (VerboseAsm) {
+ O.PadToColumn(MAI->getCommentColumn());
+ O << MAI->getCommentString() << ' ';
+ WriteAsOperand(O, FP, /*PrintType=*/false);
+ }
+}
+
bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
unsigned AsmVariant, const char *ExtraCode){
// Does this asm operand have a single letter operand modifier?
@@ -1183,7 +1207,8 @@
EmitAlignment(Align, GVar);
O << name << ":";
if (VerboseAsm) {
- O << "\t\t\t\t" << MAI->getCommentString() << ' ';
+ O.PadToColumn(MAI->getCommentColumn());
+ O << MAI->getCommentString() << ' ';
WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
}
O << '\n';
@@ -1206,7 +1231,8 @@
O << "," << (MAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
}
if (VerboseAsm) {
- O << "\t\t" << MAI->getCommentString() << " ";
+ O.PadToColumn(MAI->getCommentColumn());
+ O << MAI->getCommentString() << ' ';
WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
}
O << "\n";
@@ -1244,7 +1270,8 @@
EmitAlignment(Align, GVar);
O << name << ":";
if (VerboseAsm) {
- O << "\t\t\t\t" << MAI->getCommentString() << " ";
+ O.PadToColumn(MAI->getCommentColumn());
+ O << MAI->getCommentString() << ' ';
WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
}
O << "\n";
Modified: llvm/branches/Apple/Leela/lib/Target/Alpha/AlphaISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/Alpha/AlphaISelLowering.cpp?rev=85374&r1=85373&r2=85374&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/Alpha/AlphaISelLowering.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/Alpha/AlphaISelLowering.cpp Wed Oct 28 00:14:25 2009
@@ -157,11 +157,6 @@
setStackPointerRegisterToSaveRestore(Alpha::R30);
- addLegalFPImmediate(APFloat(+0.0)); //F31
- addLegalFPImmediate(APFloat(+0.0f)); //F31
- addLegalFPImmediate(APFloat(-0.0)); //-F31
- addLegalFPImmediate(APFloat(-0.0f)); //-F31
-
setJumpBufSize(272);
setJumpBufAlignment(16);
@@ -919,3 +914,13 @@
// The Alpha target isn't yet aware of offsets.
return false;
}
+
+bool AlphaTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
+ if (VT != MVT::f32 && VT != MVT::f64)
+ return false;
+ // +0.0 F31
+ // +0.0f F31
+ // -0.0 -F31
+ // -0.0f -F31
+ return Imm.isZero() || Imm.isNegZero();
+}
Modified: llvm/branches/Apple/Leela/lib/Target/Alpha/AlphaISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/Alpha/AlphaISelLowering.h?rev=85374&r1=85373&r2=85374&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/Alpha/AlphaISelLowering.h (original)
+++ llvm/branches/Apple/Leela/lib/Target/Alpha/AlphaISelLowering.h Wed Oct 28 00:14:25 2009
@@ -102,6 +102,11 @@
/// getFunctionAlignment - Return the Log2 alignment of this function.
virtual unsigned getFunctionAlignment(const Function *F) const;
+ /// isFPImmLegal - Returns true if the target can instruction select the
+ /// specified FP immediate natively. If false, the legalizer will
+ /// materialize the FP immediate as a load from a constant pool.
+ virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
+
private:
// Helpers for custom lowering.
void LowerVAARG(SDNode *N, SDValue &Chain, SDValue &DataPtr,
Modified: llvm/branches/Apple/Leela/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/Mips/MipsISelLowering.cpp?rev=85374&r1=85373&r2=85374&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/Mips/MipsISelLowering.cpp Wed Oct 28 00:14:25 2009
@@ -72,9 +72,6 @@
if (!Subtarget->isFP64bit())
addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
- // Legal fp constants
- addLegalFPImmediate(APFloat(+0.0f));
-
// Load extented operations for i1 types must be promoted
setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
@@ -1224,3 +1221,9 @@
// The Mips target isn't yet aware of offsets.
return false;
}
+
+bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
+ if (VT != MVT::f32 && VT != MVT::f64)
+ return false;
+ return Imm.isZero();
+}
Modified: llvm/branches/Apple/Leela/lib/Target/Mips/MipsISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/Mips/MipsISelLowering.h?rev=85374&r1=85373&r2=85374&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/Mips/MipsISelLowering.h (original)
+++ llvm/branches/Apple/Leela/lib/Target/Mips/MipsISelLowering.h Wed Oct 28 00:14:25 2009
@@ -146,6 +146,11 @@
EVT VT) const;
virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
+
+ /// isFPImmLegal - Returns true if the target can instruction select the
+ /// specified FP immediate natively. If false, the legalizer will
+ /// materialize the FP immediate as a load from a constant pool.
+ virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
};
}
Modified: llvm/branches/Apple/Leela/lib/Target/SystemZ/SystemZISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/SystemZ/SystemZISelLowering.cpp?rev=85374&r1=85373&r2=85374&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/SystemZ/SystemZISelLowering.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/SystemZ/SystemZISelLowering.cpp Wed Oct 28 00:14:25 2009
@@ -53,11 +53,6 @@
if (!UseSoftFloat) {
addRegisterClass(MVT::f32, SystemZ::FP32RegisterClass);
addRegisterClass(MVT::f64, SystemZ::FP64RegisterClass);
-
- addLegalFPImmediate(APFloat(+0.0)); // lzer
- addLegalFPImmediate(APFloat(+0.0f)); // lzdr
- addLegalFPImmediate(APFloat(-0.0)); // lzer + lner
- addLegalFPImmediate(APFloat(-0.0f)); // lzdr + lndr
}
// Compute derived properties from the register classes
@@ -169,6 +164,17 @@
}
}
+bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
+ if (UseSoftFloat || (VT != MVT::f32 && VT != MVT::f64))
+ return false;
+
+ // +0.0 lzer
+ // +0.0f lzdr
+ // -0.0 lzer + lner
+ // -0.0f lzdr + lndr
+ return Imm.isZero() || Imm.isNegZero();
+}
+
//===----------------------------------------------------------------------===//
// SystemZ Inline Assembly Support
//===----------------------------------------------------------------------===//
Modified: llvm/branches/Apple/Leela/lib/Target/SystemZ/SystemZISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/SystemZ/SystemZISelLowering.h?rev=85374&r1=85373&r2=85374&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/SystemZ/SystemZISelLowering.h (original)
+++ llvm/branches/Apple/Leela/lib/Target/SystemZ/SystemZISelLowering.h Wed Oct 28 00:14:25 2009
@@ -89,6 +89,11 @@
MachineBasicBlock *BB,
DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
+ /// isFPImmLegal - Returns true if the target can instruction select the
+ /// specified FP immediate natively. If false, the legalizer will
+ /// materialize the FP immediate as a load from a constant pool.
+ virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
+
private:
SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg,
Modified: llvm/branches/Apple/Leela/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/X86/X86ISelLowering.cpp?rev=85374&r1=85373&r2=85374&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/X86/X86ISelLowering.cpp Wed Oct 28 00:14:25 2009
@@ -2310,6 +2310,17 @@
}
}
+/// isFPImmLegal - Returns true if the target can instruction select the
+/// specified FP immediate natively. If false, the legalizer will
+/// materialize the FP immediate as a load from a constant pool.
+bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
+ for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
+ if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
+ return true;
+ }
+ return false;
+}
+
/// isUndefOrInRange - Return true if Val is undef or if its value falls within
/// the specified range (L, H].
static bool isUndefOrInRange(int Val, int Low, int Hi) {
Modified: llvm/branches/Apple/Leela/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/X86/X86ISelLowering.h?rev=85374&r1=85373&r2=85374&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/branches/Apple/Leela/lib/Target/X86/X86ISelLowering.h Wed Oct 28 00:14:25 2009
@@ -493,6 +493,11 @@
/// from i32 to i8 but not from i32 to i16.
virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const;
+ /// isFPImmLegal - Returns true if the target can instruction select the
+ /// specified FP immediate natively. If false, the legalizer will
+ /// materialize the FP immediate as a load from a constant pool.
+ virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
+
/// isShuffleMaskLegal - Targets can use this to indicate that they only
/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
/// By default, if a target supports the VECTOR_SHUFFLE node, all mask
@@ -578,6 +583,15 @@
bool X86ScalarSSEf32;
bool X86ScalarSSEf64;
+ /// LegalFPImmediates - A list of legal fp immediates.
+ std::vector<APFloat> LegalFPImmediates;
+
+ /// addLegalFPImmediate - Indicate that this x86 target can instruction
+ /// select the specified FP immediate natively.
+ void addLegalFPImmediate(const APFloat& Imm) {
+ LegalFPImmediates.push_back(Imm);
+ }
+
SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
Added: llvm/branches/Apple/Leela/test/CodeGen/ARM/fpconsts.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/ARM/fpconsts.ll?rev=85374&view=auto
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/ARM/fpconsts.ll (added)
+++ llvm/branches/Apple/Leela/test/CodeGen/ARM/fpconsts.ll Wed Oct 28 00:14:25 2009
@@ -0,0 +1,33 @@
+; RUN: llc < %s -march=arm -mattr=+vfp3 | FileCheck %s
+
+define arm_apcscc float @t1(float %x) nounwind readnone optsize {
+entry:
+; CHECK: t1:
+; CHECK: fconsts s1, 16
+ %0 = fadd float %x, 4.000000e+00
+ ret float %0
+}
+
+define arm_apcscc double @t2(double %x) nounwind readnone optsize {
+entry:
+; CHECK: t2:
+; CHECK: fconstd d1, 8
+ %0 = fadd double %x, 3.000000e+00
+ ret double %0
+}
+
+define arm_apcscc double @t3(double %x) nounwind readnone optsize {
+entry:
+; CHECK: t3:
+; CHECK: fconstd d1, 170
+ %0 = fmul double %x, -1.300000e+01
+ ret double %0
+}
+
+define arm_apcscc float @t4(float %x) nounwind readnone optsize {
+entry:
+; CHECK: t4:
+; CHECK: fconsts s1, 184
+ %0 = fmul float %x, -2.400000e+01
+ ret float %0
+}
More information about the llvm-branch-commits
mailing list