[llvm-branch-commits] [llvm-branch] r85288 - in /llvm/branches/Apple/Leela/lib/Target/ARM: ARMISelDAGToDAG.cpp ARMInstrFormats.td ARMInstrInfo.td
Bill Wendling
isanbard at gmail.com
Tue Oct 27 13:10:59 PDT 2009
Author: void
Date: Tue Oct 27 15:10:59 2009
New Revision: 85288
URL: http://llvm.org/viewvc/llvm-project?rev=85288&view=rev
Log:
$ svn merge -c 85167 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85167 into '.':
U lib/Target/ARM/ARMInstrInfo.td
$ svn merge -c 85169 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85169 into '.':
U lib/Target/ARM/ARMInstrFormats.td
$ svn merge -c 85173 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85173 into '.':
G lib/Target/ARM/ARMInstrInfo.td
$ svn merge -c 85255 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85255 into '.':
U lib/Target/ARM/ARMISelDAGToDAG.cpp
$ svn merge -c 85271 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85271 into '.':
G lib/Target/ARM/ARMInstrInfo.td
Modified:
llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelDAGToDAG.cpp
llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrFormats.td
llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.td
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=85288&r1=85287&r2=85288&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelDAGToDAG.cpp Tue Oct 27 15:10:59 2009
@@ -284,7 +284,7 @@
}
}
- // Otherwise this is R +/- [possibly shifted] R
+ // Otherwise this is R +/- [possibly shifted] R.
ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
unsigned ShAmt = 0;
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrFormats.td?rev=85288&r1=85287&r2=85288&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrFormats.td Tue Oct 27 15:10:59 2009
@@ -1125,8 +1125,8 @@
// Single precision unary, if no NEON
// Same as ASuI except not available if NEON is enabled
class ASuIn<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, dag oops, dag iops,
- InstrItinClass itin, string opc, string asm, list<dag> pattern>
- : ASuI<opcod1, opcod2, opcod2, oops, iops, itin, opc, asm, pattern> {
+ InstrItinClass itin, string opc, string asm, list<dag> pattern>
+ : ASuI<opcod1, opcod2, opcod3, oops, iops, itin, opc, asm, pattern> {
list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
}
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.td?rev=85288&r1=85287&r2=85288&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.td Tue Oct 27 15:10:59 2009
@@ -398,6 +398,7 @@
def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
IIC_iALUi, opc, "s\t$dst, $a, $b",
[(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
+ let Inst{20} = 1;
let Inst{25} = 1;
}
def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
@@ -405,6 +406,7 @@
[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
let isCommutable = Commutable;
let Inst{4} = 0;
+ let Inst{20} = 1;
let Inst{25} = 0;
}
def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
@@ -412,6 +414,7 @@
[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
let Inst{4} = 1;
let Inst{7} = 0;
+ let Inst{20} = 1;
let Inst{25} = 0;
}
}
@@ -456,14 +459,15 @@
IIC_iUNAr, opc, "\t$dst, $src",
[(set GPR:$dst, (opnode GPR:$src))]>,
Requires<[IsARM, HasV6]> {
- let Inst{19-16} = 0b1111;
- }
+ let Inst{11-10} = 0b00;
+ let Inst{19-16} = 0b1111;
+ }
def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src, i32imm:$rot),
IIC_iUNAsi, opc, "\t$dst, $src, ror $rot",
[(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>,
Requires<[IsARM, HasV6]> {
- let Inst{19-16} = 0b1111;
- }
+ let Inst{19-16} = 0b1111;
+ }
}
/// AI_bin_rrot - A binary operation with two forms: one whose operand is a
@@ -472,7 +476,9 @@
def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
IIC_iALUr, opc, "\t$dst, $LHS, $RHS",
[(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
- Requires<[IsARM, HasV6]>;
+ Requires<[IsARM, HasV6]> {
+ let Inst{11-10} = 0b00;
+ }
def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
IIC_iALUsi, opc, "\t$dst, $LHS, $RHS, ror $rot",
[(set GPR:$dst, (opnode GPR:$LHS,
@@ -512,6 +518,7 @@
[(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
Requires<[IsARM, CarryDefIsUsed]> {
let Defs = [CPSR];
+ let Inst{20} = 1;
let Inst{25} = 1;
}
def Srr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
@@ -520,6 +527,7 @@
Requires<[IsARM, CarryDefIsUsed]> {
let Defs = [CPSR];
let Inst{4} = 0;
+ let Inst{20} = 1;
let Inst{25} = 0;
}
def Srs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
@@ -529,6 +537,7 @@
let Defs = [CPSR];
let Inst{4} = 1;
let Inst{7} = 0;
+ let Inst{20} = 1;
let Inst{25} = 0;
}
}
@@ -1086,23 +1095,35 @@
def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
IIC_iALUi, "rsb", "\t$dst, $a, $b",
[(set GPR:$dst, (sub so_imm:$b, GPR:$a))]> {
+ let Inst{20} = 0;
let Inst{25} = 1;
}
def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
IIC_iALUsr, "rsb", "\t$dst, $a, $b",
- [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>;
+ [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]> {
+ let Inst{4} = 1;
+ let Inst{7} = 0;
+ let Inst{20} = 0;
+ let Inst{25} = 0;
+}
// RSB with 's' bit set.
let Defs = [CPSR] in {
def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
IIC_iALUi, "rsb", "s\t$dst, $a, $b",
[(set GPR:$dst, (subc so_imm:$b, GPR:$a))]> {
+ let Inst{20} = 1;
let Inst{25} = 1;
}
def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
IIC_iALUsr, "rsb", "s\t$dst, $a, $b",
- [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>;
+ [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]> {
+ let Inst{4} = 1;
+ let Inst{7} = 0;
+ let Inst{20} = 1;
+ let Inst{25} = 0;
+}
}
let Uses = [CPSR] in {
@@ -1110,12 +1131,18 @@
DPFrm, IIC_iALUi, "rsc", "\t$dst, $a, $b",
[(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
Requires<[IsARM, CarryDefIsUnused]> {
+ let Inst{20} = 0;
let Inst{25} = 1;
}
def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
DPSoRegFrm, IIC_iALUsr, "rsc", "\t$dst, $a, $b",
[(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
- Requires<[IsARM, CarryDefIsUnused]>;
+ Requires<[IsARM, CarryDefIsUnused]> {
+ let Inst{4} = 1;
+ let Inst{7} = 0;
+ let Inst{20} = 0;
+ let Inst{25} = 0;
+}
}
// FIXME: Allow these to be predicated.
@@ -1124,12 +1151,18 @@
DPFrm, IIC_iALUi, "rscs\t$dst, $a, $b",
[(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
Requires<[IsARM, CarryDefIsUnused]> {
+ let Inst{20} = 1;
let Inst{25} = 1;
}
def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
DPSoRegFrm, IIC_iALUsr, "rscs\t$dst, $a, $b",
[(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
- Requires<[IsARM, CarryDefIsUnused]>;
+ Requires<[IsARM, CarryDefIsUnused]> {
+ let Inst{4} = 1;
+ let Inst{7} = 0;
+ let Inst{20} = 1;
+ let Inst{25} = 0;
+}
}
// (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
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